OpenCores
URL https://opencores.org/ocsvn/udp_ip_stack/udp_ip_stack/trunk

Subversion Repositories udp_ip_stack

[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [UDP_Complete_nomac.vhd] - Blame information for rev 10

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 pjf
----------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer: 
4
-- 
5
-- Create Date:    09:38:49 06/13/2011 
6
-- Design Name: 
7
-- Module Name:    UDP_Complete_nomac - Behavioral 
8
-- Project Name: 
9
-- Target Devices: 
10
-- Tool versions: 
11
-- Description: 
12
--
13
-- Dependencies: 
14
--
15
-- Revision: 
16
-- Revision 0.01 - File Created
17
-- Revision 0.02 - separated RX and TX clocks
18 4 pjf
-- Revision 0.03 - Added mac_tx_tfirst
19 2 pjf
-- Additional Comments: 
20
--
21
----------------------------------------------------------------------------------
22
library IEEE;
23
use IEEE.STD_LOGIC_1164.ALL;
24
use IEEE.NUMERIC_STD.ALL;
25
use work.axi.all;
26
use work.ipv4_types.all;
27
use work.arp_types.all;
28
 
29
entity UDP_Complete_nomac is
30 8 pjf
         generic (
31
                        CLOCK_FREQ                      : integer := 125000000;                                                 -- freq of data_in_clk -- needed to timout cntr
32 10 pjf
                        ARP_TIMEOUT                     : integer := 60;                                                                        -- ARP response timeout (s)
33
                        ARP_MAX_PKT_TMO : integer := 5;                                                                 -- # wrong nwk pkts received before set error
34
                        MAX_ARP_ENTRIES         : integer := 255                                                                        -- max entries in the ARP store
35 8 pjf
                        );
36 2 pjf
    Port (
37
                        -- UDP TX signals
38
                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
39
                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
40
                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
41
                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
42
                        -- UDP RX signals
43
                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
44
                        udp_rxo                                 : out udp_rx_type;
45
                        -- IP RX signals
46
                        ip_rx_hdr                               : out ipv4_rx_header_type;
47
                        -- system signals
48
                        rx_clk                                  : in  STD_LOGIC;
49
                        tx_clk                                  : in  STD_LOGIC;
50
                        reset                                   : in  STD_LOGIC;
51
                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
52
                        our_mac_address                 : in std_logic_vector (47 downto 0);
53 8 pjf
                        control                                 : in udp_control_type;
54 2 pjf
                        -- status signals
55
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
56
                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
57
                        -- MAC Transmitter
58
                        mac_tx_tdata         : out  std_logic_vector(7 downto 0);        -- data byte to tx
59
                        mac_tx_tvalid        : out  std_logic;                                                  -- tdata is valid
60
                        mac_tx_tready        : in std_logic;                                                    -- mac is ready to accept data
61 4 pjf
                        mac_tx_tfirst        : out  std_logic;                                                  -- indicates first byte of frame
62 2 pjf
                        mac_tx_tlast         : out  std_logic;                                                  -- indicates last byte of frame
63
                        -- MAC Receiver
64
                        mac_rx_tdata         : in std_logic_vector(7 downto 0);  -- data byte received
65
                        mac_rx_tvalid        : in std_logic;                                                    -- indicates tdata is valid
66
                        mac_rx_tready        : out  std_logic;                                                  -- tells mac that we are ready to take data
67
                        mac_rx_tlast         : in std_logic                                                             -- indicates last byte of the trame
68
                        );
69
end UDP_Complete_nomac;
70
 
71
 
72 10 pjf
 
73
 
74
 
75 2 pjf
architecture structural of UDP_Complete_nomac is
76
 
77
  ------------------------------------------------------------------------------
78
  -- Component Declaration for UDP TX
79
  ------------------------------------------------------------------------------
80
 
81
    COMPONENT UDP_TX
82
    PORT(
83
                        -- UDP Layer signals
84
                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
85
                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
86
                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
87
                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
88
                        -- system signals
89
                        clk                                             : in  STD_LOGIC;                                                        -- same clock used to clock mac data and ip data
90
                        reset                                   : in  STD_LOGIC;
91
                        -- IP layer TX signals
92
                        ip_tx_start                             : out std_logic;
93
                        ip_tx                                           : out ipv4_tx_type;                                                     -- IP tx cxns
94
                        ip_tx_result                    : in std_logic_vector (1 downto 0);              -- tx status (changes during transmission)
95
                        ip_tx_data_out_ready    : in std_logic                                                                  -- indicates IP TX is ready to take data
96
                        );
97
    END COMPONENT;
98
 
99
  ------------------------------------------------------------------------------
100
  -- Component Declaration for UDP RX
101
  ------------------------------------------------------------------------------
102
 
103
    COMPONENT UDP_RX
104
    PORT(
105
                        -- UDP Layer signals
106
                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
107
                        udp_rxo                                 : out udp_rx_type;
108
                        -- system signals
109
                        clk                                             : in  STD_LOGIC;
110
                        reset                                   : in  STD_LOGIC;
111
                        -- IP layer RX signals
112
                        ip_rx_start                             : in std_logic;                                                 -- indicates receipt of ip header
113
                        ip_rx                                           : in ipv4_rx_type
114
                        );
115
    END COMPONENT;
116
 
117
  ------------------------------------------------------------------------------
118
  -- Component Declaration for the IP layer
119
  ------------------------------------------------------------------------------
120
 
121
component IP_complete_nomac
122 8 pjf
         generic (
123
                        CLOCK_FREQ                      : integer := 125000000;                                                 -- freq of data_in_clk -- needed to timout cntr
124 10 pjf
                        ARP_TIMEOUT                     : integer := 60;                                                                        -- ARP response timeout (s)
125
                        ARP_MAX_PKT_TMO : integer := 5;                                                                 -- # wrong nwk pkts received before set error
126
                        MAX_ARP_ENTRIES         : integer := 255                                                                        -- max entries in the ARP store
127 8 pjf
                        );
128 2 pjf
    Port (
129
                        -- IP Layer signals
130
                        ip_tx_start                             : in std_logic;
131
                        ip_tx                                           : in ipv4_tx_type;                                                              -- IP tx cxns
132
                        ip_tx_result                    : out std_logic_vector (1 downto 0);             -- tx status (changes during transmission)
133
                        ip_tx_data_out_ready    : out std_logic;                                                                        -- indicates IP TX is ready to take data
134
                        ip_rx_start                             : out std_logic;                                                                        -- indicates receipt of ip frame.
135
                        ip_rx                                           : out ipv4_rx_type;
136
                        -- system signals
137
                        rx_clk                                  : in  STD_LOGIC;
138
                        tx_clk                                  : in  STD_LOGIC;
139
                        reset                                   : in  STD_LOGIC;
140
                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
141
                        our_mac_address                 : in std_logic_vector (47 downto 0);
142 8 pjf
                        control                                 : in ip_control_type;
143 2 pjf
                        -- status signals
144 4 pjf
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
145
                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
146 2 pjf
                        -- MAC Transmitter
147
                        mac_tx_tdata         : out  std_logic_vector(7 downto 0);        -- data byte to tx
148 4 pjf
                        mac_tx_tvalid        : out  std_logic;                                                  -- tdata is valid
149
                        mac_tx_tready        : in std_logic;                                                    -- mac is ready to accept data
150
                        mac_tx_tfirst        : out  std_logic;                                                  -- indicates first byte of frame
151
                        mac_tx_tlast         : out  std_logic;                                                  -- indicates last byte of frame
152 2 pjf
                        -- MAC Receiver
153 4 pjf
                        mac_rx_tdata         : in std_logic_vector(7 downto 0);  -- data byte received
154
                        mac_rx_tvalid        : in std_logic;                                                    -- indicates tdata is valid
155
                        mac_rx_tready        : out  std_logic;                                                  -- tells mac that we are ready to take data
156
                        mac_rx_tlast         : in std_logic                                                             -- indicates last byte of the trame
157 2 pjf
                        );
158
end component;
159
 
160
        -- IP TX connectivity
161
   signal ip_tx_int                                             : ipv4_tx_type;
162
   signal ip_tx_start_int                               : std_logic;
163
        signal ip_tx_result_int                         : std_logic_vector (1 downto 0);
164
        signal ip_tx_data_out_ready_int : std_logic;
165
 
166
        -- IP RX connectivity
167
   signal ip_rx_int                     : ipv4_rx_type;
168
   signal ip_rx_start_int       : std_logic := '0';
169
 
170
 
171
begin
172
 
173
        -- output followers
174
        ip_rx_hdr <= ip_rx_int.hdr;
175
 
176
        -- Instantiate the UDP TX block
177 8 pjf
   udp_tx_block: UDP_TX
178
                        PORT MAP (
179 2 pjf
                                -- UDP Layer signals
180
                                udp_tx_start                    => udp_tx_start,
181
                                udp_txi                                         => udp_txi,
182
                                udp_tx_result                   => udp_tx_result,
183
                                udp_tx_data_out_ready=> udp_tx_data_out_ready,
184
                                -- system signals
185
                                clk                                             => tx_clk,
186
                                reset                                   => reset,
187
                                -- IP layer TX signals
188
                                ip_tx_start                     => ip_tx_start_int,
189
                                ip_tx                                   => ip_tx_int,
190
                                ip_tx_result                    => ip_tx_result_int,
191
                                ip_tx_data_out_ready    => ip_tx_data_out_ready_int
192
        );
193
 
194
        -- Instantiate the UDP RX block
195
   udp_rx_block: UDP_RX PORT MAP (
196
                                 -- UDP Layer signals
197
                                 udp_rxo                                => udp_rxo,
198
                                 udp_rx_start                   => udp_rx_start,
199
                                 -- system signals
200
                                 clk                                            => rx_clk,
201
                                 reset                                  => reset,
202
                                 -- IP layer RX signals
203
                                 ip_rx_start                    => ip_rx_start_int,
204
                                 ip_rx                                  => ip_rx_int
205
        );
206
 
207
   ------------------------------------------------------------------------------
208
   -- Instantiate the IP layer
209
   ------------------------------------------------------------------------------
210 8 pjf
    IP_block : IP_complete_nomac
211
                generic map (
212
                         CLOCK_FREQ                     => CLOCK_FREQ,
213 10 pjf
                         ARP_TIMEOUT            => ARP_TIMEOUT,
214
                         ARP_MAX_PKT_TMO        => ARP_MAX_PKT_TMO,
215
                         MAX_ARP_ENTRIES        => MAX_ARP_ENTRIES
216 8 pjf
                         )
217
                PORT MAP (
218 2 pjf
                                -- IP interface
219
                                ip_tx_start                     => ip_tx_start_int,
220
                                ip_tx                                   => ip_tx_int,
221
                                ip_tx_result                    => ip_tx_result_int,
222
                                ip_tx_data_out_ready    => ip_tx_data_out_ready_int,
223
                                ip_rx_start                     => ip_rx_start_int,
224
                                ip_rx                                   => ip_rx_int,
225
                                -- System interface
226
                                rx_clk                                  => rx_clk,
227
                                tx_clk                                  => tx_clk,
228
                                reset                                   => reset,
229
                                our_ip_address          => our_ip_address,
230
                                our_mac_address                 => our_mac_address,
231 8 pjf
                                control                                 => control.ip_controls,
232 2 pjf
                                -- status signals
233
                                arp_pkt_count                   => arp_pkt_count,
234
                                ip_pkt_count                    => ip_pkt_count,
235
                                -- MAC Transmitter
236
                                mac_tx_tdata                    => mac_tx_tdata,
237
                                mac_tx_tvalid                   => mac_tx_tvalid,
238
                                mac_tx_tready                   => mac_tx_tready,
239 4 pjf
                                mac_tx_tfirst                   => mac_tx_tfirst,
240 2 pjf
                                mac_tx_tlast                    => mac_tx_tlast,
241
                                -- MAC Receiver
242
                                mac_rx_tdata                    => mac_rx_tdata,
243
                                mac_rx_tvalid                   => mac_rx_tvalid,
244
                                mac_rx_tready                   => mac_rx_tready,
245
                                mac_rx_tlast                    => mac_rx_tlast
246
        );
247
 
248
 
249
end structural;
250
 
251 10 pjf
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.