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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [UDP_Complete_nomac.vhd] - Blame information for rev 8

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----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    09:38:49 06/13/2011 
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-- Design Name: 
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-- Module Name:    UDP_Complete_nomac - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Revision 0.02 - separated RX and TX clocks
18 4 pjf
-- Revision 0.03 - Added mac_tx_tfirst
19 2 pjf
-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.axi.all;
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use work.ipv4_types.all;
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use work.arp_types.all;
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entity UDP_Complete_nomac is
30 8 pjf
         generic (
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                        CLOCK_FREQ                      : integer := 125000000;                                                 -- freq of data_in_clk -- needed to timout cntr
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                        ARP_TIMEOUT                     : integer := 60                                                                 -- ARP response timeout (s)
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                        );
34 2 pjf
    Port (
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                        -- UDP TX signals
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                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
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                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
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                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
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                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
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                        -- UDP RX signals
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                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
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                        udp_rxo                                 : out udp_rx_type;
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                        -- IP RX signals
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                        ip_rx_hdr                               : out ipv4_rx_header_type;
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                        -- system signals
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                        rx_clk                                  : in  STD_LOGIC;
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                        tx_clk                                  : in  STD_LOGIC;
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                        reset                                   : in  STD_LOGIC;
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                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
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                        our_mac_address                 : in std_logic_vector (47 downto 0);
51 8 pjf
                        control                                 : in udp_control_type;
52 2 pjf
                        -- status signals
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                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
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                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
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                        -- MAC Transmitter
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                        mac_tx_tdata         : out  std_logic_vector(7 downto 0);        -- data byte to tx
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                        mac_tx_tvalid        : out  std_logic;                                                  -- tdata is valid
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                        mac_tx_tready        : in std_logic;                                                    -- mac is ready to accept data
59 4 pjf
                        mac_tx_tfirst        : out  std_logic;                                                  -- indicates first byte of frame
60 2 pjf
                        mac_tx_tlast         : out  std_logic;                                                  -- indicates last byte of frame
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                        -- MAC Receiver
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                        mac_rx_tdata         : in std_logic_vector(7 downto 0);  -- data byte received
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                        mac_rx_tvalid        : in std_logic;                                                    -- indicates tdata is valid
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                        mac_rx_tready        : out  std_logic;                                                  -- tells mac that we are ready to take data
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                        mac_rx_tlast         : in std_logic                                                             -- indicates last byte of the trame
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                        );
67
end UDP_Complete_nomac;
68
 
69
 
70
architecture structural of UDP_Complete_nomac is
71
 
72
  ------------------------------------------------------------------------------
73
  -- Component Declaration for UDP TX
74
  ------------------------------------------------------------------------------
75
 
76
    COMPONENT UDP_TX
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    PORT(
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                        -- UDP Layer signals
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                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
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                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
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                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
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                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
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                        -- system signals
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                        clk                                             : in  STD_LOGIC;                                                        -- same clock used to clock mac data and ip data
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                        reset                                   : in  STD_LOGIC;
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                        -- IP layer TX signals
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                        ip_tx_start                             : out std_logic;
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                        ip_tx                                           : out ipv4_tx_type;                                                     -- IP tx cxns
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                        ip_tx_result                    : in std_logic_vector (1 downto 0);              -- tx status (changes during transmission)
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                        ip_tx_data_out_ready    : in std_logic                                                                  -- indicates IP TX is ready to take data
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                        );
92
    END COMPONENT;
93
 
94
  ------------------------------------------------------------------------------
95
  -- Component Declaration for UDP RX
96
  ------------------------------------------------------------------------------
97
 
98
    COMPONENT UDP_RX
99
    PORT(
100
                        -- UDP Layer signals
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                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
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                        udp_rxo                                 : out udp_rx_type;
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                        -- system signals
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                        clk                                             : in  STD_LOGIC;
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                        reset                                   : in  STD_LOGIC;
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                        -- IP layer RX signals
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                        ip_rx_start                             : in std_logic;                                                 -- indicates receipt of ip header
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                        ip_rx                                           : in ipv4_rx_type
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                        );
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    END COMPONENT;
111
 
112
  ------------------------------------------------------------------------------
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  -- Component Declaration for the IP layer
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  ------------------------------------------------------------------------------
115
 
116
component IP_complete_nomac
117 8 pjf
         generic (
118
                        CLOCK_FREQ                      : integer := 125000000;                                                 -- freq of data_in_clk -- needed to timout cntr
119
                        ARP_TIMEOUT                     : integer := 60                                                                 -- ARP response timeout (s)
120
                        );
121 2 pjf
    Port (
122
                        -- IP Layer signals
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                        ip_tx_start                             : in std_logic;
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                        ip_tx                                           : in ipv4_tx_type;                                                              -- IP tx cxns
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                        ip_tx_result                    : out std_logic_vector (1 downto 0);             -- tx status (changes during transmission)
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                        ip_tx_data_out_ready    : out std_logic;                                                                        -- indicates IP TX is ready to take data
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                        ip_rx_start                             : out std_logic;                                                                        -- indicates receipt of ip frame.
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                        ip_rx                                           : out ipv4_rx_type;
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                        -- system signals
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                        rx_clk                                  : in  STD_LOGIC;
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                        tx_clk                                  : in  STD_LOGIC;
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                        reset                                   : in  STD_LOGIC;
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                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
134
                        our_mac_address                 : in std_logic_vector (47 downto 0);
135 8 pjf
                        control                                 : in ip_control_type;
136 2 pjf
                        -- status signals
137 4 pjf
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
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                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
139 2 pjf
                        -- MAC Transmitter
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                        mac_tx_tdata         : out  std_logic_vector(7 downto 0);        -- data byte to tx
141 4 pjf
                        mac_tx_tvalid        : out  std_logic;                                                  -- tdata is valid
142
                        mac_tx_tready        : in std_logic;                                                    -- mac is ready to accept data
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                        mac_tx_tfirst        : out  std_logic;                                                  -- indicates first byte of frame
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                        mac_tx_tlast         : out  std_logic;                                                  -- indicates last byte of frame
145 2 pjf
                        -- MAC Receiver
146 4 pjf
                        mac_rx_tdata         : in std_logic_vector(7 downto 0);  -- data byte received
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                        mac_rx_tvalid        : in std_logic;                                                    -- indicates tdata is valid
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                        mac_rx_tready        : out  std_logic;                                                  -- tells mac that we are ready to take data
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                        mac_rx_tlast         : in std_logic                                                             -- indicates last byte of the trame
150 2 pjf
                        );
151
end component;
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        -- IP TX connectivity
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   signal ip_tx_int                                             : ipv4_tx_type;
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   signal ip_tx_start_int                               : std_logic;
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        signal ip_tx_result_int                         : std_logic_vector (1 downto 0);
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        signal ip_tx_data_out_ready_int : std_logic;
158
 
159
        -- IP RX connectivity
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   signal ip_rx_int                     : ipv4_rx_type;
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   signal ip_rx_start_int       : std_logic := '0';
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163
 
164
begin
165
 
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        -- output followers
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        ip_rx_hdr <= ip_rx_int.hdr;
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        -- Instantiate the UDP TX block
170 8 pjf
   udp_tx_block: UDP_TX
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                        PORT MAP (
172 2 pjf
                                -- UDP Layer signals
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                                udp_tx_start                    => udp_tx_start,
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                                udp_txi                                         => udp_txi,
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                                udp_tx_result                   => udp_tx_result,
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                                udp_tx_data_out_ready=> udp_tx_data_out_ready,
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                                -- system signals
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                                clk                                             => tx_clk,
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                                reset                                   => reset,
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                                -- IP layer TX signals
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                                ip_tx_start                     => ip_tx_start_int,
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                                ip_tx                                   => ip_tx_int,
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                                ip_tx_result                    => ip_tx_result_int,
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                                ip_tx_data_out_ready    => ip_tx_data_out_ready_int
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        );
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        -- Instantiate the UDP RX block
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   udp_rx_block: UDP_RX PORT MAP (
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                                 -- UDP Layer signals
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                                 udp_rxo                                => udp_rxo,
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                                 udp_rx_start                   => udp_rx_start,
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                                 -- system signals
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                                 clk                                            => rx_clk,
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                                 reset                                  => reset,
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                                 -- IP layer RX signals
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                                 ip_rx_start                    => ip_rx_start_int,
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                                 ip_rx                                  => ip_rx_int
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        );
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   ------------------------------------------------------------------------------
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   -- Instantiate the IP layer
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   ------------------------------------------------------------------------------
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    IP_block : IP_complete_nomac
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                generic map (
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                         CLOCK_FREQ                     => CLOCK_FREQ,
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                         ARP_TIMEOUT            => ARP_TIMEOUT
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                         )
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                PORT MAP (
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                                -- IP interface
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                                ip_tx_start                     => ip_tx_start_int,
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                                ip_tx                                   => ip_tx_int,
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                                ip_tx_result                    => ip_tx_result_int,
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                                ip_tx_data_out_ready    => ip_tx_data_out_ready_int,
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                                ip_rx_start                     => ip_rx_start_int,
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                                ip_rx                                   => ip_rx_int,
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                                -- System interface
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                                rx_clk                                  => rx_clk,
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                                tx_clk                                  => tx_clk,
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                                reset                                   => reset,
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                                our_ip_address          => our_ip_address,
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                                our_mac_address                 => our_mac_address,
222 8 pjf
                                control                                 => control.ip_controls,
223 2 pjf
                                -- status signals
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                                arp_pkt_count                   => arp_pkt_count,
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                                ip_pkt_count                    => ip_pkt_count,
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                                -- MAC Transmitter
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                                mac_tx_tdata                    => mac_tx_tdata,
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                                mac_tx_tvalid                   => mac_tx_tvalid,
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                                mac_tx_tready                   => mac_tx_tready,
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                                mac_tx_tfirst                   => mac_tx_tfirst,
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                                mac_tx_tlast                    => mac_tx_tlast,
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                                -- MAC Receiver
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                                mac_rx_tdata                    => mac_rx_tdata,
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                                mac_rx_tvalid                   => mac_rx_tvalid,
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                                mac_rx_tready                   => mac_rx_tready,
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                                mac_rx_tlast                    => mac_rx_tlast
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        );
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end structural;
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