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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [arp_SYNC.vhd] - Blame information for rev 18

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1 18 pjf
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    14:09:01 02/20/2012 
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-- Design Name: 
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-- Module Name:    arp_SYNC - Behavioral - synchronises between rx and tx clock domains
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
20 10 pjf
library IEEE;
21 18 pjf
use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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use work.arp_types.all;
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entity arp_SYNC is
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  port (
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    -- REQ to TX
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    arp_nwk_req           : in  arp_nwk_request_t;  -- request for a translation from IP to MAC
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    send_who_has          : out std_logic;
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    ip_entry              : out std_logic_vector (31 downto 0);
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    -- RX to TX
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    recv_who_has          : in  std_logic;          -- this is for us, we will respond
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    arp_entry_for_who_has : in  arp_entry_t;
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    send_I_have           : out std_logic;
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    arp_entry             : out arp_entry_t;
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    -- RX to REQ
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    I_have_received       : in  std_logic;
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    nwk_result_status     : out arp_nwk_rslt_t;
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    -- System Signals
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    rx_clk                : in  std_logic;
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    tx_clk                : in  std_logic;
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    reset                 : in  std_logic
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    );
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end arp_SYNC;
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architecture Behavioral of arp_SYNC is
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  type sync_state_t is (IDLE, HOLD1, HOLD2);
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  -- state registers
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  signal ip_entry_state  : sync_state_t;
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  signal arp_entry_state : sync_state_t;
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  signal ip_entry_reg    : std_logic_vector (31 downto 0);
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  signal arp_entry_reg   : arp_entry_t;
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  -- synchronisation registers  
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  signal send_who_has_r1 : std_logic;
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  signal send_who_has_r2 : std_logic;
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  signal send_I_have_r1  : std_logic;
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  signal send_I_have_r2  : std_logic;
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begin
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  combinatorial : process (
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    -- input signals
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    arp_nwk_req, recv_who_has, arp_entry_for_who_has, I_have_received, reset,
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    -- state
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    ip_entry_state, ip_entry_reg, arp_entry_state, arp_entry_reg,
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    -- synchronisation registers
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    send_who_has_r1, send_who_has_r2,
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    send_I_have_r1, send_I_have_r2
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    )
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  begin
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    -- set output followers
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    send_who_has <= send_who_has_r2;
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    ip_entry     <= ip_entry_reg;
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    send_I_have  <= send_I_have_r2;
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    arp_entry    <= arp_entry_reg;
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    -- combinaltorial outputs
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    if I_have_received = '1' then
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      nwk_result_status <= RECEIVED;
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    else
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      nwk_result_status <= IDLE;
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    end if;
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  end process;
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  -- process for stablisising RX clock domain data registers
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  -- essentially holds data registers ip_entry and arp_entry static for 2 rx clk cycles
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  -- during transfer to TX clk domain
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  rx_sequential : process (tx_clk)
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  begin
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    if rising_edge(tx_clk) then
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      if reset = '1' then
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        -- reset state variables
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        ip_entry_reg      <= (others => '0');
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        arp_entry_reg.ip  <= (others => '0');
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        arp_entry_reg.mac <= (others => '0');
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      else
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        -- normal (non reset) processing
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        case ip_entry_state is
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          when IDLE =>
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            if arp_nwk_req.req = '1' then
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              ip_entry_reg   <= arp_nwk_req.ip;
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              ip_entry_state <= HOLD1;
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            else
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              ip_entry_reg   <= ip_entry_reg;
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              ip_entry_state <= IDLE;
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            end if;
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          when HOLD1 =>
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            ip_entry_reg   <= ip_entry_reg;
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            ip_entry_state <= HOLD2;
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          when HOLD2 =>
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            ip_entry_reg   <= ip_entry_reg;
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            ip_entry_state <= IDLE;
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        end case;
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        case arp_entry_state is
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          when IDLE =>
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            if recv_who_has = '1' then
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              arp_entry_reg   <= arp_entry_for_who_has;
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              arp_entry_state <= HOLD1;
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            else
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              arp_entry_reg   <= arp_entry_reg;
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              arp_entry_state <= IDLE;
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            end if;
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          when HOLD1 =>
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            arp_entry_reg   <= arp_entry_reg;
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            arp_entry_state <= HOLD2;
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          when HOLD2 =>
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            arp_entry_reg   <= arp_entry_reg;
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            arp_entry_state <= IDLE;
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        end case;
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      end if;
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    end if;
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  end process;
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  -- process for syncing to the TX clock domain
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  -- clocks control signals through 2 layers of tx clocking
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  tx_sequential : process (tx_clk)
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  begin
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    if rising_edge(tx_clk) then
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      if reset = '1' then
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        -- reset state variables
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        send_who_has_r1 <= '0';
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        send_who_has_r2 <= '0';
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        send_I_have_r1  <= '0';
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        send_I_have_r2  <= '0';
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      else
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        -- normal (non reset) processing
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        send_who_has_r1 <= arp_nwk_req.req;
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        send_who_has_r2 <= send_who_has_r1;
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        send_I_have_r1 <= recv_who_has;
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        send_I_have_r2 <= send_I_have_r1;
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      end if;
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    end if;
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  end process;
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end Behavioral;
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