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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [ml605/] [IP_complete.vhd] - Blame information for rev 8

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----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer:            Peter Fall
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-- 
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-- Create Date:    20:25:56 06/03/2011 
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-- Design Name: 
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-- Module Name:    IP_complete - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: Implements complete IP stack with ARP and MAC
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.axi.all;
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use work.ipv4_types.all;
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use work.arp_types.all;
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27
entity IP_complete is
28 8 pjf
         generic (
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                        CLOCK_FREQ                      : integer := 125000000;                                                 -- freq of data_in_clk -- needed to timout cntr
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                        ARP_TIMEOUT                     : integer := 60                                                                 -- ARP response timeout (s)
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                        );
32 2 pjf
    Port (
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                        -- IP Layer signals
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                        ip_tx_start                             : in std_logic;
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                        ip_tx                                           : in ipv4_tx_type;                                                              -- IP tx cxns
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                        ip_tx_result                    : out std_logic_vector (1 downto 0);             -- tx status (changes during transmission)
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                        ip_tx_data_out_ready    : out std_logic;                                                                        -- indicates IP TX is ready to take data
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                        ip_rx_start                             : out std_logic;                                                                        -- indicates receipt of ip frame.
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                        ip_rx                                           : out ipv4_rx_type;
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                        -- system signals
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                        clk_in_p             : in  std_logic;                                           -- 200MHz clock input from board
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                        clk_in_n             : in  std_logic;
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                        clk_out                                 : out std_logic;
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                        reset                                   : in  STD_LOGIC;
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                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
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                        our_mac_address                 : in std_logic_vector (47 downto 0);
47 8 pjf
                        control                                 : in ip_control_type;
48 2 pjf
                        -- status signals
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                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
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                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
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                        -- GMII Interface
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                        phy_resetn           : out std_logic;
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                        gmii_txd             : out std_logic_vector(7 downto 0);
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                        gmii_tx_en           : out std_logic;
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                        gmii_tx_er           : out std_logic;
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                        gmii_tx_clk          : out std_logic;
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                        gmii_rxd             : in  std_logic_vector(7 downto 0);
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                        gmii_rx_dv           : in  std_logic;
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                        gmii_rx_er           : in  std_logic;
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                        gmii_rx_clk          : in  std_logic;
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                        gmii_col             : in  std_logic;
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                        gmii_crs             : in  std_logic;
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                        mii_tx_clk           : in  std_logic
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                        );
65
end IP_complete;
66
 
67
architecture structural of IP_complete is
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69
  ------------------------------------------------------------------------------
70
  -- Component Declaration for the IP layer
71
  ------------------------------------------------------------------------------
72
 
73
    COMPONENT IP_complete_nomac
74 8 pjf
         generic (
75
                        CLOCK_FREQ                      : integer := 125000000;                                                 -- freq of data_in_clk -- needed to timout cntr
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                        ARP_TIMEOUT                     : integer := 60                                                                 -- ARP response timeout (s)
77
                        );
78
    Port (
79 2 pjf
                        -- IP Layer signals
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                        ip_tx_start                             : in std_logic;
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                        ip_tx                                           : in ipv4_tx_type;                                                              -- IP tx cxns
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                        ip_tx_result                    : out std_logic_vector (1 downto 0);             -- tx status (changes during transmission)
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                        ip_tx_data_out_ready    : out std_logic;                                                                        -- indicates IP TX is ready to take data
84
                        ip_rx_start                             : out std_logic;                                                                        -- indicates receipt of ip frame.
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                        ip_rx                                           : out ipv4_rx_type;
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                        -- system signals
87 4 pjf
                        rx_clk                                  : in  STD_LOGIC;
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                        tx_clk                                  : in  STD_LOGIC;
89 2 pjf
                        reset                                   : in  STD_LOGIC;
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                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
91
                        our_mac_address                 : in std_logic_vector (47 downto 0);
92 8 pjf
                        control                                 : in ip_control_type;
93 2 pjf
                        -- status signals
94
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
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                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
96
                        -- MAC Transmitter
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                        mac_tx_tdata         : out  std_logic_vector(7 downto 0);        -- data byte to tx
98
                        mac_tx_tvalid        : out  std_logic;                                                  -- tdata is valid
99
                        mac_tx_tready        : in std_logic;                                                    -- mac is ready to accept data
100 4 pjf
                        mac_tx_tfirst        : out  std_logic;                                                  -- indicates first byte of frame
101 2 pjf
                        mac_tx_tlast         : out  std_logic;                                                  -- indicates last byte of frame
102
                        -- MAC Receiver
103
                        mac_rx_tdata         : in std_logic_vector(7 downto 0);  -- data byte received
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                        mac_rx_tvalid        : in std_logic;                                                    -- indicates tdata is valid
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                        mac_rx_tready        : out  std_logic;                                                  -- tells mac that we are ready to take data
106 4 pjf
                        mac_rx_tlast         : in std_logic                                                             -- indicates last byte of the trame
107 8 pjf
                        );
108 2 pjf
    END COMPONENT;
109
 
110
 
111
  ------------------------------------------------------------------------------
112
  -- Component Declaration for the MAC layer
113
  ------------------------------------------------------------------------------
114
component mac_layer
115
         port (
116
                        -- System controls
117
                        ------------------
118
                        glbl_rst                      : in  std_logic;                                  -- asynchronous reset
119
                        mac_reset                       : in  std_logic;                                                        -- reset mac layer
120
                        clk_in_p                                : in  std_logic;                                        -- 200MHz clock input from board
121
                        clk_in_n                                : in  std_logic;
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123
                        -- MAC Transmitter (AXI-S) Interface
124
                        ---------------------------------------------
125
                        mac_tx_clock                            : out  std_logic;                                                       -- data sampled on rising edge
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                        mac_tx_tdata                            : in  std_logic_vector(7 downto 0);      -- data byte to tx
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                        mac_tx_tvalid                           : in  std_logic;                                                        -- tdata is valid
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                        mac_tx_tready                           : out std_logic;                                                        -- mac is ready to accept data
129
                        mac_tx_tlast                            : in  std_logic;                                                        -- indicates last byte of frame
130
 
131
                        -- MAC Receiver (AXI-S) Interface
132
                        ------------------------------------------
133
                        mac_rx_clock                            : out  std_logic;                                                       -- data valid on rising edge
134
                        mac_rx_tdata                            : out std_logic_vector(7 downto 0);      -- data byte received
135
                        mac_rx_tvalid                           : out std_logic;                                                        -- indicates tdata is valid
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                        mac_rx_tready                           : in  std_logic;                                                        -- tells mac that we are ready to take data
137
                        mac_rx_tlast                            : out std_logic;                                                        -- indicates last byte of the trame
138
 
139
                        -- GMII Interface
140
                        -----------------     
141
                        phy_resetn                              : out std_logic;
142
                        gmii_txd                      : out std_logic_vector(7 downto 0);
143
                        gmii_tx_en                    : out std_logic;
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                        gmii_tx_er                    : out std_logic;
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                        gmii_tx_clk                   : out std_logic;
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                        gmii_rxd                      : in  std_logic_vector(7 downto 0);
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                        gmii_rx_dv                    : in  std_logic;
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                        gmii_rx_er                    : in  std_logic;
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                        gmii_rx_clk                   : in  std_logic;
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                        gmii_col                      : in  std_logic;
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                        gmii_crs                      : in  std_logic;
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                        mii_tx_clk                    : in  std_logic
153
         );
154
end component;
155
 
156
        ---------------------------
157
        -- Signals
158
        ---------------------------
159
 
160
        -- MAC RX bus
161
        signal mac_rx_clock                     : std_logic;
162
        signal mac_rx_tdata                     : std_logic_vector (7 downto 0);
163
        signal mac_rx_tvalid                    : std_logic;
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        signal mac_rx_tready                    : std_logic;
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        signal mac_rx_tlast                     : std_logic;
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        -- MAC TX bus
167
        signal mac_tx_clock                     : std_logic;
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        signal mac_tx_tdata                     : std_logic_vector (7 downto 0);
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        signal mac_tx_tvalid                    : std_logic;
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        signal mac_tx_tready                    : std_logic;
171
        signal mac_tx_tlast                     : std_logic;
172
        -- control signals
173
        signal mac_tx_tready_int        : std_logic;
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        signal mac_tx_granted_int       : std_logic;
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176
begin
177
 
178
        clk_out <= mac_rx_clock;
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180
   ------------------------------------------------------------------------------
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   -- Instantiate the IP layer
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   ------------------------------------------------------------------------------
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184 8 pjf
    IP_layer : IP_complete_nomac
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                generic map (
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                         CLOCK_FREQ                     => CLOCK_FREQ,
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                         ARP_TIMEOUT            => ARP_TIMEOUT
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                         )
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                PORT MAP (
190 2 pjf
                         -- IP Layer signals
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          ip_tx_start                   => ip_tx_start,
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          ip_tx                                         => ip_tx,
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          ip_tx_result                  => ip_tx_result,
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          ip_tx_data_out_ready => ip_tx_data_out_ready,
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          ip_rx_start                   => ip_rx_start,
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          ip_rx                                         => ip_rx,
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                         -- system signals
198 4 pjf
          rx_clk                                        => mac_rx_clock,
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          tx_clk                                        => mac_rx_clock,
200 2 pjf
          reset                                         => reset,
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          our_ip_address                => our_ip_address,
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          our_mac_address               => our_mac_address,
203 8 pjf
                         control                                        => control,
204 2 pjf
                         -- status signals
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          arp_pkt_count                 => arp_pkt_count,
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                         ip_pkt_count                   => ip_pkt_count,
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                         -- MAC Transmitter
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          mac_tx_tready                 => mac_tx_tready_int,
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          mac_tx_tvalid                 => mac_tx_tvalid,
210 4 pjf
                         mac_tx_tfirst                  => open,
211 2 pjf
          mac_tx_tlast                  => mac_tx_tlast,
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          mac_tx_tdata                  => mac_tx_tdata,
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                    -- MAC Receiver
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          mac_rx_tdata                  => mac_rx_tdata,
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          mac_rx_tvalid                 => mac_rx_tvalid,
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                         mac_rx_tready                  => mac_rx_tready,
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          mac_rx_tlast                  => mac_rx_tlast
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        );
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   ------------------------------------------------------------------------------
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   -- Instantiate the MAC layer
223
   ------------------------------------------------------------------------------
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        mac_block : mac_layer
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                 Port map(
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                                -- System controls
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                                ------------------
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                                glbl_rst                                => reset,
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                                mac_reset         => '0',
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                                clk_in_p          => clk_in_p,
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                                clk_in_n          => clk_in_n,
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                                -- MAC Transmitter (AXI-S) Interface
234
                                ---------------------------------------------
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                                mac_tx_clock      => mac_tx_clock,
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                                mac_tx_tdata      => mac_tx_tdata,
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                                mac_tx_tvalid     => mac_tx_tvalid,
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                                mac_tx_tready     => mac_tx_tready_int,
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                                mac_tx_tlast      => mac_tx_tlast,
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241
                                -- MAC Receiver (AXI-S) Interface
242
                                ------------------------------------------
243
                                mac_rx_clock      => mac_rx_clock,
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                                mac_rx_tdata      => mac_rx_tdata,
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                                mac_rx_tvalid     => mac_rx_tvalid,
246
                                mac_rx_tready     => mac_rx_tready,
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                                mac_rx_tlast      => mac_rx_tlast,
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249
                                -- GMII Interface
250
                                -----------------     
251
                                phy_resetn        => phy_resetn,
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                                gmii_txd                => gmii_txd,
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                                gmii_tx_en        => gmii_tx_en,
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                                gmii_tx_er        => gmii_tx_er,
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                                gmii_tx_clk       => gmii_tx_clk,
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                                gmii_rxd                => gmii_rxd,
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                                gmii_rx_dv        => gmii_rx_dv,
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                                gmii_rx_er        => gmii_rx_er,
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                                gmii_rx_clk       => gmii_rx_clk,
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                                gmii_col        => gmii_col,
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                                gmii_crs                => gmii_crs,
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                                mii_tx_clk        => mii_tx_clk
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                          );
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end structural;
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