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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [ml605/] [UDP_Complete.vhd] - Blame information for rev 4

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1 2 pjf
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    17:51:18 06/11/2011 
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-- Design Name: 
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-- Module Name:    UDP_Complete - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Revision 0.02 - separated RX and TX clocks
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.axi.all;
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use work.ipv4_types.all;
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use work.arp_types.all;
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entity UDP_Complete is
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    Port (
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                        -- UDP TX signals
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                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
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                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
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                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
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                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
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                        -- UDP RX signals
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                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
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                        udp_rxo                                 : out udp_rx_type;
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                        -- IP RX signals
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                        ip_rx_hdr                               : out ipv4_rx_header_type;
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                        -- system signals
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                        clk_in_p             : in  std_logic;                                           -- 200MHz clock input from board
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                        clk_in_n             : in  std_logic;
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                        clk_out                                 : out std_logic;
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                        reset                                   : in  STD_LOGIC;
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                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
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                        our_mac_address                 : in std_logic_vector (47 downto 0);
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                        -- status signals
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                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
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                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
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                        -- GMII Interface
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                        phy_resetn           : out std_logic;
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                        gmii_txd             : out std_logic_vector(7 downto 0);
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                        gmii_tx_en           : out std_logic;
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                        gmii_tx_er           : out std_logic;
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                        gmii_tx_clk          : out std_logic;
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                        gmii_rxd             : in  std_logic_vector(7 downto 0);
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                        gmii_rx_dv           : in  std_logic;
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                        gmii_rx_er           : in  std_logic;
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                        gmii_rx_clk          : in  std_logic;
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                        gmii_col             : in  std_logic;
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                        gmii_crs             : in  std_logic;
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                        mii_tx_clk           : in  std_logic
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                        );
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end UDP_Complete;
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architecture structural of UDP_Complete is
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  ------------------------------------------------------------------------------
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  -- Component Declaration for UDP complete no mac
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  ------------------------------------------------------------------------------
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    COMPONENT UDP_Complete_nomac
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    PORT(
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                        -- UDP TX signals
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                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
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                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
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                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
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                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
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                        -- UDP RX signals
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                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
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                        udp_rxo                                 : out udp_rx_type;
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                        -- IP RX signals
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                        ip_rx_hdr                               : out ipv4_rx_header_type;
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                        -- system signals
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                        rx_clk                                  : in  STD_LOGIC;
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                        tx_clk                                  : in  STD_LOGIC;
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                        reset                                   : in  STD_LOGIC;
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                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
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                        our_mac_address                 : in std_logic_vector (47 downto 0);
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                        -- status signals
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                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
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                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
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                        -- MAC Transmitter
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                        mac_tx_tdata         : out  std_logic_vector(7 downto 0);        -- data byte to tx
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                        mac_tx_tvalid        : out  std_logic;                                                  -- tdata is valid
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                        mac_tx_tready        : in std_logic;                                                    -- mac is ready to accept data
97 4 pjf
                        mac_tx_tfirst        : out  std_logic;                                                  -- indicates first byte of frame
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                        mac_tx_tlast         : out  std_logic;                                                  -- indicates last byte of frame
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                        -- MAC Receiver
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                        mac_rx_tdata         : in std_logic_vector(7 downto 0);  -- data byte received
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                        mac_rx_tvalid        : in std_logic;                                                    -- indicates tdata is valid
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                        mac_rx_tready        : out  std_logic;                                                  -- tells mac that we are ready to take data
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                        mac_rx_tlast         : in std_logic                                                             -- indicates last byte of the trame
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                        );
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    END COMPONENT;
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107
 
108
  ------------------------------------------------------------------------------
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  -- Component Declaration for the MAC layer
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  ------------------------------------------------------------------------------
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component mac_layer
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         port (
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                        -- System controls
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                        ------------------
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                        glbl_rst                      : in  std_logic;                                  -- asynchronous reset
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                        mac_reset                       : in  std_logic;                                                        -- reset mac layer
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                        clk_in_p                                : in  std_logic;                                        -- 200MHz clock input from board
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                        clk_in_n                                : in  std_logic;
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120
                        -- MAC Transmitter (AXI-S) Interface
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                        ---------------------------------------------
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                        mac_tx_clock                            : out  std_logic;                                                       -- data sampled on rising edge
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                        mac_tx_tdata                            : in  std_logic_vector(7 downto 0);      -- data byte to tx
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                        mac_tx_tvalid                           : in  std_logic;                                                        -- tdata is valid
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                        mac_tx_tready                           : out std_logic;                                                        -- mac is ready to accept data
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                        mac_tx_tlast                            : in  std_logic;                                                        -- indicates last byte of frame
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128
                        -- MAC Receiver (AXI-S) Interface
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                        ------------------------------------------
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                        mac_rx_clock                            : out  std_logic;                                                       -- data valid on rising edge
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                        mac_rx_tdata                            : out std_logic_vector(7 downto 0);      -- data byte received
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                        mac_rx_tvalid                           : out std_logic;                                                        -- indicates tdata is valid
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                        mac_rx_tready                           : in  std_logic;                                                        -- tells mac that we are ready to take data
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                        mac_rx_tlast                            : out std_logic;                                                        -- indicates last byte of the trame
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136
                        -- GMII Interface
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                        -----------------     
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                        phy_resetn                              : out std_logic;
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                        gmii_txd                      : out std_logic_vector(7 downto 0);
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                        gmii_tx_en                    : out std_logic;
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                        gmii_tx_er                    : out std_logic;
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                        gmii_tx_clk                   : out std_logic;
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                        gmii_rxd                      : in  std_logic_vector(7 downto 0);
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                        gmii_rx_dv                    : in  std_logic;
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                        gmii_rx_er                    : in  std_logic;
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                        gmii_rx_clk                   : in  std_logic;
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                        gmii_col                      : in  std_logic;
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                        gmii_crs                      : in  std_logic;
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                        mii_tx_clk                    : in  std_logic
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         );
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end component;
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        ---------------------------
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        -- Signals
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        ---------------------------
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        -- MAC RX bus
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        signal mac_rx_clock                     : std_logic;
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        signal mac_rx_tdata                     : std_logic_vector (7 downto 0);
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        signal mac_rx_tvalid                    : std_logic;
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        signal mac_rx_tready                    : std_logic;
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        signal mac_rx_tlast                     : std_logic;
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        -- MAC TX bus
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        signal mac_tx_clock                     : std_logic;
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        signal mac_tx_tdata                     : std_logic_vector (7 downto 0);
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        signal mac_tx_tvalid                    : std_logic;
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        signal mac_tx_tready                    : std_logic;
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        signal mac_tx_tlast                     : std_logic;
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        -- control signals
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        signal mac_tx_tready_int        : std_logic;
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        signal mac_tx_granted_int       : std_logic;
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174
 
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begin
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        process (mac_tx_clock)
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        begin
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                -- output followers
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                clk_out <= mac_tx_clock;
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        end process;
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   ------------------------------------------------------------------------------
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   -- Instantiate the UDP layer
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   ------------------------------------------------------------------------------
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   udp_block: UDP_Complete_nomac PORT MAP (
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                         -- UDP TX signals
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          udp_tx_start                  => udp_tx_start,
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          udp_txi                               => udp_txi,
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          udp_tx_result                 => udp_tx_result,
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          udp_tx_data_out_ready => udp_tx_data_out_ready,
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                         -- UDP RX signals
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          udp_rx_start                  => udp_rx_start,
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          udp_rxo                               => udp_rxo,
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                         -- IP RX signals
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          ip_rx_hdr                             => ip_rx_hdr,
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                         -- system signals
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          rx_clk                                        => mac_rx_clock,
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          tx_clk                                        => mac_tx_clock,
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          reset                                         => reset,
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          our_ip_address                => our_ip_address,
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          our_mac_address               => our_mac_address,
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                         -- status signals
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          arp_pkt_count                 => arp_pkt_count,
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          ip_pkt_count                  => ip_pkt_count,
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                         -- MAC Transmitter
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          mac_tx_tready                 => mac_tx_tready_int,
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          mac_tx_tvalid                 => mac_tx_tvalid,
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                         mac_tx_tfirst                  => open,
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          mac_tx_tlast                  => mac_tx_tlast,
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          mac_tx_tdata                  => mac_tx_tdata,
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                    -- MAC Receiver
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          mac_rx_tdata                  => mac_rx_tdata,
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          mac_rx_tvalid                 => mac_rx_tvalid,
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                         mac_rx_tready                  => mac_rx_tready,
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          mac_rx_tlast                  => mac_rx_tlast
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        );
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   ------------------------------------------------------------------------------
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   -- Instantiate the MAC layer
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   ------------------------------------------------------------------------------
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        mac_block : mac_layer
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                 Port map(
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                                -- System controls
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                                ------------------
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                                glbl_rst                                => reset,
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                                mac_reset         => '0',
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                                clk_in_p          => clk_in_p,
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                                clk_in_n          => clk_in_n,
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                                -- MAC Transmitter (AXI-S) Interface
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                                ---------------------------------------------
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                                mac_tx_clock      => mac_tx_clock,
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                                mac_tx_tdata      => mac_tx_tdata,
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                                mac_tx_tvalid     => mac_tx_tvalid,
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                                mac_tx_tready     => mac_tx_tready_int,
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                                mac_tx_tlast      => mac_tx_tlast,
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                                -- MAC Receiver (AXI-S) Interface
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                                ------------------------------------------
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                                mac_rx_clock      => mac_rx_clock,
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                                mac_rx_tdata      => mac_rx_tdata,
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                                mac_rx_tvalid     => mac_rx_tvalid,
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                                mac_rx_tready     => mac_rx_tready,
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                                mac_rx_tlast      => mac_rx_tlast,
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                                -- GMII Interface
252
                                -----------------     
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                                phy_resetn        => phy_resetn,
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                                gmii_txd                => gmii_txd,
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                                gmii_tx_en        => gmii_tx_en,
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                                gmii_tx_er        => gmii_tx_er,
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                                gmii_tx_clk       => gmii_tx_clk,
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                                gmii_rxd                => gmii_rxd,
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                                gmii_rx_dv        => gmii_rx_dv,
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                                gmii_rx_er        => gmii_rx_er,
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                                gmii_rx_clk       => gmii_rx_clk,
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                                gmii_col        => gmii_col,
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                                gmii_crs                => gmii_crs,
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                                mii_tx_clk        => mii_tx_clk
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                          );
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end structural;
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