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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [ml605/] [udp_constraints.ucf] - Blame information for rev 8

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Line No. Rev Author Line
1 2 pjf
CONFIG PART = xc6vlx240tff1156-1;
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########## ML605 Board ##########
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NET  clk_in_p        LOC = J9   |IOSTANDARD = LVDS_25  |DIFF_TERM = TRUE;
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NET  clk_in_n        LOC = H9   |IOSTANDARD = LVDS_25  |DIFF_TERM = TRUE;
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Net reset         LOC = H10  |IOSTANDARD = LVCMOS15 |TIG;
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# downgrade the Place:1153 error in the mapper
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NET "reset" CLOCK_DEDICATED_ROUTE = FALSE;
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#### Module LEDs_8Bit constraints
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NET "display[0]" LOC = AC22;
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NET "display[1]" LOC = AC24;
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NET "display[2]" LOC = AE22;
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NET "display[3]" LOC = AE23;
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NET "display[4]" LOC = AB23;
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NET "display[5]" LOC = AG23;
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NET "display[6]" LOC = AE24;
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NET "display[7]" LOC = AD24;
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NET PBTX_LED            LOC = AD21;
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NET UDP_RX              LOC = AH27;
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NET UDP_START           LOC = AH28;
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NET TX_RSLT_0   LOC = AE21;
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NET TX_RSLT_1   LOC = AP24;
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#### Module Push_Buttons_4Bit constraints
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NET PBTX                        LOC = H17;
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NET reset_leds          LOC = G26;
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#### Module DIP_Switches_4Bit constraints
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Net phy_resetn       LOC = AH13 |IOSTANDARD = LVCMOS25 |TIG;
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Net gmii_rxd<7>      LOC = AC13 |IOSTANDARD = LVCMOS25;
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Net gmii_rxd<6>      LOC = AC12 |IOSTANDARD = LVCMOS25;
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Net gmii_rxd<5>      LOC = AD11 |IOSTANDARD = LVCMOS25;
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Net gmii_rxd<4>      LOC = AM12 |IOSTANDARD = LVCMOS25;
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Net gmii_rxd<3>      LOC = AN12 |IOSTANDARD = LVCMOS25;
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Net gmii_rxd<2>      LOC = AE14 |IOSTANDARD = LVCMOS25;
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Net gmii_rxd<1>      LOC = AF14 |IOSTANDARD = LVCMOS25;
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Net gmii_rxd<0>      LOC = AN13 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<7>      LOC = AF11 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<6>      LOC = AE11 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<5>      LOC = AM10 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<4>      LOC = AL10 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<3>      LOC = AG11 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<2>      LOC = AG10 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<1>      LOC = AL11 |IOSTANDARD = LVCMOS25;
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Net gmii_txd<0>      LOC = AM11 |IOSTANDARD = LVCMOS25;
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Net gmii_col         LOC = AK13 |IOSTANDARD = LVCMOS25;
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Net gmii_crs         LOC = AL13 |IOSTANDARD = LVCMOS25;
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Net mii_tx_clk       LOC = AD12 |IOSTANDARD = LVCMOS25;
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Net gmii_tx_en       LOC = AJ10 |IOSTANDARD = LVCMOS25;
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Net gmii_tx_er       LOC = AH10 |IOSTANDARD = LVCMOS25;
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Net gmii_tx_clk      LOC = AH12 |IOSTANDARD = LVCMOS25;
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Net gmii_rx_dv       LOC = AM13 |IOSTANDARD = LVCMOS25;
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Net gmii_rx_er       LOC = AG12 |IOSTANDARD = LVCMOS25;
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# P20 - GCLK7
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Net gmii_rx_clk      LOC = AP11 |IOSTANDARD = LVCMOS25;
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NET "clk_in_p" TNM_NET = "clk_in_p";
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TIMESPEC "TS_emac1_clk_in_p" = PERIOD "clk_in_p" 5.000 ns HIGH 50% INPUT_JITTER 50.0ps;
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# Ethernet GTX_CLK high quality 125 MHz reference clock
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NET "*mac_block/gtx_clk_bufg" TNM_NET = "ref_gtx_clk";
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TIMEGRP "emac1_clk_ref_gtx" = "ref_gtx_clk";
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TIMESPEC TS_emac1_clk_ref_gtx = PERIOD "N/A" 8 ns HIGH 50%;
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