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[/] [usb_device_core/] [trunk/] [src_v/] [usbf_device_core.v] - Blame information for rev 5

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1 5 ultra_embe
//-----------------------------------------------------------------
2
//                       USB Device Core
3
//                           V1.0
4
//                     Ultra-Embedded.com
5
//                     Copyright 2014-2019
6
//
7
//                 Email: admin@ultra-embedded.com
8
//
9
//                         License: GPL
10
// If you would like a version with a more permissive license for
11
// use in closed source commercial applications please contact me
12
// for details.
13
//-----------------------------------------------------------------
14
//
15
// This file is open source HDL; you can redistribute it and/or 
16
// modify it under the terms of the GNU General Public License as 
17
// published by the Free Software Foundation; either version 2 of 
18
// the License, or (at your option) any later version.
19
//
20
// This file is distributed in the hope that it will be useful,
21
// but WITHOUT ANY WARRANTY; without even the implied warranty of
22
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23
// GNU General Public License for more details.
24
//
25
// You should have received a copy of the GNU General Public 
26
// License along with this file; if not, write to the Free Software
27
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
28
// USA
29
//-----------------------------------------------------------------
30
 
31
//-----------------------------------------------------------------
32
//                          Generated File
33
//-----------------------------------------------------------------
34
 
35
module usbf_device_core
36
(
37
    // Inputs
38
     input           clk_i
39
    ,input           rst_i
40
    ,input  [  7:0]  utmi_data_i
41
    ,input           utmi_txready_i
42
    ,input           utmi_rxvalid_i
43
    ,input           utmi_rxactive_i
44
    ,input           utmi_rxerror_i
45
    ,input  [  1:0]  utmi_linestate_i
46
    ,input           ep0_stall_i
47
    ,input           ep0_iso_i
48
    ,input           ep0_cfg_int_rx_i
49
    ,input           ep0_cfg_int_tx_i
50
    ,input           ep0_rx_space_i
51
    ,input           ep0_tx_ready_i
52
    ,input           ep0_tx_data_valid_i
53
    ,input           ep0_tx_data_strb_i
54
    ,input  [  7:0]  ep0_tx_data_i
55
    ,input           ep0_tx_data_last_i
56
    ,input           ep1_stall_i
57
    ,input           ep1_iso_i
58
    ,input           ep1_cfg_int_rx_i
59
    ,input           ep1_cfg_int_tx_i
60
    ,input           ep1_rx_space_i
61
    ,input           ep1_tx_ready_i
62
    ,input           ep1_tx_data_valid_i
63
    ,input           ep1_tx_data_strb_i
64
    ,input  [  7:0]  ep1_tx_data_i
65
    ,input           ep1_tx_data_last_i
66
    ,input           ep2_stall_i
67
    ,input           ep2_iso_i
68
    ,input           ep2_cfg_int_rx_i
69
    ,input           ep2_cfg_int_tx_i
70
    ,input           ep2_rx_space_i
71
    ,input           ep2_tx_ready_i
72
    ,input           ep2_tx_data_valid_i
73
    ,input           ep2_tx_data_strb_i
74
    ,input  [  7:0]  ep2_tx_data_i
75
    ,input           ep2_tx_data_last_i
76
    ,input           ep3_stall_i
77
    ,input           ep3_iso_i
78
    ,input           ep3_cfg_int_rx_i
79
    ,input           ep3_cfg_int_tx_i
80
    ,input           ep3_rx_space_i
81
    ,input           ep3_tx_ready_i
82
    ,input           ep3_tx_data_valid_i
83
    ,input           ep3_tx_data_strb_i
84
    ,input  [  7:0]  ep3_tx_data_i
85
    ,input           ep3_tx_data_last_i
86
    ,input           reg_chirp_en_i
87
    ,input           reg_int_en_sof_i
88
    ,input           reg_sts_rst_clr_i
89
    ,input  [  6:0]  reg_dev_addr_i
90
 
91
    // Outputs
92
    ,output          intr_o
93
    ,output [  7:0]  utmi_data_o
94
    ,output          utmi_txvalid_o
95
    ,output          rx_strb_o
96
    ,output [  7:0]  rx_data_o
97
    ,output          rx_last_o
98
    ,output          rx_crc_err_o
99
    ,output          ep0_rx_setup_o
100
    ,output          ep0_rx_valid_o
101
    ,output          ep0_tx_data_accept_o
102
    ,output          ep1_rx_setup_o
103
    ,output          ep1_rx_valid_o
104
    ,output          ep1_tx_data_accept_o
105
    ,output          ep2_rx_setup_o
106
    ,output          ep2_rx_valid_o
107
    ,output          ep2_tx_data_accept_o
108
    ,output          ep3_rx_setup_o
109
    ,output          ep3_rx_valid_o
110
    ,output          ep3_tx_data_accept_o
111
    ,output          reg_sts_rst_o
112
    ,output [ 10:0]  reg_sts_frame_num_o
113
);
114
 
115
 
116
 
117
//-----------------------------------------------------------------
118
// Defines:
119
//-----------------------------------------------------------------
120
`include "usbf_defs.v"
121
 
122
`define USB_RESET_CNT_W     15
123
 
124
localparam STATE_W                       = 3;
125
localparam STATE_RX_IDLE                 = 3'd0;
126
localparam STATE_RX_DATA                 = 3'd1;
127
localparam STATE_RX_DATA_READY           = 3'd2;
128
localparam STATE_RX_DATA_IGNORE          = 3'd3;
129
localparam STATE_TX_DATA                 = 3'd4;
130
localparam STATE_TX_DATA_COMPLETE        = 3'd5;
131
localparam STATE_TX_HANDSHAKE            = 3'd6;
132
localparam STATE_TX_CHIRP                = 3'd7;
133
reg [STATE_W-1:0] state_q;
134
 
135
//-----------------------------------------------------------------
136
// Reset detection
137
//-----------------------------------------------------------------
138
reg [`USB_RESET_CNT_W-1:0] se0_cnt_q;
139
 
140
always @ (posedge clk_i or posedge rst_i)
141
if (rst_i)
142
    se0_cnt_q <= `USB_RESET_CNT_W'b0;
143
else if (utmi_linestate_i == 2'b0)
144
begin
145
    if (!se0_cnt_q[`USB_RESET_CNT_W-1])
146
        se0_cnt_q <= se0_cnt_q + `USB_RESET_CNT_W'd1;
147
end
148
else
149
    se0_cnt_q <= `USB_RESET_CNT_W'b0;
150
 
151
wire usb_rst_w = se0_cnt_q[`USB_RESET_CNT_W-1];
152
 
153
//-----------------------------------------------------------------
154
// Wire / Regs
155
//-----------------------------------------------------------------
156
`define USB_FRAME_W    11
157
wire [`USB_FRAME_W-1:0] frame_num_w;
158
 
159
wire                    frame_valid_w;
160
 
161
`define USB_DEV_W      7
162
wire [`USB_DEV_W-1:0]   token_dev_w;
163
 
164
`define USB_EP_W       4
165
wire [`USB_EP_W-1:0]    token_ep_w;
166
 
167
`define USB_PID_W      8
168
wire [`USB_PID_W-1:0]   token_pid_w;
169
 
170
wire                    token_valid_w;
171
 
172
wire                    rx_data_valid_w;
173
wire                    rx_data_complete_w;
174
 
175
wire                    rx_handshake_w;
176
 
177
reg                     tx_data_valid_r;
178
reg                     tx_data_strb_r;
179
reg  [7:0]              tx_data_r;
180
reg                     tx_data_last_r;
181
wire                    tx_data_accept_w;
182
 
183
reg                     tx_valid_q;
184
reg [7:0]               tx_pid_q;
185
wire                    tx_accept_w;
186
 
187
reg                     rx_space_q;
188
reg                     rx_space_r;
189
reg                     tx_ready_r;
190
reg                     ep_data_bit_r;
191
 
192
reg                     ep_stall_r;
193
reg                     ep_iso_r;
194
 
195
reg                     rx_enable_q;
196
reg                     rx_setup_q;
197
 
198
reg                     ep0_data_bit_q;
199
reg                     ep1_data_bit_q;
200
reg                     ep2_data_bit_q;
201
reg                     ep3_data_bit_q;
202
 
203
wire                    status_stage_w;
204
 
205
reg [`USB_DEV_W-1:0]    current_addr_q;
206
 
207
//-----------------------------------------------------------------
208
// SIE - TX
209
//-----------------------------------------------------------------
210
usbf_sie_tx
211
u_sie_tx
212
(
213
    .clk_i(clk_i),
214
    .rst_i(rst_i),
215
 
216
    .enable_i(~usb_rst_w),
217
    .chirp_i(reg_chirp_en_i),
218
 
219
    // UTMI Interface
220
    .utmi_data_o(utmi_data_o),
221
    .utmi_txvalid_o(utmi_txvalid_o),
222
    .utmi_txready_i(utmi_txready_i),
223
 
224
    // Request
225
    .tx_valid_i(tx_valid_q),
226
    .tx_pid_i(tx_pid_q),
227
    .tx_accept_o(tx_accept_w),
228
 
229
    // Data
230
    .data_valid_i(tx_data_valid_r),
231
    .data_strb_i(tx_data_strb_r),
232
    .data_i(tx_data_r),
233
    .data_last_i(tx_data_last_r),
234
    .data_accept_o(tx_data_accept_w)
235
);
236
 
237
always @ *
238
begin
239
    tx_data_valid_r = 1'b0;
240
    tx_data_strb_r  = 1'b0;
241
    tx_data_r       = 8'b0;
242
    tx_data_last_r  = 1'b0;
243
 
244
    case (token_ep_w)
245
    4'd0:
246
    begin
247
        tx_data_valid_r = ep0_tx_data_valid_i;
248
        tx_data_strb_r  = ep0_tx_data_strb_i;
249
        tx_data_r       = ep0_tx_data_i;
250
        tx_data_last_r  = ep0_tx_data_last_i;
251
    end
252
    4'd1:
253
    begin
254
        tx_data_valid_r = ep1_tx_data_valid_i;
255
        tx_data_strb_r  = ep1_tx_data_strb_i;
256
        tx_data_r       = ep1_tx_data_i;
257
        tx_data_last_r  = ep1_tx_data_last_i;
258
    end
259
    4'd2:
260
    begin
261
        tx_data_valid_r = ep2_tx_data_valid_i;
262
        tx_data_strb_r  = ep2_tx_data_strb_i;
263
        tx_data_r       = ep2_tx_data_i;
264
        tx_data_last_r  = ep2_tx_data_last_i;
265
    end
266
    4'd3:
267
    begin
268
        tx_data_valid_r = ep3_tx_data_valid_i;
269
        tx_data_strb_r  = ep3_tx_data_strb_i;
270
        tx_data_r       = ep3_tx_data_i;
271
        tx_data_last_r  = ep3_tx_data_last_i;
272
    end
273
    default:
274
        ;
275
    endcase
276
end
277
 
278
assign ep0_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd0);
279
assign ep1_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd1);
280
assign ep2_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd2);
281
assign ep3_tx_data_accept_o = tx_data_accept_w & (token_ep_w == 4'd3);
282
 
283
always @ *
284
begin
285
    rx_space_r    = 1'b0;
286
    tx_ready_r    = 1'b0;
287
    ep_data_bit_r = 1'b0;
288
 
289
    ep_stall_r = 1'b0;
290
    ep_iso_r   = 1'b0;
291
 
292
    case (token_ep_w)
293
    4'd0:
294
    begin
295
        rx_space_r    = ep0_rx_space_i;
296
        tx_ready_r    = ep0_tx_ready_i;
297
        ep_data_bit_r = ep0_data_bit_q | status_stage_w;
298
        ep_stall_r    = ep0_stall_i;
299
        ep_iso_r      = ep0_iso_i;
300
    end
301
    4'd1:
302
    begin
303
        rx_space_r    = ep1_rx_space_i;
304
        tx_ready_r    = ep1_tx_ready_i;
305
        ep_data_bit_r = ep1_data_bit_q | status_stage_w;
306
        ep_stall_r    = ep1_stall_i;
307
        ep_iso_r      = ep1_iso_i;
308
    end
309
    4'd2:
310
    begin
311
        rx_space_r    = ep2_rx_space_i;
312
        tx_ready_r    = ep2_tx_ready_i;
313
        ep_data_bit_r = ep2_data_bit_q | status_stage_w;
314
        ep_stall_r    = ep2_stall_i;
315
        ep_iso_r      = ep2_iso_i;
316
    end
317
    4'd3:
318
    begin
319
        rx_space_r    = ep3_rx_space_i;
320
        tx_ready_r    = ep3_tx_ready_i;
321
        ep_data_bit_r = ep3_data_bit_q | status_stage_w;
322
        ep_stall_r    = ep3_stall_i;
323
        ep_iso_r      = ep3_iso_i;
324
    end
325
    default:
326
        ;
327
    endcase
328
end
329
 
330
always @ (posedge clk_i or posedge rst_i)
331
if (rst_i)
332
    rx_space_q <= 1'b0;
333
else if (state_q == STATE_RX_IDLE)
334
    rx_space_q <= rx_space_r;
335
 
336
//-----------------------------------------------------------------
337
// SIE - RX
338
//-----------------------------------------------------------------
339
usbf_sie_rx
340
u_sie_rx
341
(
342
    .clk_i(clk_i),
343
    .rst_i(rst_i),
344
 
345
    .enable_i(~usb_rst_w && ~reg_chirp_en_i),
346
 
347
    // UTMI Interface
348
    .utmi_data_i(utmi_data_i),
349
    .utmi_rxvalid_i(utmi_rxvalid_i),
350
    .utmi_rxactive_i(utmi_rxactive_i),
351
 
352
    .current_addr_i(current_addr_q),
353
 
354
    .pid_o(token_pid_w),
355
 
356
    .frame_valid_o(frame_valid_w),
357
    .frame_number_o(reg_sts_frame_num_o),
358
 
359
    .token_valid_o(token_valid_w),
360
    .token_addr_o(token_dev_w),
361
    .token_ep_o(token_ep_w),
362
    .token_crc_err_o(),
363
 
364
    .handshake_valid_o(rx_handshake_w),
365
 
366
    .data_valid_o(rx_data_valid_w),
367
    .data_strb_o(rx_strb_o),
368
    .data_o(rx_data_o),
369
    .data_last_o(rx_last_o),
370
 
371
    .data_complete_o(rx_data_complete_w),
372
    .data_crc_err_o(rx_crc_err_o)
373
);
374
 
375
assign ep0_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd0);
376
assign ep0_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
377
assign ep1_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd1);
378
assign ep1_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
379
assign ep2_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd2);
380
assign ep2_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
381
assign ep3_rx_valid_o = rx_enable_q & rx_data_valid_w & (token_ep_w == 4'd3);
382
assign ep3_rx_setup_o = rx_setup_q & (token_ep_w == 4'd0);
383
 
384
//-----------------------------------------------------------------
385
// Next state
386
//-----------------------------------------------------------------
387
reg [STATE_W-1:0] next_state_r;
388
 
389
always @ *
390
begin
391
    next_state_r = state_q;
392
 
393
    //-----------------------------------------
394
    // State Machine
395
    //-----------------------------------------
396
    case (state_q)
397
 
398
    //-----------------------------------------
399
    // IDLE
400
    //-----------------------------------------
401
    STATE_RX_IDLE :
402
    begin
403
        // Token received (OUT, IN, SETUP, PING)
404
        if (token_valid_w)
405
        begin
406
            //-------------------------------
407
            // IN transfer (device -> host)
408
            //-------------------------------
409
            if (token_pid_w == `PID_IN)
410
            begin
411
                // Stalled endpoint?
412
                if (ep_stall_r)
413
                    next_state_r  = STATE_TX_HANDSHAKE;
414
                // Some data to TX?
415
                else if (tx_ready_r)
416
                    next_state_r  = STATE_TX_DATA;
417
                // No data to TX
418
                else
419
                    next_state_r  = STATE_TX_HANDSHAKE;
420
            end
421
            //-------------------------------
422
            // PING transfer (device -> host)
423
            //-------------------------------
424
            else if (token_pid_w == `PID_PING)
425
            begin
426
                next_state_r  = STATE_TX_HANDSHAKE;
427
            end
428
            //-------------------------------
429
            // OUT transfer (host -> device)
430
            //-------------------------------
431
            else if (token_pid_w == `PID_OUT)
432
            begin
433
                // Stalled endpoint?
434
                if (ep_stall_r)
435
                    next_state_r  = STATE_RX_DATA_IGNORE;
436
                // Some space to rx
437
                else if (rx_space_r)
438
                    next_state_r  = STATE_RX_DATA;
439
                // No rx space, ignore receive
440
                else
441
                    next_state_r  = STATE_RX_DATA_IGNORE;
442
            end
443
            //-------------------------------
444
            // SETUP transfer (host -> device)
445
            //-------------------------------
446
            else if (token_pid_w == `PID_SETUP)
447
            begin
448
                // Some space to rx
449
                if (rx_space_r)
450
                    next_state_r  = STATE_RX_DATA;
451
                // No rx space, ignore receive
452
                else
453
                    next_state_r  = STATE_RX_DATA_IGNORE;
454
            end
455
        end
456
        else if (reg_chirp_en_i)
457
            next_state_r  = STATE_TX_CHIRP;
458
    end
459
 
460
    //-----------------------------------------
461
    // RX_DATA
462
    //-----------------------------------------
463
    STATE_RX_DATA :
464
    begin
465
        // TODO: Exit data state handling?
466
 
467
        // TODO: Sort out ISO data bit handling
468
        // Check for expected DATAx PID
469
        if ((token_pid_w == `PID_DATA0 &&  ep_data_bit_r && !ep_iso_r) ||
470
            (token_pid_w == `PID_DATA1 && !ep_data_bit_r && !ep_iso_r))
471
            next_state_r  = STATE_RX_DATA_IGNORE;
472
        // Receive complete
473
        else if (rx_data_valid_w && rx_last_o)
474
            next_state_r  = STATE_RX_DATA_READY;
475
    end
476
    //-----------------------------------------
477
    // RX_DATA_IGNORE
478
    //-----------------------------------------
479
    STATE_RX_DATA_IGNORE :
480
    begin
481
        // Receive complete
482
        if (rx_data_valid_w && rx_last_o)
483
            next_state_r  = STATE_RX_DATA_READY;
484
    end
485
    //-----------------------------------------
486
    // RX_DATA_READY
487
    //-----------------------------------------
488
    STATE_RX_DATA_READY :
489
    begin
490
        if (rx_data_complete_w)
491
        begin
492
            // No response on CRC16 error
493
            if (rx_crc_err_o)
494
                next_state_r  = STATE_RX_IDLE;
495
            // ISO endpoint, no response?
496
            else if (ep_iso_r)
497
                next_state_r  = STATE_RX_IDLE;
498
            else
499
                next_state_r  = STATE_TX_HANDSHAKE;
500
        end
501
    end
502
    //-----------------------------------------
503
    // TX_DATA
504
    //-----------------------------------------
505
    STATE_TX_DATA :
506
    begin
507
        if (!tx_valid_q || tx_accept_w)
508
            if (tx_data_valid_r && tx_data_last_r && tx_data_accept_w)
509
                next_state_r  = STATE_TX_DATA_COMPLETE;
510
    end
511
    //-----------------------------------------
512
    // TX_HANDSHAKE
513
    //-----------------------------------------
514
    STATE_TX_DATA_COMPLETE :
515
    begin
516
        next_state_r  = STATE_RX_IDLE;
517
    end
518
    //-----------------------------------------
519
    // TX_HANDSHAKE
520
    //-----------------------------------------
521
    STATE_TX_HANDSHAKE :
522
    begin
523
        if (tx_accept_w)
524
            next_state_r  = STATE_RX_IDLE;
525
    end
526
    //-----------------------------------------
527
    // TX_CHIRP
528
    //-----------------------------------------
529
    STATE_TX_CHIRP :
530
    begin
531
        if (!reg_chirp_en_i)
532
            next_state_r  = STATE_RX_IDLE;
533
    end
534
 
535
    default :
536
       ;
537
 
538
    endcase
539
 
540
    //-----------------------------------------
541
    // USB Bus Reset (HOST->DEVICE)
542
    //----------------------------------------- 
543
    if (usb_rst_w && !reg_chirp_en_i)
544
        next_state_r  = STATE_RX_IDLE;
545
end
546
 
547
// Update state
548
always @ (posedge clk_i or posedge rst_i)
549
if (rst_i)
550
    state_q   <= STATE_RX_IDLE;
551
else
552
    state_q   <= next_state_r;
553
 
554
//-----------------------------------------------------------------
555
// Response
556
//-----------------------------------------------------------------
557
reg         tx_valid_r;
558
reg [7:0]   tx_pid_r;
559
 
560
always @ *
561
begin
562
    tx_valid_r = 1'b0;
563
    tx_pid_r   = 8'b0;
564
 
565
    case (state_q)
566
    //-----------------------------------------
567
    // IDLE
568
    //-----------------------------------------
569
    STATE_RX_IDLE :
570
    begin
571
        // Token received (OUT, IN, SETUP, PING)
572
        if (token_valid_w)
573
        begin
574
            //-------------------------------
575
            // IN transfer (device -> host)
576
            //-------------------------------
577
            if (token_pid_w == `PID_IN)
578
            begin
579
                // Stalled endpoint?
580
                if (ep_stall_r)
581
                begin
582
                    tx_valid_r = 1'b1;
583
                    tx_pid_r   = `PID_STALL;
584
                end
585
                // Some data to TX?
586
                else if (tx_ready_r)
587
                begin
588
                    tx_valid_r = 1'b1;
589
                    // TODO: Handle MDATA for ISOs
590
                    tx_pid_r   = ep_data_bit_r ? `PID_DATA1 : `PID_DATA0;
591
                end
592
                // No data to TX
593
                else
594
                begin
595
                    tx_valid_r = 1'b1;
596
                    tx_pid_r   = `PID_NAK;
597
                end
598
            end
599
            //-------------------------------
600
            // PING transfer (device -> host)
601
            //-------------------------------
602
            else if (token_pid_w == `PID_PING)
603
            begin
604
                // Stalled endpoint?
605
                if (ep_stall_r)
606
                begin
607
                    tx_valid_r = 1'b1;
608
                    tx_pid_r   = `PID_STALL;
609
                end
610
                // Data ready to RX
611
                else if (rx_space_r)
612
                begin
613
                    tx_valid_r = 1'b1;
614
                    tx_pid_r   = `PID_ACK;
615
                end
616
                // No data to TX
617
                else
618
                begin
619
                    tx_valid_r = 1'b1;
620
                    tx_pid_r   = `PID_NAK;
621
                end
622
            end
623
        end
624
    end
625
 
626
    //-----------------------------------------
627
    // RX_DATA_READY
628
    //-----------------------------------------
629
    STATE_RX_DATA_READY :
630
    begin
631
       // Receive complete
632
       if (rx_data_complete_w)
633
       begin
634
            // No response on CRC16 error
635
            if (rx_crc_err_o)
636
                ;
637
            // ISO endpoint, no response?
638
            else if (ep_iso_r)
639
                ;
640
            // Send STALL?
641
            else if (ep_stall_r)
642
            begin
643
                tx_valid_r = 1'b1;
644
                tx_pid_r   = `PID_STALL;
645
            end
646
            // DATAx bit mismatch
647
            else if ( (token_pid_w == `PID_DATA0 && ep_data_bit_r) ||
648
                      (token_pid_w == `PID_DATA1 && !ep_data_bit_r) )
649
            begin
650
                // Ack transfer to resync
651
                tx_valid_r = 1'b1;
652
                tx_pid_r   = `PID_ACK;
653
            end
654
            // Send NAK
655
            else if (!rx_space_q)
656
            begin
657
                tx_valid_r = 1'b1;
658
                tx_pid_r   = `PID_NAK;
659
            end
660
            // TODO: USB 2.0, no more buffer space, return NYET
661
            else
662
            begin
663
                tx_valid_r = 1'b1;
664
                tx_pid_r   = `PID_ACK;
665
            end
666
       end
667
    end
668
 
669
    //-----------------------------------------
670
    // TX_CHIRP
671
    //-----------------------------------------
672
    STATE_TX_CHIRP :
673
    begin
674
        tx_valid_r = 1'b1;
675
        tx_pid_r   = 8'b0;
676
    end
677
 
678
    default :
679
       ;
680
 
681
    endcase
682
end
683
 
684
always @ (posedge clk_i or posedge rst_i)
685
if (rst_i)
686
    tx_valid_q <= 1'b0;
687
else if (!tx_valid_q || tx_accept_w)
688
    tx_valid_q <= tx_valid_r;
689
 
690
always @ (posedge clk_i or posedge rst_i)
691
if (rst_i)
692
    tx_pid_q <= 8'b0;
693
else if (!tx_valid_q || tx_accept_w)
694
    tx_pid_q <= tx_pid_r;
695
 
696
//-----------------------------------------------------------------
697
// Receive enable
698
//-----------------------------------------------------------------
699
always @ (posedge clk_i or posedge rst_i)
700
if (rst_i)
701
    rx_enable_q <= 1'b0;
702
else if (usb_rst_w ||reg_chirp_en_i)
703
    rx_enable_q <= 1'b0;
704
else
705
    rx_enable_q <= (state_q == STATE_RX_DATA);
706
 
707
//-----------------------------------------------------------------
708
// Receive SETUP: Pulse on SETUP packet receive
709
//-----------------------------------------------------------------
710
always @ (posedge clk_i or posedge rst_i)
711
if (rst_i)
712
    rx_setup_q <= 1'b0;
713
else if (usb_rst_w ||reg_chirp_en_i)
714
    rx_setup_q <= 1'b0;
715
else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_SETUP) && (token_ep_w == 4'd0))
716
    rx_setup_q <= 1'b1;
717
else
718
    rx_setup_q <= 1'b0;
719
 
720
//-----------------------------------------------------------------
721
// Set Address
722
//-----------------------------------------------------------------
723
reg addr_update_pending_q;
724
 
725
wire ep0_tx_zlp_w = ep0_tx_data_valid_i && (ep0_tx_data_strb_i == 1'b0) &&
726
                    ep0_tx_data_last_i && ep0_tx_data_accept_o;
727
 
728
always @ (posedge clk_i or posedge rst_i)
729
if (rst_i)
730
    addr_update_pending_q   <= 1'b0;
731
else if (ep0_tx_zlp_w || usb_rst_w)
732
    addr_update_pending_q   <= 1'b0;
733
// TODO: Use write strobe
734
else if (reg_dev_addr_i != current_addr_q)
735
    addr_update_pending_q   <= 1'b1;
736
 
737
always @ (posedge clk_i or posedge rst_i)
738
if (rst_i)
739
    current_addr_q  <= `USB_DEV_W'b0;
740
else if (usb_rst_w)
741
    current_addr_q  <= `USB_DEV_W'b0;
742
else if (ep0_tx_zlp_w && addr_update_pending_q)
743
    current_addr_q  <= reg_dev_addr_i;
744
 
745
//-----------------------------------------------------------------
746
// SETUP request tracking
747
//-----------------------------------------------------------------
748
reg ep0_dir_in_q;
749
reg ep0_dir_out_q;
750
 
751
always @ (posedge clk_i or posedge rst_i)
752
if (rst_i)
753
    ep0_dir_in_q <= 1'b0;
754
else if (usb_rst_w ||reg_chirp_en_i)
755
    ep0_dir_in_q <= 1'b0;
756
else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_SETUP) && (token_ep_w == 4'd0))
757
    ep0_dir_in_q <= 1'b0;
758
else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_IN) && (token_ep_w == 4'd0))
759
    ep0_dir_in_q <= 1'b1;
760
 
761
always @ (posedge clk_i or posedge rst_i)
762
if (rst_i)
763
    ep0_dir_out_q <= 1'b0;
764
else if (usb_rst_w ||reg_chirp_en_i)
765
    ep0_dir_out_q <= 1'b0;
766
else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_SETUP) && (token_ep_w == 4'd0))
767
    ep0_dir_out_q <= 1'b0;
768
else if ((state_q == STATE_RX_IDLE) && token_valid_w && (token_pid_w == `PID_OUT) && (token_ep_w == 4'd0))
769
    ep0_dir_out_q <= 1'b1;
770
 
771
assign status_stage_w = ep0_dir_in_q && ep0_dir_out_q && (token_ep_w == 4'd0);
772
 
773
//-----------------------------------------------------------------
774
// Endpoint data bit toggle
775
//-----------------------------------------------------------------
776
reg new_data_bit_r;
777
always @ *
778
begin
779
    new_data_bit_r = ep_data_bit_r;
780
 
781
    case (state_q)
782
    //-----------------------------------------
783
    // RX_DATA_READY
784
    //-----------------------------------------
785
    STATE_RX_DATA_READY :
786
    begin
787
       // Receive complete
788
       if (rx_data_complete_w)
789
       begin
790
            // No toggle on CRC16 error
791
            if (rx_crc_err_o)
792
                ;
793
            // ISO endpoint, no response?
794
            else if (ep_iso_r)
795
                ; // TODO: HS handling
796
            // STALL?
797
            else if (ep_stall_r)
798
                ;
799
            // DATAx bit mismatch
800
            else if ( (token_pid_w == `PID_DATA0 && ep_data_bit_r) ||
801
                      (token_pid_w == `PID_DATA1 && !ep_data_bit_r) )
802
                ;
803
            // NAKd
804
            else if (!rx_space_q)
805
                ;
806
            // Data accepted - toggle data bit
807
            else
808
                new_data_bit_r = !ep_data_bit_r;
809
       end
810
    end
811
    //-----------------------------------------
812
    // RX_IDLE
813
    //-----------------------------------------
814
    STATE_RX_IDLE :
815
    begin
816
        // Token received (OUT, IN, SETUP, PING)
817
        if (token_valid_w)
818
        begin
819
            // SETUP packets always start with DATA0
820
            if (token_pid_w == `PID_SETUP)
821
                new_data_bit_r = 1'b0;
822
        end
823
        // ACK received
824
        else if (rx_handshake_w && token_pid_w == `PID_ACK)
825
        begin
826
            new_data_bit_r = !ep_data_bit_r;
827
        end
828
    end
829
    default:
830
        ;
831
    endcase
832
end
833
 
834
always @ (posedge clk_i or posedge rst_i)
835
if (rst_i)
836
    ep0_data_bit_q <= 1'b0;
837
else if (usb_rst_w)
838
    ep0_data_bit_q <= 1'b0;
839
else if (token_ep_w == 4'd0)
840
    ep0_data_bit_q <= new_data_bit_r;
841
always @ (posedge clk_i or posedge rst_i)
842
if (rst_i)
843
    ep1_data_bit_q <= 1'b0;
844
else if (usb_rst_w)
845
    ep1_data_bit_q <= 1'b0;
846
else if (token_ep_w == 4'd1)
847
    ep1_data_bit_q <= new_data_bit_r;
848
always @ (posedge clk_i or posedge rst_i)
849
if (rst_i)
850
    ep2_data_bit_q <= 1'b0;
851
else if (usb_rst_w)
852
    ep2_data_bit_q <= 1'b0;
853
else if (token_ep_w == 4'd2)
854
    ep2_data_bit_q <= new_data_bit_r;
855
always @ (posedge clk_i or posedge rst_i)
856
if (rst_i)
857
    ep3_data_bit_q <= 1'b0;
858
else if (usb_rst_w)
859
    ep3_data_bit_q <= 1'b0;
860
else if (token_ep_w == 4'd3)
861
    ep3_data_bit_q <= new_data_bit_r;
862
 
863
//-----------------------------------------------------------------
864
// Reset event
865
//-----------------------------------------------------------------
866
reg rst_event_q;
867
 
868
always @ (posedge clk_i or posedge rst_i)
869
if (rst_i)
870
    rst_event_q <= 1'b0;
871
else if (usb_rst_w)
872
    rst_event_q <= 1'b1;
873
else if (reg_sts_rst_clr_i)
874
    rst_event_q <= 1'b0;
875
 
876
assign reg_sts_rst_o = rst_event_q;
877
 
878
//-----------------------------------------------------------------
879
// Interrupts
880
//-----------------------------------------------------------------
881
reg intr_q;
882
 
883
reg cfg_int_rx_r;
884
reg cfg_int_tx_r;
885
 
886
always @ *
887
begin
888
    cfg_int_rx_r = 1'b0;
889
    cfg_int_tx_r = 1'b0;
890
 
891
    case (token_ep_w)
892
    4'd0:
893
    begin
894
        cfg_int_rx_r = ep0_cfg_int_rx_i;
895
        cfg_int_tx_r = ep0_cfg_int_tx_i;
896
    end
897
    4'd1:
898
    begin
899
        cfg_int_rx_r = ep1_cfg_int_rx_i;
900
        cfg_int_tx_r = ep1_cfg_int_tx_i;
901
    end
902
    4'd2:
903
    begin
904
        cfg_int_rx_r = ep2_cfg_int_rx_i;
905
        cfg_int_tx_r = ep2_cfg_int_tx_i;
906
    end
907
    4'd3:
908
    begin
909
        cfg_int_rx_r = ep3_cfg_int_rx_i;
910
        cfg_int_tx_r = ep3_cfg_int_tx_i;
911
    end
912
    default:
913
        ;
914
    endcase
915
end
916
 
917
always @ (posedge clk_i or posedge rst_i)
918
if (rst_i)
919
    intr_q <= 1'b0;
920
// SOF
921
else if (frame_valid_w && reg_int_en_sof_i)
922
    intr_q <= 1'b1;
923
// Reset event
924
else if (!rst_event_q && usb_rst_w)
925
    intr_q <= 1'b1;
926
// Rx ready
927
else if (state_q == STATE_RX_DATA_READY && rx_space_q && cfg_int_rx_r)
928
    intr_q <= 1'b1;
929
// Tx complete
930
else if (state_q == STATE_TX_DATA_COMPLETE && cfg_int_tx_r)
931
    intr_q <= 1'b1;
932
else
933
    intr_q <= 1'b0;
934
 
935
assign intr_o = intr_q;
936
 
937
//-------------------------------------------------------------------
938
// Debug
939
//-------------------------------------------------------------------
940
`ifdef verilator
941
/* verilator lint_off WIDTH */
942
reg [79:0] dbg_state;
943
 
944
always @ *
945
begin
946
    dbg_state = "-";
947
 
948
    case (state_q)
949
    STATE_RX_IDLE: dbg_state = "IDLE";
950
    STATE_RX_DATA: dbg_state = "RX_DATA";
951
    STATE_RX_DATA_READY: dbg_state = "RX_DATA_READY";
952
    STATE_RX_DATA_IGNORE: dbg_state = "RX_IGNORE";
953
    STATE_TX_DATA: dbg_state = "TX_DATA";
954
    STATE_TX_DATA_COMPLETE: dbg_state = "TX_DATA_COMPLETE";
955
    STATE_TX_HANDSHAKE: dbg_state = "TX_HANDSHAKE";
956
    STATE_TX_CHIRP: dbg_state = "CHIRP";
957
    endcase
958
end
959
 
960
reg [79:0] dbg_pid;
961
reg [7:0]  dbg_pid_r;
962
always @ *
963
begin
964
    dbg_pid = "-";
965
 
966
    if (tx_valid_q && tx_accept_w)
967
        dbg_pid_r = tx_pid_q;
968
    else if (token_valid_w || rx_handshake_w || rx_data_valid_w)
969
        dbg_pid_r = token_pid_w;
970
    else
971
        dbg_pid_r = 8'b0;
972
 
973
    case (dbg_pid_r)
974
    // Token
975
    `PID_OUT:
976
        dbg_pid = "OUT";
977
    `PID_IN:
978
        dbg_pid = "IN";
979
    `PID_SOF:
980
        dbg_pid = "SOF";
981
    `PID_SETUP:
982
        dbg_pid = "SETUP";
983
    `PID_PING:
984
        dbg_pid = "PING";
985
    // Data
986
    `PID_DATA0:
987
        dbg_pid = "DATA0";
988
    `PID_DATA1:
989
        dbg_pid = "DATA1";
990
    `PID_DATA2:
991
        dbg_pid = "DATA2";
992
    `PID_MDATA:
993
        dbg_pid = "MDATA";
994
    // Handshake
995
    `PID_ACK:
996
        dbg_pid = "ACK";
997
    `PID_NAK:
998
        dbg_pid = "NAK";
999
    `PID_STALL:
1000
        dbg_pid = "STALL";
1001
    `PID_NYET:
1002
        dbg_pid = "NYET";
1003
    // Special
1004
    `PID_PRE:
1005
        dbg_pid = "PRE/ERR";
1006
    `PID_SPLIT:
1007
        dbg_pid = "SPLIT";
1008
    default:
1009
        ;
1010
    endcase
1011
end
1012
/* verilator lint_on WIDTH */
1013
`endif
1014
 
1015
 
1016
endmodule

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