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ultra_embe |
//-----------------------------------------------------------------
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// USB Full Speed Host
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// V0.5
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// Ultra-Embedded.com
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// Copyright 2015-2019
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//
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// Email: admin@ultra-embedded.com
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//
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// License: GPL
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// If you would like a version with a more permissive license for
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// use in closed source commercial applications please contact me
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// for details.
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//-----------------------------------------------------------------
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//
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// This file is open source HDL; you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as
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// published by the Free Software Foundation; either version 2 of
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// the License, or (at your option) any later version.
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//
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// This file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this file; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Generated File
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//-----------------------------------------------------------------
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//-----------------------------------------------------------------
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// Module: 16-bit CRC used by USB data packets
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//-----------------------------------------------------------------
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module usbh_crc16
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(
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input [15:0] crc_i,
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input [7:0] data_i,
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output [15:0] crc_o
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);
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//-----------------------------------------------------------------
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// Implementation
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//-----------------------------------------------------------------
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assign crc_o[15] = data_i[0] ^ data_i[1] ^ data_i[2] ^ data_i[3] ^ data_i[4] ^
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data_i[5] ^ data_i[6] ^ data_i[7] ^ crc_i[7] ^ crc_i[6] ^
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crc_i[5] ^ crc_i[4] ^ crc_i[3] ^ crc_i[2] ^
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crc_i[1] ^ crc_i[0];
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assign crc_o[14] = data_i[0] ^ data_i[1] ^ data_i[2] ^ data_i[3] ^ data_i[4] ^ data_i[5] ^
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data_i[6] ^ crc_i[6] ^ crc_i[5] ^ crc_i[4] ^
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crc_i[3] ^ crc_i[2] ^ crc_i[1] ^ crc_i[0];
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assign crc_o[13] = data_i[6] ^ data_i[7] ^ crc_i[7] ^ crc_i[6];
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assign crc_o[12] = data_i[5] ^ data_i[6] ^ crc_i[6] ^ crc_i[5];
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assign crc_o[11] = data_i[4] ^ data_i[5] ^ crc_i[5] ^ crc_i[4];
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assign crc_o[10] = data_i[3] ^ data_i[4] ^ crc_i[4] ^ crc_i[3];
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assign crc_o[9] = data_i[2] ^ data_i[3] ^ crc_i[3] ^ crc_i[2];
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assign crc_o[8] = data_i[1] ^ data_i[2] ^ crc_i[2] ^ crc_i[1];
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assign crc_o[7] = data_i[0] ^ data_i[1] ^ crc_i[15] ^ crc_i[1] ^ crc_i[0];
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assign crc_o[6] = data_i[0] ^ crc_i[14] ^ crc_i[0];
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assign crc_o[5] = crc_i[13];
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assign crc_o[4] = crc_i[12];
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assign crc_o[3] = crc_i[11];
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assign crc_o[2] = crc_i[10];
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assign crc_o[1] = crc_i[9];
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assign crc_o[0] = data_i[0] ^ data_i[1] ^ data_i[2] ^ data_i[3] ^ data_i[4] ^ data_i[5] ^
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data_i[6] ^ data_i[7] ^ crc_i[8] ^ crc_i[7] ^ crc_i[6] ^
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crc_i[5] ^ crc_i[4] ^ crc_i[3] ^ crc_i[2] ^
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crc_i[1] ^ crc_i[0];
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endmodule
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