OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [bench/] [tb_wb_b3_ram_be.v] - Blame information for rev 102

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 88 unneback
module vl_wb_b3_ram_be_tb ();
2
 
3 89 unneback
   wire [31:0] wbm_a_dat_o;
4
   wire [3:0]  wbm_a_sel_o;
5
   wire [31:0] wbm_a_adr_o;
6
   wire [2:0]  wbm_a_cti_o;
7
   wire [1:0]  wbm_a_bte_o;
8
   wire        wbm_a_we_o ;
9
   wire        wbm_a_cyc_o;
10
   wire        wbm_a_stb_o;
11
   wire [31:0] wbm_a_dat_i;
12
   wire        wbm_a_ack_i;
13
   reg         wbm_a_clk  ;
14
   reg         wbm_a_rst  ;
15 88 unneback
 
16 91 unneback
parameter wb_clk_period = 20;
17 88 unneback
 
18 91 unneback
parameter [1:0] linear = 2'b00,
19
                beat4  = 2'b01,
20
                beat8  = 2'b10,
21
                beat16 = 2'b11;
22
 
23
parameter [2:0] classic = 3'b000,
24
                inc     = 3'b010,
25
                eob     = 3'b111;
26
parameter rd = 1'b0;
27
parameter wr = 1'b1;
28 89 unneback
 
29 91 unneback
parameter instructions = 32;
30 89 unneback
 
31 91 unneback
// {adr_o,bte_o,cti_o,dat_o,sel_o,we_o,cyc_o,stb_o}
32
parameter [32+2+3+32+4+1+1+1:1] inst_rom [0:instructions-1]= {
33
                {32'h0,linear,classic,32'h0,4'b1111,rd,1'b0,1'b0},
34
                {32'h100,linear,classic,32'h12345678,4'b1111,wr,1'b1,1'b1}, // write 0x12345678 @ 0x100
35
                {32'h100,linear,classic,32'h0,4'b1111,rd,1'b1,1'b1},        // read  @ 0x100            
36
                {32'h100,beat4,eob,32'h87654321,4'b1111,wr,1'b1,1'b1}, // write 0x12345678 @ 0x100 with 01,111
37
                {32'h100,linear,classic,32'h0,4'b1111,rd,1'b1,1'b1},        // read  @ 0x100
38
                {32'h0,linear,classic,32'h0,4'b1111,rd,1'b0,1'b0},
39
                {32'h100,beat4,inc,32'h00010002,4'b1111,wr,1'b1,1'b1}, // write burst
40
                {32'h104,beat4,inc,32'h00030004,4'b1111,wr,1'b1,1'b1},
41
                {32'h108,beat4,inc,32'h00050006,4'b1111,wr,1'b1,1'b1},
42
                {32'h10c,beat4,eob,32'h00070008,4'b1111,wr,1'b1,1'b1},
43
                {32'h104,linear,classic,32'hA1FFFFFF,4'b1000,wr,1'b1,1'b1},// write byte                
44
                {32'h108,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1}, // read burst
45
                {32'h10c,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1},
46
                {32'h100,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1},
47
                {32'h104,beat4,eob,32'h0,4'b1111,rd,1'b1,1'b1},
48
                {32'h100,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1}, // read burst with strobe going low once
49
                {32'h104,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1},
50
                {32'h104,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b0},
51
                {32'h108,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1},
52
                {32'h10c,beat4,eob,32'h0,4'b1111,rd,1'b1,1'b1},
53
                {32'h100,linear,inc,32'hdeaddead,4'b1111,1'b1,1'b1,1'b1}, // write
54
                {32'h104,linear,eob,32'h55555555,4'b1111,1'b1,1'b1,1'b1}, //            
55
                {32'h100,linear,inc,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read
56
                {32'h104,linear,eob,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read
57
                {32'h100,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1}, // read burst with strobe going low
58
                {32'h104,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b0},
59
                {32'h104,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1},
60
                {32'h108,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1},
61
                {32'h108,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b0},
62
                {32'h10c,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b0},
63
                {32'h10c,beat4,eob,32'h0,4'b1111,rd,1'b1,1'b1},
64
                {32'h0,linear,classic,32'h0,4'b1111,rd,1'b0,1'b0}};
65
 
66
        parameter [31:0] dat [0:instructions-1] = {
67
                32'h0,
68
                32'h0,
69
                32'h0,
70
                32'h12345678,
71
                32'h0,
72
                32'h87654321,
73
                32'h0,
74
                32'h0,
75
                32'h0,
76
                32'h0,
77
                32'h0,
78
                32'h0,
79
                32'h00050006,
80
                32'h00070008,
81
                32'h00010002,
82
                32'ha1030004,
83
                32'h00010002,
84
                32'ha1030004,
85
                32'h0,
86
                32'h00050006,
87
                32'h00070008,
88
                32'h0,
89
                32'h0,
90
                32'hdeaddead,
91
                32'h55555555,
92
                32'hdeaddead,
93
                32'h0,
94
                32'h55555555,
95
                32'h00050006,
96
                32'h0,
97
                32'h0,
98
                32'h00070008};
99
 
100
 
101 102 unneback
vl_wb_b3_ram_be
102 91 unneback
dut (
103
    .wbs_dat_i(wbm_a_dat_o),
104
    .wbs_adr_i(wbm_a_adr_o[31:2]),
105
    .wbs_cti_i(wbm_a_cti_o),
106
    .wbs_bte_i(wbm_a_bte_o),
107
    .wbs_sel_i(wbm_a_sel_o),
108
    .wbs_we_i (wbm_a_we_o),
109
    .wbs_stb_i(wbm_a_stb_o),
110
    .wbs_cyc_i(wbm_a_cyc_o),
111
    .wbs_dat_o(wbm_a_dat_i),
112
    .wbs_ack_o(wbm_a_ack_i),
113
    .wb_clk(wbm_a_clk),
114
    .wb_rst(wbm_a_rst));
115
 
116
wbm # ( .inst_rom(inst_rom), .dat(dat), .testcase("\nTest case:\nwb_b3_ram_be\n"))
117
wbmi(
118 89 unneback
            .adr_o(wbm_a_adr_o),
119
            .bte_o(wbm_a_bte_o),
120
            .cti_o(wbm_a_cti_o),
121
            .dat_o(wbm_a_dat_o),
122
            .sel_o(wbm_a_sel_o),
123
            .we_o (wbm_a_we_o),
124
            .cyc_o(wbm_a_cyc_o),
125
            .stb_o(wbm_a_stb_o),
126
            .dat_i(wbm_a_dat_i),
127
            .ack_i(wbm_a_ack_i),
128
            .clk(wbm_a_clk),
129
            .reset(wbm_a_rst),
130
            .OK(wbm_OK)
131
);
132
 
133
initial
134
    begin
135
        #0      wbm_a_rst = 1'b1;
136
        #200    wbm_a_rst = 1'b0;
137
    end
138
 
139
// Wishbone clock
140
initial
141
    begin
142
        #0 wbm_a_clk = 1'b0;
143
        forever
144
            #(wb_clk_period/2) wbm_a_clk = !wbm_a_clk;
145
    end
146
 
147 91 unneback
initial
148
    #20000 $finish;
149 88 unneback
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.