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[/] [versatile_library/] [trunk/] [bench/] [tb_wb_cache.v] - Blame information for rev 144

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1 102 unneback
module vl_wb_cache_tb ();
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   wire [31:0] wbm_a_dat_o;
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   wire [3:0]  wbm_a_sel_o;
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   wire [31:0] wbm_a_adr_o;
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   wire [2:0]  wbm_a_cti_o;
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   wire [1:0]  wbm_a_bte_o;
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   wire        wbm_a_we_o ;
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   wire        wbm_a_cyc_o;
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   wire        wbm_a_stb_o;
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   wire [31:0] wbm_a_dat_i;
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   wire        wbm_a_ack_i;
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   reg         wbm_a_clk  ;
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   reg         wbm_a_rst  ;
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   wire [31:0] wbm_b_dat_o;
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   wire [3:0]  wbm_b_sel_o;
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   wire [31:0] wbm_b_adr_o;
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   wire [2:0]  wbm_b_cti_o;
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   wire [1:0]  wbm_b_bte_o;
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   wire        wbm_b_we_o ;
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   wire        wbm_b_cyc_o;
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   wire        wbm_b_stb_o;
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   wire [31:0] wbm_b_dat_i;
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   wire        wbm_b_ack_i;
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   wire        wbm_b_stall_i;
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   reg         wbm_b_clk  ;
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   reg         wbm_b_rst  ;
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parameter wb_clk_period = 20;
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parameter [1:0] linear = 2'b00,
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                beat4  = 2'b01,
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                beat8  = 2'b10,
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                beat16 = 2'b11;
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parameter [2:0] classic = 3'b000,
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                inc     = 3'b010,
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                eob     = 3'b111;
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parameter rd = 1'b0;
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parameter wr = 1'b1;
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parameter instructions = 32;
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// {adr_o,bte_o,cti_o,dat_o,sel_o,we_o,cyc_o,stb_o}
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parameter [32+2+3+32+4+1+1+1:1] inst_rom0 [0:instructions-1]= {
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                {32'h0,linear,classic,32'h0,4'b1111,rd,1'b0,1'b0},
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                {32'h100,linear,classic,32'h12345678,4'b1111,wr,1'b1,1'b1}, // write 0x12345678 @ 0x100
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                {32'h100,linear,classic,32'h0,4'b1111,rd,1'b1,1'b1},        // read  @ 0x100            
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                {32'h1100,beat4,eob,32'h87654321,4'b1111,wr,1'b1,1'b1},     // write 0x87654321 @ 0x1100 with 01,111
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                {32'h1100,linear,classic,32'h0,4'b1111,rd,1'b1,1'b1},       // read  @ 0x1100
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                {32'h0,linear,classic,32'h0,4'b1111,rd,1'b0,1'b0},
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                {32'h100,beat4,inc,32'h00010002,4'b1111,wr,1'b1,1'b1},      // write burst @ 0x100
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                {32'h104,beat4,inc,32'h00030004,4'b1111,wr,1'b1,1'b1},
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                {32'h108,beat4,inc,32'h00050006,4'b1111,wr,1'b1,1'b1},
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                {32'h10c,beat4,eob,32'h00070008,4'b1111,wr,1'b1,1'b1},
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                {32'h104,linear,classic,32'hA1FFFFFF,4'b1000,wr,1'b1,1'b1}, // write byte a1 @ 104              
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                {32'h108,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1},             // read burst
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                {32'h10c,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1},
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                {32'h100,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1},
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                {32'h104,beat4,eob,32'h0,4'b1111,rd,1'b1,1'b1},
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                {32'h100,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1},             // read burst with strobe going low once
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                {32'h104,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1},
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                {32'h104,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b0},
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                {32'h108,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1},
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                {32'h10c,beat4,eob,32'h0,4'b1111,rd,1'b1,1'b1},
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                {32'h100,linear,inc,32'hdeaddead,4'b1111,1'b1,1'b1,1'b1}, // write
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                {32'h104,linear,eob,32'h55555555,4'b1111,1'b1,1'b1,1'b1}, //            
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                {32'h100,linear,inc,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read
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                {32'h104,linear,eob,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read
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                {32'h100,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1}, // read burst with strobe going low
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                {32'h104,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b0},
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                {32'h104,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1},
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                {32'h108,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b1},
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                {32'h108,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b0},
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                {32'h10c,beat4,inc,32'h0,4'b1111,rd,1'b1,1'b0},
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                {32'h10c,beat4,eob,32'h0,4'b1111,rd,1'b1,1'b1},
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                {32'h0,linear,classic,32'h0,4'b1111,rd,1'b0,1'b0}};
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        parameter [31:0] dat0 [0:instructions-1] = {
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                32'h0,
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                32'h0,
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                32'h0,
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                32'h12345678,
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                32'h0,
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                32'h87654321,
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                32'h0,
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                32'h0,
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                32'h0,
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                32'h0,
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                32'h0,
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                32'h0,
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                32'h00050006,
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                32'h00070008,
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                32'h00010002,
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                32'ha1030004,
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                32'h00010002,
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                32'ha1030004,
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                32'h0,
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                32'h00050006,
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                32'h00070008,
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                32'h0,
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                32'h0,
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                32'hdeaddead,
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                32'h55555555,
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                32'hdeaddead,
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                32'h0,
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                32'h55555555,
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                32'h00050006,
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                32'h0,
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                32'h0,
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                32'h00070008};
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vl_wb_cache
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# (
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    .dw_s(32),
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    .aw_s(16),
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    .dw_m(32),
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    .wbs_max_burst_width(4),
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    .wbm_burst_size(4),
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    .aw_offset(2),
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    .aw_slot(5),
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    .valid_mem(1),
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    .async(1),
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    .debug(0))
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dut (
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    .wbs_dat_i(wbm_a_dat_o),
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    .wbs_adr_i(wbm_a_adr_o[17:2]),
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    .wbs_sel_i(wbm_a_sel_o),
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    .wbs_cti_i(wbm_a_cti_o),
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    .wbs_bte_i(wbm_a_bte_o),
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    .wbs_we_i(wbm_a_we_o),
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    .wbs_stb_i(wbm_a_stb_o),
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    .wbs_cyc_i(wbm_a_cyc_o),
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    .wbs_dat_o(wbm_a_dat_i),
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    .wbs_ack_o(wbm_a_ack_i),
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    .wbs_clk(wbm_a_clk),
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    .wbs_rst(wbm_a_rst),
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    .wbm_dat_o(wbm_b_dat_o),
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    .wbm_adr_o(wbm_b_adr_o[17:2]),
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    .wbm_sel_o(wbm_b_sel_o),
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    .wbm_cti_o(wbm_b_cti_o),
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    .wbm_bte_o(wbm_b_bte_o),
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    .wbm_we_o(wbm_b_we_o),
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    .wbm_stb_o(wbm_b_stb_o),
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    .wbm_cyc_o(wbm_b_cyc_o),
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    .wbm_dat_i(wbm_b_dat_i),
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    .wbm_ack_i(wbm_b_ack_i),
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    .wbm_stall_i(wbm_b_stall_i),
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    .wbm_clk(wbm_b_clk),
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    .wbm_rst(wbm_b_rst));
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assign wbm_b_adr_o[31:18] = 14'h00;
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assign wbm_b_adr_o[1:0] = 2'b00;
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wbm # ( .inst_rom(inst_rom0), .dat(dat0), .testcase("\nTest case:\nwb_b3_dpram A side\n"))
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wbmi0(
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            .adr_o(wbm_a_adr_o),
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            .bte_o(wbm_a_bte_o),
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            .cti_o(wbm_a_cti_o),
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            .dat_o(wbm_a_dat_o),
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            .sel_o(wbm_a_sel_o),
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            .we_o (wbm_a_we_o),
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            .cyc_o(wbm_a_cyc_o),
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            .stb_o(wbm_a_stb_o),
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            .dat_i(wbm_a_dat_i),
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            .ack_i(wbm_a_ack_i),
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            .clk(wbm_a_clk),
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            .reset(wbm_a_rst),
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            .OK(wbm_OK)
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);
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vl_wb_ram # (
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    .dat_width(32),
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    .adr_width(16),
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    .memory_init(2),
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    .mode("B4"))
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main_mem (
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    .wbs_dat_i(wbm_b_dat_o),
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    .wbs_adr_i(wbm_b_adr_o[17:2]),
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    .wbs_sel_i(wbm_b_sel_o),
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    .wbs_we_i (wbm_b_we_o),
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    .wbs_bte_i(wbm_b_bte_o),
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    .wbs_cti_i(wbm_b_cti_o),
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    .wbs_stb_i(wbm_b_stb_o),
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    .wbs_cyc_i(wbm_b_cyc_o),
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    .wbs_dat_o(wbm_b_dat_i),
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    .wbs_stall_o(wbm_b_stall_i),
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    .wbs_ack_o(wbm_b_ack_i),
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    .wb_clk(wbm_b_clk),
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    .wb_rst(wbm_b_rst));
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initial
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    begin
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        #0      wbm_a_rst = 1'b1;
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        #200    wbm_a_rst = 1'b0;
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    end
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// Wishbone clock
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initial
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    begin
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        #0 wbm_a_clk = 1'b0;
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        forever
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            #(wb_clk_period/2) wbm_a_clk = !wbm_a_clk;
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    end
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initial
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    begin
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        #0      wbm_b_rst = 1'b1;
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        #200    wbm_b_rst = 1'b0;
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    end
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// Wishbone clock
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initial
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    begin
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        #0 wbm_b_clk = 1'b0;
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        forever
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            #(wb_clk_period/5) wbm_b_clk = !wbm_b_clk;
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    end
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initial
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    #20000 $finish;
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endmodule

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