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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Blame information for rev 40

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45 4 unneback
// use to enable global buffers for high fan out signals such as clock and reset
46 3 unneback
 
47
`ifdef ACTEL
48 40 unneback
`ifdef GBUF
49 3 unneback
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63 40 unneback
`define MODULE gbuf
64
module `BASE`MODULE ( i, o);
65
`undef MODULE
66 3 unneback
input i;
67
output o;
68 4 unneback
//E2_ifdef SIM_GBUF
69
assign o=i;
70
//E2_else
71 3 unneback
gbuf gbuf_i0 ( .CLK(i), .GL(o));
72 4 unneback
//E2_endif
73 3 unneback
endmodule
74 40 unneback
`endif
75 33 unneback
 
76 3 unneback
`else
77 33 unneback
 
78 40 unneback
`ifdef ALTERA
79
`ifdef GBUF
80 21 unneback
//altera
81 40 unneback
`define MODULE gbuf
82
module `BASE`MODULE ( i, o);
83
`undef MODULE
84 33 unneback
input i;
85
output o;
86
assign o = i;
87
endmodule
88 40 unneback
`endif
89 33 unneback
 
90 3 unneback
`else
91
 
92 40 unneback
`ifdef GBUF
93 4 unneback
`timescale 1 ns/100 ps
94 40 unneback
`define MODULE
95
module `BASE`MODULE ( i, o);
96
`undef MODULE
97 3 unneback
input i;
98
output o;
99
assign o = i;
100
endmodule
101 40 unneback
`endif
102 3 unneback
`endif // ALTERA
103
`endif //ACTEL
104
 
105 40 unneback
`ifdef SYNC_RST
106 3 unneback
// sync reset
107 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
108 3 unneback
// output active high global reset sync with two DFFs 
109 4 unneback
`timescale 1 ns/100 ps
110 40 unneback
`define MODULE sync_rst
111
module `BASE`MODULE ( rst_n_i, rst_o, clk);
112
`undef MODULE
113 3 unneback
input rst_n_i, clk;
114
output rst_o;
115 18 unneback
reg [1:0] tmp;
116 3 unneback
always @ (posedge clk or negedge rst_n_i)
117
if (!rst_n_i)
118 17 unneback
        tmp <= 2'b11;
119 3 unneback
else
120 33 unneback
        tmp <= {1'b0,tmp[1]};
121 40 unneback
`define MODULE gbuf
122
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
123
`undef MODULE
124 3 unneback
endmodule
125 40 unneback
`endif
126 3 unneback
 
127 40 unneback
`ifdef PLL
128 3 unneback
// vl_pll
129
`ifdef ACTEL
130 32 unneback
///////////////////////////////////////////////////////////////////////////////
131 17 unneback
`timescale 1 ps/1 ps
132 40 unneback
`define MODULE pll
133
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
134
`undef MODULE
135 3 unneback
parameter index = 0;
136 4 unneback
parameter number_of_clk = 1;
137 17 unneback
parameter period_time_0 = 20000;
138
parameter period_time_1 = 20000;
139
parameter period_time_2 = 20000;
140
parameter lock_delay = 2000000;
141 3 unneback
input clk_i, rst_n_i;
142
output lock;
143
output reg [0:number_of_clk-1] clk_o;
144
output [0:number_of_clk-1] rst_o;
145
 
146
//E2_ifdef SIM_PLL
147
 
148 4 unneback
always
149
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
150
 
151
generate if (number_of_clk > 1)
152
always
153
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
154
endgenerate
155
 
156
generate if (number_of_clk > 2)
157
always
158
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
159
endgenerate
160
 
161 3 unneback
genvar i;
162
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
163
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
164
end
165
endgenerate
166
 
167
assign #lock_delay lock = rst_n_i;
168 4 unneback
 
169 3 unneback
endmodule
170
//E2_else
171
generate if (number_of_clk==1 & index==0) begin
172
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
173
end
174
endgenerate // index==0
175
generate if (number_of_clk==1 & index==1) begin
176
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
177
end
178
endgenerate // index==1
179
generate if (number_of_clk==1 & index==2) begin
180
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
181
end
182
endgenerate // index==2
183
generate if (number_of_clk==1 & index==3) begin
184
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
185
end
186
endgenerate // index==0
187
 
188
generate if (number_of_clk==2 & index==0) begin
189
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
190
end
191
endgenerate // index==0
192
generate if (number_of_clk==2 & index==1) begin
193
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
194
end
195
endgenerate // index==1
196
generate if (number_of_clk==2 & index==2) begin
197
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
198
end
199
endgenerate // index==2
200
generate if (number_of_clk==2 & index==3) begin
201
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
202
end
203
endgenerate // index==0
204
 
205
generate if (number_of_clk==3 & index==0) begin
206
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
207
end
208
endgenerate // index==0
209
generate if (number_of_clk==3 & index==1) begin
210
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
211
end
212
endgenerate // index==1
213
generate if (number_of_clk==3 & index==2) begin
214
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
215
end
216
endgenerate // index==2
217
generate if (number_of_clk==3 & index==3) begin
218
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
219
end
220
endgenerate // index==0
221
 
222
genvar i;
223
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
224 40 unneback
`define MODULE sync_rst
225
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
226
`undef MODULE
227 3 unneback
end
228
endgenerate
229
endmodule
230
//E2_endif
231 32 unneback
///////////////////////////////////////////////////////////////////////////////
232 3 unneback
 
233
`else
234
 
235 32 unneback
///////////////////////////////////////////////////////////////////////////////
236 3 unneback
`ifdef ALTERA
237
 
238 32 unneback
`timescale 1 ps/1 ps
239 40 unneback
`define MODULE pll
240
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
241
`undef MODULE
242 32 unneback
parameter index = 0;
243
parameter number_of_clk = 1;
244
parameter period_time_0 = 20000;
245
parameter period_time_1 = 20000;
246
parameter period_time_2 = 20000;
247
parameter period_time_3 = 20000;
248
parameter period_time_4 = 20000;
249
parameter lock_delay = 2000000;
250
input clk_i, rst_n_i;
251
output lock;
252
output reg [0:number_of_clk-1] clk_o;
253
output [0:number_of_clk-1] rst_o;
254
 
255
//E2_ifdef SIM_PLL
256
 
257
always
258
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
259
 
260
generate if (number_of_clk > 1)
261
always
262
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
263
endgenerate
264
 
265
generate if (number_of_clk > 2)
266
always
267
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
268
endgenerate
269
 
270 33 unneback
generate if (number_of_clk > 3)
271 32 unneback
always
272
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
273
endgenerate
274
 
275 33 unneback
generate if (number_of_clk > 4)
276 32 unneback
always
277
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
278
endgenerate
279
 
280
genvar i;
281
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
282
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
283
end
284
endgenerate
285
 
286 33 unneback
//assign #lock_delay lock = rst_n_i;
287
assign lock = rst_n_i;
288 32 unneback
 
289
endmodule
290
//E2_else
291
 
292 33 unneback
//E2_ifdef VL_PLL0
293
//E2_ifdef VL_PLL0_CLK1
294
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
295
//E2_endif
296
//E2_ifdef VL_PLL0_CLK2
297
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
298
//E2_endif
299
//E2_ifdef VL_PLL0_CLK3
300
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
301
//E2_endif
302
//E2_ifdef VL_PLL0_CLK4
303
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
304
//E2_endif
305
//E2_ifdef VL_PLL0_CLK5
306
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
307
//E2_endif
308
//E2_endif
309 32 unneback
 
310 33 unneback
//E2_ifdef VL_PLL1
311
//E2_ifdef VL_PLL1_CLK1
312
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
313
//E2_endif
314
//E2_ifdef VL_PLL1_CLK2
315
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
316
//E2_endif
317
//E2_ifdef VL_PLL1_CLK3
318
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
319
//E2_endif
320
//E2_ifdef VL_PLL1_CLK4
321
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
322
//E2_endif
323
//E2_ifdef VL_PLL1_CLK5
324
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
325
//E2_endif
326
//E2_endif
327 32 unneback
 
328 33 unneback
//E2_ifdef VL_PLL2
329
//E2_ifdef VL_PLL2_CLK1
330
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
331
//E2_endif
332
//E2_ifdef VL_PLL2_CLK2
333
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
334
//E2_endif
335
//E2_ifdef VL_PLL2_CLK3
336
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
337
//E2_endif
338
//E2_ifdef VL_PLL2_CLK4
339
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
340
//E2_endif
341
//E2_ifdef VL_PLL2_CLK5
342
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
343
//E2_endif
344
//E2_endif
345 32 unneback
 
346 33 unneback
//E2_ifdef VL_PLL3
347
//E2_ifdef VL_PLL3_CLK1
348
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
349
//E2_endif
350
//E2_ifdef VL_PLL3_CLK2
351
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
352
//E2_endif
353
//E2_ifdef VL_PLL3_CLK3
354
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
355
//E2_endif
356
//E2_ifdef VL_PLL3_CLK4
357
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
358
//E2_endif
359
//E2_ifdef VL_PLL3_CLK5
360
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
361
//E2_endif
362
//E2_endif
363 32 unneback
 
364
genvar i;
365
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
366 40 unneback
`define MODULE sync_rst
367
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
368
`undef MODULE
369 32 unneback
end
370
endgenerate
371
endmodule
372
//E2_endif
373
///////////////////////////////////////////////////////////////////////////////
374
 
375 3 unneback
`else
376
 
377
// generic PLL
378 17 unneback
`timescale 1 ps/1 ps
379 40 unneback
`define MODULE pll
380
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
381
`undef MODULE
382 3 unneback
parameter index = 0;
383 4 unneback
parameter number_of_clk = 1;
384 17 unneback
parameter period_time_0 = 20000;
385
parameter period_time_1 = 20000;
386
parameter period_time_2 = 20000;
387 3 unneback
parameter lock_delay = 2000;
388
input clk_i, rst_n_i;
389
output lock;
390
output reg [0:number_of_clk-1] clk_o;
391
output [0:number_of_clk-1] rst_o;
392
 
393 4 unneback
always
394
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
395
 
396
generate if (number_of_clk > 1)
397
always
398
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
399
endgenerate
400
 
401
generate if (number_of_clk > 2)
402
always
403
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
404
endgenerate
405
 
406 3 unneback
genvar i;
407 4 unneback
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
408 40 unneback
`define MODULE sync_rst
409
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
410
`undef MODULE
411 3 unneback
end
412
endgenerate
413
 
414
assign #lock_delay lock = rst_n_i;
415
 
416
endmodule
417
 
418
`endif //altera
419 17 unneback
`endif //actel
420 40 unneback
`undef MODULE
421
`endif

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