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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 77

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`ifndef BASE
`define BASE vl_
`endif
 
// default SYN_KEEP definition
`define SYN_KEEP /*synthesis syn_keep = 1*/
 
`ifdef ACTEL
`undef SYN_KEEP
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ALL
 
`define GBUF
`define SYNC_RST
`define PLL
 
`define MULTS
`define MULTS18X18
`define MULT
`define SHIFT_UNIT_32
`define LOGIC_UNIT
 
`define CNT_SHREG_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define PARITY
 
`define ROM_INIT
`define RAM
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_2R2W
`define DPRAM_BE_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX
`define REG_FILE
 
`define DFF
`define DFF_ARRAY
`define DFF_CE
`define DFF_CE_CLEAR
`define DF_CE_SET
`define SPR
`define SRP
`define DFF_SR
`define LATCH
`define SHREG
`define SHREG_CE
`define DELAY
`define DELAY_EMPTYFLAG
 
`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_B3_RAM_BE
`define WB_B4_RAM_BE
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
 
`define IO_DFF_OE
`define O_DFF
 
`endif
 
`ifdef PLL
`ifndef SYNC_RST
`define SYNC_RST
`endif
`endif
 
`ifdef SYNC_RST
`ifndef GBUF
`define GBUF
`endif
`endif
 
`ifdef WB_DPRAM
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef SPR
`define SPR
`endif
`endif
 
`ifdef WB_B3_RAM_BE
`ifndef WB3_ARBITER_TYPE1
`define WB3_ARBITER_TYPE1
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
`endif
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef WB3AVALON_BRIDGE
`ifndef WB3WB3_BRIDGE
`define WB3WB3_BRIDGE
`endif
`endif
 
`ifdef WB3WB3_BRIDGE
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DFF_CE
`define DFF_CE
`endif
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`endif
`endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef SHIFT_UNIT_32
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef MUX2_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX3_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX4_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX5_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX6_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_BIN_CE
`define CNT_BIN_CE
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_LFSR_CE
`define CNT_LFSR_CE
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`endif
`endif
 
`ifdef FIFO_1R1W_ASYNC
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_CMP_ASYNC
`ifndef DFF_SR
`define DFF_SR
`endif
`ifndef DFF
`define DFF
`endif
`endif
 
`ifdef REG_FILE
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif

Line No.	Rev	Author	Line
1	40	unneback	`ifndef BASE
2			`define BASE vl_
3			`endif
4
5	60	unneback	`// default SYN_KEEP definition`
6			`define SYN_KEEP /synthesis syn_keep = 1/
7
8	44	unneback	`ifdef ACTEL
9	60	unneback	`undef SYN_KEEP
10	44	unneback	`define SYN_KEEP /synthesis syn_keep = 1/
11			`endif
12
13	40	unneback	`ifdef ALL
14
15			`define GBUF
16			`define SYNC_RST
17			`define PLL
18
19			`define MULTS
20			`define MULTS18X18
21			`define MULT
22			`define SHIFT_UNIT_32
23			`define LOGIC_UNIT
24
25			`define CNT_SHREG_WRAP
26			`define CNT_SHREG_CE_WRAP
27			`define CNT_SHREG_CE_CLEAR
28			`define CNT_SHREG_CE_CLEAR_WRAP
29
30			`define MUX_ANDOR
31			`define MUX2_ANDOR
32			`define MUX3_ANDOR
33			`define MUX4_ANDOR
34			`define MUX5_ANDOR
35			`define MUX6_ANDOR
36	43	unneback	`define PARITY
37	40	unneback
38			`define ROM_INIT
39			`define RAM
40			`define RAM_BE
41			`define DPRAM_1R1W
42			`define DPRAM_2R1W
43			`define DPRAM_2R2W
44	75	unneback	`define DPRAM_BE_2R2W
45	40	unneback	`define FIFO_1R1W_FILL_LEVEL_SYNC
46			`define FIFO_2R2W_SYNC_SIMPLEX
47			`define FIFO_CMP_ASYNC
48			`define FIFO_1R1W_ASYNC
49			`define FIFO_2R2W_ASYNC
50			`define FIFO_2R2W_ASYNC_SIMPLEX
51	48	unneback	`define REG_FILE
52	40	unneback
53			`define DFF
54			`define DFF_ARRAY
55			`define DFF_CE
56			`define DFF_CE_CLEAR
57			`define DF_CE_SET
58			`define SPR
59			`define SRP
60			`define DFF_SR
61			`define LATCH
62			`define SHREG
63			`define SHREG_CE
64			`define DELAY
65			`define DELAY_EMPTYFLAG
66
67	75	unneback	`define WB3AVALON_BRIDGE
68	40	unneback	`define WB3WB3_BRIDGE
69			`define WB3_ARBITER_TYPE1
70	59	unneback	`define WB_B3_RAM_BE
71	49	unneback	`define WB_B4_RAM_BE
72	48	unneback	`define WB_B4_ROM
73	40	unneback	`define WB_BOOT_ROM
74			`define WB_DPRAM
75
76	44	unneback	`define IO_DFF_OE
77			`define O_DFF
78
79	40	unneback	`endif
80
81			`ifdef PLL
82			`ifndef SYNC_RST
83			`define SYNC_RST
84			`endif
85			`endif
86
87			`ifdef SYNC_RST
88			`ifndef GBUF
89			`define GBUF
90			`endif
91			`endif
92
93			`ifdef WB_DPRAM
94			`ifndef DPRAM_2R2W
95			`define DPRAM_2R2W
96			`endif
97			`ifndef SPR
98			`define SPR
99			`endif
100			`endif
101
102	62	unneback	`ifdef WB_B3_RAM_BE
103			`ifndef WB3_ARBITER_TYPE1
104			`define WB3_ARBITER_TYPE1
105			`endif
106			`ifndef RAM_BE
107			`define RAM_BE
108			`endif
109			`endif
110
111	40	unneback	`ifdef WB3_ARBITER_TYPE1
112	42	unneback	`ifndef SPR
113			`define SPR
114			`endif
115	40	unneback	`ifndef MUX_ANDOR
116			`define MUX_ANDOR
117			`endif
118			`endif
119
120	76	unneback	`ifdef WB3AVALON_BRIDGE
121			`ifndef WB3WB3_BRIDGE
122			`define WB3WB3_BRIDGE
123			`endif
124			`endif
125
126	40	unneback	`ifdef WB3WB3_BRIDGE
127			`ifndef CNT_SHREG_CE_CLEAR
128			`define CNT_SHREG_CE_CLEAR
129			`endif
130			`ifndef DFF
131			`define DFF
132			`endif
133			`ifndef DFF_CE
134			`define DFF_CE
135			`endif
136			`ifndef CNT_SHREG_CE_CLEAR
137			`define CNT_SHREG_CE_CLEAR
138			`endif
139			`ifndef FIFO_2R2W_ASYNC_SIMPLEX
140			`define FIFO_2R2W_ASYNC_SIMPLEX
141			`endif
142			`endif
143
144			`ifdef MULTS18X18
145			`ifndef MULTS
146			`define MULTS
147			`endif
148			`endif
149
150			`ifdef SHIFT_UNIT_32
151			`ifndef MULTS
152			`define MULTS
153			`endif
154			`endif
155
156			`ifdef MUX2_ANDOR
157			`ifndef MUX_ANDOR
158			`define MUX_ANDOR
159			`endif
160			`endif
161
162			`ifdef MUX3_ANDOR
163			`ifndef MUX_ANDOR
164			`define MUX_ANDOR
165			`endif
166			`endif
167
168			`ifdef MUX4_ANDOR
169			`ifndef MUX_ANDOR
170			`define MUX_ANDOR
171			`endif
172			`endif
173
174			`ifdef MUX5_ANDOR
175			`ifndef MUX_ANDOR
176			`define MUX_ANDOR
177			`endif
178			`endif
179
180			`ifdef MUX6_ANDOR
181			`ifndef MUX_ANDOR
182			`define MUX_ANDOR
183			`endif
184			`endif
185
186			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
187			`ifndef CNT_BIN_CE
188			`define CNT_BIN_CE
189			`endif
190			`ifndef DPRAM_1R1W
191			`define DPRAM_1R1W
192			`endif
193			`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
194			`define CNT_BIN_CE_REW_Q_ZQ_L1
195			`endif
196			`endif
197
198			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
199			`ifndef CNT_LFSR_CE
200			`define CNT_LFSR_CE
201			`endif
202			`ifndef DPRAM_2R2W
203			`define DPRAM_2R2W
204			`endif
205			`ifndef CNT_BIN_CE_REW_ZQ_L1
206			`define CNT_BIN_CE_REW_ZQ_L1
207			`endif
208			`endif
209
210			`ifdef FIFO_2R2W_ASYNC_SIMPLEX
211			`ifndef CNT_GRAY_CE_BIN
212			`define CNT_GRAY_CE_BIN
213			`endif
214			`ifndef DPRAM_2R2W
215			`define DPRAM_2R2W
216			`endif
217			`ifndef FIFO_CMP_ASYNC
218			`define FIFO_CMP_ASYNC
219			`endif
220			`endif
221
222			`ifdef FIFO_2R2W_ASYNC
223			`ifndef FIFO_1R1W_ASYNC
224			`define FIFO_1R1W_ASYNC
225			`endif
226			`endif
227
228			`ifdef FIFO_1R1W_ASYNC
229			`ifndef CNT_GRAY_CE_BIN
230			`define CNT_GRAY_CE_BIN
231			`endif
232			`ifndef DPRAM_1R1W
233			`define DPRAM_1R1W
234			`endif
235			`ifndef FIFO_CMP_ASYNC
236			`define FIFO_CMP_ASYNC
237			`endif
238			`endif
239
240			`ifdef FIFO_CMP_ASYNC
241			`ifndef DFF_SR
242			`define DFF_SR
243			`endif
244			`ifndef DFF
245			`define DFF
246			`endif
247			`endif
248	48	unneback
249			`ifdef REG_FILE
250			`ifndef DPRAM_1R1W
251			`define DPRAM_1R1W
252			`endif
253			`endif

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Blame information for rev 77