OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Blame information for rev 111

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, memories                                 ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  memories                                                    ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more memory types                                    ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef ROM_INIT
44 5 unneback
/// ROM
45 40 unneback
`define MODULE rom_init
46
module `BASE`MODULE ( adr, q, clk);
47
`undef MODULE
48 5 unneback
 
49 7 unneback
   parameter data_width = 32;
50
   parameter addr_width = 8;
51 75 unneback
   parameter mem_size = 1<<addr_width;
52 7 unneback
   input [(addr_width-1):0]       adr;
53
   output reg [(data_width-1):0] q;
54
   input                         clk;
55 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
56 7 unneback
   parameter memory_file = "vl_rom.vmem";
57
   initial
58
     begin
59
        $readmemh(memory_file, rom);
60
     end
61
 
62
   always @ (posedge clk)
63
     q <= rom[adr];
64 5 unneback
 
65 7 unneback
endmodule
66 40 unneback
`endif
67 7 unneback
 
68 40 unneback
`ifdef RAM
69
`define MODULE ram
70 5 unneback
// Single port RAM
71 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
72
`undef MODULE
73 5 unneback
 
74
   parameter data_width = 32;
75
   parameter addr_width = 8;
76 75 unneback
   parameter mem_size = 1<<addr_width;
77 100 unneback
   parameter debug = 0;
78 5 unneback
   input [(data_width-1):0]      d;
79
   input [(addr_width-1):0]       adr;
80
   input                         we;
81 7 unneback
   output reg [(data_width-1):0] q;
82 5 unneback
   input                         clk;
83 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
84 100 unneback
 
85
    parameter memory_init = 0;
86
    parameter memory_file = "vl_ram.vmem";
87
    generate
88
    if (memory_init == 1) begin : init_mem
89
        initial
90
            $readmemh(memory_file, ram);
91
   end else if (memory_init == 2) begin : init_zero
92
        integer k;
93
        initial
94
            for (k = 0; k < mem_size; k = k + 1)
95
                ram[k] = 0;
96 7 unneback
   end
97
   endgenerate
98
 
99 100 unneback
    generate
100
    if (debug==1) begin : debug_we
101
        always @ (posedge clk)
102
        if (we)
103
            $display ("Value %h written at address %h : time %t", d, adr, $time);
104
 
105
    end
106
    endgenerate
107
 
108 5 unneback
   always @ (posedge clk)
109
   begin
110
   if (we)
111
     ram[adr] <= d;
112
   q <= ram[adr];
113
   end
114
 
115
endmodule
116 40 unneback
`endif
117 5 unneback
 
118 40 unneback
`ifdef RAM_BE
119
`define MODULE ram_be
120 91 unneback
module `BASE`MODULE ( d, adr, be, we, q, clk);
121 40 unneback
`undef MODULE
122
 
123 7 unneback
   parameter data_width = 32;
124 72 unneback
   parameter addr_width = 6;
125 75 unneback
   parameter mem_size = 1<<addr_width;
126 7 unneback
   input [(data_width-1):0]      d;
127
   input [(addr_width-1):0]       adr;
128 73 unneback
   input [(data_width/8)-1:0]    be;
129 7 unneback
   input                         we;
130
   output reg [(data_width-1):0] q;
131
   input                         clk;
132
 
133 84 unneback
 
134 65 unneback
//E2_ifdef SYSTEMVERILOG
135 95 unneback
    // use a multi-dimensional packed array
136
    //t o model individual bytes within the word
137
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
138 65 unneback
//E2_else
139 84 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
140
    wire [data_width/8-1:0] cke;
141 65 unneback
//E2_endif
142
 
143 100 unneback
    parameter memory_init = 0;
144
    parameter memory_file = "vl_ram.vmem";
145
    generate
146
    if (memory_init == 1) begin : init_mem
147
        initial
148
            $readmemh(memory_file, ram);
149
    end else if (memory_init == 2) begin : init_zero
150
        integer k;
151
        initial
152
            for (k = 0; k < mem_size; k = k + 1)
153
                ram[k] = 0;
154
    end
155 7 unneback
   endgenerate
156
 
157 60 unneback
//E2_ifdef SYSTEMVERILOG
158
 
159
always_ff@(posedge clk)
160
begin
161 95 unneback
    if(we) begin
162 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
163
        if(be[2]) ram[adr][2] <= d[23:16];
164
        if(be[1]) ram[adr][1] <= d[15:8];
165
        if(be[0]) ram[adr][0] <= d[7:0];
166 60 unneback
    end
167 90 unneback
        q <= ram[adr];
168 60 unneback
end
169
 
170
//E2_else
171
 
172 84 unneback
assign cke = {data_width/8{we}} & be;
173 7 unneback
   genvar i;
174 84 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
175 7 unneback
      always @ (posedge clk)
176 84 unneback
      if (cke[i])
177 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
178
   end
179
   endgenerate
180
 
181
   always @ (posedge clk)
182
      q <= ram[adr];
183
 
184 60 unneback
//E2_endif
185
 
186 93 unneback
//E2_ifdef verilator
187 84 unneback
   // Function to access RAM (for use by Verilator).
188
   function [31:0] get_mem;
189
      // verilator public
190 90 unneback
      input [addr_width-1:0]             addr;
191 84 unneback
      get_mem = ram[addr];
192
   endfunction // get_mem
193
 
194
   // Function to write RAM (for use by Verilator).
195
   function set_mem;
196
      // verilator public
197 90 unneback
      input [addr_width-1:0]             addr;
198
      input [data_width-1:0]             data;
199 84 unneback
      ram[addr] = data;
200
   endfunction // set_mem
201 93 unneback
//E2_endif
202 84 unneback
 
203 7 unneback
endmodule
204 40 unneback
`endif
205 7 unneback
 
206 40 unneback
`ifdef DPRAM_1R1W
207
`define MODULE dpram_1r1w
208
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
209
`undef MODULE
210 5 unneback
   parameter data_width = 32;
211
   parameter addr_width = 8;
212 75 unneback
   parameter mem_size = 1<<addr_width;
213 5 unneback
   input [(data_width-1):0]      d_a;
214
   input [(addr_width-1):0]       adr_a;
215
   input [(addr_width-1):0]       adr_b;
216
   input                         we_a;
217
   output [(data_width-1):0]      q_b;
218
   input                         clk_a, clk_b;
219
   reg [(addr_width-1):0]         adr_b_reg;
220 100 unneback
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
221 7 unneback
 
222 100 unneback
    parameter memory_init = 0;
223
    parameter memory_file = "vl_ram.vmem";
224
    parameter debug = 0;
225
 
226
    generate
227
    if (memory_init == 1) begin : init_mem
228
        initial
229
            $readmemh(memory_file, ram);
230
    end else if (memory_init == 2) begin : init_zero
231
        integer k;
232
        initial
233
            for (k = 0; k < mem_size; k = k + 1)
234
                ram[k] = 0;
235
    end
236 7 unneback
   endgenerate
237
 
238 100 unneback
    generate
239
    if (debug==1) begin : debug_we
240
        always @ (posedge clk_a)
241
        if (we_a)
242
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
243
 
244
    end
245
    endgenerate
246
 
247 5 unneback
   always @ (posedge clk_a)
248
   if (we_a)
249
     ram[adr_a] <= d_a;
250
   always @ (posedge clk_b)
251
   adr_b_reg <= adr_b;
252
   assign q_b = ram[adr_b_reg];
253 40 unneback
 
254 5 unneback
endmodule
255 40 unneback
`endif
256 5 unneback
 
257 40 unneback
`ifdef DPRAM_2R1W
258
`define MODULE dpram_2r1w
259
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
260
`undef MODULE
261
 
262 5 unneback
   parameter data_width = 32;
263
   parameter addr_width = 8;
264 75 unneback
   parameter mem_size = 1<<addr_width;
265 5 unneback
   input [(data_width-1):0]      d_a;
266
   input [(addr_width-1):0]       adr_a;
267
   input [(addr_width-1):0]       adr_b;
268
   input                         we_a;
269
   output [(data_width-1):0]      q_b;
270
   output reg [(data_width-1):0] q_a;
271
   input                         clk_a, clk_b;
272
   reg [(data_width-1):0]         q_b;
273 98 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
274 7 unneback
 
275 100 unneback
    parameter memory_init = 0;
276
    parameter memory_file = "vl_ram.vmem";
277
    parameter debug = 0;
278
 
279
    generate
280
    if (memory_init == 1) begin : init_mem
281
        initial
282
            $readmemh(memory_file, ram);
283
    end else if (memory_init == 2) begin : init_zero
284
        integer k;
285
        initial
286
            for (k = 0; k < mem_size; k = k + 1)
287
                ram[k] = 0;
288
    end
289 7 unneback
   endgenerate
290
 
291 100 unneback
    generate
292
    if (debug==1) begin : debug_we
293
        always @ (posedge clk_a)
294
        if (we_a)
295
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
296
 
297
    end
298
    endgenerate
299
 
300 5 unneback
   always @ (posedge clk_a)
301
     begin
302
        q_a <= ram[adr_a];
303
        if (we_a)
304
             ram[adr_a] <= d_a;
305
     end
306
   always @ (posedge clk_b)
307
          q_b <= ram[adr_b];
308
endmodule
309 40 unneback
`endif
310 5 unneback
 
311 100 unneback
`ifdef DPRAM_1R2W
312
`define MODULE dpram_1r2w
313
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
314
`undef MODULE
315
 
316
   parameter data_width = 32;
317
   parameter addr_width = 8;
318
   parameter mem_size = 1<<addr_width;
319
   input [(data_width-1):0]      d_a;
320
   input [(addr_width-1):0]       adr_a;
321
   input [(addr_width-1):0]       adr_b;
322
   input                         we_a;
323
   input [(data_width-1):0]       d_b;
324
   output reg [(data_width-1):0] q_a;
325
   input                         we_b;
326
   input                         clk_a, clk_b;
327
   reg [(data_width-1):0]         q_b;
328
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
329
 
330
    parameter memory_init = 0;
331
    parameter memory_file = "vl_ram.vmem";
332
    parameter debug = 0;
333
 
334
    generate
335
    if (memory_init == 1) begin : init_mem
336
        initial
337
            $readmemh(memory_file, ram);
338
    end else if (memory_init == 2) begin : init_zero
339
        integer k;
340
        initial
341
            for (k = 0; k < mem_size; k = k + 1)
342
                ram[k] = 0;
343
    end
344
   endgenerate
345
 
346
    generate
347
    if (debug==1) begin : debug_we
348
        always @ (posedge clk_a)
349
        if (we_a)
350
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
351
        always @ (posedge clk_b)
352
        if (we_b)
353
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
354
    end
355
    endgenerate
356
 
357
   always @ (posedge clk_a)
358
     begin
359
        q_a <= ram[adr_a];
360
        if (we_a)
361
             ram[adr_a] <= d_a;
362
     end
363
   always @ (posedge clk_b)
364
     begin
365
        if (we_b)
366
          ram[adr_b] <= d_b;
367
     end
368
endmodule
369
`endif
370
 
371 40 unneback
`ifdef DPRAM_2R2W
372
`define MODULE dpram_2r2w
373
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
374
`undef MODULE
375
 
376 5 unneback
   parameter data_width = 32;
377
   parameter addr_width = 8;
378 75 unneback
   parameter mem_size = 1<<addr_width;
379 5 unneback
   input [(data_width-1):0]      d_a;
380
   input [(addr_width-1):0]       adr_a;
381
   input [(addr_width-1):0]       adr_b;
382
   input                         we_a;
383
   output [(data_width-1):0]      q_b;
384
   input [(data_width-1):0]       d_b;
385
   output reg [(data_width-1):0] q_a;
386
   input                         we_b;
387
   input                         clk_a, clk_b;
388
   reg [(data_width-1):0]         q_b;
389 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
390 7 unneback
 
391 100 unneback
    parameter memory_init = 0;
392
    parameter memory_file = "vl_ram.vmem";
393
    parameter debug = 0;
394
 
395
    generate
396
    if (memory_init) begin : init_mem
397
        initial
398
            $readmemh(memory_file, ram);
399
    end else if (memory_init == 2) begin : init_zero
400
        integer k;
401
        initial
402
            for (k = 0; k < mem_size; k = k + 1)
403
                ram[k] = 0;
404
    end
405 7 unneback
   endgenerate
406
 
407 100 unneback
    generate
408
    if (debug==1) begin : debug_we
409
        always @ (posedge clk_a)
410
        if (we_a)
411
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
412
        always @ (posedge clk_b)
413
        if (we_b)
414
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
415
    end
416
    endgenerate
417
 
418 5 unneback
   always @ (posedge clk_a)
419
     begin
420
        q_a <= ram[adr_a];
421
        if (we_a)
422
             ram[adr_a] <= d_a;
423
     end
424
   always @ (posedge clk_b)
425
     begin
426
        q_b <= ram[adr_b];
427
        if (we_b)
428
          ram[adr_b] <= d_b;
429
     end
430
endmodule
431 40 unneback
`endif
432 5 unneback
 
433 83 unneback
 
434 75 unneback
`ifdef DPRAM_BE_2R2W
435
`define MODULE dpram_be_2r2w
436 92 unneback
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
437 75 unneback
`undef MODULE
438
 
439
   parameter a_data_width = 32;
440
   parameter a_addr_width = 8;
441 95 unneback
   parameter b_data_width = 64; //a_data_width;
442 91 unneback
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
443 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
444
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
445 91 unneback
 
446 100 unneback
   parameter memory_init = 0;
447 95 unneback
   parameter memory_file = "vl_ram.vmem";
448 100 unneback
   parameter debug = 0;
449 95 unneback
 
450 75 unneback
   input [(a_data_width-1):0]      d_a;
451 91 unneback
   input [(a_addr_width-1):0]       adr_a;
452
   input [(a_data_width/8-1):0]    be_a;
453
   input                           we_a;
454 75 unneback
   output reg [(a_data_width-1):0] q_a;
455 91 unneback
   input [(b_data_width-1):0]       d_b;
456
   input [(b_addr_width-1):0]       adr_b;
457 92 unneback
   input [(b_data_width/8-1):0]    be_b;
458
   input                           we_b;
459
   output reg [(b_data_width-1):0]          q_b;
460 91 unneback
   input                           clk_a, clk_b;
461 75 unneback
 
462 100 unneback
    generate
463
    if (debug==1) begin : debug_we
464
        always @ (posedge clk_a)
465
        if (we_a)
466
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
467
        always @ (posedge clk_b)
468
        if (we_b)
469
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
470
    end
471
    endgenerate
472
 
473
 
474 91 unneback
//E2_ifdef SYSTEMVERILOG
475
// use a multi-dimensional packed array
476
//to model individual bytes within the word
477
 
478 75 unneback
generate
479 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
480 75 unneback
 
481 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
482 95 unneback
 
483
    initial
484 100 unneback
        if (memory_init==1)
485 95 unneback
            $readmemh(memory_file, ram);
486 100 unneback
 
487
    integer k;
488
    initial
489
        if (memory_init==2)
490
            for (k = 0; k < mem_size; k = k + 1)
491
                ram[k] = 0;
492 91 unneback
 
493
    always_ff@(posedge clk_a)
494
    begin
495
        if(we_a) begin
496 100 unneback
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
497
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
498
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
499
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
500 91 unneback
        end
501
    end
502
 
503 92 unneback
    always@(posedge clk_a)
504
        q_a = ram[adr_a];
505 91 unneback
 
506
    always_ff@(posedge clk_b)
507 92 unneback
    begin
508
        if(we_b) begin
509 100 unneback
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
510
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
511
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
512
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
513 92 unneback
        end
514
    end
515 91 unneback
 
516 92 unneback
    always@(posedge clk_b)
517
        q_b = ram[adr_b];
518 91 unneback
 
519 75 unneback
end
520
endgenerate
521
 
522 95 unneback
generate
523
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
524
 
525 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
526 95 unneback
 
527
    initial
528 100 unneback
        if (memory_init==1)
529 95 unneback
            $readmemh(memory_file, ram);
530 100 unneback
 
531
    integer k;
532
    initial
533
        if (memory_init==2)
534
            for (k = 0; k < mem_size; k = k + 1)
535
                ram[k] = 0;
536 95 unneback
 
537
    always_ff@(posedge clk_a)
538
    begin
539
        if(we_a) begin
540
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
541
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
542
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
543
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
544
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
545
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
546
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
547
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
548
        end
549
    end
550
 
551
    always@(posedge clk_a)
552
        q_a = ram[adr_a];
553
 
554
    always_ff@(posedge clk_b)
555
    begin
556
        if(we_b) begin
557
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
558
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
559
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
560
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
561
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
562
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
563
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
564
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
565
        end
566
    end
567
 
568
    always@(posedge clk_b)
569
        q_b = ram[adr_b];
570
 
571
end
572
endgenerate
573
 
574
generate
575
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
576
logic [31:0] temp;
577
`define MODULE dpram_be_2r2w
578 111 unneback
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
579 95 unneback
`undef MODULE
580
dpram6464 (
581
    .d_a(d_a),
582
    .q_a(q_a),
583
    .adr_a(adr_a),
584
    .be_a(be_a),
585
    .we_a(we_a),
586
    .clk_a(clk_a),
587
    .d_b({d_b,d_b}),
588
    .q_b(temp),
589
    .adr_b(adr_b),
590
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
591
    .we_b(we_b),
592
    .clk_b(clk_b)
593
);
594
 
595 100 unneback
always @ (adr_b[0] or temp)
596 95 unneback
    if (adr_b[0])
597
        q_b = temp[31:16];
598
    else
599
        q_b = temp[15:0];
600
 
601
end
602
endgenerate
603
 
604
generate
605
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
606
logic [63:0] temp;
607
`define MODULE dpram_be_2r2w
608 111 unneback
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
609 95 unneback
`undef MODULE
610
dpram6464 (
611
    .d_a({d_a,d_a}),
612
    .q_a(temp),
613
    .adr_a(adr_a[a_addr_width-1:1]),
614
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
615
    .we_a(we_a),
616
    .clk_a(clk_a),
617
    .d_b(d_b),
618
    .q_b(q_b),
619
    .adr_b(adr_b),
620
    .be_b(be_b),
621
    .we_b(we_b),
622
    .clk_b(clk_b)
623
);
624
 
625 100 unneback
always @ (adr_a[0] or temp)
626 95 unneback
    if (adr_a[0])
627
        q_a = temp[63:32];
628
    else
629
        q_a = temp[31:0];
630
 
631
end
632
endgenerate
633
 
634 91 unneback
//E2_else
635 92 unneback
    // This modules requires SystemVerilog
636 98 unneback
    // at this point anyway
637 91 unneback
//E2_endif
638 75 unneback
endmodule
639
`endif
640
 
641 91 unneback
`ifdef CAM
642 5 unneback
// Content addresable memory, CAM
643 91 unneback
`endif
644 5 unneback
 
645 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
646 5 unneback
// FIFO
647 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
648
module `BASE`MODULE (
649
`undef MODULE
650 25 unneback
    d, wr, fifo_full,
651
    q, rd, fifo_empty,
652
    fill_level,
653
    clk, rst
654
    );
655
 
656
parameter data_width = 18;
657
parameter addr_width = 4;
658 5 unneback
 
659 25 unneback
// write side
660
input  [data_width-1:0] d;
661
input                   wr;
662
output                  fifo_full;
663
// read side
664
output [data_width-1:0] q;
665
input                   rd;
666
output                  fifo_empty;
667
// common
668
output [addr_width:0]   fill_level;
669
input rst, clk;
670
 
671
wire [addr_width:1] wadr, radr;
672
 
673 40 unneback
`define MODULE cnt_bin_ce
674
`BASE`MODULE
675 25 unneback
    # ( .length(addr_width))
676
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
677 40 unneback
`BASE`MODULE
678 25 unneback
    # (.length(addr_width))
679
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
680 40 unneback
`undef MODULE
681 25 unneback
 
682 40 unneback
`define MODULE dpram_1r1w
683
`BASE`MODULE
684 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
685
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
686 40 unneback
`undef MODULE
687 25 unneback
 
688 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
689
`BASE`MODULE
690 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
691 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
692 40 unneback
`undef MODULE
693 25 unneback
endmodule
694 40 unneback
`endif
695 25 unneback
 
696 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
697 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
698
// RAM is supposed to be larger than the two FIFOs
699
// LFSR counters used adr pointers
700 40 unneback
`define MODULE fifo_2r2w_sync_simplex
701
module `BASE`MODULE (
702
`undef MODULE
703 27 unneback
    // a side
704
    a_d, a_wr, a_fifo_full,
705
    a_q, a_rd, a_fifo_empty,
706
    a_fill_level,
707
    // b side
708
    b_d, b_wr, b_fifo_full,
709
    b_q, b_rd, b_fifo_empty,
710
    b_fill_level,
711
    // common
712
    clk, rst
713
    );
714
parameter data_width = 8;
715
parameter addr_width = 5;
716
parameter fifo_full_level = (1<<addr_width)-1;
717
 
718
// a side
719
input  [data_width-1:0] a_d;
720
input                   a_wr;
721
output                  a_fifo_full;
722
output [data_width-1:0] a_q;
723
input                   a_rd;
724
output                  a_fifo_empty;
725
output [addr_width-1:0] a_fill_level;
726
 
727
// b side
728
input  [data_width-1:0] b_d;
729
input                   b_wr;
730
output                  b_fifo_full;
731
output [data_width-1:0] b_q;
732
input                   b_rd;
733
output                  b_fifo_empty;
734
output [addr_width-1:0] b_fill_level;
735
 
736
input                   clk;
737
input                   rst;
738
 
739
// adr_gen
740
wire [addr_width:1] a_wadr, a_radr;
741
wire [addr_width:1] b_wadr, b_radr;
742
// dpram
743
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
744
 
745 40 unneback
`define MODULE cnt_lfsr_ce
746
`BASE`MODULE
747 27 unneback
    # ( .length(addr_width))
748
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
749
 
750 40 unneback
`BASE`MODULE
751 27 unneback
    # (.length(addr_width))
752
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
753
 
754 40 unneback
`BASE`MODULE
755 27 unneback
    # ( .length(addr_width))
756
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
757
 
758 40 unneback
`BASE`MODULE
759 27 unneback
    # (.length(addr_width))
760
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
761 40 unneback
`undef MODULE
762 27 unneback
 
763
// mux read or write adr to DPRAM
764
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
765
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
766
 
767 40 unneback
`define MODULE dpram_2r2w
768
`BASE`MODULE
769 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
770
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
771
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
772 40 unneback
`undef MODULE
773
 
774
`define MODULE cnt_bin_ce_rew_zq_l1
775
`BASE`MODULE
776 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
777 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
778
 
779 40 unneback
`BASE`MODULE
780 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
781 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
782 40 unneback
`undef MODULE
783 27 unneback
 
784
endmodule
785 40 unneback
`endif
786 27 unneback
 
787 40 unneback
`ifdef FIFO_CMP_ASYNC
788
`define MODULE fifo_cmp_async
789
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
790
`undef MODULE
791 5 unneback
 
792 11 unneback
   parameter addr_width = 4;
793
   parameter N = addr_width-1;
794 5 unneback
 
795
   parameter Q1 = 2'b00;
796
   parameter Q2 = 2'b01;
797
   parameter Q3 = 2'b11;
798
   parameter Q4 = 2'b10;
799
 
800
   parameter going_empty = 1'b0;
801
   parameter going_full  = 1'b1;
802
 
803
   input [N:0]  wptr, rptr;
804 14 unneback
   output       fifo_empty;
805 5 unneback
   output       fifo_full;
806
   input        wclk, rclk, rst;
807
 
808
`ifndef GENERATE_DIRECTION_AS_LATCH
809
   wire direction;
810
`endif
811
`ifdef GENERATE_DIRECTION_AS_LATCH
812
   reg direction;
813
`endif
814
   reg  direction_set, direction_clr;
815
 
816
   wire async_empty, async_full;
817
   wire fifo_full2;
818 14 unneback
   wire fifo_empty2;
819 5 unneback
 
820
   // direction_set
821
   always @ (wptr[N:N-1] or rptr[N:N-1])
822
     case ({wptr[N:N-1],rptr[N:N-1]})
823
       {Q1,Q2} : direction_set <= 1'b1;
824
       {Q2,Q3} : direction_set <= 1'b1;
825
       {Q3,Q4} : direction_set <= 1'b1;
826
       {Q4,Q1} : direction_set <= 1'b1;
827
       default : direction_set <= 1'b0;
828
     endcase
829
 
830
   // direction_clear
831
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
832
     if (rst)
833
       direction_clr <= 1'b1;
834
     else
835
       case ({wptr[N:N-1],rptr[N:N-1]})
836
         {Q2,Q1} : direction_clr <= 1'b1;
837
         {Q3,Q2} : direction_clr <= 1'b1;
838
         {Q4,Q3} : direction_clr <= 1'b1;
839
         {Q1,Q4} : direction_clr <= 1'b1;
840
         default : direction_clr <= 1'b0;
841
       endcase
842
 
843 40 unneback
`define MODULE dff_sr
844 5 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
845 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
846 5 unneback
`endif
847
 
848
`ifdef GENERATE_DIRECTION_AS_LATCH
849
   always @ (posedge direction_set or posedge direction_clr)
850
     if (direction_clr)
851
       direction <= going_empty;
852
     else
853
       direction <= going_full;
854
`endif
855
 
856
   assign async_empty = (wptr == rptr) && (direction==going_empty);
857
   assign async_full  = (wptr == rptr) && (direction==going_full);
858
 
859 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
860
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
861
`undef MODULE
862 5 unneback
 
863
/*
864
   always @ (posedge wclk or posedge rst or posedge async_full)
865
     if (rst)
866
       {fifo_full, fifo_full2} <= 2'b00;
867
     else if (async_full)
868
       {fifo_full, fifo_full2} <= 2'b11;
869
     else
870
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
871
*/
872 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
873 5 unneback
     if (async_empty)
874
       {fifo_empty, fifo_empty2} <= 2'b11;
875
     else
876 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
877 40 unneback
`define MODULE dff
878
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
879
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
880
`undef MODULE
881 25 unneback
endmodule // async_compb
882 40 unneback
`endif
883 5 unneback
 
884 40 unneback
`ifdef FIFO_1R1W_ASYNC
885
`define MODULE fifo_1r1w_async
886
module `BASE`MODULE (
887
`undef MODULE
888 5 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
889
    q, rd, fifo_empty, rd_clk, rd_rst
890
    );
891
 
892
parameter data_width = 18;
893
parameter addr_width = 4;
894
 
895
// write side
896
input  [data_width-1:0] d;
897
input                   wr;
898
output                  fifo_full;
899
input                   wr_clk;
900
input                   wr_rst;
901
// read side
902
output [data_width-1:0] q;
903
input                   rd;
904
output                  fifo_empty;
905
input                   rd_clk;
906
input                   rd_rst;
907
 
908
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
909 23 unneback
 
910 40 unneback
`define MODULE cnt_gray_ce_bin
911
`BASE`MODULE
912 5 unneback
    # ( .length(addr_width))
913
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
914
 
915 40 unneback
`BASE`MODULE
916 5 unneback
    # (.length(addr_width))
917 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
918 40 unneback
`undef MODULE
919 5 unneback
 
920 40 unneback
`define MODULE dpram_1r1w
921
`BASE`MODULE
922 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
923
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
924 40 unneback
`undef MODULE
925 5 unneback
 
926 40 unneback
`define MODULE fifo_cmp_async
927
`BASE`MODULE
928 5 unneback
    # (.addr_width(addr_width))
929
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
930 40 unneback
`undef MODULE
931 5 unneback
 
932
endmodule
933 40 unneback
`endif
934 5 unneback
 
935 40 unneback
`ifdef FIFO_2R2W_ASYNC
936
`define MODULE fifo_2r2w_async
937
module `BASE`MODULE (
938
`undef MODULE
939 5 unneback
    // a side
940
    a_d, a_wr, a_fifo_full,
941
    a_q, a_rd, a_fifo_empty,
942
    a_clk, a_rst,
943
    // b side
944
    b_d, b_wr, b_fifo_full,
945
    b_q, b_rd, b_fifo_empty,
946
    b_clk, b_rst
947
    );
948
 
949
parameter data_width = 18;
950
parameter addr_width = 4;
951
 
952
// a side
953
input  [data_width-1:0] a_d;
954
input                   a_wr;
955
output                  a_fifo_full;
956
output [data_width-1:0] a_q;
957
input                   a_rd;
958
output                  a_fifo_empty;
959
input                   a_clk;
960
input                   a_rst;
961
 
962
// b side
963
input  [data_width-1:0] b_d;
964
input                   b_wr;
965
output                  b_fifo_full;
966
output [data_width-1:0] b_q;
967
input                   b_rd;
968
output                  b_fifo_empty;
969
input                   b_clk;
970
input                   b_rst;
971
 
972 40 unneback
`define MODULE fifo_1r1w_async
973
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
974 5 unneback
vl_fifo_1r1w_async_a (
975
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
976
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
977
    );
978
 
979 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
980 5 unneback
vl_fifo_1r1w_async_b (
981
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
982
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
983
    );
984 40 unneback
`undef MODULE
985
 
986 5 unneback
endmodule
987 40 unneback
`endif
988 5 unneback
 
989 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
990
`define MODULE fifo_2r2w_async_simplex
991
module `BASE`MODULE (
992
`undef MODULE
993 5 unneback
    // a side
994
    a_d, a_wr, a_fifo_full,
995
    a_q, a_rd, a_fifo_empty,
996
    a_clk, a_rst,
997
    // b side
998
    b_d, b_wr, b_fifo_full,
999
    b_q, b_rd, b_fifo_empty,
1000
    b_clk, b_rst
1001
    );
1002
 
1003
parameter data_width = 18;
1004
parameter addr_width = 4;
1005
 
1006
// a side
1007
input  [data_width-1:0] a_d;
1008
input                   a_wr;
1009
output                  a_fifo_full;
1010
output [data_width-1:0] a_q;
1011
input                   a_rd;
1012
output                  a_fifo_empty;
1013
input                   a_clk;
1014
input                   a_rst;
1015
 
1016
// b side
1017
input  [data_width-1:0] b_d;
1018
input                   b_wr;
1019
output                  b_fifo_full;
1020
output [data_width-1:0] b_q;
1021
input                   b_rd;
1022
output                  b_fifo_empty;
1023
input                   b_clk;
1024
input                   b_rst;
1025
 
1026
// adr_gen
1027
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1028
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1029
// dpram
1030
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1031
 
1032 40 unneback
`define MODULE cnt_gray_ce_bin
1033
`BASE`MODULE
1034 5 unneback
    # ( .length(addr_width))
1035
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1036
 
1037 40 unneback
`BASE`MODULE
1038 5 unneback
    # (.length(addr_width))
1039
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1040
 
1041 40 unneback
`BASE`MODULE
1042 5 unneback
    # ( .length(addr_width))
1043
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1044
 
1045 40 unneback
`BASE`MODULE
1046 5 unneback
    # (.length(addr_width))
1047
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1048 40 unneback
`undef MODULE
1049 5 unneback
 
1050
// mux read or write adr to DPRAM
1051
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1052
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1053
 
1054 40 unneback
`define MODULE dpram_2r2w
1055
`BASE`MODULE
1056 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1057
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1058
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1059 40 unneback
`undef MODULE
1060 5 unneback
 
1061 40 unneback
`define MODULE fifo_cmp_async
1062
`BASE`MODULE
1063 5 unneback
    # (.addr_width(addr_width))
1064
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1065
 
1066 40 unneback
`BASE`MODULE
1067 5 unneback
    # (.addr_width(addr_width))
1068
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1069 40 unneback
`undef MODULE
1070 5 unneback
 
1071
endmodule
1072 40 unneback
`endif
1073 48 unneback
 
1074
`ifdef REG_FILE
1075
`define MODULE reg_file
1076
module `BASE`MODULE (
1077
`undef MODULE
1078
    a1, a2, a3, wd3, we3, rd1, rd2, clk
1079
);
1080
parameter data_width = 32;
1081
parameter addr_width = 5;
1082
input [addr_width-1:0] a1, a2, a3;
1083
input [data_width-1:0] wd3;
1084
input we3;
1085
output [data_width-1:0] rd1, rd2;
1086
input clk;
1087
 
1088
`ifdef ACTEL
1089
reg [data_width-1:0] wd3_reg;
1090
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
1091
reg we3_reg;
1092 98 unneback
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
1093
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
1094 48 unneback
always @ (posedge clk or posedge rst)
1095
if (rst)
1096
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
1097
else
1098
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
1099
 
1100
    always @ (negedge clk)
1101
    if (we3_reg)
1102
        ram1[a3_reg] <= wd3;
1103
    always @ (posedge clk)
1104
        a1_reg <= a1;
1105
    assign rd1 = ram1[a1_reg];
1106
 
1107
    always @ (negedge clk)
1108
    if (we3_reg)
1109
        ram2[a3_reg] <= wd3;
1110
    always @ (posedge clk)
1111
        a2_reg <= a2;
1112
    assign rd2 = ram2[a2_reg];
1113
 
1114
`else
1115
 
1116
`define MODULE dpram_1r1w
1117
`BASE`MODULE
1118
    # ( .data_width(data_width), .addr_width(addr_width))
1119
    ram1 (
1120
        .d_a(wd3),
1121
        .adr_a(a3),
1122
        .we_a(we3),
1123
        .clk_a(clk),
1124
        .q_b(rd1),
1125
        .adr_b(a1),
1126
        .clk_b(clk) );
1127
 
1128
`BASE`MODULE
1129
    # ( .data_width(data_width), .addr_width(addr_width))
1130
    ram2 (
1131
        .d_a(wd3),
1132
        .adr_a(a3),
1133
        .we_a(we3),
1134
        .clk_a(clk),
1135
        .q_b(rd2),
1136
        .adr_b(a2),
1137
        .clk_b(clk) );
1138
`undef MODULE
1139
 
1140
`endif
1141
 
1142
endmodule
1143
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.