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1 5 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, memories                                 ////
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////                                                              ////
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////  Description                                                 ////
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////  memories                                                    ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more memory types                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef ROM_INIT
44 5 unneback
/// ROM
45 40 unneback
`define MODULE rom_init
46
module `BASE`MODULE ( adr, q, clk);
47
`undef MODULE
48 5 unneback
 
49 7 unneback
   parameter data_width = 32;
50
   parameter addr_width = 8;
51
   input [(addr_width-1):0]       adr;
52
   output reg [(data_width-1):0] q;
53
   input                         clk;
54
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
55
   parameter memory_file = "vl_rom.vmem";
56
   initial
57
     begin
58
        $readmemh(memory_file, rom);
59
     end
60
 
61
   always @ (posedge clk)
62
     q <= rom[adr];
63 5 unneback
 
64 7 unneback
endmodule
65 40 unneback
`endif
66 7 unneback
 
67 40 unneback
`ifdef RAM
68
`define MODULE ram
69 5 unneback
// Single port RAM
70 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
71
`undef MODULE
72 5 unneback
 
73
   parameter data_width = 32;
74
   parameter addr_width = 8;
75
   input [(data_width-1):0]      d;
76
   input [(addr_width-1):0]       adr;
77
   input                         we;
78 7 unneback
   output reg [(data_width-1):0] q;
79 5 unneback
   input                         clk;
80
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
81 7 unneback
   parameter init = 0;
82
   parameter memory_file = "vl_ram.vmem";
83
   generate if (init) begin : init_mem
84
   initial
85
     begin
86
        $readmemh(memory_file, ram);
87
     end
88
   end
89
   endgenerate
90
 
91 5 unneback
   always @ (posedge clk)
92
   begin
93
   if (we)
94
     ram[adr] <= d;
95
   q <= ram[adr];
96
   end
97
 
98
endmodule
99 40 unneback
`endif
100 5 unneback
 
101 40 unneback
`ifdef RAM_BE
102
`define MODULE ram_be
103
module `BASE`MODULE ( d, adr, be, we, q, clk);
104
`undef MODULE
105
 
106 7 unneback
   parameter data_width = 32;
107
   parameter addr_width = 8;
108
   input [(data_width-1):0]      d;
109
   input [(addr_width-1):0]       adr;
110
   input [(addr_width/4)-1:0]    be;
111
   input                         we;
112
   output reg [(data_width-1):0] q;
113
   input                         clk;
114
 
115 65 unneback
//E2_ifdef SYSTEMVERILOG
116
   logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
117
//E2_else
118 7 unneback
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
119 65 unneback
//E2_endif
120
 
121 60 unneback
   parameter memory_init = 0;
122 7 unneback
   parameter memory_file = "vl_ram.vmem";
123 60 unneback
   generate if (memory_init) begin : init_mem
124 7 unneback
   initial
125
     begin
126
        $readmemh(memory_file, ram);
127
     end
128
   end
129
   endgenerate
130
 
131 60 unneback
//E2_ifdef SYSTEMVERILOG
132
// use a multi-dimensional packed array
133
//to model individual bytes within the word
134
 
135
always_ff@(posedge clk)
136
begin
137
    if(we) begin // note: we should have a for statement to support any bus width
138 65 unneback
        if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
139
        if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
140
        if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
141
        if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
142 60 unneback
    end
143 65 unneback
    q <= ram[adr];
144 60 unneback
end
145
 
146
//E2_else
147
 
148 7 unneback
   genvar i;
149
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
150
      always @ (posedge clk)
151
      if (we & be[i])
152
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
153
   end
154
   endgenerate
155
 
156
   always @ (posedge clk)
157
      q <= ram[adr];
158
 
159 60 unneback
//E2_endif
160
 
161 7 unneback
endmodule
162 40 unneback
`endif
163 7 unneback
 
164 5 unneback
`ifdef ACTEL
165 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
166 5 unneback
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
167
`else
168
        `define SYN
169
`endif
170
 
171 40 unneback
`ifdef DPRAM_1R1W
172
`define MODULE dpram_1r1w
173
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
174
`undef MODULE
175 5 unneback
   parameter data_width = 32;
176
   parameter addr_width = 8;
177
   input [(data_width-1):0]      d_a;
178
   input [(addr_width-1):0]       adr_a;
179
   input [(addr_width-1):0]       adr_b;
180
   input                         we_a;
181
   output [(data_width-1):0]      q_b;
182
   input                         clk_a, clk_b;
183
   reg [(addr_width-1):0]         adr_b_reg;
184
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
185 7 unneback
 
186
   parameter init = 0;
187
   parameter memory_file = "vl_ram.vmem";
188
   generate if (init) begin : init_mem
189
   initial
190
     begin
191
        $readmemh(memory_file, ram);
192
     end
193
   end
194
   endgenerate
195
 
196 5 unneback
   always @ (posedge clk_a)
197
   if (we_a)
198
     ram[adr_a] <= d_a;
199
   always @ (posedge clk_b)
200
   adr_b_reg <= adr_b;
201
   assign q_b = ram[adr_b_reg];
202 40 unneback
 
203 5 unneback
endmodule
204 40 unneback
`endif
205 5 unneback
 
206 40 unneback
`ifdef DPRAM_2R1W
207
`define MODULE dpram_2r1w
208
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
209
`undef MODULE
210
 
211 5 unneback
   parameter data_width = 32;
212
   parameter addr_width = 8;
213
   input [(data_width-1):0]      d_a;
214
   input [(addr_width-1):0]       adr_a;
215
   input [(addr_width-1):0]       adr_b;
216
   input                         we_a;
217
   output [(data_width-1):0]      q_b;
218
   output reg [(data_width-1):0] q_a;
219
   input                         clk_a, clk_b;
220
   reg [(data_width-1):0]         q_b;
221
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
222 7 unneback
 
223
   parameter init = 0;
224
   parameter memory_file = "vl_ram.vmem";
225
   generate if (init) begin : init_mem
226
   initial
227
     begin
228
        $readmemh(memory_file, ram);
229
     end
230
   end
231
   endgenerate
232
 
233 5 unneback
   always @ (posedge clk_a)
234
     begin
235
        q_a <= ram[adr_a];
236
        if (we_a)
237
             ram[adr_a] <= d_a;
238
     end
239
   always @ (posedge clk_b)
240
          q_b <= ram[adr_b];
241
endmodule
242 40 unneback
`endif
243 5 unneback
 
244 40 unneback
`ifdef DPRAM_2R2W
245
`define MODULE dpram_2r2w
246
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
247
`undef MODULE
248
 
249 5 unneback
   parameter data_width = 32;
250
   parameter addr_width = 8;
251
   input [(data_width-1):0]      d_a;
252
   input [(addr_width-1):0]       adr_a;
253
   input [(addr_width-1):0]       adr_b;
254
   input                         we_a;
255
   output [(data_width-1):0]      q_b;
256
   input [(data_width-1):0]       d_b;
257
   output reg [(data_width-1):0] q_a;
258
   input                         we_b;
259
   input                         clk_a, clk_b;
260
   reg [(data_width-1):0]         q_b;
261
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
262 7 unneback
 
263
   parameter init = 0;
264
   parameter memory_file = "vl_ram.vmem";
265
   generate if (init) begin : init_mem
266
   initial
267
     begin
268
        $readmemh(memory_file, ram);
269
     end
270
   end
271
   endgenerate
272
 
273 5 unneback
   always @ (posedge clk_a)
274
     begin
275
        q_a <= ram[adr_a];
276
        if (we_a)
277
             ram[adr_a] <= d_a;
278
     end
279
   always @ (posedge clk_b)
280
     begin
281
        q_b <= ram[adr_b];
282
        if (we_b)
283
          ram[adr_b] <= d_b;
284
     end
285
endmodule
286 40 unneback
`endif
287 5 unneback
 
288
// Content addresable memory, CAM
289
 
290 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
291 5 unneback
// FIFO
292 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
293
module `BASE`MODULE (
294
`undef MODULE
295 25 unneback
    d, wr, fifo_full,
296
    q, rd, fifo_empty,
297
    fill_level,
298
    clk, rst
299
    );
300
 
301
parameter data_width = 18;
302
parameter addr_width = 4;
303 5 unneback
 
304 25 unneback
// write side
305
input  [data_width-1:0] d;
306
input                   wr;
307
output                  fifo_full;
308
// read side
309
output [data_width-1:0] q;
310
input                   rd;
311
output                  fifo_empty;
312
// common
313
output [addr_width:0]   fill_level;
314
input rst, clk;
315
 
316
wire [addr_width:1] wadr, radr;
317
 
318 40 unneback
`define MODULE cnt_bin_ce
319
`BASE`MODULE
320 25 unneback
    # ( .length(addr_width))
321
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
322 40 unneback
`BASE`MODULE
323 25 unneback
    # (.length(addr_width))
324
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
325 40 unneback
`undef MODULE
326 25 unneback
 
327 40 unneback
`define MODULE dpram_1r1w
328
`BASE`MODULE
329 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
330
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
331 40 unneback
`undef MODULE
332 25 unneback
 
333 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
334
`BASE`MODULE
335 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
336 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
337 40 unneback
`undef MODULE
338 25 unneback
endmodule
339 40 unneback
`endif
340 25 unneback
 
341 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
342 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
343
// RAM is supposed to be larger than the two FIFOs
344
// LFSR counters used adr pointers
345 40 unneback
`define MODULE fifo_2r2w_sync_simplex
346
module `BASE`MODULE (
347
`undef MODULE
348 27 unneback
    // a side
349
    a_d, a_wr, a_fifo_full,
350
    a_q, a_rd, a_fifo_empty,
351
    a_fill_level,
352
    // b side
353
    b_d, b_wr, b_fifo_full,
354
    b_q, b_rd, b_fifo_empty,
355
    b_fill_level,
356
    // common
357
    clk, rst
358
    );
359
parameter data_width = 8;
360
parameter addr_width = 5;
361
parameter fifo_full_level = (1<<addr_width)-1;
362
 
363
// a side
364
input  [data_width-1:0] a_d;
365
input                   a_wr;
366
output                  a_fifo_full;
367
output [data_width-1:0] a_q;
368
input                   a_rd;
369
output                  a_fifo_empty;
370
output [addr_width-1:0] a_fill_level;
371
 
372
// b side
373
input  [data_width-1:0] b_d;
374
input                   b_wr;
375
output                  b_fifo_full;
376
output [data_width-1:0] b_q;
377
input                   b_rd;
378
output                  b_fifo_empty;
379
output [addr_width-1:0] b_fill_level;
380
 
381
input                   clk;
382
input                   rst;
383
 
384
// adr_gen
385
wire [addr_width:1] a_wadr, a_radr;
386
wire [addr_width:1] b_wadr, b_radr;
387
// dpram
388
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
389
 
390 40 unneback
`define MODULE cnt_lfsr_ce
391
`BASE`MODULE
392 27 unneback
    # ( .length(addr_width))
393
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
394
 
395 40 unneback
`BASE`MODULE
396 27 unneback
    # (.length(addr_width))
397
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
398
 
399 40 unneback
`BASE`MODULE
400 27 unneback
    # ( .length(addr_width))
401
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
402
 
403 40 unneback
`BASE`MODULE
404 27 unneback
    # (.length(addr_width))
405
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
406 40 unneback
`undef MODULE
407 27 unneback
 
408
// mux read or write adr to DPRAM
409
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
410
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
411
 
412 40 unneback
`define MODULE dpram_2r2w
413
`BASE`MODULE
414 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
415
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
416
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
417 40 unneback
`undef MODULE
418
 
419
`define MODULE cnt_bin_ce_rew_zq_l1
420
`BASE`MODULE
421 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
422 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
423
 
424 40 unneback
`BASE`MODULE
425 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
426 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
427 40 unneback
`undef MODULE
428 27 unneback
 
429
endmodule
430 40 unneback
`endif
431 27 unneback
 
432 40 unneback
`ifdef FIFO_CMP_ASYNC
433
`define MODULE fifo_cmp_async
434
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
435
`undef MODULE
436 5 unneback
 
437 11 unneback
   parameter addr_width = 4;
438
   parameter N = addr_width-1;
439 5 unneback
 
440
   parameter Q1 = 2'b00;
441
   parameter Q2 = 2'b01;
442
   parameter Q3 = 2'b11;
443
   parameter Q4 = 2'b10;
444
 
445
   parameter going_empty = 1'b0;
446
   parameter going_full  = 1'b1;
447
 
448
   input [N:0]  wptr, rptr;
449 14 unneback
   output       fifo_empty;
450 5 unneback
   output       fifo_full;
451
   input        wclk, rclk, rst;
452
 
453
`ifndef GENERATE_DIRECTION_AS_LATCH
454
   wire direction;
455
`endif
456
`ifdef GENERATE_DIRECTION_AS_LATCH
457
   reg direction;
458
`endif
459
   reg  direction_set, direction_clr;
460
 
461
   wire async_empty, async_full;
462
   wire fifo_full2;
463 14 unneback
   wire fifo_empty2;
464 5 unneback
 
465
   // direction_set
466
   always @ (wptr[N:N-1] or rptr[N:N-1])
467
     case ({wptr[N:N-1],rptr[N:N-1]})
468
       {Q1,Q2} : direction_set <= 1'b1;
469
       {Q2,Q3} : direction_set <= 1'b1;
470
       {Q3,Q4} : direction_set <= 1'b1;
471
       {Q4,Q1} : direction_set <= 1'b1;
472
       default : direction_set <= 1'b0;
473
     endcase
474
 
475
   // direction_clear
476
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
477
     if (rst)
478
       direction_clr <= 1'b1;
479
     else
480
       case ({wptr[N:N-1],rptr[N:N-1]})
481
         {Q2,Q1} : direction_clr <= 1'b1;
482
         {Q3,Q2} : direction_clr <= 1'b1;
483
         {Q4,Q3} : direction_clr <= 1'b1;
484
         {Q1,Q4} : direction_clr <= 1'b1;
485
         default : direction_clr <= 1'b0;
486
       endcase
487
 
488 40 unneback
`define MODULE dff_sr
489 5 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
490 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
491 5 unneback
`endif
492
 
493
`ifdef GENERATE_DIRECTION_AS_LATCH
494
   always @ (posedge direction_set or posedge direction_clr)
495
     if (direction_clr)
496
       direction <= going_empty;
497
     else
498
       direction <= going_full;
499
`endif
500
 
501
   assign async_empty = (wptr == rptr) && (direction==going_empty);
502
   assign async_full  = (wptr == rptr) && (direction==going_full);
503
 
504 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
505
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
506
`undef MODULE
507 5 unneback
 
508
/*
509
   always @ (posedge wclk or posedge rst or posedge async_full)
510
     if (rst)
511
       {fifo_full, fifo_full2} <= 2'b00;
512
     else if (async_full)
513
       {fifo_full, fifo_full2} <= 2'b11;
514
     else
515
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
516
*/
517 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
518 5 unneback
     if (async_empty)
519
       {fifo_empty, fifo_empty2} <= 2'b11;
520
     else
521 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
522 40 unneback
`define MODULE dff
523
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
524
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
525
`undef MODULE
526 25 unneback
endmodule // async_compb
527 40 unneback
`endif
528 5 unneback
 
529 40 unneback
`ifdef FIFO_1R1W_ASYNC
530
`define MODULE fifo_1r1w_async
531
module `BASE`MODULE (
532
`undef MODULE
533 5 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
534
    q, rd, fifo_empty, rd_clk, rd_rst
535
    );
536
 
537
parameter data_width = 18;
538
parameter addr_width = 4;
539
 
540
// write side
541
input  [data_width-1:0] d;
542
input                   wr;
543
output                  fifo_full;
544
input                   wr_clk;
545
input                   wr_rst;
546
// read side
547
output [data_width-1:0] q;
548
input                   rd;
549
output                  fifo_empty;
550
input                   rd_clk;
551
input                   rd_rst;
552
 
553
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
554 23 unneback
 
555 40 unneback
`define MODULE cnt_gray_ce_bin
556
`BASE`MODULE
557 5 unneback
    # ( .length(addr_width))
558
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
559
 
560 40 unneback
`BASE`MODULE
561 5 unneback
    # (.length(addr_width))
562 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
563 40 unneback
`undef MODULE
564 5 unneback
 
565 40 unneback
`define MODULE dpram_1r1w
566
`BASE`MODULE
567 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
568
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
569 40 unneback
`undef MODULE
570 5 unneback
 
571 40 unneback
`define MODULE fifo_cmp_async
572
`BASE`MODULE
573 5 unneback
    # (.addr_width(addr_width))
574
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
575 40 unneback
`undef MODULE
576 5 unneback
 
577
endmodule
578 40 unneback
`endif
579 5 unneback
 
580 40 unneback
`ifdef FIFO_2R2W_ASYNC
581
`define MODULE fifo_2r2w_async
582
module `BASE`MODULE (
583
`undef MODULE
584 5 unneback
    // a side
585
    a_d, a_wr, a_fifo_full,
586
    a_q, a_rd, a_fifo_empty,
587
    a_clk, a_rst,
588
    // b side
589
    b_d, b_wr, b_fifo_full,
590
    b_q, b_rd, b_fifo_empty,
591
    b_clk, b_rst
592
    );
593
 
594
parameter data_width = 18;
595
parameter addr_width = 4;
596
 
597
// a side
598
input  [data_width-1:0] a_d;
599
input                   a_wr;
600
output                  a_fifo_full;
601
output [data_width-1:0] a_q;
602
input                   a_rd;
603
output                  a_fifo_empty;
604
input                   a_clk;
605
input                   a_rst;
606
 
607
// b side
608
input  [data_width-1:0] b_d;
609
input                   b_wr;
610
output                  b_fifo_full;
611
output [data_width-1:0] b_q;
612
input                   b_rd;
613
output                  b_fifo_empty;
614
input                   b_clk;
615
input                   b_rst;
616
 
617 40 unneback
`define MODULE fifo_1r1w_async
618
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
619 5 unneback
vl_fifo_1r1w_async_a (
620
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
621
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
622
    );
623
 
624 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
625 5 unneback
vl_fifo_1r1w_async_b (
626
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
627
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
628
    );
629 40 unneback
`undef MODULE
630
 
631 5 unneback
endmodule
632 40 unneback
`endif
633 5 unneback
 
634 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
635
`define MODULE fifo_2r2w_async_simplex
636
module `BASE`MODULE (
637
`undef MODULE
638 5 unneback
    // a side
639
    a_d, a_wr, a_fifo_full,
640
    a_q, a_rd, a_fifo_empty,
641
    a_clk, a_rst,
642
    // b side
643
    b_d, b_wr, b_fifo_full,
644
    b_q, b_rd, b_fifo_empty,
645
    b_clk, b_rst
646
    );
647
 
648
parameter data_width = 18;
649
parameter addr_width = 4;
650
 
651
// a side
652
input  [data_width-1:0] a_d;
653
input                   a_wr;
654
output                  a_fifo_full;
655
output [data_width-1:0] a_q;
656
input                   a_rd;
657
output                  a_fifo_empty;
658
input                   a_clk;
659
input                   a_rst;
660
 
661
// b side
662
input  [data_width-1:0] b_d;
663
input                   b_wr;
664
output                  b_fifo_full;
665
output [data_width-1:0] b_q;
666
input                   b_rd;
667
output                  b_fifo_empty;
668
input                   b_clk;
669
input                   b_rst;
670
 
671
// adr_gen
672
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
673
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
674
// dpram
675
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
676
 
677 40 unneback
`define MODULE cnt_gray_ce_bin
678
`BASE`MODULE
679 5 unneback
    # ( .length(addr_width))
680
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
681
 
682 40 unneback
`BASE`MODULE
683 5 unneback
    # (.length(addr_width))
684
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
685
 
686 40 unneback
`BASE`MODULE
687 5 unneback
    # ( .length(addr_width))
688
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
689
 
690 40 unneback
`BASE`MODULE
691 5 unneback
    # (.length(addr_width))
692
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
693 40 unneback
`undef MODULE
694 5 unneback
 
695
// mux read or write adr to DPRAM
696
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
697
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
698
 
699 40 unneback
`define MODULE dpram_2r2w
700
`BASE`MODULE
701 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
702
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
703
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
704 40 unneback
`undef MODULE
705 5 unneback
 
706 40 unneback
`define MODULE fifo_cmp_async
707
`BASE`MODULE
708 5 unneback
    # (.addr_width(addr_width))
709
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
710
 
711 40 unneback
`BASE`MODULE
712 5 unneback
    # (.addr_width(addr_width))
713
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
714 40 unneback
`undef MODULE
715 5 unneback
 
716
endmodule
717 40 unneback
`endif
718 48 unneback
 
719
`ifdef REG_FILE
720
`define MODULE reg_file
721
module `BASE`MODULE (
722
`undef MODULE
723
    a1, a2, a3, wd3, we3, rd1, rd2, clk
724
);
725
parameter data_width = 32;
726
parameter addr_width = 5;
727
input [addr_width-1:0] a1, a2, a3;
728
input [data_width-1:0] wd3;
729
input we3;
730
output [data_width-1:0] rd1, rd2;
731
input clk;
732
 
733
`ifdef ACTEL
734
reg [data_width-1:0] wd3_reg;
735
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
736
reg we3_reg;
737
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
738
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
739
always @ (posedge clk or posedge rst)
740
if (rst)
741
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
742
else
743
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
744
 
745
    always @ (negedge clk)
746
    if (we3_reg)
747
        ram1[a3_reg] <= wd3;
748
    always @ (posedge clk)
749
        a1_reg <= a1;
750
    assign rd1 = ram1[a1_reg];
751
 
752
    always @ (negedge clk)
753
    if (we3_reg)
754
        ram2[a3_reg] <= wd3;
755
    always @ (posedge clk)
756
        a2_reg <= a2;
757
    assign rd2 = ram2[a2_reg];
758
 
759
`else
760
 
761
`define MODULE dpram_1r1w
762
`BASE`MODULE
763
    # ( .data_width(data_width), .addr_width(addr_width))
764
    ram1 (
765
        .d_a(wd3),
766
        .adr_a(a3),
767
        .we_a(we3),
768
        .clk_a(clk),
769
        .q_b(rd1),
770
        .adr_b(a1),
771
        .clk_b(clk) );
772
 
773
`BASE`MODULE
774
    # ( .data_width(data_width), .addr_width(addr_width))
775
    ram2 (
776
        .d_a(wd3),
777
        .adr_a(a3),
778
        .we_a(we3),
779
        .clk_a(clk),
780
        .q_b(rd2),
781
        .adr_b(a2),
782
        .clk_b(clk) );
783
`undef MODULE
784
 
785
`endif
786
 
787
endmodule
788
`endif

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