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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, memories                                 ////
4
////                                                              ////
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////  Description                                                 ////
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////  memories                                                    ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more memory types                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef ROM_INIT
44 5 unneback
/// ROM
45 40 unneback
`define MODULE rom_init
46
module `BASE`MODULE ( adr, q, clk);
47
`undef MODULE
48 5 unneback
 
49 7 unneback
   parameter data_width = 32;
50
   parameter addr_width = 8;
51
   input [(addr_width-1):0]       adr;
52
   output reg [(data_width-1):0] q;
53
   input                         clk;
54
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
55
   parameter memory_file = "vl_rom.vmem";
56
   initial
57
     begin
58
        $readmemh(memory_file, rom);
59
     end
60
 
61
   always @ (posedge clk)
62
     q <= rom[adr];
63 5 unneback
 
64 7 unneback
endmodule
65 40 unneback
`endif
66 7 unneback
 
67 40 unneback
`ifdef RAM
68
`define MODULE ram
69 5 unneback
// Single port RAM
70 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
71
`undef MODULE
72 5 unneback
 
73
   parameter data_width = 32;
74
   parameter addr_width = 8;
75
   input [(data_width-1):0]      d;
76
   input [(addr_width-1):0]       adr;
77
   input                         we;
78 7 unneback
   output reg [(data_width-1):0] q;
79 5 unneback
   input                         clk;
80
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
81 7 unneback
   parameter init = 0;
82
   parameter memory_file = "vl_ram.vmem";
83
   generate if (init) begin : init_mem
84
   initial
85
     begin
86
        $readmemh(memory_file, ram);
87
     end
88
   end
89
   endgenerate
90
 
91 5 unneback
   always @ (posedge clk)
92
   begin
93
   if (we)
94
     ram[adr] <= d;
95
   q <= ram[adr];
96
   end
97
 
98
endmodule
99 40 unneback
`endif
100 5 unneback
 
101 40 unneback
`ifdef RAM_BE
102
`define MODULE ram_be
103
module `BASE`MODULE ( d, adr, be, we, q, clk);
104
`undef MODULE
105
 
106 7 unneback
   parameter data_width = 32;
107 72 unneback
   parameter addr_width = 6;
108 68 unneback
   parameter mem_size = 256;
109 7 unneback
   input [(data_width-1):0]      d;
110
   input [(addr_width-1):0]       adr;
111 73 unneback
   input [(data_width/8)-1:0]    be;
112 7 unneback
   input                         we;
113
   output reg [(data_width-1):0] q;
114
   input                         clk;
115
 
116 65 unneback
//E2_ifdef SYSTEMVERILOG
117 68 unneback
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
118 65 unneback
//E2_else
119 68 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
120 65 unneback
//E2_endif
121
 
122 60 unneback
   parameter memory_init = 0;
123 7 unneback
   parameter memory_file = "vl_ram.vmem";
124 60 unneback
   generate if (memory_init) begin : init_mem
125 7 unneback
   initial
126
     begin
127
        $readmemh(memory_file, ram);
128
     end
129
   end
130
   endgenerate
131
 
132 60 unneback
//E2_ifdef SYSTEMVERILOG
133
// use a multi-dimensional packed array
134
//to model individual bytes within the word
135
 
136
always_ff@(posedge clk)
137
begin
138
    if(we) begin // note: we should have a for statement to support any bus width
139 65 unneback
        if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
140
        if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
141
        if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
142
        if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
143 60 unneback
    end
144 65 unneback
    q <= ram[adr];
145 60 unneback
end
146
 
147
//E2_else
148
 
149 7 unneback
   genvar i;
150
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
151
      always @ (posedge clk)
152
      if (we & be[i])
153
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
154
   end
155
   endgenerate
156
 
157
   always @ (posedge clk)
158
      q <= ram[adr];
159
 
160 60 unneback
//E2_endif
161
 
162 7 unneback
endmodule
163 40 unneback
`endif
164 7 unneback
 
165 5 unneback
`ifdef ACTEL
166 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
167 5 unneback
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
168
`else
169
        `define SYN
170
`endif
171
 
172 40 unneback
`ifdef DPRAM_1R1W
173
`define MODULE dpram_1r1w
174
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
175
`undef MODULE
176 5 unneback
   parameter data_width = 32;
177
   parameter addr_width = 8;
178
   input [(data_width-1):0]      d_a;
179
   input [(addr_width-1):0]       adr_a;
180
   input [(addr_width-1):0]       adr_b;
181
   input                         we_a;
182
   output [(data_width-1):0]      q_b;
183
   input                         clk_a, clk_b;
184
   reg [(addr_width-1):0]         adr_b_reg;
185
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
186 7 unneback
 
187
   parameter init = 0;
188
   parameter memory_file = "vl_ram.vmem";
189
   generate if (init) begin : init_mem
190
   initial
191
     begin
192
        $readmemh(memory_file, ram);
193
     end
194
   end
195
   endgenerate
196
 
197 5 unneback
   always @ (posedge clk_a)
198
   if (we_a)
199
     ram[adr_a] <= d_a;
200
   always @ (posedge clk_b)
201
   adr_b_reg <= adr_b;
202
   assign q_b = ram[adr_b_reg];
203 40 unneback
 
204 5 unneback
endmodule
205 40 unneback
`endif
206 5 unneback
 
207 40 unneback
`ifdef DPRAM_2R1W
208
`define MODULE dpram_2r1w
209
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
210
`undef MODULE
211
 
212 5 unneback
   parameter data_width = 32;
213
   parameter addr_width = 8;
214
   input [(data_width-1):0]      d_a;
215
   input [(addr_width-1):0]       adr_a;
216
   input [(addr_width-1):0]       adr_b;
217
   input                         we_a;
218
   output [(data_width-1):0]      q_b;
219
   output reg [(data_width-1):0] q_a;
220
   input                         clk_a, clk_b;
221
   reg [(data_width-1):0]         q_b;
222
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
223 7 unneback
 
224
   parameter init = 0;
225
   parameter memory_file = "vl_ram.vmem";
226
   generate if (init) begin : init_mem
227
   initial
228
     begin
229
        $readmemh(memory_file, ram);
230
     end
231
   end
232
   endgenerate
233
 
234 5 unneback
   always @ (posedge clk_a)
235
     begin
236
        q_a <= ram[adr_a];
237
        if (we_a)
238
             ram[adr_a] <= d_a;
239
     end
240
   always @ (posedge clk_b)
241
          q_b <= ram[adr_b];
242
endmodule
243 40 unneback
`endif
244 5 unneback
 
245 40 unneback
`ifdef DPRAM_2R2W
246
`define MODULE dpram_2r2w
247
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
248
`undef MODULE
249
 
250 5 unneback
   parameter data_width = 32;
251
   parameter addr_width = 8;
252
   input [(data_width-1):0]      d_a;
253
   input [(addr_width-1):0]       adr_a;
254
   input [(addr_width-1):0]       adr_b;
255
   input                         we_a;
256
   output [(data_width-1):0]      q_b;
257
   input [(data_width-1):0]       d_b;
258
   output reg [(data_width-1):0] q_a;
259
   input                         we_b;
260
   input                         clk_a, clk_b;
261
   reg [(data_width-1):0]         q_b;
262
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
263 7 unneback
 
264
   parameter init = 0;
265
   parameter memory_file = "vl_ram.vmem";
266
   generate if (init) begin : init_mem
267
   initial
268
     begin
269
        $readmemh(memory_file, ram);
270
     end
271
   end
272
   endgenerate
273
 
274 5 unneback
   always @ (posedge clk_a)
275
     begin
276
        q_a <= ram[adr_a];
277
        if (we_a)
278
             ram[adr_a] <= d_a;
279
     end
280
   always @ (posedge clk_b)
281
     begin
282
        q_b <= ram[adr_b];
283
        if (we_b)
284
          ram[adr_b] <= d_b;
285
     end
286
endmodule
287 40 unneback
`endif
288 5 unneback
 
289
// Content addresable memory, CAM
290
 
291 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
292 5 unneback
// FIFO
293 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
294
module `BASE`MODULE (
295
`undef MODULE
296 25 unneback
    d, wr, fifo_full,
297
    q, rd, fifo_empty,
298
    fill_level,
299
    clk, rst
300
    );
301
 
302
parameter data_width = 18;
303
parameter addr_width = 4;
304 5 unneback
 
305 25 unneback
// write side
306
input  [data_width-1:0] d;
307
input                   wr;
308
output                  fifo_full;
309
// read side
310
output [data_width-1:0] q;
311
input                   rd;
312
output                  fifo_empty;
313
// common
314
output [addr_width:0]   fill_level;
315
input rst, clk;
316
 
317
wire [addr_width:1] wadr, radr;
318
 
319 40 unneback
`define MODULE cnt_bin_ce
320
`BASE`MODULE
321 25 unneback
    # ( .length(addr_width))
322
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
323 40 unneback
`BASE`MODULE
324 25 unneback
    # (.length(addr_width))
325
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
326 40 unneback
`undef MODULE
327 25 unneback
 
328 40 unneback
`define MODULE dpram_1r1w
329
`BASE`MODULE
330 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
331
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
332 40 unneback
`undef MODULE
333 25 unneback
 
334 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
335
`BASE`MODULE
336 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
337 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
338 40 unneback
`undef MODULE
339 25 unneback
endmodule
340 40 unneback
`endif
341 25 unneback
 
342 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
343 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
344
// RAM is supposed to be larger than the two FIFOs
345
// LFSR counters used adr pointers
346 40 unneback
`define MODULE fifo_2r2w_sync_simplex
347
module `BASE`MODULE (
348
`undef MODULE
349 27 unneback
    // a side
350
    a_d, a_wr, a_fifo_full,
351
    a_q, a_rd, a_fifo_empty,
352
    a_fill_level,
353
    // b side
354
    b_d, b_wr, b_fifo_full,
355
    b_q, b_rd, b_fifo_empty,
356
    b_fill_level,
357
    // common
358
    clk, rst
359
    );
360
parameter data_width = 8;
361
parameter addr_width = 5;
362
parameter fifo_full_level = (1<<addr_width)-1;
363
 
364
// a side
365
input  [data_width-1:0] a_d;
366
input                   a_wr;
367
output                  a_fifo_full;
368
output [data_width-1:0] a_q;
369
input                   a_rd;
370
output                  a_fifo_empty;
371
output [addr_width-1:0] a_fill_level;
372
 
373
// b side
374
input  [data_width-1:0] b_d;
375
input                   b_wr;
376
output                  b_fifo_full;
377
output [data_width-1:0] b_q;
378
input                   b_rd;
379
output                  b_fifo_empty;
380
output [addr_width-1:0] b_fill_level;
381
 
382
input                   clk;
383
input                   rst;
384
 
385
// adr_gen
386
wire [addr_width:1] a_wadr, a_radr;
387
wire [addr_width:1] b_wadr, b_radr;
388
// dpram
389
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
390
 
391 40 unneback
`define MODULE cnt_lfsr_ce
392
`BASE`MODULE
393 27 unneback
    # ( .length(addr_width))
394
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
395
 
396 40 unneback
`BASE`MODULE
397 27 unneback
    # (.length(addr_width))
398
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
399
 
400 40 unneback
`BASE`MODULE
401 27 unneback
    # ( .length(addr_width))
402
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
403
 
404 40 unneback
`BASE`MODULE
405 27 unneback
    # (.length(addr_width))
406
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
407 40 unneback
`undef MODULE
408 27 unneback
 
409
// mux read or write adr to DPRAM
410
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
411
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
412
 
413 40 unneback
`define MODULE dpram_2r2w
414
`BASE`MODULE
415 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
416
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
417
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
418 40 unneback
`undef MODULE
419
 
420
`define MODULE cnt_bin_ce_rew_zq_l1
421
`BASE`MODULE
422 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
423 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
424
 
425 40 unneback
`BASE`MODULE
426 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
427 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
428 40 unneback
`undef MODULE
429 27 unneback
 
430
endmodule
431 40 unneback
`endif
432 27 unneback
 
433 40 unneback
`ifdef FIFO_CMP_ASYNC
434
`define MODULE fifo_cmp_async
435
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
436
`undef MODULE
437 5 unneback
 
438 11 unneback
   parameter addr_width = 4;
439
   parameter N = addr_width-1;
440 5 unneback
 
441
   parameter Q1 = 2'b00;
442
   parameter Q2 = 2'b01;
443
   parameter Q3 = 2'b11;
444
   parameter Q4 = 2'b10;
445
 
446
   parameter going_empty = 1'b0;
447
   parameter going_full  = 1'b1;
448
 
449
   input [N:0]  wptr, rptr;
450 14 unneback
   output       fifo_empty;
451 5 unneback
   output       fifo_full;
452
   input        wclk, rclk, rst;
453
 
454
`ifndef GENERATE_DIRECTION_AS_LATCH
455
   wire direction;
456
`endif
457
`ifdef GENERATE_DIRECTION_AS_LATCH
458
   reg direction;
459
`endif
460
   reg  direction_set, direction_clr;
461
 
462
   wire async_empty, async_full;
463
   wire fifo_full2;
464 14 unneback
   wire fifo_empty2;
465 5 unneback
 
466
   // direction_set
467
   always @ (wptr[N:N-1] or rptr[N:N-1])
468
     case ({wptr[N:N-1],rptr[N:N-1]})
469
       {Q1,Q2} : direction_set <= 1'b1;
470
       {Q2,Q3} : direction_set <= 1'b1;
471
       {Q3,Q4} : direction_set <= 1'b1;
472
       {Q4,Q1} : direction_set <= 1'b1;
473
       default : direction_set <= 1'b0;
474
     endcase
475
 
476
   // direction_clear
477
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
478
     if (rst)
479
       direction_clr <= 1'b1;
480
     else
481
       case ({wptr[N:N-1],rptr[N:N-1]})
482
         {Q2,Q1} : direction_clr <= 1'b1;
483
         {Q3,Q2} : direction_clr <= 1'b1;
484
         {Q4,Q3} : direction_clr <= 1'b1;
485
         {Q1,Q4} : direction_clr <= 1'b1;
486
         default : direction_clr <= 1'b0;
487
       endcase
488
 
489 40 unneback
`define MODULE dff_sr
490 5 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
491 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
492 5 unneback
`endif
493
 
494
`ifdef GENERATE_DIRECTION_AS_LATCH
495
   always @ (posedge direction_set or posedge direction_clr)
496
     if (direction_clr)
497
       direction <= going_empty;
498
     else
499
       direction <= going_full;
500
`endif
501
 
502
   assign async_empty = (wptr == rptr) && (direction==going_empty);
503
   assign async_full  = (wptr == rptr) && (direction==going_full);
504
 
505 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
506
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
507
`undef MODULE
508 5 unneback
 
509
/*
510
   always @ (posedge wclk or posedge rst or posedge async_full)
511
     if (rst)
512
       {fifo_full, fifo_full2} <= 2'b00;
513
     else if (async_full)
514
       {fifo_full, fifo_full2} <= 2'b11;
515
     else
516
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
517
*/
518 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
519 5 unneback
     if (async_empty)
520
       {fifo_empty, fifo_empty2} <= 2'b11;
521
     else
522 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
523 40 unneback
`define MODULE dff
524
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
525
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
526
`undef MODULE
527 25 unneback
endmodule // async_compb
528 40 unneback
`endif
529 5 unneback
 
530 40 unneback
`ifdef FIFO_1R1W_ASYNC
531
`define MODULE fifo_1r1w_async
532
module `BASE`MODULE (
533
`undef MODULE
534 5 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
535
    q, rd, fifo_empty, rd_clk, rd_rst
536
    );
537
 
538
parameter data_width = 18;
539
parameter addr_width = 4;
540
 
541
// write side
542
input  [data_width-1:0] d;
543
input                   wr;
544
output                  fifo_full;
545
input                   wr_clk;
546
input                   wr_rst;
547
// read side
548
output [data_width-1:0] q;
549
input                   rd;
550
output                  fifo_empty;
551
input                   rd_clk;
552
input                   rd_rst;
553
 
554
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
555 23 unneback
 
556 40 unneback
`define MODULE cnt_gray_ce_bin
557
`BASE`MODULE
558 5 unneback
    # ( .length(addr_width))
559
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
560
 
561 40 unneback
`BASE`MODULE
562 5 unneback
    # (.length(addr_width))
563 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
564 40 unneback
`undef MODULE
565 5 unneback
 
566 40 unneback
`define MODULE dpram_1r1w
567
`BASE`MODULE
568 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
569
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
570 40 unneback
`undef MODULE
571 5 unneback
 
572 40 unneback
`define MODULE fifo_cmp_async
573
`BASE`MODULE
574 5 unneback
    # (.addr_width(addr_width))
575
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
576 40 unneback
`undef MODULE
577 5 unneback
 
578
endmodule
579 40 unneback
`endif
580 5 unneback
 
581 40 unneback
`ifdef FIFO_2R2W_ASYNC
582
`define MODULE fifo_2r2w_async
583
module `BASE`MODULE (
584
`undef MODULE
585 5 unneback
    // a side
586
    a_d, a_wr, a_fifo_full,
587
    a_q, a_rd, a_fifo_empty,
588
    a_clk, a_rst,
589
    // b side
590
    b_d, b_wr, b_fifo_full,
591
    b_q, b_rd, b_fifo_empty,
592
    b_clk, b_rst
593
    );
594
 
595
parameter data_width = 18;
596
parameter addr_width = 4;
597
 
598
// a side
599
input  [data_width-1:0] a_d;
600
input                   a_wr;
601
output                  a_fifo_full;
602
output [data_width-1:0] a_q;
603
input                   a_rd;
604
output                  a_fifo_empty;
605
input                   a_clk;
606
input                   a_rst;
607
 
608
// b side
609
input  [data_width-1:0] b_d;
610
input                   b_wr;
611
output                  b_fifo_full;
612
output [data_width-1:0] b_q;
613
input                   b_rd;
614
output                  b_fifo_empty;
615
input                   b_clk;
616
input                   b_rst;
617
 
618 40 unneback
`define MODULE fifo_1r1w_async
619
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
620 5 unneback
vl_fifo_1r1w_async_a (
621
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
622
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
623
    );
624
 
625 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
626 5 unneback
vl_fifo_1r1w_async_b (
627
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
628
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
629
    );
630 40 unneback
`undef MODULE
631
 
632 5 unneback
endmodule
633 40 unneback
`endif
634 5 unneback
 
635 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
636
`define MODULE fifo_2r2w_async_simplex
637
module `BASE`MODULE (
638
`undef MODULE
639 5 unneback
    // a side
640
    a_d, a_wr, a_fifo_full,
641
    a_q, a_rd, a_fifo_empty,
642
    a_clk, a_rst,
643
    // b side
644
    b_d, b_wr, b_fifo_full,
645
    b_q, b_rd, b_fifo_empty,
646
    b_clk, b_rst
647
    );
648
 
649
parameter data_width = 18;
650
parameter addr_width = 4;
651
 
652
// a side
653
input  [data_width-1:0] a_d;
654
input                   a_wr;
655
output                  a_fifo_full;
656
output [data_width-1:0] a_q;
657
input                   a_rd;
658
output                  a_fifo_empty;
659
input                   a_clk;
660
input                   a_rst;
661
 
662
// b side
663
input  [data_width-1:0] b_d;
664
input                   b_wr;
665
output                  b_fifo_full;
666
output [data_width-1:0] b_q;
667
input                   b_rd;
668
output                  b_fifo_empty;
669
input                   b_clk;
670
input                   b_rst;
671
 
672
// adr_gen
673
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
674
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
675
// dpram
676
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
677
 
678 40 unneback
`define MODULE cnt_gray_ce_bin
679
`BASE`MODULE
680 5 unneback
    # ( .length(addr_width))
681
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
682
 
683 40 unneback
`BASE`MODULE
684 5 unneback
    # (.length(addr_width))
685
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
686
 
687 40 unneback
`BASE`MODULE
688 5 unneback
    # ( .length(addr_width))
689
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
690
 
691 40 unneback
`BASE`MODULE
692 5 unneback
    # (.length(addr_width))
693
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
694 40 unneback
`undef MODULE
695 5 unneback
 
696
// mux read or write adr to DPRAM
697
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
698
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
699
 
700 40 unneback
`define MODULE dpram_2r2w
701
`BASE`MODULE
702 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
703
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
704
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
705 40 unneback
`undef MODULE
706 5 unneback
 
707 40 unneback
`define MODULE fifo_cmp_async
708
`BASE`MODULE
709 5 unneback
    # (.addr_width(addr_width))
710
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
711
 
712 40 unneback
`BASE`MODULE
713 5 unneback
    # (.addr_width(addr_width))
714
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
715 40 unneback
`undef MODULE
716 5 unneback
 
717
endmodule
718 40 unneback
`endif
719 48 unneback
 
720
`ifdef REG_FILE
721
`define MODULE reg_file
722
module `BASE`MODULE (
723
`undef MODULE
724
    a1, a2, a3, wd3, we3, rd1, rd2, clk
725
);
726
parameter data_width = 32;
727
parameter addr_width = 5;
728
input [addr_width-1:0] a1, a2, a3;
729
input [data_width-1:0] wd3;
730
input we3;
731
output [data_width-1:0] rd1, rd2;
732
input clk;
733
 
734
`ifdef ACTEL
735
reg [data_width-1:0] wd3_reg;
736
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
737
reg we3_reg;
738
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
739
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
740
always @ (posedge clk or posedge rst)
741
if (rst)
742
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
743
else
744
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
745
 
746
    always @ (negedge clk)
747
    if (we3_reg)
748
        ram1[a3_reg] <= wd3;
749
    always @ (posedge clk)
750
        a1_reg <= a1;
751
    assign rd1 = ram1[a1_reg];
752
 
753
    always @ (negedge clk)
754
    if (we3_reg)
755
        ram2[a3_reg] <= wd3;
756
    always @ (posedge clk)
757
        a2_reg <= a2;
758
    assign rd2 = ram2[a2_reg];
759
 
760
`else
761
 
762
`define MODULE dpram_1r1w
763
`BASE`MODULE
764
    # ( .data_width(data_width), .addr_width(addr_width))
765
    ram1 (
766
        .d_a(wd3),
767
        .adr_a(a3),
768
        .we_a(we3),
769
        .clk_a(clk),
770
        .q_b(rd1),
771
        .adr_b(a1),
772
        .clk_b(clk) );
773
 
774
`BASE`MODULE
775
    # ( .data_width(data_width), .addr_width(addr_width))
776
    ram2 (
777
        .d_a(wd3),
778
        .adr_a(a3),
779
        .we_a(we3),
780
        .clk_a(clk),
781
        .q_b(rd2),
782
        .adr_b(a2),
783
        .clk_b(clk) );
784
`undef MODULE
785
 
786
`endif
787
 
788
endmodule
789
`endif

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