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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile library, memories                                 ////
////                                                              ////
////  Description                                                 ////
////  memories                                                    ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////   - add more memory types                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`ifdef ROM_INIT
/// ROM
`define MODULE rom_init
module `BASE`MODULE ( adr, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(addr_width-1):0]       adr;
   output reg [(data_width-1):0] q;
   input                         clk;
   reg [data_width-1:0] rom [mem_size-1:0];
   parameter memory_file = "vl_rom.vmem";
   initial
     begin
        $readmemh(memory_file, rom);
     end
 
   always @ (posedge clk)
     q <= rom[adr];
 
endmodule
`endif
 
`ifdef RAM
`define MODULE ram
// Single port RAM
module `BASE`MODULE ( d, adr, we, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input                         we;
   output reg [(data_width-1):0] q;
   input                         clk;
   reg [data_width-1:0] ram [mem_szie-1:0];
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk)
   begin
   if (we)
     ram[adr] <= d;
   q <= ram[adr];
   end
 
endmodule
`endif
 
`ifdef RAM_BE
`define MODULE ram_be
module `BASE`MODULE ( d, adr, be, we, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 6;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(data_width/8)-1:0]    be;
   input                         we;
   output reg [(data_width-1):0] q;
   input                         clk;
 
//E2_ifdef SYSTEMVERILOG
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
//E2_else
   reg [data_width-1:0] ram [mem_size-1:0];
//E2_endif
 
   parameter memory_init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (memory_init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
//E2_ifdef SYSTEMVERILOG
// use a multi-dimensional packed array
//to model individual bytes within the word
 
always_ff@(posedge clk)
begin
    if(we) begin // note: we should have a for statement to support any bus width
        if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
        if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
        if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
        if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
    end
    q <= ram[adr];
end
 
//E2_else
 
   genvar i;
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
      always @ (posedge clk)
      if (we & be[i])
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
   end
   endgenerate
 
   always @ (posedge clk)
      q <= ram[adr];
 
//E2_endif
 
endmodule
`endif
 
`ifdef ACTEL
        // ACTEL FPGA should not use logic to handle rw collision
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
`else
        `define SYN
`endif
 
`ifdef DPRAM_1R1W
`define MODULE dpram_1r1w
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
`undef MODULE
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   input                         clk_a, clk_b;
   reg [(addr_width-1):0]         adr_b_reg;
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
   if (we_a)
     ram[adr_a] <= d_a;
   always @ (posedge clk_b)
   adr_b_reg <= adr_b;
   assign q_b = ram[adr_b_reg];
 
endmodule
`endif
 
`ifdef DPRAM_2R1W
`define MODULE dpram_2r1w
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output reg [(data_width-1):0] q_a;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
          q_b <= ram[adr_b];
endmodule
`endif
 
`ifdef DPRAM_2R2W
`define MODULE dpram_2r2w
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   input [(data_width-1):0]       d_b;
   output reg [(data_width-1):0] q_a;
   input                         we_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
     begin
        q_b <= ram[adr_b];
        if (we_b)
          ram[adr_b] <= d_b;
     end
endmodule
`endif
 
`ifdef DPRAM_BE_2R2W
`define MODULE dpram_be_2r2w
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
`undef MODULE
 
   parameter a_data_width = 32;
   parameter a_addr_width = 8;
   parameter b_data_width = 64;
   parameter b_addr_width = 7;
   //parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
   parameter mem_size = 1024;
   input [(a_data_width-1):0]      d_a;
   input [(a_addr_width-1):0]     adr_a;
   input [(b_addr_width-1):0]     adr_b;
   input [(a_data_width/4-1):0]    be_a;
   input                         we_a;
   output [(b_data_width-1):0]    q_b;
   input [(b_data_width-1):0]     d_b;
   output reg [(a_data_width-1):0] q_a;
   input [(b_data_width/4-1):0]    be_b;
   input                         we_b;
   input                         clk_a, clk_b;
   reg [(b_data_width-1):0]       q_b;
 
generate
if (a_data_width==32 & b_data_width==64) begin : inst32to64
 
    wire [63:0] temp;
    `define MODULE dpram_2r2w
    `BASE`MODULE
    # (.data_width(8), .addr_width(b_addr_width-3))
    ram0 (
        .d_a(d_a[7:0]),
        .q_a(tmp[7:0]),
        .adr_a(adr_a[a_addr_width-3-1:0]),
        .we_a(we_a & be_a[0] & !adr_a[0]),
        .clk_a(clk_a),
        .d_b(d_b[7:0]),
        .q_b(q_b[7:0]),
        .adr_b(adr_b[b_addr_width-3-1:0]),
        .we_b(we_b),
        .clk_b(clk_b) );
    `BASE`MODULE
    # (.data_width(8), .addr_width(b_addr_width-3))
    ram1 (
        .d_a(d_a[7:0]),
        .q_a(tmp[7:0]),
        .adr_a(adr_a[a_addr_width-3-1:0]),
        .we_a(we_a),
        .clk_a(clk_a),
        .d_b(d_b[7:0]),
        .q_b(q_b[7:0]),
        .adr_b(adr_b[b_addr_width-3-1:0]),
        .we_b(we_b),
        .clk_b(clk_b) );
    `BASE`MODULE
    # (.data_width(8), .addr_width(b_addr_width-3))
    ram2 (
        .d_a(d_a[15:8]),
        .q_a(tmp[7:0]),
        .adr_a(adr_a[a_addr_width-3-1:0]),
        .we_a(we_a),
        .clk_a(clk_a),
        .d_b(d_b[7:0]),
        .q_b(q_b[7:0]),
        .adr_b(adr_b[b_addr_width-3-1:0]),
        .we_b(we_b),
        .clk_b(clk_b) );
    `BASE`MODULE
    # (.data_width(8), .addr_width(b_addr_width-3))
    ram3 (
        .d_a(d_a[15:8]),
        .q_a(tmp[7:0]),
        .adr_a(adr_a[a_addr_width-3-1:0]),
        .we_a(we_a),
        .clk_a(clk_a),
        .d_b(d_b[7:0]),
        .q_b(q_b[7:0]),
        .adr_b(adr_b[b_addr_width-3-1:0]),
        .we_b(we_b),
        .clk_b(clk_b) );
    `BASE`MODULE
    # (.data_width(8), .addr_width(b_addr_width-3))
    ram4 (
        .d_a(d_a[23:16]),
        .q_a(tmp[7:0]),
        .adr_a(adr_a[a_addr_width-3-1:0]),
        .we_a(we_a),
        .clk_a(clk_a),
        .d_b(d_b[7:0]),
        .q_b(q_b[7:0]),
        .adr_b(adr_b[b_addr_width-3-1:0]),
        .we_b(we_b),
        .clk_b(clk_b) );
    `BASE`MODULE
    # (.data_width(8), .addr_width(b_addr_width-3))
    ram5 (
        .d_a(d_a[23:16]),
        .q_a(tmp[7:0]),
        .adr_a(adr_a[a_addr_width-3-1:0]),
        .we_a(we_a),
        .clk_a(clk_a),
        .d_b(d_b[7:0]),
        .q_b(q_b[7:0]),
        .adr_b(adr_b[b_addr_width-3-1:0]),
        .we_b(we_b),
        .clk_b(clk_b) );
    `BASE`MODULE
    # (.data_width(8), .addr_width(b_addr_width-3))
    ram6 (
        .d_a(d_a[31:24]),
        .q_a(tmp[7:0]),
        .adr_a(adr_a[a_addr_width-3-1:0]),
        .we_a(we_a),
        .clk_a(clk_a),
        .d_b(d_b[7:0]),
        .q_b(q_b[7:0]),
        .adr_b(adr_b[b_addr_width-3-1:0]),
        .we_b(we_b),
        .clk_b(clk_b) );
    `BASE`MODULE
    # (.data_width(8), .addr_width(b_addr_width-3))
    ram7 (
        .d_a(d_a[31:24]),
        .q_a(tmp[7:0]),
        .adr_a(adr_a[a_addr_width-3-1:0]),
        .we_a(we_a),
        .clk_a(clk_a),
        .d_b(d_b[7:0]),
        .q_b(q_b[7:0]),
        .adr_b(adr_b[b_addr_width-3-1:0]),
        .we_b(we_b),
        .clk_b(clk_b) );
`undef MODULE
/*
   reg [7:0] ram0 [mem_size/8-1:0];
   wire [7:0] wea, web;
   assign wea = we_a & be_a[0];
   assign web = we_b & be_b[0];
   always @ (posedge clk_a)
    if (wea)
        ram0[adr_a] <= d_a[7:0];
    always @ (posedge clk_a)
        q_a[7:0] <= ram0[adr_a];
   always @ (posedge clk_a)
    if (web)
        ram0[adr_b] <= d_b[7:0];
    always @ (posedge clk_b)
        q_b[7:0] <= ram0[adr_b];
*/
end
endgenerate
/*
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_rama
      always @ (posedge clk_a)
      if (we_a & be_a[i])
        ram[adr_a][(i+1)*8-1:i*8] <= d_a[(i+1)*8-1:i*8];
   end
   endgenerate
 
   always @ (posedge clk_a)
      q_a <= ram[adr_a];
 
   genvar i;
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ramb
      always @ (posedge clk_a)
      if (we_b & be_b[i])
        ram[adr_b][(i+1)*8-1:i*8] <= d_b[(i+1)*8-1:i*8];
   end
   endgenerate
 
   always @ (posedge clk_b)
      q_b <= ram[adr_b];
*/
/*
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
     begin
        q_b <= ram[adr_b];
        if (we_b)
          ram[adr_b] <= d_b;
     end
*/
endmodule
`endif
 
// Content addresable memory, CAM
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
// FIFO
`define MODULE fifo_1r1w_fill_level_sync
module `BASE`MODULE (
`undef MODULE
    d, wr, fifo_full,
    q, rd, fifo_empty,
    fill_level,
    clk, rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// write side
input  [data_width-1:0] d;
input                   wr;
output                  fifo_full;
// read side
output [data_width-1:0] q;
input                   rd;
output                  fifo_empty;
// common
output [addr_width:0]   fill_level;
input rst, clk;
 
wire [addr_width:1] wadr, radr;
 
`define MODULE cnt_bin_ce
`BASE`MODULE
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
`BASE`MODULE
    # (.length(addr_width))
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
`undef MODULE
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
`undef MODULE
 
`define MODULE cnt_bin_ce_rew_q_zq_l1
`BASE`MODULE
    # (.length(addr_width+1), .level1_value(1<<addr_width))
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
`undef MODULE
endmodule
`endif
 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
// RAM is supposed to be larger than the two FIFOs
// LFSR counters used adr pointers
`define MODULE fifo_2r2w_sync_simplex
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_fill_level,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_fill_level,
    // common
    clk, rst
    );
parameter data_width = 8;
parameter addr_width = 5;
parameter fifo_full_level = (1<<addr_width)-1;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
output [addr_width-1:0] a_fill_level;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
output [addr_width-1:0] b_fill_level;
 
input                   clk;
input                   rst;
 
// adr_gen
wire [addr_width:1] a_wadr, a_radr;
wire [addr_width:1] b_wadr, b_radr;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
`define MODULE cnt_lfsr_ce
`BASE`MODULE
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
`undef MODULE
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
 
`define MODULE dpram_2r2w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
`undef MODULE
 
`define MODULE cnt_bin_ce_rew_zq_l1
`BASE`MODULE
    # (.length(addr_width), .level1_value(fifo_full_level))
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width), .level1_value(fifo_full_level))
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_CMP_ASYNC
`define MODULE fifo_cmp_async
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
`undef MODULE
 
   parameter addr_width = 4;
   parameter N = addr_width-1;
 
   parameter Q1 = 2'b00;
   parameter Q2 = 2'b01;
   parameter Q3 = 2'b11;
   parameter Q4 = 2'b10;
 
   parameter going_empty = 1'b0;
   parameter going_full  = 1'b1;
 
   input [N:0]  wptr, rptr;
   output       fifo_empty;
   output       fifo_full;
   input        wclk, rclk, rst;
 
`ifndef GENERATE_DIRECTION_AS_LATCH
   wire direction;
`endif
`ifdef GENERATE_DIRECTION_AS_LATCH
   reg direction;
`endif
   reg  direction_set, direction_clr;
 
   wire async_empty, async_full;
   wire fifo_full2;
   wire fifo_empty2;
 
   // direction_set
   always @ (wptr[N:N-1] or rptr[N:N-1])
     case ({wptr[N:N-1],rptr[N:N-1]})
       {Q1,Q2} : direction_set <= 1'b1;
       {Q2,Q3} : direction_set <= 1'b1;
       {Q3,Q4} : direction_set <= 1'b1;
       {Q4,Q1} : direction_set <= 1'b1;
       default : direction_set <= 1'b0;
     endcase
 
   // direction_clear
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
     if (rst)
       direction_clr <= 1'b1;
     else
       case ({wptr[N:N-1],rptr[N:N-1]})
         {Q2,Q1} : direction_clr <= 1'b1;
         {Q3,Q2} : direction_clr <= 1'b1;
         {Q4,Q3} : direction_clr <= 1'b1;
         {Q1,Q4} : direction_clr <= 1'b1;
         default : direction_clr <= 1'b0;
       endcase
 
`define MODULE dff_sr
`ifndef GENERATE_DIRECTION_AS_LATCH
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
`endif
 
`ifdef GENERATE_DIRECTION_AS_LATCH
   always @ (posedge direction_set or posedge direction_clr)
     if (direction_clr)
       direction <= going_empty;
     else
       direction <= going_full;
`endif
 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_full  = (wptr == rptr) && (direction==going_full);
 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
`undef MODULE
 
/*
   always @ (posedge wclk or posedge rst or posedge async_full)
     if (rst)
       {fifo_full, fifo_full2} <= 2'b00;
     else if (async_full)
       {fifo_full, fifo_full2} <= 2'b11;
     else
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
/*   always @ (posedge rclk or posedge async_empty)
     if (async_empty)
       {fifo_empty, fifo_empty2} <= 2'b11;
     else
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
`define MODULE dff
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
`undef MODULE
endmodule // async_compb
`endif
 
`ifdef FIFO_1R1W_ASYNC
`define MODULE fifo_1r1w_async
module `BASE`MODULE (
`undef MODULE
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// write side
input  [data_width-1:0] d;
input                   wr;
output                  fifo_full;
input                   wr_clk;
input                   wr_rst;
// read side
output [data_width-1:0] q;
input                   rd;
output                  fifo_empty;
input                   rd_clk;
input                   rd_rst;
 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
 
`define MODULE cnt_gray_ce_bin
`BASE`MODULE
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
`undef MODULE
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
`undef MODULE
 
`define MODULE fifo_cmp_async
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_2R2W_ASYNC
`define MODULE fifo_2r2w_async
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
input                   a_clk;
input                   a_rst;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
input                   b_clk;
input                   b_rst;
 
`define MODULE fifo_1r1w_async
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_a (
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
    );
 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_b (
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
    );
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`define MODULE fifo_2r2w_async_simplex
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
input                   a_clk;
input                   a_rst;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
input                   b_clk;
input                   b_rst;
 
// adr_gen
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
`define MODULE cnt_gray_ce_bin
`BASE`MODULE
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
 
`BASE`MODULE
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
`undef MODULE
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
 
`define MODULE dpram_2r2w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
`undef MODULE
 
`define MODULE fifo_cmp_async
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
 
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
`undef MODULE
 
endmodule
`endif
 
`ifdef REG_FILE
`define MODULE reg_file
module `BASE`MODULE (
`undef MODULE
    a1, a2, a3, wd3, we3, rd1, rd2, clk
);
parameter data_width = 32;
parameter addr_width = 5;
input [addr_width-1:0] a1, a2, a3;
input [data_width-1:0] wd3;
input we3;
output [data_width-1:0] rd1, rd2;
input clk;
 
`ifdef ACTEL
reg [data_width-1:0] wd3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg we3_reg;
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
always @ (posedge clk or posedge rst)
if (rst)
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
else
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
 
    always @ (negedge clk)
    if (we3_reg)
        ram1[a3_reg] <= wd3;
    always @ (posedge clk)
        a1_reg <= a1;
    assign rd1 = ram1[a1_reg];
 
    always @ (negedge clk)
    if (we3_reg)
        ram2[a3_reg] <= wd3;
    always @ (posedge clk)
        a2_reg <= a2;
    assign rd2 = ram2[a2_reg];
 
`else
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # ( .data_width(data_width), .addr_width(addr_width))
    ram1 (
        .d_a(wd3),
        .adr_a(a3),
        .we_a(we3),
        .clk_a(clk),
        .q_b(rd1),
        .adr_b(a1),
        .clk_b(clk) );
 
`BASE`MODULE
    # ( .data_width(data_width), .addr_width(addr_width))
    ram2 (
        .d_a(wd3),
        .adr_a(a3),
        .we_a(we3),
        .clk_a(clk),
        .q_b(rd2),
        .adr_b(a2),
        .clk_b(clk) );
`undef MODULE
 
`endif
 
endmodule
`endif

Line No.	Rev	Author	Line
1	5	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Versatile library, memories ////`
4			`//// ////`
5			`//// Description ////`
6			`//// memories ////`
7			`//// ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - add more memory types ////`
11			`//// ////`
12			`//// Author(s): ////`
13			`//// - Michael Unneback, unneback@opencores.org ////`
14			`//// ORSoC AB ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43	40	unneback	`ifdef ROM_INIT
44	5	unneback	`/// ROM`
45	40	unneback	`define MODULE rom_init
46			module `BASE`MODULE ( adr, q, clk);
47			`undef MODULE
48	5	unneback
49	7	unneback	`parameter data_width = 32;`
50			`parameter addr_width = 8;`
51	75	unneback	`parameter mem_size = 1<<addr_width;`
52	7	unneback	`input [(addr_width-1):0] adr;`
53			`output reg [(data_width-1):0] q;`
54			`input clk;`
55	75	unneback	`reg [data_width-1:0] rom [mem_size-1:0];`
56	7	unneback	`parameter memory_file = "vl_rom.vmem";`
57			`initial`
58			`begin`
59			`$readmemh(memory_file, rom);`
60			`end`
61
62			`always @ (posedge clk)`
63			`q <= rom[adr];`
64	5	unneback
65	7	unneback	`endmodule`
66	40	unneback	`endif
67	7	unneback
68	40	unneback	`ifdef RAM
69			`define MODULE ram
70	5	unneback	`// Single port RAM`
71	40	unneback	module `BASE`MODULE ( d, adr, we, q, clk);
72			`undef MODULE
73	5	unneback
74			`parameter data_width = 32;`
75			`parameter addr_width = 8;`
76	75	unneback	`parameter mem_size = 1<<addr_width;`
77	5	unneback	`input [(data_width-1):0] d;`
78			`input [(addr_width-1):0] adr;`
79			`input we;`
80	7	unneback	`output reg [(data_width-1):0] q;`
81	5	unneback	`input clk;`
82	75	unneback	`reg [data_width-1:0] ram [mem_szie-1:0];`
83	7	unneback	`parameter init = 0;`
84			`parameter memory_file = "vl_ram.vmem";`
85			`generate if (init) begin : init_mem`
86			`initial`
87			`begin`
88			`$readmemh(memory_file, ram);`
89			`end`
90			`end`
91			`endgenerate`
92
93	5	unneback	`always @ (posedge clk)`
94			`begin`
95			`if (we)`
96			`ram[adr] <= d;`
97			`q <= ram[adr];`
98			`end`
99
100			`endmodule`
101	40	unneback	`endif
102	5	unneback
103	40	unneback	`ifdef RAM_BE
104			`define MODULE ram_be
105			module `BASE`MODULE ( d, adr, be, we, q, clk);
106			`undef MODULE
107
108	7	unneback	`parameter data_width = 32;`
109	72	unneback	`parameter addr_width = 6;`
110	75	unneback	`parameter mem_size = 1<<addr_width;`
111	7	unneback	`input [(data_width-1):0] d;`
112			`input [(addr_width-1):0] adr;`
113	73	unneback	`input [(data_width/8)-1:0] be;`
114	7	unneback	`input we;`
115			`output reg [(data_width-1):0] q;`
116			`input clk;`
117
118	65	unneback	`//E2_ifdef SYSTEMVERILOG`
119	68	unneback	`logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width`
120	65	unneback	`//E2_else`
121	68	unneback	`reg [data_width-1:0] ram [mem_size-1:0];`
122	65	unneback	`//E2_endif`
123
124	60	unneback	`parameter memory_init = 0;`
125	7	unneback	`parameter memory_file = "vl_ram.vmem";`
126	60	unneback	`generate if (memory_init) begin : init_mem`
127	7	unneback	`initial`
128			`begin`
129			`$readmemh(memory_file, ram);`
130			`end`
131			`end`
132			`endgenerate`
133
134	60	unneback	`//E2_ifdef SYSTEMVERILOG`
135			`// use a multi-dimensional packed array`
136			`//to model individual bytes within the word`
137
138			`always_ff@(posedge clk)`
139			`begin`
140			`if(we) begin // note: we should have a for statement to support any bus width`
141	65	unneback	`if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];`
142			`if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];`
143			`if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];`
144			`if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];`
145	60	unneback	`end`
146	65	unneback	`q <= ram[adr];`
147	60	unneback	`end`
148
149			`//E2_else`
150
151	7	unneback	`genvar i;`
152			`generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram`
153			`always @ (posedge clk)`
154			`if (we & be[i])`
155			`ram[adr][(i+1)8-1:i8] <= d[(i+1)8-1:i8];`
156			`end`
157			`endgenerate`
158
159			`always @ (posedge clk)`
160			`q <= ram[adr];`
161
162	60	unneback	`//E2_endif`
163
164	7	unneback	`endmodule`
165	40	unneback	`endif
166	7	unneback
167	5	unneback	`ifdef ACTEL
168	48	unneback	`// ACTEL FPGA should not use logic to handle rw collision`
169	5	unneback	`define SYN /synthesis syn_ramstyle = "no_rw_check"/
170			`else
171			`define SYN
172			`endif
173
174	40	unneback	`ifdef DPRAM_1R1W
175			`define MODULE dpram_1r1w
176			module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
177			`undef MODULE
178	5	unneback	`parameter data_width = 32;`
179			`parameter addr_width = 8;`
180	75	unneback	`parameter mem_size = 1<<addr_width;`
181	5	unneback	`input [(data_width-1):0] d_a;`
182			`input [(addr_width-1):0] adr_a;`
183			`input [(addr_width-1):0] adr_b;`
184			`input we_a;`
185			`output [(data_width-1):0] q_b;`
186			`input clk_a, clk_b;`
187			`reg [(addr_width-1):0] adr_b_reg;`
188	75	unneback	reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
189	7	unneback
190			`parameter init = 0;`
191			`parameter memory_file = "vl_ram.vmem";`
192			`generate if (init) begin : init_mem`
193			`initial`
194			`begin`
195			`$readmemh(memory_file, ram);`
196			`end`
197			`end`
198			`endgenerate`
199
200	5	unneback	`always @ (posedge clk_a)`
201			`if (we_a)`
202			`ram[adr_a] <= d_a;`
203			`always @ (posedge clk_b)`
204			`adr_b_reg <= adr_b;`
205			`assign q_b = ram[adr_b_reg];`
206	40	unneback
207	5	unneback	`endmodule`
208	40	unneback	`endif
209	5	unneback
210	40	unneback	`ifdef DPRAM_2R1W
211			`define MODULE dpram_2r1w
212			module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
213			`undef MODULE
214
215	5	unneback	`parameter data_width = 32;`
216			`parameter addr_width = 8;`
217	75	unneback	`parameter mem_size = 1<<addr_width;`
218	5	unneback	`input [(data_width-1):0] d_a;`
219			`input [(addr_width-1):0] adr_a;`
220			`input [(addr_width-1):0] adr_b;`
221			`input we_a;`
222			`output [(data_width-1):0] q_b;`
223			`output reg [(data_width-1):0] q_a;`
224			`input clk_a, clk_b;`
225			`reg [(data_width-1):0] q_b;`
226	75	unneback	reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
227	7	unneback
228			`parameter init = 0;`
229			`parameter memory_file = "vl_ram.vmem";`
230			`generate if (init) begin : init_mem`
231			`initial`
232			`begin`
233			`$readmemh(memory_file, ram);`
234			`end`
235			`end`
236			`endgenerate`
237
238	5	unneback	`always @ (posedge clk_a)`
239			`begin`
240			`q_a <= ram[adr_a];`
241			`if (we_a)`
242			`ram[adr_a] <= d_a;`
243			`end`
244			`always @ (posedge clk_b)`
245			`q_b <= ram[adr_b];`
246			`endmodule`
247	40	unneback	`endif
248	5	unneback
249	40	unneback	`ifdef DPRAM_2R2W
250			`define MODULE dpram_2r2w
251			module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
252			`undef MODULE
253
254	5	unneback	`parameter data_width = 32;`
255			`parameter addr_width = 8;`
256	75	unneback	`parameter mem_size = 1<<addr_width;`
257	5	unneback	`input [(data_width-1):0] d_a;`
258			`input [(addr_width-1):0] adr_a;`
259			`input [(addr_width-1):0] adr_b;`
260			`input we_a;`
261			`output [(data_width-1):0] q_b;`
262			`input [(data_width-1):0] d_b;`
263			`output reg [(data_width-1):0] q_a;`
264			`input we_b;`
265			`input clk_a, clk_b;`
266			`reg [(data_width-1):0] q_b;`
267	75	unneback	reg [data_width-1:0] ram [mem_size-1:0] `SYN;
268	7	unneback
269			`parameter init = 0;`
270			`parameter memory_file = "vl_ram.vmem";`
271			`generate if (init) begin : init_mem`
272			`initial`
273			`begin`
274			`$readmemh(memory_file, ram);`
275			`end`
276			`end`
277			`endgenerate`
278
279	5	unneback	`always @ (posedge clk_a)`
280			`begin`
281			`q_a <= ram[adr_a];`
282			`if (we_a)`
283			`ram[adr_a] <= d_a;`
284			`end`
285			`always @ (posedge clk_b)`
286			`begin`
287			`q_b <= ram[adr_b];`
288			`if (we_b)`
289			`ram[adr_b] <= d_b;`
290			`end`
291			`endmodule`
292	40	unneback	`endif
293	5	unneback
294	75	unneback	`ifdef DPRAM_BE_2R2W
295			`define MODULE dpram_be_2r2w
296			module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
297			`undef MODULE
298
299			`parameter a_data_width = 32;`
300			`parameter a_addr_width = 8;`
301			`parameter b_data_width = 64;`
302			`parameter b_addr_width = 7;`
303			`//parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);`
304			`parameter mem_size = 1024;`
305			`input [(a_data_width-1):0] d_a;`
306			`input [(a_addr_width-1):0] adr_a;`
307			`input [(b_addr_width-1):0] adr_b;`
308			`input [(a_data_width/4-1):0] be_a;`
309			`input we_a;`
310			`output [(b_data_width-1):0] q_b;`
311			`input [(b_data_width-1):0] d_b;`
312			`output reg [(a_data_width-1):0] q_a;`
313			`input [(b_data_width/4-1):0] be_b;`
314			`input we_b;`
315			`input clk_a, clk_b;`
316			`reg [(b_data_width-1):0] q_b;`
317
318			`generate`
319			`if (a_data_width==32 & b_data_width==64) begin : inst32to64`
320
321			`wire [63:0] temp;`
322			`define MODULE dpram_2r2w
323			`BASE`MODULE
324			`# (.data_width(8), .addr_width(b_addr_width-3))`
325			`ram0 (`
326			`.d_a(d_a[7:0]),`
327			`.q_a(tmp[7:0]),`
328			`.adr_a(adr_a[a_addr_width-3-1:0]),`
329			`.we_a(we_a & be_a[0] & !adr_a[0]),`
330			`.clk_a(clk_a),`
331			`.d_b(d_b[7:0]),`
332			`.q_b(q_b[7:0]),`
333			`.adr_b(adr_b[b_addr_width-3-1:0]),`
334			`.we_b(we_b),`
335			`.clk_b(clk_b) );`
336			`BASE`MODULE
337			`# (.data_width(8), .addr_width(b_addr_width-3))`
338			`ram1 (`
339			`.d_a(d_a[7:0]),`
340			`.q_a(tmp[7:0]),`
341			`.adr_a(adr_a[a_addr_width-3-1:0]),`
342			`.we_a(we_a),`
343			`.clk_a(clk_a),`
344			`.d_b(d_b[7:0]),`
345			`.q_b(q_b[7:0]),`
346			`.adr_b(adr_b[b_addr_width-3-1:0]),`
347			`.we_b(we_b),`
348			`.clk_b(clk_b) );`
349			`BASE`MODULE
350			`# (.data_width(8), .addr_width(b_addr_width-3))`
351			`ram2 (`
352			`.d_a(d_a[15:8]),`
353			`.q_a(tmp[7:0]),`
354			`.adr_a(adr_a[a_addr_width-3-1:0]),`
355			`.we_a(we_a),`
356			`.clk_a(clk_a),`
357			`.d_b(d_b[7:0]),`
358			`.q_b(q_b[7:0]),`
359			`.adr_b(adr_b[b_addr_width-3-1:0]),`
360			`.we_b(we_b),`
361			`.clk_b(clk_b) );`
362			`BASE`MODULE
363			`# (.data_width(8), .addr_width(b_addr_width-3))`
364			`ram3 (`
365			`.d_a(d_a[15:8]),`
366			`.q_a(tmp[7:0]),`
367			`.adr_a(adr_a[a_addr_width-3-1:0]),`
368			`.we_a(we_a),`
369			`.clk_a(clk_a),`
370			`.d_b(d_b[7:0]),`
371			`.q_b(q_b[7:0]),`
372			`.adr_b(adr_b[b_addr_width-3-1:0]),`
373			`.we_b(we_b),`
374			`.clk_b(clk_b) );`
375			`BASE`MODULE
376			`# (.data_width(8), .addr_width(b_addr_width-3))`
377			`ram4 (`
378			`.d_a(d_a[23:16]),`
379			`.q_a(tmp[7:0]),`
380			`.adr_a(adr_a[a_addr_width-3-1:0]),`
381			`.we_a(we_a),`
382			`.clk_a(clk_a),`
383			`.d_b(d_b[7:0]),`
384			`.q_b(q_b[7:0]),`
385			`.adr_b(adr_b[b_addr_width-3-1:0]),`
386			`.we_b(we_b),`
387			`.clk_b(clk_b) );`
388			`BASE`MODULE
389			`# (.data_width(8), .addr_width(b_addr_width-3))`
390			`ram5 (`
391			`.d_a(d_a[23:16]),`
392			`.q_a(tmp[7:0]),`
393			`.adr_a(adr_a[a_addr_width-3-1:0]),`
394			`.we_a(we_a),`
395			`.clk_a(clk_a),`
396			`.d_b(d_b[7:0]),`
397			`.q_b(q_b[7:0]),`
398			`.adr_b(adr_b[b_addr_width-3-1:0]),`
399			`.we_b(we_b),`
400			`.clk_b(clk_b) );`
401			`BASE`MODULE
402			`# (.data_width(8), .addr_width(b_addr_width-3))`
403			`ram6 (`
404			`.d_a(d_a[31:24]),`
405			`.q_a(tmp[7:0]),`
406			`.adr_a(adr_a[a_addr_width-3-1:0]),`
407			`.we_a(we_a),`
408			`.clk_a(clk_a),`
409			`.d_b(d_b[7:0]),`
410			`.q_b(q_b[7:0]),`
411			`.adr_b(adr_b[b_addr_width-3-1:0]),`
412			`.we_b(we_b),`
413			`.clk_b(clk_b) );`
414			`BASE`MODULE
415			`# (.data_width(8), .addr_width(b_addr_width-3))`
416			`ram7 (`
417			`.d_a(d_a[31:24]),`
418			`.q_a(tmp[7:0]),`
419			`.adr_a(adr_a[a_addr_width-3-1:0]),`
420			`.we_a(we_a),`
421			`.clk_a(clk_a),`
422			`.d_b(d_b[7:0]),`
423			`.q_b(q_b[7:0]),`
424			`.adr_b(adr_b[b_addr_width-3-1:0]),`
425			`.we_b(we_b),`
426			`.clk_b(clk_b) );`
427			`undef MODULE
428			`/*`
429			`reg [7:0] ram0 [mem_size/8-1:0];`
430			`wire [7:0] wea, web;`
431			`assign wea = we_a & be_a[0];`
432			`assign web = we_b & be_b[0];`
433			`always @ (posedge clk_a)`
434			`if (wea)`
435			`ram0[adr_a] <= d_a[7:0];`
436			`always @ (posedge clk_a)`
437			`q_a[7:0] <= ram0[adr_a];`
438			`always @ (posedge clk_a)`
439			`if (web)`
440			`ram0[adr_b] <= d_b[7:0];`
441			`always @ (posedge clk_b)`
442			`q_b[7:0] <= ram0[adr_b];`
443			`*/`
444			`end`
445			`endgenerate`
446			`/*`
447			`generate for (i=0;i<addr_width/4;i=i+1) begin : be_rama`
448			`always @ (posedge clk_a)`
449			`if (we_a & be_a[i])`
450			`ram[adr_a][(i+1)8-1:i8] <= d_a[(i+1)8-1:i8];`
451			`end`
452			`endgenerate`
453
454			`always @ (posedge clk_a)`
455			`q_a <= ram[adr_a];`
456
457			`genvar i;`
458			`generate for (i=0;i<addr_width/4;i=i+1) begin : be_ramb`
459			`always @ (posedge clk_a)`
460			`if (we_b & be_b[i])`
461			`ram[adr_b][(i+1)8-1:i8] <= d_b[(i+1)8-1:i8];`
462			`end`
463			`endgenerate`
464
465			`always @ (posedge clk_b)`
466			`q_b <= ram[adr_b];`
467			`*/`
468			`/*`
469			`always @ (posedge clk_a)`
470			`begin`
471			`q_a <= ram[adr_a];`
472			`if (we_a)`
473			`ram[adr_a] <= d_a;`
474			`end`
475			`always @ (posedge clk_b)`
476			`begin`
477			`q_b <= ram[adr_b];`
478			`if (we_b)`
479			`ram[adr_b] <= d_b;`
480			`end`
481			`*/`
482			`endmodule`
483			`endif
484
485	5	unneback	`// Content addresable memory, CAM`
486
487	40	unneback	`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
488	5	unneback	`// FIFO`
489	40	unneback	`define MODULE fifo_1r1w_fill_level_sync
490			module `BASE`MODULE (
491			`undef MODULE
492	25	unneback	`d, wr, fifo_full,`
493			`q, rd, fifo_empty,`
494			`fill_level,`
495			`clk, rst`
496			`);`
497
498			`parameter data_width = 18;`
499			`parameter addr_width = 4;`
500	5	unneback

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