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1 5 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, memories                                 ////
4
////                                                              ////
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////  Description                                                 ////
6
////  memories                                                    ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more memory types                                    ////
11
////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
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////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef ROM_INIT
44 5 unneback
/// ROM
45 40 unneback
`define MODULE rom_init
46
module `BASE`MODULE ( adr, q, clk);
47
`undef MODULE
48 5 unneback
 
49 7 unneback
   parameter data_width = 32;
50
   parameter addr_width = 8;
51 75 unneback
   parameter mem_size = 1<<addr_width;
52 7 unneback
   input [(addr_width-1):0]       adr;
53
   output reg [(data_width-1):0] q;
54
   input                         clk;
55 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
56 7 unneback
   parameter memory_file = "vl_rom.vmem";
57
   initial
58
     begin
59
        $readmemh(memory_file, rom);
60
     end
61
 
62
   always @ (posedge clk)
63
     q <= rom[adr];
64 5 unneback
 
65 7 unneback
endmodule
66 40 unneback
`endif
67 7 unneback
 
68 40 unneback
`ifdef RAM
69
`define MODULE ram
70 5 unneback
// Single port RAM
71 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
72
`undef MODULE
73 5 unneback
 
74
   parameter data_width = 32;
75
   parameter addr_width = 8;
76 75 unneback
   parameter mem_size = 1<<addr_width;
77 5 unneback
   input [(data_width-1):0]      d;
78
   input [(addr_width-1):0]       adr;
79
   input                         we;
80 7 unneback
   output reg [(data_width-1):0] q;
81 5 unneback
   input                         clk;
82 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0];
83 7 unneback
   parameter init = 0;
84
   parameter memory_file = "vl_ram.vmem";
85
   generate if (init) begin : init_mem
86
   initial
87
     begin
88
        $readmemh(memory_file, ram);
89
     end
90
   end
91
   endgenerate
92
 
93 5 unneback
   always @ (posedge clk)
94
   begin
95
   if (we)
96
     ram[adr] <= d;
97
   q <= ram[adr];
98
   end
99
 
100
endmodule
101 40 unneback
`endif
102 5 unneback
 
103 40 unneback
`ifdef RAM_BE
104
`define MODULE ram_be
105
module `BASE`MODULE ( d, adr, be, we, q, clk);
106
`undef MODULE
107
 
108 7 unneback
   parameter data_width = 32;
109 72 unneback
   parameter addr_width = 6;
110 75 unneback
   parameter mem_size = 1<<addr_width;
111 7 unneback
   input [(data_width-1):0]      d;
112
   input [(addr_width-1):0]       adr;
113 73 unneback
   input [(data_width/8)-1:0]    be;
114 7 unneback
   input                         we;
115
   output reg [(data_width-1):0] q;
116
   input                         clk;
117
 
118 65 unneback
//E2_ifdef SYSTEMVERILOG
119 68 unneback
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
120 65 unneback
//E2_else
121 68 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
122 65 unneback
//E2_endif
123
 
124 60 unneback
   parameter memory_init = 0;
125 7 unneback
   parameter memory_file = "vl_ram.vmem";
126 60 unneback
   generate if (memory_init) begin : init_mem
127 7 unneback
   initial
128
     begin
129
        $readmemh(memory_file, ram);
130
     end
131
   end
132
   endgenerate
133
 
134 60 unneback
//E2_ifdef SYSTEMVERILOG
135
// use a multi-dimensional packed array
136
//to model individual bytes within the word
137
 
138
always_ff@(posedge clk)
139
begin
140
    if(we) begin // note: we should have a for statement to support any bus width
141 65 unneback
        if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
142
        if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
143
        if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
144
        if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
145 60 unneback
    end
146 65 unneback
    q <= ram[adr];
147 60 unneback
end
148
 
149
//E2_else
150
 
151 7 unneback
   genvar i;
152
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
153
      always @ (posedge clk)
154
      if (we & be[i])
155
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
156
   end
157
   endgenerate
158
 
159
   always @ (posedge clk)
160
      q <= ram[adr];
161
 
162 60 unneback
//E2_endif
163
 
164 7 unneback
endmodule
165 40 unneback
`endif
166 7 unneback
 
167 5 unneback
`ifdef ACTEL
168 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
169 5 unneback
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
170
`else
171
        `define SYN
172
`endif
173
 
174 40 unneback
`ifdef DPRAM_1R1W
175
`define MODULE dpram_1r1w
176
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
177
`undef MODULE
178 5 unneback
   parameter data_width = 32;
179
   parameter addr_width = 8;
180 75 unneback
   parameter mem_size = 1<<addr_width;
181 5 unneback
   input [(data_width-1):0]      d_a;
182
   input [(addr_width-1):0]       adr_a;
183
   input [(addr_width-1):0]       adr_b;
184
   input                         we_a;
185
   output [(data_width-1):0]      q_b;
186
   input                         clk_a, clk_b;
187
   reg [(addr_width-1):0]         adr_b_reg;
188 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
189 7 unneback
 
190
   parameter init = 0;
191
   parameter memory_file = "vl_ram.vmem";
192
   generate if (init) begin : init_mem
193
   initial
194
     begin
195
        $readmemh(memory_file, ram);
196
     end
197
   end
198
   endgenerate
199
 
200 5 unneback
   always @ (posedge clk_a)
201
   if (we_a)
202
     ram[adr_a] <= d_a;
203
   always @ (posedge clk_b)
204
   adr_b_reg <= adr_b;
205
   assign q_b = ram[adr_b_reg];
206 40 unneback
 
207 5 unneback
endmodule
208 40 unneback
`endif
209 5 unneback
 
210 40 unneback
`ifdef DPRAM_2R1W
211
`define MODULE dpram_2r1w
212
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
213
`undef MODULE
214
 
215 5 unneback
   parameter data_width = 32;
216
   parameter addr_width = 8;
217 75 unneback
   parameter mem_size = 1<<addr_width;
218 5 unneback
   input [(data_width-1):0]      d_a;
219
   input [(addr_width-1):0]       adr_a;
220
   input [(addr_width-1):0]       adr_b;
221
   input                         we_a;
222
   output [(data_width-1):0]      q_b;
223
   output reg [(data_width-1):0] q_a;
224
   input                         clk_a, clk_b;
225
   reg [(data_width-1):0]         q_b;
226 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
227 7 unneback
 
228
   parameter init = 0;
229
   parameter memory_file = "vl_ram.vmem";
230
   generate if (init) begin : init_mem
231
   initial
232
     begin
233
        $readmemh(memory_file, ram);
234
     end
235
   end
236
   endgenerate
237
 
238 5 unneback
   always @ (posedge clk_a)
239
     begin
240
        q_a <= ram[adr_a];
241
        if (we_a)
242
             ram[adr_a] <= d_a;
243
     end
244
   always @ (posedge clk_b)
245
          q_b <= ram[adr_b];
246
endmodule
247 40 unneback
`endif
248 5 unneback
 
249 40 unneback
`ifdef DPRAM_2R2W
250
`define MODULE dpram_2r2w
251
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
252
`undef MODULE
253
 
254 5 unneback
   parameter data_width = 32;
255
   parameter addr_width = 8;
256 75 unneback
   parameter mem_size = 1<<addr_width;
257 5 unneback
   input [(data_width-1):0]      d_a;
258
   input [(addr_width-1):0]       adr_a;
259
   input [(addr_width-1):0]       adr_b;
260
   input                         we_a;
261
   output [(data_width-1):0]      q_b;
262
   input [(data_width-1):0]       d_b;
263
   output reg [(data_width-1):0] q_a;
264
   input                         we_b;
265
   input                         clk_a, clk_b;
266
   reg [(data_width-1):0]         q_b;
267 75 unneback
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
268 7 unneback
 
269
   parameter init = 0;
270
   parameter memory_file = "vl_ram.vmem";
271
   generate if (init) begin : init_mem
272
   initial
273
     begin
274
        $readmemh(memory_file, ram);
275
     end
276
   end
277
   endgenerate
278
 
279 5 unneback
   always @ (posedge clk_a)
280
     begin
281
        q_a <= ram[adr_a];
282
        if (we_a)
283
             ram[adr_a] <= d_a;
284
     end
285
   always @ (posedge clk_b)
286
     begin
287
        q_b <= ram[adr_b];
288
        if (we_b)
289
          ram[adr_b] <= d_b;
290
     end
291
endmodule
292 40 unneback
`endif
293 5 unneback
 
294 83 unneback
`ifdef DPRAM_MIXED_WIDTH_2R2W
295
`define MODULE dpram_mixed_width_2r2w
296
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
297
`undef MODULE
298
   parameter data_width = 32;
299
   parameter addr_width = 8;
300
   parameter data_width_ratio = 2;
301
   parameter b_data_width = data_width * data_width_ratio;
302
   parameter b_addr_width = addr_width ;
303
endmodule
304
`endif
305
 
306 75 unneback
`ifdef DPRAM_BE_2R2W
307
`define MODULE dpram_be_2r2w
308
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
309
`undef MODULE
310
 
311
   parameter a_data_width = 32;
312
   parameter a_addr_width = 8;
313
   parameter b_data_width = 64;
314
   parameter b_addr_width = 7;
315
   //parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
316
   parameter mem_size = 1024;
317
   input [(a_data_width-1):0]      d_a;
318
   input [(a_addr_width-1):0]     adr_a;
319
   input [(b_addr_width-1):0]     adr_b;
320
   input [(a_data_width/4-1):0]    be_a;
321
   input                         we_a;
322
   output [(b_data_width-1):0]    q_b;
323
   input [(b_data_width-1):0]     d_b;
324
   output reg [(a_data_width-1):0] q_a;
325
   input [(b_data_width/4-1):0]    be_b;
326
   input                         we_b;
327
   input                         clk_a, clk_b;
328
   reg [(b_data_width-1):0]       q_b;
329
 
330
generate
331
if (a_data_width==32 & b_data_width==64) begin : inst32to64
332
 
333 77 unneback
    wire [63:0] tmp;
334 75 unneback
    `define MODULE dpram_2r2w
335
    `BASE`MODULE
336
    # (.data_width(8), .addr_width(b_addr_width-3))
337
    ram0 (
338
        .d_a(d_a[7:0]),
339
        .q_a(tmp[7:0]),
340
        .adr_a(adr_a[a_addr_width-3-1:0]),
341
        .we_a(we_a & be_a[0] & !adr_a[0]),
342
        .clk_a(clk_a),
343
        .d_b(d_b[7:0]),
344
        .q_b(q_b[7:0]),
345
        .adr_b(adr_b[b_addr_width-3-1:0]),
346
        .we_b(we_b),
347
        .clk_b(clk_b) );
348
    `BASE`MODULE
349
    # (.data_width(8), .addr_width(b_addr_width-3))
350
    ram1 (
351
        .d_a(d_a[7:0]),
352
        .q_a(tmp[7:0]),
353
        .adr_a(adr_a[a_addr_width-3-1:0]),
354
        .we_a(we_a),
355
        .clk_a(clk_a),
356
        .d_b(d_b[7:0]),
357
        .q_b(q_b[7:0]),
358
        .adr_b(adr_b[b_addr_width-3-1:0]),
359
        .we_b(we_b),
360
        .clk_b(clk_b) );
361
    `BASE`MODULE
362
    # (.data_width(8), .addr_width(b_addr_width-3))
363
    ram2 (
364
        .d_a(d_a[15:8]),
365
        .q_a(tmp[7:0]),
366
        .adr_a(adr_a[a_addr_width-3-1:0]),
367
        .we_a(we_a),
368
        .clk_a(clk_a),
369
        .d_b(d_b[7:0]),
370
        .q_b(q_b[7:0]),
371
        .adr_b(adr_b[b_addr_width-3-1:0]),
372
        .we_b(we_b),
373
        .clk_b(clk_b) );
374
    `BASE`MODULE
375
    # (.data_width(8), .addr_width(b_addr_width-3))
376
    ram3 (
377
        .d_a(d_a[15:8]),
378
        .q_a(tmp[7:0]),
379
        .adr_a(adr_a[a_addr_width-3-1:0]),
380
        .we_a(we_a),
381
        .clk_a(clk_a),
382
        .d_b(d_b[7:0]),
383
        .q_b(q_b[7:0]),
384
        .adr_b(adr_b[b_addr_width-3-1:0]),
385
        .we_b(we_b),
386
        .clk_b(clk_b) );
387
    `BASE`MODULE
388
    # (.data_width(8), .addr_width(b_addr_width-3))
389
    ram4 (
390
        .d_a(d_a[23:16]),
391
        .q_a(tmp[7:0]),
392
        .adr_a(adr_a[a_addr_width-3-1:0]),
393
        .we_a(we_a),
394
        .clk_a(clk_a),
395
        .d_b(d_b[7:0]),
396
        .q_b(q_b[7:0]),
397
        .adr_b(adr_b[b_addr_width-3-1:0]),
398
        .we_b(we_b),
399
        .clk_b(clk_b) );
400
    `BASE`MODULE
401
    # (.data_width(8), .addr_width(b_addr_width-3))
402
    ram5 (
403
        .d_a(d_a[23:16]),
404
        .q_a(tmp[7:0]),
405
        .adr_a(adr_a[a_addr_width-3-1:0]),
406
        .we_a(we_a),
407
        .clk_a(clk_a),
408
        .d_b(d_b[7:0]),
409
        .q_b(q_b[7:0]),
410
        .adr_b(adr_b[b_addr_width-3-1:0]),
411
        .we_b(we_b),
412
        .clk_b(clk_b) );
413
    `BASE`MODULE
414
    # (.data_width(8), .addr_width(b_addr_width-3))
415
    ram6 (
416
        .d_a(d_a[31:24]),
417
        .q_a(tmp[7:0]),
418
        .adr_a(adr_a[a_addr_width-3-1:0]),
419
        .we_a(we_a),
420
        .clk_a(clk_a),
421
        .d_b(d_b[7:0]),
422
        .q_b(q_b[7:0]),
423
        .adr_b(adr_b[b_addr_width-3-1:0]),
424
        .we_b(we_b),
425
        .clk_b(clk_b) );
426
    `BASE`MODULE
427
    # (.data_width(8), .addr_width(b_addr_width-3))
428
    ram7 (
429
        .d_a(d_a[31:24]),
430
        .q_a(tmp[7:0]),
431
        .adr_a(adr_a[a_addr_width-3-1:0]),
432
        .we_a(we_a),
433
        .clk_a(clk_a),
434
        .d_b(d_b[7:0]),
435
        .q_b(q_b[7:0]),
436
        .adr_b(adr_b[b_addr_width-3-1:0]),
437
        .we_b(we_b),
438
        .clk_b(clk_b) );
439
`undef MODULE
440
/*
441
   reg [7:0] ram0 [mem_size/8-1:0];
442
   wire [7:0] wea, web;
443
   assign wea = we_a & be_a[0];
444
   assign web = we_b & be_b[0];
445
   always @ (posedge clk_a)
446
    if (wea)
447
        ram0[adr_a] <= d_a[7:0];
448
    always @ (posedge clk_a)
449
        q_a[7:0] <= ram0[adr_a];
450
   always @ (posedge clk_a)
451
    if (web)
452
        ram0[adr_b] <= d_b[7:0];
453
    always @ (posedge clk_b)
454
        q_b[7:0] <= ram0[adr_b];
455
*/
456
end
457
endgenerate
458
/*
459
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_rama
460
      always @ (posedge clk_a)
461
      if (we_a & be_a[i])
462
        ram[adr_a][(i+1)*8-1:i*8] <= d_a[(i+1)*8-1:i*8];
463
   end
464
   endgenerate
465
 
466
   always @ (posedge clk_a)
467
      q_a <= ram[adr_a];
468
 
469
   genvar i;
470
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ramb
471
      always @ (posedge clk_a)
472
      if (we_b & be_b[i])
473
        ram[adr_b][(i+1)*8-1:i*8] <= d_b[(i+1)*8-1:i*8];
474
   end
475
   endgenerate
476
 
477
   always @ (posedge clk_b)
478
      q_b <= ram[adr_b];
479
*/
480
/*
481
   always @ (posedge clk_a)
482
     begin
483
        q_a <= ram[adr_a];
484
        if (we_a)
485
             ram[adr_a] <= d_a;
486
     end
487
   always @ (posedge clk_b)
488
     begin
489
        q_b <= ram[adr_b];
490
        if (we_b)
491
          ram[adr_b] <= d_b;
492
     end
493
*/
494
endmodule
495
`endif
496
 
497 5 unneback
// Content addresable memory, CAM
498
 
499 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
500 5 unneback
// FIFO
501 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
502
module `BASE`MODULE (
503
`undef MODULE
504 25 unneback
    d, wr, fifo_full,
505
    q, rd, fifo_empty,
506
    fill_level,
507
    clk, rst
508
    );
509
 
510
parameter data_width = 18;
511
parameter addr_width = 4;
512 5 unneback
 
513 25 unneback
// write side
514
input  [data_width-1:0] d;
515
input                   wr;
516
output                  fifo_full;
517
// read side
518
output [data_width-1:0] q;
519
input                   rd;
520
output                  fifo_empty;
521
// common
522
output [addr_width:0]   fill_level;
523
input rst, clk;
524
 
525
wire [addr_width:1] wadr, radr;
526
 
527 40 unneback
`define MODULE cnt_bin_ce
528
`BASE`MODULE
529 25 unneback
    # ( .length(addr_width))
530
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
531 40 unneback
`BASE`MODULE
532 25 unneback
    # (.length(addr_width))
533
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
534 40 unneback
`undef MODULE
535 25 unneback
 
536 40 unneback
`define MODULE dpram_1r1w
537
`BASE`MODULE
538 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
539
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
540 40 unneback
`undef MODULE
541 25 unneback
 
542 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
543
`BASE`MODULE
544 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
545 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
546 40 unneback
`undef MODULE
547 25 unneback
endmodule
548 40 unneback
`endif
549 25 unneback
 
550 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
551 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
552
// RAM is supposed to be larger than the two FIFOs
553
// LFSR counters used adr pointers
554 40 unneback
`define MODULE fifo_2r2w_sync_simplex
555
module `BASE`MODULE (
556
`undef MODULE
557 27 unneback
    // a side
558
    a_d, a_wr, a_fifo_full,
559
    a_q, a_rd, a_fifo_empty,
560
    a_fill_level,
561
    // b side
562
    b_d, b_wr, b_fifo_full,
563
    b_q, b_rd, b_fifo_empty,
564
    b_fill_level,
565
    // common
566
    clk, rst
567
    );
568
parameter data_width = 8;
569
parameter addr_width = 5;
570
parameter fifo_full_level = (1<<addr_width)-1;
571
 
572
// a side
573
input  [data_width-1:0] a_d;
574
input                   a_wr;
575
output                  a_fifo_full;
576
output [data_width-1:0] a_q;
577
input                   a_rd;
578
output                  a_fifo_empty;
579
output [addr_width-1:0] a_fill_level;
580
 
581
// b side
582
input  [data_width-1:0] b_d;
583
input                   b_wr;
584
output                  b_fifo_full;
585
output [data_width-1:0] b_q;
586
input                   b_rd;
587
output                  b_fifo_empty;
588
output [addr_width-1:0] b_fill_level;
589
 
590
input                   clk;
591
input                   rst;
592
 
593
// adr_gen
594
wire [addr_width:1] a_wadr, a_radr;
595
wire [addr_width:1] b_wadr, b_radr;
596
// dpram
597
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
598
 
599 40 unneback
`define MODULE cnt_lfsr_ce
600
`BASE`MODULE
601 27 unneback
    # ( .length(addr_width))
602
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
603
 
604 40 unneback
`BASE`MODULE
605 27 unneback
    # (.length(addr_width))
606
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
607
 
608 40 unneback
`BASE`MODULE
609 27 unneback
    # ( .length(addr_width))
610
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
611
 
612 40 unneback
`BASE`MODULE
613 27 unneback
    # (.length(addr_width))
614
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
615 40 unneback
`undef MODULE
616 27 unneback
 
617
// mux read or write adr to DPRAM
618
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
619
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
620
 
621 40 unneback
`define MODULE dpram_2r2w
622
`BASE`MODULE
623 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
624
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
625
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
626 40 unneback
`undef MODULE
627
 
628
`define MODULE cnt_bin_ce_rew_zq_l1
629
`BASE`MODULE
630 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
631 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
632
 
633 40 unneback
`BASE`MODULE
634 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
635 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
636 40 unneback
`undef MODULE
637 27 unneback
 
638
endmodule
639 40 unneback
`endif
640 27 unneback
 
641 40 unneback
`ifdef FIFO_CMP_ASYNC
642
`define MODULE fifo_cmp_async
643
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
644
`undef MODULE
645 5 unneback
 
646 11 unneback
   parameter addr_width = 4;
647
   parameter N = addr_width-1;
648 5 unneback
 
649
   parameter Q1 = 2'b00;
650
   parameter Q2 = 2'b01;
651
   parameter Q3 = 2'b11;
652
   parameter Q4 = 2'b10;
653
 
654
   parameter going_empty = 1'b0;
655
   parameter going_full  = 1'b1;
656
 
657
   input [N:0]  wptr, rptr;
658 14 unneback
   output       fifo_empty;
659 5 unneback
   output       fifo_full;
660
   input        wclk, rclk, rst;
661
 
662
`ifndef GENERATE_DIRECTION_AS_LATCH
663
   wire direction;
664
`endif
665
`ifdef GENERATE_DIRECTION_AS_LATCH
666
   reg direction;
667
`endif
668
   reg  direction_set, direction_clr;
669
 
670
   wire async_empty, async_full;
671
   wire fifo_full2;
672 14 unneback
   wire fifo_empty2;
673 5 unneback
 
674
   // direction_set
675
   always @ (wptr[N:N-1] or rptr[N:N-1])
676
     case ({wptr[N:N-1],rptr[N:N-1]})
677
       {Q1,Q2} : direction_set <= 1'b1;
678
       {Q2,Q3} : direction_set <= 1'b1;
679
       {Q3,Q4} : direction_set <= 1'b1;
680
       {Q4,Q1} : direction_set <= 1'b1;
681
       default : direction_set <= 1'b0;
682
     endcase
683
 
684
   // direction_clear
685
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
686
     if (rst)
687
       direction_clr <= 1'b1;
688
     else
689
       case ({wptr[N:N-1],rptr[N:N-1]})
690
         {Q2,Q1} : direction_clr <= 1'b1;
691
         {Q3,Q2} : direction_clr <= 1'b1;
692
         {Q4,Q3} : direction_clr <= 1'b1;
693
         {Q1,Q4} : direction_clr <= 1'b1;
694
         default : direction_clr <= 1'b0;
695
       endcase
696
 
697 40 unneback
`define MODULE dff_sr
698 5 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
699 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
700 5 unneback
`endif
701
 
702
`ifdef GENERATE_DIRECTION_AS_LATCH
703
   always @ (posedge direction_set or posedge direction_clr)
704
     if (direction_clr)
705
       direction <= going_empty;
706
     else
707
       direction <= going_full;
708
`endif
709
 
710
   assign async_empty = (wptr == rptr) && (direction==going_empty);
711
   assign async_full  = (wptr == rptr) && (direction==going_full);
712
 
713 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
714
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
715
`undef MODULE
716 5 unneback
 
717
/*
718
   always @ (posedge wclk or posedge rst or posedge async_full)
719
     if (rst)
720
       {fifo_full, fifo_full2} <= 2'b00;
721
     else if (async_full)
722
       {fifo_full, fifo_full2} <= 2'b11;
723
     else
724
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
725
*/
726 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
727 5 unneback
     if (async_empty)
728
       {fifo_empty, fifo_empty2} <= 2'b11;
729
     else
730 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
731 40 unneback
`define MODULE dff
732
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
733
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
734
`undef MODULE
735 25 unneback
endmodule // async_compb
736 40 unneback
`endif
737 5 unneback
 
738 40 unneback
`ifdef FIFO_1R1W_ASYNC
739
`define MODULE fifo_1r1w_async
740
module `BASE`MODULE (
741
`undef MODULE
742 5 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
743
    q, rd, fifo_empty, rd_clk, rd_rst
744
    );
745
 
746
parameter data_width = 18;
747
parameter addr_width = 4;
748
 
749
// write side
750
input  [data_width-1:0] d;
751
input                   wr;
752
output                  fifo_full;
753
input                   wr_clk;
754
input                   wr_rst;
755
// read side
756
output [data_width-1:0] q;
757
input                   rd;
758
output                  fifo_empty;
759
input                   rd_clk;
760
input                   rd_rst;
761
 
762
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
763 23 unneback
 
764 40 unneback
`define MODULE cnt_gray_ce_bin
765
`BASE`MODULE
766 5 unneback
    # ( .length(addr_width))
767
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
768
 
769 40 unneback
`BASE`MODULE
770 5 unneback
    # (.length(addr_width))
771 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
772 40 unneback
`undef MODULE
773 5 unneback
 
774 40 unneback
`define MODULE dpram_1r1w
775
`BASE`MODULE
776 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
777
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
778 40 unneback
`undef MODULE
779 5 unneback
 
780 40 unneback
`define MODULE fifo_cmp_async
781
`BASE`MODULE
782 5 unneback
    # (.addr_width(addr_width))
783
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
784 40 unneback
`undef MODULE
785 5 unneback
 
786
endmodule
787 40 unneback
`endif
788 5 unneback
 
789 40 unneback
`ifdef FIFO_2R2W_ASYNC
790
`define MODULE fifo_2r2w_async
791
module `BASE`MODULE (
792
`undef MODULE
793 5 unneback
    // a side
794
    a_d, a_wr, a_fifo_full,
795
    a_q, a_rd, a_fifo_empty,
796
    a_clk, a_rst,
797
    // b side
798
    b_d, b_wr, b_fifo_full,
799
    b_q, b_rd, b_fifo_empty,
800
    b_clk, b_rst
801
    );
802
 
803
parameter data_width = 18;
804
parameter addr_width = 4;
805
 
806
// a side
807
input  [data_width-1:0] a_d;
808
input                   a_wr;
809
output                  a_fifo_full;
810
output [data_width-1:0] a_q;
811
input                   a_rd;
812
output                  a_fifo_empty;
813
input                   a_clk;
814
input                   a_rst;
815
 
816
// b side
817
input  [data_width-1:0] b_d;
818
input                   b_wr;
819
output                  b_fifo_full;
820
output [data_width-1:0] b_q;
821
input                   b_rd;
822
output                  b_fifo_empty;
823
input                   b_clk;
824
input                   b_rst;
825
 
826 40 unneback
`define MODULE fifo_1r1w_async
827
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
828 5 unneback
vl_fifo_1r1w_async_a (
829
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
830
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
831
    );
832
 
833 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
834 5 unneback
vl_fifo_1r1w_async_b (
835
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
836
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
837
    );
838 40 unneback
`undef MODULE
839
 
840 5 unneback
endmodule
841 40 unneback
`endif
842 5 unneback
 
843 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
844
`define MODULE fifo_2r2w_async_simplex
845
module `BASE`MODULE (
846
`undef MODULE
847 5 unneback
    // a side
848
    a_d, a_wr, a_fifo_full,
849
    a_q, a_rd, a_fifo_empty,
850
    a_clk, a_rst,
851
    // b side
852
    b_d, b_wr, b_fifo_full,
853
    b_q, b_rd, b_fifo_empty,
854
    b_clk, b_rst
855
    );
856
 
857
parameter data_width = 18;
858
parameter addr_width = 4;
859
 
860
// a side
861
input  [data_width-1:0] a_d;
862
input                   a_wr;
863
output                  a_fifo_full;
864
output [data_width-1:0] a_q;
865
input                   a_rd;
866
output                  a_fifo_empty;
867
input                   a_clk;
868
input                   a_rst;
869
 
870
// b side
871
input  [data_width-1:0] b_d;
872
input                   b_wr;
873
output                  b_fifo_full;
874
output [data_width-1:0] b_q;
875
input                   b_rd;
876
output                  b_fifo_empty;
877
input                   b_clk;
878
input                   b_rst;
879
 
880
// adr_gen
881
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
882
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
883
// dpram
884
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
885
 
886 40 unneback
`define MODULE cnt_gray_ce_bin
887
`BASE`MODULE
888 5 unneback
    # ( .length(addr_width))
889
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
890
 
891 40 unneback
`BASE`MODULE
892 5 unneback
    # (.length(addr_width))
893
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
894
 
895 40 unneback
`BASE`MODULE
896 5 unneback
    # ( .length(addr_width))
897
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
898
 
899 40 unneback
`BASE`MODULE
900 5 unneback
    # (.length(addr_width))
901
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
902 40 unneback
`undef MODULE
903 5 unneback
 
904
// mux read or write adr to DPRAM
905
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
906
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
907
 
908 40 unneback
`define MODULE dpram_2r2w
909
`BASE`MODULE
910 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
911
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
912
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
913 40 unneback
`undef MODULE
914 5 unneback
 
915 40 unneback
`define MODULE fifo_cmp_async
916
`BASE`MODULE
917 5 unneback
    # (.addr_width(addr_width))
918
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
919
 
920 40 unneback
`BASE`MODULE
921 5 unneback
    # (.addr_width(addr_width))
922
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
923 40 unneback
`undef MODULE
924 5 unneback
 
925
endmodule
926 40 unneback
`endif
927 48 unneback
 
928
`ifdef REG_FILE
929
`define MODULE reg_file
930
module `BASE`MODULE (
931
`undef MODULE
932
    a1, a2, a3, wd3, we3, rd1, rd2, clk
933
);
934
parameter data_width = 32;
935
parameter addr_width = 5;
936
input [addr_width-1:0] a1, a2, a3;
937
input [data_width-1:0] wd3;
938
input we3;
939
output [data_width-1:0] rd1, rd2;
940
input clk;
941
 
942
`ifdef ACTEL
943
reg [data_width-1:0] wd3_reg;
944
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
945
reg we3_reg;
946
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
947
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
948
always @ (posedge clk or posedge rst)
949
if (rst)
950
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
951
else
952
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
953
 
954
    always @ (negedge clk)
955
    if (we3_reg)
956
        ram1[a3_reg] <= wd3;
957
    always @ (posedge clk)
958
        a1_reg <= a1;
959
    assign rd1 = ram1[a1_reg];
960
 
961
    always @ (negedge clk)
962
    if (we3_reg)
963
        ram2[a3_reg] <= wd3;
964
    always @ (posedge clk)
965
        a2_reg <= a2;
966
    assign rd2 = ram2[a2_reg];
967
 
968
`else
969
 
970
`define MODULE dpram_1r1w
971
`BASE`MODULE
972
    # ( .data_width(data_width), .addr_width(addr_width))
973
    ram1 (
974
        .d_a(wd3),
975
        .adr_a(a3),
976
        .we_a(we3),
977
        .clk_a(clk),
978
        .q_b(rd1),
979
        .adr_b(a1),
980
        .clk_b(clk) );
981
 
982
`BASE`MODULE
983
    # ( .data_width(data_width), .addr_width(addr_width))
984
    ram2 (
985
        .d_a(wd3),
986
        .adr_a(a3),
987
        .we_a(we3),
988
        .clk_a(clk),
989
        .q_b(rd2),
990
        .adr_b(a2),
991
        .clk_b(clk) );
992
`undef MODULE
993
 
994
`endif
995
 
996
endmodule
997
`endif

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