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1 5 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, memories                                 ////
4
////                                                              ////
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////  Description                                                 ////
6
////  memories                                                    ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more memory types                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef ROM_INIT
44 5 unneback
/// ROM
45 40 unneback
`define MODULE rom_init
46
module `BASE`MODULE ( adr, q, clk);
47
`undef MODULE
48 5 unneback
 
49 7 unneback
   parameter data_width = 32;
50
   parameter addr_width = 8;
51 75 unneback
   parameter mem_size = 1<<addr_width;
52 7 unneback
   input [(addr_width-1):0]       adr;
53
   output reg [(data_width-1):0] q;
54
   input                         clk;
55 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
56 7 unneback
   parameter memory_file = "vl_rom.vmem";
57
   initial
58
     begin
59
        $readmemh(memory_file, rom);
60
     end
61
 
62
   always @ (posedge clk)
63
     q <= rom[adr];
64 5 unneback
 
65 7 unneback
endmodule
66 40 unneback
`endif
67 7 unneback
 
68 40 unneback
`ifdef RAM
69
`define MODULE ram
70 5 unneback
// Single port RAM
71 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
72
`undef MODULE
73 5 unneback
 
74
   parameter data_width = 32;
75
   parameter addr_width = 8;
76 75 unneback
   parameter mem_size = 1<<addr_width;
77 5 unneback
   input [(data_width-1):0]      d;
78
   input [(addr_width-1):0]       adr;
79
   input                         we;
80 7 unneback
   output reg [(data_width-1):0] q;
81 5 unneback
   input                         clk;
82 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0];
83 7 unneback
   parameter init = 0;
84
   parameter memory_file = "vl_ram.vmem";
85
   generate if (init) begin : init_mem
86
   initial
87
     begin
88
        $readmemh(memory_file, ram);
89
     end
90
   end
91
   endgenerate
92
 
93 5 unneback
   always @ (posedge clk)
94
   begin
95
   if (we)
96
     ram[adr] <= d;
97
   q <= ram[adr];
98
   end
99
 
100
endmodule
101 40 unneback
`endif
102 5 unneback
 
103 40 unneback
`ifdef RAM_BE
104
`define MODULE ram_be
105
module `BASE`MODULE ( d, adr, be, we, q, clk);
106
`undef MODULE
107
 
108 7 unneback
   parameter data_width = 32;
109 72 unneback
   parameter addr_width = 6;
110 75 unneback
   parameter mem_size = 1<<addr_width;
111 7 unneback
   input [(data_width-1):0]      d;
112
   input [(addr_width-1):0]       adr;
113 73 unneback
   input [(data_width/8)-1:0]    be;
114 7 unneback
   input                         we;
115
   output reg [(data_width-1):0] q;
116
   input                         clk;
117
 
118 84 unneback
 
119 65 unneback
//E2_ifdef SYSTEMVERILOG
120 68 unneback
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
121 65 unneback
//E2_else
122 84 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
123
    wire [data_width/8-1:0] cke;
124 65 unneback
//E2_endif
125
 
126 60 unneback
   parameter memory_init = 0;
127 7 unneback
   parameter memory_file = "vl_ram.vmem";
128 60 unneback
   generate if (memory_init) begin : init_mem
129 7 unneback
   initial
130
     begin
131
        $readmemh(memory_file, ram);
132
     end
133
   end
134
   endgenerate
135
 
136 60 unneback
//E2_ifdef SYSTEMVERILOG
137
// use a multi-dimensional packed array
138
//to model individual bytes within the word
139
 
140
always_ff@(posedge clk)
141
begin
142
    if(we) begin // note: we should have a for statement to support any bus width
143 85 unneback
        if(be[3]) ram[adr[3] <= d[31:24];
144
        if(be[2]) ram[adr[2] <= d[23:16];
145
        if(be[1]) ram[adr[1] <= d[15:8];
146
        if(be[0]) ram[adr[0] <= d[7:0];
147 60 unneback
    end
148 65 unneback
    q <= ram[adr];
149 60 unneback
end
150
 
151
//E2_else
152
 
153 84 unneback
assign cke = {data_width/8{we}} & be;
154 7 unneback
   genvar i;
155 84 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
156 7 unneback
      always @ (posedge clk)
157 84 unneback
      if (cke[i])
158 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
159
   end
160
   endgenerate
161
 
162
   always @ (posedge clk)
163
      q <= ram[adr];
164
 
165 60 unneback
//E2_endif
166
 
167 84 unneback
   // Function to access RAM (for use by Verilator).
168
   function [31:0] get_mem;
169
      // verilator public
170
      input [aw-1:0]             addr;
171
      get_mem = ram[addr];
172
   endfunction // get_mem
173
 
174
   // Function to write RAM (for use by Verilator).
175
   function set_mem;
176
      // verilator public
177
      input [aw-1:0]             addr;
178
      input [dw-1:0]             data;
179
      ram[addr] = data;
180
   endfunction // set_mem
181
 
182 7 unneback
endmodule
183 40 unneback
`endif
184 7 unneback
 
185 5 unneback
`ifdef ACTEL
186 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
187 5 unneback
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
188
`else
189
        `define SYN
190
`endif
191
 
192 40 unneback
`ifdef DPRAM_1R1W
193
`define MODULE dpram_1r1w
194
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
195
`undef MODULE
196 5 unneback
   parameter data_width = 32;
197
   parameter addr_width = 8;
198 75 unneback
   parameter mem_size = 1<<addr_width;
199 5 unneback
   input [(data_width-1):0]      d_a;
200
   input [(addr_width-1):0]       adr_a;
201
   input [(addr_width-1):0]       adr_b;
202
   input                         we_a;
203
   output [(data_width-1):0]      q_b;
204
   input                         clk_a, clk_b;
205
   reg [(addr_width-1):0]         adr_b_reg;
206 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
207 7 unneback
 
208
   parameter init = 0;
209
   parameter memory_file = "vl_ram.vmem";
210
   generate if (init) begin : init_mem
211
   initial
212
     begin
213
        $readmemh(memory_file, ram);
214
     end
215
   end
216
   endgenerate
217
 
218 5 unneback
   always @ (posedge clk_a)
219
   if (we_a)
220
     ram[adr_a] <= d_a;
221
   always @ (posedge clk_b)
222
   adr_b_reg <= adr_b;
223
   assign q_b = ram[adr_b_reg];
224 40 unneback
 
225 5 unneback
endmodule
226 40 unneback
`endif
227 5 unneback
 
228 40 unneback
`ifdef DPRAM_2R1W
229
`define MODULE dpram_2r1w
230
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
231
`undef MODULE
232
 
233 5 unneback
   parameter data_width = 32;
234
   parameter addr_width = 8;
235 75 unneback
   parameter mem_size = 1<<addr_width;
236 5 unneback
   input [(data_width-1):0]      d_a;
237
   input [(addr_width-1):0]       adr_a;
238
   input [(addr_width-1):0]       adr_b;
239
   input                         we_a;
240
   output [(data_width-1):0]      q_b;
241
   output reg [(data_width-1):0] q_a;
242
   input                         clk_a, clk_b;
243
   reg [(data_width-1):0]         q_b;
244 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
245 7 unneback
 
246
   parameter init = 0;
247
   parameter memory_file = "vl_ram.vmem";
248
   generate if (init) begin : init_mem
249
   initial
250
     begin
251
        $readmemh(memory_file, ram);
252
     end
253
   end
254
   endgenerate
255
 
256 5 unneback
   always @ (posedge clk_a)
257
     begin
258
        q_a <= ram[adr_a];
259
        if (we_a)
260
             ram[adr_a] <= d_a;
261
     end
262
   always @ (posedge clk_b)
263
          q_b <= ram[adr_b];
264
endmodule
265 40 unneback
`endif
266 5 unneback
 
267 40 unneback
`ifdef DPRAM_2R2W
268
`define MODULE dpram_2r2w
269
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
270
`undef MODULE
271
 
272 5 unneback
   parameter data_width = 32;
273
   parameter addr_width = 8;
274 75 unneback
   parameter mem_size = 1<<addr_width;
275 5 unneback
   input [(data_width-1):0]      d_a;
276
   input [(addr_width-1):0]       adr_a;
277
   input [(addr_width-1):0]       adr_b;
278
   input                         we_a;
279
   output [(data_width-1):0]      q_b;
280
   input [(data_width-1):0]       d_b;
281
   output reg [(data_width-1):0] q_a;
282
   input                         we_b;
283
   input                         clk_a, clk_b;
284
   reg [(data_width-1):0]         q_b;
285 75 unneback
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
286 7 unneback
 
287
   parameter init = 0;
288
   parameter memory_file = "vl_ram.vmem";
289
   generate if (init) begin : init_mem
290
   initial
291
     begin
292
        $readmemh(memory_file, ram);
293
     end
294
   end
295
   endgenerate
296
 
297 5 unneback
   always @ (posedge clk_a)
298
     begin
299
        q_a <= ram[adr_a];
300
        if (we_a)
301
             ram[adr_a] <= d_a;
302
     end
303
   always @ (posedge clk_b)
304
     begin
305
        q_b <= ram[adr_b];
306
        if (we_b)
307
          ram[adr_b] <= d_b;
308
     end
309
endmodule
310 40 unneback
`endif
311 5 unneback
 
312 83 unneback
`ifdef DPRAM_MIXED_WIDTH_2R2W
313
`define MODULE dpram_mixed_width_2r2w
314
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
315
`undef MODULE
316
   parameter data_width = 32;
317
   parameter addr_width = 8;
318
   parameter data_width_ratio = 2;
319
   parameter b_data_width = data_width * data_width_ratio;
320
   parameter b_addr_width = addr_width ;
321
endmodule
322
`endif
323
 
324 75 unneback
`ifdef DPRAM_BE_2R2W
325
`define MODULE dpram_be_2r2w
326
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
327
`undef MODULE
328
 
329
   parameter a_data_width = 32;
330
   parameter a_addr_width = 8;
331
   parameter b_data_width = 64;
332
   parameter b_addr_width = 7;
333
   //parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
334
   parameter mem_size = 1024;
335
   input [(a_data_width-1):0]      d_a;
336
   input [(a_addr_width-1):0]     adr_a;
337
   input [(b_addr_width-1):0]     adr_b;
338
   input [(a_data_width/4-1):0]    be_a;
339
   input                         we_a;
340
   output [(b_data_width-1):0]    q_b;
341
   input [(b_data_width-1):0]     d_b;
342
   output reg [(a_data_width-1):0] q_a;
343
   input [(b_data_width/4-1):0]    be_b;
344
   input                         we_b;
345
   input                         clk_a, clk_b;
346
   reg [(b_data_width-1):0]       q_b;
347
 
348
generate
349
if (a_data_width==32 & b_data_width==64) begin : inst32to64
350
 
351 77 unneback
    wire [63:0] tmp;
352 75 unneback
    `define MODULE dpram_2r2w
353
    `BASE`MODULE
354
    # (.data_width(8), .addr_width(b_addr_width-3))
355
    ram0 (
356
        .d_a(d_a[7:0]),
357
        .q_a(tmp[7:0]),
358
        .adr_a(adr_a[a_addr_width-3-1:0]),
359
        .we_a(we_a & be_a[0] & !adr_a[0]),
360
        .clk_a(clk_a),
361
        .d_b(d_b[7:0]),
362
        .q_b(q_b[7:0]),
363
        .adr_b(adr_b[b_addr_width-3-1:0]),
364
        .we_b(we_b),
365
        .clk_b(clk_b) );
366
    `BASE`MODULE
367
    # (.data_width(8), .addr_width(b_addr_width-3))
368
    ram1 (
369
        .d_a(d_a[7:0]),
370
        .q_a(tmp[7:0]),
371
        .adr_a(adr_a[a_addr_width-3-1:0]),
372
        .we_a(we_a),
373
        .clk_a(clk_a),
374
        .d_b(d_b[7:0]),
375
        .q_b(q_b[7:0]),
376
        .adr_b(adr_b[b_addr_width-3-1:0]),
377
        .we_b(we_b),
378
        .clk_b(clk_b) );
379
    `BASE`MODULE
380
    # (.data_width(8), .addr_width(b_addr_width-3))
381
    ram2 (
382
        .d_a(d_a[15:8]),
383
        .q_a(tmp[7:0]),
384
        .adr_a(adr_a[a_addr_width-3-1:0]),
385
        .we_a(we_a),
386
        .clk_a(clk_a),
387
        .d_b(d_b[7:0]),
388
        .q_b(q_b[7:0]),
389
        .adr_b(adr_b[b_addr_width-3-1:0]),
390
        .we_b(we_b),
391
        .clk_b(clk_b) );
392
    `BASE`MODULE
393
    # (.data_width(8), .addr_width(b_addr_width-3))
394
    ram3 (
395
        .d_a(d_a[15:8]),
396
        .q_a(tmp[7:0]),
397
        .adr_a(adr_a[a_addr_width-3-1:0]),
398
        .we_a(we_a),
399
        .clk_a(clk_a),
400
        .d_b(d_b[7:0]),
401
        .q_b(q_b[7:0]),
402
        .adr_b(adr_b[b_addr_width-3-1:0]),
403
        .we_b(we_b),
404
        .clk_b(clk_b) );
405
    `BASE`MODULE
406
    # (.data_width(8), .addr_width(b_addr_width-3))
407
    ram4 (
408
        .d_a(d_a[23:16]),
409
        .q_a(tmp[7:0]),
410
        .adr_a(adr_a[a_addr_width-3-1:0]),
411
        .we_a(we_a),
412
        .clk_a(clk_a),
413
        .d_b(d_b[7:0]),
414
        .q_b(q_b[7:0]),
415
        .adr_b(adr_b[b_addr_width-3-1:0]),
416
        .we_b(we_b),
417
        .clk_b(clk_b) );
418
    `BASE`MODULE
419
    # (.data_width(8), .addr_width(b_addr_width-3))
420
    ram5 (
421
        .d_a(d_a[23:16]),
422
        .q_a(tmp[7:0]),
423
        .adr_a(adr_a[a_addr_width-3-1:0]),
424
        .we_a(we_a),
425
        .clk_a(clk_a),
426
        .d_b(d_b[7:0]),
427
        .q_b(q_b[7:0]),
428
        .adr_b(adr_b[b_addr_width-3-1:0]),
429
        .we_b(we_b),
430
        .clk_b(clk_b) );
431
    `BASE`MODULE
432
    # (.data_width(8), .addr_width(b_addr_width-3))
433
    ram6 (
434
        .d_a(d_a[31:24]),
435
        .q_a(tmp[7:0]),
436
        .adr_a(adr_a[a_addr_width-3-1:0]),
437
        .we_a(we_a),
438
        .clk_a(clk_a),
439
        .d_b(d_b[7:0]),
440
        .q_b(q_b[7:0]),
441
        .adr_b(adr_b[b_addr_width-3-1:0]),
442
        .we_b(we_b),
443
        .clk_b(clk_b) );
444
    `BASE`MODULE
445
    # (.data_width(8), .addr_width(b_addr_width-3))
446
    ram7 (
447
        .d_a(d_a[31:24]),
448
        .q_a(tmp[7:0]),
449
        .adr_a(adr_a[a_addr_width-3-1:0]),
450
        .we_a(we_a),
451
        .clk_a(clk_a),
452
        .d_b(d_b[7:0]),
453
        .q_b(q_b[7:0]),
454
        .adr_b(adr_b[b_addr_width-3-1:0]),
455
        .we_b(we_b),
456
        .clk_b(clk_b) );
457
`undef MODULE
458
/*
459
   reg [7:0] ram0 [mem_size/8-1:0];
460
   wire [7:0] wea, web;
461
   assign wea = we_a & be_a[0];
462
   assign web = we_b & be_b[0];
463
   always @ (posedge clk_a)
464
    if (wea)
465
        ram0[adr_a] <= d_a[7:0];
466
    always @ (posedge clk_a)
467
        q_a[7:0] <= ram0[adr_a];
468
   always @ (posedge clk_a)
469
    if (web)
470
        ram0[adr_b] <= d_b[7:0];
471
    always @ (posedge clk_b)
472
        q_b[7:0] <= ram0[adr_b];
473
*/
474
end
475
endgenerate
476
/*
477
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_rama
478
      always @ (posedge clk_a)
479
      if (we_a & be_a[i])
480
        ram[adr_a][(i+1)*8-1:i*8] <= d_a[(i+1)*8-1:i*8];
481
   end
482
   endgenerate
483
 
484
   always @ (posedge clk_a)
485
      q_a <= ram[adr_a];
486
 
487
   genvar i;
488
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ramb
489
      always @ (posedge clk_a)
490
      if (we_b & be_b[i])
491
        ram[adr_b][(i+1)*8-1:i*8] <= d_b[(i+1)*8-1:i*8];
492
   end
493
   endgenerate
494
 
495
   always @ (posedge clk_b)
496
      q_b <= ram[adr_b];
497
*/
498
/*
499
   always @ (posedge clk_a)
500
     begin
501
        q_a <= ram[adr_a];
502
        if (we_a)
503
             ram[adr_a] <= d_a;
504
     end
505
   always @ (posedge clk_b)
506
     begin
507
        q_b <= ram[adr_b];
508
        if (we_b)
509
          ram[adr_b] <= d_b;
510
     end
511
*/
512
endmodule
513
`endif
514
 
515 5 unneback
// Content addresable memory, CAM
516
 
517 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
518 5 unneback
// FIFO
519 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
520
module `BASE`MODULE (
521
`undef MODULE
522 25 unneback
    d, wr, fifo_full,
523
    q, rd, fifo_empty,
524
    fill_level,
525
    clk, rst
526
    );
527
 
528
parameter data_width = 18;
529
parameter addr_width = 4;
530 5 unneback
 
531 25 unneback
// write side
532
input  [data_width-1:0] d;
533
input                   wr;
534
output                  fifo_full;
535
// read side
536
output [data_width-1:0] q;
537
input                   rd;
538
output                  fifo_empty;
539
// common
540
output [addr_width:0]   fill_level;
541
input rst, clk;
542
 
543
wire [addr_width:1] wadr, radr;
544
 
545 40 unneback
`define MODULE cnt_bin_ce
546
`BASE`MODULE
547 25 unneback
    # ( .length(addr_width))
548
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
549 40 unneback
`BASE`MODULE
550 25 unneback
    # (.length(addr_width))
551
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
552 40 unneback
`undef MODULE
553 25 unneback
 
554 40 unneback
`define MODULE dpram_1r1w
555
`BASE`MODULE
556 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
557
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
558 40 unneback
`undef MODULE
559 25 unneback
 
560 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
561
`BASE`MODULE
562 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
563 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
564 40 unneback
`undef MODULE
565 25 unneback
endmodule
566 40 unneback
`endif
567 25 unneback
 
568 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
569 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
570
// RAM is supposed to be larger than the two FIFOs
571
// LFSR counters used adr pointers
572 40 unneback
`define MODULE fifo_2r2w_sync_simplex
573
module `BASE`MODULE (
574
`undef MODULE
575 27 unneback
    // a side
576
    a_d, a_wr, a_fifo_full,
577
    a_q, a_rd, a_fifo_empty,
578
    a_fill_level,
579
    // b side
580
    b_d, b_wr, b_fifo_full,
581
    b_q, b_rd, b_fifo_empty,
582
    b_fill_level,
583
    // common
584
    clk, rst
585
    );
586
parameter data_width = 8;
587
parameter addr_width = 5;
588
parameter fifo_full_level = (1<<addr_width)-1;
589
 
590
// a side
591
input  [data_width-1:0] a_d;
592
input                   a_wr;
593
output                  a_fifo_full;
594
output [data_width-1:0] a_q;
595
input                   a_rd;
596
output                  a_fifo_empty;
597
output [addr_width-1:0] a_fill_level;
598
 
599
// b side
600
input  [data_width-1:0] b_d;
601
input                   b_wr;
602
output                  b_fifo_full;
603
output [data_width-1:0] b_q;
604
input                   b_rd;
605
output                  b_fifo_empty;
606
output [addr_width-1:0] b_fill_level;
607
 
608
input                   clk;
609
input                   rst;
610
 
611
// adr_gen
612
wire [addr_width:1] a_wadr, a_radr;
613
wire [addr_width:1] b_wadr, b_radr;
614
// dpram
615
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
616
 
617 40 unneback
`define MODULE cnt_lfsr_ce
618
`BASE`MODULE
619 27 unneback
    # ( .length(addr_width))
620
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
621
 
622 40 unneback
`BASE`MODULE
623 27 unneback
    # (.length(addr_width))
624
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
625
 
626 40 unneback
`BASE`MODULE
627 27 unneback
    # ( .length(addr_width))
628
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
629
 
630 40 unneback
`BASE`MODULE
631 27 unneback
    # (.length(addr_width))
632
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
633 40 unneback
`undef MODULE
634 27 unneback
 
635
// mux read or write adr to DPRAM
636
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
637
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
638
 
639 40 unneback
`define MODULE dpram_2r2w
640
`BASE`MODULE
641 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
642
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
643
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
644 40 unneback
`undef MODULE
645
 
646
`define MODULE cnt_bin_ce_rew_zq_l1
647
`BASE`MODULE
648 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
649 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
650
 
651 40 unneback
`BASE`MODULE
652 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
653 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
654 40 unneback
`undef MODULE
655 27 unneback
 
656
endmodule
657 40 unneback
`endif
658 27 unneback
 
659 40 unneback
`ifdef FIFO_CMP_ASYNC
660
`define MODULE fifo_cmp_async
661
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
662
`undef MODULE
663 5 unneback
 
664 11 unneback
   parameter addr_width = 4;
665
   parameter N = addr_width-1;
666 5 unneback
 
667
   parameter Q1 = 2'b00;
668
   parameter Q2 = 2'b01;
669
   parameter Q3 = 2'b11;
670
   parameter Q4 = 2'b10;
671
 
672
   parameter going_empty = 1'b0;
673
   parameter going_full  = 1'b1;
674
 
675
   input [N:0]  wptr, rptr;
676 14 unneback
   output       fifo_empty;
677 5 unneback
   output       fifo_full;
678
   input        wclk, rclk, rst;
679
 
680
`ifndef GENERATE_DIRECTION_AS_LATCH
681
   wire direction;
682
`endif
683
`ifdef GENERATE_DIRECTION_AS_LATCH
684
   reg direction;
685
`endif
686
   reg  direction_set, direction_clr;
687
 
688
   wire async_empty, async_full;
689
   wire fifo_full2;
690 14 unneback
   wire fifo_empty2;
691 5 unneback
 
692
   // direction_set
693
   always @ (wptr[N:N-1] or rptr[N:N-1])
694
     case ({wptr[N:N-1],rptr[N:N-1]})
695
       {Q1,Q2} : direction_set <= 1'b1;
696
       {Q2,Q3} : direction_set <= 1'b1;
697
       {Q3,Q4} : direction_set <= 1'b1;
698
       {Q4,Q1} : direction_set <= 1'b1;
699
       default : direction_set <= 1'b0;
700
     endcase
701
 
702
   // direction_clear
703
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
704
     if (rst)
705
       direction_clr <= 1'b1;
706
     else
707
       case ({wptr[N:N-1],rptr[N:N-1]})
708
         {Q2,Q1} : direction_clr <= 1'b1;
709
         {Q3,Q2} : direction_clr <= 1'b1;
710
         {Q4,Q3} : direction_clr <= 1'b1;
711
         {Q1,Q4} : direction_clr <= 1'b1;
712
         default : direction_clr <= 1'b0;
713
       endcase
714
 
715 40 unneback
`define MODULE dff_sr
716 5 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
717 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
718 5 unneback
`endif
719
 
720
`ifdef GENERATE_DIRECTION_AS_LATCH
721
   always @ (posedge direction_set or posedge direction_clr)
722
     if (direction_clr)
723
       direction <= going_empty;
724
     else
725
       direction <= going_full;
726
`endif
727
 
728
   assign async_empty = (wptr == rptr) && (direction==going_empty);
729
   assign async_full  = (wptr == rptr) && (direction==going_full);
730
 
731 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
732
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
733
`undef MODULE
734 5 unneback
 
735
/*
736
   always @ (posedge wclk or posedge rst or posedge async_full)
737
     if (rst)
738
       {fifo_full, fifo_full2} <= 2'b00;
739
     else if (async_full)
740
       {fifo_full, fifo_full2} <= 2'b11;
741
     else
742
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
743
*/
744 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
745 5 unneback
     if (async_empty)
746
       {fifo_empty, fifo_empty2} <= 2'b11;
747
     else
748 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
749 40 unneback
`define MODULE dff
750
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
751
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
752
`undef MODULE
753 25 unneback
endmodule // async_compb
754 40 unneback
`endif
755 5 unneback
 
756 40 unneback
`ifdef FIFO_1R1W_ASYNC
757
`define MODULE fifo_1r1w_async
758
module `BASE`MODULE (
759
`undef MODULE
760 5 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
761
    q, rd, fifo_empty, rd_clk, rd_rst
762
    );
763
 
764
parameter data_width = 18;
765
parameter addr_width = 4;
766
 
767
// write side
768
input  [data_width-1:0] d;
769
input                   wr;
770
output                  fifo_full;
771
input                   wr_clk;
772
input                   wr_rst;
773
// read side
774
output [data_width-1:0] q;
775
input                   rd;
776
output                  fifo_empty;
777
input                   rd_clk;
778
input                   rd_rst;
779
 
780
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
781 23 unneback
 
782 40 unneback
`define MODULE cnt_gray_ce_bin
783
`BASE`MODULE
784 5 unneback
    # ( .length(addr_width))
785
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
786
 
787 40 unneback
`BASE`MODULE
788 5 unneback
    # (.length(addr_width))
789 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
790 40 unneback
`undef MODULE
791 5 unneback
 
792 40 unneback
`define MODULE dpram_1r1w
793
`BASE`MODULE
794 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
795
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
796 40 unneback
`undef MODULE
797 5 unneback
 
798 40 unneback
`define MODULE fifo_cmp_async
799
`BASE`MODULE
800 5 unneback
    # (.addr_width(addr_width))
801
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
802 40 unneback
`undef MODULE
803 5 unneback
 
804
endmodule
805 40 unneback
`endif
806 5 unneback
 
807 40 unneback
`ifdef FIFO_2R2W_ASYNC
808
`define MODULE fifo_2r2w_async
809
module `BASE`MODULE (
810
`undef MODULE
811 5 unneback
    // a side
812
    a_d, a_wr, a_fifo_full,
813
    a_q, a_rd, a_fifo_empty,
814
    a_clk, a_rst,
815
    // b side
816
    b_d, b_wr, b_fifo_full,
817
    b_q, b_rd, b_fifo_empty,
818
    b_clk, b_rst
819
    );
820
 
821
parameter data_width = 18;
822
parameter addr_width = 4;
823
 
824
// a side
825
input  [data_width-1:0] a_d;
826
input                   a_wr;
827
output                  a_fifo_full;
828
output [data_width-1:0] a_q;
829
input                   a_rd;
830
output                  a_fifo_empty;
831
input                   a_clk;
832
input                   a_rst;
833
 
834
// b side
835
input  [data_width-1:0] b_d;
836
input                   b_wr;
837
output                  b_fifo_full;
838
output [data_width-1:0] b_q;
839
input                   b_rd;
840
output                  b_fifo_empty;
841
input                   b_clk;
842
input                   b_rst;
843
 
844 40 unneback
`define MODULE fifo_1r1w_async
845
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
846 5 unneback
vl_fifo_1r1w_async_a (
847
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
848
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
849
    );
850
 
851 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
852 5 unneback
vl_fifo_1r1w_async_b (
853
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
854
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
855
    );
856 40 unneback
`undef MODULE
857
 
858 5 unneback
endmodule
859 40 unneback
`endif
860 5 unneback
 
861 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
862
`define MODULE fifo_2r2w_async_simplex
863
module `BASE`MODULE (
864
`undef MODULE
865 5 unneback
    // a side
866
    a_d, a_wr, a_fifo_full,
867
    a_q, a_rd, a_fifo_empty,
868
    a_clk, a_rst,
869
    // b side
870
    b_d, b_wr, b_fifo_full,
871
    b_q, b_rd, b_fifo_empty,
872
    b_clk, b_rst
873
    );
874
 
875
parameter data_width = 18;
876
parameter addr_width = 4;
877
 
878
// a side
879
input  [data_width-1:0] a_d;
880
input                   a_wr;
881
output                  a_fifo_full;
882
output [data_width-1:0] a_q;
883
input                   a_rd;
884
output                  a_fifo_empty;
885
input                   a_clk;
886
input                   a_rst;
887
 
888
// b side
889
input  [data_width-1:0] b_d;
890
input                   b_wr;
891
output                  b_fifo_full;
892
output [data_width-1:0] b_q;
893
input                   b_rd;
894
output                  b_fifo_empty;
895
input                   b_clk;
896
input                   b_rst;
897
 
898
// adr_gen
899
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
900
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
901
// dpram
902
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
903
 
904 40 unneback
`define MODULE cnt_gray_ce_bin
905
`BASE`MODULE
906 5 unneback
    # ( .length(addr_width))
907
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
908
 
909 40 unneback
`BASE`MODULE
910 5 unneback
    # (.length(addr_width))
911
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
912
 
913 40 unneback
`BASE`MODULE
914 5 unneback
    # ( .length(addr_width))
915
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
916
 
917 40 unneback
`BASE`MODULE
918 5 unneback
    # (.length(addr_width))
919
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
920 40 unneback
`undef MODULE
921 5 unneback
 
922
// mux read or write adr to DPRAM
923
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
924
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
925
 
926 40 unneback
`define MODULE dpram_2r2w
927
`BASE`MODULE
928 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
929
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
930
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
931 40 unneback
`undef MODULE
932 5 unneback
 
933 40 unneback
`define MODULE fifo_cmp_async
934
`BASE`MODULE
935 5 unneback
    # (.addr_width(addr_width))
936
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
937
 
938 40 unneback
`BASE`MODULE
939 5 unneback
    # (.addr_width(addr_width))
940
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
941 40 unneback
`undef MODULE
942 5 unneback
 
943
endmodule
944 40 unneback
`endif
945 48 unneback
 
946
`ifdef REG_FILE
947
`define MODULE reg_file
948
module `BASE`MODULE (
949
`undef MODULE
950
    a1, a2, a3, wd3, we3, rd1, rd2, clk
951
);
952
parameter data_width = 32;
953
parameter addr_width = 5;
954
input [addr_width-1:0] a1, a2, a3;
955
input [data_width-1:0] wd3;
956
input we3;
957
output [data_width-1:0] rd1, rd2;
958
input clk;
959
 
960
`ifdef ACTEL
961
reg [data_width-1:0] wd3_reg;
962
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
963
reg we3_reg;
964
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
965
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
966
always @ (posedge clk or posedge rst)
967
if (rst)
968
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
969
else
970
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
971
 
972
    always @ (negedge clk)
973
    if (we3_reg)
974
        ram1[a3_reg] <= wd3;
975
    always @ (posedge clk)
976
        a1_reg <= a1;
977
    assign rd1 = ram1[a1_reg];
978
 
979
    always @ (negedge clk)
980
    if (we3_reg)
981
        ram2[a3_reg] <= wd3;
982
    always @ (posedge clk)
983
        a2_reg <= a2;
984
    assign rd2 = ram2[a2_reg];
985
 
986
`else
987
 
988
`define MODULE dpram_1r1w
989
`BASE`MODULE
990
    # ( .data_width(data_width), .addr_width(addr_width))
991
    ram1 (
992
        .d_a(wd3),
993
        .adr_a(a3),
994
        .we_a(we3),
995
        .clk_a(clk),
996
        .q_b(rd1),
997
        .adr_b(a1),
998
        .clk_b(clk) );
999
 
1000
`BASE`MODULE
1001
    # ( .data_width(data_width), .addr_width(addr_width))
1002
    ram2 (
1003
        .d_a(wd3),
1004
        .adr_a(a3),
1005
        .we_a(we3),
1006
        .clk_a(clk),
1007
        .q_b(rd2),
1008
        .adr_b(a2),
1009
        .clk_b(clk) );
1010
`undef MODULE
1011
 
1012
`endif
1013
 
1014
endmodule
1015
`endif

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