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1 5 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, memories                                 ////
4
////                                                              ////
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////  Description                                                 ////
6
////  memories                                                    ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more memory types                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef ROM_INIT
44 5 unneback
/// ROM
45 40 unneback
`define MODULE rom_init
46
module `BASE`MODULE ( adr, q, clk);
47
`undef MODULE
48 5 unneback
 
49 7 unneback
   parameter data_width = 32;
50
   parameter addr_width = 8;
51 75 unneback
   parameter mem_size = 1<<addr_width;
52 7 unneback
   input [(addr_width-1):0]       adr;
53
   output reg [(data_width-1):0] q;
54
   input                         clk;
55 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
56 7 unneback
   parameter memory_file = "vl_rom.vmem";
57
   initial
58
     begin
59
        $readmemh(memory_file, rom);
60
     end
61
 
62
   always @ (posedge clk)
63
     q <= rom[adr];
64 5 unneback
 
65 7 unneback
endmodule
66 40 unneback
`endif
67 7 unneback
 
68 40 unneback
`ifdef RAM
69
`define MODULE ram
70 5 unneback
// Single port RAM
71 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
72
`undef MODULE
73 5 unneback
 
74
   parameter data_width = 32;
75
   parameter addr_width = 8;
76 75 unneback
   parameter mem_size = 1<<addr_width;
77 5 unneback
   input [(data_width-1):0]      d;
78
   input [(addr_width-1):0]       adr;
79
   input                         we;
80 7 unneback
   output reg [(data_width-1):0] q;
81 5 unneback
   input                         clk;
82 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0];
83 7 unneback
   parameter init = 0;
84
   parameter memory_file = "vl_ram.vmem";
85
   generate if (init) begin : init_mem
86
   initial
87
     begin
88
        $readmemh(memory_file, ram);
89
     end
90
   end
91
   endgenerate
92
 
93 5 unneback
   always @ (posedge clk)
94
   begin
95
   if (we)
96
     ram[adr] <= d;
97
   q <= ram[adr];
98
   end
99
 
100
endmodule
101 40 unneback
`endif
102 5 unneback
 
103 40 unneback
`ifdef RAM_BE
104
`define MODULE ram_be
105 90 unneback
module `BASE`MODULE ( d, adr, be, re, we, q, clk);
106 40 unneback
`undef MODULE
107
 
108 7 unneback
   parameter data_width = 32;
109 72 unneback
   parameter addr_width = 6;
110 75 unneback
   parameter mem_size = 1<<addr_width;
111 7 unneback
   input [(data_width-1):0]      d;
112
   input [(addr_width-1):0]       adr;
113 73 unneback
   input [(data_width/8)-1:0]    be;
114 90 unneback
   input                         re;
115 7 unneback
   input                         we;
116
   output reg [(data_width-1):0] q;
117
   input                         clk;
118
 
119 84 unneback
 
120 65 unneback
//E2_ifdef SYSTEMVERILOG
121 68 unneback
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
122 65 unneback
//E2_else
123 84 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
124
    wire [data_width/8-1:0] cke;
125 65 unneback
//E2_endif
126
 
127 60 unneback
   parameter memory_init = 0;
128 7 unneback
   parameter memory_file = "vl_ram.vmem";
129 60 unneback
   generate if (memory_init) begin : init_mem
130 7 unneback
   initial
131
     begin
132
        $readmemh(memory_file, ram);
133
     end
134
   end
135
   endgenerate
136
 
137 60 unneback
//E2_ifdef SYSTEMVERILOG
138
// use a multi-dimensional packed array
139
//to model individual bytes within the word
140
 
141
always_ff@(posedge clk)
142
begin
143
    if(we) begin // note: we should have a for statement to support any bus width
144 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
145
        if(be[2]) ram[adr][2] <= d[23:16];
146
        if(be[1]) ram[adr][1] <= d[15:8];
147
        if(be[0]) ram[adr][0] <= d[7:0];
148 60 unneback
    end
149 90 unneback
    if (re)
150
        q <= ram[adr];
151 60 unneback
end
152
 
153
//E2_else
154
 
155 84 unneback
assign cke = {data_width/8{we}} & be;
156 7 unneback
   genvar i;
157 84 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
158 7 unneback
      always @ (posedge clk)
159 84 unneback
      if (cke[i])
160 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
161
   end
162
   endgenerate
163
 
164
   always @ (posedge clk)
165 90 unneback
    if (re)
166 7 unneback
      q <= ram[adr];
167
 
168 60 unneback
//E2_endif
169
 
170 84 unneback
   // Function to access RAM (for use by Verilator).
171
   function [31:0] get_mem;
172
      // verilator public
173 90 unneback
      input [addr_width-1:0]             addr;
174 84 unneback
      get_mem = ram[addr];
175
   endfunction // get_mem
176
 
177
   // Function to write RAM (for use by Verilator).
178
   function set_mem;
179
      // verilator public
180 90 unneback
      input [addr_width-1:0]             addr;
181
      input [data_width-1:0]             data;
182 84 unneback
      ram[addr] = data;
183
   endfunction // set_mem
184
 
185 7 unneback
endmodule
186 40 unneback
`endif
187 7 unneback
 
188 5 unneback
`ifdef ACTEL
189 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
190 5 unneback
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
191
`else
192
        `define SYN
193
`endif
194
 
195 40 unneback
`ifdef DPRAM_1R1W
196
`define MODULE dpram_1r1w
197
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
198
`undef MODULE
199 5 unneback
   parameter data_width = 32;
200
   parameter addr_width = 8;
201 75 unneback
   parameter mem_size = 1<<addr_width;
202 5 unneback
   input [(data_width-1):0]      d_a;
203
   input [(addr_width-1):0]       adr_a;
204
   input [(addr_width-1):0]       adr_b;
205
   input                         we_a;
206
   output [(data_width-1):0]      q_b;
207
   input                         clk_a, clk_b;
208
   reg [(addr_width-1):0]         adr_b_reg;
209 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
210 7 unneback
 
211
   parameter init = 0;
212
   parameter memory_file = "vl_ram.vmem";
213
   generate if (init) begin : init_mem
214
   initial
215
     begin
216
        $readmemh(memory_file, ram);
217
     end
218
   end
219
   endgenerate
220
 
221 5 unneback
   always @ (posedge clk_a)
222
   if (we_a)
223
     ram[adr_a] <= d_a;
224
   always @ (posedge clk_b)
225
   adr_b_reg <= adr_b;
226
   assign q_b = ram[adr_b_reg];
227 40 unneback
 
228 5 unneback
endmodule
229 40 unneback
`endif
230 5 unneback
 
231 40 unneback
`ifdef DPRAM_2R1W
232
`define MODULE dpram_2r1w
233
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
234
`undef MODULE
235
 
236 5 unneback
   parameter data_width = 32;
237
   parameter addr_width = 8;
238 75 unneback
   parameter mem_size = 1<<addr_width;
239 5 unneback
   input [(data_width-1):0]      d_a;
240
   input [(addr_width-1):0]       adr_a;
241
   input [(addr_width-1):0]       adr_b;
242
   input                         we_a;
243
   output [(data_width-1):0]      q_b;
244
   output reg [(data_width-1):0] q_a;
245
   input                         clk_a, clk_b;
246
   reg [(data_width-1):0]         q_b;
247 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
248 7 unneback
 
249
   parameter init = 0;
250
   parameter memory_file = "vl_ram.vmem";
251
   generate if (init) begin : init_mem
252
   initial
253
     begin
254
        $readmemh(memory_file, ram);
255
     end
256
   end
257
   endgenerate
258
 
259 5 unneback
   always @ (posedge clk_a)
260
     begin
261
        q_a <= ram[adr_a];
262
        if (we_a)
263
             ram[adr_a] <= d_a;
264
     end
265
   always @ (posedge clk_b)
266
          q_b <= ram[adr_b];
267
endmodule
268 40 unneback
`endif
269 5 unneback
 
270 40 unneback
`ifdef DPRAM_2R2W
271
`define MODULE dpram_2r2w
272
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
273
`undef MODULE
274
 
275 5 unneback
   parameter data_width = 32;
276
   parameter addr_width = 8;
277 75 unneback
   parameter mem_size = 1<<addr_width;
278 5 unneback
   input [(data_width-1):0]      d_a;
279
   input [(addr_width-1):0]       adr_a;
280
   input [(addr_width-1):0]       adr_b;
281
   input                         we_a;
282
   output [(data_width-1):0]      q_b;
283
   input [(data_width-1):0]       d_b;
284
   output reg [(data_width-1):0] q_a;
285
   input                         we_b;
286
   input                         clk_a, clk_b;
287
   reg [(data_width-1):0]         q_b;
288 75 unneback
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
289 7 unneback
 
290
   parameter init = 0;
291
   parameter memory_file = "vl_ram.vmem";
292
   generate if (init) begin : init_mem
293
   initial
294
     begin
295
        $readmemh(memory_file, ram);
296
     end
297
   end
298
   endgenerate
299
 
300 5 unneback
   always @ (posedge clk_a)
301
     begin
302
        q_a <= ram[adr_a];
303
        if (we_a)
304
             ram[adr_a] <= d_a;
305
     end
306
   always @ (posedge clk_b)
307
     begin
308
        q_b <= ram[adr_b];
309
        if (we_b)
310
          ram[adr_b] <= d_b;
311
     end
312
endmodule
313 40 unneback
`endif
314 5 unneback
 
315 83 unneback
`ifdef DPRAM_MIXED_WIDTH_2R2W
316
`define MODULE dpram_mixed_width_2r2w
317
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
318
`undef MODULE
319
   parameter data_width = 32;
320
   parameter addr_width = 8;
321
   parameter data_width_ratio = 2;
322
   parameter b_data_width = data_width * data_width_ratio;
323
   parameter b_addr_width = addr_width ;
324
endmodule
325
`endif
326
 
327 75 unneback
`ifdef DPRAM_BE_2R2W
328
`define MODULE dpram_be_2r2w
329
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
330
`undef MODULE
331
 
332
   parameter a_data_width = 32;
333
   parameter a_addr_width = 8;
334
   parameter b_data_width = 64;
335
   parameter b_addr_width = 7;
336
   //parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
337
   parameter mem_size = 1024;
338
   input [(a_data_width-1):0]      d_a;
339
   input [(a_addr_width-1):0]     adr_a;
340
   input [(b_addr_width-1):0]     adr_b;
341
   input [(a_data_width/4-1):0]    be_a;
342
   input                         we_a;
343
   output [(b_data_width-1):0]    q_b;
344
   input [(b_data_width-1):0]     d_b;
345
   output reg [(a_data_width-1):0] q_a;
346
   input [(b_data_width/4-1):0]    be_b;
347
   input                         we_b;
348
   input                         clk_a, clk_b;
349
   reg [(b_data_width-1):0]       q_b;
350
 
351
generate
352
if (a_data_width==32 & b_data_width==64) begin : inst32to64
353
 
354 77 unneback
    wire [63:0] tmp;
355 75 unneback
    `define MODULE dpram_2r2w
356
    `BASE`MODULE
357
    # (.data_width(8), .addr_width(b_addr_width-3))
358
    ram0 (
359
        .d_a(d_a[7:0]),
360
        .q_a(tmp[7:0]),
361
        .adr_a(adr_a[a_addr_width-3-1:0]),
362
        .we_a(we_a & be_a[0] & !adr_a[0]),
363
        .clk_a(clk_a),
364
        .d_b(d_b[7:0]),
365
        .q_b(q_b[7:0]),
366
        .adr_b(adr_b[b_addr_width-3-1:0]),
367
        .we_b(we_b),
368
        .clk_b(clk_b) );
369
    `BASE`MODULE
370
    # (.data_width(8), .addr_width(b_addr_width-3))
371
    ram1 (
372
        .d_a(d_a[7:0]),
373
        .q_a(tmp[7:0]),
374
        .adr_a(adr_a[a_addr_width-3-1:0]),
375
        .we_a(we_a),
376
        .clk_a(clk_a),
377
        .d_b(d_b[7:0]),
378
        .q_b(q_b[7:0]),
379
        .adr_b(adr_b[b_addr_width-3-1:0]),
380
        .we_b(we_b),
381
        .clk_b(clk_b) );
382
    `BASE`MODULE
383
    # (.data_width(8), .addr_width(b_addr_width-3))
384
    ram2 (
385
        .d_a(d_a[15:8]),
386
        .q_a(tmp[7:0]),
387
        .adr_a(adr_a[a_addr_width-3-1:0]),
388
        .we_a(we_a),
389
        .clk_a(clk_a),
390
        .d_b(d_b[7:0]),
391
        .q_b(q_b[7:0]),
392
        .adr_b(adr_b[b_addr_width-3-1:0]),
393
        .we_b(we_b),
394
        .clk_b(clk_b) );
395
    `BASE`MODULE
396
    # (.data_width(8), .addr_width(b_addr_width-3))
397
    ram3 (
398
        .d_a(d_a[15:8]),
399
        .q_a(tmp[7:0]),
400
        .adr_a(adr_a[a_addr_width-3-1:0]),
401
        .we_a(we_a),
402
        .clk_a(clk_a),
403
        .d_b(d_b[7:0]),
404
        .q_b(q_b[7:0]),
405
        .adr_b(adr_b[b_addr_width-3-1:0]),
406
        .we_b(we_b),
407
        .clk_b(clk_b) );
408
    `BASE`MODULE
409
    # (.data_width(8), .addr_width(b_addr_width-3))
410
    ram4 (
411
        .d_a(d_a[23:16]),
412
        .q_a(tmp[7:0]),
413
        .adr_a(adr_a[a_addr_width-3-1:0]),
414
        .we_a(we_a),
415
        .clk_a(clk_a),
416
        .d_b(d_b[7:0]),
417
        .q_b(q_b[7:0]),
418
        .adr_b(adr_b[b_addr_width-3-1:0]),
419
        .we_b(we_b),
420
        .clk_b(clk_b) );
421
    `BASE`MODULE
422
    # (.data_width(8), .addr_width(b_addr_width-3))
423
    ram5 (
424
        .d_a(d_a[23:16]),
425
        .q_a(tmp[7:0]),
426
        .adr_a(adr_a[a_addr_width-3-1:0]),
427
        .we_a(we_a),
428
        .clk_a(clk_a),
429
        .d_b(d_b[7:0]),
430
        .q_b(q_b[7:0]),
431
        .adr_b(adr_b[b_addr_width-3-1:0]),
432
        .we_b(we_b),
433
        .clk_b(clk_b) );
434
    `BASE`MODULE
435
    # (.data_width(8), .addr_width(b_addr_width-3))
436
    ram6 (
437
        .d_a(d_a[31:24]),
438
        .q_a(tmp[7:0]),
439
        .adr_a(adr_a[a_addr_width-3-1:0]),
440
        .we_a(we_a),
441
        .clk_a(clk_a),
442
        .d_b(d_b[7:0]),
443
        .q_b(q_b[7:0]),
444
        .adr_b(adr_b[b_addr_width-3-1:0]),
445
        .we_b(we_b),
446
        .clk_b(clk_b) );
447
    `BASE`MODULE
448
    # (.data_width(8), .addr_width(b_addr_width-3))
449
    ram7 (
450
        .d_a(d_a[31:24]),
451
        .q_a(tmp[7:0]),
452
        .adr_a(adr_a[a_addr_width-3-1:0]),
453
        .we_a(we_a),
454
        .clk_a(clk_a),
455
        .d_b(d_b[7:0]),
456
        .q_b(q_b[7:0]),
457
        .adr_b(adr_b[b_addr_width-3-1:0]),
458
        .we_b(we_b),
459
        .clk_b(clk_b) );
460
`undef MODULE
461
/*
462
   reg [7:0] ram0 [mem_size/8-1:0];
463
   wire [7:0] wea, web;
464
   assign wea = we_a & be_a[0];
465
   assign web = we_b & be_b[0];
466
   always @ (posedge clk_a)
467
    if (wea)
468
        ram0[adr_a] <= d_a[7:0];
469
    always @ (posedge clk_a)
470
        q_a[7:0] <= ram0[adr_a];
471
   always @ (posedge clk_a)
472
    if (web)
473
        ram0[adr_b] <= d_b[7:0];
474
    always @ (posedge clk_b)
475
        q_b[7:0] <= ram0[adr_b];
476
*/
477
end
478
endgenerate
479
/*
480
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_rama
481
      always @ (posedge clk_a)
482
      if (we_a & be_a[i])
483
        ram[adr_a][(i+1)*8-1:i*8] <= d_a[(i+1)*8-1:i*8];
484
   end
485
   endgenerate
486
 
487
   always @ (posedge clk_a)
488
      q_a <= ram[adr_a];
489
 
490
   genvar i;
491
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ramb
492
      always @ (posedge clk_a)
493
      if (we_b & be_b[i])
494
        ram[adr_b][(i+1)*8-1:i*8] <= d_b[(i+1)*8-1:i*8];
495
   end
496
   endgenerate
497
 
498
   always @ (posedge clk_b)
499
      q_b <= ram[adr_b];
500
*/
501
/*
502
   always @ (posedge clk_a)
503
     begin
504
        q_a <= ram[adr_a];
505
        if (we_a)
506
             ram[adr_a] <= d_a;
507
     end
508
   always @ (posedge clk_b)
509
     begin
510
        q_b <= ram[adr_b];
511
        if (we_b)
512
          ram[adr_b] <= d_b;
513
     end
514
*/
515
endmodule
516
`endif
517
 
518 5 unneback
// Content addresable memory, CAM
519
 
520 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
521 5 unneback
// FIFO
522 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
523
module `BASE`MODULE (
524
`undef MODULE
525 25 unneback
    d, wr, fifo_full,
526
    q, rd, fifo_empty,
527
    fill_level,
528
    clk, rst
529
    );
530
 
531
parameter data_width = 18;
532
parameter addr_width = 4;
533 5 unneback
 
534 25 unneback
// write side
535
input  [data_width-1:0] d;
536
input                   wr;
537
output                  fifo_full;
538
// read side
539
output [data_width-1:0] q;
540
input                   rd;
541
output                  fifo_empty;
542
// common
543
output [addr_width:0]   fill_level;
544
input rst, clk;
545
 
546
wire [addr_width:1] wadr, radr;
547
 
548 40 unneback
`define MODULE cnt_bin_ce
549
`BASE`MODULE
550 25 unneback
    # ( .length(addr_width))
551
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
552 40 unneback
`BASE`MODULE
553 25 unneback
    # (.length(addr_width))
554
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
555 40 unneback
`undef MODULE
556 25 unneback
 
557 40 unneback
`define MODULE dpram_1r1w
558
`BASE`MODULE
559 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
560
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
561 40 unneback
`undef MODULE
562 25 unneback
 
563 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
564
`BASE`MODULE
565 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
566 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
567 40 unneback
`undef MODULE
568 25 unneback
endmodule
569 40 unneback
`endif
570 25 unneback
 
571 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
572 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
573
// RAM is supposed to be larger than the two FIFOs
574
// LFSR counters used adr pointers
575 40 unneback
`define MODULE fifo_2r2w_sync_simplex
576
module `BASE`MODULE (
577
`undef MODULE
578 27 unneback
    // a side
579
    a_d, a_wr, a_fifo_full,
580
    a_q, a_rd, a_fifo_empty,
581
    a_fill_level,
582
    // b side
583
    b_d, b_wr, b_fifo_full,
584
    b_q, b_rd, b_fifo_empty,
585
    b_fill_level,
586
    // common
587
    clk, rst
588
    );
589
parameter data_width = 8;
590
parameter addr_width = 5;
591
parameter fifo_full_level = (1<<addr_width)-1;
592
 
593
// a side
594
input  [data_width-1:0] a_d;
595
input                   a_wr;
596
output                  a_fifo_full;
597
output [data_width-1:0] a_q;
598
input                   a_rd;
599
output                  a_fifo_empty;
600
output [addr_width-1:0] a_fill_level;
601
 
602
// b side
603
input  [data_width-1:0] b_d;
604
input                   b_wr;
605
output                  b_fifo_full;
606
output [data_width-1:0] b_q;
607
input                   b_rd;
608
output                  b_fifo_empty;
609
output [addr_width-1:0] b_fill_level;
610
 
611
input                   clk;
612
input                   rst;
613
 
614
// adr_gen
615
wire [addr_width:1] a_wadr, a_radr;
616
wire [addr_width:1] b_wadr, b_radr;
617
// dpram
618
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
619
 
620 40 unneback
`define MODULE cnt_lfsr_ce
621
`BASE`MODULE
622 27 unneback
    # ( .length(addr_width))
623
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
624
 
625 40 unneback
`BASE`MODULE
626 27 unneback
    # (.length(addr_width))
627
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
628
 
629 40 unneback
`BASE`MODULE
630 27 unneback
    # ( .length(addr_width))
631
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
632
 
633 40 unneback
`BASE`MODULE
634 27 unneback
    # (.length(addr_width))
635
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
636 40 unneback
`undef MODULE
637 27 unneback
 
638
// mux read or write adr to DPRAM
639
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
640
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
641
 
642 40 unneback
`define MODULE dpram_2r2w
643
`BASE`MODULE
644 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
645
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
646
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
647 40 unneback
`undef MODULE
648
 
649
`define MODULE cnt_bin_ce_rew_zq_l1
650
`BASE`MODULE
651 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
652 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
653
 
654 40 unneback
`BASE`MODULE
655 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
656 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
657 40 unneback
`undef MODULE
658 27 unneback
 
659
endmodule
660 40 unneback
`endif
661 27 unneback
 
662 40 unneback
`ifdef FIFO_CMP_ASYNC
663
`define MODULE fifo_cmp_async
664
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
665
`undef MODULE
666 5 unneback
 
667 11 unneback
   parameter addr_width = 4;
668
   parameter N = addr_width-1;
669 5 unneback
 
670
   parameter Q1 = 2'b00;
671
   parameter Q2 = 2'b01;
672
   parameter Q3 = 2'b11;
673
   parameter Q4 = 2'b10;
674
 
675
   parameter going_empty = 1'b0;
676
   parameter going_full  = 1'b1;
677
 
678
   input [N:0]  wptr, rptr;
679 14 unneback
   output       fifo_empty;
680 5 unneback
   output       fifo_full;
681
   input        wclk, rclk, rst;
682
 
683
`ifndef GENERATE_DIRECTION_AS_LATCH
684
   wire direction;
685
`endif
686
`ifdef GENERATE_DIRECTION_AS_LATCH
687
   reg direction;
688
`endif
689
   reg  direction_set, direction_clr;
690
 
691
   wire async_empty, async_full;
692
   wire fifo_full2;
693 14 unneback
   wire fifo_empty2;
694 5 unneback
 
695
   // direction_set
696
   always @ (wptr[N:N-1] or rptr[N:N-1])
697
     case ({wptr[N:N-1],rptr[N:N-1]})
698
       {Q1,Q2} : direction_set <= 1'b1;
699
       {Q2,Q3} : direction_set <= 1'b1;
700
       {Q3,Q4} : direction_set <= 1'b1;
701
       {Q4,Q1} : direction_set <= 1'b1;
702
       default : direction_set <= 1'b0;
703
     endcase
704
 
705
   // direction_clear
706
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
707
     if (rst)
708
       direction_clr <= 1'b1;
709
     else
710
       case ({wptr[N:N-1],rptr[N:N-1]})
711
         {Q2,Q1} : direction_clr <= 1'b1;
712
         {Q3,Q2} : direction_clr <= 1'b1;
713
         {Q4,Q3} : direction_clr <= 1'b1;
714
         {Q1,Q4} : direction_clr <= 1'b1;
715
         default : direction_clr <= 1'b0;
716
       endcase
717
 
718 40 unneback
`define MODULE dff_sr
719 5 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
720 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
721 5 unneback
`endif
722
 
723
`ifdef GENERATE_DIRECTION_AS_LATCH
724
   always @ (posedge direction_set or posedge direction_clr)
725
     if (direction_clr)
726
       direction <= going_empty;
727
     else
728
       direction <= going_full;
729
`endif
730
 
731
   assign async_empty = (wptr == rptr) && (direction==going_empty);
732
   assign async_full  = (wptr == rptr) && (direction==going_full);
733
 
734 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
735
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
736
`undef MODULE
737 5 unneback
 
738
/*
739
   always @ (posedge wclk or posedge rst or posedge async_full)
740
     if (rst)
741
       {fifo_full, fifo_full2} <= 2'b00;
742
     else if (async_full)
743
       {fifo_full, fifo_full2} <= 2'b11;
744
     else
745
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
746
*/
747 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
748 5 unneback
     if (async_empty)
749
       {fifo_empty, fifo_empty2} <= 2'b11;
750
     else
751 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
752 40 unneback
`define MODULE dff
753
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
754
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
755
`undef MODULE
756 25 unneback
endmodule // async_compb
757 40 unneback
`endif
758 5 unneback
 
759 40 unneback
`ifdef FIFO_1R1W_ASYNC
760
`define MODULE fifo_1r1w_async
761
module `BASE`MODULE (
762
`undef MODULE
763 5 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
764
    q, rd, fifo_empty, rd_clk, rd_rst
765
    );
766
 
767
parameter data_width = 18;
768
parameter addr_width = 4;
769
 
770
// write side
771
input  [data_width-1:0] d;
772
input                   wr;
773
output                  fifo_full;
774
input                   wr_clk;
775
input                   wr_rst;
776
// read side
777
output [data_width-1:0] q;
778
input                   rd;
779
output                  fifo_empty;
780
input                   rd_clk;
781
input                   rd_rst;
782
 
783
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
784 23 unneback
 
785 40 unneback
`define MODULE cnt_gray_ce_bin
786
`BASE`MODULE
787 5 unneback
    # ( .length(addr_width))
788
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
789
 
790 40 unneback
`BASE`MODULE
791 5 unneback
    # (.length(addr_width))
792 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
793 40 unneback
`undef MODULE
794 5 unneback
 
795 40 unneback
`define MODULE dpram_1r1w
796
`BASE`MODULE
797 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
798
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
799 40 unneback
`undef MODULE
800 5 unneback
 
801 40 unneback
`define MODULE fifo_cmp_async
802
`BASE`MODULE
803 5 unneback
    # (.addr_width(addr_width))
804
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
805 40 unneback
`undef MODULE
806 5 unneback
 
807
endmodule
808 40 unneback
`endif
809 5 unneback
 
810 40 unneback
`ifdef FIFO_2R2W_ASYNC
811
`define MODULE fifo_2r2w_async
812
module `BASE`MODULE (
813
`undef MODULE
814 5 unneback
    // a side
815
    a_d, a_wr, a_fifo_full,
816
    a_q, a_rd, a_fifo_empty,
817
    a_clk, a_rst,
818
    // b side
819
    b_d, b_wr, b_fifo_full,
820
    b_q, b_rd, b_fifo_empty,
821
    b_clk, b_rst
822
    );
823
 
824
parameter data_width = 18;
825
parameter addr_width = 4;
826
 
827
// a side
828
input  [data_width-1:0] a_d;
829
input                   a_wr;
830
output                  a_fifo_full;
831
output [data_width-1:0] a_q;
832
input                   a_rd;
833
output                  a_fifo_empty;
834
input                   a_clk;
835
input                   a_rst;
836
 
837
// b side
838
input  [data_width-1:0] b_d;
839
input                   b_wr;
840
output                  b_fifo_full;
841
output [data_width-1:0] b_q;
842
input                   b_rd;
843
output                  b_fifo_empty;
844
input                   b_clk;
845
input                   b_rst;
846
 
847 40 unneback
`define MODULE fifo_1r1w_async
848
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
849 5 unneback
vl_fifo_1r1w_async_a (
850
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
851
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
852
    );
853
 
854 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
855 5 unneback
vl_fifo_1r1w_async_b (
856
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
857
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
858
    );
859 40 unneback
`undef MODULE
860
 
861 5 unneback
endmodule
862 40 unneback
`endif
863 5 unneback
 
864 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
865
`define MODULE fifo_2r2w_async_simplex
866
module `BASE`MODULE (
867
`undef MODULE
868 5 unneback
    // a side
869
    a_d, a_wr, a_fifo_full,
870
    a_q, a_rd, a_fifo_empty,
871
    a_clk, a_rst,
872
    // b side
873
    b_d, b_wr, b_fifo_full,
874
    b_q, b_rd, b_fifo_empty,
875
    b_clk, b_rst
876
    );
877
 
878
parameter data_width = 18;
879
parameter addr_width = 4;
880
 
881
// a side
882
input  [data_width-1:0] a_d;
883
input                   a_wr;
884
output                  a_fifo_full;
885
output [data_width-1:0] a_q;
886
input                   a_rd;
887
output                  a_fifo_empty;
888
input                   a_clk;
889
input                   a_rst;
890
 
891
// b side
892
input  [data_width-1:0] b_d;
893
input                   b_wr;
894
output                  b_fifo_full;
895
output [data_width-1:0] b_q;
896
input                   b_rd;
897
output                  b_fifo_empty;
898
input                   b_clk;
899
input                   b_rst;
900
 
901
// adr_gen
902
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
903
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
904
// dpram
905
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
906
 
907 40 unneback
`define MODULE cnt_gray_ce_bin
908
`BASE`MODULE
909 5 unneback
    # ( .length(addr_width))
910
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
911
 
912 40 unneback
`BASE`MODULE
913 5 unneback
    # (.length(addr_width))
914
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
915
 
916 40 unneback
`BASE`MODULE
917 5 unneback
    # ( .length(addr_width))
918
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
919
 
920 40 unneback
`BASE`MODULE
921 5 unneback
    # (.length(addr_width))
922
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
923 40 unneback
`undef MODULE
924 5 unneback
 
925
// mux read or write adr to DPRAM
926
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
927
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
928
 
929 40 unneback
`define MODULE dpram_2r2w
930
`BASE`MODULE
931 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
932
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
933
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
934 40 unneback
`undef MODULE
935 5 unneback
 
936 40 unneback
`define MODULE fifo_cmp_async
937
`BASE`MODULE
938 5 unneback
    # (.addr_width(addr_width))
939
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
940
 
941 40 unneback
`BASE`MODULE
942 5 unneback
    # (.addr_width(addr_width))
943
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
944 40 unneback
`undef MODULE
945 5 unneback
 
946
endmodule
947 40 unneback
`endif
948 48 unneback
 
949
`ifdef REG_FILE
950
`define MODULE reg_file
951
module `BASE`MODULE (
952
`undef MODULE
953
    a1, a2, a3, wd3, we3, rd1, rd2, clk
954
);
955
parameter data_width = 32;
956
parameter addr_width = 5;
957
input [addr_width-1:0] a1, a2, a3;
958
input [data_width-1:0] wd3;
959
input we3;
960
output [data_width-1:0] rd1, rd2;
961
input clk;
962
 
963
`ifdef ACTEL
964
reg [data_width-1:0] wd3_reg;
965
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
966
reg we3_reg;
967
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
968
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
969
always @ (posedge clk or posedge rst)
970
if (rst)
971
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
972
else
973
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
974
 
975
    always @ (negedge clk)
976
    if (we3_reg)
977
        ram1[a3_reg] <= wd3;
978
    always @ (posedge clk)
979
        a1_reg <= a1;
980
    assign rd1 = ram1[a1_reg];
981
 
982
    always @ (negedge clk)
983
    if (we3_reg)
984
        ram2[a3_reg] <= wd3;
985
    always @ (posedge clk)
986
        a2_reg <= a2;
987
    assign rd2 = ram2[a2_reg];
988
 
989
`else
990
 
991
`define MODULE dpram_1r1w
992
`BASE`MODULE
993
    # ( .data_width(data_width), .addr_width(addr_width))
994
    ram1 (
995
        .d_a(wd3),
996
        .adr_a(a3),
997
        .we_a(we3),
998
        .clk_a(clk),
999
        .q_b(rd1),
1000
        .adr_b(a1),
1001
        .clk_b(clk) );
1002
 
1003
`BASE`MODULE
1004
    # ( .data_width(data_width), .addr_width(addr_width))
1005
    ram2 (
1006
        .d_a(wd3),
1007
        .adr_a(a3),
1008
        .we_a(we3),
1009
        .clk_a(clk),
1010
        .q_b(rd2),
1011
        .adr_b(a2),
1012
        .clk_b(clk) );
1013
`undef MODULE
1014
 
1015
`endif
1016
 
1017
endmodule
1018
`endif

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