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1 5 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, memories                                 ////
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////                                                              ////
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////  Description                                                 ////
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////  memories                                                    ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more memory types                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef ROM_INIT
44 5 unneback
/// ROM
45 40 unneback
`define MODULE rom_init
46
module `BASE`MODULE ( adr, q, clk);
47
`undef MODULE
48 5 unneback
 
49 7 unneback
   parameter data_width = 32;
50
   parameter addr_width = 8;
51 75 unneback
   parameter mem_size = 1<<addr_width;
52 7 unneback
   input [(addr_width-1):0]       adr;
53
   output reg [(data_width-1):0] q;
54
   input                         clk;
55 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
56 7 unneback
   parameter memory_file = "vl_rom.vmem";
57
   initial
58
     begin
59
        $readmemh(memory_file, rom);
60
     end
61
 
62
   always @ (posedge clk)
63
     q <= rom[adr];
64 5 unneback
 
65 7 unneback
endmodule
66 40 unneback
`endif
67 7 unneback
 
68 40 unneback
`ifdef RAM
69
`define MODULE ram
70 5 unneback
// Single port RAM
71 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
72
`undef MODULE
73 5 unneback
 
74
   parameter data_width = 32;
75
   parameter addr_width = 8;
76 75 unneback
   parameter mem_size = 1<<addr_width;
77 5 unneback
   input [(data_width-1):0]      d;
78
   input [(addr_width-1):0]       adr;
79
   input                         we;
80 7 unneback
   output reg [(data_width-1):0] q;
81 5 unneback
   input                         clk;
82 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0];
83 7 unneback
   parameter init = 0;
84
   parameter memory_file = "vl_ram.vmem";
85
   generate if (init) begin : init_mem
86
   initial
87
     begin
88
        $readmemh(memory_file, ram);
89
     end
90
   end
91
   endgenerate
92
 
93 5 unneback
   always @ (posedge clk)
94
   begin
95
   if (we)
96
     ram[adr] <= d;
97
   q <= ram[adr];
98
   end
99
 
100
endmodule
101 40 unneback
`endif
102 5 unneback
 
103 40 unneback
`ifdef RAM_BE
104
`define MODULE ram_be
105 91 unneback
module `BASE`MODULE ( d, adr, be, we, q, clk);
106 40 unneback
`undef MODULE
107
 
108 7 unneback
   parameter data_width = 32;
109 72 unneback
   parameter addr_width = 6;
110 75 unneback
   parameter mem_size = 1<<addr_width;
111 7 unneback
   input [(data_width-1):0]      d;
112
   input [(addr_width-1):0]       adr;
113 73 unneback
   input [(data_width/8)-1:0]    be;
114 7 unneback
   input                         we;
115
   output reg [(data_width-1):0] q;
116
   input                         clk;
117
 
118 84 unneback
 
119 65 unneback
//E2_ifdef SYSTEMVERILOG
120 68 unneback
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
121 65 unneback
//E2_else
122 84 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
123
    wire [data_width/8-1:0] cke;
124 65 unneback
//E2_endif
125
 
126 60 unneback
   parameter memory_init = 0;
127 7 unneback
   parameter memory_file = "vl_ram.vmem";
128 60 unneback
   generate if (memory_init) begin : init_mem
129 7 unneback
   initial
130
     begin
131
        $readmemh(memory_file, ram);
132
     end
133
   end
134
   endgenerate
135
 
136 60 unneback
//E2_ifdef SYSTEMVERILOG
137
// use a multi-dimensional packed array
138
//to model individual bytes within the word
139
 
140
always_ff@(posedge clk)
141
begin
142
    if(we) begin // note: we should have a for statement to support any bus width
143 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
144
        if(be[2]) ram[adr][2] <= d[23:16];
145
        if(be[1]) ram[adr][1] <= d[15:8];
146
        if(be[0]) ram[adr][0] <= d[7:0];
147 60 unneback
    end
148 90 unneback
        q <= ram[adr];
149 60 unneback
end
150
 
151
//E2_else
152
 
153 84 unneback
assign cke = {data_width/8{we}} & be;
154 7 unneback
   genvar i;
155 84 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
156 7 unneback
      always @ (posedge clk)
157 84 unneback
      if (cke[i])
158 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
159
   end
160
   endgenerate
161
 
162
   always @ (posedge clk)
163
      q <= ram[adr];
164
 
165 60 unneback
//E2_endif
166
 
167 84 unneback
   // Function to access RAM (for use by Verilator).
168
   function [31:0] get_mem;
169
      // verilator public
170 90 unneback
      input [addr_width-1:0]             addr;
171 84 unneback
      get_mem = ram[addr];
172
   endfunction // get_mem
173
 
174
   // Function to write RAM (for use by Verilator).
175
   function set_mem;
176
      // verilator public
177 90 unneback
      input [addr_width-1:0]             addr;
178
      input [data_width-1:0]             data;
179 84 unneback
      ram[addr] = data;
180
   endfunction // set_mem
181
 
182 7 unneback
endmodule
183 40 unneback
`endif
184 7 unneback
 
185 5 unneback
`ifdef ACTEL
186 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
187 5 unneback
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
188
`else
189
        `define SYN
190
`endif
191
 
192 40 unneback
`ifdef DPRAM_1R1W
193
`define MODULE dpram_1r1w
194
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
195
`undef MODULE
196 5 unneback
   parameter data_width = 32;
197
   parameter addr_width = 8;
198 75 unneback
   parameter mem_size = 1<<addr_width;
199 5 unneback
   input [(data_width-1):0]      d_a;
200
   input [(addr_width-1):0]       adr_a;
201
   input [(addr_width-1):0]       adr_b;
202
   input                         we_a;
203
   output [(data_width-1):0]      q_b;
204
   input                         clk_a, clk_b;
205
   reg [(addr_width-1):0]         adr_b_reg;
206 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
207 7 unneback
 
208
   parameter init = 0;
209
   parameter memory_file = "vl_ram.vmem";
210
   generate if (init) begin : init_mem
211
   initial
212
     begin
213
        $readmemh(memory_file, ram);
214
     end
215
   end
216
   endgenerate
217
 
218 5 unneback
   always @ (posedge clk_a)
219
   if (we_a)
220
     ram[adr_a] <= d_a;
221
   always @ (posedge clk_b)
222
   adr_b_reg <= adr_b;
223
   assign q_b = ram[adr_b_reg];
224 40 unneback
 
225 5 unneback
endmodule
226 40 unneback
`endif
227 5 unneback
 
228 40 unneback
`ifdef DPRAM_2R1W
229
`define MODULE dpram_2r1w
230
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
231
`undef MODULE
232
 
233 5 unneback
   parameter data_width = 32;
234
   parameter addr_width = 8;
235 75 unneback
   parameter mem_size = 1<<addr_width;
236 5 unneback
   input [(data_width-1):0]      d_a;
237
   input [(addr_width-1):0]       adr_a;
238
   input [(addr_width-1):0]       adr_b;
239
   input                         we_a;
240
   output [(data_width-1):0]      q_b;
241
   output reg [(data_width-1):0] q_a;
242
   input                         clk_a, clk_b;
243
   reg [(data_width-1):0]         q_b;
244 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
245 7 unneback
 
246
   parameter init = 0;
247
   parameter memory_file = "vl_ram.vmem";
248
   generate if (init) begin : init_mem
249
   initial
250
     begin
251
        $readmemh(memory_file, ram);
252
     end
253
   end
254
   endgenerate
255
 
256 5 unneback
   always @ (posedge clk_a)
257
     begin
258
        q_a <= ram[adr_a];
259
        if (we_a)
260
             ram[adr_a] <= d_a;
261
     end
262
   always @ (posedge clk_b)
263
          q_b <= ram[adr_b];
264
endmodule
265 40 unneback
`endif
266 5 unneback
 
267 40 unneback
`ifdef DPRAM_2R2W
268
`define MODULE dpram_2r2w
269
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
270
`undef MODULE
271
 
272 5 unneback
   parameter data_width = 32;
273
   parameter addr_width = 8;
274 75 unneback
   parameter mem_size = 1<<addr_width;
275 5 unneback
   input [(data_width-1):0]      d_a;
276
   input [(addr_width-1):0]       adr_a;
277
   input [(addr_width-1):0]       adr_b;
278
   input                         we_a;
279
   output [(data_width-1):0]      q_b;
280
   input [(data_width-1):0]       d_b;
281
   output reg [(data_width-1):0] q_a;
282
   input                         we_b;
283
   input                         clk_a, clk_b;
284
   reg [(data_width-1):0]         q_b;
285 75 unneback
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
286 7 unneback
 
287
   parameter init = 0;
288
   parameter memory_file = "vl_ram.vmem";
289
   generate if (init) begin : init_mem
290
   initial
291
     begin
292
        $readmemh(memory_file, ram);
293
     end
294
   end
295
   endgenerate
296
 
297 5 unneback
   always @ (posedge clk_a)
298
     begin
299
        q_a <= ram[adr_a];
300
        if (we_a)
301
             ram[adr_a] <= d_a;
302
     end
303
   always @ (posedge clk_b)
304
     begin
305
        q_b <= ram[adr_b];
306
        if (we_b)
307
          ram[adr_b] <= d_b;
308
     end
309
endmodule
310 40 unneback
`endif
311 5 unneback
 
312 83 unneback
 
313 75 unneback
`ifdef DPRAM_BE_2R2W
314
`define MODULE dpram_be_2r2w
315 91 unneback
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, re_a, we_a, clk_a, d_b, q_b, adr_b, re_b, we_b, clk_b );
316 75 unneback
`undef MODULE
317
 
318
   parameter a_data_width = 32;
319
   parameter a_addr_width = 8;
320 91 unneback
   parameter b_data_width = 32;
321
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
322
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
323
 
324 75 unneback
   input [(a_data_width-1):0]      d_a;
325 91 unneback
   input [(a_addr_width-1):0]       adr_a;
326
   input [(a_data_width/8-1):0]    be_a;
327
   input                           re_a;
328
   input                           we_a;
329 75 unneback
   output reg [(a_data_width-1):0] q_a;
330 91 unneback
   input [(b_data_width-1):0]       d_b;
331
   input [(b_addr_width-1):0]       adr_b;
332
   input                           re_b,we_b;
333
   output [(b_data_width-1):0]      q_b;
334
   input                           clk_a, clk_b;
335 75 unneback
 
336 91 unneback
//E2_ifdef SYSTEMVERILOG
337
// use a multi-dimensional packed array
338
//to model individual bytes within the word
339
 
340 75 unneback
generate
341 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
342 75 unneback
 
343 91 unneback
   logic [3:0][7:0] ram [0:mem_size-1];
344
    reg [a_addr_width-1:0] rd_adr_a;
345
    reg [b_addr_width-1:0] rd_adr_b;
346
 
347
    always_ff@(posedge clk_a)
348
    begin
349
        if(we_a) begin
350
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
351
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
352
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
353
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
354
        end
355
    end
356
 
357
    always@(posedge clk_a or posedge rst)
358
    if (rst)
359
        rd_adr_a <= 0;
360
    else if (re_a)
361
        rd_adr_a <= adr_a;
362
 
363
    assign q_a = ram[rd_adr_a];
364
 
365
    always_ff@(posedge clk_b)
366
    if(we_b)
367
        ram[adr_b] <= d_b;
368
 
369
    always@(posedge clk_b or posedge rst)
370
    if (rst)
371
        rd_adr_b <= 0;
372
    else if (re_b)
373
        rd_adr_b <= adr_b;
374
 
375
    assign q_b = ram[rd_adr_b];
376
 
377 75 unneback
end
378
endgenerate
379
 
380 91 unneback
//E2_else
381
//E2_endif
382 75 unneback
endmodule
383
`endif
384
 
385 91 unneback
`ifdef CAM
386 5 unneback
// Content addresable memory, CAM
387 91 unneback
`endif
388 5 unneback
 
389 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
390 5 unneback
// FIFO
391 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
392
module `BASE`MODULE (
393
`undef MODULE
394 25 unneback
    d, wr, fifo_full,
395
    q, rd, fifo_empty,
396
    fill_level,
397
    clk, rst
398
    );
399
 
400
parameter data_width = 18;
401
parameter addr_width = 4;
402 5 unneback
 
403 25 unneback
// write side
404
input  [data_width-1:0] d;
405
input                   wr;
406
output                  fifo_full;
407
// read side
408
output [data_width-1:0] q;
409
input                   rd;
410
output                  fifo_empty;
411
// common
412
output [addr_width:0]   fill_level;
413
input rst, clk;
414
 
415
wire [addr_width:1] wadr, radr;
416
 
417 40 unneback
`define MODULE cnt_bin_ce
418
`BASE`MODULE
419 25 unneback
    # ( .length(addr_width))
420
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
421 40 unneback
`BASE`MODULE
422 25 unneback
    # (.length(addr_width))
423
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
424 40 unneback
`undef MODULE
425 25 unneback
 
426 40 unneback
`define MODULE dpram_1r1w
427
`BASE`MODULE
428 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
429
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
430 40 unneback
`undef MODULE
431 25 unneback
 
432 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
433
`BASE`MODULE
434 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
435 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
436 40 unneback
`undef MODULE
437 25 unneback
endmodule
438 40 unneback
`endif
439 25 unneback
 
440 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
441 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
442
// RAM is supposed to be larger than the two FIFOs
443
// LFSR counters used adr pointers
444 40 unneback
`define MODULE fifo_2r2w_sync_simplex
445
module `BASE`MODULE (
446
`undef MODULE
447 27 unneback
    // a side
448
    a_d, a_wr, a_fifo_full,
449
    a_q, a_rd, a_fifo_empty,
450
    a_fill_level,
451
    // b side
452
    b_d, b_wr, b_fifo_full,
453
    b_q, b_rd, b_fifo_empty,
454
    b_fill_level,
455
    // common
456
    clk, rst
457
    );
458
parameter data_width = 8;
459
parameter addr_width = 5;
460
parameter fifo_full_level = (1<<addr_width)-1;
461
 
462
// a side
463
input  [data_width-1:0] a_d;
464
input                   a_wr;
465
output                  a_fifo_full;
466
output [data_width-1:0] a_q;
467
input                   a_rd;
468
output                  a_fifo_empty;
469
output [addr_width-1:0] a_fill_level;
470
 
471
// b side
472
input  [data_width-1:0] b_d;
473
input                   b_wr;
474
output                  b_fifo_full;
475
output [data_width-1:0] b_q;
476
input                   b_rd;
477
output                  b_fifo_empty;
478
output [addr_width-1:0] b_fill_level;
479
 
480
input                   clk;
481
input                   rst;
482
 
483
// adr_gen
484
wire [addr_width:1] a_wadr, a_radr;
485
wire [addr_width:1] b_wadr, b_radr;
486
// dpram
487
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
488
 
489 40 unneback
`define MODULE cnt_lfsr_ce
490
`BASE`MODULE
491 27 unneback
    # ( .length(addr_width))
492
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
493
 
494 40 unneback
`BASE`MODULE
495 27 unneback
    # (.length(addr_width))
496
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
497
 
498 40 unneback
`BASE`MODULE
499 27 unneback
    # ( .length(addr_width))
500
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
501
 
502 40 unneback
`BASE`MODULE
503 27 unneback
    # (.length(addr_width))
504
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
505 40 unneback
`undef MODULE
506 27 unneback
 
507
// mux read or write adr to DPRAM
508
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
509
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
510
 
511 40 unneback
`define MODULE dpram_2r2w
512
`BASE`MODULE
513 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
514
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
515
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
516 40 unneback
`undef MODULE
517
 
518
`define MODULE cnt_bin_ce_rew_zq_l1
519
`BASE`MODULE
520 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
521 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
522
 
523 40 unneback
`BASE`MODULE
524 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
525 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
526 40 unneback
`undef MODULE
527 27 unneback
 
528
endmodule
529 40 unneback
`endif
530 27 unneback
 
531 40 unneback
`ifdef FIFO_CMP_ASYNC
532
`define MODULE fifo_cmp_async
533
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
534
`undef MODULE
535 5 unneback
 
536 11 unneback
   parameter addr_width = 4;
537
   parameter N = addr_width-1;
538 5 unneback
 
539
   parameter Q1 = 2'b00;
540
   parameter Q2 = 2'b01;
541
   parameter Q3 = 2'b11;
542
   parameter Q4 = 2'b10;
543
 
544
   parameter going_empty = 1'b0;
545
   parameter going_full  = 1'b1;
546
 
547
   input [N:0]  wptr, rptr;
548 14 unneback
   output       fifo_empty;
549 5 unneback
   output       fifo_full;
550
   input        wclk, rclk, rst;
551
 
552
`ifndef GENERATE_DIRECTION_AS_LATCH
553
   wire direction;
554
`endif
555
`ifdef GENERATE_DIRECTION_AS_LATCH
556
   reg direction;
557
`endif
558
   reg  direction_set, direction_clr;
559
 
560
   wire async_empty, async_full;
561
   wire fifo_full2;
562 14 unneback
   wire fifo_empty2;
563 5 unneback
 
564
   // direction_set
565
   always @ (wptr[N:N-1] or rptr[N:N-1])
566
     case ({wptr[N:N-1],rptr[N:N-1]})
567
       {Q1,Q2} : direction_set <= 1'b1;
568
       {Q2,Q3} : direction_set <= 1'b1;
569
       {Q3,Q4} : direction_set <= 1'b1;
570
       {Q4,Q1} : direction_set <= 1'b1;
571
       default : direction_set <= 1'b0;
572
     endcase
573
 
574
   // direction_clear
575
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
576
     if (rst)
577
       direction_clr <= 1'b1;
578
     else
579
       case ({wptr[N:N-1],rptr[N:N-1]})
580
         {Q2,Q1} : direction_clr <= 1'b1;
581
         {Q3,Q2} : direction_clr <= 1'b1;
582
         {Q4,Q3} : direction_clr <= 1'b1;
583
         {Q1,Q4} : direction_clr <= 1'b1;
584
         default : direction_clr <= 1'b0;
585
       endcase
586
 
587 40 unneback
`define MODULE dff_sr
588 5 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
589 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
590 5 unneback
`endif
591
 
592
`ifdef GENERATE_DIRECTION_AS_LATCH
593
   always @ (posedge direction_set or posedge direction_clr)
594
     if (direction_clr)
595
       direction <= going_empty;
596
     else
597
       direction <= going_full;
598
`endif
599
 
600
   assign async_empty = (wptr == rptr) && (direction==going_empty);
601
   assign async_full  = (wptr == rptr) && (direction==going_full);
602
 
603 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
604
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
605
`undef MODULE
606 5 unneback
 
607
/*
608
   always @ (posedge wclk or posedge rst or posedge async_full)
609
     if (rst)
610
       {fifo_full, fifo_full2} <= 2'b00;
611
     else if (async_full)
612
       {fifo_full, fifo_full2} <= 2'b11;
613
     else
614
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
615
*/
616 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
617 5 unneback
     if (async_empty)
618
       {fifo_empty, fifo_empty2} <= 2'b11;
619
     else
620 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
621 40 unneback
`define MODULE dff
622
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
623
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
624
`undef MODULE
625 25 unneback
endmodule // async_compb
626 40 unneback
`endif
627 5 unneback
 
628 40 unneback
`ifdef FIFO_1R1W_ASYNC
629
`define MODULE fifo_1r1w_async
630
module `BASE`MODULE (
631
`undef MODULE
632 5 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
633
    q, rd, fifo_empty, rd_clk, rd_rst
634
    );
635
 
636
parameter data_width = 18;
637
parameter addr_width = 4;
638
 
639
// write side
640
input  [data_width-1:0] d;
641
input                   wr;
642
output                  fifo_full;
643
input                   wr_clk;
644
input                   wr_rst;
645
// read side
646
output [data_width-1:0] q;
647
input                   rd;
648
output                  fifo_empty;
649
input                   rd_clk;
650
input                   rd_rst;
651
 
652
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
653 23 unneback
 
654 40 unneback
`define MODULE cnt_gray_ce_bin
655
`BASE`MODULE
656 5 unneback
    # ( .length(addr_width))
657
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
658
 
659 40 unneback
`BASE`MODULE
660 5 unneback
    # (.length(addr_width))
661 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
662 40 unneback
`undef MODULE
663 5 unneback
 
664 40 unneback
`define MODULE dpram_1r1w
665
`BASE`MODULE
666 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
667
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
668 40 unneback
`undef MODULE
669 5 unneback
 
670 40 unneback
`define MODULE fifo_cmp_async
671
`BASE`MODULE
672 5 unneback
    # (.addr_width(addr_width))
673
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
674 40 unneback
`undef MODULE
675 5 unneback
 
676
endmodule
677 40 unneback
`endif
678 5 unneback
 
679 40 unneback
`ifdef FIFO_2R2W_ASYNC
680
`define MODULE fifo_2r2w_async
681
module `BASE`MODULE (
682
`undef MODULE
683 5 unneback
    // a side
684
    a_d, a_wr, a_fifo_full,
685
    a_q, a_rd, a_fifo_empty,
686
    a_clk, a_rst,
687
    // b side
688
    b_d, b_wr, b_fifo_full,
689
    b_q, b_rd, b_fifo_empty,
690
    b_clk, b_rst
691
    );
692
 
693
parameter data_width = 18;
694
parameter addr_width = 4;
695
 
696
// a side
697
input  [data_width-1:0] a_d;
698
input                   a_wr;
699
output                  a_fifo_full;
700
output [data_width-1:0] a_q;
701
input                   a_rd;
702
output                  a_fifo_empty;
703
input                   a_clk;
704
input                   a_rst;
705
 
706
// b side
707
input  [data_width-1:0] b_d;
708
input                   b_wr;
709
output                  b_fifo_full;
710
output [data_width-1:0] b_q;
711
input                   b_rd;
712
output                  b_fifo_empty;
713
input                   b_clk;
714
input                   b_rst;
715
 
716 40 unneback
`define MODULE fifo_1r1w_async
717
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
718 5 unneback
vl_fifo_1r1w_async_a (
719
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
720
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
721
    );
722
 
723 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
724 5 unneback
vl_fifo_1r1w_async_b (
725
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
726
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
727
    );
728 40 unneback
`undef MODULE
729
 
730 5 unneback
endmodule
731 40 unneback
`endif
732 5 unneback
 
733 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
734
`define MODULE fifo_2r2w_async_simplex
735
module `BASE`MODULE (
736
`undef MODULE
737 5 unneback
    // a side
738
    a_d, a_wr, a_fifo_full,
739
    a_q, a_rd, a_fifo_empty,
740
    a_clk, a_rst,
741
    // b side
742
    b_d, b_wr, b_fifo_full,
743
    b_q, b_rd, b_fifo_empty,
744
    b_clk, b_rst
745
    );
746
 
747
parameter data_width = 18;
748
parameter addr_width = 4;
749
 
750
// a side
751
input  [data_width-1:0] a_d;
752
input                   a_wr;
753
output                  a_fifo_full;
754
output [data_width-1:0] a_q;
755
input                   a_rd;
756
output                  a_fifo_empty;
757
input                   a_clk;
758
input                   a_rst;
759
 
760
// b side
761
input  [data_width-1:0] b_d;
762
input                   b_wr;
763
output                  b_fifo_full;
764
output [data_width-1:0] b_q;
765
input                   b_rd;
766
output                  b_fifo_empty;
767
input                   b_clk;
768
input                   b_rst;
769
 
770
// adr_gen
771
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
772
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
773
// dpram
774
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
775
 
776 40 unneback
`define MODULE cnt_gray_ce_bin
777
`BASE`MODULE
778 5 unneback
    # ( .length(addr_width))
779
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
780
 
781 40 unneback
`BASE`MODULE
782 5 unneback
    # (.length(addr_width))
783
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
784
 
785 40 unneback
`BASE`MODULE
786 5 unneback
    # ( .length(addr_width))
787
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
788
 
789 40 unneback
`BASE`MODULE
790 5 unneback
    # (.length(addr_width))
791
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
792 40 unneback
`undef MODULE
793 5 unneback
 
794
// mux read or write adr to DPRAM
795
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
796
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
797
 
798 40 unneback
`define MODULE dpram_2r2w
799
`BASE`MODULE
800 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
801
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
802
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
803 40 unneback
`undef MODULE
804 5 unneback
 
805 40 unneback
`define MODULE fifo_cmp_async
806
`BASE`MODULE
807 5 unneback
    # (.addr_width(addr_width))
808
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
809
 
810 40 unneback
`BASE`MODULE
811 5 unneback
    # (.addr_width(addr_width))
812
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
813 40 unneback
`undef MODULE
814 5 unneback
 
815
endmodule
816 40 unneback
`endif
817 48 unneback
 
818
`ifdef REG_FILE
819
`define MODULE reg_file
820
module `BASE`MODULE (
821
`undef MODULE
822
    a1, a2, a3, wd3, we3, rd1, rd2, clk
823
);
824
parameter data_width = 32;
825
parameter addr_width = 5;
826
input [addr_width-1:0] a1, a2, a3;
827
input [data_width-1:0] wd3;
828
input we3;
829
output [data_width-1:0] rd1, rd2;
830
input clk;
831
 
832
`ifdef ACTEL
833
reg [data_width-1:0] wd3_reg;
834
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
835
reg we3_reg;
836
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
837
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
838
always @ (posedge clk or posedge rst)
839
if (rst)
840
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
841
else
842
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
843
 
844
    always @ (negedge clk)
845
    if (we3_reg)
846
        ram1[a3_reg] <= wd3;
847
    always @ (posedge clk)
848
        a1_reg <= a1;
849
    assign rd1 = ram1[a1_reg];
850
 
851
    always @ (negedge clk)
852
    if (we3_reg)
853
        ram2[a3_reg] <= wd3;
854
    always @ (posedge clk)
855
        a2_reg <= a2;
856
    assign rd2 = ram2[a2_reg];
857
 
858
`else
859
 
860
`define MODULE dpram_1r1w
861
`BASE`MODULE
862
    # ( .data_width(data_width), .addr_width(addr_width))
863
    ram1 (
864
        .d_a(wd3),
865
        .adr_a(a3),
866
        .we_a(we3),
867
        .clk_a(clk),
868
        .q_b(rd1),
869
        .adr_b(a1),
870
        .clk_b(clk) );
871
 
872
`BASE`MODULE
873
    # ( .data_width(data_width), .addr_width(addr_width))
874
    ram2 (
875
        .d_a(wd3),
876
        .adr_a(a3),
877
        .we_a(we3),
878
        .clk_a(clk),
879
        .q_b(rd2),
880
        .adr_b(a2),
881
        .clk_b(clk) );
882
`undef MODULE
883
 
884
`endif
885
 
886
endmodule
887
`endif

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