OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Blame information for rev 95

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, memories                                 ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  memories                                                    ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more memory types                                    ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef ROM_INIT
44 5 unneback
/// ROM
45 40 unneback
`define MODULE rom_init
46
module `BASE`MODULE ( adr, q, clk);
47
`undef MODULE
48 5 unneback
 
49 7 unneback
   parameter data_width = 32;
50
   parameter addr_width = 8;
51 75 unneback
   parameter mem_size = 1<<addr_width;
52 7 unneback
   input [(addr_width-1):0]       adr;
53
   output reg [(data_width-1):0] q;
54
   input                         clk;
55 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
56 7 unneback
   parameter memory_file = "vl_rom.vmem";
57
   initial
58
     begin
59
        $readmemh(memory_file, rom);
60
     end
61
 
62
   always @ (posedge clk)
63
     q <= rom[adr];
64 5 unneback
 
65 7 unneback
endmodule
66 40 unneback
`endif
67 7 unneback
 
68 40 unneback
`ifdef RAM
69
`define MODULE ram
70 5 unneback
// Single port RAM
71 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
72
`undef MODULE
73 5 unneback
 
74
   parameter data_width = 32;
75
   parameter addr_width = 8;
76 75 unneback
   parameter mem_size = 1<<addr_width;
77 5 unneback
   input [(data_width-1):0]      d;
78
   input [(addr_width-1):0]       adr;
79
   input                         we;
80 7 unneback
   output reg [(data_width-1):0] q;
81 5 unneback
   input                         clk;
82 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0];
83 7 unneback
   parameter init = 0;
84
   parameter memory_file = "vl_ram.vmem";
85
   generate if (init) begin : init_mem
86
   initial
87
     begin
88
        $readmemh(memory_file, ram);
89
     end
90
   end
91
   endgenerate
92
 
93 5 unneback
   always @ (posedge clk)
94
   begin
95
   if (we)
96
     ram[adr] <= d;
97
   q <= ram[adr];
98
   end
99
 
100
endmodule
101 40 unneback
`endif
102 5 unneback
 
103 40 unneback
`ifdef RAM_BE
104
`define MODULE ram_be
105 91 unneback
module `BASE`MODULE ( d, adr, be, we, q, clk);
106 40 unneback
`undef MODULE
107
 
108 7 unneback
   parameter data_width = 32;
109 72 unneback
   parameter addr_width = 6;
110 75 unneback
   parameter mem_size = 1<<addr_width;
111 7 unneback
   input [(data_width-1):0]      d;
112
   input [(addr_width-1):0]       adr;
113 73 unneback
   input [(data_width/8)-1:0]    be;
114 7 unneback
   input                         we;
115
   output reg [(data_width-1):0] q;
116
   input                         clk;
117
 
118 84 unneback
 
119 65 unneback
//E2_ifdef SYSTEMVERILOG
120 95 unneback
    // use a multi-dimensional packed array
121
    //t o model individual bytes within the word
122
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
123 65 unneback
//E2_else
124 84 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
125
    wire [data_width/8-1:0] cke;
126 65 unneback
//E2_endif
127
 
128 60 unneback
   parameter memory_init = 0;
129 7 unneback
   parameter memory_file = "vl_ram.vmem";
130 60 unneback
   generate if (memory_init) begin : init_mem
131 7 unneback
   initial
132
     begin
133
        $readmemh(memory_file, ram);
134
     end
135
   end
136
   endgenerate
137
 
138 60 unneback
//E2_ifdef SYSTEMVERILOG
139
 
140
always_ff@(posedge clk)
141
begin
142 95 unneback
    if(we) begin
143 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
144
        if(be[2]) ram[adr][2] <= d[23:16];
145
        if(be[1]) ram[adr][1] <= d[15:8];
146
        if(be[0]) ram[adr][0] <= d[7:0];
147 60 unneback
    end
148 90 unneback
        q <= ram[adr];
149 60 unneback
end
150
 
151
//E2_else
152
 
153 84 unneback
assign cke = {data_width/8{we}} & be;
154 7 unneback
   genvar i;
155 84 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
156 7 unneback
      always @ (posedge clk)
157 84 unneback
      if (cke[i])
158 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
159
   end
160
   endgenerate
161
 
162
   always @ (posedge clk)
163
      q <= ram[adr];
164
 
165 60 unneback
//E2_endif
166
 
167 93 unneback
//E2_ifdef verilator
168 84 unneback
   // Function to access RAM (for use by Verilator).
169
   function [31:0] get_mem;
170
      // verilator public
171 90 unneback
      input [addr_width-1:0]             addr;
172 84 unneback
      get_mem = ram[addr];
173
   endfunction // get_mem
174
 
175
   // Function to write RAM (for use by Verilator).
176
   function set_mem;
177
      // verilator public
178 90 unneback
      input [addr_width-1:0]             addr;
179
      input [data_width-1:0]             data;
180 84 unneback
      ram[addr] = data;
181
   endfunction // set_mem
182 93 unneback
//E2_endif
183 84 unneback
 
184 7 unneback
endmodule
185 40 unneback
`endif
186 7 unneback
 
187 5 unneback
`ifdef ACTEL
188 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
189 5 unneback
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
190
`else
191
        `define SYN
192
`endif
193
 
194 40 unneback
`ifdef DPRAM_1R1W
195
`define MODULE dpram_1r1w
196
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
197
`undef MODULE
198 5 unneback
   parameter data_width = 32;
199
   parameter addr_width = 8;
200 75 unneback
   parameter mem_size = 1<<addr_width;
201 5 unneback
   input [(data_width-1):0]      d_a;
202
   input [(addr_width-1):0]       adr_a;
203
   input [(addr_width-1):0]       adr_b;
204
   input                         we_a;
205
   output [(data_width-1):0]      q_b;
206
   input                         clk_a, clk_b;
207
   reg [(addr_width-1):0]         adr_b_reg;
208 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
209 7 unneback
 
210
   parameter init = 0;
211
   parameter memory_file = "vl_ram.vmem";
212
   generate if (init) begin : init_mem
213
   initial
214
     begin
215
        $readmemh(memory_file, ram);
216
     end
217
   end
218
   endgenerate
219
 
220 5 unneback
   always @ (posedge clk_a)
221
   if (we_a)
222
     ram[adr_a] <= d_a;
223
   always @ (posedge clk_b)
224
   adr_b_reg <= adr_b;
225
   assign q_b = ram[adr_b_reg];
226 40 unneback
 
227 5 unneback
endmodule
228 40 unneback
`endif
229 5 unneback
 
230 40 unneback
`ifdef DPRAM_2R1W
231
`define MODULE dpram_2r1w
232
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
233
`undef MODULE
234
 
235 5 unneback
   parameter data_width = 32;
236
   parameter addr_width = 8;
237 75 unneback
   parameter mem_size = 1<<addr_width;
238 5 unneback
   input [(data_width-1):0]      d_a;
239
   input [(addr_width-1):0]       adr_a;
240
   input [(addr_width-1):0]       adr_b;
241
   input                         we_a;
242
   output [(data_width-1):0]      q_b;
243
   output reg [(data_width-1):0] q_a;
244
   input                         clk_a, clk_b;
245
   reg [(data_width-1):0]         q_b;
246 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
247 7 unneback
 
248
   parameter init = 0;
249
   parameter memory_file = "vl_ram.vmem";
250
   generate if (init) begin : init_mem
251
   initial
252
     begin
253
        $readmemh(memory_file, ram);
254
     end
255
   end
256
   endgenerate
257
 
258 5 unneback
   always @ (posedge clk_a)
259
     begin
260
        q_a <= ram[adr_a];
261
        if (we_a)
262
             ram[adr_a] <= d_a;
263
     end
264
   always @ (posedge clk_b)
265
          q_b <= ram[adr_b];
266
endmodule
267 40 unneback
`endif
268 5 unneback
 
269 40 unneback
`ifdef DPRAM_2R2W
270
`define MODULE dpram_2r2w
271
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
272
`undef MODULE
273
 
274 5 unneback
   parameter data_width = 32;
275
   parameter addr_width = 8;
276 75 unneback
   parameter mem_size = 1<<addr_width;
277 5 unneback
   input [(data_width-1):0]      d_a;
278
   input [(addr_width-1):0]       adr_a;
279
   input [(addr_width-1):0]       adr_b;
280
   input                         we_a;
281
   output [(data_width-1):0]      q_b;
282
   input [(data_width-1):0]       d_b;
283
   output reg [(data_width-1):0] q_a;
284
   input                         we_b;
285
   input                         clk_a, clk_b;
286
   reg [(data_width-1):0]         q_b;
287 75 unneback
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
288 7 unneback
 
289
   parameter init = 0;
290
   parameter memory_file = "vl_ram.vmem";
291
   generate if (init) begin : init_mem
292
   initial
293
     begin
294
        $readmemh(memory_file, ram);
295
     end
296
   end
297
   endgenerate
298
 
299 5 unneback
   always @ (posedge clk_a)
300
     begin
301
        q_a <= ram[adr_a];
302
        if (we_a)
303
             ram[adr_a] <= d_a;
304
     end
305
   always @ (posedge clk_b)
306
     begin
307
        q_b <= ram[adr_b];
308
        if (we_b)
309
          ram[adr_b] <= d_b;
310
     end
311
endmodule
312 40 unneback
`endif
313 5 unneback
 
314 83 unneback
 
315 75 unneback
`ifdef DPRAM_BE_2R2W
316
`define MODULE dpram_be_2r2w
317 92 unneback
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
318 75 unneback
`undef MODULE
319
 
320
   parameter a_data_width = 32;
321
   parameter a_addr_width = 8;
322 95 unneback
   parameter b_data_width = 64; //a_data_width;
323 91 unneback
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
324 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
325
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
326 91 unneback
 
327 95 unneback
   parameter init = 0;
328
   parameter memory_file = "vl_ram.vmem";
329
 
330 75 unneback
   input [(a_data_width-1):0]      d_a;
331 91 unneback
   input [(a_addr_width-1):0]       adr_a;
332
   input [(a_data_width/8-1):0]    be_a;
333
   input                           we_a;
334 75 unneback
   output reg [(a_data_width-1):0] q_a;
335 91 unneback
   input [(b_data_width-1):0]       d_b;
336
   input [(b_addr_width-1):0]       adr_b;
337 92 unneback
   input [(b_data_width/8-1):0]    be_b;
338
   input                           we_b;
339
   output reg [(b_data_width-1):0]          q_b;
340 91 unneback
   input                           clk_a, clk_b;
341 75 unneback
 
342 91 unneback
//E2_ifdef SYSTEMVERILOG
343
// use a multi-dimensional packed array
344
//to model individual bytes within the word
345
 
346 75 unneback
generate
347 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
348 75 unneback
 
349 95 unneback
    logic [0:3][7:0] ram [0:mem_size-1];
350
 
351
    initial
352
        if (init)
353
            $readmemh(memory_file, ram);
354 91 unneback
 
355
    always_ff@(posedge clk_a)
356
    begin
357
        if(we_a) begin
358
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
359
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
360
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
361
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
362
        end
363
    end
364
 
365 92 unneback
    always@(posedge clk_a)
366
        q_a = ram[adr_a];
367 91 unneback
 
368
    always_ff@(posedge clk_b)
369 92 unneback
    begin
370
        if(we_b) begin
371
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
372
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
373
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
374
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
375
        end
376
    end
377 91 unneback
 
378 92 unneback
    always@(posedge clk_b)
379
        q_b = ram[adr_b];
380 91 unneback
 
381 75 unneback
end
382
endgenerate
383
 
384 95 unneback
generate
385
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
386
 
387
    logic [0:7][7:0] ram [0:mem_size-1];
388
 
389
    initial
390
        if (init)
391
            $readmemh(memory_file, ram);
392
 
393
    always_ff@(posedge clk_a)
394
    begin
395
        if(we_a) begin
396
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
397
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
398
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
399
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
400
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
401
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
402
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
403
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
404
        end
405
    end
406
 
407
    always@(posedge clk_a)
408
        q_a = ram[adr_a];
409
 
410
    always_ff@(posedge clk_b)
411
    begin
412
        if(we_b) begin
413
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
414
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
415
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
416
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
417
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
418
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
419
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
420
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
421
        end
422
    end
423
 
424
    always@(posedge clk_b)
425
        q_b = ram[adr_b];
426
 
427
end
428
endgenerate
429
 
430
generate
431
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
432
logic [31:0] temp;
433
`define MODULE dpram_be_2r2w
434
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
435
`undef MODULE
436
dpram6464 (
437
    .d_a(d_a),
438
    .q_a(q_a),
439
    .adr_a(adr_a),
440
    .be_a(be_a),
441
    .we_a(we_a),
442
    .clk_a(clk_a),
443
    .d_b({d_b,d_b}),
444
    .q_b(temp),
445
    .adr_b(adr_b),
446
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
447
    .we_b(we_b),
448
    .clk_b(clk_b)
449
);
450
 
451
always_comb
452
    if (adr_b[0])
453
        q_b = temp[31:16];
454
    else
455
        q_b = temp[15:0];
456
 
457
end
458
endgenerate
459
 
460
generate
461
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
462
logic [63:0] temp;
463
`define MODULE dpram_be_2r2w
464
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
465
`undef MODULE
466
dpram6464 (
467
    .d_a({d_a,d_a}),
468
    .q_a(temp),
469
    .adr_a(adr_a[a_addr_width-1:1]),
470
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
471
    .we_a(we_a),
472
    .clk_a(clk_a),
473
    .d_b(d_b),
474
    .q_b(q_b),
475
    .adr_b(adr_b),
476
    .be_b(be_b),
477
    .we_b(we_b),
478
    .clk_b(clk_b)
479
);
480
 
481
always_comb
482
    if (adr_a[0])
483
        q_a = temp[63:32];
484
    else
485
        q_a = temp[31:0];
486
 
487
end
488
endgenerate
489
 
490 91 unneback
//E2_else
491 92 unneback
    // This modules requires SystemVerilog
492 91 unneback
//E2_endif
493 75 unneback
endmodule
494
`endif
495
 
496 91 unneback
`ifdef CAM
497 5 unneback
// Content addresable memory, CAM
498 91 unneback
`endif
499 5 unneback
 
500 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
501 5 unneback
// FIFO
502 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
503
module `BASE`MODULE (
504
`undef MODULE
505 25 unneback
    d, wr, fifo_full,
506
    q, rd, fifo_empty,
507
    fill_level,
508
    clk, rst
509
    );
510
 
511
parameter data_width = 18;
512
parameter addr_width = 4;
513 5 unneback
 
514 25 unneback
// write side
515
input  [data_width-1:0] d;
516
input                   wr;
517
output                  fifo_full;
518
// read side
519
output [data_width-1:0] q;
520
input                   rd;
521
output                  fifo_empty;
522
// common
523
output [addr_width:0]   fill_level;
524
input rst, clk;
525
 
526
wire [addr_width:1] wadr, radr;
527
 
528 40 unneback
`define MODULE cnt_bin_ce
529
`BASE`MODULE
530 25 unneback
    # ( .length(addr_width))
531
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
532 40 unneback
`BASE`MODULE
533 25 unneback
    # (.length(addr_width))
534
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
535 40 unneback
`undef MODULE
536 25 unneback
 
537 40 unneback
`define MODULE dpram_1r1w
538
`BASE`MODULE
539 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
540
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
541 40 unneback
`undef MODULE
542 25 unneback
 
543 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
544
`BASE`MODULE
545 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
546 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
547 40 unneback
`undef MODULE
548 25 unneback
endmodule
549 40 unneback
`endif
550 25 unneback
 
551 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
552 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
553
// RAM is supposed to be larger than the two FIFOs
554
// LFSR counters used adr pointers
555 40 unneback
`define MODULE fifo_2r2w_sync_simplex
556
module `BASE`MODULE (
557
`undef MODULE
558 27 unneback
    // a side
559
    a_d, a_wr, a_fifo_full,
560
    a_q, a_rd, a_fifo_empty,
561
    a_fill_level,
562
    // b side
563
    b_d, b_wr, b_fifo_full,
564
    b_q, b_rd, b_fifo_empty,
565
    b_fill_level,
566
    // common
567
    clk, rst
568
    );
569
parameter data_width = 8;
570
parameter addr_width = 5;
571
parameter fifo_full_level = (1<<addr_width)-1;
572
 
573
// a side
574
input  [data_width-1:0] a_d;
575
input                   a_wr;
576
output                  a_fifo_full;
577
output [data_width-1:0] a_q;
578
input                   a_rd;
579
output                  a_fifo_empty;
580
output [addr_width-1:0] a_fill_level;
581
 
582
// b side
583
input  [data_width-1:0] b_d;
584
input                   b_wr;
585
output                  b_fifo_full;
586
output [data_width-1:0] b_q;
587
input                   b_rd;
588
output                  b_fifo_empty;
589
output [addr_width-1:0] b_fill_level;
590
 
591
input                   clk;
592
input                   rst;
593
 
594
// adr_gen
595
wire [addr_width:1] a_wadr, a_radr;
596
wire [addr_width:1] b_wadr, b_radr;
597
// dpram
598
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
599
 
600 40 unneback
`define MODULE cnt_lfsr_ce
601
`BASE`MODULE
602 27 unneback
    # ( .length(addr_width))
603
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
604
 
605 40 unneback
`BASE`MODULE
606 27 unneback
    # (.length(addr_width))
607
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
608
 
609 40 unneback
`BASE`MODULE
610 27 unneback
    # ( .length(addr_width))
611
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
612
 
613 40 unneback
`BASE`MODULE
614 27 unneback
    # (.length(addr_width))
615
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
616 40 unneback
`undef MODULE
617 27 unneback
 
618
// mux read or write adr to DPRAM
619
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
620
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
621
 
622 40 unneback
`define MODULE dpram_2r2w
623
`BASE`MODULE
624 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
625
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
626
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
627 40 unneback
`undef MODULE
628
 
629
`define MODULE cnt_bin_ce_rew_zq_l1
630
`BASE`MODULE
631 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
632 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
633
 
634 40 unneback
`BASE`MODULE
635 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
636 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
637 40 unneback
`undef MODULE
638 27 unneback
 
639
endmodule
640 40 unneback
`endif
641 27 unneback
 
642 40 unneback
`ifdef FIFO_CMP_ASYNC
643
`define MODULE fifo_cmp_async
644
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
645
`undef MODULE
646 5 unneback
 
647 11 unneback
   parameter addr_width = 4;
648
   parameter N = addr_width-1;
649 5 unneback
 
650
   parameter Q1 = 2'b00;
651
   parameter Q2 = 2'b01;
652
   parameter Q3 = 2'b11;
653
   parameter Q4 = 2'b10;
654
 
655
   parameter going_empty = 1'b0;
656
   parameter going_full  = 1'b1;
657
 
658
   input [N:0]  wptr, rptr;
659 14 unneback
   output       fifo_empty;
660 5 unneback
   output       fifo_full;
661
   input        wclk, rclk, rst;
662
 
663
`ifndef GENERATE_DIRECTION_AS_LATCH
664
   wire direction;
665
`endif
666
`ifdef GENERATE_DIRECTION_AS_LATCH
667
   reg direction;
668
`endif
669
   reg  direction_set, direction_clr;
670
 
671
   wire async_empty, async_full;
672
   wire fifo_full2;
673 14 unneback
   wire fifo_empty2;
674 5 unneback
 
675
   // direction_set
676
   always @ (wptr[N:N-1] or rptr[N:N-1])
677
     case ({wptr[N:N-1],rptr[N:N-1]})
678
       {Q1,Q2} : direction_set <= 1'b1;
679
       {Q2,Q3} : direction_set <= 1'b1;
680
       {Q3,Q4} : direction_set <= 1'b1;
681
       {Q4,Q1} : direction_set <= 1'b1;
682
       default : direction_set <= 1'b0;
683
     endcase
684
 
685
   // direction_clear
686
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
687
     if (rst)
688
       direction_clr <= 1'b1;
689
     else
690
       case ({wptr[N:N-1],rptr[N:N-1]})
691
         {Q2,Q1} : direction_clr <= 1'b1;
692
         {Q3,Q2} : direction_clr <= 1'b1;
693
         {Q4,Q3} : direction_clr <= 1'b1;
694
         {Q1,Q4} : direction_clr <= 1'b1;
695
         default : direction_clr <= 1'b0;
696
       endcase
697
 
698 40 unneback
`define MODULE dff_sr
699 5 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
700 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
701 5 unneback
`endif
702
 
703
`ifdef GENERATE_DIRECTION_AS_LATCH
704
   always @ (posedge direction_set or posedge direction_clr)
705
     if (direction_clr)
706
       direction <= going_empty;
707
     else
708
       direction <= going_full;
709
`endif
710
 
711
   assign async_empty = (wptr == rptr) && (direction==going_empty);
712
   assign async_full  = (wptr == rptr) && (direction==going_full);
713
 
714 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
715
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
716
`undef MODULE
717 5 unneback
 
718
/*
719
   always @ (posedge wclk or posedge rst or posedge async_full)
720
     if (rst)
721
       {fifo_full, fifo_full2} <= 2'b00;
722
     else if (async_full)
723
       {fifo_full, fifo_full2} <= 2'b11;
724
     else
725
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
726
*/
727 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
728 5 unneback
     if (async_empty)
729
       {fifo_empty, fifo_empty2} <= 2'b11;
730
     else
731 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
732 40 unneback
`define MODULE dff
733
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
734
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
735
`undef MODULE
736 25 unneback
endmodule // async_compb
737 40 unneback
`endif
738 5 unneback
 
739 40 unneback
`ifdef FIFO_1R1W_ASYNC
740
`define MODULE fifo_1r1w_async
741
module `BASE`MODULE (
742
`undef MODULE
743 5 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
744
    q, rd, fifo_empty, rd_clk, rd_rst
745
    );
746
 
747
parameter data_width = 18;
748
parameter addr_width = 4;
749
 
750
// write side
751
input  [data_width-1:0] d;
752
input                   wr;
753
output                  fifo_full;
754
input                   wr_clk;
755
input                   wr_rst;
756
// read side
757
output [data_width-1:0] q;
758
input                   rd;
759
output                  fifo_empty;
760
input                   rd_clk;
761
input                   rd_rst;
762
 
763
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
764 23 unneback
 
765 40 unneback
`define MODULE cnt_gray_ce_bin
766
`BASE`MODULE
767 5 unneback
    # ( .length(addr_width))
768
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
769
 
770 40 unneback
`BASE`MODULE
771 5 unneback
    # (.length(addr_width))
772 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
773 40 unneback
`undef MODULE
774 5 unneback
 
775 40 unneback
`define MODULE dpram_1r1w
776
`BASE`MODULE
777 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
778
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
779 40 unneback
`undef MODULE
780 5 unneback
 
781 40 unneback
`define MODULE fifo_cmp_async
782
`BASE`MODULE
783 5 unneback
    # (.addr_width(addr_width))
784
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
785 40 unneback
`undef MODULE
786 5 unneback
 
787
endmodule
788 40 unneback
`endif
789 5 unneback
 
790 40 unneback
`ifdef FIFO_2R2W_ASYNC
791
`define MODULE fifo_2r2w_async
792
module `BASE`MODULE (
793
`undef MODULE
794 5 unneback
    // a side
795
    a_d, a_wr, a_fifo_full,
796
    a_q, a_rd, a_fifo_empty,
797
    a_clk, a_rst,
798
    // b side
799
    b_d, b_wr, b_fifo_full,
800
    b_q, b_rd, b_fifo_empty,
801
    b_clk, b_rst
802
    );
803
 
804
parameter data_width = 18;
805
parameter addr_width = 4;
806
 
807
// a side
808
input  [data_width-1:0] a_d;
809
input                   a_wr;
810
output                  a_fifo_full;
811
output [data_width-1:0] a_q;
812
input                   a_rd;
813
output                  a_fifo_empty;
814
input                   a_clk;
815
input                   a_rst;
816
 
817
// b side
818
input  [data_width-1:0] b_d;
819
input                   b_wr;
820
output                  b_fifo_full;
821
output [data_width-1:0] b_q;
822
input                   b_rd;
823
output                  b_fifo_empty;
824
input                   b_clk;
825
input                   b_rst;
826
 
827 40 unneback
`define MODULE fifo_1r1w_async
828
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
829 5 unneback
vl_fifo_1r1w_async_a (
830
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
831
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
832
    );
833
 
834 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
835 5 unneback
vl_fifo_1r1w_async_b (
836
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
837
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
838
    );
839 40 unneback
`undef MODULE
840
 
841 5 unneback
endmodule
842 40 unneback
`endif
843 5 unneback
 
844 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
845
`define MODULE fifo_2r2w_async_simplex
846
module `BASE`MODULE (
847
`undef MODULE
848 5 unneback
    // a side
849
    a_d, a_wr, a_fifo_full,
850
    a_q, a_rd, a_fifo_empty,
851
    a_clk, a_rst,
852
    // b side
853
    b_d, b_wr, b_fifo_full,
854
    b_q, b_rd, b_fifo_empty,
855
    b_clk, b_rst
856
    );
857
 
858
parameter data_width = 18;
859
parameter addr_width = 4;
860
 
861
// a side
862
input  [data_width-1:0] a_d;
863
input                   a_wr;
864
output                  a_fifo_full;
865
output [data_width-1:0] a_q;
866
input                   a_rd;
867
output                  a_fifo_empty;
868
input                   a_clk;
869
input                   a_rst;
870
 
871
// b side
872
input  [data_width-1:0] b_d;
873
input                   b_wr;
874
output                  b_fifo_full;
875
output [data_width-1:0] b_q;
876
input                   b_rd;
877
output                  b_fifo_empty;
878
input                   b_clk;
879
input                   b_rst;
880
 
881
// adr_gen
882
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
883
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
884
// dpram
885
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
886
 
887 40 unneback
`define MODULE cnt_gray_ce_bin
888
`BASE`MODULE
889 5 unneback
    # ( .length(addr_width))
890
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
891
 
892 40 unneback
`BASE`MODULE
893 5 unneback
    # (.length(addr_width))
894
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
895
 
896 40 unneback
`BASE`MODULE
897 5 unneback
    # ( .length(addr_width))
898
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
899
 
900 40 unneback
`BASE`MODULE
901 5 unneback
    # (.length(addr_width))
902
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
903 40 unneback
`undef MODULE
904 5 unneback
 
905
// mux read or write adr to DPRAM
906
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
907
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
908
 
909 40 unneback
`define MODULE dpram_2r2w
910
`BASE`MODULE
911 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
912
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
913
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
914 40 unneback
`undef MODULE
915 5 unneback
 
916 40 unneback
`define MODULE fifo_cmp_async
917
`BASE`MODULE
918 5 unneback
    # (.addr_width(addr_width))
919
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
920
 
921 40 unneback
`BASE`MODULE
922 5 unneback
    # (.addr_width(addr_width))
923
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
924 40 unneback
`undef MODULE
925 5 unneback
 
926
endmodule
927 40 unneback
`endif
928 48 unneback
 
929
`ifdef REG_FILE
930
`define MODULE reg_file
931
module `BASE`MODULE (
932
`undef MODULE
933
    a1, a2, a3, wd3, we3, rd1, rd2, clk
934
);
935
parameter data_width = 32;
936
parameter addr_width = 5;
937
input [addr_width-1:0] a1, a2, a3;
938
input [data_width-1:0] wd3;
939
input we3;
940
output [data_width-1:0] rd1, rd2;
941
input clk;
942
 
943
`ifdef ACTEL
944
reg [data_width-1:0] wd3_reg;
945
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
946
reg we3_reg;
947
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
948
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
949
always @ (posedge clk or posedge rst)
950
if (rst)
951
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
952
else
953
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
954
 
955
    always @ (negedge clk)
956
    if (we3_reg)
957
        ram1[a3_reg] <= wd3;
958
    always @ (posedge clk)
959
        a1_reg <= a1;
960
    assign rd1 = ram1[a1_reg];
961
 
962
    always @ (negedge clk)
963
    if (we3_reg)
964
        ram2[a3_reg] <= wd3;
965
    always @ (posedge clk)
966
        a2_reg <= a2;
967
    assign rd2 = ram2[a2_reg];
968
 
969
`else
970
 
971
`define MODULE dpram_1r1w
972
`BASE`MODULE
973
    # ( .data_width(data_width), .addr_width(addr_width))
974
    ram1 (
975
        .d_a(wd3),
976
        .adr_a(a3),
977
        .we_a(we3),
978
        .clk_a(clk),
979
        .q_b(rd1),
980
        .adr_b(a1),
981
        .clk_b(clk) );
982
 
983
`BASE`MODULE
984
    # ( .data_width(data_width), .addr_width(addr_width))
985
    ram2 (
986
        .d_a(wd3),
987
        .adr_a(a3),
988
        .we_a(we3),
989
        .clk_a(clk),
990
        .q_b(rd2),
991
        .adr_b(a2),
992
        .clk_b(clk) );
993
`undef MODULE
994
 
995
`endif
996
 
997
endmodule
998
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.