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1 5 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, memories                                 ////
4
////                                                              ////
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////  Description                                                 ////
6
////  memories                                                    ////
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////                                                              ////
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////                                                              ////
9
////  To Do:                                                      ////
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////   - add more memory types                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
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////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef ROM_INIT
44 5 unneback
/// ROM
45 40 unneback
`define MODULE rom_init
46
module `BASE`MODULE ( adr, q, clk);
47
`undef MODULE
48 5 unneback
 
49 7 unneback
   parameter data_width = 32;
50
   parameter addr_width = 8;
51 75 unneback
   parameter mem_size = 1<<addr_width;
52 7 unneback
   input [(addr_width-1):0]       adr;
53
   output reg [(data_width-1):0] q;
54
   input                         clk;
55 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
56 7 unneback
   parameter memory_file = "vl_rom.vmem";
57
   initial
58
     begin
59
        $readmemh(memory_file, rom);
60
     end
61
 
62
   always @ (posedge clk)
63
     q <= rom[adr];
64 5 unneback
 
65 7 unneback
endmodule
66 40 unneback
`endif
67 7 unneback
 
68 40 unneback
`ifdef RAM
69
`define MODULE ram
70 5 unneback
// Single port RAM
71 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
72
`undef MODULE
73 5 unneback
 
74
   parameter data_width = 32;
75
   parameter addr_width = 8;
76 75 unneback
   parameter mem_size = 1<<addr_width;
77 5 unneback
   input [(data_width-1):0]      d;
78
   input [(addr_width-1):0]       adr;
79
   input                         we;
80 7 unneback
   output reg [(data_width-1):0] q;
81 5 unneback
   input                         clk;
82 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
83 7 unneback
   parameter init = 0;
84
   parameter memory_file = "vl_ram.vmem";
85
   generate if (init) begin : init_mem
86
   initial
87
     begin
88
        $readmemh(memory_file, ram);
89
     end
90
   end
91
   endgenerate
92
 
93 5 unneback
   always @ (posedge clk)
94
   begin
95
   if (we)
96
     ram[adr] <= d;
97
   q <= ram[adr];
98
   end
99
 
100
endmodule
101 40 unneback
`endif
102 5 unneback
 
103 40 unneback
`ifdef RAM_BE
104
`define MODULE ram_be
105 91 unneback
module `BASE`MODULE ( d, adr, be, we, q, clk);
106 40 unneback
`undef MODULE
107
 
108 7 unneback
   parameter data_width = 32;
109 72 unneback
   parameter addr_width = 6;
110 75 unneback
   parameter mem_size = 1<<addr_width;
111 7 unneback
   input [(data_width-1):0]      d;
112
   input [(addr_width-1):0]       adr;
113 73 unneback
   input [(data_width/8)-1:0]    be;
114 7 unneback
   input                         we;
115
   output reg [(data_width-1):0] q;
116
   input                         clk;
117
 
118 84 unneback
 
119 65 unneback
//E2_ifdef SYSTEMVERILOG
120 95 unneback
    // use a multi-dimensional packed array
121
    //t o model individual bytes within the word
122
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
123 65 unneback
//E2_else
124 84 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
125
    wire [data_width/8-1:0] cke;
126 65 unneback
//E2_endif
127
 
128 60 unneback
   parameter memory_init = 0;
129 7 unneback
   parameter memory_file = "vl_ram.vmem";
130 60 unneback
   generate if (memory_init) begin : init_mem
131 7 unneback
   initial
132
     begin
133
        $readmemh(memory_file, ram);
134
     end
135
   end
136
   endgenerate
137
 
138 60 unneback
//E2_ifdef SYSTEMVERILOG
139
 
140
always_ff@(posedge clk)
141
begin
142 95 unneback
    if(we) begin
143 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
144
        if(be[2]) ram[adr][2] <= d[23:16];
145
        if(be[1]) ram[adr][1] <= d[15:8];
146
        if(be[0]) ram[adr][0] <= d[7:0];
147 60 unneback
    end
148 90 unneback
        q <= ram[adr];
149 60 unneback
end
150
 
151
//E2_else
152
 
153 84 unneback
assign cke = {data_width/8{we}} & be;
154 7 unneback
   genvar i;
155 84 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
156 7 unneback
      always @ (posedge clk)
157 84 unneback
      if (cke[i])
158 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
159
   end
160
   endgenerate
161
 
162
   always @ (posedge clk)
163
      q <= ram[adr];
164
 
165 60 unneback
//E2_endif
166
 
167 93 unneback
//E2_ifdef verilator
168 84 unneback
   // Function to access RAM (for use by Verilator).
169
   function [31:0] get_mem;
170
      // verilator public
171 90 unneback
      input [addr_width-1:0]             addr;
172 84 unneback
      get_mem = ram[addr];
173
   endfunction // get_mem
174
 
175
   // Function to write RAM (for use by Verilator).
176
   function set_mem;
177
      // verilator public
178 90 unneback
      input [addr_width-1:0]             addr;
179
      input [data_width-1:0]             data;
180 84 unneback
      ram[addr] = data;
181
   endfunction // set_mem
182 93 unneback
//E2_endif
183 84 unneback
 
184 7 unneback
endmodule
185 40 unneback
`endif
186 7 unneback
 
187 40 unneback
`ifdef DPRAM_1R1W
188
`define MODULE dpram_1r1w
189
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
190
`undef MODULE
191 5 unneback
   parameter data_width = 32;
192
   parameter addr_width = 8;
193 75 unneback
   parameter mem_size = 1<<addr_width;
194 5 unneback
   input [(data_width-1):0]      d_a;
195
   input [(addr_width-1):0]       adr_a;
196
   input [(addr_width-1):0]       adr_b;
197
   input                         we_a;
198
   output [(data_width-1):0]      q_b;
199
   input                         clk_a, clk_b;
200
   reg [(addr_width-1):0]         adr_b_reg;
201 98 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
202 7 unneback
 
203
   parameter init = 0;
204
   parameter memory_file = "vl_ram.vmem";
205
   generate if (init) begin : init_mem
206
   initial
207
     begin
208
        $readmemh(memory_file, ram);
209
     end
210
   end
211
   endgenerate
212
 
213 5 unneback
   always @ (posedge clk_a)
214
   if (we_a)
215
     ram[adr_a] <= d_a;
216
   always @ (posedge clk_b)
217
   adr_b_reg <= adr_b;
218
   assign q_b = ram[adr_b_reg];
219 40 unneback
 
220 5 unneback
endmodule
221 40 unneback
`endif
222 5 unneback
 
223 40 unneback
`ifdef DPRAM_2R1W
224
`define MODULE dpram_2r1w
225
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
226
`undef MODULE
227
 
228 5 unneback
   parameter data_width = 32;
229
   parameter addr_width = 8;
230 75 unneback
   parameter mem_size = 1<<addr_width;
231 5 unneback
   input [(data_width-1):0]      d_a;
232
   input [(addr_width-1):0]       adr_a;
233
   input [(addr_width-1):0]       adr_b;
234
   input                         we_a;
235
   output [(data_width-1):0]      q_b;
236
   output reg [(data_width-1):0] q_a;
237
   input                         clk_a, clk_b;
238
   reg [(data_width-1):0]         q_b;
239 98 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
240 7 unneback
 
241
   parameter init = 0;
242
   parameter memory_file = "vl_ram.vmem";
243
   generate if (init) begin : init_mem
244
   initial
245
     begin
246
        $readmemh(memory_file, ram);
247
     end
248
   end
249
   endgenerate
250
 
251 5 unneback
   always @ (posedge clk_a)
252
     begin
253
        q_a <= ram[adr_a];
254
        if (we_a)
255
             ram[adr_a] <= d_a;
256
     end
257
   always @ (posedge clk_b)
258
          q_b <= ram[adr_b];
259
endmodule
260 40 unneback
`endif
261 5 unneback
 
262 40 unneback
`ifdef DPRAM_2R2W
263
`define MODULE dpram_2r2w
264
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
265
`undef MODULE
266
 
267 5 unneback
   parameter data_width = 32;
268
   parameter addr_width = 8;
269 75 unneback
   parameter mem_size = 1<<addr_width;
270 5 unneback
   input [(data_width-1):0]      d_a;
271
   input [(addr_width-1):0]       adr_a;
272
   input [(addr_width-1):0]       adr_b;
273
   input                         we_a;
274
   output [(data_width-1):0]      q_b;
275
   input [(data_width-1):0]       d_b;
276
   output reg [(data_width-1):0] q_a;
277
   input                         we_b;
278
   input                         clk_a, clk_b;
279
   reg [(data_width-1):0]         q_b;
280 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
281 7 unneback
 
282
   parameter init = 0;
283
   parameter memory_file = "vl_ram.vmem";
284
   generate if (init) begin : init_mem
285
   initial
286
     begin
287
        $readmemh(memory_file, ram);
288
     end
289
   end
290
   endgenerate
291
 
292 5 unneback
   always @ (posedge clk_a)
293
     begin
294
        q_a <= ram[adr_a];
295
        if (we_a)
296
             ram[adr_a] <= d_a;
297
     end
298
   always @ (posedge clk_b)
299
     begin
300
        q_b <= ram[adr_b];
301
        if (we_b)
302
          ram[adr_b] <= d_b;
303
     end
304
endmodule
305 40 unneback
`endif
306 5 unneback
 
307 83 unneback
 
308 75 unneback
`ifdef DPRAM_BE_2R2W
309
`define MODULE dpram_be_2r2w
310 92 unneback
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
311 75 unneback
`undef MODULE
312
 
313
   parameter a_data_width = 32;
314
   parameter a_addr_width = 8;
315 95 unneback
   parameter b_data_width = 64; //a_data_width;
316 91 unneback
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
317 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
318
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
319 91 unneback
 
320 95 unneback
   parameter init = 0;
321
   parameter memory_file = "vl_ram.vmem";
322
 
323 75 unneback
   input [(a_data_width-1):0]      d_a;
324 91 unneback
   input [(a_addr_width-1):0]       adr_a;
325
   input [(a_data_width/8-1):0]    be_a;
326
   input                           we_a;
327 75 unneback
   output reg [(a_data_width-1):0] q_a;
328 91 unneback
   input [(b_data_width-1):0]       d_b;
329
   input [(b_addr_width-1):0]       adr_b;
330 92 unneback
   input [(b_data_width/8-1):0]    be_b;
331
   input                           we_b;
332
   output reg [(b_data_width-1):0]          q_b;
333 91 unneback
   input                           clk_a, clk_b;
334 75 unneback
 
335 91 unneback
//E2_ifdef SYSTEMVERILOG
336
// use a multi-dimensional packed array
337
//to model individual bytes within the word
338
 
339 75 unneback
generate
340 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
341 75 unneback
 
342 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
343 95 unneback
 
344
    initial
345
        if (init)
346
            $readmemh(memory_file, ram);
347 91 unneback
 
348
    always_ff@(posedge clk_a)
349
    begin
350
        if(we_a) begin
351
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
352
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
353
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
354
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
355
        end
356
    end
357
 
358 92 unneback
    always@(posedge clk_a)
359
        q_a = ram[adr_a];
360 91 unneback
 
361
    always_ff@(posedge clk_b)
362 92 unneback
    begin
363
        if(we_b) begin
364
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
365
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
366
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
367
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
368
        end
369
    end
370 91 unneback
 
371 92 unneback
    always@(posedge clk_b)
372
        q_b = ram[adr_b];
373 91 unneback
 
374 75 unneback
end
375
endgenerate
376
 
377 95 unneback
generate
378
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
379
 
380 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
381 95 unneback
 
382
    initial
383
        if (init)
384
            $readmemh(memory_file, ram);
385
 
386
    always_ff@(posedge clk_a)
387
    begin
388
        if(we_a) begin
389
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
390
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
391
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
392
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
393
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
394
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
395
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
396
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
397
        end
398
    end
399
 
400
    always@(posedge clk_a)
401
        q_a = ram[adr_a];
402
 
403
    always_ff@(posedge clk_b)
404
    begin
405
        if(we_b) begin
406
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
407
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
408
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
409
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
410
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
411
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
412
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
413
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
414
        end
415
    end
416
 
417
    always@(posedge clk_b)
418
        q_b = ram[adr_b];
419
 
420
end
421
endgenerate
422
 
423
generate
424
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
425
logic [31:0] temp;
426
`define MODULE dpram_be_2r2w
427
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
428
`undef MODULE
429
dpram6464 (
430
    .d_a(d_a),
431
    .q_a(q_a),
432
    .adr_a(adr_a),
433
    .be_a(be_a),
434
    .we_a(we_a),
435
    .clk_a(clk_a),
436
    .d_b({d_b,d_b}),
437
    .q_b(temp),
438
    .adr_b(adr_b),
439
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
440
    .we_b(we_b),
441
    .clk_b(clk_b)
442
);
443
 
444
always_comb
445
    if (adr_b[0])
446
        q_b = temp[31:16];
447
    else
448
        q_b = temp[15:0];
449
 
450
end
451
endgenerate
452
 
453
generate
454
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
455
logic [63:0] temp;
456
`define MODULE dpram_be_2r2w
457
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
458
`undef MODULE
459
dpram6464 (
460
    .d_a({d_a,d_a}),
461
    .q_a(temp),
462
    .adr_a(adr_a[a_addr_width-1:1]),
463
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
464
    .we_a(we_a),
465
    .clk_a(clk_a),
466
    .d_b(d_b),
467
    .q_b(q_b),
468
    .adr_b(adr_b),
469
    .be_b(be_b),
470
    .we_b(we_b),
471
    .clk_b(clk_b)
472
);
473
 
474
always_comb
475
    if (adr_a[0])
476
        q_a = temp[63:32];
477
    else
478
        q_a = temp[31:0];
479
 
480
end
481
endgenerate
482
 
483 91 unneback
//E2_else
484 92 unneback
    // This modules requires SystemVerilog
485 98 unneback
    // at this point anyway
486 91 unneback
//E2_endif
487 75 unneback
endmodule
488
`endif
489
 
490 91 unneback
`ifdef CAM
491 5 unneback
// Content addresable memory, CAM
492 91 unneback
`endif
493 5 unneback
 
494 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
495 5 unneback
// FIFO
496 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
497
module `BASE`MODULE (
498
`undef MODULE
499 25 unneback
    d, wr, fifo_full,
500
    q, rd, fifo_empty,
501
    fill_level,
502
    clk, rst
503
    );
504
 
505
parameter data_width = 18;
506
parameter addr_width = 4;
507 5 unneback
 
508 25 unneback
// write side
509
input  [data_width-1:0] d;
510
input                   wr;
511
output                  fifo_full;
512
// read side
513
output [data_width-1:0] q;
514
input                   rd;
515
output                  fifo_empty;
516
// common
517
output [addr_width:0]   fill_level;
518
input rst, clk;
519
 
520
wire [addr_width:1] wadr, radr;
521
 
522 40 unneback
`define MODULE cnt_bin_ce
523
`BASE`MODULE
524 25 unneback
    # ( .length(addr_width))
525
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
526 40 unneback
`BASE`MODULE
527 25 unneback
    # (.length(addr_width))
528
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
529 40 unneback
`undef MODULE
530 25 unneback
 
531 40 unneback
`define MODULE dpram_1r1w
532
`BASE`MODULE
533 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
534
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
535 40 unneback
`undef MODULE
536 25 unneback
 
537 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
538
`BASE`MODULE
539 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
540 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
541 40 unneback
`undef MODULE
542 25 unneback
endmodule
543 40 unneback
`endif
544 25 unneback
 
545 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
546 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
547
// RAM is supposed to be larger than the two FIFOs
548
// LFSR counters used adr pointers
549 40 unneback
`define MODULE fifo_2r2w_sync_simplex
550
module `BASE`MODULE (
551
`undef MODULE
552 27 unneback
    // a side
553
    a_d, a_wr, a_fifo_full,
554
    a_q, a_rd, a_fifo_empty,
555
    a_fill_level,
556
    // b side
557
    b_d, b_wr, b_fifo_full,
558
    b_q, b_rd, b_fifo_empty,
559
    b_fill_level,
560
    // common
561
    clk, rst
562
    );
563
parameter data_width = 8;
564
parameter addr_width = 5;
565
parameter fifo_full_level = (1<<addr_width)-1;
566
 
567
// a side
568
input  [data_width-1:0] a_d;
569
input                   a_wr;
570
output                  a_fifo_full;
571
output [data_width-1:0] a_q;
572
input                   a_rd;
573
output                  a_fifo_empty;
574
output [addr_width-1:0] a_fill_level;
575
 
576
// b side
577
input  [data_width-1:0] b_d;
578
input                   b_wr;
579
output                  b_fifo_full;
580
output [data_width-1:0] b_q;
581
input                   b_rd;
582
output                  b_fifo_empty;
583
output [addr_width-1:0] b_fill_level;
584
 
585
input                   clk;
586
input                   rst;
587
 
588
// adr_gen
589
wire [addr_width:1] a_wadr, a_radr;
590
wire [addr_width:1] b_wadr, b_radr;
591
// dpram
592
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
593
 
594 40 unneback
`define MODULE cnt_lfsr_ce
595
`BASE`MODULE
596 27 unneback
    # ( .length(addr_width))
597
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
598
 
599 40 unneback
`BASE`MODULE
600 27 unneback
    # (.length(addr_width))
601
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
602
 
603 40 unneback
`BASE`MODULE
604 27 unneback
    # ( .length(addr_width))
605
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
606
 
607 40 unneback
`BASE`MODULE
608 27 unneback
    # (.length(addr_width))
609
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
610 40 unneback
`undef MODULE
611 27 unneback
 
612
// mux read or write adr to DPRAM
613
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
614
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
615
 
616 40 unneback
`define MODULE dpram_2r2w
617
`BASE`MODULE
618 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
619
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
620
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
621 40 unneback
`undef MODULE
622
 
623
`define MODULE cnt_bin_ce_rew_zq_l1
624
`BASE`MODULE
625 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
626 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
627
 
628 40 unneback
`BASE`MODULE
629 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
630 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
631 40 unneback
`undef MODULE
632 27 unneback
 
633
endmodule
634 40 unneback
`endif
635 27 unneback
 
636 40 unneback
`ifdef FIFO_CMP_ASYNC
637
`define MODULE fifo_cmp_async
638
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
639
`undef MODULE
640 5 unneback
 
641 11 unneback
   parameter addr_width = 4;
642
   parameter N = addr_width-1;
643 5 unneback
 
644
   parameter Q1 = 2'b00;
645
   parameter Q2 = 2'b01;
646
   parameter Q3 = 2'b11;
647
   parameter Q4 = 2'b10;
648
 
649
   parameter going_empty = 1'b0;
650
   parameter going_full  = 1'b1;
651
 
652
   input [N:0]  wptr, rptr;
653 14 unneback
   output       fifo_empty;
654 5 unneback
   output       fifo_full;
655
   input        wclk, rclk, rst;
656
 
657
`ifndef GENERATE_DIRECTION_AS_LATCH
658
   wire direction;
659
`endif
660
`ifdef GENERATE_DIRECTION_AS_LATCH
661
   reg direction;
662
`endif
663
   reg  direction_set, direction_clr;
664
 
665
   wire async_empty, async_full;
666
   wire fifo_full2;
667 14 unneback
   wire fifo_empty2;
668 5 unneback
 
669
   // direction_set
670
   always @ (wptr[N:N-1] or rptr[N:N-1])
671
     case ({wptr[N:N-1],rptr[N:N-1]})
672
       {Q1,Q2} : direction_set <= 1'b1;
673
       {Q2,Q3} : direction_set <= 1'b1;
674
       {Q3,Q4} : direction_set <= 1'b1;
675
       {Q4,Q1} : direction_set <= 1'b1;
676
       default : direction_set <= 1'b0;
677
     endcase
678
 
679
   // direction_clear
680
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
681
     if (rst)
682
       direction_clr <= 1'b1;
683
     else
684
       case ({wptr[N:N-1],rptr[N:N-1]})
685
         {Q2,Q1} : direction_clr <= 1'b1;
686
         {Q3,Q2} : direction_clr <= 1'b1;
687
         {Q4,Q3} : direction_clr <= 1'b1;
688
         {Q1,Q4} : direction_clr <= 1'b1;
689
         default : direction_clr <= 1'b0;
690
       endcase
691
 
692 40 unneback
`define MODULE dff_sr
693 5 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
694 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
695 5 unneback
`endif
696
 
697
`ifdef GENERATE_DIRECTION_AS_LATCH
698
   always @ (posedge direction_set or posedge direction_clr)
699
     if (direction_clr)
700
       direction <= going_empty;
701
     else
702
       direction <= going_full;
703
`endif
704
 
705
   assign async_empty = (wptr == rptr) && (direction==going_empty);
706
   assign async_full  = (wptr == rptr) && (direction==going_full);
707
 
708 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
709
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
710
`undef MODULE
711 5 unneback
 
712
/*
713
   always @ (posedge wclk or posedge rst or posedge async_full)
714
     if (rst)
715
       {fifo_full, fifo_full2} <= 2'b00;
716
     else if (async_full)
717
       {fifo_full, fifo_full2} <= 2'b11;
718
     else
719
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
720
*/
721 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
722 5 unneback
     if (async_empty)
723
       {fifo_empty, fifo_empty2} <= 2'b11;
724
     else
725 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
726 40 unneback
`define MODULE dff
727
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
728
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
729
`undef MODULE
730 25 unneback
endmodule // async_compb
731 40 unneback
`endif
732 5 unneback
 
733 40 unneback
`ifdef FIFO_1R1W_ASYNC
734
`define MODULE fifo_1r1w_async
735
module `BASE`MODULE (
736
`undef MODULE
737 5 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
738
    q, rd, fifo_empty, rd_clk, rd_rst
739
    );
740
 
741
parameter data_width = 18;
742
parameter addr_width = 4;
743
 
744
// write side
745
input  [data_width-1:0] d;
746
input                   wr;
747
output                  fifo_full;
748
input                   wr_clk;
749
input                   wr_rst;
750
// read side
751
output [data_width-1:0] q;
752
input                   rd;
753
output                  fifo_empty;
754
input                   rd_clk;
755
input                   rd_rst;
756
 
757
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
758 23 unneback
 
759 40 unneback
`define MODULE cnt_gray_ce_bin
760
`BASE`MODULE
761 5 unneback
    # ( .length(addr_width))
762
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
763
 
764 40 unneback
`BASE`MODULE
765 5 unneback
    # (.length(addr_width))
766 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
767 40 unneback
`undef MODULE
768 5 unneback
 
769 40 unneback
`define MODULE dpram_1r1w
770
`BASE`MODULE
771 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
772
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
773 40 unneback
`undef MODULE
774 5 unneback
 
775 40 unneback
`define MODULE fifo_cmp_async
776
`BASE`MODULE
777 5 unneback
    # (.addr_width(addr_width))
778
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
779 40 unneback
`undef MODULE
780 5 unneback
 
781
endmodule
782 40 unneback
`endif
783 5 unneback
 
784 40 unneback
`ifdef FIFO_2R2W_ASYNC
785
`define MODULE fifo_2r2w_async
786
module `BASE`MODULE (
787
`undef MODULE
788 5 unneback
    // a side
789
    a_d, a_wr, a_fifo_full,
790
    a_q, a_rd, a_fifo_empty,
791
    a_clk, a_rst,
792
    // b side
793
    b_d, b_wr, b_fifo_full,
794
    b_q, b_rd, b_fifo_empty,
795
    b_clk, b_rst
796
    );
797
 
798
parameter data_width = 18;
799
parameter addr_width = 4;
800
 
801
// a side
802
input  [data_width-1:0] a_d;
803
input                   a_wr;
804
output                  a_fifo_full;
805
output [data_width-1:0] a_q;
806
input                   a_rd;
807
output                  a_fifo_empty;
808
input                   a_clk;
809
input                   a_rst;
810
 
811
// b side
812
input  [data_width-1:0] b_d;
813
input                   b_wr;
814
output                  b_fifo_full;
815
output [data_width-1:0] b_q;
816
input                   b_rd;
817
output                  b_fifo_empty;
818
input                   b_clk;
819
input                   b_rst;
820
 
821 40 unneback
`define MODULE fifo_1r1w_async
822
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
823 5 unneback
vl_fifo_1r1w_async_a (
824
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
825
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
826
    );
827
 
828 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
829 5 unneback
vl_fifo_1r1w_async_b (
830
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
831
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
832
    );
833 40 unneback
`undef MODULE
834
 
835 5 unneback
endmodule
836 40 unneback
`endif
837 5 unneback
 
838 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
839
`define MODULE fifo_2r2w_async_simplex
840
module `BASE`MODULE (
841
`undef MODULE
842 5 unneback
    // a side
843
    a_d, a_wr, a_fifo_full,
844
    a_q, a_rd, a_fifo_empty,
845
    a_clk, a_rst,
846
    // b side
847
    b_d, b_wr, b_fifo_full,
848
    b_q, b_rd, b_fifo_empty,
849
    b_clk, b_rst
850
    );
851
 
852
parameter data_width = 18;
853
parameter addr_width = 4;
854
 
855
// a side
856
input  [data_width-1:0] a_d;
857
input                   a_wr;
858
output                  a_fifo_full;
859
output [data_width-1:0] a_q;
860
input                   a_rd;
861
output                  a_fifo_empty;
862
input                   a_clk;
863
input                   a_rst;
864
 
865
// b side
866
input  [data_width-1:0] b_d;
867
input                   b_wr;
868
output                  b_fifo_full;
869
output [data_width-1:0] b_q;
870
input                   b_rd;
871
output                  b_fifo_empty;
872
input                   b_clk;
873
input                   b_rst;
874
 
875
// adr_gen
876
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
877
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
878
// dpram
879
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
880
 
881 40 unneback
`define MODULE cnt_gray_ce_bin
882
`BASE`MODULE
883 5 unneback
    # ( .length(addr_width))
884
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
885
 
886 40 unneback
`BASE`MODULE
887 5 unneback
    # (.length(addr_width))
888
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
889
 
890 40 unneback
`BASE`MODULE
891 5 unneback
    # ( .length(addr_width))
892
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
893
 
894 40 unneback
`BASE`MODULE
895 5 unneback
    # (.length(addr_width))
896
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
897 40 unneback
`undef MODULE
898 5 unneback
 
899
// mux read or write adr to DPRAM
900
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
901
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
902
 
903 40 unneback
`define MODULE dpram_2r2w
904
`BASE`MODULE
905 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
906
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
907
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
908 40 unneback
`undef MODULE
909 5 unneback
 
910 40 unneback
`define MODULE fifo_cmp_async
911
`BASE`MODULE
912 5 unneback
    # (.addr_width(addr_width))
913
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
914
 
915 40 unneback
`BASE`MODULE
916 5 unneback
    # (.addr_width(addr_width))
917
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
918 40 unneback
`undef MODULE
919 5 unneback
 
920
endmodule
921 40 unneback
`endif
922 48 unneback
 
923
`ifdef REG_FILE
924
`define MODULE reg_file
925
module `BASE`MODULE (
926
`undef MODULE
927
    a1, a2, a3, wd3, we3, rd1, rd2, clk
928
);
929
parameter data_width = 32;
930
parameter addr_width = 5;
931
input [addr_width-1:0] a1, a2, a3;
932
input [data_width-1:0] wd3;
933
input we3;
934
output [data_width-1:0] rd1, rd2;
935
input clk;
936
 
937
`ifdef ACTEL
938
reg [data_width-1:0] wd3_reg;
939
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
940
reg we3_reg;
941 98 unneback
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
942
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
943 48 unneback
always @ (posedge clk or posedge rst)
944
if (rst)
945
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
946
else
947
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
948
 
949
    always @ (negedge clk)
950
    if (we3_reg)
951
        ram1[a3_reg] <= wd3;
952
    always @ (posedge clk)
953
        a1_reg <= a1;
954
    assign rd1 = ram1[a1_reg];
955
 
956
    always @ (negedge clk)
957
    if (we3_reg)
958
        ram2[a3_reg] <= wd3;
959
    always @ (posedge clk)
960
        a2_reg <= a2;
961
    assign rd2 = ram2[a2_reg];
962
 
963
`else
964
 
965
`define MODULE dpram_1r1w
966
`BASE`MODULE
967
    # ( .data_width(data_width), .addr_width(addr_width))
968
    ram1 (
969
        .d_a(wd3),
970
        .adr_a(a3),
971
        .we_a(we3),
972
        .clk_a(clk),
973
        .q_b(rd1),
974
        .adr_b(a1),
975
        .clk_b(clk) );
976
 
977
`BASE`MODULE
978
    # ( .data_width(data_width), .addr_width(addr_width))
979
    ram2 (
980
        .d_a(wd3),
981
        .adr_a(a3),
982
        .we_a(we3),
983
        .clk_a(clk),
984
        .q_b(rd2),
985
        .adr_b(a2),
986
        .clk_b(clk) );
987
`undef MODULE
988
 
989
`endif
990
 
991
endmodule
992
`endif

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