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1 3 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, registers                                ////
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////                                                              ////
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////  Description                                                 ////
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////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module dff ( d, q, clk, rst);
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        parameter width = 1;
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        parameter reset_value = 0;
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        input [width-1:0] d;
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        input clk, rst;
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        output reg [width-1:0] q;
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        always @ (posedge clk or posedge rst)
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        if (rst)
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                q <= reset_value;
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        else
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                q <= d;
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endmodule
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60 5 unneback
module dff_array ( d, q, clk, rst);
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        parameter width = 1;
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        parameter depth = 2;
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        parameter reset_value = 1'b0;
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        input [width-1:0] d;
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        input clk, rst;
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        output [width-1:0] q;
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        reg  [0:depth-1] q_tmp [width-1:0];
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        integer i;
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        always @ (posedge clk or posedge rst)
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        if (rst) begin
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            for (i=0;i<depth;i=i+1)
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                q_tmp[i] <= {width{reset_value}};
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        end else begin
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            q_tmp[0] <= d;
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            for (i=1;i<depth;i=i+1)
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                q_tmp[i] <= q_tmp[i-1];
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        end
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    assign q = q_tmp[depth-1];
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endmodule
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85 3 unneback
module dff_ce ( d, ce, q, clk, rst);
86
 
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        parameter width = 1;
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        parameter reset_value = 0;
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90
        input [width-1:0] d;
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        input ce, clk, rst;
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        output reg [width-1:0] q;
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        always @ (posedge clk or posedge rst)
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        if (rst)
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                q <= reset_value;
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        else
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                if (ce)
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                        q <= d;
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101
endmodule
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103 8 unneback
module dff_ce_clear ( d, ce, clear, q, clk, rst);
104
 
105
        parameter width = 1;
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        parameter reset_value = 0;
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        input [width-1:0] d;
109 10 unneback
        input ce, clear, clk, rst;
110 8 unneback
        output reg [width-1:0] q;
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112
        always @ (posedge clk or posedge rst)
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        if (rst)
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            q <= reset_value;
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        else
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            if (ce)
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                if (clear)
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                    q <= {width{1'b0}};
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                else
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                    q <= d;
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endmodule
123
 
124 3 unneback
`ifdef ALTERA
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// megafunction wizard: %LPM_FF%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: lpm_ff 
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// ============================================================
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// File Name: dff_sr.v
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// Megafunction Name(s):
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//                      lpm_ff
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//
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// Simulation Library Files(s):
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//                      lpm
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2010 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions 
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//and other software and tools, and its AMPP partner logic 
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//functions, and any output files from any of the foregoing 
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//(including device programming or simulation files), and any 
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//associated documentation or information are expressly subject 
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//to the terms and conditions of the Altera Program License 
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//Subscription Agreement, Altera MegaCore Function License 
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//Agreement, or other applicable license agreement, including, 
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//without limitation, that your use is for the sole purpose of 
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//programming logic devices manufactured by Altera and sold by 
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//Altera or its authorized distributors.  Please refer to the 
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//applicable agreement for further details.
158
 
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module dff_sr (
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        aclr,
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        aset,
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        clock,
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        data,
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        q);
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        input     aclr;
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        input     aset;
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        input     clock;
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        input     data;
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        output    q;
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        wire [0:0] sub_wire0;
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        wire [0:0] sub_wire1 = sub_wire0[0:0];
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        wire  q = sub_wire1;
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        wire  sub_wire2 = data;
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        wire  sub_wire3 = sub_wire2;
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        lpm_ff  lpm_ff_component (
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                                .aclr (aclr),
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                                .clock (clock),
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                                .data (sub_wire3),
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                                .aset (aset),
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                                .q (sub_wire0)
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                                // synopsys translate_off
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                                ,
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                                .aload (),
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                                .enable (),
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                                .sclr (),
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                                .sload (),
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                                .sset ()
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                                // synopsys translate_on
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                                );
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        defparam
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                lpm_ff_component.lpm_fftype = "DFF",
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                lpm_ff_component.lpm_type = "LPM_FF",
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                lpm_ff_component.lpm_width = 1;
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203
endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ACLR NUMERIC "1"
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// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
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// Retrieval info: PRIVATE: ASET NUMERIC "1"
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// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
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// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
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// Retrieval info: PRIVATE: DFF NUMERIC "1"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: SCLR NUMERIC "0"
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// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
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// Retrieval info: PRIVATE: SSET NUMERIC "0"
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// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
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// Retrieval info: PRIVATE: nBit NUMERIC "1"
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// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
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// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
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// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
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// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
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// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
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// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
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// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
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// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
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// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
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// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
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// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
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// Retrieval info: LIB_FILE: lpm
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245
`else
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module dff_sr ( aclr, aset, clock, data, q);
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250
    input         aclr;
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    input         aset;
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    input         clock;
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    input         data;
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    output reg    q;
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256
   always @ (posedge clock or posedge aclr or posedge aset)
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     if (aclr)
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       q <= 1'b0;
259
     else if (aset)
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       q <= 1'b1;
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     else
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       q <= data;
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264
endmodule
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266
`endif
267 5 unneback
 
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// LATCH
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// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
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`ifdef ALTERA
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module latch ( d, le, q, clk);
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input d, le;
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output q;
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input clk;
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dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
276
endmodule
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`else
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module latch ( d, le, q, clk);
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input d, le;
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output q;
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input clk;/*
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   always @ (posedge direction_set or posedge direction_clr)
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     if (direction_clr)
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       direction <= going_empty;
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     else
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       direction <= going_full;*/
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endmodule
288 15 unneback
`endif
289
 
290
module delay ( d, q, clk, rst);
291
parameter depth = 10;
292
input d;
293
output q;
294
input clk, rst;
295
 
296
reg [1:depth] dffs;
297
 
298
always @ (posedge clk or posedge rst)
299
if (rst)
300
    dffs <= {depth{1'b0}};
301
else
302
    dffs <= {d,dffs[1:depth-1]};
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assign q = dffs[depth];
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endmodule

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