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1 3 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, registers                                ////
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////                                                              ////
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////  Description                                                 ////
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////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef DFF
44
`define MODULE dff
45
module `BASE`MODULE ( d, q, clk, rst);
46
`undef MODULE
47 3 unneback
        parameter width = 1;
48
        parameter reset_value = 0;
49
 
50
        input [width-1:0] d;
51
        input clk, rst;
52
        output reg [width-1:0] q;
53
 
54
        always @ (posedge clk or posedge rst)
55
        if (rst)
56
                q <= reset_value;
57
        else
58
                q <= d;
59
 
60
endmodule
61 40 unneback
`endif
62 3 unneback
 
63 40 unneback
`ifdef DFF_ARRAY
64
`define MODULE dff_array
65
module `BASE`MODULE ( d, q, clk, rst);
66
`undef MODULE
67 5 unneback
 
68
        parameter width = 1;
69
        parameter depth = 2;
70
        parameter reset_value = 1'b0;
71
 
72
        input [width-1:0] d;
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        input clk, rst;
74
        output [width-1:0] q;
75
        reg  [0:depth-1] q_tmp [width-1:0];
76
        integer i;
77
        always @ (posedge clk or posedge rst)
78
        if (rst) begin
79
            for (i=0;i<depth;i=i+1)
80
                q_tmp[i] <= {width{reset_value}};
81
        end else begin
82
            q_tmp[0] <= d;
83
            for (i=1;i<depth;i=i+1)
84
                q_tmp[i] <= q_tmp[i-1];
85
        end
86
 
87
    assign q = q_tmp[depth-1];
88
 
89
endmodule
90 40 unneback
`endif
91 5 unneback
 
92 40 unneback
`ifdef DFF_CE
93
`define MODULE dff_ce
94
module `BASE`MODULE ( d, ce, q, clk, rst);
95
`undef MODULE
96 3 unneback
 
97
        parameter width = 1;
98
        parameter reset_value = 0;
99
 
100
        input [width-1:0] d;
101
        input ce, clk, rst;
102
        output reg [width-1:0] q;
103
 
104
        always @ (posedge clk or posedge rst)
105
        if (rst)
106
                q <= reset_value;
107
        else
108
                if (ce)
109
                        q <= d;
110
 
111
endmodule
112 40 unneback
`endif
113 3 unneback
 
114 40 unneback
`ifdef DFF_CE_CLEAR
115
`define MODULE dff_ce_clear
116
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
117
`undef MODULE
118 8 unneback
 
119
        parameter width = 1;
120
        parameter reset_value = 0;
121
 
122
        input [width-1:0] d;
123 10 unneback
        input ce, clear, clk, rst;
124 8 unneback
        output reg [width-1:0] q;
125
 
126
        always @ (posedge clk or posedge rst)
127
        if (rst)
128
            q <= reset_value;
129
        else
130
            if (ce)
131
                if (clear)
132
                    q <= {width{1'b0}};
133
                else
134
                    q <= d;
135
 
136
endmodule
137 40 unneback
`endif
138 8 unneback
 
139 40 unneback
`ifdef DF_CE_SET
140
`define MODULE dff_ce_set
141
module `BASE`MODULE ( d, ce, set, q, clk, rst);
142
`undef MODULE
143 24 unneback
 
144
        parameter width = 1;
145
        parameter reset_value = 0;
146
 
147
        input [width-1:0] d;
148
        input ce, set, clk, rst;
149
        output reg [width-1:0] q;
150
 
151
        always @ (posedge clk or posedge rst)
152
        if (rst)
153
            q <= reset_value;
154
        else
155
            if (ce)
156
                if (set)
157
                    q <= {width{1'b1}};
158
                else
159
                    q <= d;
160
 
161
endmodule
162 40 unneback
`endif
163 24 unneback
 
164 40 unneback
`ifdef SPR
165
`define MODULE spr
166
module `BASE`MODULE ( sp, r, q, clk, rst);
167
`undef MODULE
168
 
169 29 unneback
        parameter width = 1;
170
        parameter reset_value = 0;
171
 
172
        input sp, r;
173
        output reg q;
174
        input clk, rst;
175
 
176
        always @ (posedge clk or posedge rst)
177
        if (rst)
178
            q <= reset_value;
179
        else
180
            if (sp)
181
                q <= 1'b1;
182
            else if (r)
183
                q <= 1'b0;
184
 
185
endmodule
186 40 unneback
`endif
187 29 unneback
 
188 40 unneback
`ifdef SRP
189
`define MODULE srp
190
module `BASE`MODULE ( s, rp, q, clk, rst);
191
`undef MODULE
192
 
193 29 unneback
        parameter width = 1;
194
        parameter reset_value = 0;
195
 
196
        input s, rp;
197
        output reg q;
198
        input clk, rst;
199
 
200
        always @ (posedge clk or posedge rst)
201
        if (rst)
202
            q <= reset_value;
203
        else
204
            if (rp)
205
                q <= 1'b0;
206
            else if (s)
207
                q <= 1'b1;
208
 
209
endmodule
210 40 unneback
`endif
211 29 unneback
 
212 40 unneback
`ifdef ALTERA
213 29 unneback
 
214 40 unneback
`ifdef DFF_SR
215 3 unneback
// megafunction wizard: %LPM_FF%
216
// GENERATION: STANDARD
217
// VERSION: WM1.0
218
// MODULE: lpm_ff 
219
 
220
// ============================================================
221
// File Name: dff_sr.v
222
// Megafunction Name(s):
223
//                      lpm_ff
224
//
225
// Simulation Library Files(s):
226
//                      lpm
227
// ============================================================
228
// ************************************************************
229
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
230
//
231
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
232
// ************************************************************
233
 
234
 
235
//Copyright (C) 1991-2010 Altera Corporation
236
//Your use of Altera Corporation's design tools, logic functions 
237
//and other software and tools, and its AMPP partner logic 
238
//functions, and any output files from any of the foregoing 
239
//(including device programming or simulation files), and any 
240
//associated documentation or information are expressly subject 
241
//to the terms and conditions of the Altera Program License 
242
//Subscription Agreement, Altera MegaCore Function License 
243
//Agreement, or other applicable license agreement, including, 
244
//without limitation, that your use is for the sole purpose of 
245
//programming logic devices manufactured by Altera and sold by 
246
//Altera or its authorized distributors.  Please refer to the 
247
//applicable agreement for further details.
248
 
249
 
250
// synopsys translate_off
251
`timescale 1 ps / 1 ps
252
// synopsys translate_on
253 40 unneback
`define MODULE dff_sr
254
module `BASE`MODULE (
255
`undef MODULE
256
 
257 3 unneback
        aclr,
258
        aset,
259
        clock,
260
        data,
261
        q);
262
 
263
        input     aclr;
264
        input     aset;
265
        input     clock;
266
        input     data;
267
        output    q;
268
 
269
        wire [0:0] sub_wire0;
270
        wire [0:0] sub_wire1 = sub_wire0[0:0];
271
        wire  q = sub_wire1;
272
        wire  sub_wire2 = data;
273
        wire  sub_wire3 = sub_wire2;
274
 
275
        lpm_ff  lpm_ff_component (
276
                                .aclr (aclr),
277
                                .clock (clock),
278
                                .data (sub_wire3),
279
                                .aset (aset),
280
                                .q (sub_wire0)
281
                                // synopsys translate_off
282
                                ,
283
                                .aload (),
284
                                .enable (),
285
                                .sclr (),
286
                                .sload (),
287
                                .sset ()
288
                                // synopsys translate_on
289
                                );
290
        defparam
291
                lpm_ff_component.lpm_fftype = "DFF",
292
                lpm_ff_component.lpm_type = "LPM_FF",
293
                lpm_ff_component.lpm_width = 1;
294
 
295
 
296
endmodule
297
 
298
// ============================================================
299
// CNX file retrieval info
300
// ============================================================
301
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
302
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
303
// Retrieval info: PRIVATE: ASET NUMERIC "1"
304
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
305
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
306
// Retrieval info: PRIVATE: DFF NUMERIC "1"
307
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
308
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
309
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
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// Retrieval info: PRIVATE: SSET NUMERIC "0"
311
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
312
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
313
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
314
// Retrieval info: PRIVATE: nBit NUMERIC "1"
315
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
316
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
317
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
318
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
319
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
320
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
321
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
322
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
323
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
324
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
325
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
326
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
327
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
328
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
329
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
330
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
331
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
332
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
333
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
334
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
335
// Retrieval info: LIB_FILE: lpm
336 40 unneback
`endif
337 3 unneback
 
338
`else
339
 
340 40 unneback
`ifdef DFF_SR
341
`define MODULE dff_sr
342
module `BASE`MODULE ( aclr, aset, clock, data, q);
343
`undef MODULE
344 3 unneback
 
345
    input         aclr;
346
    input         aset;
347
    input         clock;
348
    input         data;
349
    output reg    q;
350
 
351
   always @ (posedge clock or posedge aclr or posedge aset)
352
     if (aclr)
353
       q <= 1'b0;
354
     else if (aset)
355
       q <= 1'b1;
356
     else
357
       q <= data;
358
 
359
endmodule
360 40 unneback
`endif
361 3 unneback
 
362
`endif
363 5 unneback
 
364
// LATCH
365
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
366
`ifdef ALTERA
367 40 unneback
 
368
`ifdef LATCH
369
`define MODULE latch
370
module `BASE`MODULE ( d, le, q, clk);
371
`undef MODULE
372 5 unneback
input d, le;
373
output q;
374
input clk;
375
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
376
endmodule
377 40 unneback
`endif
378
 
379 5 unneback
`else
380 40 unneback
 
381
`ifdef LATCH
382
`define MODULE latch
383
module `BASE`MODULE ( d, le, q, clk);
384
`undef MODULE
385 5 unneback
input d, le;
386 48 unneback
input clk;
387
always @ (le or d)
388
if le
389
    d <= q;
390 5 unneback
endmodule
391 15 unneback
`endif
392
 
393 40 unneback
`endif
394
 
395
`ifdef SHREG
396
`define MODULE shreg
397
module `BASE`MODULE ( d, q, clk, rst);
398
`undef MODULE
399
 
400 17 unneback
parameter depth = 10;
401
input d;
402
output q;
403
input clk, rst;
404
 
405
reg [1:depth] dffs;
406
 
407
always @ (posedge clk or posedge rst)
408
if (rst)
409
    dffs <= {depth{1'b0}};
410
else
411
    dffs <= {d,dffs[1:depth-1]};
412
assign q = dffs[depth];
413
endmodule
414 40 unneback
`endif
415 17 unneback
 
416 40 unneback
`ifdef SHREG_CE
417
`define MODULE shreg_ce
418
module `BASE`MODULE ( d, ce, q, clk, rst);
419
`undef MODULE
420 17 unneback
parameter depth = 10;
421
input d, ce;
422
output q;
423
input clk, rst;
424
 
425
reg [1:depth] dffs;
426
 
427
always @ (posedge clk or posedge rst)
428
if (rst)
429
    dffs <= {depth{1'b0}};
430
else
431
    if (ce)
432
        dffs <= {d,dffs[1:depth-1]};
433
assign q = dffs[depth];
434
endmodule
435 40 unneback
`endif
436 17 unneback
 
437 40 unneback
`ifdef DELAY
438
`define MODULE delay
439
module `BASE`MODULE ( d, q, clk, rst);
440
`undef MODULE
441 15 unneback
parameter depth = 10;
442
input d;
443
output q;
444
input clk, rst;
445
 
446
reg [1:depth] dffs;
447
 
448
always @ (posedge clk or posedge rst)
449
if (rst)
450
    dffs <= {depth{1'b0}};
451
else
452
    dffs <= {d,dffs[1:depth-1]};
453
assign q = dffs[depth];
454 17 unneback
endmodule
455 40 unneback
`endif
456 17 unneback
 
457 40 unneback
`ifdef DELAY_EMPTYFLAG
458
`define MODULE delay_emptyflag
459 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
460 40 unneback
`undef MODULE
461 17 unneback
parameter depth = 10;
462
input d;
463
output q, emptyflag;
464
input clk, rst;
465
 
466
reg [1:depth] dffs;
467
 
468
always @ (posedge clk or posedge rst)
469
if (rst)
470
    dffs <= {depth{1'b0}};
471
else
472
    dffs <= {d,dffs[1:depth-1]};
473
assign q = dffs[depth];
474
assign emptyflag = !(|dffs);
475
endmodule
476 40 unneback
`endif

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