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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 101

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 98 unneback 
`ifdef ACTEL
14 
    // ACTEL FPGA should not use logic to handle rw collision
15 
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16 
`else
17 
    `define SYN_NO_RW_CHECK
18 
`endif
19 
 
20 40 unneback 
`ifdef ALL
21 
 
22 
`define GBUF
23 
`define SYNC_RST
24 
`define PLL
25 
 
26 
`define MULTS
27 
`define MULTS18X18
28 
`define MULT
29 
`define SHIFT_UNIT_32
30 
`define LOGIC_UNIT
31 
 
32 
`define CNT_SHREG_WRAP
33 
`define CNT_SHREG_CE_WRAP
34 
`define CNT_SHREG_CE_CLEAR
35 
`define CNT_SHREG_CE_CLEAR_WRAP
36 
 
37 
`define MUX_ANDOR
38 
`define MUX2_ANDOR
39 
`define MUX3_ANDOR
40 
`define MUX4_ANDOR
41 
`define MUX5_ANDOR
42 
`define MUX6_ANDOR
43 43 unneback 
`define PARITY
44 40 unneback 
 
45 
`define ROM_INIT
46 
`define RAM
47 
`define RAM_BE
48 
`define DPRAM_1R1W
49 
`define DPRAM_2R1W
50 100 unneback 
`define DPRAM_1R2W
51 40 unneback 
`define DPRAM_2R2W
52 75 unneback 
`define DPRAM_BE_2R2W
53 40 unneback 
`define FIFO_1R1W_FILL_LEVEL_SYNC
54 
`define FIFO_2R2W_SYNC_SIMPLEX
55 
`define FIFO_CMP_ASYNC
56 
`define FIFO_1R1W_ASYNC
57 
`define FIFO_2R2W_ASYNC
58 
`define FIFO_2R2W_ASYNC_SIMPLEX
59 48 unneback 
`define REG_FILE
60 40 unneback 
 
61 
`define DFF
62 
`define DFF_ARRAY
63 
`define DFF_CE
64 
`define DFF_CE_CLEAR
65 
`define DF_CE_SET
66 
`define SPR
67 
`define SRP
68 
`define DFF_SR
69 
`define LATCH
70 
`define SHREG
71 
`define SHREG_CE
72 
`define DELAY
73 
`define DELAY_EMPTYFLAG
74 94 unneback 
`define PULSE2TOGGLE
75 
`define TOGGLE2PULSE
76 
`define SYNCHRONIZER
77 
`define CDC
78 40 unneback 
 
79 75 unneback 
`define WB3AVALON_BRIDGE
80 40 unneback 
`define WB3WB3_BRIDGE
81 
`define WB3_ARBITER_TYPE1
82 83 unneback 
`define WB_ADR_INC
83 101 unneback 
`define WB_RAM
84 48 unneback 
`define WB_B4_ROM
85 40 unneback 
`define WB_BOOT_ROM
86 
`define WB_DPRAM
87 101 unneback 
`define WB_CACHE
88 40 unneback 
 
89 44 unneback 
`define IO_DFF_OE
90 
`define O_DFF
91 
 
92 40 unneback 
`endif
93 
 
94 
`ifdef PLL
95 
`ifndef SYNC_RST
96 
`define SYNC_RST
97 
`endif
98 
`endif
99 
 
100 
`ifdef SYNC_RST
101 
`ifndef GBUF
102 
`define GBUF
103 
`endif
104 
`endif
105 
 
106 92 unneback 
`ifdef WB_B3_DPRAM
107 
`ifndef WB_ADR_INC
108 
`define WB_ADR_INC
109 40 unneback 
`endif
110 92 unneback 
`ifndef DPRAM_BE_2R2W
111 
`define DPRAM_BE_2R2W
112 40 unneback 
`endif
113 
`endif
114 
 
115 101 unneback 
`ifdef WB_RAM
116 83 unneback 
`ifndef WB_ADR_INC
117 
`define WB_ADR_INC
118 62 unneback 
`endif
119 
`ifndef RAM_BE
120 
`define RAM_BE
121 
`endif
122 
`endif
123 
 
124 40 unneback 
`ifdef WB3_ARBITER_TYPE1
125 42 unneback 
`ifndef SPR
126 
`define SPR
127 
`endif
128 40 unneback 
`ifndef MUX_ANDOR
129 
`define MUX_ANDOR
130 
`endif
131 
`endif
132 
 
133 76 unneback 
`ifdef WB3AVALON_BRIDGE
134 
`ifndef WB3WB3_BRIDGE
135 
`define WB3WB3_BRIDGE
136 
`endif
137 
`endif
138 
 
139 40 unneback 
`ifdef WB3WB3_BRIDGE
140 
`ifndef CNT_SHREG_CE_CLEAR
141 
`define CNT_SHREG_CE_CLEAR
142 
`endif
143 
`ifndef DFF
144 
`define DFF
145 
`endif
146 
`ifndef DFF_CE
147 
`define DFF_CE
148 
`endif
149 
`ifndef CNT_SHREG_CE_CLEAR
150 
`define CNT_SHREG_CE_CLEAR
151 
`endif
152 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
153 
`define FIFO_2R2W_ASYNC_SIMPLEX
154 
`endif
155 
`endif
156 
 
157 101 unneback 
`ifdef WB_CACHE
158 100 unneback 
`ifndef RAM
159 
`define RAM
160 
`endif
161 
`ifndef WB_ADR_INC
162 
`define WB_ADR_INC
163 
`endif
164 
`ifndef DPRAM_1R1W
165 
`define DPRAM_1R1W
166 
`endif
167 
`ifndef DPRAM_1R2W
168 
`define DPRAM_1R2W
169 
`endif
170 
`ifndef DPRAM_BE_2R2W
171 
`define DPRAM_BE_2R2W
172 
`endif
173 
`ifndef CDC
174 
`define CDC
175 
`endif
176 
`endif
177 97 unneback 
 
178 40 unneback 
`ifdef MULTS18X18
179 
`ifndef MULTS
180 
`define MULTS
181 
`endif
182 
`endif
183 
 
184 
`ifdef SHIFT_UNIT_32
185 
`ifndef MULTS
186 
`define MULTS
187 
`endif
188 
`endif
189 
 
190 
`ifdef MUX2_ANDOR
191 
`ifndef MUX_ANDOR
192 
`define MUX_ANDOR
193 
`endif
194 
`endif
195 
 
196 
`ifdef MUX3_ANDOR
197 
`ifndef MUX_ANDOR
198 
`define MUX_ANDOR
199 
`endif
200 
`endif
201 
 
202 
`ifdef MUX4_ANDOR
203 
`ifndef MUX_ANDOR
204 
`define MUX_ANDOR
205 
`endif
206 
`endif
207 
 
208 
`ifdef MUX5_ANDOR
209 
`ifndef MUX_ANDOR
210 
`define MUX_ANDOR
211 
`endif
212 
`endif
213 
 
214 
`ifdef MUX6_ANDOR
215 
`ifndef MUX_ANDOR
216 
`define MUX_ANDOR
217 
`endif
218 
`endif
219 
 
220 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
221 
`ifndef CNT_BIN_CE
222 
`define CNT_BIN_CE
223 
`endif
224 
`ifndef DPRAM_1R1W
225 
`define DPRAM_1R1W
226 
`endif
227 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
228 
`define CNT_BIN_CE_REW_Q_ZQ_L1
229 
`endif
230 
`endif
231 
 
232 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
233 
`ifndef CNT_LFSR_CE
234 
`define CNT_LFSR_CE
235 
`endif
236 
`ifndef DPRAM_2R2W
237 
`define DPRAM_2R2W
238 
`endif
239 
`ifndef CNT_BIN_CE_REW_ZQ_L1
240 
`define CNT_BIN_CE_REW_ZQ_L1
241 
`endif
242 
`endif
243 
 
244 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
245 
`ifndef CNT_GRAY_CE_BIN
246 
`define CNT_GRAY_CE_BIN
247 
`endif
248 
`ifndef DPRAM_2R2W
249 
`define DPRAM_2R2W
250 
`endif
251 
`ifndef FIFO_CMP_ASYNC
252 
`define FIFO_CMP_ASYNC
253 
`endif
254 
`endif
255 
 
256 
`ifdef FIFO_2R2W_ASYNC
257 
`ifndef FIFO_1R1W_ASYNC
258 
`define FIFO_1R1W_ASYNC
259 
`endif
260 
`endif
261 
 
262 
`ifdef FIFO_1R1W_ASYNC
263 
`ifndef CNT_GRAY_CE_BIN
264 
`define CNT_GRAY_CE_BIN
265 
`endif
266 
`ifndef DPRAM_1R1W
267 
`define DPRAM_1R1W
268 
`endif
269 
`ifndef FIFO_CMP_ASYNC
270 
`define FIFO_CMP_ASYNC
271 
`endif
272 
`endif
273 
 
274 
`ifdef FIFO_CMP_ASYNC
275 
`ifndef DFF_SR
276 
`define DFF_SR
277 
`endif
278 
`ifndef DFF
279 
`define DFF
280 
`endif
281 
`endif
282 48 unneback 
 
283 
`ifdef REG_FILE
284 
`ifndef DPRAM_1R1W
285 
`define DPRAM_1R1W
286 
`endif
287 
`endif
288 97 unneback 
 
289 98 unneback 
`ifdef CDC
290 
`ifndef PULSE2TOGGLE
291 
`define PULSE2TOGGLE
292 
`endif
293 
`ifndef TOGGLE2PULSE
294 
`define TOGGLE2PULSE
295 
`endif
296 
`ifndef SYNCHRONIZER
297 
`define SYNCHRONIZER
298 
`endif
299 
`endif
300 
 
301 97 unneback 
// size to width
302 100 unneback 
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
303 62 unneback 
//////////////////////////////////////////////////////////////////////
304 6 unneback 
////                                                              ////
305 
////  Versatile library, clock and reset                          ////
306 
////                                                              ////
307 
////  Description                                                 ////
308 
////  Logic related to clock and reset                            ////
309 
////                                                              ////
310 
////                                                              ////
311 
////  To Do:                                                      ////
312 
////   - add more different registers                             ////
313 
////                                                              ////
314 
////  Author(s):                                                  ////
315 
////      - Michael Unneback, unneback@opencores.org              ////
316 
////        ORSoC AB                                              ////
317 
////                                                              ////
318 
//////////////////////////////////////////////////////////////////////
319 
////                                                              ////
320 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
321 
////                                                              ////
322 
//// This source file may be used and distributed without         ////
323 
//// restriction provided that this copyright statement is not    ////
324 
//// removed from the file and that any derivative work contains  ////
325 
//// the original copyright notice and the associated disclaimer. ////
326 
////                                                              ////
327 
//// This source file is free software; you can redistribute it   ////
328 
//// and/or modify it under the terms of the GNU Lesser General   ////
329 
//// Public License as published by the Free Software Foundation; ////
330 
//// either version 2.1 of the License, or (at your option) any   ////
331 
//// later version.                                               ////
332 
////                                                              ////
333 
//// This source is distributed in the hope that it will be       ////
334 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
335 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
336 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
337 
//// details.                                                     ////
338 
////                                                              ////
339 
//// You should have received a copy of the GNU Lesser General    ////
340 
//// Public License along with this source; if not, download it   ////
341 
//// from http://www.opencores.org/lgpl.shtml                     ////
342 
////                                                              ////
343 
//////////////////////////////////////////////////////////////////////
344 
 
345 48 unneback 
`ifdef ACTEL
346 
`ifdef GBUF
347 
`timescale 1 ns/100 ps
348 6 unneback 
// Global buffer
349 
// usage:
350 
// use to enable global buffers for high fan out signals such as clock and reset
351 
// Version: 8.4 8.4.0.33
352 
module gbuf(GL,CLK);
353 
output GL;
354 
input  CLK;
355 
 
356 
    wire GND;
357 
 
358 
    GND GND_1_net(.Y(GND));
359 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
360 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
361 
 
362 
endmodule
363 
`timescale 1 ns/1 ns
364 40 unneback 
`define MODULE gbuf
365 
module `BASE`MODULE ( i, o);
366 
`undef MODULE
367 6 unneback 
input i;
368 
output o;
369 
`ifdef SIM_GBUF
370 
assign o=i;
371 
`else
372 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
373 
`endif
374 
endmodule
375 40 unneback 
`endif
376 33 unneback 
 
377 6 unneback 
`else
378 33 unneback 
 
379 40 unneback 
`ifdef ALTERA
380 
`ifdef GBUF
381 21 unneback 
//altera
382 40 unneback 
`define MODULE gbuf
383 
module `BASE`MODULE ( i, o);
384 
`undef MODULE
385 33 unneback 
input i;
386 
output o;
387 
assign o = i;
388 
endmodule
389 40 unneback 
`endif
390 33 unneback 
 
391 6 unneback 
`else
392 
 
393 40 unneback 
`ifdef GBUF
394 6 unneback 
`timescale 1 ns/100 ps
395 40 unneback 
`define MODULE
396 
module `BASE`MODULE ( i, o);
397 
`undef MODULE
398 6 unneback 
input i;
399 
output o;
400 
assign o = i;
401 
endmodule
402 40 unneback 
`endif
403 6 unneback 
`endif // ALTERA
404 
`endif //ACTEL
405 
 
406 40 unneback 
`ifdef SYNC_RST
407 6 unneback 
// sync reset
408 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
409 6 unneback 
// output active high global reset sync with two DFFs
410 
`timescale 1 ns/100 ps
411 40 unneback 
`define MODULE sync_rst
412 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
413 
`undef MODULE
414 6 unneback 
input rst_n_i, clk;
415 
output rst_o;
416 18 unneback 
reg [1:0] tmp;
417 6 unneback 
always @ (posedge clk or negedge rst_n_i)
418 
if (!rst_n_i)
419 17 unneback 
        tmp <= 2'b11;
420 6 unneback 
else
421 33 unneback 
        tmp <= {1'b0,tmp[1]};
422 40 unneback 
`define MODULE gbuf
423 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
424 
`undef MODULE
425 6 unneback 
endmodule
426 40 unneback 
`endif
427 6 unneback 
 
428 40 unneback 
`ifdef PLL
429 6 unneback 
// vl_pll
430 
`ifdef ACTEL
431 32 unneback 
///////////////////////////////////////////////////////////////////////////////
432 17 unneback 
`timescale 1 ps/1 ps
433 40 unneback 
`define MODULE pll
434 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
435 
`undef MODULE
436 6 unneback 
parameter index = 0;
437 
parameter number_of_clk = 1;
438 17 unneback 
parameter period_time_0 = 20000;
439 
parameter period_time_1 = 20000;
440 
parameter period_time_2 = 20000;
441 
parameter lock_delay = 2000000;
442 6 unneback 
input clk_i, rst_n_i;
443 
output lock;
444 
output reg [0:number_of_clk-1] clk_o;
445 
output [0:number_of_clk-1] rst_o;
446 
 
447 
`ifdef SIM_PLL
448 
 
449 
always
450 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
451 
 
452 
generate if (number_of_clk > 1)
453 
always
454 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
455 
endgenerate
456 
 
457 
generate if (number_of_clk > 2)
458 
always
459 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
460 
endgenerate
461 
 
462 
genvar i;
463 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
464 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
465 
end
466 
endgenerate
467 
 
468 
assign #lock_delay lock = rst_n_i;
469 
 
470 
endmodule
471 
`else
472 
generate if (number_of_clk==1 & index==0) begin
473 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
474 
end
475 
endgenerate // index==0
476 
generate if (number_of_clk==1 & index==1) begin
477 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
478 
end
479 
endgenerate // index==1
480 
generate if (number_of_clk==1 & index==2) begin
481 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
482 
end
483 
endgenerate // index==2
484 
generate if (number_of_clk==1 & index==3) begin
485 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
486 
end
487 
endgenerate // index==0
488 
 
489 
generate if (number_of_clk==2 & index==0) begin
490 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
491 
end
492 
endgenerate // index==0
493 
generate if (number_of_clk==2 & index==1) begin
494 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
495 
end
496 
endgenerate // index==1
497 
generate if (number_of_clk==2 & index==2) begin
498 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
499 
end
500 
endgenerate // index==2
501 
generate if (number_of_clk==2 & index==3) begin
502 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
503 
end
504 
endgenerate // index==0
505 
 
506 
generate if (number_of_clk==3 & index==0) begin
507 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
508 
end
509 
endgenerate // index==0
510 
generate if (number_of_clk==3 & index==1) begin
511 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
512 
end
513 
endgenerate // index==1
514 
generate if (number_of_clk==3 & index==2) begin
515 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
516 
end
517 
endgenerate // index==2
518 
generate if (number_of_clk==3 & index==3) begin
519 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
520 
end
521 
endgenerate // index==0
522 
 
523 
genvar i;
524 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
525 40 unneback 
`define MODULE sync_rst
526 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
527 
`undef MODULE
528 6 unneback 
end
529 
endgenerate
530 
endmodule
531 
`endif
532 32 unneback 
///////////////////////////////////////////////////////////////////////////////
533 6 unneback 
 
534 
`else
535 
 
536 32 unneback 
///////////////////////////////////////////////////////////////////////////////
537 6 unneback 
`ifdef ALTERA
538 
 
539 32 unneback 
`timescale 1 ps/1 ps
540 40 unneback 
`define MODULE pll
541 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
542 
`undef MODULE
543 32 unneback 
parameter index = 0;
544 
parameter number_of_clk = 1;
545 
parameter period_time_0 = 20000;
546 
parameter period_time_1 = 20000;
547 
parameter period_time_2 = 20000;
548 
parameter period_time_3 = 20000;
549 
parameter period_time_4 = 20000;
550 
parameter lock_delay = 2000000;
551 
input clk_i, rst_n_i;
552 
output lock;
553 
output reg [0:number_of_clk-1] clk_o;
554 
output [0:number_of_clk-1] rst_o;
555 
 
556 
`ifdef SIM_PLL
557 
 
558 
always
559 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
560 
 
561 
generate if (number_of_clk > 1)
562 
always
563 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
564 
endgenerate
565 
 
566 
generate if (number_of_clk > 2)
567 
always
568 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
569 
endgenerate
570 
 
571 33 unneback 
generate if (number_of_clk > 3)
572 32 unneback 
always
573 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
574 
endgenerate
575 
 
576 33 unneback 
generate if (number_of_clk > 4)
577 32 unneback 
always
578 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
579 
endgenerate
580 
 
581 
genvar i;
582 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
583 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
584 
end
585 
endgenerate
586 
 
587 33 unneback 
//assign #lock_delay lock = rst_n_i;
588 
assign lock = rst_n_i;
589 32 unneback 
 
590 
endmodule
591 6 unneback 
`else
592 
 
593 33 unneback 
`ifdef VL_PLL0
594 
`ifdef VL_PLL0_CLK1
595 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
596 
`endif
597 
`ifdef VL_PLL0_CLK2
598 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
599 
`endif
600 
`ifdef VL_PLL0_CLK3
601 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
602 
`endif
603 
`ifdef VL_PLL0_CLK4
604 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
605 
`endif
606 
`ifdef VL_PLL0_CLK5
607 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
608 
`endif
609 
`endif
610 32 unneback 
 
611 33 unneback 
`ifdef VL_PLL1
612 
`ifdef VL_PLL1_CLK1
613 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
614 
`endif
615 
`ifdef VL_PLL1_CLK2
616 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
617 
`endif
618 
`ifdef VL_PLL1_CLK3
619 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
620 
`endif
621 
`ifdef VL_PLL1_CLK4
622 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
623 
`endif
624 
`ifdef VL_PLL1_CLK5
625 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
626 
`endif
627 
`endif
628 32 unneback 
 
629 33 unneback 
`ifdef VL_PLL2
630 
`ifdef VL_PLL2_CLK1
631 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
632 
`endif
633 
`ifdef VL_PLL2_CLK2
634 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
635 
`endif
636 
`ifdef VL_PLL2_CLK3
637 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
638 
`endif
639 
`ifdef VL_PLL2_CLK4
640 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
641 
`endif
642 
`ifdef VL_PLL2_CLK5
643 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
644 
`endif
645 
`endif
646 32 unneback 
 
647 33 unneback 
`ifdef VL_PLL3
648 
`ifdef VL_PLL3_CLK1
649 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
650 
`endif
651 
`ifdef VL_PLL3_CLK2
652 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
653 
`endif
654 
`ifdef VL_PLL3_CLK3
655 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
656 
`endif
657 
`ifdef VL_PLL3_CLK4
658 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
659 
`endif
660 
`ifdef VL_PLL3_CLK5
661 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
662 
`endif
663 
`endif
664 32 unneback 
 
665 
genvar i;
666 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
667 40 unneback 
`define MODULE sync_rst
668 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
669 
`undef MODULE
670 32 unneback 
end
671 
endgenerate
672 
endmodule
673 
`endif
674 
///////////////////////////////////////////////////////////////////////////////
675 
 
676 
`else
677 
 
678 6 unneback 
// generic PLL
679 17 unneback 
`timescale 1 ps/1 ps
680 40 unneback 
`define MODULE pll
681 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
682 
`undef MODULE
683 6 unneback 
parameter index = 0;
684 
parameter number_of_clk = 1;
685 17 unneback 
parameter period_time_0 = 20000;
686 
parameter period_time_1 = 20000;
687 
parameter period_time_2 = 20000;
688 6 unneback 
parameter lock_delay = 2000;
689 
input clk_i, rst_n_i;
690 
output lock;
691 
output reg [0:number_of_clk-1] clk_o;
692 
output [0:number_of_clk-1] rst_o;
693 
 
694 
always
695 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
696 
 
697 
generate if (number_of_clk > 1)
698 
always
699 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
700 
endgenerate
701 
 
702 
generate if (number_of_clk > 2)
703 
always
704 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
705 
endgenerate
706 
 
707 
genvar i;
708 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
709 40 unneback 
`define MODULE sync_rst
710 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
711 
`undef MODULE
712 6 unneback 
end
713 
endgenerate
714 
 
715 
assign #lock_delay lock = rst_n_i;
716 
 
717 
endmodule
718 
 
719 
`endif //altera
720 17 unneback 
`endif //actel
721 40 unneback 
`undef MODULE
722 
`endif//////////////////////////////////////////////////////////////////////
723 6 unneback 
////                                                              ////
724 
////  Versatile library, registers                                ////
725 
////                                                              ////
726 
////  Description                                                 ////
727 
////  Different type of registers                                 ////
728 
////                                                              ////
729 
////                                                              ////
730 
////  To Do:                                                      ////
731 
////   - add more different registers                             ////
732 
////                                                              ////
733 
////  Author(s):                                                  ////
734 
////      - Michael Unneback, unneback@opencores.org              ////
735 
////        ORSoC AB                                              ////
736 
////                                                              ////
737 
//////////////////////////////////////////////////////////////////////
738 
////                                                              ////
739 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
740 
////                                                              ////
741 
//// This source file may be used and distributed without         ////
742 
//// restriction provided that this copyright statement is not    ////
743 
//// removed from the file and that any derivative work contains  ////
744 
//// the original copyright notice and the associated disclaimer. ////
745 
////                                                              ////
746 
//// This source file is free software; you can redistribute it   ////
747 
//// and/or modify it under the terms of the GNU Lesser General   ////
748 
//// Public License as published by the Free Software Foundation; ////
749 
//// either version 2.1 of the License, or (at your option) any   ////
750 
//// later version.                                               ////
751 
////                                                              ////
752 
//// This source is distributed in the hope that it will be       ////
753 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
754 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
755 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
756 
//// details.                                                     ////
757 
////                                                              ////
758 
//// You should have received a copy of the GNU Lesser General    ////
759 
//// Public License along with this source; if not, download it   ////
760 
//// from http://www.opencores.org/lgpl.shtml                     ////
761 
////                                                              ////
762 
//////////////////////////////////////////////////////////////////////
763 
 
764 40 unneback 
`ifdef DFF
765 
`define MODULE dff
766 
module `BASE`MODULE ( d, q, clk, rst);
767 
`undef MODULE
768 6 unneback 
        parameter width = 1;
769 
        parameter reset_value = 0;
770 
 
771 
        input [width-1:0] d;
772 
        input clk, rst;
773 
        output reg [width-1:0] q;
774 
 
775 
        always @ (posedge clk or posedge rst)
776 
        if (rst)
777 
                q <= reset_value;
778 
        else
779 
                q <= d;
780 
 
781 
endmodule
782 40 unneback 
`endif
783 6 unneback 
 
784 40 unneback 
`ifdef DFF_ARRAY
785 
`define MODULE dff_array
786 
module `BASE`MODULE ( d, q, clk, rst);
787 
`undef MODULE
788 6 unneback 
 
789 
        parameter width = 1;
790 
        parameter depth = 2;
791 
        parameter reset_value = 1'b0;
792 
 
793 
        input [width-1:0] d;
794 
        input clk, rst;
795 
        output [width-1:0] q;
796 
        reg  [0:depth-1] q_tmp [width-1:0];
797 
        integer i;
798 
        always @ (posedge clk or posedge rst)
799 
        if (rst) begin
800 
            for (i=0;i<depth;i=i+1)
801 
                q_tmp[i] <= {width{reset_value}};
802 
        end else begin
803 
            q_tmp[0] <= d;
804 
            for (i=1;i<depth;i=i+1)
805 
                q_tmp[i] <= q_tmp[i-1];
806 
        end
807 
 
808 
    assign q = q_tmp[depth-1];
809 
 
810 
endmodule
811 40 unneback 
`endif
812 6 unneback 
 
813 40 unneback 
`ifdef DFF_CE
814 
`define MODULE dff_ce
815 
module `BASE`MODULE ( d, ce, q, clk, rst);
816 
`undef MODULE
817 6 unneback 
 
818 
        parameter width = 1;
819 
        parameter reset_value = 0;
820 
 
821 
        input [width-1:0] d;
822 
        input ce, clk, rst;
823 
        output reg [width-1:0] q;
824 
 
825 
        always @ (posedge clk or posedge rst)
826 
        if (rst)
827 
                q <= reset_value;
828 
        else
829 
                if (ce)
830 
                        q <= d;
831 
 
832 
endmodule
833 40 unneback 
`endif
834 6 unneback 
 
835 40 unneback 
`ifdef DFF_CE_CLEAR
836 
`define MODULE dff_ce_clear
837 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
838 
`undef MODULE
839 8 unneback 
 
840 
        parameter width = 1;
841 
        parameter reset_value = 0;
842 
 
843 
        input [width-1:0] d;
844 10 unneback 
        input ce, clear, clk, rst;
845 8 unneback 
        output reg [width-1:0] q;
846 
 
847 
        always @ (posedge clk or posedge rst)
848 
        if (rst)
849 
            q <= reset_value;
850 
        else
851 
            if (ce)
852 
                if (clear)
853 
                    q <= {width{1'b0}};
854 
                else
855 
                    q <= d;
856 
 
857 
endmodule
858 40 unneback 
`endif
859 8 unneback 
 
860 40 unneback 
`ifdef DF_CE_SET
861 
`define MODULE dff_ce_set
862 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
863 
`undef MODULE
864 24 unneback 
 
865 
        parameter width = 1;
866 
        parameter reset_value = 0;
867 
 
868 
        input [width-1:0] d;
869 
        input ce, set, clk, rst;
870 
        output reg [width-1:0] q;
871 
 
872 
        always @ (posedge clk or posedge rst)
873 
        if (rst)
874 
            q <= reset_value;
875 
        else
876 
            if (ce)
877 
                if (set)
878 
                    q <= {width{1'b1}};
879 
                else
880 
                    q <= d;
881 
 
882 
endmodule
883 40 unneback 
`endif
884 24 unneback 
 
885 40 unneback 
`ifdef SPR
886 
`define MODULE spr
887 
module `BASE`MODULE ( sp, r, q, clk, rst);
888 
`undef MODULE
889 
 
890 64 unneback 
        //parameter width = 1;
891 
        parameter reset_value = 1'b0;
892 29 unneback 
 
893 
        input sp, r;
894 
        output reg q;
895 
        input clk, rst;
896 
 
897 
        always @ (posedge clk or posedge rst)
898 
        if (rst)
899 
            q <= reset_value;
900 
        else
901 
            if (sp)
902 
                q <= 1'b1;
903 
            else if (r)
904 
                q <= 1'b0;
905 
 
906 
endmodule
907 40 unneback 
`endif
908 29 unneback 
 
909 40 unneback 
`ifdef SRP
910 
`define MODULE srp
911 
module `BASE`MODULE ( s, rp, q, clk, rst);
912 
`undef MODULE
913 
 
914 29 unneback 
        parameter width = 1;
915 
        parameter reset_value = 0;
916 
 
917 
        input s, rp;
918 
        output reg q;
919 
        input clk, rst;
920 
 
921 
        always @ (posedge clk or posedge rst)
922 
        if (rst)
923 
            q <= reset_value;
924 
        else
925 
            if (rp)
926 
                q <= 1'b0;
927 
            else if (s)
928 
                q <= 1'b1;
929 
 
930 
endmodule
931 40 unneback 
`endif
932 29 unneback 
 
933 40 unneback 
`ifdef ALTERA
934 29 unneback 
 
935 40 unneback 
`ifdef DFF_SR
936 6 unneback 
// megafunction wizard: %LPM_FF%
937 
// GENERATION: STANDARD
938 
// VERSION: WM1.0
939 
// MODULE: lpm_ff
940 
 
941 
// ============================================================
942 
// File Name: dff_sr.v
943 
// Megafunction Name(s):
944 
//                      lpm_ff
945 
//
946 
// Simulation Library Files(s):
947 
//                      lpm
948 
// ============================================================
949 
// ************************************************************
950 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
951 
//
952 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
953 
// ************************************************************
954 
 
955 
 
956 
//Copyright (C) 1991-2010 Altera Corporation
957 
//Your use of Altera Corporation's design tools, logic functions
958 
//and other software and tools, and its AMPP partner logic
959 
//functions, and any output files from any of the foregoing
960 
//(including device programming or simulation files), and any
961 
//associated documentation or information are expressly subject
962 
//to the terms and conditions of the Altera Program License
963 
//Subscription Agreement, Altera MegaCore Function License
964 
//Agreement, or other applicable license agreement, including,
965 
//without limitation, that your use is for the sole purpose of
966 
//programming logic devices manufactured by Altera and sold by
967 
//Altera or its authorized distributors.  Please refer to the
968 
//applicable agreement for further details.
969 
 
970 
 
971 
// synopsys translate_off
972 
`timescale 1 ps / 1 ps
973 
// synopsys translate_on
974 40 unneback 
`define MODULE dff_sr
975 
module `BASE`MODULE (
976 
`undef MODULE
977 
 
978 6 unneback 
        aclr,
979 
        aset,
980 
        clock,
981 
        data,
982 
        q);
983 
 
984 
        input     aclr;
985 
        input     aset;
986 
        input     clock;
987 
        input     data;
988 
        output    q;
989 
 
990 
        wire [0:0] sub_wire0;
991 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
992 
        wire  q = sub_wire1;
993 
        wire  sub_wire2 = data;
994 
        wire  sub_wire3 = sub_wire2;
995 
 
996 
        lpm_ff  lpm_ff_component (
997 
                                .aclr (aclr),
998 
                                .clock (clock),
999 
                                .data (sub_wire3),
1000 
                                .aset (aset),
1001 
                                .q (sub_wire0)
1002 
                                // synopsys translate_off
1003 
                                ,
1004 
                                .aload (),
1005 
                                .enable (),
1006 
                                .sclr (),
1007 
                                .sload (),
1008 
                                .sset ()
1009 
                                // synopsys translate_on
1010 
                                );
1011 
        defparam
1012 
                lpm_ff_component.lpm_fftype = "DFF",
1013 
                lpm_ff_component.lpm_type = "LPM_FF",
1014 
                lpm_ff_component.lpm_width = 1;
1015 
 
1016 
 
1017 
endmodule
1018 
 
1019 
// ============================================================
1020 
// CNX file retrieval info
1021 
// ============================================================
1022 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1023 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1024 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1025 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1026 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1027 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1028 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1029 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1030 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1031 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1032 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1033 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1034 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1035 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1036 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1037 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1038 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1039 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1040 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1041 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1042 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1043 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1044 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1045 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1046 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1047 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1048 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1049 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1050 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1051 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1052 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1053 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1054 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1055 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1056 
// Retrieval info: LIB_FILE: lpm
1057 40 unneback 
`endif
1058 6 unneback 
 
1059 
`else
1060 
 
1061 40 unneback 
`ifdef DFF_SR
1062 
`define MODULE dff_sr
1063 
module `BASE`MODULE ( aclr, aset, clock, data, q);
1064 
`undef MODULE
1065 6 unneback 
 
1066 
    input         aclr;
1067 
    input         aset;
1068 
    input         clock;
1069 
    input         data;
1070 
    output reg    q;
1071 
 
1072 
   always @ (posedge clock or posedge aclr or posedge aset)
1073 
     if (aclr)
1074 
       q <= 1'b0;
1075 
     else if (aset)
1076 
       q <= 1'b1;
1077 
     else
1078 
       q <= data;
1079 
 
1080 
endmodule
1081 40 unneback 
`endif
1082 6 unneback 
 
1083 
`endif
1084 
 
1085 
// LATCH
1086 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1087 
`ifdef ALTERA
1088 40 unneback 
 
1089 
`ifdef LATCH
1090 
`define MODULE latch
1091 
module `BASE`MODULE ( d, le, q, clk);
1092 
`undef MODULE
1093 6 unneback 
input d, le;
1094 
output q;
1095 
input clk;
1096 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1097 
endmodule
1098 40 unneback 
`endif
1099 
 
1100 6 unneback 
`else
1101 40 unneback 
 
1102 
`ifdef LATCH
1103 
`define MODULE latch
1104 
module `BASE`MODULE ( d, le, q, clk);
1105 
`undef MODULE
1106 6 unneback 
input d, le;
1107 48 unneback 
input clk;
1108 
always @ (le or d)
1109 60 unneback 
if (le)
1110 48 unneback 
    d <= q;
1111 6 unneback 
endmodule
1112 15 unneback 
`endif
1113 
 
1114 40 unneback 
`endif
1115 
 
1116 
`ifdef SHREG
1117 
`define MODULE shreg
1118 
module `BASE`MODULE ( d, q, clk, rst);
1119 
`undef MODULE
1120 
 
1121 17 unneback 
parameter depth = 10;
1122 
input d;
1123 
output q;
1124 
input clk, rst;
1125 
 
1126 
reg [1:depth] dffs;
1127 
 
1128 
always @ (posedge clk or posedge rst)
1129 
if (rst)
1130 
    dffs <= {depth{1'b0}};
1131 
else
1132 
    dffs <= {d,dffs[1:depth-1]};
1133 
assign q = dffs[depth];
1134 
endmodule
1135 40 unneback 
`endif
1136 17 unneback 
 
1137 40 unneback 
`ifdef SHREG_CE
1138 
`define MODULE shreg_ce
1139 
module `BASE`MODULE ( d, ce, q, clk, rst);
1140 
`undef MODULE
1141 17 unneback 
parameter depth = 10;
1142 
input d, ce;
1143 
output q;
1144 
input clk, rst;
1145 
 
1146 
reg [1:depth] dffs;
1147 
 
1148 
always @ (posedge clk or posedge rst)
1149 
if (rst)
1150 
    dffs <= {depth{1'b0}};
1151 
else
1152 
    if (ce)
1153 
        dffs <= {d,dffs[1:depth-1]};
1154 
assign q = dffs[depth];
1155 
endmodule
1156 40 unneback 
`endif
1157 17 unneback 
 
1158 40 unneback 
`ifdef DELAY
1159 
`define MODULE delay
1160 
module `BASE`MODULE ( d, q, clk, rst);
1161 
`undef MODULE
1162 15 unneback 
parameter depth = 10;
1163 
input d;
1164 
output q;
1165 
input clk, rst;
1166 
 
1167 
reg [1:depth] dffs;
1168 
 
1169 
always @ (posedge clk or posedge rst)
1170 
if (rst)
1171 
    dffs <= {depth{1'b0}};
1172 
else
1173 
    dffs <= {d,dffs[1:depth-1]};
1174 
assign q = dffs[depth];
1175 17 unneback 
endmodule
1176 40 unneback 
`endif
1177 17 unneback 
 
1178 40 unneback 
`ifdef DELAY_EMPTYFLAG
1179 
`define MODULE delay_emptyflag
1180 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1181 40 unneback 
`undef MODULE
1182 17 unneback 
parameter depth = 10;
1183 
input d;
1184 
output q, emptyflag;
1185 
input clk, rst;
1186 
 
1187 
reg [1:depth] dffs;
1188 
 
1189 
always @ (posedge clk or posedge rst)
1190 
if (rst)
1191 
    dffs <= {depth{1'b0}};
1192 
else
1193 
    dffs <= {d,dffs[1:depth-1]};
1194 
assign q = dffs[depth];
1195 
assign emptyflag = !(|dffs);
1196 
endmodule
1197 40 unneback 
`endif
1198 75 unneback 
 
1199 94 unneback 
`ifdef PULSE2TOGGLE
1200 98 unneback 
`define MODULE pulse2toggle
1201 
module `BASE`MODULE ( pl, q, clk, rst);
1202 75 unneback 
`undef MODULE
1203 94 unneback 
input pl;
1204 98 unneback 
output reg q;
1205 94 unneback 
input clk, rst;
1206 
always @ (posedge clk or posedge rst)
1207 75 unneback 
if (rst)
1208 94 unneback 
    q <= 1'b0;
1209 75 unneback 
else
1210 94 unneback 
    q <= pl ^ q;
1211 
endmodule
1212 
`endif
1213 75 unneback 
 
1214 94 unneback 
`ifdef TOGGLE2PULSE
1215 98 unneback 
`define MODULE toggle2pulse
1216 94 unneback 
module `BASE`MODULE (d, pl, clk, rst);
1217 97 unneback 
`undef MODULE
1218 94 unneback 
input d;
1219 
output pl;
1220 
input clk, rst;
1221 
reg dff;
1222 
always @ (posedge clk or posedge rst)
1223 
if (rst)
1224 
    dff <= 1'b0;
1225 75 unneback 
else
1226 94 unneback 
    dff <= d;
1227 98 unneback 
assign pl = d ^ dff;
1228 94 unneback 
endmodule
1229 
`endif
1230 75 unneback 
 
1231 94 unneback 
`ifdef SYNCHRONIZER
1232 
`define MODULE synchronizer
1233 
module `BASE`MODULE (d, q, clk, rst);
1234 
`undef MODULE
1235 
input d;
1236 
output reg q;
1237 
output clk, rst;
1238 
reg dff;
1239 
always @ (posedge clk or posedge rst)
1240 
if (rst)
1241 100 unneback 
    {q,dff} <= 2'b00;
1242 75 unneback 
else
1243 100 unneback 
    {q,dff} <= {dff,d};
1244 94 unneback 
endmodule
1245 
`endif
1246 75 unneback 
 
1247 94 unneback 
`ifdef CDC
1248 
`define MODULE cdc
1249 97 unneback 
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1250 94 unneback 
`undef MODULE
1251 
input start_pl;
1252 
output take_it_pl;
1253 
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1254 
output got_it_pl;
1255 
input clk_src, rst_src;
1256 
input clk_dst, rst_dst;
1257 
wire take_it_tg, take_it_tg_sync;
1258 
wire got_it_tg, got_it_tg_sync;
1259 
// src -> dst
1260 
`define MODULE pulse2toggle
1261 
`BASE`MODULE p2t0 (
1262 
`undef MODULE
1263 
    .pl(start_pl),
1264 
    .q(take_it_tg),
1265 
    .clk(clk_src),
1266 
    .rst(rst_src));
1267 75 unneback 
 
1268 94 unneback 
`define MODULE synchronizer
1269 
`BASE`MODULE sync0 (
1270 
`undef MODULE
1271 
    .d(take_it_tg),
1272 
    .q(take_it_tg_sync),
1273 
    .clk(clk_dst),
1274 
    .rst(rst_dst));
1275 
 
1276 
`define MODULE toggle2pulse
1277 
`BASE`MODULE t2p0 (
1278 
`undef MODULE
1279 100 unneback 
    .d(take_it_tg_sync),
1280 94 unneback 
    .pl(take_it_pl),
1281 
    .clk(clk_dst),
1282 
    .rst(rst_dst));
1283 
 
1284 
// dst -> src
1285 
`define MODULE pulse2toggle
1286 98 unneback 
`BASE`MODULE p2t1 (
1287 94 unneback 
`undef MODULE
1288 
    .pl(take_it_grant_pl),
1289 
    .q(got_it_tg),
1290 
    .clk(clk_dst),
1291 
    .rst(rst_dst));
1292 
 
1293 
`define MODULE synchronizer
1294 
`BASE`MODULE sync1 (
1295 
`undef MODULE
1296 
    .d(got_it_tg),
1297 
    .q(got_it_tg_sync),
1298 
    .clk(clk_src),
1299 
    .rst(rst_src));
1300 
 
1301 
`define MODULE toggle2pulse
1302 
`BASE`MODULE t2p1 (
1303 
`undef MODULE
1304 100 unneback 
    .d(got_it_tg_sync),
1305 94 unneback 
    .pl(got_it_pl),
1306 
    .clk(clk_src),
1307 
    .rst(rst_src));
1308 
 
1309 75 unneback 
endmodule
1310 
`endif
1311 17 unneback 
//////////////////////////////////////////////////////////////////////
1312 6 unneback 
////                                                              ////
1313 18 unneback 
////  Logic functions                                             ////
1314 
////                                                              ////
1315 
////  Description                                                 ////
1316 
////  Logic functions such as multiplexers                        ////
1317 
////                                                              ////
1318 
////                                                              ////
1319 
////  To Do:                                                      ////
1320 
////   -                                                          ////
1321 
////                                                              ////
1322 
////  Author(s):                                                  ////
1323 
////      - Michael Unneback, unneback@opencores.org              ////
1324 
////        ORSoC AB                                              ////
1325 
////                                                              ////
1326 
//////////////////////////////////////////////////////////////////////
1327 
////                                                              ////
1328 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1329 
////                                                              ////
1330 
//// This source file may be used and distributed without         ////
1331 
//// restriction provided that this copyright statement is not    ////
1332 
//// removed from the file and that any derivative work contains  ////
1333 
//// the original copyright notice and the associated disclaimer. ////
1334 
////                                                              ////
1335 
//// This source file is free software; you can redistribute it   ////
1336 
//// and/or modify it under the terms of the GNU Lesser General   ////
1337 
//// Public License as published by the Free Software Foundation; ////
1338 
//// either version 2.1 of the License, or (at your option) any   ////
1339 
//// later version.                                               ////
1340 
////                                                              ////
1341 
//// This source is distributed in the hope that it will be       ////
1342 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1343 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1344 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1345 
//// details.                                                     ////
1346 
////                                                              ////
1347 
//// You should have received a copy of the GNU Lesser General    ////
1348 
//// Public License along with this source; if not, download it   ////
1349 
//// from http://www.opencores.org/lgpl.shtml                     ////
1350 
////                                                              ////
1351 
//////////////////////////////////////////////////////////////////////
1352 40 unneback 
`ifdef MUX_ANDOR
1353 
`define MODULE mux_andor
1354 
module `BASE`MODULE ( a, sel, dout);
1355 
`undef MODULE
1356 36 unneback 
 
1357 
parameter width = 32;
1358 
parameter nr_of_ports = 4;
1359 
 
1360 
input [nr_of_ports*width-1:0] a;
1361 
input [nr_of_ports-1:0] sel;
1362 
output reg [width-1:0] dout;
1363 
 
1364 38 unneback 
integer i,j;
1365 
 
1366 36 unneback 
always @ (a, sel)
1367 
begin
1368 
    dout = a[width-1:0] & {width{sel[0]}};
1369 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1370 
        for (j=0;j<width;j=j+1)
1371 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1372 36 unneback 
end
1373 
 
1374 
endmodule
1375 40 unneback 
`endif
1376 36 unneback 
 
1377 40 unneback 
`ifdef MUX2_ANDOR
1378 
`define MODULE mux2_andor
1379 
module `BASE`MODULE ( a1, a0, sel, dout);
1380 
`undef MODULE
1381 18 unneback 
 
1382 34 unneback 
parameter width = 32;
1383 35 unneback 
localparam nr_of_ports = 2;
1384 34 unneback 
input [width-1:0] a1, a0;
1385 
input [nr_of_ports-1:0] sel;
1386 
output [width-1:0] dout;
1387 
 
1388 40 unneback 
`define MODULE mux_andor
1389 
`BASE`MODULE
1390 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1391 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1392 40 unneback 
`undef MODULE
1393 
 
1394 34 unneback 
endmodule
1395 40 unneback 
`endif
1396 34 unneback 
 
1397 40 unneback 
`ifdef MUX3_ANDOR
1398 
`define MODULE mux3_andor
1399 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1400 
`undef MODULE
1401 34 unneback 
 
1402 
parameter width = 32;
1403 35 unneback 
localparam nr_of_ports = 3;
1404 34 unneback 
input [width-1:0] a2, a1, a0;
1405 
input [nr_of_ports-1:0] sel;
1406 
output [width-1:0] dout;
1407 
 
1408 40 unneback 
`define MODULE mux_andor
1409 
`BASE`MODULE
1410 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1411 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1412 40 unneback 
`undef MODULE
1413 34 unneback 
endmodule
1414 40 unneback 
`endif
1415 34 unneback 
 
1416 40 unneback 
`ifdef MUX4_ANDOR
1417 
`define MODULE mux4_andor
1418 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1419 
`undef MODULE
1420 18 unneback 
 
1421 
parameter width = 32;
1422 35 unneback 
localparam nr_of_ports = 4;
1423 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1424 
input [nr_of_ports-1:0] sel;
1425 22 unneback 
output [width-1:0] dout;
1426 18 unneback 
 
1427 40 unneback 
`define MODULE mux_andor
1428 
`BASE`MODULE
1429 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1430 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1431 40 unneback 
`undef MODULE
1432 18 unneback 
 
1433 
endmodule
1434 40 unneback 
`endif
1435 18 unneback 
 
1436 40 unneback 
`ifdef MUX5_ANDOR
1437 
`define MODULE mux5_andor
1438 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1439 
`undef MODULE
1440 18 unneback 
 
1441 
parameter width = 32;
1442 35 unneback 
localparam nr_of_ports = 5;
1443 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1444 
input [nr_of_ports-1:0] sel;
1445 22 unneback 
output [width-1:0] dout;
1446 18 unneback 
 
1447 40 unneback 
`define MODULE mux_andor
1448 
`BASE`MODULE
1449 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1450 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1451 40 unneback 
`undef MODULE
1452 18 unneback 
 
1453 
endmodule
1454 40 unneback 
`endif
1455 18 unneback 
 
1456 40 unneback 
`ifdef MUX6_ANDOR
1457 
`define MODULE mux6_andor
1458 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1459 
`undef MODULE
1460 18 unneback 
 
1461 
parameter width = 32;
1462 35 unneback 
localparam nr_of_ports = 6;
1463 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1464 
input [nr_of_ports-1:0] sel;
1465 22 unneback 
output [width-1:0] dout;
1466 18 unneback 
 
1467 40 unneback 
`define MODULE mux_andor
1468 
`BASE`MODULE
1469 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1470 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1471 40 unneback 
`undef MODULE
1472 18 unneback 
 
1473 
endmodule
1474 40 unneback 
`endif
1475 43 unneback 
 
1476 
`ifdef PARITY
1477 
 
1478 
`define MODULE parity_generate
1479 
module `BASE`MODULE (data, parity);
1480 
`undef MODULE
1481 
parameter word_size = 32;
1482 
parameter chunk_size = 8;
1483 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1484 
input [word_size-1:0] data;
1485 
output reg [word_size/chunk_size-1:0] parity;
1486 
integer i,j;
1487 
always @ (data)
1488 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1489 
    parity[i] = parity_type;
1490 
    for (j=0;j<chunk_size;j=j+1) begin
1491 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1492 43 unneback 
    end
1493 
end
1494 
endmodule
1495 
 
1496 
`define MODULE parity_check
1497 
module `BASE`MODULE( data, parity, parity_error);
1498 
`undef MODULE
1499 
parameter word_size = 32;
1500 
parameter chunk_size = 8;
1501 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1502 
input [word_size-1:0] data;
1503 
input [word_size/chunk_size-1:0] parity;
1504 
output parity_error;
1505 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1506 43 unneback 
integer i,j;
1507 
always @ (data or parity)
1508 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1509 
    error_flag[i] = parity[i] ^ parity_type;
1510 
    for (j=0;j<chunk_size;j=j+1) begin
1511 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1512 43 unneback 
    end
1513 
end
1514 
assign parity_error = |error_flag;
1515 
endmodule
1516 
 
1517 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1518 
////                                                              ////
1519 
////  IO functions                                                ////
1520 
////                                                              ////
1521 
////  Description                                                 ////
1522 
////  IO functions such as IOB flip-flops                         ////
1523 
////                                                              ////
1524 
////                                                              ////
1525 
////  To Do:                                                      ////
1526 
////   -                                                          ////
1527 
////                                                              ////
1528 
////  Author(s):                                                  ////
1529 
////      - Michael Unneback, unneback@opencores.org              ////
1530 
////        ORSoC AB                                              ////
1531 
////                                                              ////
1532 18 unneback 
//////////////////////////////////////////////////////////////////////
1533 
////                                                              ////
1534 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1535 
////                                                              ////
1536 
//// This source file may be used and distributed without         ////
1537 
//// restriction provided that this copyright statement is not    ////
1538 
//// removed from the file and that any derivative work contains  ////
1539 
//// the original copyright notice and the associated disclaimer. ////
1540 
////                                                              ////
1541 
//// This source file is free software; you can redistribute it   ////
1542 
//// and/or modify it under the terms of the GNU Lesser General   ////
1543 
//// Public License as published by the Free Software Foundation; ////
1544 
//// either version 2.1 of the License, or (at your option) any   ////
1545 
//// later version.                                               ////
1546 
////                                                              ////
1547 
//// This source is distributed in the hope that it will be       ////
1548 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1549 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1550 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1551 
//// details.                                                     ////
1552 
////                                                              ////
1553 
//// You should have received a copy of the GNU Lesser General    ////
1554 
//// Public License along with this source; if not, download it   ////
1555 
//// from http://www.opencores.org/lgpl.shtml                     ////
1556 
////                                                              ////
1557 
//////////////////////////////////////////////////////////////////////
1558 45 unneback 
`timescale 1ns/1ns
1559 44 unneback 
`ifdef O_DFF
1560 
`define MODULE o_dff
1561 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1562 
`undef MODULE
1563 
parameter width = 1;
1564 45 unneback 
parameter reset_value = {width{1'b0}};
1565 
input  [width-1:0]  d_i;
1566 44 unneback 
output [width-1:0] o_pad;
1567 
input clk, rst;
1568 
wire [width-1:0] d_i_int `SYN_KEEP;
1569 45 unneback 
reg  [width-1:0] o_pad_int;
1570 44 unneback 
assign d_i_int = d_i;
1571 
genvar i;
1572 45 unneback 
generate
1573 44 unneback 
for (i=0;i<width;i=i+1) begin
1574 
    always @ (posedge clk or posedge rst)
1575 
    if (rst)
1576 45 unneback 
        o_pad_int[i] <= reset_value[i];
1577 44 unneback 
    else
1578 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1579 
    assign #1 o_pad[i] = o_pad_int[i];
1580 44 unneback 
end
1581 
endgenerate
1582 
endmodule
1583 
`endif
1584 
 
1585 45 unneback 
`timescale 1ns/1ns
1586 44 unneback 
`ifdef IO_DFF_OE
1587 
`define MODULE io_dff_oe
1588 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1589 
`undef MODULE
1590 
parameter width = 1;
1591 
input  [width-1:0] d_o;
1592 
output reg [width-1:0] d_i;
1593 
input oe;
1594 
inout [width-1:0] io_pad;
1595 
input clk, rst;
1596 
wire [width-1:0] oe_d `SYN_KEEP;
1597 
reg [width-1:0] oe_q;
1598 
reg [width-1:0] d_o_q;
1599 
assign oe_d = {width{oe}};
1600 
genvar i;
1601 
generate
1602 
for (i=0;i<width;i=i+1) begin
1603 
    always @ (posedge clk or posedge rst)
1604 
    if (rst)
1605 
        oe_q[i] <= 1'b0;
1606 
    else
1607 
        oe_q[i] <= oe_d[i];
1608 
    always @ (posedge clk or posedge rst)
1609 
    if (rst)
1610 
        d_o_q[i] <= 1'b0;
1611 
    else
1612 
        d_o_q[i] <= d_o[i];
1613 
    always @ (posedge clk or posedge rst)
1614 
    if (rst)
1615 
        d_i[i] <= 1'b0;
1616 
    else
1617 
        d_i[i] <= io_pad[i];
1618 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1619 44 unneback 
end
1620 
endgenerate
1621 
endmodule
1622 
`endif
1623 
`ifdef CNT_BIN
1624 
//////////////////////////////////////////////////////////////////////
1625 
////                                                              ////
1626 6 unneback 
////  Versatile counter                                           ////
1627 
////                                                              ////
1628 
////  Description                                                 ////
1629 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1630 
////  counter                                                     ////
1631 
////                                                              ////
1632 
////  To Do:                                                      ////
1633 
////   - add LFSR with more taps                                  ////
1634 
////                                                              ////
1635 
////  Author(s):                                                  ////
1636 
////      - Michael Unneback, unneback@opencores.org              ////
1637 
////        ORSoC AB                                              ////
1638 
////                                                              ////
1639 
//////////////////////////////////////////////////////////////////////
1640 
////                                                              ////
1641 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1642 
////                                                              ////
1643 
//// This source file may be used and distributed without         ////
1644 
//// restriction provided that this copyright statement is not    ////
1645 
//// removed from the file and that any derivative work contains  ////
1646 
//// the original copyright notice and the associated disclaimer. ////
1647 
////                                                              ////
1648 
//// This source file is free software; you can redistribute it   ////
1649 
//// and/or modify it under the terms of the GNU Lesser General   ////
1650 
//// Public License as published by the Free Software Foundation; ////
1651 
//// either version 2.1 of the License, or (at your option) any   ////
1652 
//// later version.                                               ////
1653 
////                                                              ////
1654 
//// This source is distributed in the hope that it will be       ////
1655 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1656 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1657 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1658 
//// details.                                                     ////
1659 
////                                                              ////
1660 
//// You should have received a copy of the GNU Lesser General    ////
1661 
//// Public License along with this source; if not, download it   ////
1662 
//// from http://www.opencores.org/lgpl.shtml                     ////
1663 
////                                                              ////
1664 
//////////////////////////////////////////////////////////////////////
1665 
 
1666 
// binary counter
1667 22 unneback 
 
1668 40 unneback 
`define MODULE cnt_bin
1669 
module `BASE`MODULE (
1670 
`undef MODULE
1671 
 q, rst, clk);
1672 
 
1673 22 unneback 
   parameter length = 4;
1674 
   output [length:1] q;
1675 
   input rst;
1676 
   input clk;
1677 
 
1678 
   parameter clear_value = 0;
1679 
   parameter set_value = 1;
1680 
   parameter wrap_value = 0;
1681 
   parameter level1_value = 15;
1682 
 
1683 
   reg  [length:1] qi;
1684 
   wire [length:1] q_next;
1685 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1686 
 
1687 
   always @ (posedge clk or posedge rst)
1688 
     if (rst)
1689 
       qi <= {length{1'b0}};
1690 
     else
1691 
       qi <= q_next;
1692 
 
1693 
   assign q = qi;
1694 
 
1695 
endmodule
1696 40 unneback 
`endif
1697 
`ifdef CNT_BIN_CLEAR
1698 22 unneback 
//////////////////////////////////////////////////////////////////////
1699 
////                                                              ////
1700 
////  Versatile counter                                           ////
1701 
////                                                              ////
1702 
////  Description                                                 ////
1703 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1704 
////  counter                                                     ////
1705 
////                                                              ////
1706 
////  To Do:                                                      ////
1707 
////   - add LFSR with more taps                                  ////
1708 
////                                                              ////
1709 
////  Author(s):                                                  ////
1710 
////      - Michael Unneback, unneback@opencores.org              ////
1711 
////        ORSoC AB                                              ////
1712 
////                                                              ////
1713 
//////////////////////////////////////////////////////////////////////
1714 
////                                                              ////
1715 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1716 
////                                                              ////
1717 
//// This source file may be used and distributed without         ////
1718 
//// restriction provided that this copyright statement is not    ////
1719 
//// removed from the file and that any derivative work contains  ////
1720 
//// the original copyright notice and the associated disclaimer. ////
1721 
////                                                              ////
1722 
//// This source file is free software; you can redistribute it   ////
1723 
//// and/or modify it under the terms of the GNU Lesser General   ////
1724 
//// Public License as published by the Free Software Foundation; ////
1725 
//// either version 2.1 of the License, or (at your option) any   ////
1726 
//// later version.                                               ////
1727 
////                                                              ////
1728 
//// This source is distributed in the hope that it will be       ////
1729 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1730 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1731 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1732 
//// details.                                                     ////
1733 
////                                                              ////
1734 
//// You should have received a copy of the GNU Lesser General    ////
1735 
//// Public License along with this source; if not, download it   ////
1736 
//// from http://www.opencores.org/lgpl.shtml                     ////
1737 
////                                                              ////
1738 
//////////////////////////////////////////////////////////////////////
1739 
 
1740 
// binary counter
1741 
 
1742 40 unneback 
`define MODULE cnt_bin_clear
1743 
module `BASE`MODULE (
1744 
`undef MODULE
1745 
 clear, q, rst, clk);
1746 
 
1747 22 unneback 
   parameter length = 4;
1748 
   input clear;
1749 
   output [length:1] q;
1750 
   input rst;
1751 
   input clk;
1752 
 
1753 
   parameter clear_value = 0;
1754 
   parameter set_value = 1;
1755 
   parameter wrap_value = 0;
1756 
   parameter level1_value = 15;
1757 
 
1758 
   reg  [length:1] qi;
1759 
   wire [length:1] q_next;
1760 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1761 
 
1762 
   always @ (posedge clk or posedge rst)
1763 
     if (rst)
1764 
       qi <= {length{1'b0}};
1765 
     else
1766 
       qi <= q_next;
1767 
 
1768 
   assign q = qi;
1769 
 
1770 
endmodule
1771 40 unneback 
`endif
1772 
`ifdef CNT_BIN_CE
1773 22 unneback 
//////////////////////////////////////////////////////////////////////
1774 
////                                                              ////
1775 
////  Versatile counter                                           ////
1776 
////                                                              ////
1777 
////  Description                                                 ////
1778 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1779 
////  counter                                                     ////
1780 
////                                                              ////
1781 
////  To Do:                                                      ////
1782 
////   - add LFSR with more taps                                  ////
1783 
////                                                              ////
1784 
////  Author(s):                                                  ////
1785 
////      - Michael Unneback, unneback@opencores.org              ////
1786 
////        ORSoC AB                                              ////
1787 
////                                                              ////
1788 
//////////////////////////////////////////////////////////////////////
1789 
////                                                              ////
1790 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1791 
////                                                              ////
1792 
//// This source file may be used and distributed without         ////
1793 
//// restriction provided that this copyright statement is not    ////
1794 
//// removed from the file and that any derivative work contains  ////
1795 
//// the original copyright notice and the associated disclaimer. ////
1796 
////                                                              ////
1797 
//// This source file is free software; you can redistribute it   ////
1798 
//// and/or modify it under the terms of the GNU Lesser General   ////
1799 
//// Public License as published by the Free Software Foundation; ////
1800 
//// either version 2.1 of the License, or (at your option) any   ////
1801 
//// later version.                                               ////
1802 
////                                                              ////
1803 
//// This source is distributed in the hope that it will be       ////
1804 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1805 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1806 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1807 
//// details.                                                     ////
1808 
////                                                              ////
1809 
//// You should have received a copy of the GNU Lesser General    ////
1810 
//// Public License along with this source; if not, download it   ////
1811 
//// from http://www.opencores.org/lgpl.shtml                     ////
1812 
////                                                              ////
1813 
//////////////////////////////////////////////////////////////////////
1814 
 
1815 
// binary counter
1816 6 unneback 
 
1817 40 unneback 
`define MODULE cnt_bin_ce
1818 
module `BASE`MODULE (
1819 
`undef MODULE
1820 
 cke, q, rst, clk);
1821 
 
1822 6 unneback 
   parameter length = 4;
1823 
   input cke;
1824 
   output [length:1] q;
1825 
   input rst;
1826 
   input clk;
1827 
 
1828 
   parameter clear_value = 0;
1829 
   parameter set_value = 1;
1830 
   parameter wrap_value = 0;
1831 
   parameter level1_value = 15;
1832 
 
1833 
   reg  [length:1] qi;
1834 
   wire [length:1] q_next;
1835 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1836 
 
1837 
   always @ (posedge clk or posedge rst)
1838 
     if (rst)
1839 
       qi <= {length{1'b0}};
1840 
     else
1841 
     if (cke)
1842 
       qi <= q_next;
1843 
 
1844 
   assign q = qi;
1845 
 
1846 
endmodule
1847 40 unneback 
`endif
1848 
`ifdef CNT_BIN_CE_CLEAR
1849 6 unneback 
//////////////////////////////////////////////////////////////////////
1850 
////                                                              ////
1851 
////  Versatile counter                                           ////
1852 
////                                                              ////
1853 
////  Description                                                 ////
1854 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1855 
////  counter                                                     ////
1856 
////                                                              ////
1857 
////  To Do:                                                      ////
1858 
////   - add LFSR with more taps                                  ////
1859 
////                                                              ////
1860 
////  Author(s):                                                  ////
1861 
////      - Michael Unneback, unneback@opencores.org              ////
1862 
////        ORSoC AB                                              ////
1863 
////                                                              ////
1864 
//////////////////////////////////////////////////////////////////////
1865 
////                                                              ////
1866 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1867 
////                                                              ////
1868 
//// This source file may be used and distributed without         ////
1869 
//// restriction provided that this copyright statement is not    ////
1870 
//// removed from the file and that any derivative work contains  ////
1871 
//// the original copyright notice and the associated disclaimer. ////
1872 
////                                                              ////
1873 
//// This source file is free software; you can redistribute it   ////
1874 
//// and/or modify it under the terms of the GNU Lesser General   ////
1875 
//// Public License as published by the Free Software Foundation; ////
1876 
//// either version 2.1 of the License, or (at your option) any   ////
1877 
//// later version.                                               ////
1878 
////                                                              ////
1879 
//// This source is distributed in the hope that it will be       ////
1880 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1881 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1882 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1883 
//// details.                                                     ////
1884 
////                                                              ////
1885 
//// You should have received a copy of the GNU Lesser General    ////
1886 
//// Public License along with this source; if not, download it   ////
1887 
//// from http://www.opencores.org/lgpl.shtml                     ////
1888 
////                                                              ////
1889 
//////////////////////////////////////////////////////////////////////
1890 
 
1891 
// binary counter
1892 
 
1893 40 unneback 
`define MODULE cnt_bin_ce_clear
1894 
module `BASE`MODULE (
1895 
`undef MODULE
1896 
 clear, cke, q, rst, clk);
1897 
 
1898 6 unneback 
   parameter length = 4;
1899 
   input clear;
1900 
   input cke;
1901 
   output [length:1] q;
1902 
   input rst;
1903 
   input clk;
1904 
 
1905 
   parameter clear_value = 0;
1906 
   parameter set_value = 1;
1907 
   parameter wrap_value = 0;
1908 
   parameter level1_value = 15;
1909 
 
1910 
   reg  [length:1] qi;
1911 
   wire [length:1] q_next;
1912 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1913 
 
1914 
   always @ (posedge clk or posedge rst)
1915 
     if (rst)
1916 
       qi <= {length{1'b0}};
1917 
     else
1918 
     if (cke)
1919 
       qi <= q_next;
1920 
 
1921 
   assign q = qi;
1922 
 
1923 
endmodule
1924 40 unneback 
`endif
1925 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1926 6 unneback 
//////////////////////////////////////////////////////////////////////
1927 
////                                                              ////
1928 
////  Versatile counter                                           ////
1929 
////                                                              ////
1930 
////  Description                                                 ////
1931 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1932 
////  counter                                                     ////
1933 
////                                                              ////
1934 
////  To Do:                                                      ////
1935 
////   - add LFSR with more taps                                  ////
1936 
////                                                              ////
1937 
////  Author(s):                                                  ////
1938 
////      - Michael Unneback, unneback@opencores.org              ////
1939 
////        ORSoC AB                                              ////
1940 
////                                                              ////
1941 
//////////////////////////////////////////////////////////////////////
1942 
////                                                              ////
1943 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1944 
////                                                              ////
1945 
//// This source file may be used and distributed without         ////
1946 
//// restriction provided that this copyright statement is not    ////
1947 
//// removed from the file and that any derivative work contains  ////
1948 
//// the original copyright notice and the associated disclaimer. ////
1949 
////                                                              ////
1950 
//// This source file is free software; you can redistribute it   ////
1951 
//// and/or modify it under the terms of the GNU Lesser General   ////
1952 
//// Public License as published by the Free Software Foundation; ////
1953 
//// either version 2.1 of the License, or (at your option) any   ////
1954 
//// later version.                                               ////
1955 
////                                                              ////
1956 
//// This source is distributed in the hope that it will be       ////
1957 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1958 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1959 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1960 
//// details.                                                     ////
1961 
////                                                              ////
1962 
//// You should have received a copy of the GNU Lesser General    ////
1963 
//// Public License along with this source; if not, download it   ////
1964 
//// from http://www.opencores.org/lgpl.shtml                     ////
1965 
////                                                              ////
1966 
//////////////////////////////////////////////////////////////////////
1967 
 
1968 
// binary counter
1969 29 unneback 
 
1970 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1971 
module `BASE`MODULE (
1972 
`undef MODULE
1973 
 clear, cke, q, level1, level2, rst, clk);
1974 
 
1975 29 unneback 
   parameter length = 4;
1976 
   input clear;
1977 
   input cke;
1978 
   output [length:1] q;
1979 
   output reg level1;
1980 
   output reg level2;
1981 
   input rst;
1982 
   input clk;
1983 
 
1984 
   parameter clear_value = 0;
1985 
   parameter set_value = 1;
1986 30 unneback 
   parameter wrap_value = 15;
1987 
   parameter level1_value = 8;
1988 
   parameter level2_value = 15;
1989 29 unneback 
 
1990 
   wire rew;
1991 30 unneback 
   assign rew = 1'b0;
1992 29 unneback 
   reg  [length:1] qi;
1993 
   wire [length:1] q_next;
1994 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1995 
 
1996 
   always @ (posedge clk or posedge rst)
1997 
     if (rst)
1998 
       qi <= {length{1'b0}};
1999 
     else
2000 
     if (cke)
2001 
       qi <= q_next;
2002 
 
2003 
   assign q = qi;
2004 
 
2005 
 
2006 
    always @ (posedge clk or posedge rst)
2007 
    if (rst)
2008 
        level1 <= 1'b0;
2009 
    else
2010 
    if (cke)
2011 
    if (clear)
2012 
        level1 <= 1'b0;
2013 
    else if (q_next == level1_value)
2014 
        level1 <= 1'b1;
2015 
    else if (qi == level1_value & rew)
2016 
        level1 <= 1'b0;
2017 
 
2018 
    always @ (posedge clk or posedge rst)
2019 
    if (rst)
2020 
        level2 <= 1'b0;
2021 
    else
2022 
    if (cke)
2023 
    if (clear)
2024 
        level2 <= 1'b0;
2025 
    else if (q_next == level2_value)
2026 
        level2 <= 1'b1;
2027 
    else if (qi == level2_value & rew)
2028 
        level2 <= 1'b0;
2029 
endmodule
2030 40 unneback 
`endif
2031 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2032 29 unneback 
//////////////////////////////////////////////////////////////////////
2033 
////                                                              ////
2034 
////  Versatile counter                                           ////
2035 
////                                                              ////
2036 
////  Description                                                 ////
2037 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2038 
////  counter                                                     ////
2039 
////                                                              ////
2040 
////  To Do:                                                      ////
2041 
////   - add LFSR with more taps                                  ////
2042 
////                                                              ////
2043 
////  Author(s):                                                  ////
2044 
////      - Michael Unneback, unneback@opencores.org              ////
2045 
////        ORSoC AB                                              ////
2046 
////                                                              ////
2047 
//////////////////////////////////////////////////////////////////////
2048 
////                                                              ////
2049 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2050 
////                                                              ////
2051 
//// This source file may be used and distributed without         ////
2052 
//// restriction provided that this copyright statement is not    ////
2053 
//// removed from the file and that any derivative work contains  ////
2054 
//// the original copyright notice and the associated disclaimer. ////
2055 
////                                                              ////
2056 
//// This source file is free software; you can redistribute it   ////
2057 
//// and/or modify it under the terms of the GNU Lesser General   ////
2058 
//// Public License as published by the Free Software Foundation; ////
2059 
//// either version 2.1 of the License, or (at your option) any   ////
2060 
//// later version.                                               ////
2061 
////                                                              ////
2062 
//// This source is distributed in the hope that it will be       ////
2063 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2064 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2065 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2066 
//// details.                                                     ////
2067 
////                                                              ////
2068 
//// You should have received a copy of the GNU Lesser General    ////
2069 
//// Public License along with this source; if not, download it   ////
2070 
//// from http://www.opencores.org/lgpl.shtml                     ////
2071 
////                                                              ////
2072 
//////////////////////////////////////////////////////////////////////
2073 
 
2074 
// binary counter
2075 6 unneback 
 
2076 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
2077 
module `BASE`MODULE (
2078 
`undef MODULE
2079 
 clear, set, cke, rew, q, rst, clk);
2080 
 
2081 6 unneback 
   parameter length = 4;
2082 
   input clear;
2083 
   input set;
2084 
   input cke;
2085 
   input rew;
2086 
   output [length:1] q;
2087 
   input rst;
2088 
   input clk;
2089 
 
2090 
   parameter clear_value = 0;
2091 
   parameter set_value = 1;
2092 
   parameter wrap_value = 0;
2093 
   parameter level1_value = 15;
2094 
 
2095 
   reg  [length:1] qi;
2096 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2097 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2098 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2099 
   assign q_next = rew ? q_next_rew : q_next_fw;
2100 
 
2101 
   always @ (posedge clk or posedge rst)
2102 
     if (rst)
2103 
       qi <= {length{1'b0}};
2104 
     else
2105 
     if (cke)
2106 
       qi <= q_next;
2107 
 
2108 
   assign q = qi;
2109 
 
2110 
endmodule
2111 40 unneback 
`endif
2112 
`ifdef CNT_BIN_CE_REW_L1
2113 6 unneback 
//////////////////////////////////////////////////////////////////////
2114 
////                                                              ////
2115 
////  Versatile counter                                           ////
2116 
////                                                              ////
2117 
////  Description                                                 ////
2118 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2119 
////  counter                                                     ////
2120 
////                                                              ////
2121 
////  To Do:                                                      ////
2122 
////   - add LFSR with more taps                                  ////
2123 
////                                                              ////
2124 
////  Author(s):                                                  ////
2125 
////      - Michael Unneback, unneback@opencores.org              ////
2126 
////        ORSoC AB                                              ////
2127 
////                                                              ////
2128 
//////////////////////////////////////////////////////////////////////
2129 
////                                                              ////
2130 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2131 
////                                                              ////
2132 
//// This source file may be used and distributed without         ////
2133 
//// restriction provided that this copyright statement is not    ////
2134 
//// removed from the file and that any derivative work contains  ////
2135 
//// the original copyright notice and the associated disclaimer. ////
2136 
////                                                              ////
2137 
//// This source file is free software; you can redistribute it   ////
2138 
//// and/or modify it under the terms of the GNU Lesser General   ////
2139 
//// Public License as published by the Free Software Foundation; ////
2140 
//// either version 2.1 of the License, or (at your option) any   ////
2141 
//// later version.                                               ////
2142 
////                                                              ////
2143 
//// This source is distributed in the hope that it will be       ////
2144 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2145 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2146 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2147 
//// details.                                                     ////
2148 
////                                                              ////
2149 
//// You should have received a copy of the GNU Lesser General    ////
2150 
//// Public License along with this source; if not, download it   ////
2151 
//// from http://www.opencores.org/lgpl.shtml                     ////
2152 
////                                                              ////
2153 
//////////////////////////////////////////////////////////////////////
2154 
 
2155 
// binary counter
2156 
 
2157 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
2158 
module `BASE`MODULE (
2159 
`undef MODULE
2160 
 cke, rew, level1, rst, clk);
2161 
 
2162 6 unneback 
   parameter length = 4;
2163 
   input cke;
2164 
   input rew;
2165 
   output reg level1;
2166 
   input rst;
2167 
   input clk;
2168 
 
2169 
   parameter clear_value = 0;
2170 
   parameter set_value = 1;
2171 
   parameter wrap_value = 1;
2172 
   parameter level1_value = 15;
2173 
 
2174 29 unneback 
   wire clear;
2175 30 unneback 
   assign clear = 1'b0;
2176 6 unneback 
   reg  [length:1] qi;
2177 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2178 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2179 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2180 
   assign q_next = rew ? q_next_rew : q_next_fw;
2181 
 
2182 
   always @ (posedge clk or posedge rst)
2183 
     if (rst)
2184 
       qi <= {length{1'b0}};
2185 
     else
2186 
     if (cke)
2187 
       qi <= q_next;
2188 
 
2189 
 
2190 
 
2191 
    always @ (posedge clk or posedge rst)
2192 
    if (rst)
2193 
        level1 <= 1'b0;
2194 
    else
2195 
    if (cke)
2196 29 unneback 
    if (clear)
2197 
        level1 <= 1'b0;
2198 
    else if (q_next == level1_value)
2199 6 unneback 
        level1 <= 1'b1;
2200 
    else if (qi == level1_value & rew)
2201 
        level1 <= 1'b0;
2202 
endmodule
2203 40 unneback 
`endif
2204 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2205 6 unneback 
//////////////////////////////////////////////////////////////////////
2206 
////                                                              ////
2207 
////  Versatile counter                                           ////
2208 
////                                                              ////
2209 
////  Description                                                 ////
2210 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2211 
////  counter                                                     ////
2212 
////                                                              ////
2213 
////  To Do:                                                      ////
2214 
////   - add LFSR with more taps                                  ////
2215 
////                                                              ////
2216 
////  Author(s):                                                  ////
2217 
////      - Michael Unneback, unneback@opencores.org              ////
2218 
////        ORSoC AB                                              ////
2219 
////                                                              ////
2220 
//////////////////////////////////////////////////////////////////////
2221 
////                                                              ////
2222 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2223 
////                                                              ////
2224 
//// This source file may be used and distributed without         ////
2225 
//// restriction provided that this copyright statement is not    ////
2226 
//// removed from the file and that any derivative work contains  ////
2227 
//// the original copyright notice and the associated disclaimer. ////
2228 
////                                                              ////
2229 
//// This source file is free software; you can redistribute it   ////
2230 
//// and/or modify it under the terms of the GNU Lesser General   ////
2231 
//// Public License as published by the Free Software Foundation; ////
2232 
//// either version 2.1 of the License, or (at your option) any   ////
2233 
//// later version.                                               ////
2234 
////                                                              ////
2235 
//// This source is distributed in the hope that it will be       ////
2236 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2237 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2238 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2239 
//// details.                                                     ////
2240 
////                                                              ////
2241 
//// You should have received a copy of the GNU Lesser General    ////
2242 
//// Public License along with this source; if not, download it   ////
2243 
//// from http://www.opencores.org/lgpl.shtml                     ////
2244 
////                                                              ////
2245 
//////////////////////////////////////////////////////////////////////
2246 
 
2247 25 unneback 
// binary counter
2248 
 
2249 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2250 
module `BASE`MODULE (
2251 
`undef MODULE
2252 
 cke, rew, zq, level1, rst, clk);
2253 
 
2254 25 unneback 
   parameter length = 4;
2255 
   input cke;
2256 
   input rew;
2257 
   output reg zq;
2258 
   output reg level1;
2259 
   input rst;
2260 
   input clk;
2261 
 
2262 
   parameter clear_value = 0;
2263 
   parameter set_value = 1;
2264 
   parameter wrap_value = 1;
2265 
   parameter level1_value = 15;
2266 
 
2267 29 unneback 
   wire clear;
2268 30 unneback 
   assign clear = 1'b0;
2269 25 unneback 
   reg  [length:1] qi;
2270 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2271 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2272 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2273 
   assign q_next = rew ? q_next_rew : q_next_fw;
2274 
 
2275 
   always @ (posedge clk or posedge rst)
2276 
     if (rst)
2277 
       qi <= {length{1'b0}};
2278 
     else
2279 
     if (cke)
2280 
       qi <= q_next;
2281 
 
2282 
 
2283 
 
2284 
   always @ (posedge clk or posedge rst)
2285 
     if (rst)
2286 
       zq <= 1'b1;
2287 
     else
2288 
     if (cke)
2289 
       zq <= q_next == {length{1'b0}};
2290 
 
2291 
    always @ (posedge clk or posedge rst)
2292 
    if (rst)
2293 
        level1 <= 1'b0;
2294 
    else
2295 
    if (cke)
2296 29 unneback 
    if (clear)
2297 
        level1 <= 1'b0;
2298 
    else if (q_next == level1_value)
2299 25 unneback 
        level1 <= 1'b1;
2300 
    else if (qi == level1_value & rew)
2301 
        level1 <= 1'b0;
2302 
endmodule
2303 40 unneback 
`endif
2304 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2305 25 unneback 
//////////////////////////////////////////////////////////////////////
2306 
////                                                              ////
2307 
////  Versatile counter                                           ////
2308 
////                                                              ////
2309 
////  Description                                                 ////
2310 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2311 
////  counter                                                     ////
2312 
////                                                              ////
2313 
////  To Do:                                                      ////
2314 
////   - add LFSR with more taps                                  ////
2315 
////                                                              ////
2316 
////  Author(s):                                                  ////
2317 
////      - Michael Unneback, unneback@opencores.org              ////
2318 
////        ORSoC AB                                              ////
2319 
////                                                              ////
2320 
//////////////////////////////////////////////////////////////////////
2321 
////                                                              ////
2322 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2323 
////                                                              ////
2324 
//// This source file may be used and distributed without         ////
2325 
//// restriction provided that this copyright statement is not    ////
2326 
//// removed from the file and that any derivative work contains  ////
2327 
//// the original copyright notice and the associated disclaimer. ////
2328 
////                                                              ////
2329 
//// This source file is free software; you can redistribute it   ////
2330 
//// and/or modify it under the terms of the GNU Lesser General   ////
2331 
//// Public License as published by the Free Software Foundation; ////
2332 
//// either version 2.1 of the License, or (at your option) any   ////
2333 
//// later version.                                               ////
2334 
////                                                              ////
2335 
//// This source is distributed in the hope that it will be       ////
2336 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2337 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2338 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2339 
//// details.                                                     ////
2340 
////                                                              ////
2341 
//// You should have received a copy of the GNU Lesser General    ////
2342 
//// Public License along with this source; if not, download it   ////
2343 
//// from http://www.opencores.org/lgpl.shtml                     ////
2344 
////                                                              ////
2345 
//////////////////////////////////////////////////////////////////////
2346 
 
2347 
// binary counter
2348 
 
2349 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2350 
module `BASE`MODULE (
2351 
`undef MODULE
2352 
 cke, rew, q, zq, level1, rst, clk);
2353 
 
2354 25 unneback 
   parameter length = 4;
2355 
   input cke;
2356 
   input rew;
2357 
   output [length:1] q;
2358 
   output reg zq;
2359 
   output reg level1;
2360 
   input rst;
2361 
   input clk;
2362 
 
2363 
   parameter clear_value = 0;
2364 
   parameter set_value = 1;
2365 
   parameter wrap_value = 1;
2366 
   parameter level1_value = 15;
2367 
 
2368 29 unneback 
   wire clear;
2369 30 unneback 
   assign clear = 1'b0;
2370 25 unneback 
   reg  [length:1] qi;
2371 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2372 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2373 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2374 
   assign q_next = rew ? q_next_rew : q_next_fw;
2375 
 
2376 
   always @ (posedge clk or posedge rst)
2377 
     if (rst)
2378 
       qi <= {length{1'b0}};
2379 
     else
2380 
     if (cke)
2381 
       qi <= q_next;
2382 
 
2383 
   assign q = qi;
2384 
 
2385 
 
2386 
   always @ (posedge clk or posedge rst)
2387 
     if (rst)
2388 
       zq <= 1'b1;
2389 
     else
2390 
     if (cke)
2391 
       zq <= q_next == {length{1'b0}};
2392 
 
2393 
    always @ (posedge clk or posedge rst)
2394 
    if (rst)
2395 
        level1 <= 1'b0;
2396 
    else
2397 
    if (cke)
2398 29 unneback 
    if (clear)
2399 
        level1 <= 1'b0;
2400 
    else if (q_next == level1_value)
2401 25 unneback 
        level1 <= 1'b1;
2402 
    else if (qi == level1_value & rew)
2403 
        level1 <= 1'b0;
2404 
endmodule
2405 40 unneback 
`endif
2406 
`ifdef CNT_LFSR_ZQ
2407 25 unneback 
//////////////////////////////////////////////////////////////////////
2408 
////                                                              ////
2409 
////  Versatile counter                                           ////
2410 
////                                                              ////
2411 
////  Description                                                 ////
2412 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2413 
////  counter                                                     ////
2414 
////                                                              ////
2415 
////  To Do:                                                      ////
2416 
////   - add LFSR with more taps                                  ////
2417 
////                                                              ////
2418 
////  Author(s):                                                  ////
2419 
////      - Michael Unneback, unneback@opencores.org              ////
2420 
////        ORSoC AB                                              ////
2421 
////                                                              ////
2422 
//////////////////////////////////////////////////////////////////////
2423 
////                                                              ////
2424 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2425 
////                                                              ////
2426 
//// This source file may be used and distributed without         ////
2427 
//// restriction provided that this copyright statement is not    ////
2428 
//// removed from the file and that any derivative work contains  ////
2429 
//// the original copyright notice and the associated disclaimer. ////
2430 
////                                                              ////
2431 
//// This source file is free software; you can redistribute it   ////
2432 
//// and/or modify it under the terms of the GNU Lesser General   ////
2433 
//// Public License as published by the Free Software Foundation; ////
2434 
//// either version 2.1 of the License, or (at your option) any   ////
2435 
//// later version.                                               ////
2436 
////                                                              ////
2437 
//// This source is distributed in the hope that it will be       ////
2438 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2439 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2440 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2441 
//// details.                                                     ////
2442 
////                                                              ////
2443 
//// You should have received a copy of the GNU Lesser General    ////
2444 
//// Public License along with this source; if not, download it   ////
2445 
//// from http://www.opencores.org/lgpl.shtml                     ////
2446 
////                                                              ////
2447 
//////////////////////////////////////////////////////////////////////
2448 
 
2449 6 unneback 
// LFSR counter
2450 
 
2451 40 unneback 
`define MODULE cnt_lfsr_zq
2452 
module `BASE`MODULE (
2453 
`undef MODULE
2454 
 zq, rst, clk);
2455 
 
2456 6 unneback 
   parameter length = 4;
2457 
   output reg zq;
2458 
   input rst;
2459 
   input clk;
2460 
 
2461 
   parameter clear_value = 0;
2462 
   parameter set_value = 1;
2463 
   parameter wrap_value = 8;
2464 
   parameter level1_value = 15;
2465 
 
2466 
   reg  [length:1] qi;
2467 
   reg lfsr_fb;
2468 
   wire [length:1] q_next;
2469 
   reg [32:1] polynom;
2470 
   integer i;
2471 
 
2472 
   always @ (qi)
2473 
   begin
2474 
        case (length)
2475 
         2: polynom = 32'b11;                               // 0x3
2476 
         3: polynom = 32'b110;                              // 0x6
2477 
         4: polynom = 32'b1100;                             // 0xC
2478 
         5: polynom = 32'b10100;                            // 0x14
2479 
         6: polynom = 32'b110000;                           // 0x30
2480 
         7: polynom = 32'b1100000;                          // 0x60
2481 
         8: polynom = 32'b10111000;                         // 0xb8
2482 
         9: polynom = 32'b100010000;                        // 0x110
2483 
        10: polynom = 32'b1001000000;                       // 0x240
2484 
        11: polynom = 32'b10100000000;                      // 0x500
2485 
        12: polynom = 32'b100000101001;                     // 0x829
2486 
        13: polynom = 32'b1000000001100;                    // 0x100C
2487 
        14: polynom = 32'b10000000010101;                   // 0x2015
2488 
        15: polynom = 32'b110000000000000;                  // 0x6000
2489 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2490 
        17: polynom = 32'b10010000000000000;                // 0x12000
2491 
        18: polynom = 32'b100000010000000000;               // 0x20400
2492 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2493 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2494 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2495 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2496 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2497 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2498 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2499 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2500 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2501 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2502 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2503 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2504 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2505 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2506 
        default: polynom = 32'b0;
2507 
        endcase
2508 
        lfsr_fb = qi[length];
2509 
        for (i=length-1; i>=1; i=i-1) begin
2510 
            if (polynom[i])
2511 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2512 
        end
2513 
    end
2514 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2515 
 
2516 
   always @ (posedge clk or posedge rst)
2517 
     if (rst)
2518 
       qi <= {length{1'b0}};
2519 
     else
2520 
       qi <= q_next;
2521 
 
2522 
 
2523 
 
2524 
   always @ (posedge clk or posedge rst)
2525 
     if (rst)
2526 
       zq <= 1'b1;
2527 
     else
2528 
       zq <= q_next == {length{1'b0}};
2529 
endmodule
2530 40 unneback 
`endif
2531 75 unneback 
`ifdef CNT_LFSR_CE
2532 
//////////////////////////////////////////////////////////////////////
2533 
////                                                              ////
2534 
////  Versatile counter                                           ////
2535 
////                                                              ////
2536 
////  Description                                                 ////
2537 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2538 
////  counter                                                     ////
2539 
////                                                              ////
2540 
////  To Do:                                                      ////
2541 
////   - add LFSR with more taps                                  ////
2542 
////                                                              ////
2543 
////  Author(s):                                                  ////
2544 
////      - Michael Unneback, unneback@opencores.org              ////
2545 
////        ORSoC AB                                              ////
2546 
////                                                              ////
2547 
//////////////////////////////////////////////////////////////////////
2548 
////                                                              ////
2549 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2550 
////                                                              ////
2551 
//// This source file may be used and distributed without         ////
2552 
//// restriction provided that this copyright statement is not    ////
2553 
//// removed from the file and that any derivative work contains  ////
2554 
//// the original copyright notice and the associated disclaimer. ////
2555 
////                                                              ////
2556 
//// This source file is free software; you can redistribute it   ////
2557 
//// and/or modify it under the terms of the GNU Lesser General   ////
2558 
//// Public License as published by the Free Software Foundation; ////
2559 
//// either version 2.1 of the License, or (at your option) any   ////
2560 
//// later version.                                               ////
2561 
////                                                              ////
2562 
//// This source is distributed in the hope that it will be       ////
2563 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2564 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2565 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2566 
//// details.                                                     ////
2567 
////                                                              ////
2568 
//// You should have received a copy of the GNU Lesser General    ////
2569 
//// Public License along with this source; if not, download it   ////
2570 
//// from http://www.opencores.org/lgpl.shtml                     ////
2571 
////                                                              ////
2572 
//////////////////////////////////////////////////////////////////////
2573 
 
2574 
// LFSR counter
2575 
 
2576 
`define MODULE cnt_lfsr_ce
2577 
module `BASE`MODULE (
2578 
`undef MODULE
2579 
 cke, zq, rst, clk);
2580 
 
2581 
   parameter length = 4;
2582 
   input cke;
2583 
   output reg zq;
2584 
   input rst;
2585 
   input clk;
2586 
 
2587 
   parameter clear_value = 0;
2588 
   parameter set_value = 1;
2589 
   parameter wrap_value = 0;
2590 
   parameter level1_value = 15;
2591 
 
2592 
   reg  [length:1] qi;
2593 
   reg lfsr_fb;
2594 
   wire [length:1] q_next;
2595 
   reg [32:1] polynom;
2596 
   integer i;
2597 
 
2598 
   always @ (qi)
2599 
   begin
2600 
        case (length)
2601 
         2: polynom = 32'b11;                               // 0x3
2602 
         3: polynom = 32'b110;                              // 0x6
2603 
         4: polynom = 32'b1100;                             // 0xC
2604 
         5: polynom = 32'b10100;                            // 0x14
2605 
         6: polynom = 32'b110000;                           // 0x30
2606 
         7: polynom = 32'b1100000;                          // 0x60
2607 
         8: polynom = 32'b10111000;                         // 0xb8
2608 
         9: polynom = 32'b100010000;                        // 0x110
2609 
        10: polynom = 32'b1001000000;                       // 0x240
2610 
        11: polynom = 32'b10100000000;                      // 0x500
2611 
        12: polynom = 32'b100000101001;                     // 0x829
2612 
        13: polynom = 32'b1000000001100;                    // 0x100C
2613 
        14: polynom = 32'b10000000010101;                   // 0x2015
2614 
        15: polynom = 32'b110000000000000;                  // 0x6000
2615 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2616 
        17: polynom = 32'b10010000000000000;                // 0x12000
2617 
        18: polynom = 32'b100000010000000000;               // 0x20400
2618 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2619 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2620 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2621 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2622 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2623 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2624 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2625 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2626 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2627 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2628 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2629 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2630 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2631 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2632 
        default: polynom = 32'b0;
2633 
        endcase
2634 
        lfsr_fb = qi[length];
2635 
        for (i=length-1; i>=1; i=i-1) begin
2636 
            if (polynom[i])
2637 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2638 
        end
2639 
    end
2640 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2641 
 
2642 
   always @ (posedge clk or posedge rst)
2643 
     if (rst)
2644 
       qi <= {length{1'b0}};
2645 
     else
2646 
     if (cke)
2647 
       qi <= q_next;
2648 
 
2649 
 
2650 
 
2651 
   always @ (posedge clk or posedge rst)
2652 
     if (rst)
2653 
       zq <= 1'b1;
2654 
     else
2655 
     if (cke)
2656 
       zq <= q_next == {length{1'b0}};
2657 
endmodule
2658 
`endif
2659 40 unneback 
`ifdef CNT_LFSR_CE_ZQ
2660 6 unneback 
//////////////////////////////////////////////////////////////////////
2661 
////                                                              ////
2662 
////  Versatile counter                                           ////
2663 
////                                                              ////
2664 
////  Description                                                 ////
2665 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2666 
////  counter                                                     ////
2667 
////                                                              ////
2668 
////  To Do:                                                      ////
2669 
////   - add LFSR with more taps                                  ////
2670 
////                                                              ////
2671 
////  Author(s):                                                  ////
2672 
////      - Michael Unneback, unneback@opencores.org              ////
2673 
////        ORSoC AB                                              ////
2674 
////                                                              ////
2675 
//////////////////////////////////////////////////////////////////////
2676 
////                                                              ////
2677 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2678 
////                                                              ////
2679 
//// This source file may be used and distributed without         ////
2680 
//// restriction provided that this copyright statement is not    ////
2681 
//// removed from the file and that any derivative work contains  ////
2682 
//// the original copyright notice and the associated disclaimer. ////
2683 
////                                                              ////
2684 
//// This source file is free software; you can redistribute it   ////
2685 
//// and/or modify it under the terms of the GNU Lesser General   ////
2686 
//// Public License as published by the Free Software Foundation; ////
2687 
//// either version 2.1 of the License, or (at your option) any   ////
2688 
//// later version.                                               ////
2689 
////                                                              ////
2690 
//// This source is distributed in the hope that it will be       ////
2691 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2692 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2693 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2694 
//// details.                                                     ////
2695 
////                                                              ////
2696 
//// You should have received a copy of the GNU Lesser General    ////
2697 
//// Public License along with this source; if not, download it   ////
2698 
//// from http://www.opencores.org/lgpl.shtml                     ////
2699 
////                                                              ////
2700 
//////////////////////////////////////////////////////////////////////
2701 
 
2702 
// LFSR counter
2703 
 
2704 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2705 
module `BASE`MODULE (
2706 
`undef MODULE
2707 
 cke, zq, rst, clk);
2708 
 
2709 6 unneback 
   parameter length = 4;
2710 
   input cke;
2711 
   output reg zq;
2712 
   input rst;
2713 
   input clk;
2714 
 
2715 
   parameter clear_value = 0;
2716 
   parameter set_value = 1;
2717 
   parameter wrap_value = 8;
2718 
   parameter level1_value = 15;
2719 
 
2720 
   reg  [length:1] qi;
2721 
   reg lfsr_fb;
2722 
   wire [length:1] q_next;
2723 
   reg [32:1] polynom;
2724 
   integer i;
2725 
 
2726 
   always @ (qi)
2727 
   begin
2728 
        case (length)
2729 
         2: polynom = 32'b11;                               // 0x3
2730 
         3: polynom = 32'b110;                              // 0x6
2731 
         4: polynom = 32'b1100;                             // 0xC
2732 
         5: polynom = 32'b10100;                            // 0x14
2733 
         6: polynom = 32'b110000;                           // 0x30
2734 
         7: polynom = 32'b1100000;                          // 0x60
2735 
         8: polynom = 32'b10111000;                         // 0xb8
2736 
         9: polynom = 32'b100010000;                        // 0x110
2737 
        10: polynom = 32'b1001000000;                       // 0x240
2738 
        11: polynom = 32'b10100000000;                      // 0x500
2739 
        12: polynom = 32'b100000101001;                     // 0x829
2740 
        13: polynom = 32'b1000000001100;                    // 0x100C
2741 
        14: polynom = 32'b10000000010101;                   // 0x2015
2742 
        15: polynom = 32'b110000000000000;                  // 0x6000
2743 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2744 
        17: polynom = 32'b10010000000000000;                // 0x12000
2745 
        18: polynom = 32'b100000010000000000;               // 0x20400
2746 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2747 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2748 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2749 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2750 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2751 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2752 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2753 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2754 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2755 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2756 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2757 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2758 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2759 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2760 
        default: polynom = 32'b0;
2761 
        endcase
2762 
        lfsr_fb = qi[length];
2763 
        for (i=length-1; i>=1; i=i-1) begin
2764 
            if (polynom[i])
2765 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2766 
        end
2767 
    end
2768 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2769 
 
2770 
   always @ (posedge clk or posedge rst)
2771 
     if (rst)
2772 
       qi <= {length{1'b0}};
2773 
     else
2774 
     if (cke)
2775 
       qi <= q_next;
2776 
 
2777 
 
2778 
 
2779 
   always @ (posedge clk or posedge rst)
2780 
     if (rst)
2781 
       zq <= 1'b1;
2782 
     else
2783 
     if (cke)
2784 
       zq <= q_next == {length{1'b0}};
2785 
endmodule
2786 40 unneback 
`endif
2787 
`ifdef CNT_LFSR_CE_Q
2788 6 unneback 
//////////////////////////////////////////////////////////////////////
2789 
////                                                              ////
2790 
////  Versatile counter                                           ////
2791 
////                                                              ////
2792 
////  Description                                                 ////
2793 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2794 
////  counter                                                     ////
2795 
////                                                              ////
2796 
////  To Do:                                                      ////
2797 
////   - add LFSR with more taps                                  ////
2798 
////                                                              ////
2799 
////  Author(s):                                                  ////
2800 
////      - Michael Unneback, unneback@opencores.org              ////
2801 
////        ORSoC AB                                              ////
2802 
////                                                              ////
2803 
//////////////////////////////////////////////////////////////////////
2804 
////                                                              ////
2805 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2806 
////                                                              ////
2807 
//// This source file may be used and distributed without         ////
2808 
//// restriction provided that this copyright statement is not    ////
2809 
//// removed from the file and that any derivative work contains  ////
2810 
//// the original copyright notice and the associated disclaimer. ////
2811 
////                                                              ////
2812 
//// This source file is free software; you can redistribute it   ////
2813 
//// and/or modify it under the terms of the GNU Lesser General   ////
2814 
//// Public License as published by the Free Software Foundation; ////
2815 
//// either version 2.1 of the License, or (at your option) any   ////
2816 
//// later version.                                               ////
2817 
////                                                              ////
2818