OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 101

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 98 unneback 
`ifdef ACTEL
14 
    // ACTEL FPGA should not use logic to handle rw collision
15 
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16 
`else
17 
    `define SYN_NO_RW_CHECK
18 
`endif
19 
 
20 40 unneback 
`ifdef ALL
21 
 
22 
`define GBUF
23 
`define SYNC_RST
24 
`define PLL
25 
 
26 
`define MULTS
27 
`define MULTS18X18
28 
`define MULT
29 
`define SHIFT_UNIT_32
30 
`define LOGIC_UNIT
31 
 
32 
`define CNT_SHREG_WRAP
33 
`define CNT_SHREG_CE_WRAP
34 
`define CNT_SHREG_CE_CLEAR
35 
`define CNT_SHREG_CE_CLEAR_WRAP
36 
 
37 
`define MUX_ANDOR
38 
`define MUX2_ANDOR
39 
`define MUX3_ANDOR
40 
`define MUX4_ANDOR
41 
`define MUX5_ANDOR
42 
`define MUX6_ANDOR
43 43 unneback 
`define PARITY
44 40 unneback 
 
45 
`define ROM_INIT
46 
`define RAM
47 
`define RAM_BE
48 
`define DPRAM_1R1W
49 
`define DPRAM_2R1W
50 100 unneback 
`define DPRAM_1R2W
51 40 unneback 
`define DPRAM_2R2W
52 75 unneback 
`define DPRAM_BE_2R2W
53 40 unneback 
`define FIFO_1R1W_FILL_LEVEL_SYNC
54 
`define FIFO_2R2W_SYNC_SIMPLEX
55 
`define FIFO_CMP_ASYNC
56 
`define FIFO_1R1W_ASYNC
57 
`define FIFO_2R2W_ASYNC
58 
`define FIFO_2R2W_ASYNC_SIMPLEX
59 48 unneback 
`define REG_FILE
60 40 unneback 
 
61 
`define DFF
62 
`define DFF_ARRAY
63 
`define DFF_CE
64 
`define DFF_CE_CLEAR
65 
`define DF_CE_SET
66 
`define SPR
67 
`define SRP
68 
`define DFF_SR
69 
`define LATCH
70 
`define SHREG
71 
`define SHREG_CE
72 
`define DELAY
73 
`define DELAY_EMPTYFLAG
74 94 unneback 
`define PULSE2TOGGLE
75 
`define TOGGLE2PULSE
76 
`define SYNCHRONIZER
77 
`define CDC
78 40 unneback 
 
79 75 unneback 
`define WB3AVALON_BRIDGE
80 40 unneback 
`define WB3WB3_BRIDGE
81 
`define WB3_ARBITER_TYPE1
82 83 unneback 
`define WB_ADR_INC
83 101 unneback 
`define WB_RAM
84 48 unneback 
`define WB_B4_ROM
85 40 unneback 
`define WB_BOOT_ROM
86 
`define WB_DPRAM
87 101 unneback 
`define WB_CACHE
88 40 unneback 
 
89 44 unneback 
`define IO_DFF_OE
90 
`define O_DFF
91 
 
92 40 unneback 
`endif
93 
 
94 
`ifdef PLL
95 
`ifndef SYNC_RST
96 
`define SYNC_RST
97 
`endif
98 
`endif
99 
 
100 
`ifdef SYNC_RST
101 
`ifndef GBUF
102 
`define GBUF
103 
`endif
104 
`endif
105 
 
106 92 unneback 
`ifdef WB_B3_DPRAM
107 
`ifndef WB_ADR_INC
108 
`define WB_ADR_INC
109 40 unneback 
`endif
110 92 unneback 
`ifndef DPRAM_BE_2R2W
111 
`define DPRAM_BE_2R2W
112 40 unneback 
`endif
113 
`endif
114 
 
115 101 unneback 
`ifdef WB_RAM
116 83 unneback 
`ifndef WB_ADR_INC
117 
`define WB_ADR_INC
118 62 unneback 
`endif
119 
`ifndef RAM_BE
120 
`define RAM_BE
121 
`endif
122 
`endif
123 
 
124 40 unneback 
`ifdef WB3_ARBITER_TYPE1
125 42 unneback 
`ifndef SPR
126 
`define SPR
127 
`endif
128 40 unneback 
`ifndef MUX_ANDOR
129 
`define MUX_ANDOR
130 
`endif
131 
`endif
132 
 
133 76 unneback 
`ifdef WB3AVALON_BRIDGE
134 
`ifndef WB3WB3_BRIDGE
135 
`define WB3WB3_BRIDGE
136 
`endif
137 
`endif
138 
 
139 40 unneback 
`ifdef WB3WB3_BRIDGE
140 
`ifndef CNT_SHREG_CE_CLEAR
141 
`define CNT_SHREG_CE_CLEAR
142 
`endif
143 
`ifndef DFF
144 
`define DFF
145 
`endif
146 
`ifndef DFF_CE
147 
`define DFF_CE
148 
`endif
149 
`ifndef CNT_SHREG_CE_CLEAR
150 
`define CNT_SHREG_CE_CLEAR
151 
`endif
152 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
153 
`define FIFO_2R2W_ASYNC_SIMPLEX
154 
`endif
155 
`endif
156 
 
157 101 unneback 
`ifdef WB_CACHE
158 100 unneback 
`ifndef RAM
159 
`define RAM
160 
`endif
161 
`ifndef WB_ADR_INC
162 
`define WB_ADR_INC
163 
`endif
164 
`ifndef DPRAM_1R1W
165 
`define DPRAM_1R1W
166 
`endif
167 
`ifndef DPRAM_1R2W
168 
`define DPRAM_1R2W
169 
`endif
170 
`ifndef DPRAM_BE_2R2W
171 
`define DPRAM_BE_2R2W
172 
`endif
173 
`ifndef CDC
174 
`define CDC
175 
`endif
176 
`endif
177 97 unneback 
 
178 40 unneback 
`ifdef MULTS18X18
179 
`ifndef MULTS
180 
`define MULTS
181 
`endif
182 
`endif
183 
 
184 
`ifdef SHIFT_UNIT_32
185 
`ifndef MULTS
186 
`define MULTS
187 
`endif
188 
`endif
189 
 
190 
`ifdef MUX2_ANDOR
191 
`ifndef MUX_ANDOR
192 
`define MUX_ANDOR
193 
`endif
194 
`endif
195 
 
196 
`ifdef MUX3_ANDOR
197 
`ifndef MUX_ANDOR
198 
`define MUX_ANDOR
199 
`endif
200 
`endif
201 
 
202 
`ifdef MUX4_ANDOR
203 
`ifndef MUX_ANDOR
204 
`define MUX_ANDOR
205 
`endif
206 
`endif
207 
 
208 
`ifdef MUX5_ANDOR
209 
`ifndef MUX_ANDOR
210 
`define MUX_ANDOR
211 
`endif
212 
`endif
213 
 
214 
`ifdef MUX6_ANDOR
215 
`ifndef MUX_ANDOR
216 
`define MUX_ANDOR
217 
`endif
218 
`endif
219 
 
220 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
221 
`ifndef CNT_BIN_CE
222 
`define CNT_BIN_CE
223 
`endif
224 
`ifndef DPRAM_1R1W
225 
`define DPRAM_1R1W
226 
`endif
227 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
228 
`define CNT_BIN_CE_REW_Q_ZQ_L1
229 
`endif
230 
`endif
231 
 
232 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
233 
`ifndef CNT_LFSR_CE
234 
`define CNT_LFSR_CE
235 
`endif
236 
`ifndef DPRAM_2R2W
237 
`define DPRAM_2R2W
238 
`endif
239 
`ifndef CNT_BIN_CE_REW_ZQ_L1
240 
`define CNT_BIN_CE_REW_ZQ_L1
241 
`endif
242 
`endif
243 
 
244 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
245 
`ifndef CNT_GRAY_CE_BIN
246 
`define CNT_GRAY_CE_BIN
247 
`endif
248 
`ifndef DPRAM_2R2W
249 
`define DPRAM_2R2W
250 
`endif
251 
`ifndef FIFO_CMP_ASYNC
252 
`define FIFO_CMP_ASYNC
253 
`endif
254 
`endif
255 
 
256 
`ifdef FIFO_2R2W_ASYNC
257 
`ifndef FIFO_1R1W_ASYNC
258 
`define FIFO_1R1W_ASYNC
259 
`endif
260 
`endif
261 
 
262 
`ifdef FIFO_1R1W_ASYNC
263 
`ifndef CNT_GRAY_CE_BIN
264 
`define CNT_GRAY_CE_BIN
265 
`endif
266 
`ifndef DPRAM_1R1W
267 
`define DPRAM_1R1W
268 
`endif
269 
`ifndef FIFO_CMP_ASYNC
270 
`define FIFO_CMP_ASYNC
271 
`endif
272 
`endif
273 
 
274 
`ifdef FIFO_CMP_ASYNC
275 
`ifndef DFF_SR
276 
`define DFF_SR
277 
`endif
278 
`ifndef DFF
279 
`define DFF
280 
`endif
281 
`endif
282 48 unneback 
 
283 
`ifdef REG_FILE
284 
`ifndef DPRAM_1R1W
285 
`define DPRAM_1R1W
286 
`endif
287 
`endif
288 97 unneback 
 
289 98 unneback 
`ifdef CDC
290 
`ifndef PULSE2TOGGLE
291 
`define PULSE2TOGGLE
292 
`endif
293 
`ifndef TOGGLE2PULSE
294 
`define TOGGLE2PULSE
295 
`endif
296 
`ifndef SYNCHRONIZER
297 
`define SYNCHRONIZER
298 
`endif
299 
`endif
300 
 
301 97 unneback 
// size to width
302 100 unneback 
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
303 62 unneback 
//////////////////////////////////////////////////////////////////////
304 6 unneback 
////                                                              ////
305 
////  Versatile library, clock and reset                          ////
306 
////                                                              ////
307 
////  Description                                                 ////
308 
////  Logic related to clock and reset                            ////
309 
////                                                              ////
310 
////                                                              ////
311 
////  To Do:                                                      ////
312 
////   - add more different registers                             ////
313 
////                                                              ////
314 
////  Author(s):                                                  ////
315 
////      - Michael Unneback, unneback@opencores.org              ////
316 
////        ORSoC AB                                              ////
317 
////                                                              ////
318 
//////////////////////////////////////////////////////////////////////
319 
////                                                              ////
320 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
321 
////                                                              ////
322 
//// This source file may be used and distributed without         ////
323 
//// restriction provided that this copyright statement is not    ////
324 
//// removed from the file and that any derivative work contains  ////
325 
//// the original copyright notice and the associated disclaimer. ////
326 
////                                                              ////
327 
//// This source file is free software; you can redistribute it   ////
328 
//// and/or modify it under the terms of the GNU Lesser General   ////
329 
//// Public License as published by the Free Software Foundation; ////
330 
//// either version 2.1 of the License, or (at your option) any   ////
331 
//// later version.                                               ////
332 
////                                                              ////
333 
//// This source is distributed in the hope that it will be       ////
334 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
335 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
336 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
337 
//// details.                                                     ////
338 
////                                                              ////
339 
//// You should have received a copy of the GNU Lesser General    ////
340 
//// Public License along with this source; if not, download it   ////
341 
//// from http://www.opencores.org/lgpl.shtml                     ////
342 
////                                                              ////
343 
//////////////////////////////////////////////////////////////////////
344 
 
345 48 unneback 
`ifdef ACTEL
346 
`ifdef GBUF
347 
`timescale 1 ns/100 ps
348 6 unneback 
// Global buffer
349 
// usage:
350 
// use to enable global buffers for high fan out signals such as clock and reset
351 
// Version: 8.4 8.4.0.33
352 
module gbuf(GL,CLK);
353 
output GL;
354 
input  CLK;
355 
 
356 
    wire GND;
357 
 
358 
    GND GND_1_net(.Y(GND));
359 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
360 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
361 
 
362 
endmodule
363 
`timescale 1 ns/1 ns
364 40 unneback 
`define MODULE gbuf
365 
module `BASE`MODULE ( i, o);
366 
`undef MODULE
367 6 unneback 
input i;
368 
output o;
369 
`ifdef SIM_GBUF
370 
assign o=i;
371 
`else
372 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
373 
`endif
374 
endmodule
375 40 unneback 
`endif
376 33 unneback 
 
377 6 unneback 
`else
378 33 unneback 
 
379 40 unneback 
`ifdef ALTERA
380 
`ifdef GBUF
381 21 unneback 
//altera
382 40 unneback 
`define MODULE gbuf
383 
module `BASE`MODULE ( i, o);
384 
`undef MODULE
385 33 unneback 
input i;
386 
output o;
387 
assign o = i;
388 
endmodule
389 40 unneback 
`endif
390 33 unneback 
 
391 6 unneback 
`else
392 
 
393 40 unneback 
`ifdef GBUF
394 6 unneback 
`timescale 1 ns/100 ps
395 40 unneback 
`define MODULE
396 
module `BASE`MODULE ( i, o);
397 
`undef MODULE
398 6 unneback 
input i;
399 
output o;
400 
assign o = i;
401 
endmodule
402 40 unneback 
`endif
403 6 unneback 
`endif // ALTERA
404 
`endif //ACTEL
405 
 
406 40 unneback 
`ifdef SYNC_RST
407 6 unneback 
// sync reset
408 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
409 6 unneback 
// output active high global reset sync with two DFFs
410 
`timescale 1 ns/100 ps
411 40 unneback 
`define MODULE sync_rst
412 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
413 
`undef MODULE
414 6 unneback 
input rst_n_i, clk;
415 
output rst_o;
416 18 unneback 
reg [1:0] tmp;
417 6 unneback 
always @ (posedge clk or negedge rst_n_i)
418 
if (!rst_n_i)
419 17 unneback 
        tmp <= 2'b11;
420 6 unneback 
else
421 33 unneback 
        tmp <= {1'b0,tmp[1]};
422 40 unneback 
`define MODULE gbuf
423 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
424 
`undef MODULE
425 6 unneback 
endmodule
426 40 unneback 
`endif
427 6 unneback 
 
428 40 unneback 
`ifdef PLL
429 6 unneback 
// vl_pll
430 
`ifdef ACTEL
431 32 unneback 
///////////////////////////////////////////////////////////////////////////////
432 17 unneback 
`timescale 1 ps/1 ps
433 40 unneback 
`define MODULE pll
434 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
435 
`undef MODULE
436 6 unneback 
parameter index = 0;
437 
parameter number_of_clk = 1;
438 17 unneback 
parameter period_time_0 = 20000;
439 
parameter period_time_1 = 20000;
440 
parameter period_time_2 = 20000;
441 
parameter lock_delay = 2000000;
442 6 unneback 
input clk_i, rst_n_i;
443 
output lock;
444 
output reg [0:number_of_clk-1] clk_o;
445 
output [0:number_of_clk-1] rst_o;
446 
 
447 
`ifdef SIM_PLL
448 
 
449 
always
450 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
451 
 
452 
generate if (number_of_clk > 1)
453 
always
454 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
455 
endgenerate
456 
 
457 
generate if (number_of_clk > 2)
458 
always
459 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
460 
endgenerate
461 
 
462 
genvar i;
463 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
464 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
465 
end
466 
endgenerate
467 
 
468 
assign #lock_delay lock = rst_n_i;
469 
 
470 
endmodule
471 
`else
472 
generate if (number_of_clk==1 & index==0) begin
473 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
474 
end
475 
endgenerate // index==0
476 
generate if (number_of_clk==1 & index==1) begin
477 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
478 
end
479 
endgenerate // index==1
480 
generate if (number_of_clk==1 & index==2) begin
481 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
482 
end
483 
endgenerate // index==2
484 
generate if (number_of_clk==1 & index==3) begin
485 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
486 
end
487 
endgenerate // index==0
488 
 
489 
generate if (number_of_clk==2 & index==0) begin
490 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
491 
end
492 
endgenerate // index==0
493 
generate if (number_of_clk==2 & index==1) begin
494 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
495 
end
496 
endgenerate // index==1
497 
generate if (number_of_clk==2 & index==2) begin
498 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
499 
end
500 
endgenerate // index==2
501 
generate if (number_of_clk==2 & index==3) begin
502 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
503 
end
504 
endgenerate // index==0
505 
 
506 
generate if (number_of_clk==3 & index==0) begin
507 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
508 
end
509 
endgenerate // index==0
510 
generate if (number_of_clk==3 & index==1) begin
511 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
512 
end
513 
endgenerate // index==1
514 
generate if (number_of_clk==3 & index==2) begin
515 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
516 
end
517 
endgenerate // index==2
518 
generate if (number_of_clk==3 & index==3) begin
519 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
520 
end
521 
endgenerate // index==0
522 
 
523 
genvar i;
524 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
525 40 unneback 
`define MODULE sync_rst
526 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
527 
`undef MODULE
528 6 unneback 
end
529 
endgenerate
530 
endmodule
531 
`endif
532 32 unneback 
///////////////////////////////////////////////////////////////////////////////
533 6 unneback 
 
534 
`else
535 
 
536 32 unneback 
///////////////////////////////////////////////////////////////////////////////
537 6 unneback 
`ifdef ALTERA
538 
 
539 32 unneback 
`timescale 1 ps/1 ps
540 40 unneback 
`define MODULE pll
541 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
542 
`undef MODULE
543 32 unneback 
parameter index = 0;
544 
parameter number_of_clk = 1;
545 
parameter period_time_0 = 20000;
546 
parameter period_time_1 = 20000;
547 
parameter period_time_2 = 20000;
548 
parameter period_time_3 = 20000;
549 
parameter period_time_4 = 20000;
550 
parameter lock_delay = 2000000;
551 
input clk_i, rst_n_i;
552 
output lock;
553 
output reg [0:number_of_clk-1] clk_o;
554 
output [0:number_of_clk-1] rst_o;
555 
 
556 
`ifdef SIM_PLL
557 
 
558 
always
559 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
560 
 
561 
generate if (number_of_clk > 1)
562 
always
563 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
564 
endgenerate
565 
 
566 
generate if (number_of_clk > 2)
567 
always
568 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
569 
endgenerate
570 
 
571 33 unneback 
generate if (number_of_clk > 3)
572 32 unneback 
always
573 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
574 
endgenerate
575 
 
576 33 unneback 
generate if (number_of_clk > 4)
577 32 unneback 
always
578 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
579 
endgenerate
580 
 
581 
genvar i;
582 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
583 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
584 
end
585 
endgenerate
586 
 
587 33 unneback 
//assign #lock_delay lock = rst_n_i;
588 
assign lock = rst_n_i;
589 32 unneback 
 
590 
endmodule
591 6 unneback 
`else
592 
 
593 33 unneback 
`ifdef VL_PLL0
594 
`ifdef VL_PLL0_CLK1
595 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
596 
`endif
597 
`ifdef VL_PLL0_CLK2
598 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
599 
`endif
600 
`ifdef VL_PLL0_CLK3
601 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
602 
`endif
603 
`ifdef VL_PLL0_CLK4
604 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
605 
`endif
606 
`ifdef VL_PLL0_CLK5
607 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
608 
`endif
609 
`endif
610 32 unneback 
 
611 33 unneback 
`ifdef VL_PLL1
612 
`ifdef VL_PLL1_CLK1
613 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
614 
`endif
615 
`ifdef VL_PLL1_CLK2
616 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
617 
`endif
618 
`ifdef VL_PLL1_CLK3
619 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
620 
`endif
621 
`ifdef VL_PLL1_CLK4
622 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
623 
`endif
624 
`ifdef VL_PLL1_CLK5
625 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
626 
`endif
627 
`endif
628 32 unneback 
 
629 33 unneback 
`ifdef VL_PLL2
630 
`ifdef VL_PLL2_CLK1
631 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
632 
`endif
633 
`ifdef VL_PLL2_CLK2
634 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
635 
`endif
636 
`ifdef VL_PLL2_CLK3
637 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
638 
`endif
639 
`ifdef VL_PLL2_CLK4
640 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
641 
`endif
642 
`ifdef VL_PLL2_CLK5
643 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
644 
`endif
645 
`endif
646 32 unneback 
 
647 33 unneback 
`ifdef VL_PLL3
648 
`ifdef VL_PLL3_CLK1
649 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
650 
`endif
651 
`ifdef VL_PLL3_CLK2
652 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
653 
`endif
654 
`ifdef VL_PLL3_CLK3
655 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
656 
`endif
657 
`ifdef VL_PLL3_CLK4
658 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
659 
`endif
660 
`ifdef VL_PLL3_CLK5
661 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
662 
`endif
663 
`endif
664 32 unneback 
 
665 
genvar i;
666 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
667 40 unneback 
`define MODULE sync_rst
668 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
669 
`undef MODULE
670 32 unneback 
end
671 
endgenerate
672 
endmodule
673 
`endif
674 
///////////////////////////////////////////////////////////////////////////////
675 
 
676 
`else
677 
 
678 6 unneback 
// generic PLL
679 17 unneback 
`timescale 1 ps/1 ps
680 40 unneback 
`define MODULE pll
681 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
682 
`undef MODULE
683 6 unneback 
parameter index = 0;
684 
parameter number_of_clk = 1;
685 17 unneback 
parameter period_time_0 = 20000;
686 
parameter period_time_1 = 20000;
687 
parameter period_time_2 = 20000;
688 6 unneback 
parameter lock_delay = 2000;
689 
input clk_i, rst_n_i;
690 
output lock;
691 
output reg [0:number_of_clk-1] clk_o;
692 
output [0:number_of_clk-1] rst_o;
693 
 
694 
always
695 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
696 
 
697 
generate if (number_of_clk > 1)
698 
always
699 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
700 
endgenerate
701 
 
702 
generate if (number_of_clk > 2)
703 
always
704 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
705 
endgenerate
706 
 
707 
genvar i;
708 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
709 40 unneback 
`define MODULE sync_rst
710 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
711 
`undef MODULE
712 6 unneback 
end
713 
endgenerate
714 
 
715 
assign #lock_delay lock = rst_n_i;
716 
 
717 
endmodule
718 
 
719 
`endif //altera
720 17 unneback 
`endif //actel
721 40 unneback 
`undef MODULE
722 
`endif//////////////////////////////////////////////////////////////////////
723 6 unneback 
////                                                              ////
724 
////  Versatile library, registers                                ////
725 
////                                                              ////
726 
////  Description                                                 ////
727 
////  Different type of registers                                 ////
728 
////                                                              ////
729 
////                                                              ////
730 
////  To Do:                                                      ////
731 
////   - add more different registers                             ////
732 
////                                                              ////
733 
////  Author(s):                                                  ////
734 
////      - Michael Unneback, unneback@opencores.org              ////
735 
////        ORSoC AB                                              ////
736 
////                                                              ////
737 
//////////////////////////////////////////////////////////////////////
738 
////                                                              ////
739 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
740 
////                                                              ////
741 
//// This source file may be used and distributed without         ////
742 
//// restriction provided that this copyright statement is not    ////
743 
//// removed from the file and that any derivative work contains  ////
744 
//// the original copyright notice and the associated disclaimer. ////
745 
////                                                              ////
746 
//// This source file is free software; you can redistribute it   ////
747 
//// and/or modify it under the terms of the GNU Lesser General   ////
748 
//// Public License as published by the Free Software Foundation; ////
749 
//// either version 2.1 of the License, or (at your option) any   ////
750 
//// later version.                                               ////
751 
////                                                              ////
752 
//// This source is distributed in the hope that it will be       ////
753 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
754 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
755 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
756 
//// details.                                                     ////
757 
////                                                              ////
758 
//// You should have received a copy of the GNU Lesser General    ////
759 
//// Public License along with this source; if not, download it   ////
760 
//// from http://www.opencores.org/lgpl.shtml                     ////
761 
////                                                              ////
762 
//////////////////////////////////////////////////////////////////////
763 
 
764 40 unneback 
`ifdef DFF
765 
`define MODULE dff
766 
module `BASE`MODULE ( d, q, clk, rst);
767 
`undef MODULE
768 6 unneback 
        parameter width = 1;
769 
        parameter reset_value = 0;
770 
 
771 
        input [width-1:0] d;
772 
        input clk, rst;
773 
        output reg [width-1:0] q;
774 
 
775 
        always @ (posedge clk or posedge rst)
776 
        if (rst)
777 
                q <= reset_value;
778 
        else
779 
                q <= d;
780 
 
781 
endmodule
782 40 unneback 
`endif
783 6 unneback 
 
784 40 unneback 
`ifdef DFF_ARRAY
785 
`define MODULE dff_array
786 
module `BASE`MODULE ( d, q, clk, rst);
787 
`undef MODULE
788 6 unneback 
 
789 
        parameter width = 1;
790 
        parameter depth = 2;
791 
        parameter reset_value = 1'b0;
792 
 
793 
        input [width-1:0] d;
794 
        input clk, rst;
795 
        output [width-1:0] q;
796 
        reg  [0:depth-1] q_tmp [width-1:0];
797 
        integer i;
798 
        always @ (posedge clk or posedge rst)
799 
        if (rst) begin
800 
            for (i=0;i<depth;i=i+1)
801 
                q_tmp[i] <= {width{reset_value}};
802 
        end else begin
803 
            q_tmp[0] <= d;
804 
            for (i=1;i<depth;i=i+1)
805 
                q_tmp[i] <= q_tmp[i-1];
806 
        end
807 
 
808 
    assign q = q_tmp[depth-1];
809 
 
810 
endmodule
811 40 unneback 
`endif
812 6 unneback 
 
813 40 unneback 
`ifdef DFF_CE
814 
`define MODULE dff_ce
815 
module `BASE`MODULE ( d, ce, q, clk, rst);
816 
`undef MODULE
817 6 unneback 
 
818 
        parameter width = 1;
819 
        parameter reset_value = 0;
820 
 
821 
        input [width-1:0] d;
822 
        input ce, clk, rst;
823 
        output reg [width-1:0] q;
824 
 
825 
        always @ (posedge clk or posedge rst)
826 
        if (rst)
827 
                q <= reset_value;
828 
        else
829 
                if (ce)
830 
                        q <= d;
831 
 
832 
endmodule
833 40 unneback 
`endif
834 6 unneback 
 
835 40 unneback 
`ifdef DFF_CE_CLEAR
836 
`define MODULE dff_ce_clear
837 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
838 
`undef MODULE
839 8 unneback 
 
840 
        parameter width = 1;
841 
        parameter reset_value = 0;
842 
 
843 
        input [width-1:0] d;
844 10 unneback 
        input ce, clear, clk, rst;
845 8 unneback 
        output reg [width-1:0] q;
846 
 
847 
        always @ (posedge clk or posedge rst)
848 
        if (rst)
849 
            q <= reset_value;
850 
        else
851 
            if (ce)
852 
                if (clear)
853 
                    q <= {width{1'b0}};
854 
                else
855 
                    q <= d;
856 
 
857 
endmodule
858 40 unneback 
`endif
859 8 unneback 
 
860 40 unneback 
`ifdef DF_CE_SET
861 
`define MODULE dff_ce_set
862 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
863 
`undef MODULE
864 24 unneback 
 
865 
        parameter width = 1;
866 
        parameter reset_value = 0;
867 
 
868 
        input [width-1:0] d;
869 
        input ce, set, clk, rst;
870 
        output reg [width-1:0] q;
871 
 
872 
        always @ (posedge clk or posedge rst)
873 
        if (rst)
874 
            q <= reset_value;
875 
        else
876 
            if (ce)
877 
                if (set)
878 
                    q <= {width{1'b1}};
879 
                else
880 
                    q <= d;
881 
 
882 
endmodule
883 40 unneback 
`endif
884 24 unneback 
 
885 40 unneback 
`ifdef SPR
886 
`define MODULE spr
887 
module `BASE`MODULE ( sp, r, q, clk, rst);
888 
`undef MODULE
889 
 
890 64 unneback 
        //parameter width = 1;
891 
        parameter reset_value = 1'b0;
892 29 unneback 
 
893 
        input sp, r;
894 
        output reg q;
895 
        input clk, rst;
896 
 
897 
        always @ (posedge clk or posedge rst)
898 
        if (rst)
899 
            q <= reset_value;
900 
        else
901 
            if (sp)
902 
                q <= 1'b1;
903 
            else if (r)
904 
                q <= 1'b0;
905 
 
906 
endmodule
907 40 unneback 
`endif
908 29 unneback 
 
909 40 unneback 
`ifdef SRP
910 
`define MODULE srp
911 
module `BASE`MODULE ( s, rp, q, clk, rst);
912 
`undef MODULE
913 
 
914 29 unneback 
        parameter width = 1;
915 
        parameter reset_value = 0;
916 
 
917 
        input s, rp;
918 
        output reg q;
919 
        input clk, rst;
920 
 
921 
        always @ (posedge clk or posedge rst)
922 
        if (rst)
923 
            q <= reset_value;
924 
        else
925 
            if (rp)
926 
                q <= 1'b0;
927 
            else if (s)
928 
                q <= 1'b1;
929 
 
930 
endmodule
931 40 unneback 
`endif
932 29 unneback 
 
933 40 unneback 
`ifdef ALTERA
934 29 unneback 
 
935 40 unneback 
`ifdef DFF_SR
936 6 unneback 
// megafunction wizard: %LPM_FF%
937 
// GENERATION: STANDARD
938 
// VERSION: WM1.0
939 
// MODULE: lpm_ff
940 
 
941 
// ============================================================
942 
// File Name: dff_sr.v
943 
// Megafunction Name(s):
944 
//                      lpm_ff
945 
//
946 
// Simulation Library Files(s):
947 
//                      lpm
948 
// ============================================================
949 
// ************************************************************
950 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
951 
//
952 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
953 
// ************************************************************
954 
 
955 
 
956 
//Copyright (C) 1991-2010 Altera Corporation
957 
//Your use of Altera Corporation's design tools, logic functions
958 
//and other software and tools, and its AMPP partner logic
959 
//functions, and any output files from any of the foregoing
960 
//(including device programming or simulation files), and any
961 
//associated documentation or information are expressly subject
962 
//to the terms and conditions of the Altera Program License
963 
//Subscription Agreement, Altera MegaCore Function License
964 
//Agreement, or other applicable license agreement, including,
965 
//without limitation, that your use is for the sole purpose of
966 
//programming logic devices manufactured by Altera and sold by
967 
//Altera or its authorized distributors.  Please refer to the
968 
//applicable agreement for further details.
969 
 
970 
 
971 
// synopsys translate_off
972 
`timescale 1 ps / 1 ps
973 
// synopsys translate_on
974 40 unneback 
`define MODULE dff_sr
975 
module `BASE`MODULE (
976 
`undef MODULE
977 
 
978 6 unneback 
        aclr,
979 
        aset,
980 
        clock,
981 
        data,
982 
        q);
983 
 
984 
        input     aclr;
985 
        input     aset;
986 
        input     clock;
987 
        input     data;
988 
        output    q;
989 
 
990 
        wire [0:0] sub_wire0;
991 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
992 
        wire  q = sub_wire1;
993 
        wire  sub_wire2 = data;
994 
        wire  sub_wire3 = sub_wire2;
995 
 
996 
        lpm_ff  lpm_ff_component (
997 
                                .aclr (aclr),
998 
                                .clock (clock),
999 
                                .data (sub_wire3),
1000 
                                .aset (aset),
1001 
                                .q (sub_wire0)
1002 
                                // synopsys translate_off
1003 
                                ,
1004 
                                .aload (),
1005 
                                .enable (),
1006 
                                .sclr (),
1007 
                                .sload (),
1008 
                                .sset ()
1009 
                                // synopsys translate_on
1010 
                                );
1011 
        defparam
1012 
                lpm_ff_component.lpm_fftype = "DFF",
1013 
                lpm_ff_component.lpm_type = "LPM_FF",
1014 
                lpm_ff_component.lpm_width = 1;
1015 
 
1016 
 
1017 
endmodule
1018 
 
1019 
// ============================================================
1020 
// CNX file retrieval info
1021 
// ============================================================
1022 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1023 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1024 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1025 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1026 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1027 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1028 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1029 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1030 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1031 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1032 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1033 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1034 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1035 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1036 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1037 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1038 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1039 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1040 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1041 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1042 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1043 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1044 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1045 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1046 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1047 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1048 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1049 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1050 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1051 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1052 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1053 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1054 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1055 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1056 
// Retrieval info: LIB_FILE: lpm
1057 40 unneback 
`endif
1058 6 unneback 
 
1059 
`else
1060 
 
1061 40 unneback 
`ifdef DFF_SR
1062 
`define MODULE dff_sr
1063 
module `BASE`MODULE ( aclr, aset, clock, data, q);
1064 
`undef MODULE
1065 6 unneback 
 
1066 
    input         aclr;
1067 
    input         aset;
1068 
    input         clock;
1069 
    input         data;
1070 
    output reg    q;
1071 
 
1072 
   always @ (posedge clock or posedge aclr or posedge aset)
1073 
     if (aclr)
1074 
       q <= 1'b0;
1075 
     else if (aset)
1076 
       q <= 1'b1;
1077 
     else
1078 
       q <= data;
1079 
 
1080 
endmodule
1081 40 unneback 
`endif
1082 6 unneback 
 
1083 
`endif
1084 
 
1085 
// LATCH
1086 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1087 
`ifdef ALTERA
1088 40 unneback 
 
1089 
`ifdef LATCH
1090 
`define MODULE latch
1091 
module `BASE`MODULE ( d, le, q, clk);
1092 
`undef MODULE
1093 6 unneback 
input d, le;
1094 
output q;
1095 
input clk;
1096 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1097 
endmodule
1098 40 unneback 
`endif
1099 
 
1100 6 unneback 
`else
1101 40 unneback 
 
1102 
`ifdef LATCH
1103 
`define MODULE latch
1104 
module `BASE`MODULE ( d, le, q, clk);
1105 
`undef MODULE
1106 6 unneback 
input d, le;
1107 48 unneback 
input clk;
1108 
always @ (le or d)
1109 60 unneback 
if (le)
1110 48 unneback 
    d <= q;
1111 6 unneback 
endmodule
1112 15 unneback 
`endif
1113 
 
1114 40 unneback 
`endif
1115 
 
1116 
`ifdef SHREG
1117 
`define MODULE shreg
1118 
module `BASE`MODULE ( d, q, clk, rst);
1119 
`undef MODULE
1120 
 
1121 17 unneback 
parameter depth = 10;
1122 
input d;
1123 
output q;
1124 
input clk, rst;
1125 
 
1126 
reg [1:depth] dffs;
1127 
 
1128 
always @ (posedge clk or posedge rst)
1129 
if (rst)
1130 
    dffs <= {depth{1'b0}};
1131 
else
1132 
    dffs <= {d,dffs[1:depth-1]};
1133 
assign q = dffs[depth];
1134 
endmodule
1135 40 unneback 
`endif
1136 17 unneback 
 
1137 40 unneback 
`ifdef SHREG_CE
1138 
`define MODULE shreg_ce
1139 
module `BASE`MODULE ( d, ce, q, clk, rst);
1140 
`undef MODULE
1141 17 unneback 
parameter depth = 10;
1142 
input d, ce;
1143 
output q;
1144 
input clk, rst;
1145 
 
1146 
reg [1:depth] dffs;
1147 
 
1148 
always @ (posedge clk or posedge rst)
1149 
if (rst)
1150 
    dffs <= {depth{1'b0}};
1151 
else
1152 
    if (ce)
1153 
        dffs <= {d,dffs[1:depth-1]};
1154 
assign q = dffs[depth];
1155 
endmodule
1156 40 unneback 
`endif
1157 17 unneback 
 
1158 40 unneback 
`ifdef DELAY
1159 
`define MODULE delay
1160 
module `BASE`MODULE ( d, q, clk, rst);
1161 
`undef MODULE
1162 15 unneback 
parameter depth = 10;
1163 
input d;
1164 
output q;
1165 
input clk, rst;
1166 
 
1167 
reg [1:depth] dffs;
1168 
 
1169 
always @ (posedge clk or posedge rst)
1170 
if (rst)
1171 
    dffs <= {depth{1'b0}};
1172 
else
1173 
    dffs <= {d,dffs[1:depth-1]};
1174 
assign q = dffs[depth];
1175 17 unneback 
endmodule
1176 40 unneback 
`endif
1177 17 unneback 
 
1178 40 unneback 
`ifdef DELAY_EMPTYFLAG
1179 
`define MODULE delay_emptyflag
1180 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1181 40 unneback 
`undef MODULE
1182 17 unneback 
parameter depth = 10;
1183 
input d;
1184 
output q, emptyflag;
1185 
input clk, rst;
1186 
 
1187 
reg [1:depth] dffs;
1188 
 
1189 
always @ (posedge clk or posedge rst)
1190 
if (rst)
1191 
    dffs <= {depth{1'b0}};
1192 
else
1193 
    dffs <= {d,dffs[1:depth-1]};
1194 
assign q = dffs[depth];
1195 
assign emptyflag = !(|dffs);
1196 
endmodule
1197 40 unneback 
`endif
1198 75 unneback 
 
1199 94 unneback 
`ifdef PULSE2TOGGLE
1200 98 unneback 
`define MODULE pulse2toggle
1201 
module `BASE`MODULE ( pl, q, clk, rst);
1202 75 unneback 
`undef MODULE
1203 94 unneback 
input pl;
1204 98 unneback 
output reg q;
1205 94 unneback 
input clk, rst;
1206 
always @ (posedge clk or posedge rst)
1207 75 unneback 
if (rst)
1208 94 unneback 
    q <= 1'b0;
1209 75 unneback 
else
1210 94 unneback 
    q <= pl ^ q;
1211 
endmodule
1212 
`endif
1213 75 unneback 
 
1214 94 unneback 
`ifdef TOGGLE2PULSE
1215 98 unneback 
`define MODULE toggle2pulse
1216 94 unneback 
module `BASE`MODULE (d, pl, clk, rst);
1217 97 unneback 
`undef MODULE
1218 94 unneback 
input d;
1219 
output pl;
1220 
input clk, rst;
1221 
reg dff;
1222 
always @ (posedge clk or posedge rst)
1223 
if (rst)
1224 
    dff <= 1'b0;
1225 75 unneback 
else
1226 94 unneback 
    dff <= d;
1227 98 unneback 
assign pl = d ^ dff;
1228 94 unneback 
endmodule
1229 
`endif
1230 75 unneback 
 
1231 94 unneback 
`ifdef SYNCHRONIZER
1232 
`define MODULE synchronizer
1233 
module `BASE`MODULE (d, q, clk, rst);
1234 
`undef MODULE
1235 
input d;
1236 
output reg q;
1237 
output clk, rst;
1238 
reg dff;
1239 
always @ (posedge clk or posedge rst)
1240 
if (rst)
1241 100 unneback 
    {q,dff} <= 2'b00;
1242 75 unneback 
else
1243 100 unneback 
    {q,dff} <= {dff,d};
1244 94 unneback 
endmodule
1245 
`endif
1246 75 unneback 
 
1247 94 unneback 
`ifdef CDC
1248 
`define MODULE cdc
1249 97 unneback 
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1250 94 unneback 
`undef MODULE
1251 
input start_pl;
1252 
output take_it_pl;
1253 
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1254 
output got_it_pl;
1255 
input clk_src, rst_src;
1256 
input clk_dst, rst_dst;
1257 
wire take_it_tg, take_it_tg_sync;
1258 
wire got_it_tg, got_it_tg_sync;
1259 
// src -> dst
1260 
`define MODULE pulse2toggle
1261 
`BASE`MODULE p2t0 (
1262 
`undef MODULE
1263 
    .pl(start_pl),
1264 
    .q(take_it_tg),
1265 
    .clk(clk_src),
1266 
    .rst(rst_src));
1267 75 unneback 
 
1268 94 unneback 
`define MODULE synchronizer
1269 
`BASE`MODULE sync0 (
1270 
`undef MODULE
1271 
    .d(take_it_tg),
1272 
    .q(take_it_tg_sync),
1273 
    .clk(clk_dst),
1274 
    .rst(rst_dst));
1275 
 
1276 
`define MODULE toggle2pulse
1277 
`BASE`MODULE t2p0 (
1278 
`undef MODULE
1279 100 unneback 
    .d(take_it_tg_sync),
1280 94 unneback 
    .pl(take_it_pl),
1281 
    .clk(clk_dst),
1282 
    .rst(rst_dst));
1283 
 
1284 
// dst -> src
1285 
`define MODULE pulse2toggle
1286 98 unneback 
`BASE`MODULE p2t1 (
1287 94 unneback 
`undef MODULE
1288 
    .pl(take_it_grant_pl),
1289 
    .q(got_it_tg),
1290 
    .clk(clk_dst),
1291 
    .rst(rst_dst));
1292 
 
1293 
`define MODULE synchronizer
1294 
`BASE`MODULE sync1 (
1295 
`undef MODULE
1296 
    .d(got_it_tg),
1297 
    .q(got_it_tg_sync),
1298 
    .clk(clk_src),
1299 
    .rst(rst_src));
1300 
 
1301 
`define MODULE toggle2pulse
1302 
`BASE`MODULE t2p1 (
1303 
`undef MODULE
1304 100 unneback 
    .d(got_it_tg_sync),
1305 94 unneback 
    .pl(got_it_pl),
1306 
    .clk(clk_src),
1307 
    .rst(rst_src));
1308 
 
1309 75 unneback 
endmodule
1310 
`endif
1311 17 unneback 
//////////////////////////////////////////////////////////////////////
1312 6 unneback 
////                                                              ////
1313 18 unneback 
////  Logic functions                                             ////
1314 
////                                                              ////
1315 
////  Description                                                 ////
1316 
////  Logic functions such as multiplexers                        ////
1317 
////                                                              ////
1318 
////                                                              ////
1319 
////  To Do:                                                      ////
1320 
////   -                                                          ////
1321 
////                                                              ////
1322 
////  Author(s):                                                  ////
1323 
////      - Michael Unneback, unneback@opencores.org              ////
1324 
////        ORSoC AB                                              ////
1325 
////                                                              ////
1326 
//////////////////////////////////////////////////////////////////////
1327 
////                                                              ////
1328 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1329 
////                                                              ////
1330 
//// This source file may be used and distributed without         ////
1331 
//// restriction provided that this copyright statement is not    ////
1332 
//// removed from the file and that any derivative work contains  ////
1333 
//// the original copyright notice and the associated disclaimer. ////
1334 
////                                                              ////
1335 
//// This source file is free software; you can redistribute it   ////
1336 
//// and/or modify it under the terms of the GNU Lesser General   ////
1337 
//// Public License as published by the Free Software Foundation; ////
1338 
//// either version 2.1 of the License, or (at your option) any   ////
1339 
//// later version.                                               ////
1340 
////                                                              ////
1341 
//// This source is distributed in the hope that it will be       ////
1342 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1343 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1344 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1345 
//// details.                                                     ////
1346 
////                                                              ////
1347 
//// You should have received a copy of the GNU Lesser General    ////
1348 
//// Public License along with this source; if not, download it   ////
1349 
//// from http://www.opencores.org/lgpl.shtml                     ////
1350 
////                                                              ////
1351 
//////////////////////////////////////////////////////////////////////
1352 40 unneback 
`ifdef MUX_ANDOR
1353 
`define MODULE mux_andor
1354 
module `BASE`MODULE ( a, sel, dout);
1355 
`undef MODULE
1356 36 unneback 
 
1357 
parameter width = 32;
1358 
parameter nr_of_ports = 4;
1359 
 
1360 
input [nr_of_ports*width-1:0] a;
1361 
input [nr_of_ports-1:0] sel;
1362 
output reg [width-1:0] dout;
1363 
 
1364 38 unneback 
integer i,j;
1365 
 
1366 36 unneback 
always @ (a, sel)
1367 
begin
1368 
    dout = a[width-1:0] & {width{sel[0]}};
1369 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1370 
        for (j=0;j<width;j=j+1)
1371 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1372 36 unneback 
end
1373 
 
1374 
endmodule
1375 40 unneback 
`endif
1376 36 unneback 
 
1377 40 unneback 
`ifdef MUX2_ANDOR
1378 
`define MODULE mux2_andor
1379 
module `BASE`MODULE ( a1, a0, sel, dout);
1380 
`undef MODULE
1381 18 unneback 
 
1382 34 unneback 
parameter width = 32;
1383 35 unneback 
localparam nr_of_ports = 2;
1384 34 unneback 
input [width-1:0] a1, a0;
1385 
input [nr_of_ports-1:0] sel;
1386 
output [width-1:0] dout;
1387 
 
1388 40 unneback 
`define MODULE mux_andor
1389 
`BASE`MODULE
1390 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1391 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1392 40 unneback 
`undef MODULE
1393 
 
1394 34 unneback 
endmodule
1395 40 unneback 
`endif
1396 34 unneback 
 
1397 40 unneback 
`ifdef MUX3_ANDOR
1398 
`define MODULE mux3_andor
1399 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1400 
`undef MODULE
1401 34 unneback 
 
1402 
parameter width = 32;
1403 35 unneback 
localparam nr_of_ports = 3;
1404 34 unneback 
input [width-1:0] a2, a1, a0;
1405 
input [nr_of_ports-1:0] sel;
1406 
output [width-1:0] dout;
1407 
 
1408 40 unneback 
`define MODULE mux_andor
1409 
`BASE`MODULE
1410 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1411 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1412 40 unneback 
`undef MODULE
1413 34 unneback 
endmodule
1414 40 unneback 
`endif
1415 34 unneback 
 
1416 40 unneback 
`ifdef MUX4_ANDOR
1417 
`define MODULE mux4_andor
1418 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1419 
`undef MODULE
1420 18 unneback 
 
1421 
parameter width = 32;
1422 35 unneback 
localparam nr_of_ports = 4;
1423 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1424 
input [nr_of_ports-1:0] sel;
1425 22 unneback 
output [width-1:0] dout;
1426 18 unneback 
 
1427 40 unneback 
`define MODULE mux_andor
1428 
`BASE`MODULE
1429 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1430 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1431 40 unneback 
`undef MODULE
1432 18 unneback 
 
1433 
endmodule
1434 40 unneback 
`endif
1435 18 unneback 
 
1436 40 unneback 
`ifdef MUX5_ANDOR
1437 
`define MODULE mux5_andor
1438 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1439 
`undef MODULE
1440 18 unneback 
 
1441 
parameter width = 32;
1442 35 unneback 
localparam nr_of_ports = 5;
1443 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1444 
input [nr_of_ports-1:0] sel;
1445 22 unneback 
output [width-1:0] dout;
1446 18 unneback 
 
1447 40 unneback 
`define MODULE mux_andor
1448 
`BASE`MODULE
1449 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1450 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1451 40 unneback 
`undef MODULE
1452 18 unneback 
 
1453 
endmodule
1454 40 unneback 
`endif
1455 18 unneback 
 
1456 40 unneback 
`ifdef MUX6_ANDOR
1457 
`define MODULE mux6_andor
1458 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1459 
`undef MODULE
1460 18 unneback 
 
1461 
parameter width = 32;
1462 35 unneback 
localparam nr_of_ports = 6;
1463 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1464 
input [nr_of_ports-1:0] sel;
1465 22 unneback 
output [width-1:0] dout;
1466 18 unneback 
 
1467 40 unneback 
`define MODULE mux_andor
1468 
`BASE`MODULE
1469 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1470 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1471 40 unneback 
`undef MODULE
1472 18 unneback 
 
1473 
endmodule
1474 40 unneback 
`endif
1475 43 unneback 
 
1476 
`ifdef PARITY
1477 
 
1478 
`define MODULE parity_generate
1479 
module `BASE`MODULE (data, parity);
1480 
`undef MODULE
1481 
parameter word_size = 32;
1482 
parameter chunk_size = 8;
1483 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1484 
input [word_size-1:0] data;
1485 
output reg [word_size/chunk_size-1:0] parity;
1486 
integer i,j;
1487 
always @ (data)
1488 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1489 
    parity[i] = parity_type;
1490 
    for (j=0;j<chunk_size;j=j+1) begin
1491 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1492 43 unneback 
    end
1493 
end
1494 
endmodule
1495 
 
1496 
`define MODULE parity_check
1497 
module `BASE`MODULE( data, parity, parity_error);
1498 
`undef MODULE
1499 
parameter word_size = 32;
1500 
parameter chunk_size = 8;
1501 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1502 
input [word_size-1:0] data;
1503 
input [word_size/chunk_size-1:0] parity;
1504 
output parity_error;
1505 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1506 43 unneback 
integer i,j;
1507 
always @ (data or parity)
1508 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1509 
    error_flag[i] = parity[i] ^ parity_type;
1510 
    for (j=0;j<chunk_size;j=j+1) begin
1511 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1512 43 unneback 
    end
1513 
end
1514 
assign parity_error = |error_flag;
1515 
endmodule
1516 
 
1517 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1518 
////                                                              ////
1519 
////  IO functions                                                ////
1520 
////                                                              ////
1521 
////  Description                                                 ////
1522 
////  IO functions such as IOB flip-flops                         ////
1523 
////                                                              ////
1524 
////                                                              ////
1525 
////  To Do:                                                      ////
1526 
////   -                                                          ////
1527 
////                                                              ////
1528 
////  Author(s):                                                  ////
1529 
////      - Michael Unneback, unneback@opencores.org              ////
1530 
////        ORSoC AB                                              ////
1531 
////                                                              ////
1532 18 unneback 
//////////////////////////////////////////////////////////////////////
1533 
////                                                              ////
1534 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1535 
////                                                              ////
1536 
//// This source file may be used and distributed without         ////
1537 
//// restriction provided that this copyright statement is not    ////
1538 
//// removed from the file and that any derivative work contains  ////
1539 
//// the original copyright notice and the associated disclaimer. ////
1540 
////                                                              ////
1541 
//// This source file is free software; you can redistribute it   ////
1542 
//// and/or modify it under the terms of the GNU Lesser General   ////
1543 
//// Public License as published by the Free Software Foundation; ////
1544 
//// either version 2.1 of the License, or (at your option) any   ////
1545 
//// later version.                                               ////
1546 
////                                                              ////
1547 
//// This source is distributed in the hope that it will be       ////
1548 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1549 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1550 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1551 
//// details.                                                     ////
1552 
////                                                              ////
1553 
//// You should have received a copy of the GNU Lesser General    ////
1554 
//// Public License along with this source; if not, download it   ////
1555 
//// from http://www.opencores.org/lgpl.shtml                     ////
1556 
////                                                              ////
1557 
//////////////////////////////////////////////////////////////////////
1558 45 unneback 
`timescale 1ns/1ns
1559 44 unneback 
`ifdef O_DFF
1560 
`define MODULE o_dff
1561 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1562 
`undef MODULE
1563 
parameter width = 1;
1564 45 unneback 
parameter reset_value = {width{1'b0}};
1565 
input  [width-1:0]  d_i;
1566 44 unneback 
output [width-1:0] o_pad;
1567 
input clk, rst;
1568 
wire [width-1:0] d_i_int `SYN_KEEP;
1569 45 unneback 
reg  [width-1:0] o_pad_int;
1570 44 unneback 
assign d_i_int = d_i;
1571 
genvar i;
1572 45 unneback 
generate
1573 44 unneback 
for (i=0;i<width;i=i+1) begin
1574 
    always @ (posedge clk or posedge rst)
1575 
    if (rst)
1576 45 unneback 
        o_pad_int[i] <= reset_value[i];
1577 44 unneback 
    else
1578 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1579 
    assign #1 o_pad[i] = o_pad_int[i];
1580 44 unneback 
end
1581 
endgenerate
1582 
endmodule
1583 
`endif
1584 
 
1585 45 unneback 
`timescale 1ns/1ns
1586 44 unneback 
`ifdef IO_DFF_OE
1587 
`define MODULE io_dff_oe
1588 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1589 
`undef MODULE
1590 
parameter width = 1;
1591 
input  [width-1:0] d_o;
1592 
output reg [width-1:0] d_i;
1593 
input oe;
1594 
inout [width-1:0] io_pad;
1595 
input clk, rst;
1596 
wire [width-1:0] oe_d `SYN_KEEP;
1597 
reg [width-1:0] oe_q;
1598 
reg [width-1:0] d_o_q;
1599 
assign oe_d = {width{oe}};
1600 
genvar i;
1601 
generate
1602 
for (i=0;i<width;i=i+1) begin
1603 
    always @ (posedge clk or posedge rst)
1604 
    if (rst)
1605 
        oe_q[i] <= 1'b0;
1606 
    else
1607 
        oe_q[i] <= oe_d[i];
1608 
    always @ (posedge clk or posedge rst)
1609 
    if (rst)
1610 
        d_o_q[i] <= 1'b0;
1611 
    else
1612 
        d_o_q[i] <= d_o[i];
1613 
    always @ (posedge clk or posedge rst)
1614 
    if (rst)
1615 
        d_i[i] <= 1'b0;
1616 
    else
1617 
        d_i[i] <= io_pad[i];
1618 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1619 44 unneback 
end
1620 
endgenerate
1621 
endmodule
1622 
`endif
1623 
`ifdef CNT_BIN
1624 
//////////////////////////////////////////////////////////////////////
1625 
////                                                              ////
1626 6 unneback 
////  Versatile counter                                           ////
1627 
////                                                              ////
1628 
////  Description                                                 ////
1629 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1630 
////  counter                                                     ////
1631 
////                                                              ////
1632 
////  To Do:                                                      ////
1633 
////   - add LFSR with more taps                                  ////
1634 
////                                                              ////
1635 
////  Author(s):                                                  ////
1636 
////      - Michael Unneback, unneback@opencores.org              ////
1637 
////        ORSoC AB                                              ////
1638 
////                                                              ////
1639 
//////////////////////////////////////////////////////////////////////
1640 
////                                                              ////
1641 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1642 
////                                                              ////
1643 
//// This source file may be used and distributed without         ////
1644 
//// restriction provided that this copyright statement is not    ////
1645 
//// removed from the file and that any derivative work contains  ////
1646 
//// the original copyright notice and the associated disclaimer. ////
1647 
////                                                              ////
1648 
//// This source file is free software; you can redistribute it   ////
1649 
//// and/or modify it under the terms of the GNU Lesser General   ////
1650 
//// Public License as published by the Free Software Foundation; ////
1651 
//// either version 2.1 of the License, or (at your option) any   ////
1652 
//// later version.                                               ////
1653 
////                                                              ////
1654 
//// This source is distributed in the hope that it will be       ////
1655 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1656 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1657 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1658 
//// details.                                                     ////
1659 
////                                                              ////
1660 
//// You should have received a copy of the GNU Lesser General    ////
1661 
//// Public License along with this source; if not, download it   ////
1662 
//// from http://www.opencores.org/lgpl.shtml                     ////
1663 
////                                                              ////
1664 
//////////////////////////////////////////////////////////////////////
1665 
 
1666 
// binary counter
1667 22 unneback 
 
1668 40 unneback 
`define MODULE cnt_bin
1669 
module `BASE`MODULE (
1670 
`undef MODULE
1671 
 q, rst, clk);
1672 
 
1673 22 unneback 
   parameter length = 4;
1674 
   output [length:1] q;
1675 
   input rst;
1676 
   input clk;
1677 
 
1678 
   parameter clear_value = 0;
1679 
   parameter set_value = 1;
1680 
   parameter wrap_value = 0;
1681 
   parameter level1_value = 15;
1682 
 
1683 
   reg  [length:1] qi;
1684 
   wire [length:1] q_next;
1685 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1686 
 
1687 
   always @ (posedge clk or posedge rst)
1688 
     if (rst)
1689 
       qi <= {length{1'b0}};
1690 
     else
1691 
       qi <= q_next;
1692 
 
1693 
   assign q = qi;
1694 
 
1695 
endmodule
1696 40 unneback 
`endif
1697 
`ifdef CNT_BIN_CLEAR
1698 22 unneback 
//////////////////////////////////////////////////////////////////////
1699 
////                                                              ////
1700 
////  Versatile counter                                           ////
1701 
////                                                              ////
1702 
////  Description                                                 ////
1703 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1704 
////  counter                                                     ////
1705 
////                                                              ////
1706 
////  To Do:                                                      ////
1707 
////   - add LFSR with more taps                                  ////
1708 
////                                                              ////
1709 
////  Author(s):                                                  ////
1710 
////      - Michael Unneback, unneback@opencores.org              ////
1711 
////        ORSoC AB                                              ////
1712 
////                                                              ////
1713 
//////////////////////////////////////////////////////////////////////
1714 
////                                                              ////
1715 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1716 
////                                                              ////
1717 
//// This source file may be used and distributed without         ////
1718 
//// restriction provided that this copyright statement is not    ////
1719 
//// removed from the file and that any derivative work contains  ////
1720 
//// the original copyright notice and the associated disclaimer. ////
1721 
////                                                              ////
1722 
//// This source file is free software; you can redistribute it   ////
1723 
//// and/or modify it under the terms of the GNU Lesser General   ////
1724 
//// Public License as published by the Free Software Foundation; ////
1725 
//// either version 2.1 of the License, or (at your option) any   ////
1726 
//// later version.                                               ////
1727 
////                                                              ////
1728 
//// This source is distributed in the hope that it will be       ////
1729 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1730 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1731 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1732 
//// details.                                                     ////
1733 
////                                                              ////
1734 
//// You should have received a copy of the GNU Lesser General    ////
1735 
//// Public License along with this source; if not, download it   ////
1736 
//// from http://www.opencores.org/lgpl.shtml                     ////
1737 
////                                                              ////
1738 
//////////////////////////////////////////////////////////////////////
1739 
 
1740 
// binary counter
1741 
 
1742 40 unneback 
`define MODULE cnt_bin_clear
1743 
module `BASE`MODULE (
1744 
`undef MODULE
1745 
 clear, q, rst, clk);
1746 
 
1747 22 unneback 
   parameter length = 4;
1748 
   input clear;
1749 
   output [length:1] q;
1750 
   input rst;
1751 
   input clk;
1752 
 
1753 
   parameter clear_value = 0;
1754 
   parameter set_value = 1;
1755 
   parameter wrap_value = 0;
1756 
   parameter level1_value = 15;
1757 
 
1758 
   reg  [length:1] qi;
1759 
   wire [length:1] q_next;
1760 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1761 
 
1762 
   always @ (posedge clk or posedge rst)
1763 
     if (rst)
1764 
       qi <= {length{1'b0}};
1765 
     else
1766 
       qi <= q_next;
1767 
 
1768 
   assign q = qi;
1769 
 
1770 
endmodule
1771 40 unneback 
`endif
1772 
`ifdef CNT_BIN_CE
1773 22 unneback 
//////////////////////////////////////////////////////////////////////
1774 
////                                                              ////
1775 
////  Versatile counter                                           ////
1776 
////                                                              ////
1777 
////  Description                                                 ////
1778 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1779 
////  counter                                                     ////
1780 
////                                                              ////
1781 
////  To Do:                                                      ////
1782 
////   - add LFSR with more taps                                  ////
1783 
////                                                              ////
1784 
////  Author(s):                                                  ////
1785 
////      - Michael Unneback, unneback@opencores.org              ////
1786 
////        ORSoC AB                                              ////
1787 
////                                                              ////
1788 
//////////////////////////////////////////////////////////////////////
1789 
////                                                              ////
1790 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1791 
////                                                              ////
1792 
//// This source file may be used and distributed without         ////
1793 
//// restriction provided that this copyright statement is not    ////
1794 
//// removed from the file and that any derivative work contains  ////
1795 
//// the original copyright notice and the associated disclaimer. ////
1796 
////                                                              ////
1797 
//// This source file is free software; you can redistribute it   ////
1798 
//// and/or modify it under the terms of the GNU Lesser General   ////
1799 
//// Public License as published by the Free Software Foundation; ////
1800 
//// either version 2.1 of the License, or (at your option) any   ////
1801 
//// later version.                                               ////
1802 
////                                                              ////
1803 
//// This source is distributed in the hope that it will be       ////
1804 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1805 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1806 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1807 
//// details.                                                     ////
1808 
////                                                              ////
1809 
//// You should have received a copy of the GNU Lesser General    ////
1810 
//// Public License along with this source; if not, download it   ////
1811 
//// from http://www.opencores.org/lgpl.shtml                     ////
1812 
////                                                              ////
1813 
//////////////////////////////////////////////////////////////////////
1814 
 
1815 
// binary counter
1816 6 unneback 
 
1817 40 unneback 
`define MODULE cnt_bin_ce
1818 
module `BASE`MODULE (
1819 
`undef MODULE
1820 
 cke, q, rst, clk);
1821 
 
1822 6 unneback 
   parameter length = 4;
1823 
   input cke;
1824 
   output [length:1] q;
1825 
   input rst;
1826 
   input clk;
1827 
 
1828 
   parameter clear_value = 0;
1829 
   parameter set_value = 1;
1830 
   parameter wrap_value = 0;
1831 
   parameter level1_value = 15;
1832 
 
1833 
   reg  [length:1] qi;
1834 
   wire [length:1] q_next;
1835 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1836 
 
1837 
   always @ (posedge clk or posedge rst)
1838 
     if (rst)
1839 
       qi <= {length{1'b0}};
1840 
     else
1841 
     if (cke)
1842 
       qi <= q_next;
1843 
 
1844 
   assign q = qi;
1845 
 
1846 
endmodule
1847 40 unneback 
`endif
1848 
`ifdef CNT_BIN_CE_CLEAR
1849 6 unneback 
//////////////////////////////////////////////////////////////////////
1850 
////                                                              ////
1851 
////  Versatile counter                                           ////
1852 
////                                                              ////
1853 
////  Description                                                 ////
1854 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1855 
////  counter                                                     ////
1856 
////                                                              ////
1857 
////  To Do:                                                      ////
1858 
////   - add LFSR with more taps                                  ////
1859 
////                                                              ////
1860 
////  Author(s):                                                  ////
1861 
////      - Michael Unneback, unneback@opencores.org              ////
1862 
////        ORSoC AB                                              ////
1863 
////                                                              ////
1864 
//////////////////////////////////////////////////////////////////////
1865 
////                                                              ////
1866 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1867 
////                                                              ////
1868 
//// This source file may be used and distributed without         ////
1869 
//// restriction provided that this copyright statement is not    ////
1870 
//// removed from the file and that any derivative work contains  ////
1871 
//// the original copyright notice and the associated disclaimer. ////
1872 
////                                                              ////
1873 
//// This source file is free software; you can redistribute it   ////
1874 
//// and/or modify it under the terms of the GNU Lesser General   ////
1875 
//// Public License as published by the Free Software Foundation; ////
1876 
//// either version 2.1 of the License, or (at your option) any   ////
1877 
//// later version.                                               ////
1878 
////                                                              ////
1879 
//// This source is distributed in the hope that it will be       ////
1880 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1881 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1882 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1883 
//// details.                                                     ////
1884 
////                                                              ////
1885 
//// You should have received a copy of the GNU Lesser General    ////
1886 
//// Public License along with this source; if not, download it   ////
1887 
//// from http://www.opencores.org/lgpl.shtml                     ////
1888 
////                                                              ////
1889 
//////////////////////////////////////////////////////////////////////
1890 
 
1891 
// binary counter
1892 
 
1893 40 unneback 
`define MODULE cnt_bin_ce_clear
1894 
module `BASE`MODULE (
1895 
`undef MODULE
1896 
 clear, cke, q, rst, clk);
1897 
 
1898 6 unneback 
   parameter length = 4;
1899 
   input clear;
1900 
   input cke;
1901 
   output [length:1] q;
1902 
   input rst;
1903 
   input clk;
1904 
 
1905 
   parameter clear_value = 0;
1906 
   parameter set_value = 1;
1907 
   parameter wrap_value = 0;
1908 
   parameter level1_value = 15;
1909 
 
1910 
   reg  [length:1] qi;
1911 
   wire [length:1] q_next;
1912 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1913 
 
1914 
   always @ (posedge clk or posedge rst)
1915 
     if (rst)
1916 
       qi <= {length{1'b0}};
1917 
     else
1918 
     if (cke)
1919 
       qi <= q_next;
1920 
 
1921 
   assign q = qi;
1922 
 
1923 
endmodule
1924 40 unneback 
`endif
1925 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1926 6 unneback 
//////////////////////////////////////////////////////////////////////
1927 
////                                                              ////
1928 
////  Versatile counter                                           ////
1929 
////                                                              ////
1930 
////  Description                                                 ////
1931 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1932 
////  counter                                                     ////
1933 
////                                                              ////
1934 
////  To Do:                                                      ////
1935 
////   - add LFSR with more taps                                  ////
1936 
////                                                              ////
1937 
////  Author(s):                                                  ////
1938 
////      - Michael Unneback, unneback@opencores.org              ////
1939 
////        ORSoC AB                                              ////
1940 
////                                                              ////
1941 
//////////////////////////////////////////////////////////////////////
1942 
////                                                              ////
1943 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1944 
////                                                              ////
1945 
//// This source file may be used and distributed without         ////
1946 
//// restriction provided that this copyright statement is not    ////
1947 
//// removed from the file and that any derivative work contains  ////
1948 
//// the original copyright notice and the associated disclaimer. ////
1949 
////                                                              ////
1950 
//// This source file is free software; you can redistribute it   ////
1951 
//// and/or modify it under the terms of the GNU Lesser General   ////
1952 
//// Public License as published by the Free Software Foundation; ////
1953 
//// either version 2.1 of the License, or (at your option) any   ////
1954 
//// later version.                                               ////
1955 
////                                                              ////
1956 
//// This source is distributed in the hope that it will be       ////
1957 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1958 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1959 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1960 
//// details.                                                     ////
1961 
////                                                              ////
1962 
//// You should have received a copy of the GNU Lesser General    ////
1963 
//// Public License along with this source; if not, download it   ////
1964 
//// from http://www.opencores.org/lgpl.shtml                     ////
1965 
////                                                              ////
1966 
//////////////////////////////////////////////////////////////////////
1967 
 
1968 
// binary counter
1969 29 unneback 
 
1970 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1971 
module `BASE`MODULE (
1972 
`undef MODULE
1973 
 clear, cke, q, level1, level2, rst, clk);
1974 
 
1975 29 unneback 
   parameter length = 4;
1976 
   input clear;
1977 
   input cke;
1978 
   output [length:1] q;
1979 
   output reg level1;
1980 
   output reg level2;
1981 
   input rst;
1982 
   input clk;
1983 
 
1984 
   parameter clear_value = 0;
1985 
   parameter set_value = 1;
1986 30 unneback 
   parameter wrap_value = 15;
1987 
   parameter level1_value = 8;
1988 
   parameter level2_value = 15;
1989 29 unneback 
 
1990 
   wire rew;
1991 30 unneback 
   assign rew = 1'b0;
1992 29 unneback 
   reg  [length:1] qi;
1993 
   wire [length:1] q_next;
1994 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1995 
 
1996 
   always @ (posedge clk or posedge rst)
1997 
     if (rst)
1998 
       qi <= {length{1'b0}};
1999 
     else
2000 
     if (cke)
2001 
       qi <= q_next;
2002 
 
2003 
   assign q = qi;
2004 
 
2005 
 
2006 
    always @ (posedge clk or posedge rst)
2007 
    if (rst)
2008 
        level1 <= 1'b0;
2009 
    else
2010 
    if (cke)
2011 
    if (clear)
2012 
        level1 <= 1'b0;
2013 
    else if (q_next == level1_value)
2014 
        level1 <= 1'b1;
2015 
    else if (qi == level1_value & rew)
2016 
        level1 <= 1'b0;
2017 
 
2018 
    always @ (posedge clk or posedge rst)
2019 
    if (rst)
2020 
        level2 <= 1'b0;
2021 
    else
2022 
    if (cke)
2023 
    if (clear)
2024 
        level2 <= 1'b0;
2025 
    else if (q_next == level2_value)
2026 
        level2 <= 1'b1;
2027 
    else if (qi == level2_value & rew)
2028 
        level2 <= 1'b0;
2029 
endmodule
2030 40 unneback 
`endif
2031 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2032 29 unneback 
//////////////////////////////////////////////////////////////////////
2033 
////                                                              ////
2034 
////  Versatile counter                                           ////
2035 
////                                                              ////
2036 
////  Description                                                 ////
2037 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2038 
////  counter                                                     ////
2039 
////                                                              ////
2040 
////  To Do:                                                      ////
2041 
////   - add LFSR with more taps                                  ////
2042 
////                                                              ////
2043 
////  Author(s):                                                  ////
2044 
////      - Michael Unneback, unneback@opencores.org              ////
2045 
////        ORSoC AB                                              ////
2046 
////                                                              ////
2047 
//////////////////////////////////////////////////////////////////////
2048 
////                                                              ////
2049 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2050 
////                                                              ////
2051 
//// This source file may be used and distributed without         ////
2052 
//// restriction provided that this copyright statement is not    ////
2053 
//// removed from the file and that any derivative work contains  ////
2054 
//// the original copyright notice and the associated disclaimer. ////
2055 
////                                                              ////
2056 
//// This source file is free software; you can redistribute it   ////
2057 
//// and/or modify it under the terms of the GNU Lesser General   ////
2058 
//// Public License as published by the Free Software Foundation; ////
2059 
//// either version 2.1 of the License, or (at your option) any   ////
2060 
//// later version.                                               ////
2061 
////                                                              ////
2062 
//// This source is distributed in the hope that it will be       ////
2063 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2064 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2065 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2066 
//// details.                                                     ////
2067 
////                                                              ////
2068 
//// You should have received a copy of the GNU Lesser General    ////
2069 
//// Public License along with this source; if not, download it   ////
2070 
//// from http://www.opencores.org/lgpl.shtml                     ////
2071 
////                                                              ////
2072 
//////////////////////////////////////////////////////////////////////
2073 
 
2074 
// binary counter
2075 6 unneback 
 
2076 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
2077 
module `BASE`MODULE (
2078 
`undef MODULE
2079 
 clear, set, cke, rew, q, rst, clk);
2080 
 
2081 6 unneback 
   parameter length = 4;
2082 
   input clear;
2083 
   input set;
2084 
   input cke;
2085 
   input rew;
2086 
   output [length:1] q;
2087 
   input rst;
2088 
   input clk;
2089 
 
2090 
   parameter clear_value = 0;
2091 
   parameter set_value = 1;
2092 
   parameter wrap_value = 0;
2093 
   parameter level1_value = 15;
2094 
 
2095 
   reg  [length:1] qi;
2096 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2097 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2098 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2099 
   assign q_next = rew ? q_next_rew : q_next_fw;
2100 
 
2101 
   always @ (posedge clk or posedge rst)
2102 
     if (rst)
2103 
       qi <= {length{1'b0}};
2104 
     else
2105 
     if (cke)
2106 
       qi <= q_next;
2107 
 
2108 
   assign q = qi;
2109 
 
2110 
endmodule
2111 40 unneback 
`endif
2112 
`ifdef CNT_BIN_CE_REW_L1
2113 6 unneback 
//////////////////////////////////////////////////////////////////////
2114 
////                                                              ////
2115 
////  Versatile counter                                           ////
2116 
////                                                              ////
2117 
////  Description                                                 ////
2118 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2119 
////  counter                                                     ////
2120 
////                                                              ////
2121 
////  To Do:                                                      ////
2122 
////   - add LFSR with more taps                                  ////
2123 
////                                                              ////
2124 
////  Author(s):                                                  ////
2125 
////      - Michael Unneback, unneback@opencores.org              ////
2126 
////        ORSoC AB                                              ////
2127 
////                                                              ////
2128 
//////////////////////////////////////////////////////////////////////
2129 
////                                                              ////
2130 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2131 
////                                                              ////
2132 
//// This source file may be used and distributed without         ////
2133 
//// restriction provided that this copyright statement is not    ////
2134 
//// removed from the file and that any derivative work contains  ////
2135 
//// the original copyright notice and the associated disclaimer. ////
2136 
////                                                              ////
2137 
//// This source file is free software; you can redistribute it   ////
2138 
//// and/or modify it under the terms of the GNU Lesser General   ////
2139 
//// Public License as published by the Free Software Foundation; ////
2140 
//// either version 2.1 of the License, or (at your option) any   ////
2141 
//// later version.                                               ////
2142 
////                                                              ////
2143 
//// This source is distributed in the hope that it will be       ////
2144 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2145 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2146 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2147 
//// details.                                                     ////
2148 
////                                                              ////
2149 
//// You should have received a copy of the GNU Lesser General    ////
2150 
//// Public License along with this source; if not, download it   ////
2151 
//// from http://www.opencores.org/lgpl.shtml                     ////
2152 
////                                                              ////
2153 
//////////////////////////////////////////////////////////////////////
2154 
 
2155 
// binary counter
2156 
 
2157 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
2158 
module `BASE`MODULE (
2159 
`undef MODULE
2160 
 cke, rew, level1, rst, clk);
2161 
 
2162 6 unneback 
   parameter length = 4;
2163 
   input cke;
2164 
   input rew;
2165 
   output reg level1;
2166 
   input rst;
2167 
   input clk;
2168 
 
2169 
   parameter clear_value = 0;
2170 
   parameter set_value = 1;
2171 
   parameter wrap_value = 1;
2172 
   parameter level1_value = 15;
2173 
 
2174 29 unneback 
   wire clear;
2175 30 unneback 
   assign clear = 1'b0;
2176 6 unneback 
   reg  [length:1] qi;
2177 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2178 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2179 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2180 
   assign q_next = rew ? q_next_rew : q_next_fw;
2181 
 
2182 
   always @ (posedge clk or posedge rst)
2183 
     if (rst)
2184 
       qi <= {length{1'b0}};
2185 
     else
2186 
     if (cke)
2187 
       qi <= q_next;
2188 
 
2189 
 
2190 
 
2191 
    always @ (posedge clk or posedge rst)
2192 
    if (rst)
2193 
        level1 <= 1'b0;
2194 
    else
2195 
    if (cke)
2196 29 unneback 
    if (clear)
2197 
        level1 <= 1'b0;
2198 
    else if (q_next == level1_value)
2199 6 unneback 
        level1 <= 1'b1;
2200 
    else if (qi == level1_value & rew)
2201 
        level1 <= 1'b0;
2202 
endmodule
2203 40 unneback 
`endif
2204 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2205 6 unneback 
//////////////////////////////////////////////////////////////////////
2206 
////                                                              ////
2207 
////  Versatile counter                                           ////
2208 
////                                                              ////
2209 
////  Description                                                 ////
2210 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2211 
////  counter                                                     ////
2212 
////                                                              ////
2213 
////  To Do:                                                      ////
2214 
////   - add LFSR with more taps                                  ////
2215 
////                                                              ////
2216 
////  Author(s):                                                  ////
2217 
////      - Michael Unneback, unneback@opencores.org              ////
2218 
////        ORSoC AB                                              ////
2219 
////                                                              ////
2220 
//////////////////////////////////////////////////////////////////////
2221 
////                                                              ////
2222 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2223 
////                                                              ////
2224 
//// This source file may be used and distributed without         ////
2225 
//// restriction provided that this copyright statement is not    ////
2226 
//// removed from the file and that any derivative work contains  ////
2227 
//// the original copyright notice and the associated disclaimer. ////
2228 
////                                                              ////
2229 
//// This source file is free software; you can redistribute it   ////
2230 
//// and/or modify it under the terms of the GNU Lesser General   ////
2231 
//// Public License as published by the Free Software Foundation; ////
2232 
//// either version 2.1 of the License, or (at your option) any   ////
2233 
//// later version.                                               ////
2234 
////                                                              ////
2235 
//// This source is distributed in the hope that it will be       ////
2236 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2237 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2238 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2239 
//// details.                                                     ////
2240 
////                                                              ////
2241 
//// You should have received a copy of the GNU Lesser General    ////
2242 
//// Public License along with this source; if not, download it   ////
2243 
//// from http://www.opencores.org/lgpl.shtml                     ////
2244 
////                                                              ////
2245 
//////////////////////////////////////////////////////////////////////
2246 
 
2247 25 unneback 
// binary counter
2248 
 
2249 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2250 
module `BASE`MODULE (
2251 
`undef MODULE
2252 
 cke, rew, zq, level1, rst, clk);
2253 
 
2254 25 unneback 
   parameter length = 4;
2255 
   input cke;
2256 
   input rew;
2257 
   output reg zq;
2258 
   output reg level1;
2259 
   input rst;
2260 
   input clk;
2261 
 
2262 
   parameter clear_value = 0;
2263 
   parameter set_value = 1;
2264 
   parameter wrap_value = 1;
2265 
   parameter level1_value = 15;
2266 
 
2267 29 unneback 
   wire clear;
2268 30 unneback 
   assign clear = 1'b0;
2269 25 unneback 
   reg  [length:1] qi;
2270 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2271 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2272 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2273 
   assign q_next = rew ? q_next_rew : q_next_fw;
2274 
 
2275 
   always @ (posedge clk or posedge rst)
2276 
     if (rst)
2277 
       qi <= {length{1'b0}};
2278 
     else
2279 
     if (cke)
2280 
       qi <= q_next;
2281 
 
2282 
 
2283 
 
2284 
   always @ (posedge clk or posedge rst)
2285 
     if (rst)
2286 
       zq <= 1'b1;
2287 
     else
2288 
     if (cke)
2289 
       zq <= q_next == {length{1'b0}};
2290 
 
2291 
    always @ (posedge clk or posedge rst)
2292 
    if (rst)
2293 
        level1 <= 1'b0;
2294 
    else
2295 
    if (cke)
2296 29 unneback 
    if (clear)
2297 
        level1 <= 1'b0;
2298 
    else if (q_next == level1_value)
2299 25 unneback 
        level1 <= 1'b1;
2300 
    else if (qi == level1_value & rew)
2301 
        level1 <= 1'b0;
2302 
endmodule
2303 40 unneback 
`endif
2304 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2305 25 unneback 
//////////////////////////////////////////////////////////////////////
2306 
////                                                              ////
2307 
////  Versatile counter                                           ////
2308 
////                                                              ////
2309 
////  Description                                                 ////
2310 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2311 
////  counter                                                     ////
2312 
////                                                              ////
2313 
////  To Do:                                                      ////
2314 
////   - add LFSR with more taps                                  ////
2315 
////                                                              ////
2316 
////  Author(s):                                                  ////
2317 
////      - Michael Unneback, unneback@opencores.org              ////
2318 
////        ORSoC AB                                              ////
2319 
////                                                              ////
2320 
//////////////////////////////////////////////////////////////////////
2321 
////                                                              ////
2322 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2323 
////                                                              ////
2324 
//// This source file may be used and distributed without         ////
2325 
//// restriction provided that this copyright statement is not    ////
2326 
//// removed from the file and that any derivative work contains  ////
2327 
//// the original copyright notice and the associated disclaimer. ////
2328 
////                                                              ////
2329 
//// This source file is free software; you can redistribute it   ////
2330 
//// and/or modify it under the terms of the GNU Lesser General   ////
2331 
//// Public License as published by the Free Software Foundation; ////
2332 
//// either version 2.1 of the License, or (at your option) any   ////
2333 
//// later version.                                               ////
2334 
////                                                              ////
2335 
//// This source is distributed in the hope that it will be       ////
2336 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2337 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2338 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2339 
//// details.                                                     ////
2340 
////                                                              ////
2341 
//// You should have received a copy of the GNU Lesser General    ////
2342 
//// Public License along with this source; if not, download it   ////
2343 
//// from http://www.opencores.org/lgpl.shtml                     ////
2344 
////                                                              ////
2345 
//////////////////////////////////////////////////////////////////////
2346 
 
2347 
// binary counter
2348 
 
2349 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2350 
module `BASE`MODULE (
2351 
`undef MODULE
2352 
 cke, rew, q, zq, level1, rst, clk);
2353 
 
2354 25 unneback 
   parameter length = 4;
2355 
   input cke;
2356 
   input rew;
2357 
   output [length:1] q;
2358 
   output reg zq;
2359 
   output reg level1;
2360 
   input rst;
2361 
   input clk;
2362 
 
2363 
   parameter clear_value = 0;
2364 
   parameter set_value = 1;
2365 
   parameter wrap_value = 1;
2366 
   parameter level1_value = 15;
2367 
 
2368 29 unneback 
   wire clear;
2369 30 unneback 
   assign clear = 1'b0;
2370 25 unneback 
   reg  [length:1] qi;
2371 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2372 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2373 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2374 
   assign q_next = rew ? q_next_rew : q_next_fw;
2375 
 
2376 
   always @ (posedge clk or posedge rst)
2377 
     if (rst)
2378 
       qi <= {length{1'b0}};
2379 
     else
2380 
     if (cke)
2381 
       qi <= q_next;
2382 
 
2383 
   assign q = qi;
2384 
 
2385 
 
2386 
   always @ (posedge clk or posedge rst)
2387 
     if (rst)
2388 
       zq <= 1'b1;
2389 
     else
2390 
     if (cke)
2391 
       zq <= q_next == {length{1'b0}};
2392 
 
2393 
    always @ (posedge clk or posedge rst)
2394 
    if (rst)
2395 
        level1 <= 1'b0;
2396 
    else
2397 
    if (cke)
2398 29 unneback 
    if (clear)
2399 
        level1 <= 1'b0;
2400 
    else if (q_next == level1_value)
2401 25 unneback 
        level1 <= 1'b1;
2402 
    else if (qi == level1_value & rew)
2403 
        level1 <= 1'b0;
2404 
endmodule
2405 40 unneback 
`endif
2406 
`ifdef CNT_LFSR_ZQ
2407 25 unneback 
//////////////////////////////////////////////////////////////////////
2408 
////                                                              ////
2409 
////  Versatile counter                                           ////
2410 
////                                                              ////
2411 
////  Description                                                 ////
2412 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2413 
////  counter                                                     ////
2414 
////                                                              ////
2415 
////  To Do:                                                      ////
2416 
////   - add LFSR with more taps                                  ////
2417 
////                                                              ////
2418 
////  Author(s):                                                  ////
2419 
////      - Michael Unneback, unneback@opencores.org              ////
2420 
////        ORSoC AB                                              ////
2421 
////                                                              ////
2422 
//////////////////////////////////////////////////////////////////////
2423 
////                                                              ////
2424 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2425 
////                                                              ////
2426 
//// This source file may be used and distributed without         ////
2427 
//// restriction provided that this copyright statement is not    ////
2428 
//// removed from the file and that any derivative work contains  ////
2429 
//// the original copyright notice and the associated disclaimer. ////
2430 
////                                                              ////
2431 
//// This source file is free software; you can redistribute it   ////
2432 
//// and/or modify it under the terms of the GNU Lesser General   ////
2433 
//// Public License as published by the Free Software Foundation; ////
2434 
//// either version 2.1 of the License, or (at your option) any   ////
2435 
//// later version.                                               ////
2436 
////                                                              ////
2437 
//// This source is distributed in the hope that it will be       ////
2438 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2439 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2440 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2441 
//// details.                                                     ////
2442 
////                                                              ////
2443 
//// You should have received a copy of the GNU Lesser General    ////
2444 
//// Public License along with this source; if not, download it   ////
2445 
//// from http://www.opencores.org/lgpl.shtml                     ////
2446 
////                                                              ////
2447 
//////////////////////////////////////////////////////////////////////
2448 
 
2449 6 unneback 
// LFSR counter
2450 
 
2451 40 unneback 
`define MODULE cnt_lfsr_zq
2452 
module `BASE`MODULE (
2453 
`undef MODULE
2454 
 zq, rst, clk);
2455 
 
2456 6 unneback 
   parameter length = 4;
2457 
   output reg zq;
2458 
   input rst;
2459 
   input clk;
2460 
 
2461 
   parameter clear_value = 0;
2462 
   parameter set_value = 1;
2463 
   parameter wrap_value = 8;
2464 
   parameter level1_value = 15;
2465 
 
2466 
   reg  [length:1] qi;
2467 
   reg lfsr_fb;
2468 
   wire [length:1] q_next;
2469 
   reg [32:1] polynom;
2470 
   integer i;
2471 
 
2472 
   always @ (qi)
2473 
   begin
2474 
        case (length)
2475 
         2: polynom = 32'b11;                               // 0x3
2476 
         3: polynom = 32'b110;                              // 0x6
2477 
         4: polynom = 32'b1100;                             // 0xC
2478 
         5: polynom = 32'b10100;                            // 0x14
2479 
         6: polynom = 32'b110000;                           // 0x30
2480 
         7: polynom = 32'b1100000;                          // 0x60
2481 
         8: polynom = 32'b10111000;                         // 0xb8
2482 
         9: polynom = 32'b100010000;                        // 0x110
2483 
        10: polynom = 32'b1001000000;                       // 0x240
2484 
        11: polynom = 32'b10100000000;                      // 0x500
2485 
        12: polynom = 32'b100000101001;                     // 0x829
2486 
        13: polynom = 32'b1000000001100;                    // 0x100C
2487 
        14: polynom = 32'b10000000010101;                   // 0x2015
2488 
        15: polynom = 32'b110000000000000;                  // 0x6000
2489 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2490 
        17: polynom = 32'b10010000000000000;                // 0x12000
2491 
        18: polynom = 32'b100000010000000000;               // 0x20400
2492 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2493 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2494 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2495 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2496 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2497 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2498 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2499 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2500 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2501 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2502 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2503 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2504 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2505 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2506 
        default: polynom = 32'b0;
2507 
        endcase
2508 
        lfsr_fb = qi[length];
2509 
        for (i=length-1; i>=1; i=i-1) begin
2510 
            if (polynom[i])
2511 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2512 
        end
2513 
    end
2514 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2515 
 
2516 
   always @ (posedge clk or posedge rst)
2517 
     if (rst)
2518 
       qi <= {length{1'b0}};
2519 
     else
2520 
       qi <= q_next;
2521 
 
2522 
 
2523 
 
2524 
   always @ (posedge clk or posedge rst)
2525 
     if (rst)
2526 
       zq <= 1'b1;
2527 
     else
2528 
       zq <= q_next == {length{1'b0}};
2529 
endmodule
2530 40 unneback 
`endif
2531 75 unneback 
`ifdef CNT_LFSR_CE
2532 
//////////////////////////////////////////////////////////////////////
2533 
////                                                              ////
2534 
////  Versatile counter                                           ////
2535 
////                                                              ////
2536 
////  Description                                                 ////
2537 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2538 
////  counter                                                     ////
2539 
////                                                              ////
2540 
////  To Do:                                                      ////
2541 
////   - add LFSR with more taps                                  ////
2542 
////                                                              ////
2543 
////  Author(s):                                                  ////
2544 
////      - Michael Unneback, unneback@opencores.org              ////
2545 
////        ORSoC AB                                              ////
2546 
////                                                              ////
2547 
//////////////////////////////////////////////////////////////////////
2548 
////                                                              ////
2549 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2550 
////                                                              ////
2551 
//// This source file may be used and distributed without         ////
2552 
//// restriction provided that this copyright statement is not    ////
2553 
//// removed from the file and that any derivative work contains  ////
2554 
//// the original copyright notice and the associated disclaimer. ////
2555 
////                                                              ////
2556 
//// This source file is free software; you can redistribute it   ////
2557 
//// and/or modify it under the terms of the GNU Lesser General   ////
2558 
//// Public License as published by the Free Software Foundation; ////
2559 
//// either version 2.1 of the License, or (at your option) any   ////
2560 
//// later version.                                               ////
2561 
////                                                              ////
2562 
//// This source is distributed in the hope that it will be       ////
2563 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2564 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2565 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2566 
//// details.                                                     ////
2567 
////                                                              ////
2568 
//// You should have received a copy of the GNU Lesser General    ////
2569 
//// Public License along with this source; if not, download it   ////
2570 
//// from http://www.opencores.org/lgpl.shtml                     ////
2571 
////                                                              ////
2572 
//////////////////////////////////////////////////////////////////////
2573 
 
2574 
// LFSR counter
2575 
 
2576 
`define MODULE cnt_lfsr_ce
2577 
module `BASE`MODULE (
2578 
`undef MODULE
2579 
 cke, zq, rst, clk);
2580 
 
2581 
   parameter length = 4;
2582 
   input cke;
2583 
   output reg zq;
2584 
   input rst;
2585 
   input clk;
2586 
 
2587 
   parameter clear_value = 0;
2588 
   parameter set_value = 1;
2589 
   parameter wrap_value = 0;
2590 
   parameter level1_value = 15;
2591 
 
2592 
   reg  [length:1] qi;
2593 
   reg lfsr_fb;
2594 
   wire [length:1] q_next;
2595 
   reg [32:1] polynom;
2596 
   integer i;
2597 
 
2598 
   always @ (qi)
2599 
   begin
2600 
        case (length)
2601 
         2: polynom = 32'b11;                               // 0x3
2602 
         3: polynom = 32'b110;                              // 0x6
2603 
         4: polynom = 32'b1100;                             // 0xC
2604 
         5: polynom = 32'b10100;                            // 0x14
2605 
         6: polynom = 32'b110000;                           // 0x30
2606 
         7: polynom = 32'b1100000;                          // 0x60
2607 
         8: polynom = 32'b10111000;                         // 0xb8
2608 
         9: polynom = 32'b100010000;                        // 0x110
2609 
        10: polynom = 32'b1001000000;                       // 0x240
2610 
        11: polynom = 32'b10100000000;                      // 0x500
2611 
        12: polynom = 32'b100000101001;                     // 0x829
2612 
        13: polynom = 32'b1000000001100;                    // 0x100C
2613 
        14: polynom = 32'b10000000010101;                   // 0x2015
2614 
        15: polynom = 32'b110000000000000;                  // 0x6000
2615 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2616 
        17: polynom = 32'b10010000000000000;                // 0x12000
2617 
        18: polynom = 32'b100000010000000000;               // 0x20400
2618 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2619 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2620 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2621 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2622 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2623 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2624 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2625 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2626 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2627 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2628 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2629 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2630 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2631 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2632 
        default: polynom = 32'b0;
2633 
        endcase
2634 
        lfsr_fb = qi[length];
2635 
        for (i=length-1; i>=1; i=i-1) begin
2636 
            if (polynom[i])
2637 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2638 
        end
2639 
    end
2640 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2641 
 
2642 
   always @ (posedge clk or posedge rst)
2643 
     if (rst)
2644 
       qi <= {length{1'b0}};
2645 
     else
2646 
     if (cke)
2647 
       qi <= q_next;
2648 
 
2649 
 
2650 
 
2651 
   always @ (posedge clk or posedge rst)
2652 
     if (rst)
2653 
       zq <= 1'b1;
2654 
     else
2655 
     if (cke)
2656 
       zq <= q_next == {length{1'b0}};
2657 
endmodule
2658 
`endif
2659 40 unneback 
`ifdef CNT_LFSR_CE_ZQ
2660 6 unneback 
//////////////////////////////////////////////////////////////////////
2661 
////                                                              ////
2662 
////  Versatile counter                                           ////
2663 
////                                                              ////
2664 
////  Description                                                 ////
2665 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2666 
////  counter                                                     ////
2667 
////                                                              ////
2668 
////  To Do:                                                      ////
2669 
////   - add LFSR with more taps                                  ////
2670 
////                                                              ////
2671 
////  Author(s):                                                  ////
2672 
////      - Michael Unneback, unneback@opencores.org              ////
2673 
////        ORSoC AB                                              ////
2674 
////                                                              ////
2675 
//////////////////////////////////////////////////////////////////////
2676 
////                                                              ////
2677 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2678 
////                                                              ////
2679 
//// This source file may be used and distributed without         ////
2680 
//// restriction provided that this copyright statement is not    ////
2681 
//// removed from the file and that any derivative work contains  ////
2682 
//// the original copyright notice and the associated disclaimer. ////
2683 
////                                                              ////
2684 
//// This source file is free software; you can redistribute it   ////
2685 
//// and/or modify it under the terms of the GNU Lesser General   ////
2686 
//// Public License as published by the Free Software Foundation; ////
2687 
//// either version 2.1 of the License, or (at your option) any   ////
2688 
//// later version.                                               ////
2689 
////                                                              ////
2690 
//// This source is distributed in the hope that it will be       ////
2691 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2692 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2693 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2694 
//// details.                                                     ////
2695 
////                                                              ////
2696 
//// You should have received a copy of the GNU Lesser General    ////
2697 
//// Public License along with this source; if not, download it   ////
2698 
//// from http://www.opencores.org/lgpl.shtml                     ////
2699 
////                                                              ////
2700 
//////////////////////////////////////////////////////////////////////
2701 
 
2702 
// LFSR counter
2703 
 
2704 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2705 
module `BASE`MODULE (
2706 
`undef MODULE
2707 
 cke, zq, rst, clk);
2708 
 
2709 6 unneback 
   parameter length = 4;
2710 
   input cke;
2711 
   output reg zq;
2712 
   input rst;
2713 
   input clk;
2714 
 
2715 
   parameter clear_value = 0;
2716 
   parameter set_value = 1;
2717 
   parameter wrap_value = 8;
2718 
   parameter level1_value = 15;
2719 
 
2720 
   reg  [length:1] qi;
2721 
   reg lfsr_fb;
2722 
   wire [length:1] q_next;
2723 
   reg [32:1] polynom;
2724 
   integer i;
2725 
 
2726 
   always @ (qi)
2727 
   begin
2728 
        case (length)
2729 
         2: polynom = 32'b11;                               // 0x3
2730 
         3: polynom = 32'b110;                              // 0x6
2731 
         4: polynom = 32'b1100;                             // 0xC
2732 
         5: polynom = 32'b10100;                            // 0x14
2733 
         6: polynom = 32'b110000;                           // 0x30
2734 
         7: polynom = 32'b1100000;                          // 0x60
2735 
         8: polynom = 32'b10111000;                         // 0xb8
2736 
         9: polynom = 32'b100010000;                        // 0x110
2737 
        10: polynom = 32'b1001000000;                       // 0x240
2738 
        11: polynom = 32'b10100000000;                      // 0x500
2739 
        12: polynom = 32'b100000101001;                     // 0x829
2740 
        13: polynom = 32'b1000000001100;                    // 0x100C
2741 
        14: polynom = 32'b10000000010101;                   // 0x2015
2742 
        15: polynom = 32'b110000000000000;                  // 0x6000
2743 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2744 
        17: polynom = 32'b10010000000000000;                // 0x12000
2745 
        18: polynom = 32'b100000010000000000;               // 0x20400
2746 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2747 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2748 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2749 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2750 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2751 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2752 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2753 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2754 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2755 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2756 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2757 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2758 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2759 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2760 
        default: polynom = 32'b0;
2761 
        endcase
2762 
        lfsr_fb = qi[length];
2763 
        for (i=length-1; i>=1; i=i-1) begin
2764 
            if (polynom[i])
2765 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2766 
        end
2767 
    end
2768 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2769 
 
2770 
   always @ (posedge clk or posedge rst)
2771 
     if (rst)
2772 
       qi <= {length{1'b0}};
2773 
     else
2774 
     if (cke)
2775 
       qi <= q_next;
2776 
 
2777 
 
2778 
 
2779 
   always @ (posedge clk or posedge rst)
2780 
     if (rst)
2781 
       zq <= 1'b1;
2782 
     else
2783 
     if (cke)
2784 
       zq <= q_next == {length{1'b0}};
2785 
endmodule
2786 40 unneback 
`endif
2787 
`ifdef CNT_LFSR_CE_Q
2788 6 unneback 
//////////////////////////////////////////////////////////////////////
2789 
////                                                              ////
2790 
////  Versatile counter                                           ////
2791 
////                                                              ////
2792 
////  Description                                                 ////
2793 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2794 
////  counter                                                     ////
2795 
////                                                              ////
2796 
////  To Do:                                                      ////
2797 
////   - add LFSR with more taps                                  ////
2798 
////                                                              ////
2799 
////  Author(s):                                                  ////
2800 
////      - Michael Unneback, unneback@opencores.org              ////
2801 
////        ORSoC AB                                              ////
2802 
////                                                              ////
2803 
//////////////////////////////////////////////////////////////////////
2804 
////                                                              ////
2805 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2806 
////                                                              ////
2807 
//// This source file may be used and distributed without         ////
2808 
//// restriction provided that this copyright statement is not    ////
2809 
//// removed from the file and that any derivative work contains  ////
2810 
//// the original copyright notice and the associated disclaimer. ////
2811 
////                                                              ////
2812 
//// This source file is free software; you can redistribute it   ////
2813 
//// and/or modify it under the terms of the GNU Lesser General   ////
2814 
//// Public License as published by the Free Software Foundation; ////
2815 
//// either version 2.1 of the License, or (at your option) any   ////
2816 
//// later version.                                               ////
2817 
////                                                              ////
2818 
//// This source is distributed in the hope that it will be       ////
2819 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2820 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2821 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2822 
//// details.                                                     ////
2823 
////                                                              ////
2824 
//// You should have received a copy of the GNU Lesser General    ////
2825 
//// Public License along with this source; if not, download it   ////
2826 
//// from http://www.opencores.org/lgpl.shtml                     ////
2827 
////                                                              ////
2828 
//////////////////////////////////////////////////////////////////////
2829 22 unneback 
 
2830 
// LFSR counter
2831 27 unneback 
 
2832 40 unneback 
`define MODULE cnt_lfsr_ce_q
2833 
module `BASE`MODULE (
2834 
`undef MODULE
2835 
 cke, q, rst, clk);
2836 
 
2837 27 unneback 
   parameter length = 4;
2838 
   input cke;
2839 
   output [length:1] q;
2840 
   input rst;
2841 
   input clk;
2842 
 
2843 
   parameter clear_value = 0;
2844 
   parameter set_value = 1;
2845 
   parameter wrap_value = 8;
2846 
   parameter level1_value = 15;
2847 
 
2848 
   reg  [length:1] qi;
2849 
   reg lfsr_fb;
2850 
   wire [length:1] q_next;
2851 
   reg [32:1] polynom;
2852 
   integer i;
2853 
 
2854 
   always @ (qi)
2855 
   begin
2856 
        case (length)
2857 
         2: polynom = 32'b11;                               // 0x3
2858 
         3: polynom = 32'b110;                              // 0x6
2859 
         4: polynom = 32'b1100;                             // 0xC
2860 
         5: polynom = 32'b10100;                            // 0x14
2861 
         6: polynom = 32'b110000;                           // 0x30
2862 
         7: polynom = 32'b1100000;                          // 0x60
2863 
         8: polynom = 32'b10111000;                         // 0xb8
2864 
         9: polynom = 32'b100010000;                        // 0x110
2865 
        10: polynom = 32'b1001000000;                       // 0x240
2866 
        11: polynom = 32'b10100000000;                      // 0x500
2867 
        12: polynom = 32'b100000101001;                     // 0x829
2868 
        13: polynom = 32'b1000000001100;                    // 0x100C
2869 
        14: polynom = 32'b10000000010101;                   // 0x2015
2870 
        15: polynom = 32'b110000000000000;                  // 0x6000
2871 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2872 
        17: polynom = 32'b10010000000000000;                // 0x12000
2873 
        18: polynom = 32'b100000010000000000;               // 0x20400
2874 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2875 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2876 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2877 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2878 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2879 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2880 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2881 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2882 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2883 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2884 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2885 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2886 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2887 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2888 
        default: polynom = 32'b0;
2889 
        endcase
2890 
        lfsr_fb = qi[length];
2891 
        for (i=length-1; i>=1; i=i-1) begin
2892 
            if (polynom[i])
2893 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2894 
        end
2895 
    end
2896 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2897 
 
2898 
   always @ (posedge clk or posedge rst)
2899 
     if (rst)
2900 
       qi <= {length{1'b0}};
2901 
     else
2902 
     if (cke)
2903 
       qi <= q_next;
2904 
 
2905 
   assign q = qi;
2906 
 
2907 
endmodule
2908 40 unneback 
`endif
2909 
`ifdef CNT_LFSR_CE_CLEAR_Q
2910 27 unneback 
//////////////////////////////////////////////////////////////////////
2911 
////                                                              ////
2912 
////  Versatile counter                                           ////
2913 
////                                                              ////
2914 
////  Description                                                 ////
2915 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2916 
////  counter                                                     ////
2917 
////                                                              ////
2918 
////  To Do:                                                      ////
2919 
////   - add LFSR with more taps                                  ////
2920 
////                                                              ////
2921 
////  Author(s):                                                  ////
2922 
////      - Michael Unneback, unneback@opencores.org              ////
2923 
////        ORSoC AB                                              ////
2924 
////                                                              ////
2925 
//////////////////////////////////////////////////////////////////////
2926 
////                                                              ////
2927 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2928 
////                                                              ////
2929 
//// This source file may be used and distributed without         ////
2930 
//// restriction provided that this copyright statement is not    ////
2931 
//// removed from the file and that any derivative work contains  ////
2932 
//// the original copyright notice and the associated disclaimer. ////
2933 
////                                                              ////
2934 
//// This source file is free software; you can redistribute it   ////
2935 
//// and/or modify it under the terms of the GNU Lesser General   ////
2936 
//// Public License as published by the Free Software Foundation; ////
2937 
//// either version 2.1 of the License, or (at your option) any   ////
2938 
//// later version.                                               ////
2939 
////                                                              ////
2940 
//// This source is distributed in the hope that it will be       ////
2941 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2942 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2943 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2944 
//// details.                                                     ////
2945 
////                                                              ////
2946 
//// You should have received a copy of the GNU Lesser General    ////
2947 
//// Public License along with this source; if not, download it   ////
2948 
//// from http://www.opencores.org/lgpl.shtml                     ////
2949 
////                                                              ////
2950 
//////////////////////////////////////////////////////////////////////
2951 
 
2952 
// LFSR counter
2953 
 
2954 40 unneback 
`define MODULE cnt_lfsr_ce_clear_q
2955 
module `BASE`MODULE (
2956 
`undef MODULE
2957 
 clear, cke, q, rst, clk);
2958 
 
2959 27 unneback 
   parameter length = 4;
2960 
   input clear;
2961 
   input cke;
2962 
   output [length:1] q;
2963 
   input rst;
2964 
   input clk;
2965 
 
2966 
   parameter clear_value = 0;
2967 
   parameter set_value = 1;
2968 
   parameter wrap_value = 8;
2969 
   parameter level1_value = 15;
2970 
 
2971 
   reg  [length:1] qi;
2972 
   reg lfsr_fb;
2973 
   wire [length:1] q_next;
2974 
   reg [32:1] polynom;
2975 
   integer i;
2976 
 
2977 
   always @ (qi)
2978 
   begin
2979 
        case (length)
2980 
         2: polynom = 32'b11;                               // 0x3
2981 
         3: polynom = 32'b110;                              // 0x6
2982 
         4: polynom = 32'b1100;                             // 0xC
2983 
         5: polynom = 32'b10100;                            // 0x14
2984 
         6: polynom = 32'b110000;                           // 0x30
2985 
         7: polynom = 32'b1100000;                          // 0x60
2986 
         8: polynom = 32'b10111000;                         // 0xb8
2987 
         9: polynom = 32'b100010000;                        // 0x110
2988 
        10: polynom = 32'b1001000000;                       // 0x240
2989 
        11: polynom = 32'b10100000000;                      // 0x500
2990 
        12: polynom = 32'b100000101001;                     // 0x829
2991 
        13: polynom = 32'b1000000001100;                    // 0x100C
2992 
        14: polynom = 32'b10000000010101;                   // 0x2015
2993 
        15: polynom = 32'b110000000000000;                  // 0x6000
2994 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2995 
        17: polynom = 32'b10010000000000000;                // 0x12000
2996 
        18: polynom = 32'b100000010000000000;               // 0x20400
2997 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2998 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2999 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3000 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3001 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3002 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3003 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3004 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3005 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3006 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3007 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3008 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3009 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3010 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3011 
        default: polynom = 32'b0;
3012 
        endcase
3013 
        lfsr_fb = qi[length];
3014 
        for (i=length-1; i>=1; i=i-1) begin
3015 
            if (polynom[i])
3016 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3017 
        end
3018 
    end
3019 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3020 
 
3021 
   always @ (posedge clk or posedge rst)
3022 
     if (rst)
3023 
       qi <= {length{1'b0}};
3024 
     else
3025 
     if (cke)
3026 
       qi <= q_next;
3027 
 
3028 
   assign q = qi;
3029 
 
3030 
endmodule
3031 40 unneback 
`endif
3032 
`ifdef CNT_LFSR_CE_Q_ZQ
3033 27 unneback 
//////////////////////////////////////////////////////////////////////
3034 
////                                                              ////
3035 
////  Versatile counter                                           ////
3036 
////                                                              ////
3037 
////  Description                                                 ////
3038 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3039 
////  counter                                                     ////
3040 
////                                                              ////
3041 
////  To Do:                                                      ////
3042 
////   - add LFSR with more taps                                  ////
3043 
////                                                              ////
3044 
////  Author(s):                                                  ////
3045 
////      - Michael Unneback, unneback@opencores.org              ////
3046 
////        ORSoC AB                                              ////
3047 
////                                                              ////
3048 
//////////////////////////////////////////////////////////////////////
3049 
////                                                              ////
3050 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3051 
////                                                              ////
3052 
//// This source file may be used and distributed without         ////
3053 
//// restriction provided that this copyright statement is not    ////
3054 
//// removed from the file and that any derivative work contains  ////
3055 
//// the original copyright notice and the associated disclaimer. ////
3056 
////                                                              ////
3057 
//// This source file is free software; you can redistribute it   ////
3058 
//// and/or modify it under the terms of the GNU Lesser General   ////
3059 
//// Public License as published by the Free Software Foundation; ////
3060 
//// either version 2.1 of the License, or (at your option) any   ////
3061 
//// later version.                                               ////
3062 
////                                                              ////
3063 
//// This source is distributed in the hope that it will be       ////
3064 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3065 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3066 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3067 
//// details.                                                     ////
3068 
////                                                              ////
3069 
//// You should have received a copy of the GNU Lesser General    ////
3070 
//// Public License along with this source; if not, download it   ////
3071 
//// from http://www.opencores.org/lgpl.shtml                     ////
3072 
////                                                              ////
3073 
//////////////////////////////////////////////////////////////////////
3074 
 
3075 
// LFSR counter
3076 22 unneback 
 
3077 40 unneback 
`define MODULE cnt_lfsr_ce_q_zq
3078 
module `BASE`MODULE (
3079 
`undef MODULE
3080 
 cke, q, zq, rst, clk);
3081 
 
3082 22 unneback 
   parameter length = 4;
3083 
   input cke;
3084 
   output [length:1] q;
3085 
   output reg zq;
3086 
   input rst;
3087 
   input clk;
3088 
 
3089 
   parameter clear_value = 0;
3090 
   parameter set_value = 1;
3091 
   parameter wrap_value = 8;
3092 
   parameter level1_value = 15;
3093 
 
3094 
   reg  [length:1] qi;
3095 
   reg lfsr_fb;
3096 
   wire [length:1] q_next;
3097 
   reg [32:1] polynom;
3098 
   integer i;
3099 
 
3100 
   always @ (qi)
3101 
   begin
3102 
        case (length)
3103 
         2: polynom = 32'b11;                               // 0x3
3104 
         3: polynom = 32'b110;                              // 0x6
3105 
         4: polynom = 32'b1100;                             // 0xC
3106 
         5: polynom = 32'b10100;                            // 0x14
3107 
         6: polynom = 32'b110000;                           // 0x30
3108 
         7: polynom = 32'b1100000;                          // 0x60
3109 
         8: polynom = 32'b10111000;                         // 0xb8
3110 
         9: polynom = 32'b100010000;                        // 0x110
3111 
        10: polynom = 32'b1001000000;                       // 0x240
3112 
        11: polynom = 32'b10100000000;                      // 0x500
3113 
        12: polynom = 32'b100000101001;                     // 0x829
3114 
        13: polynom = 32'b1000000001100;                    // 0x100C
3115 
        14: polynom = 32'b10000000010101;                   // 0x2015
3116 
        15: polynom = 32'b110000000000000;                  // 0x6000
3117 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3118 
        17: polynom = 32'b10010000000000000;                // 0x12000
3119 
        18: polynom = 32'b100000010000000000;               // 0x20400
3120 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3121 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3122 22 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3123 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3124 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3125 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3126 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3127 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3128 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3129 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3130 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3131 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3132 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3133 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3134 
        default: polynom = 32'b0;
3135 
        endcase
3136 
        lfsr_fb = qi[length];
3137 
        for (i=length-1; i>=1; i=i-1) begin
3138 
            if (polynom[i])
3139 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3140 
        end
3141 
    end
3142 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3143 
 
3144 
   always @ (posedge clk or posedge rst)
3145 
     if (rst)
3146 
       qi <= {length{1'b0}};
3147 
     else
3148 
     if (cke)
3149 
       qi <= q_next;
3150 
 
3151 
   assign q = qi;
3152 
 
3153 
 
3154 
   always @ (posedge clk or posedge rst)
3155 
     if (rst)
3156 
       zq <= 1'b1;
3157 
     else
3158 
     if (cke)
3159 
       zq <= q_next == {length{1'b0}};
3160 
endmodule
3161 40 unneback 
`endif
3162 
`ifdef CNT_LFSR_CE_REW_L1
3163 22 unneback 
//////////////////////////////////////////////////////////////////////
3164 
////                                                              ////
3165 
////  Versatile counter                                           ////
3166 
////                                                              ////
3167 
////  Description                                                 ////
3168 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3169 
////  counter                                                     ////
3170 
////                                                              ////
3171 
////  To Do:                                                      ////
3172 
////   - add LFSR with more taps                                  ////
3173 
////                                                              ////
3174 
////  Author(s):                                                  ////
3175 
////      - Michael Unneback, unneback@opencores.org              ////
3176 
////        ORSoC AB                                              ////
3177 
////                                                              ////
3178 
//////////////////////////////////////////////////////////////////////
3179 
////                                                              ////
3180 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3181 
////                                                              ////
3182 
//// This source file may be used and distributed without         ////
3183 
//// restriction provided that this copyright statement is not    ////
3184 
//// removed from the file and that any derivative work contains  ////
3185 
//// the original copyright notice and the associated disclaimer. ////
3186 
////                                                              ////
3187 
//// This source file is free software; you can redistribute it   ////
3188 
//// and/or modify it under the terms of the GNU Lesser General   ////
3189 
//// Public License as published by the Free Software Foundation; ////
3190 
//// either version 2.1 of the License, or (at your option) any   ////
3191 
//// later version.                                               ////
3192 
////                                                              ////
3193 
//// This source is distributed in the hope that it will be       ////
3194 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3195 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3196 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3197 
//// details.                                                     ////
3198 
////                                                              ////
3199 
//// You should have received a copy of the GNU Lesser General    ////
3200 
//// Public License along with this source; if not, download it   ////
3201 
//// from http://www.opencores.org/lgpl.shtml                     ////
3202 
////                                                              ////
3203 
//////////////////////////////////////////////////////////////////////
3204 6 unneback 
 
3205 
// LFSR counter
3206 
 
3207 40 unneback 
`define MODULE cnt_lfsr_ce_rew_l1
3208 
module `BASE`MODULE (
3209 
`undef MODULE
3210 
 cke, rew, level1, rst, clk);
3211 
 
3212 6 unneback 
   parameter length = 4;
3213 
   input cke;
3214 
   input rew;
3215 
   output reg level1;
3216 
   input rst;
3217 
   input clk;
3218 
 
3219 
   parameter clear_value = 0;
3220 
   parameter set_value = 1;
3221 
   parameter wrap_value = 8;
3222 
   parameter level1_value = 15;
3223 
 
3224 29 unneback 
   wire clear;
3225 30 unneback 
   assign clear = 1'b0;
3226 6 unneback 
   reg  [length:1] qi;
3227 
   reg lfsr_fb, lfsr_fb_rew;
3228 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
3229 
   reg [32:1] polynom_rew;
3230 
   integer j;
3231 
   reg [32:1] polynom;
3232 
   integer i;
3233 
 
3234 
   always @ (qi)
3235 
   begin
3236 
        case (length)
3237 
         2: polynom = 32'b11;                               // 0x3
3238 
         3: polynom = 32'b110;                              // 0x6
3239 
         4: polynom = 32'b1100;                             // 0xC
3240 
         5: polynom = 32'b10100;                            // 0x14
3241 
         6: polynom = 32'b110000;                           // 0x30
3242 
         7: polynom = 32'b1100000;                          // 0x60
3243 
         8: polynom = 32'b10111000;                         // 0xb8
3244 
         9: polynom = 32'b100010000;                        // 0x110
3245 
        10: polynom = 32'b1001000000;                       // 0x240
3246 
        11: polynom = 32'b10100000000;                      // 0x500
3247 
        12: polynom = 32'b100000101001;                     // 0x829
3248 
        13: polynom = 32'b1000000001100;                    // 0x100C
3249 
        14: polynom = 32'b10000000010101;                   // 0x2015
3250 
        15: polynom = 32'b110000000000000;                  // 0x6000
3251 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3252 
        17: polynom = 32'b10010000000000000;                // 0x12000
3253 
        18: polynom = 32'b100000010000000000;               // 0x20400
3254 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3255 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3256 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3257 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3258 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3259 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3260 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3261 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3262 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3263 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3264 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3265 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3266 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3267 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3268 
        default: polynom = 32'b0;
3269 
        endcase
3270 
        lfsr_fb = qi[length];
3271 
        for (i=length-1; i>=1; i=i-1) begin
3272 
            if (polynom[i])
3273 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3274 
        end
3275 
    end
3276 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3277 
   always @ (qi)
3278 
   begin
3279 
        case (length)
3280 
         2: polynom_rew = 32'b11;
3281 
         3: polynom_rew = 32'b110;
3282 
         4: polynom_rew = 32'b1100;
3283 
         5: polynom_rew = 32'b10100;
3284 
         6: polynom_rew = 32'b110000;
3285 
         7: polynom_rew = 32'b1100000;
3286 
         8: polynom_rew = 32'b10111000;
3287 
         9: polynom_rew = 32'b100010000;
3288 
        10: polynom_rew = 32'b1001000000;
3289 
        11: polynom_rew = 32'b10100000000;
3290 
        12: polynom_rew = 32'b100000101001;
3291 
        13: polynom_rew = 32'b1000000001100;
3292 
        14: polynom_rew = 32'b10000000010101;
3293 
        15: polynom_rew = 32'b110000000000000;
3294 
        16: polynom_rew = 32'b1101000000001000;
3295 
        17: polynom_rew = 32'b10010000000000000;
3296 
        18: polynom_rew = 32'b100000010000000000;
3297 
        19: polynom_rew = 32'b1000000000000100011;
3298 
        20: polynom_rew = 32'b10000010000000000000;
3299 
        21: polynom_rew = 32'b101000000000000000000;
3300 
        22: polynom_rew = 32'b1100000000000000000000;
3301 
        23: polynom_rew = 32'b10000100000000000000000;
3302 
        24: polynom_rew = 32'b111000010000000000000000;
3303 
        25: polynom_rew = 32'b1001000000000000000000000;
3304 
        26: polynom_rew = 32'b10000000000000000000100011;
3305 
        27: polynom_rew = 32'b100000000000000000000010011;
3306 
        28: polynom_rew = 32'b1100100000000000000000000000;
3307 
        29: polynom_rew = 32'b10100000000000000000000000000;
3308 
        30: polynom_rew = 32'b100000000000000000000000101001;
3309 
        31: polynom_rew = 32'b1001000000000000000000000000000;
3310 
        32: polynom_rew = 32'b10000000001000000000000000000011;
3311 
        default: polynom_rew = 32'b0;
3312 
        endcase
3313 
        // rotate left
3314 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3315 
        lfsr_fb_rew = qi[length];
3316 
        for (i=length-1; i>=1; i=i-1) begin
3317 
            if (polynom_rew[i])
3318 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3319 
        end
3320 
    end
3321 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3322 
   assign q_next = rew ? q_next_rew : q_next_fw;
3323 
 
3324 
   always @ (posedge clk or posedge rst)
3325 
     if (rst)
3326 
       qi <= {length{1'b0}};
3327 
     else
3328 
     if (cke)
3329 
       qi <= q_next;
3330 
 
3331 
 
3332 
 
3333 
    always @ (posedge clk or posedge rst)
3334 
    if (rst)
3335 
        level1 <= 1'b0;
3336 
    else
3337 
    if (cke)
3338 29 unneback 
    if (clear)
3339 
        level1 <= 1'b0;
3340 
    else if (q_next == level1_value)
3341 6 unneback 
        level1 <= 1'b1;
3342 
    else if (qi == level1_value & rew)
3343 
        level1 <= 1'b0;
3344 
endmodule
3345 40 unneback 
`endif
3346 
`ifdef CNT_GRAY
3347 6 unneback 
//////////////////////////////////////////////////////////////////////
3348 
////                                                              ////
3349 
////  Versatile counter                                           ////
3350 
////                                                              ////
3351 
////  Description                                                 ////
3352 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3353 
////  counter                                                     ////
3354 
////                                                              ////
3355 
////  To Do:                                                      ////
3356 
////   - add LFSR with more taps                                  ////
3357 
////                                                              ////
3358 
////  Author(s):                                                  ////
3359 
////      - Michael Unneback, unneback@opencores.org              ////
3360 
////        ORSoC AB                                              ////
3361 
////                                                              ////
3362 
//////////////////////////////////////////////////////////////////////
3363 
////                                                              ////
3364 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3365 
////                                                              ////
3366 
//// This source file may be used and distributed without         ////
3367 
//// restriction provided that this copyright statement is not    ////
3368 
//// removed from the file and that any derivative work contains  ////
3369 
//// the original copyright notice and the associated disclaimer. ////
3370 
////                                                              ////
3371 
//// This source file is free software; you can redistribute it   ////
3372 
//// and/or modify it under the terms of the GNU Lesser General   ////
3373 
//// Public License as published by the Free Software Foundation; ////
3374 
//// either version 2.1 of the License, or (at your option) any   ////
3375 
//// later version.                                               ////
3376 
////                                                              ////
3377 
//// This source is distributed in the hope that it will be       ////
3378 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3379 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3380 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3381 
//// details.                                                     ////
3382 
////                                                              ////
3383 
//// You should have received a copy of the GNU Lesser General    ////
3384 
//// Public License along with this source; if not, download it   ////
3385 
//// from http://www.opencores.org/lgpl.shtml                     ////
3386 
////                                                              ////
3387 
//////////////////////////////////////////////////////////////////////
3388 
 
3389 
// GRAY counter
3390 
 
3391 40 unneback 
`define MODULE cnt_gray
3392 
module `BASE`MODULE (
3393 
`undef MODULE
3394 
 q, rst, clk);
3395 
 
3396 6 unneback 
   parameter length = 4;
3397 
   output reg [length:1] q;
3398 
   input rst;
3399 
   input clk;
3400 
 
3401 
   parameter clear_value = 0;
3402 
   parameter set_value = 1;
3403 
   parameter wrap_value = 8;
3404 
   parameter level1_value = 15;
3405 
 
3406 
   reg  [length:1] qi;
3407 
   wire [length:1] q_next;
3408 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3409 
 
3410 
   always @ (posedge clk or posedge rst)
3411 
     if (rst)
3412 
       qi <= {length{1'b0}};
3413 
     else
3414 
       qi <= q_next;
3415 
 
3416 
   always @ (posedge clk or posedge rst)
3417 
     if (rst)
3418 
       q <= {length{1'b0}};
3419 
     else
3420 
         q <= (q_next>>1) ^ q_next;
3421 
 
3422 
endmodule
3423 40 unneback 
`endif
3424 
`ifdef CNT_GRAY_CE
3425 6 unneback 
//////////////////////////////////////////////////////////////////////
3426 
////                                                              ////
3427 
////  Versatile counter                                           ////
3428 
////                                                              ////
3429 
////  Description                                                 ////
3430 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3431 
////  counter                                                     ////
3432 
////                                                              ////
3433 
////  To Do:                                                      ////
3434 
////   - add LFSR with more taps                                  ////
3435 
////                                                              ////
3436 
////  Author(s):                                                  ////
3437 
////      - Michael Unneback, unneback@opencores.org              ////
3438 
////        ORSoC AB                                              ////
3439 
////                                                              ////
3440 
//////////////////////////////////////////////////////////////////////
3441 
////                                                              ////
3442 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3443 
////                                                              ////
3444 
//// This source file may be used and distributed without         ////
3445 
//// restriction provided that this copyright statement is not    ////
3446 
//// removed from the file and that any derivative work contains  ////
3447 
//// the original copyright notice and the associated disclaimer. ////
3448 
////                                                              ////
3449 
//// This source file is free software; you can redistribute it   ////
3450 
//// and/or modify it under the terms of the GNU Lesser General   ////
3451 
//// Public License as published by the Free Software Foundation; ////
3452 
//// either version 2.1 of the License, or (at your option) any   ////
3453 
//// later version.                                               ////
3454 
////                                                              ////
3455 
//// This source is distributed in the hope that it will be       ////
3456 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3457 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3458 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3459 
//// details.                                                     ////
3460 
////                                                              ////
3461 
//// You should have received a copy of the GNU Lesser General    ////
3462 
//// Public License along with this source; if not, download it   ////
3463 
//// from http://www.opencores.org/lgpl.shtml                     ////
3464 
////                                                              ////
3465 
//////////////////////////////////////////////////////////////////////
3466 
 
3467 
// GRAY counter
3468 
 
3469 40 unneback 
`define MODULE cnt_gray_ce
3470 
module `BASE`MODULE (
3471 
`undef MODULE
3472 
 cke, q, rst, clk);
3473 
 
3474 6 unneback 
   parameter length = 4;
3475 
   input cke;
3476 
   output reg [length:1] q;
3477 
   input rst;
3478 
   input clk;
3479 
 
3480 
   parameter clear_value = 0;
3481 
   parameter set_value = 1;
3482 
   parameter wrap_value = 8;
3483 
   parameter level1_value = 15;
3484 
 
3485 
   reg  [length:1] qi;
3486 
   wire [length:1] q_next;
3487 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3488 
 
3489 
   always @ (posedge clk or posedge rst)
3490 
     if (rst)
3491 
       qi <= {length{1'b0}};
3492 
     else
3493 
     if (cke)
3494 
       qi <= q_next;
3495 
 
3496 
   always @ (posedge clk or posedge rst)
3497 
     if (rst)
3498 
       q <= {length{1'b0}};
3499 
     else
3500 
       if (cke)
3501 
         q <= (q_next>>1) ^ q_next;
3502 
 
3503 
endmodule
3504 40 unneback 
`endif
3505 
`ifdef CNT_GRAY_CE_BIN
3506 6 unneback 
//////////////////////////////////////////////////////////////////////
3507 
////                                                              ////
3508 
////  Versatile counter                                           ////
3509 
////                                                              ////
3510 
////  Description                                                 ////
3511 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3512 
////  counter                                                     ////
3513 
////                                                              ////
3514 
////  To Do:                                                      ////
3515 
////   - add LFSR with more taps                                  ////
3516 
////                                                              ////
3517 
////  Author(s):                                                  ////
3518 
////      - Michael Unneback, unneback@opencores.org              ////
3519 
////        ORSoC AB                                              ////
3520 
////                                                              ////
3521 
//////////////////////////////////////////////////////////////////////
3522 
////                                                              ////
3523 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3524 
////                                                              ////
3525 
//// This source file may be used and distributed without         ////
3526 
//// restriction provided that this copyright statement is not    ////
3527 
//// removed from the file and that any derivative work contains  ////
3528 
//// the original copyright notice and the associated disclaimer. ////
3529 
////                                                              ////
3530 
//// This source file is free software; you can redistribute it   ////
3531 
//// and/or modify it under the terms of the GNU Lesser General   ////
3532 
//// Public License as published by the Free Software Foundation; ////
3533 
//// either version 2.1 of the License, or (at your option) any   ////
3534 
//// later version.                                               ////
3535 
////                                                              ////
3536 
//// This source is distributed in the hope that it will be       ////
3537 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3538 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3539 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3540 
//// details.                                                     ////
3541 
////                                                              ////
3542 
//// You should have received a copy of the GNU Lesser General    ////
3543 
//// Public License along with this source; if not, download it   ////
3544 
//// from http://www.opencores.org/lgpl.shtml                     ////
3545 
////                                                              ////
3546 
//////////////////////////////////////////////////////////////////////
3547 
 
3548 
// GRAY counter
3549 
 
3550 40 unneback 
`define MODULE cnt_gray_ce_bin
3551 
module `BASE`MODULE (
3552 
`undef MODULE
3553 
 cke, q, q_bin, rst, clk);
3554 
 
3555 6 unneback 
   parameter length = 4;
3556 
   input cke;
3557 
   output reg [length:1] q;
3558 
   output [length:1] q_bin;
3559 
   input rst;
3560 
   input clk;
3561 
 
3562 
   parameter clear_value = 0;
3563 
   parameter set_value = 1;
3564 
   parameter wrap_value = 8;
3565 
   parameter level1_value = 15;
3566 
 
3567 
   reg  [length:1] qi;
3568 
   wire [length:1] q_next;
3569 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3570 
 
3571 
   always @ (posedge clk or posedge rst)
3572 
     if (rst)
3573 
       qi <= {length{1'b0}};
3574 
     else
3575 
     if (cke)
3576 
       qi <= q_next;
3577 
 
3578 
   always @ (posedge clk or posedge rst)
3579 
     if (rst)
3580 
       q <= {length{1'b0}};
3581 
     else
3582 
       if (cke)
3583 
         q <= (q_next>>1) ^ q_next;
3584 
 
3585 
   assign q_bin = qi;
3586 
 
3587 
endmodule
3588 40 unneback 
`endif
3589 6 unneback 
//////////////////////////////////////////////////////////////////////
3590 
////                                                              ////
3591 
////  Versatile library, counters                                 ////
3592 
////                                                              ////
3593 
////  Description                                                 ////
3594 
////  counters                                                    ////
3595 
////                                                              ////
3596 
////                                                              ////
3597 
////  To Do:                                                      ////
3598 
////   - add more counters                                        ////
3599 
////                                                              ////
3600 
////  Author(s):                                                  ////
3601 
////      - Michael Unneback, unneback@opencores.org              ////
3602 
////        ORSoC AB                                              ////
3603 
////                                                              ////
3604 
//////////////////////////////////////////////////////////////////////
3605 
////                                                              ////
3606 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3607 
////                                                              ////
3608 
//// This source file may be used and distributed without         ////
3609 
//// restriction provided that this copyright statement is not    ////
3610 
//// removed from the file and that any derivative work contains  ////
3611 
//// the original copyright notice and the associated disclaimer. ////
3612 
////                                                              ////
3613 
//// This source file is free software; you can redistribute it   ////
3614 
//// and/or modify it under the terms of the GNU Lesser General   ////
3615 
//// Public License as published by the Free Software Foundation; ////
3616 
//// either version 2.1 of the License, or (at your option) any   ////
3617 
//// later version.                                               ////
3618 
////                                                              ////
3619 
//// This source is distributed in the hope that it will be       ////
3620 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3621 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3622 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3623 
//// details.                                                     ////
3624 
////                                                              ////
3625 
//// You should have received a copy of the GNU Lesser General    ////
3626 
//// Public License along with this source; if not, download it   ////
3627 
//// from http://www.opencores.org/lgpl.shtml                     ////
3628 
////                                                              ////
3629 
//////////////////////////////////////////////////////////////////////
3630 
 
3631 40 unneback 
`ifdef CNT_SHREG_WRAP
3632 
`define MODULE cnt_shreg_wrap
3633 
module `BASE`MODULE ( q, rst, clk);
3634 
`undef MODULE
3635 6 unneback 
 
3636 
   parameter length = 4;
3637 
   output reg [0:length-1] q;
3638 
   input rst;
3639 
   input clk;
3640 
 
3641 
    always @ (posedge clk or posedge rst)
3642 
    if (rst)
3643 
        q <= {1'b1,{length-1{1'b0}}};
3644 
    else
3645 
        q <= {q[length-1],q[0:length-2]};
3646 
 
3647 
endmodule
3648 40 unneback 
`endif
3649 6 unneback 
 
3650 40 unneback 
`ifdef CNT_SHREG_CE_WRAP
3651 
`define MODULE cnt_shreg_ce_wrap
3652 
module `BASE`MODULE ( cke, q, rst, clk);
3653 
`undef MODULE
3654 6 unneback 
 
3655 
   parameter length = 4;
3656 
   input cke;
3657 
   output reg [0:length-1] q;
3658 
   input rst;
3659 
   input clk;
3660 
 
3661 
    always @ (posedge clk or posedge rst)
3662 
    if (rst)
3663 
        q <= {1'b1,{length-1{1'b0}}};
3664 
    else
3665 
        if (cke)
3666 
            q <= {q[length-1],q[0:length-2]};
3667 
 
3668 
endmodule
3669 40 unneback 
`endif
3670 6 unneback 
 
3671 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR
3672 
`define MODULE cnt_shreg_ce_clear
3673 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3674 
`undef MODULE
3675 6 unneback 
 
3676 
   parameter length = 4;
3677 
   input cke, clear;
3678 
   output reg [0:length-1] q;
3679 
   input rst;
3680 
   input clk;
3681 
 
3682 
    always @ (posedge clk or posedge rst)
3683 
    if (rst)
3684 
        q <= {1'b1,{length-1{1'b0}}};
3685 
    else
3686 
        if (cke)
3687 
            if (clear)
3688 
                q <= {1'b1,{length-1{1'b0}}};
3689 
            else
3690 
                q <= q >> 1;
3691 
 
3692 
endmodule
3693 40 unneback 
`endif
3694 6 unneback 
 
3695 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3696 
`define MODULE cnt_shreg_ce_clear_wrap
3697 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3698 
`undef MODULE
3699 6 unneback 
 
3700 
   parameter length = 4;
3701 
   input cke, clear;
3702 
   output reg [0:length-1] q;
3703 
   input rst;
3704 
   input clk;
3705 
 
3706 
    always @ (posedge clk or posedge rst)
3707 
    if (rst)
3708 
        q <= {1'b1,{length-1{1'b0}}};
3709 
    else
3710 
        if (cke)
3711 
            if (clear)
3712 
                q <= {1'b1,{length-1{1'b0}}};
3713 
            else
3714 
            q <= {q[length-1],q[0:length-2]};
3715 
 
3716 
endmodule
3717 40 unneback 
`endif
3718 6 unneback 
//////////////////////////////////////////////////////////////////////
3719 
////                                                              ////
3720 
////  Versatile library, memories                                 ////
3721 
////                                                              ////
3722 
////  Description                                                 ////
3723 
////  memories                                                    ////
3724 
////                                                              ////
3725 
////                                                              ////
3726 
////  To Do:                                                      ////
3727 
////   - add more memory types                                    ////
3728 
////                                                              ////
3729 
////  Author(s):                                                  ////
3730 
////      - Michael Unneback, unneback@opencores.org              ////
3731 
////        ORSoC AB                                              ////
3732 
////                                                              ////
3733 
//////////////////////////////////////////////////////////////////////
3734 
////                                                              ////
3735 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3736 
////                                                              ////
3737 
//// This source file may be used and distributed without         ////
3738 
//// restriction provided that this copyright statement is not    ////
3739 
//// removed from the file and that any derivative work contains  ////
3740 
//// the original copyright notice and the associated disclaimer. ////
3741 
////                                                              ////
3742 
//// This source file is free software; you can redistribute it   ////
3743 
//// and/or modify it under the terms of the GNU Lesser General   ////
3744 
//// Public License as published by the Free Software Foundation; ////
3745 
//// either version 2.1 of the License, or (at your option) any   ////
3746 
//// later version.                                               ////
3747 
////                                                              ////
3748 
//// This source is distributed in the hope that it will be       ////
3749 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3750 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3751 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3752 
//// details.                                                     ////
3753 
////                                                              ////
3754 
//// You should have received a copy of the GNU Lesser General    ////
3755 
//// Public License along with this source; if not, download it   ////
3756 
//// from http://www.opencores.org/lgpl.shtml                     ////
3757 
////                                                              ////
3758 
//////////////////////////////////////////////////////////////////////
3759 
 
3760 40 unneback 
`ifdef ROM_INIT
3761 6 unneback 
/// ROM
3762 40 unneback 
`define MODULE rom_init
3763 
module `BASE`MODULE ( adr, q, clk);
3764 
`undef MODULE
3765 6 unneback 
 
3766 7 unneback 
   parameter data_width = 32;
3767 
   parameter addr_width = 8;
3768 75 unneback 
   parameter mem_size = 1<<addr_width;
3769 7 unneback 
   input [(addr_width-1):0]       adr;
3770 
   output reg [(data_width-1):0] q;
3771 
   input                         clk;
3772 75 unneback 
   reg [data_width-1:0] rom [mem_size-1:0];
3773 7 unneback 
   parameter memory_file = "vl_rom.vmem";
3774 
   initial
3775 
     begin
3776 
        $readmemh(memory_file, rom);
3777 
     end
3778 
 
3779 
   always @ (posedge clk)
3780 
     q <= rom[adr];
3781 6 unneback 
 
3782 7 unneback 
endmodule
3783 40 unneback 
`endif
3784 7 unneback 
 
3785 40 unneback 
`ifdef RAM
3786 
`define MODULE ram
3787 6 unneback 
// Single port RAM
3788 40 unneback 
module `BASE`MODULE ( d, adr, we, q, clk);
3789 
`undef MODULE
3790 6 unneback 
 
3791 
   parameter data_width = 32;
3792 
   parameter addr_width = 8;
3793 75 unneback 
   parameter mem_size = 1<<addr_width;
3794 100 unneback 
   parameter debug = 0;
3795 6 unneback 
   input [(data_width-1):0]      d;
3796 
   input [(addr_width-1):0]       adr;
3797 
   input                         we;
3798 7 unneback 
   output reg [(data_width-1):0] q;
3799 6 unneback 
   input                         clk;
3800 98 unneback 
   reg [data_width-1:0] ram [mem_size-1:0];
3801 100 unneback 
 
3802 
    parameter memory_init = 0;
3803 
    parameter memory_file = "vl_ram.vmem";
3804 
    generate
3805 
    if (memory_init == 1) begin : init_mem
3806 
        initial
3807 
            $readmemh(memory_file, ram);
3808 
   end else if (memory_init == 2) begin : init_zero
3809 
        integer k;
3810 
        initial
3811 
            for (k = 0; k < mem_size; k = k + 1)
3812 
                ram[k] = 0;
3813 7 unneback 
   end
3814 
   endgenerate
3815 
 
3816 100 unneback 
    generate
3817 
    if (debug==1) begin : debug_we
3818 
        always @ (posedge clk)
3819 
        if (we)
3820 
            $display ("Value %h written at address %h : time %t", d, adr, $time);
3821 
 
3822 
    end
3823 
    endgenerate
3824 
 
3825 6 unneback 
   always @ (posedge clk)
3826 
   begin
3827 
   if (we)
3828 
     ram[adr] <= d;
3829 
   q <= ram[adr];
3830 
   end
3831 
 
3832 
endmodule
3833 40 unneback 
`endif
3834 6 unneback 
 
3835 40 unneback 
`ifdef RAM_BE
3836 
`define MODULE ram_be
3837 91 unneback 
module `BASE`MODULE ( d, adr, be, we, q, clk);
3838 40 unneback 
`undef MODULE
3839 
 
3840 7 unneback 
   parameter data_width = 32;
3841 72 unneback 
   parameter addr_width = 6;
3842 75 unneback 
   parameter mem_size = 1<<addr_width;
3843 7 unneback 
   input [(data_width-1):0]      d;
3844 
   input [(addr_width-1):0]       adr;
3845 73 unneback 
   input [(data_width/8)-1:0]    be;
3846 7 unneback 
   input                         we;
3847 
   output reg [(data_width-1):0] q;
3848 
   input                         clk;
3849 
 
3850 85 unneback 
 
3851 65 unneback 
`ifdef SYSTEMVERILOG
3852 95 unneback 
    // use a multi-dimensional packed array
3853 
    //t o model individual bytes within the word
3854 
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
3855 65 unneback 
`else
3856 85 unneback 
    reg [data_width-1:0] ram [mem_size-1:0];
3857 
    wire [data_width/8-1:0] cke;
3858 65 unneback 
`endif
3859 
 
3860 100 unneback 
    parameter memory_init = 0;
3861 
    parameter memory_file = "vl_ram.vmem";
3862 
    generate
3863 
    if (memory_init == 1) begin : init_mem
3864 
        initial
3865 
            $readmemh(memory_file, ram);
3866 
    end else if (memory_init == 2) begin : init_zero
3867 
        integer k;
3868 
        initial
3869 
            for (k = 0; k < mem_size; k = k + 1)
3870 
                ram[k] = 0;
3871 
    end
3872 7 unneback 
   endgenerate
3873 
 
3874 60 unneback 
`ifdef SYSTEMVERILOG
3875 
 
3876 
always_ff@(posedge clk)
3877 
begin
3878 95 unneback 
    if(we) begin
3879 86 unneback 
        if(be[3]) ram[adr][3] <= d[31:24];
3880 
        if(be[2]) ram[adr][2] <= d[23:16];
3881 
        if(be[1]) ram[adr][1] <= d[15:8];
3882 
        if(be[0]) ram[adr][0] <= d[7:0];
3883 60 unneback 
    end
3884 90 unneback 
        q <= ram[adr];
3885 60 unneback 
end
3886 
 
3887 
`else
3888 
 
3889 85 unneback 
assign cke = {data_width/8{we}} & be;
3890 7 unneback 
   genvar i;
3891 85 unneback 
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
3892 7 unneback 
      always @ (posedge clk)
3893 85 unneback 
      if (cke[i])
3894 7 unneback 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3895 
   end
3896 
   endgenerate
3897 
 
3898 
   always @ (posedge clk)
3899 
      q <= ram[adr];
3900 
 
3901 60 unneback 
`endif
3902 
 
3903 93 unneback 
`ifdef verilator
3904 85 unneback 
   // Function to access RAM (for use by Verilator).
3905 
   function [31:0] get_mem;
3906 
      // verilator public
3907 90 unneback 
      input [addr_width-1:0]             addr;
3908 85 unneback 
      get_mem = ram[addr];
3909 
   endfunction // get_mem
3910 
 
3911 
   // Function to write RAM (for use by Verilator).
3912 
   function set_mem;
3913 
      // verilator public
3914 90 unneback 
      input [addr_width-1:0]             addr;
3915 
      input [data_width-1:0]             data;
3916 85 unneback 
      ram[addr] = data;
3917 
   endfunction // set_mem
3918 93 unneback 
`endif
3919 85 unneback 
 
3920 7 unneback 
endmodule
3921 40 unneback 
`endif
3922 7 unneback 
 
3923 40 unneback 
`ifdef DPRAM_1R1W
3924 
`define MODULE dpram_1r1w
3925 
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3926 
`undef MODULE
3927 6 unneback 
   parameter data_width = 32;
3928 
   parameter addr_width = 8;
3929 75 unneback 
   parameter mem_size = 1<<addr_width;
3930 6 unneback 
   input [(data_width-1):0]      d_a;
3931 
   input [(addr_width-1):0]       adr_a;
3932 
   input [(addr_width-1):0]       adr_b;
3933 
   input                         we_a;
3934 
   output [(data_width-1):0]      q_b;
3935 
   input                         clk_a, clk_b;
3936 
   reg [(addr_width-1):0]         adr_b_reg;
3937 100 unneback 
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
3938 7 unneback 
 
3939 100 unneback 
    parameter memory_init = 0;
3940 
    parameter memory_file = "vl_ram.vmem";
3941 
    parameter debug = 0;
3942 
 
3943 
    generate
3944 
    if (memory_init == 1) begin : init_mem
3945 
        initial
3946 
            $readmemh(memory_file, ram);
3947 
    end else if (memory_init == 2) begin : init_zero
3948 
        integer k;
3949 
        initial
3950 
            for (k = 0; k < mem_size; k = k + 1)
3951 
                ram[k] = 0;
3952 
    end
3953 7 unneback 
   endgenerate
3954 
 
3955 100 unneback 
    generate
3956 
    if (debug==1) begin : debug_we
3957 
        always @ (posedge clk_a)
3958 
        if (we_a)
3959 
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
3960 
 
3961 
    end
3962 
    endgenerate
3963 
 
3964 6 unneback 
   always @ (posedge clk_a)
3965 
   if (we_a)
3966 
     ram[adr_a] <= d_a;
3967 
   always @ (posedge clk_b)
3968 
   adr_b_reg <= adr_b;
3969 
   assign q_b = ram[adr_b_reg];
3970 40 unneback 
 
3971 6 unneback 
endmodule
3972 40 unneback 
`endif
3973 6 unneback 
 
3974 40 unneback 
`ifdef DPRAM_2R1W
3975 
`define MODULE dpram_2r1w
3976 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3977 
`undef MODULE
3978 
 
3979 6 unneback 
   parameter data_width = 32;
3980 
   parameter addr_width = 8;
3981 75 unneback 
   parameter mem_size = 1<<addr_width;
3982 6 unneback 
   input [(data_width-1):0]      d_a;
3983 
   input [(addr_width-1):0]       adr_a;
3984 
   input [(addr_width-1):0]       adr_b;
3985 
   input                         we_a;
3986 
   output [(data_width-1):0]      q_b;
3987 
   output reg [(data_width-1):0] q_a;
3988 
   input                         clk_a, clk_b;
3989 
   reg [(data_width-1):0]         q_b;
3990 98 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
3991 7 unneback 
 
3992 100 unneback 
    parameter memory_init = 0;
3993 
    parameter memory_file = "vl_ram.vmem";
3994 
    parameter debug = 0;
3995 
 
3996 
    generate
3997 
    if (memory_init == 1) begin : init_mem
3998 
        initial
3999 
            $readmemh(memory_file, ram);
4000 
    end else if (memory_init == 2) begin : init_zero
4001 
        integer k;
4002 
        initial
4003 
            for (k = 0; k < mem_size; k = k + 1)
4004 
                ram[k] = 0;
4005 
    end
4006 7 unneback 
   endgenerate
4007 
 
4008 100 unneback 
    generate
4009 
    if (debug==1) begin : debug_we
4010 
        always @ (posedge clk_a)
4011 
        if (we_a)
4012 
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4013 
 
4014 
    end
4015 
    endgenerate
4016 
 
4017 6 unneback 
   always @ (posedge clk_a)
4018 
     begin
4019 
        q_a <= ram[adr_a];
4020 
        if (we_a)
4021 
             ram[adr_a] <= d_a;
4022 
     end
4023 
   always @ (posedge clk_b)
4024 
          q_b <= ram[adr_b];
4025 
endmodule
4026 40 unneback 
`endif
4027 6 unneback 
 
4028 100 unneback 
`ifdef DPRAM_1R2W
4029 
`define MODULE dpram_1r2w
4030 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
4031 
`undef MODULE
4032 
 
4033 
   parameter data_width = 32;
4034 
   parameter addr_width = 8;
4035 
   parameter mem_size = 1<<addr_width;
4036 
   input [(data_width-1):0]      d_a;
4037 
   input [(addr_width-1):0]       adr_a;
4038 
   input [(addr_width-1):0]       adr_b;
4039 
   input                         we_a;
4040 
   input [(data_width-1):0]       d_b;
4041 
   output reg [(data_width-1):0] q_a;
4042 
   input                         we_b;
4043 
   input                         clk_a, clk_b;
4044 
   reg [(data_width-1):0]         q_b;
4045 
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
4046 
 
4047 
    parameter memory_init = 0;
4048 
    parameter memory_file = "vl_ram.vmem";
4049 
    parameter debug = 0;
4050 
 
4051 
    generate
4052 
    if (memory_init == 1) begin : init_mem
4053 
        initial
4054 
            $readmemh(memory_file, ram);
4055 
    end else if (memory_init == 2) begin : init_zero
4056 
        integer k;
4057 
        initial
4058 
            for (k = 0; k < mem_size; k = k + 1)
4059 
                ram[k] = 0;
4060 
    end
4061 
   endgenerate
4062 
 
4063 
    generate
4064 
    if (debug==1) begin : debug_we
4065 
        always @ (posedge clk_a)
4066 
        if (we_a)
4067 
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4068 
        always @ (posedge clk_b)
4069 
        if (we_b)
4070 
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4071 
    end
4072 
    endgenerate
4073 
 
4074 
   always @ (posedge clk_a)
4075 
     begin
4076 
        q_a <= ram[adr_a];
4077 
        if (we_a)
4078 
             ram[adr_a] <= d_a;
4079 
     end
4080 
   always @ (posedge clk_b)
4081 
     begin
4082 
        if (we_b)
4083 
          ram[adr_b] <= d_b;
4084 
     end
4085 
endmodule
4086 
`endif
4087 
 
4088 40 unneback 
`ifdef DPRAM_2R2W
4089 
`define MODULE dpram_2r2w
4090 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
4091 
`undef MODULE
4092 
 
4093 6 unneback 
   parameter data_width = 32;
4094 
   parameter addr_width = 8;
4095 75 unneback 
   parameter mem_size = 1<<addr_width;
4096 6 unneback 
   input [(data_width-1):0]      d_a;
4097 
   input [(addr_width-1):0]       adr_a;
4098 
   input [(addr_width-1):0]       adr_b;
4099 
   input                         we_a;
4100 
   output [(data_width-1):0]      q_b;
4101 
   input [(data_width-1):0]       d_b;
4102 
   output reg [(data_width-1):0] q_a;
4103 
   input                         we_b;
4104 
   input                         clk_a, clk_b;
4105 
   reg [(data_width-1):0]         q_b;
4106 98 unneback 
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
4107 7 unneback 
 
4108 100 unneback 
    parameter memory_init = 0;
4109 
    parameter memory_file = "vl_ram.vmem";
4110 
    parameter debug = 0;
4111 
 
4112 
    generate
4113 
    if (memory_init) begin : init_mem
4114 
        initial
4115 
            $readmemh(memory_file, ram);
4116 
    end else if (memory_init == 2) begin : init_zero
4117 
        integer k;
4118 
        initial
4119 
            for (k = 0; k < mem_size; k = k + 1)
4120 
                ram[k] = 0;
4121 
    end
4122 7 unneback 
   endgenerate
4123 
 
4124 100 unneback 
    generate
4125 
    if (debug==1) begin : debug_we
4126 
        always @ (posedge clk_a)
4127 
        if (we_a)
4128 
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4129 
        always @ (posedge clk_b)
4130 
        if (we_b)
4131 
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4132 
    end
4133 
    endgenerate
4134 
 
4135 6 unneback 
   always @ (posedge clk_a)
4136 
     begin
4137 
        q_a <= ram[adr_a];
4138 
        if (we_a)
4139 
             ram[adr_a] <= d_a;
4140 
     end
4141 
   always @ (posedge clk_b)
4142 
     begin
4143 
        q_b <= ram[adr_b];
4144 
        if (we_b)
4145 
          ram[adr_b] <= d_b;
4146 
     end
4147 
endmodule
4148 40 unneback 
`endif
4149 6 unneback 
 
4150 83 unneback 
 
4151 75 unneback 
`ifdef DPRAM_BE_2R2W
4152 
`define MODULE dpram_be_2r2w
4153 92 unneback 
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
4154 75 unneback 
`undef MODULE
4155 
 
4156 
   parameter a_data_width = 32;
4157 
   parameter a_addr_width = 8;
4158 95 unneback 
   parameter b_data_width = 64; //a_data_width;
4159 91 unneback 
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
4160 95 unneback 
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
4161 
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
4162 91 unneback 
 
4163 100 unneback 
   parameter memory_init = 0;
4164 95 unneback 
   parameter memory_file = "vl_ram.vmem";
4165 100 unneback 
   parameter debug = 0;
4166 95 unneback 
 
4167 75 unneback 
   input [(a_data_width-1):0]      d_a;
4168 91 unneback 
   input [(a_addr_width-1):0]       adr_a;
4169 
   input [(a_data_width/8-1):0]    be_a;
4170 
   input                           we_a;
4171 75 unneback 
   output reg [(a_data_width-1):0] q_a;
4172 91 unneback 
   input [(b_data_width-1):0]       d_b;
4173 
   input [(b_addr_width-1):0]       adr_b;
4174 92 unneback 
   input [(b_data_width/8-1):0]    be_b;
4175 
   input                           we_b;
4176 
   output reg [(b_data_width-1):0]          q_b;
4177 91 unneback 
   input                           clk_a, clk_b;
4178 75 unneback 
 
4179 100 unneback 
    generate
4180 
    if (debug==1) begin : debug_we
4181 
        always @ (posedge clk_a)
4182 
        if (we_a)
4183 
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4184 
        always @ (posedge clk_b)
4185 
        if (we_b)
4186 
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4187 
    end
4188 
    endgenerate
4189 
 
4190 
 
4191 91 unneback 
`ifdef SYSTEMVERILOG
4192 
// use a multi-dimensional packed array
4193 
//to model individual bytes within the word
4194 
 
4195 75 unneback 
generate
4196 91 unneback 
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
4197 75 unneback 
 
4198 98 unneback 
    logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4199 95 unneback 
 
4200 
    initial
4201 100 unneback 
        if (memory_init==1)
4202 95 unneback 
            $readmemh(memory_file, ram);
4203 100 unneback 
 
4204 
    integer k;
4205 
    initial
4206 
        if (memory_init==2)
4207 
            for (k = 0; k < mem_size; k = k + 1)
4208 
                ram[k] = 0;
4209 91 unneback 
 
4210 
    always_ff@(posedge clk_a)
4211 
    begin
4212 
        if(we_a) begin
4213 100 unneback 
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
4214 
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
4215 
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
4216 
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
4217 91 unneback 
        end
4218 
    end
4219 
 
4220 92 unneback 
    always@(posedge clk_a)
4221 
        q_a = ram[adr_a];
4222 91 unneback 
 
4223 
    always_ff@(posedge clk_b)
4224 92 unneback 
    begin
4225 
        if(we_b) begin
4226 100 unneback 
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
4227 
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
4228 
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
4229 
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
4230 92 unneback 
        end
4231 
    end
4232 91 unneback 
 
4233 92 unneback 
    always@(posedge clk_b)
4234 
        q_b = ram[adr_b];
4235 91 unneback 
 
4236 75 unneback 
end
4237 
endgenerate
4238 
 
4239 95 unneback 
generate
4240 
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
4241 
 
4242 98 unneback 
    logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4243 95 unneback 
 
4244 
    initial
4245 100 unneback 
        if (memory_init==1)
4246 95 unneback 
            $readmemh(memory_file, ram);
4247 100 unneback 
 
4248 
    integer k;
4249 
    initial
4250 
        if (memory_init==2)
4251 
            for (k = 0; k < mem_size; k = k + 1)
4252 
                ram[k] = 0;
4253 95 unneback 
 
4254 
    always_ff@(posedge clk_a)
4255 
    begin
4256 
        if(we_a) begin
4257 
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
4258 
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
4259 
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
4260 
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
4261 
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
4262 
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
4263 
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
4264 
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
4265 
        end
4266 
    end
4267 
 
4268 
    always@(posedge clk_a)
4269 
        q_a = ram[adr_a];
4270 
 
4271 
    always_ff@(posedge clk_b)
4272 
    begin
4273 
        if(we_b) begin
4274 
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
4275 
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
4276 
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
4277 
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
4278 
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
4279 
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
4280 
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
4281 
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
4282 
        end
4283 
    end
4284 
 
4285 
    always@(posedge clk_b)
4286 
        q_b = ram[adr_b];
4287 
 
4288 
end
4289 
endgenerate
4290 
 
4291 
generate
4292 
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
4293 
logic [31:0] temp;
4294 
`define MODULE dpram_be_2r2w
4295 100 unneback 
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file))
4296 95 unneback 
`undef MODULE
4297 
dpram6464 (
4298 
    .d_a(d_a),
4299 
    .q_a(q_a),
4300 
    .adr_a(adr_a),
4301 
    .be_a(be_a),
4302 
    .we_a(we_a),
4303 
    .clk_a(clk_a),
4304 
    .d_b({d_b,d_b}),
4305 
    .q_b(temp),
4306 
    .adr_b(adr_b),
4307 
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
4308 
    .we_b(we_b),
4309 
    .clk_b(clk_b)
4310 
);
4311 
 
4312 100 unneback 
always @ (adr_b[0] or temp)
4313 95 unneback 
    if (adr_b[0])
4314 
        q_b = temp[31:16];
4315 
    else
4316 
        q_b = temp[15:0];
4317 
 
4318 
end
4319 
endgenerate
4320 
 
4321 
generate
4322 
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
4323 
logic [63:0] temp;
4324 
`define MODULE dpram_be_2r2w
4325 100 unneback 
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file))
4326 95 unneback 
`undef MODULE
4327 
dpram6464 (
4328 
    .d_a({d_a,d_a}),
4329 
    .q_a(temp),
4330 
    .adr_a(adr_a[a_addr_width-1:1]),
4331 
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
4332 
    .we_a(we_a),
4333 
    .clk_a(clk_a),
4334 
    .d_b(d_b),
4335 
    .q_b(q_b),
4336 
    .adr_b(adr_b),
4337 
    .be_b(be_b),
4338 
    .we_b(we_b),
4339 
    .clk_b(clk_b)
4340 
);
4341 
 
4342 100 unneback 
always @ (adr_a[0] or temp)
4343 95 unneback 
    if (adr_a[0])
4344 
        q_a = temp[63:32];
4345 
    else
4346 
        q_a = temp[31:0];
4347 
 
4348 
end
4349 
endgenerate
4350 
 
4351 91 unneback 
`else
4352 92 unneback 
    // This modules requires SystemVerilog
4353 98 unneback 
    // at this point anyway
4354 91 unneback 
`endif
4355 75 unneback 
endmodule
4356 
`endif
4357 
 
4358 91 unneback 
`ifdef CAM
4359 6 unneback 
// Content addresable memory, CAM
4360 91 unneback 
`endif
4361 6 unneback 
 
4362 40 unneback 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
4363 6 unneback 
// FIFO
4364 40 unneback 
`define MODULE fifo_1r1w_fill_level_sync
4365 
module `BASE`MODULE (
4366 
`undef MODULE
4367 25 unneback 
    d, wr, fifo_full,
4368 
    q, rd, fifo_empty,
4369 
    fill_level,
4370 
    clk, rst
4371 
    );
4372 
 
4373 
parameter data_width = 18;
4374 
parameter addr_width = 4;
4375 6 unneback 
 
4376 25 unneback 
// write side
4377 
input  [data_width-1:0] d;
4378 
input                   wr;
4379 
output                  fifo_full;
4380 
// read side
4381 
output [data_width-1:0] q;
4382 
input                   rd;
4383 
output                  fifo_empty;
4384 
// common
4385 
output [addr_width:0]   fill_level;
4386 
input rst, clk;
4387 
 
4388 
wire [addr_width:1] wadr, radr;
4389 
 
4390 40 unneback 
`define MODULE cnt_bin_ce
4391 
`BASE`MODULE
4392 25 unneback 
    # ( .length(addr_width))
4393 
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
4394 40 unneback 
`BASE`MODULE
4395 25 unneback 
    # (.length(addr_width))
4396 
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
4397 40 unneback 
`undef MODULE
4398 25 unneback 
 
4399 40 unneback 
`define MODULE dpram_1r1w
4400 
`BASE`MODULE
4401 25 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4402 
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
4403 40 unneback 
`undef MODULE
4404 25 unneback 
 
4405 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
4406 
`BASE`MODULE
4407 27 unneback 
    # (.length(addr_width+1), .level1_value(1<<addr_width))
4408 25 unneback 
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
4409 40 unneback 
`undef MODULE
4410 25 unneback 
endmodule
4411 40 unneback 
`endif
4412 25 unneback 
 
4413 40 unneback 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
4414 27 unneback 
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
4415 
// RAM is supposed to be larger than the two FIFOs
4416 
// LFSR counters used adr pointers
4417 40 unneback 
`define MODULE fifo_2r2w_sync_simplex
4418 
module `BASE`MODULE (
4419 
`undef MODULE
4420 27 unneback 
    // a side
4421 
    a_d, a_wr, a_fifo_full,
4422 
    a_q, a_rd, a_fifo_empty,
4423 
    a_fill_level,
4424 
    // b side
4425 
    b_d, b_wr, b_fifo_full,
4426 
    b_q, b_rd, b_fifo_empty,
4427 
    b_fill_level,
4428 
    // common
4429 
    clk, rst
4430 
    );
4431 
parameter data_width = 8;
4432 
parameter addr_width = 5;
4433 
parameter fifo_full_level = (1<<addr_width)-1;
4434 
 
4435 
// a side
4436 
input  [data_width-1:0] a_d;
4437 
input                   a_wr;
4438 
output                  a_fifo_full;
4439 
output [data_width-1:0] a_q;
4440 
input                   a_rd;
4441 
output                  a_fifo_empty;
4442 
output [addr_width-1:0] a_fill_level;
4443 
 
4444 
// b side
4445 
input  [data_width-1:0] b_d;
4446 
input                   b_wr;
4447 
output                  b_fifo_full;
4448 
output [data_width-1:0] b_q;
4449 
input                   b_rd;
4450 
output                  b_fifo_empty;
4451 
output [addr_width-1:0] b_fill_level;
4452 
 
4453 
input                   clk;
4454 
input                   rst;
4455 
 
4456 
// adr_gen
4457 
wire [addr_width:1] a_wadr, a_radr;
4458 
wire [addr_width:1] b_wadr, b_radr;
4459 
// dpram
4460 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4461 
 
4462 40 unneback 
`define MODULE cnt_lfsr_ce
4463 
`BASE`MODULE
4464 27 unneback 
    # ( .length(addr_width))
4465 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
4466 
 
4467 40 unneback 
`BASE`MODULE
4468 27 unneback 
    # (.length(addr_width))
4469 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
4470 
 
4471 40 unneback 
`BASE`MODULE
4472 27 unneback 
    # ( .length(addr_width))
4473 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
4474 
 
4475 40 unneback 
`BASE`MODULE
4476 27 unneback 
    # (.length(addr_width))
4477 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
4478 40 unneback 
`undef MODULE
4479 27 unneback 
 
4480 
// mux read or write adr to DPRAM
4481 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
4482 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
4483 
 
4484 40 unneback 
`define MODULE dpram_2r2w
4485 
`BASE`MODULE
4486 27 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4487 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4488 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4489 40 unneback 
`undef MODULE
4490 
 
4491 
`define MODULE cnt_bin_ce_rew_zq_l1
4492 
`BASE`MODULE
4493 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4494 27 unneback 
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
4495 
 
4496 40 unneback 
`BASE`MODULE
4497 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4498 27 unneback 
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
4499 40 unneback 
`undef MODULE
4500 27 unneback 
 
4501 
endmodule
4502 40 unneback 
`endif
4503 27 unneback 
 
4504 40 unneback 
`ifdef FIFO_CMP_ASYNC
4505 
`define MODULE fifo_cmp_async
4506 
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
4507 
`undef MODULE
4508 6 unneback 
 
4509 11 unneback 
   parameter addr_width = 4;
4510 
   parameter N = addr_width-1;
4511 6 unneback 
 
4512 
   parameter Q1 = 2'b00;
4513 
   parameter Q2 = 2'b01;
4514 
   parameter Q3 = 2'b11;
4515 
   parameter Q4 = 2'b10;
4516 
 
4517 
   parameter going_empty = 1'b0;
4518 
   parameter going_full  = 1'b1;
4519 
 
4520 
   input [N:0]  wptr, rptr;
4521 14 unneback 
   output       fifo_empty;
4522 6 unneback 
   output       fifo_full;
4523 
   input        wclk, rclk, rst;
4524 
 
4525 
`ifndef GENERATE_DIRECTION_AS_LATCH
4526 
   wire direction;
4527 
`endif
4528 
`ifdef GENERATE_DIRECTION_AS_LATCH
4529 
   reg direction;
4530 
`endif
4531 
   reg  direction_set, direction_clr;
4532 
 
4533 
   wire async_empty, async_full;
4534 
   wire fifo_full2;
4535 14 unneback 
   wire fifo_empty2;
4536 6 unneback 
 
4537 
   // direction_set
4538 
   always @ (wptr[N:N-1] or rptr[N:N-1])
4539 
     case ({wptr[N:N-1],rptr[N:N-1]})
4540 
       {Q1,Q2} : direction_set <= 1'b1;
4541 
       {Q2,Q3} : direction_set <= 1'b1;
4542 
       {Q3,Q4} : direction_set <= 1'b1;
4543 
       {Q4,Q1} : direction_set <= 1'b1;
4544 
       default : direction_set <= 1'b0;
4545 
     endcase
4546 
 
4547 
   // direction_clear
4548 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
4549 
     if (rst)
4550 
       direction_clr <= 1'b1;
4551 
     else
4552 
       case ({wptr[N:N-1],rptr[N:N-1]})
4553 
         {Q2,Q1} : direction_clr <= 1'b1;
4554 
         {Q3,Q2} : direction_clr <= 1'b1;
4555 
         {Q4,Q3} : direction_clr <= 1'b1;
4556 
         {Q1,Q4} : direction_clr <= 1'b1;
4557 
         default : direction_clr <= 1'b0;
4558 
       endcase
4559 
 
4560 40 unneback 
`define MODULE dff_sr
4561 6 unneback 
`ifndef GENERATE_DIRECTION_AS_LATCH
4562 40 unneback 
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
4563 6 unneback 
`endif
4564 
 
4565 
`ifdef GENERATE_DIRECTION_AS_LATCH
4566 
   always @ (posedge direction_set or posedge direction_clr)
4567 
     if (direction_clr)
4568 
       direction <= going_empty;
4569 
     else
4570 
       direction <= going_full;
4571 
`endif
4572 
 
4573 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
4574 
   assign async_full  = (wptr == rptr) && (direction==going_full);
4575 
 
4576 40 unneback 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
4577 
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
4578 
`undef MODULE
4579 6 unneback 
 
4580 
/*
4581 
   always @ (posedge wclk or posedge rst or posedge async_full)
4582 
     if (rst)
4583 
       {fifo_full, fifo_full2} <= 2'b00;
4584 
     else if (async_full)
4585 
       {fifo_full, fifo_full2} <= 2'b11;
4586 
     else
4587 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
4588 
*/
4589 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
4590 6 unneback 
     if (async_empty)
4591 
       {fifo_empty, fifo_empty2} <= 2'b11;
4592 
     else
4593 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
4594 40 unneback 
`define MODULE dff
4595 
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
4596 
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
4597 
`undef MODULE
4598 27 unneback 
endmodule // async_compb
4599 40 unneback 
`endif
4600 6 unneback 
 
4601 40 unneback 
`ifdef FIFO_1R1W_ASYNC
4602 
`define MODULE fifo_1r1w_async
4603 
module `BASE`MODULE (
4604 
`undef MODULE
4605 6 unneback 
    d, wr, fifo_full, wr_clk, wr_rst,
4606 
    q, rd, fifo_empty, rd_clk, rd_rst
4607 
    );
4608 
 
4609 
parameter data_width = 18;
4610 
parameter addr_width = 4;
4611 
 
4612 
// write side
4613 
input  [data_width-1:0] d;
4614 
input                   wr;
4615 
output                  fifo_full;
4616 
input                   wr_clk;
4617 
input                   wr_rst;
4618 
// read side
4619 
output [data_width-1:0] q;
4620 
input                   rd;
4621 
output                  fifo_empty;
4622 
input                   rd_clk;
4623 
input                   rd_rst;
4624 
 
4625 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
4626 23 unneback 
 
4627 40 unneback 
`define MODULE cnt_gray_ce_bin
4628 
`BASE`MODULE
4629 6 unneback 
    # ( .length(addr_width))
4630 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
4631 
 
4632 40 unneback 
`BASE`MODULE
4633 6 unneback 
    # (.length(addr_width))
4634 23 unneback 
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
4635 40 unneback 
`undef MODULE
4636 6 unneback 
 
4637 40 unneback 
`define MODULE dpram_1r1w
4638 
`BASE`MODULE
4639 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4640 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
4641 40 unneback 
`undef MODULE
4642 6 unneback 
 
4643 40 unneback 
`define MODULE fifo_cmp_async
4644 
`BASE`MODULE
4645 6 unneback 
    # (.addr_width(addr_width))
4646 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
4647 40 unneback 
`undef MODULE
4648 6 unneback 
 
4649 
endmodule
4650 40 unneback 
`endif
4651 6 unneback 
 
4652 40 unneback 
`ifdef FIFO_2R2W_ASYNC
4653 
`define MODULE fifo_2r2w_async
4654 
module `BASE`MODULE (
4655 
`undef MODULE
4656 6 unneback 
    // a side
4657 
    a_d, a_wr, a_fifo_full,
4658 
    a_q, a_rd, a_fifo_empty,
4659 
    a_clk, a_rst,
4660 
    // b side
4661 
    b_d, b_wr, b_fifo_full,
4662 
    b_q, b_rd, b_fifo_empty,
4663 
    b_clk, b_rst
4664 
    );
4665 
 
4666 
parameter data_width = 18;
4667 
parameter addr_width = 4;
4668 
 
4669 
// a side
4670 
input  [data_width-1:0] a_d;
4671 
input                   a_wr;
4672 
output                  a_fifo_full;
4673 
output [data_width-1:0] a_q;
4674 
input                   a_rd;
4675 
output                  a_fifo_empty;
4676 
input                   a_clk;
4677 
input                   a_rst;
4678 
 
4679 
// b side
4680 
input  [data_width-1:0] b_d;
4681 
input                   b_wr;
4682 
output                  b_fifo_full;
4683 
output [data_width-1:0] b_q;
4684 
input                   b_rd;
4685 
output                  b_fifo_empty;
4686 
input                   b_clk;
4687 
input                   b_rst;
4688 
 
4689 40 unneback 
`define MODULE fifo_1r1w_async
4690 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4691 6 unneback 
vl_fifo_1r1w_async_a (
4692 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4693 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4694 
    );
4695 
 
4696 40 unneback 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4697 6 unneback 
vl_fifo_1r1w_async_b (
4698 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4699 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4700 
    );
4701 40 unneback 
`undef MODULE
4702 
 
4703 6 unneback 
endmodule
4704 40 unneback 
`endif
4705 6 unneback 
 
4706 40 unneback 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4707 
`define MODULE fifo_2r2w_async_simplex
4708 
module `BASE`MODULE (
4709 
`undef MODULE
4710 6 unneback 
    // a side
4711 
    a_d, a_wr, a_fifo_full,
4712 
    a_q, a_rd, a_fifo_empty,
4713 
    a_clk, a_rst,
4714 
    // b side
4715 
    b_d, b_wr, b_fifo_full,
4716 
    b_q, b_rd, b_fifo_empty,
4717 
    b_clk, b_rst
4718 
    );
4719 
 
4720 
parameter data_width = 18;
4721 
parameter addr_width = 4;
4722 
 
4723 
// a side
4724 
input  [data_width-1:0] a_d;
4725 
input                   a_wr;
4726 
output                  a_fifo_full;
4727 
output [data_width-1:0] a_q;
4728 
input                   a_rd;
4729 
output                  a_fifo_empty;
4730 
input                   a_clk;
4731 
input                   a_rst;
4732 
 
4733 
// b side
4734 
input  [data_width-1:0] b_d;
4735 
input                   b_wr;
4736 
output                  b_fifo_full;
4737 
output [data_width-1:0] b_q;
4738 
input                   b_rd;
4739 
output                  b_fifo_empty;
4740 
input                   b_clk;
4741 
input                   b_rst;
4742 
 
4743 
// adr_gen
4744 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4745 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4746 
// dpram
4747 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4748 
 
4749 40 unneback 
`define MODULE cnt_gray_ce_bin
4750 
`BASE`MODULE
4751 6 unneback 
    # ( .length(addr_width))
4752 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4753 
 
4754 40 unneback 
`BASE`MODULE
4755 6 unneback 
    # (.length(addr_width))
4756 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4757 
 
4758 40 unneback 
`BASE`MODULE
4759 6 unneback 
    # ( .length(addr_width))
4760 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4761 
 
4762 40 unneback 
`BASE`MODULE
4763 6 unneback 
    # (.length(addr_width))
4764 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4765 40 unneback 
`undef MODULE
4766 6 unneback 
 
4767 
// mux read or write adr to DPRAM
4768 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4769 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4770 
 
4771 40 unneback 
`define MODULE dpram_2r2w
4772 
`BASE`MODULE
4773 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4774 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4775 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4776 40 unneback 
`undef MODULE
4777 6 unneback 
 
4778 40 unneback 
`define MODULE fifo_cmp_async
4779 
`BASE`MODULE
4780 6 unneback 
    # (.addr_width(addr_width))
4781 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4782 
 
4783 40 unneback 
`BASE`MODULE
4784 6 unneback 
    # (.addr_width(addr_width))
4785 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4786 40 unneback 
`undef MODULE
4787 6 unneback 
 
4788 
endmodule
4789 40 unneback 
`endif
4790 48 unneback 
 
4791 
`ifdef REG_FILE
4792 
`define MODULE reg_file
4793 
module `BASE`MODULE (
4794 
`undef MODULE
4795 
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4796 
);
4797 
parameter data_width = 32;
4798 
parameter addr_width = 5;
4799 
input [addr_width-1:0] a1, a2, a3;
4800 
input [data_width-1:0] wd3;
4801 
input we3;
4802 
output [data_width-1:0] rd1, rd2;
4803 
input clk;
4804 
 
4805 
`ifdef ACTEL
4806 
reg [data_width-1:0] wd3_reg;
4807 
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4808 
reg we3_reg;
4809 98 unneback 
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
4810 
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
4811 48 unneback 
always @ (posedge clk or posedge rst)
4812 
if (rst)
4813 
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4814 
else
4815 
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4816 
 
4817 
    always @ (negedge clk)
4818 
    if (we3_reg)
4819 
        ram1[a3_reg] <= wd3;
4820 
    always @ (posedge clk)
4821 
        a1_reg <= a1;
4822 
    assign rd1 = ram1[a1_reg];
4823 
 
4824 
    always @ (negedge clk)
4825 
    if (we3_reg)
4826 
        ram2[a3_reg] <= wd3;
4827 
    always @ (posedge clk)
4828 
        a2_reg <= a2;
4829 
    assign rd2 = ram2[a2_reg];
4830 
 
4831 
`else
4832 
 
4833 
`define MODULE dpram_1r1w
4834 
`BASE`MODULE
4835 
    # ( .data_width(data_width), .addr_width(addr_width))
4836 
    ram1 (
4837 
        .d_a(wd3),
4838 
        .adr_a(a3),
4839 
        .we_a(we3),
4840 
        .clk_a(clk),
4841 
        .q_b(rd1),
4842 
        .adr_b(a1),
4843 
        .clk_b(clk) );
4844 
 
4845 
`BASE`MODULE
4846 
    # ( .data_width(data_width), .addr_width(addr_width))
4847 
    ram2 (
4848 
        .d_a(wd3),
4849 
        .adr_a(a3),
4850 
        .we_a(we3),
4851 
        .clk_a(clk),
4852 
        .q_b(rd2),
4853 
        .adr_b(a2),
4854 
        .clk_b(clk) );
4855 
`undef MODULE
4856 
 
4857 
`endif
4858 
 
4859 
endmodule
4860 
`endif
4861 12 unneback 
//////////////////////////////////////////////////////////////////////
4862 
////                                                              ////
4863 
////  Versatile library, wishbone stuff                           ////
4864 
////                                                              ////
4865 
////  Description                                                 ////
4866 
////  Wishbone compliant modules                                  ////
4867 
////                                                              ////
4868 
////                                                              ////
4869 
////  To Do:                                                      ////
4870 
////   -                                                          ////
4871 
////                                                              ////
4872 
////  Author(s):                                                  ////
4873 
////      - Michael Unneback, unneback@opencores.org              ////
4874 
////        ORSoC AB                                              ////
4875 
////                                                              ////
4876 
//////////////////////////////////////////////////////////////////////
4877 
////                                                              ////
4878 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4879 
////                                                              ////
4880 
//// This source file may be used and distributed without         ////
4881 
//// restriction provided that this copyright statement is not    ////
4882 
//// removed from the file and that any derivative work contains  ////
4883 
//// the original copyright notice and the associated disclaimer. ////
4884 
////                                                              ////
4885 
//// This source file is free software; you can redistribute it   ////
4886 
//// and/or modify it under the terms of the GNU Lesser General   ////
4887 
//// Public License as published by the Free Software Foundation; ////
4888 
//// either version 2.1 of the License, or (at your option) any   ////
4889 
//// later version.                                               ////
4890 
////                                                              ////
4891 
//// This source is distributed in the hope that it will be       ////
4892 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4893 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4894 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4895 
//// details.                                                     ////
4896 
////                                                              ////
4897 
//// You should have received a copy of the GNU Lesser General    ////
4898 
//// Public License along with this source; if not, download it   ////
4899 
//// from http://www.opencores.org/lgpl.shtml                     ////
4900 
////                                                              ////
4901 
//////////////////////////////////////////////////////////////////////
4902 
 
4903 75 unneback 
`ifdef WB_ADR_INC
4904 
`timescale 1ns/1ns
4905 
`define MODULE wb_adr_inc
4906 85 unneback 
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
4907 75 unneback 
`undef MODULE
4908 83 unneback 
parameter adr_width = 10;
4909 
parameter max_burst_width = 4;
4910 85 unneback 
input cyc_i, stb_i, we_i;
4911 83 unneback 
input [2:0] cti_i;
4912 
input [1:0] bte_i;
4913 
input [adr_width-1:0] adr_i;
4914 
output [adr_width-1:0] adr_o;
4915 
output ack_o;
4916 
input clk, rst;
4917 75 unneback 
 
4918 83 unneback 
reg [adr_width-1:0] adr;
4919 90 unneback 
wire [max_burst_width-1:0] to_adr;
4920 91 unneback 
reg [max_burst_width-1:0] last_adr;
4921 92 unneback 
reg last_cycle;
4922 
localparam idle_or_eoc = 1'b0;
4923 
localparam cyc_or_ws   = 1'b1;
4924 90 unneback 
 
4925 91 unneback 
always @ (posedge clk or posedge rst)
4926 
if (rst)
4927 
    last_adr <= {max_burst_width{1'b0}};
4928 
else
4929 
    if (stb_i)
4930 92 unneback 
        last_adr <=adr_o[max_burst_width-1:0];
4931 91 unneback 
 
4932 83 unneback 
generate
4933 
if (max_burst_width==0) begin : inst_0
4934 97 unneback 
 
4935 
        reg ack_o;
4936 
        assign adr_o = adr_i;
4937 
        always @ (posedge clk or posedge rst)
4938 
        if (rst)
4939 
            ack_o <= 1'b0;
4940 
        else
4941 
            ack_o <= cyc_i & stb_i & !ack_o;
4942 
 
4943 83 unneback 
end else begin
4944 
 
4945 
    always @ (posedge clk or posedge rst)
4946 
    if (rst)
4947 92 unneback 
        last_cycle <= idle_or_eoc;
4948 83 unneback 
    else
4949 92 unneback 
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
4950 
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
4951 
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
4952 
                      cyc_or_ws; // cyc
4953 
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
4954 85 unneback 
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
4955 91 unneback 
                                        (!stb_i) ? last_adr :
4956 92 unneback 
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
4957 85 unneback 
                                        adr[max_burst_width-1:0];
4958 92 unneback 
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
4959 97 unneback 
 
4960 83 unneback 
end
4961 
endgenerate
4962 
 
4963 
generate
4964 
if (max_burst_width==2) begin : inst_2
4965 
    always @ (posedge clk or posedge rst)
4966 
    if (rst)
4967 
        adr <= 2'h0;
4968 
    else
4969 
        if (cyc_i & stb_i)
4970 
            adr[1:0] <= to_adr[1:0] + 2'd1;
4971 75 unneback 
        else
4972 83 unneback 
            adr <= to_adr[1:0];
4973 
end
4974 
endgenerate
4975 
 
4976 
generate
4977 
if (max_burst_width==3) begin : inst_3
4978 
    always @ (posedge clk or posedge rst)
4979 
    if (rst)
4980 
        adr <= 3'h0;
4981 
    else
4982 
        if (cyc_i & stb_i)
4983 
            case (bte_i)
4984 
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
4985 
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
4986 75 unneback 
            endcase
4987 83 unneback 
        else
4988 
            adr <= to_adr[2:0];
4989 
end
4990 
endgenerate
4991 
 
4992 
generate
4993 
if (max_burst_width==4) begin : inst_4
4994 
    always @ (posedge clk or posedge rst)
4995 
    if (rst)
4996 
        adr <= 4'h0;
4997 
    else
4998 91 unneback 
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
4999 83 unneback 
            case (bte_i)
5000 
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
5001 
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
5002 
            default: adr[3:0] <= to_adr + 4'd1;
5003 
            endcase
5004 
        else
5005 
            adr <= to_adr[3:0];
5006 
end
5007 
endgenerate
5008 
 
5009 
generate
5010 
if (adr_width > max_burst_width) begin : pass_through
5011 
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
5012 
end
5013 
endgenerate
5014 
 
5015 
endmodule
5016 75 unneback 
`endif
5017 
 
5018 40 unneback 
`ifdef WB3WB3_BRIDGE
5019 12 unneback 
// async wb3 - wb3 bridge
5020 
`timescale 1ns/1ns
5021 40 unneback 
`define MODULE wb3wb3_bridge
5022 
module `BASE`MODULE (
5023 
`undef MODULE
5024 12 unneback 
        // wishbone slave side
5025 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5026 
        // wishbone master side
5027 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
5028 
 
5029 95 unneback 
parameter style = "FIFO"; // valid: simple, FIFO
5030 
parameter addr_width = 4;
5031 
 
5032 12 unneback 
input [31:0] wbs_dat_i;
5033 
input [31:2] wbs_adr_i;
5034 
input [3:0]  wbs_sel_i;
5035 
input [1:0]  wbs_bte_i;
5036 
input [2:0]  wbs_cti_i;
5037 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
5038 
output [31:0] wbs_dat_o;
5039 14 unneback 
output wbs_ack_o;
5040 12 unneback 
input wbs_clk, wbs_rst;
5041 
 
5042 
output [31:0] wbm_dat_o;
5043 
output reg [31:2] wbm_adr_o;
5044 
output [3:0]  wbm_sel_o;
5045 
output reg [1:0]  wbm_bte_o;
5046 
output reg [2:0]  wbm_cti_o;
5047 14 unneback 
output reg wbm_we_o;
5048 
output wbm_cyc_o;
5049 12 unneback 
output wbm_stb_o;
5050 
input [31:0]  wbm_dat_i;
5051 
input wbm_ack_i;
5052 
input wbm_clk, wbm_rst;
5053 
 
5054 
// bte
5055 
parameter linear       = 2'b00;
5056 
parameter wrap4        = 2'b01;
5057 
parameter wrap8        = 2'b10;
5058 
parameter wrap16       = 2'b11;
5059 
// cti
5060 
parameter classic      = 3'b000;
5061 
parameter incburst     = 3'b010;
5062 
parameter endofburst   = 3'b111;
5063 
 
5064 95 unneback 
localparam wbs_adr  = 1'b0;
5065 
localparam wbs_data = 1'b1;
5066 12 unneback 
 
5067 95 unneback 
localparam wbm_adr0      = 2'b00;
5068 
localparam wbm_adr1      = 2'b01;
5069 
localparam wbm_data      = 2'b10;
5070 
localparam wbm_data_wait = 2'b11;
5071 12 unneback 
 
5072 
reg [1:0] wbs_bte_reg;
5073 
reg wbs;
5074 
wire wbs_eoc_alert, wbm_eoc_alert;
5075 
reg wbs_eoc, wbm_eoc;
5076 
reg [1:0] wbm;
5077 
 
5078 14 unneback 
wire [1:16] wbs_count, wbm_count;
5079 12 unneback 
 
5080 
wire [35:0] a_d, a_q, b_d, b_q;
5081 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
5082 
reg a_rd_reg;
5083 
wire b_rd_adr, b_rd_data;
5084 14 unneback 
wire b_rd_data_reg;
5085 
wire [35:0] temp;
5086 12 unneback 
 
5087 
`define WE 5
5088 
`define BTE 4:3
5089 
`define CTI 2:0
5090 
 
5091 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
5092 
always @ (posedge wbs_clk or posedge wbs_rst)
5093 
if (wbs_rst)
5094 
        wbs_eoc <= 1'b0;
5095 
else
5096 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
5097 78 unneback 
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
5098 12 unneback 
        else if (wbs_eoc_alert & (a_rd | a_wr))
5099 
                wbs_eoc <= 1'b1;
5100 
 
5101 40 unneback 
`define MODULE cnt_shreg_ce_clear
5102 
`BASE`MODULE # ( .length(16))
5103 
`undef MODULE
5104 12 unneback 
    cnt0 (
5105 
        .cke(wbs_ack_o),
5106 
        .clear(wbs_eoc),
5107 
        .q(wbs_count),
5108 
        .rst(wbs_rst),
5109 
        .clk(wbs_clk));
5110 
 
5111 
always @ (posedge wbs_clk or posedge wbs_rst)
5112 
if (wbs_rst)
5113 
        wbs <= wbs_adr;
5114 
else
5115 75 unneback 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
5116 12 unneback 
                wbs <= wbs_data;
5117 
        else if (wbs_eoc & wbs_ack_o)
5118 
                wbs <= wbs_adr;
5119 
 
5120 
// wbs FIFO
5121 75 unneback 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
5122 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
5123 12 unneback 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
5124 
              1'b0;
5125 
assign a_rd = !a_fifo_empty;
5126 
always @ (posedge wbs_clk or posedge wbs_rst)
5127 
if (wbs_rst)
5128 
        a_rd_reg <= 1'b0;
5129 
else
5130 
        a_rd_reg <= a_rd;
5131 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
5132 
 
5133 
assign wbs_dat_o = a_q[35:4];
5134 
 
5135 
always @ (posedge wbs_clk or posedge wbs_rst)
5136 
if (wbs_rst)
5137 13 unneback 
        wbs_bte_reg <= 2'b00;
5138 12 unneback 
else
5139 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
5140 12 unneback 
 
5141 
// wbm FIFO
5142 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
5143 
always @ (posedge wbm_clk or posedge wbm_rst)
5144 
if (wbm_rst)
5145 
        wbm_eoc <= 1'b0;
5146 
else
5147 
        if (wbm==wbm_adr0 & !b_fifo_empty)
5148 
                wbm_eoc <= b_q[`BTE] == linear;
5149 
        else if (wbm_eoc_alert & wbm_ack_i)
5150 
                wbm_eoc <= 1'b1;
5151 
 
5152 
always @ (posedge wbm_clk or posedge wbm_rst)
5153 
if (wbm_rst)
5154 
        wbm <= wbm_adr0;
5155 
else
5156 33 unneback 
/*
5157 12 unneback 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
5158 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
5159 
        (wbm==wbm_adr1 & !wbm_we_o) |
5160 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
5161 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
5162 33 unneback 
*/
5163 
    case (wbm)
5164 
    wbm_adr0:
5165 
        if (!b_fifo_empty)
5166 
            wbm <= wbm_adr1;
5167 
    wbm_adr1:
5168 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
5169 
            wbm <= wbm_data;
5170 
    wbm_data:
5171 
        if (wbm_ack_i & wbm_eoc)
5172 
            wbm <= wbm_adr0;
5173 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
5174 
            wbm <= wbm_data_wait;
5175 
    wbm_data_wait:
5176 
        if (!b_fifo_empty)
5177 
            wbm <= wbm_data;
5178 
    endcase
5179 12 unneback 
 
5180 
assign b_d = {wbm_dat_i,4'b1111};
5181 
assign b_wr = !wbm_we_o & wbm_ack_i;
5182 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
5183 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
5184 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
5185 33 unneback 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
5186 12 unneback 
                   1'b0;
5187 
assign b_rd = b_rd_adr | b_rd_data;
5188 
 
5189 40 unneback 
`define MODULE dff
5190 
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
5191 
`undef MODULE
5192 
`define MODULE dff_ce
5193 
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
5194 
`undef MODULE
5195 12 unneback 
 
5196 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
5197 
 
5198 40 unneback 
`define MODULE cnt_shreg_ce_clear
5199 42 unneback 
`BASE`MODULE # ( .length(16))
5200 40 unneback 
`undef MODULE
5201 12 unneback 
    cnt1 (
5202 
        .cke(wbm_ack_i),
5203 
        .clear(wbm_eoc),
5204 
        .q(wbm_count),
5205 
        .rst(wbm_rst),
5206 
        .clk(wbm_clk));
5207 
 
5208 33 unneback 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
5209 
assign wbm_stb_o = (wbm==wbm_data);
5210 12 unneback 
 
5211 
always @ (posedge wbm_clk or posedge wbm_rst)
5212 
if (wbm_rst)
5213 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
5214 
else begin
5215 
        if (wbm==wbm_adr0 & !b_fifo_empty)
5216 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
5217 
        else if (wbm_eoc_alert & wbm_ack_i)
5218 
                wbm_cti_o <= endofburst;
5219 
end
5220 
 
5221 
//async_fifo_dw_simplex_top
5222 40 unneback 
`define MODULE fifo_2r2w_async_simplex
5223 
`BASE`MODULE
5224 
`undef MODULE
5225 12 unneback 
# ( .data_width(36), .addr_width(addr_width))
5226 
fifo (
5227 
    // a side
5228 
    .a_d(a_d),
5229 
    .a_wr(a_wr),
5230 
    .a_fifo_full(a_fifo_full),
5231 
    .a_q(a_q),
5232 
    .a_rd(a_rd),
5233 
    .a_fifo_empty(a_fifo_empty),
5234 
    .a_clk(wbs_clk),
5235 
    .a_rst(wbs_rst),
5236 
    // b side
5237 
    .b_d(b_d),
5238 
    .b_wr(b_wr),
5239 
    .b_fifo_full(b_fifo_full),
5240 
    .b_q(b_q),
5241 
    .b_rd(b_rd),
5242 
    .b_fifo_empty(b_fifo_empty),
5243 
    .b_clk(wbm_clk),
5244 
    .b_rst(wbm_rst)
5245 
    );
5246 
 
5247 
endmodule
5248 40 unneback 
`undef WE
5249 
`undef BTE
5250 
`undef CTI
5251 
`endif
5252 17 unneback 
 
5253 75 unneback 
`ifdef WB3AVALON_BRIDGE
5254 
`define MODULE wb3avalon_bridge
5255 
module `BASE`MODULE (
5256 
`undef MODULE
5257 
        // wishbone slave side
5258 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5259 77 unneback 
        // avalon master side
5260 75 unneback 
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
5261 
 
5262 85 unneback 
parameter linewrapburst = 1'b0;
5263 
 
5264 75 unneback 
input [31:0] wbs_dat_i;
5265 
input [31:2] wbs_adr_i;
5266 
input [3:0]  wbs_sel_i;
5267 
input [1:0]  wbs_bte_i;
5268 
input [2:0]  wbs_cti_i;
5269 83 unneback 
input wbs_we_i;
5270 
input wbs_cyc_i;
5271 
input wbs_stb_i;
5272 75 unneback 
output [31:0] wbs_dat_o;
5273 
output wbs_ack_o;
5274 
input wbs_clk, wbs_rst;
5275 
 
5276 
input [31:0] readdata;
5277 
output [31:0] writedata;
5278 
output [31:2] address;
5279 
output [3:0]  be;
5280 
output write;
5281 81 unneback 
output read;
5282 75 unneback 
output beginbursttransfer;
5283 
output [3:0] burstcount;
5284 
input readdatavalid;
5285 
input waitrequest;
5286 
input clk;
5287 
input rst;
5288 
 
5289 
wire [1:0] wbm_bte_o;
5290 
wire [2:0] wbm_cti_o;
5291 
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
5292 
reg last_cyc;
5293 79 unneback 
reg [3:0] counter;
5294 82 unneback 
reg read_busy;
5295 75 unneback 
 
5296 
always @ (posedge clk or posedge rst)
5297 
if (rst)
5298 
    last_cyc <= 1'b0;
5299 
else
5300 
    last_cyc <= wbm_cyc_o;
5301 
 
5302 79 unneback 
always @ (posedge clk or posedge rst)
5303 
if (rst)
5304 82 unneback 
    read_busy <= 1'b0;
5305 79 unneback 
else
5306 82 unneback 
    if (read & !waitrequest)
5307 
        read_busy <= 1'b1;
5308 
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
5309 
        read_busy <= 1'b0;
5310 
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
5311 81 unneback 
 
5312 75 unneback 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
5313 
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
5314 
                    (wbm_bte_o==2'b10) ? 4'd8 :
5315 78 unneback 
                    (wbm_bte_o==2'b11) ? 4'd16:
5316 
                    4'd1;
5317 82 unneback 
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
5318 75 unneback 
 
5319 79 unneback 
always @ (posedge clk or posedge rst)
5320 
if (rst) begin
5321 
    counter <= 4'd0;
5322 
end else
5323 80 unneback 
    if (wbm_we_o) begin
5324 
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
5325 85 unneback 
            counter <= burstcount -4'd1;
5326 80 unneback 
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
5327 
            counter <= burstcount;
5328 
        end else if (!waitrequest & wbm_stb_o) begin
5329 
            counter <= counter - 4'd1;
5330 
        end
5331 82 unneback 
    end
5332 81 unneback 
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
5333 79 unneback 
 
5334 75 unneback 
`define MODULE wb3wb3_bridge
5335 77 unneback 
`BASE`MODULE wbwb3inst (
5336 75 unneback 
`undef MODULE
5337 
    // wishbone slave side
5338 
    .wbs_dat_i(wbs_dat_i),
5339 
    .wbs_adr_i(wbs_adr_i),
5340 
    .wbs_sel_i(wbs_sel_i),
5341 
    .wbs_bte_i(wbs_bte_i),
5342 
    .wbs_cti_i(wbs_cti_i),
5343 
    .wbs_we_i(wbs_we_i),
5344 
    .wbs_cyc_i(wbs_cyc_i),
5345 
    .wbs_stb_i(wbs_stb_i),
5346 
    .wbs_dat_o(wbs_dat_o),
5347 
    .wbs_ack_o(wbs_ack_o),
5348 
    .wbs_clk(wbs_clk),
5349 
    .wbs_rst(wbs_rst),
5350 
    // wishbone master side
5351 
    .wbm_dat_o(writedata),
5352 78 unneback 
    .wbm_adr_o(address),
5353 75 unneback 
    .wbm_sel_o(be),
5354 
    .wbm_bte_o(wbm_bte_o),
5355 
    .wbm_cti_o(wbm_cti_o),
5356 
    .wbm_we_o(wbm_we_o),
5357 
    .wbm_cyc_o(wbm_cyc_o),
5358 
    .wbm_stb_o(wbm_stb_o),
5359 
    .wbm_dat_i(readdata),
5360 
    .wbm_ack_i(wbm_ack_i),
5361 
    .wbm_clk(clk),
5362 
    .wbm_rst(rst));
5363 
 
5364 
 
5365 
endmodule
5366 
`endif
5367 
 
5368 40 unneback 
`ifdef WB3_ARBITER_TYPE1
5369 
`define MODULE wb3_arbiter_type1
5370 42 unneback 
module `BASE`MODULE (
5371 40 unneback 
`undef MODULE
5372 39 unneback 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5373 
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
5374 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5375 
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
5376 
    wb_clk, wb_rst
5377 
);
5378 
 
5379 
parameter nr_of_ports = 3;
5380 
parameter adr_size = 26;
5381 
parameter adr_lo   = 2;
5382 
parameter dat_size = 32;
5383 
parameter sel_size = dat_size/8;
5384 
 
5385 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
5386 
localparam dw = dat_size * nr_of_ports;
5387 
localparam sw = sel_size * nr_of_ports;
5388 
localparam cw = 3 * nr_of_ports;
5389 
localparam bw = 2 * nr_of_ports;
5390 
 
5391 
input  [dw-1:0] wbm_dat_o;
5392 
input  [aw-1:0] wbm_adr_o;
5393 
input  [sw-1:0] wbm_sel_o;
5394 
input  [cw-1:0] wbm_cti_o;
5395 
input  [bw-1:0] wbm_bte_o;
5396 
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
5397 
output [dw-1:0] wbm_dat_i;
5398 
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
5399 
 
5400 
output [dat_size-1:0] wbs_dat_i;
5401 
output [adr_size-1:adr_lo] wbs_adr_i;
5402 
output [sel_size-1:0] wbs_sel_i;
5403 
output [2:0] wbs_cti_i;
5404 
output [1:0] wbs_bte_i;
5405 
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
5406 
input  [dat_size-1:0] wbs_dat_o;
5407 
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
5408 
 
5409 
input wb_clk, wb_rst;
5410 
 
5411 44 unneback 
reg  [nr_of_ports-1:0] select;
5412 39 unneback 
wire [nr_of_ports-1:0] state;
5413 
wire [nr_of_ports-1:0] eoc; // end-of-cycle
5414 
wire [nr_of_ports-1:0] sel;
5415 
wire idle;
5416 
 
5417 
genvar i;
5418 
 
5419 
assign idle = !(|state);
5420 
 
5421 
generate
5422 
if (nr_of_ports == 2) begin
5423 
 
5424 
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
5425 
 
5426 
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5427 
 
5428 44 unneback 
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5429 
 
5430 
    always @ (idle or wbm_cyc_o)
5431 
    if (idle)
5432 
        casex (wbm_cyc_o)
5433 
        2'b1x : select = 2'b10;
5434 
        2'b01 : select = 2'b01;
5435 
        default : select = {nr_of_ports{1'b0}};
5436 
        endcase
5437 
    else
5438 
        select = {nr_of_ports{1'b0}};
5439 
 
5440 39 unneback 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5441 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5442 
 
5443 
end
5444 
endgenerate
5445 
 
5446 
generate
5447 
if (nr_of_ports == 3) begin
5448 
 
5449 
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5450 
 
5451 
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5452 
 
5453 44 unneback 
    always @ (idle or wbm_cyc_o)
5454 
    if (idle)
5455 
        casex (wbm_cyc_o)
5456 
        3'b1xx : select = 3'b100;
5457 
        3'b01x : select = 3'b010;
5458 
        3'b001 : select = 3'b001;
5459 
        default : select = {nr_of_ports{1'b0}};
5460 
        endcase
5461 
    else
5462 
        select = {nr_of_ports{1'b0}};
5463 
 
5464 
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5465 39 unneback 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5466 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5467 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5468 
 
5469 
end
5470 
endgenerate
5471 
 
5472 
generate
5473 44 unneback 
if (nr_of_ports == 4) begin
5474 
 
5475 
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5476 
 
5477 
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5478 
 
5479 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5480 
 
5481 
    always @ (idle or wbm_cyc_o)
5482 
    if (idle)
5483 
        casex (wbm_cyc_o)
5484 
        4'b1xxx : select = 4'b1000;
5485 
        4'b01xx : select = 4'b0100;
5486 
        4'b001x : select = 4'b0010;
5487 
        4'b0001 : select = 4'b0001;
5488 
        default : select = {nr_of_ports{1'b0}};
5489 
        endcase
5490 
    else
5491 
        select = {nr_of_ports{1'b0}};
5492 
 
5493 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5494 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5495 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5496 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5497 
 
5498 
end
5499 
endgenerate
5500 
 
5501 
generate
5502 
if (nr_of_ports == 5) begin
5503 
 
5504 
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5505 
 
5506 
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5507 
 
5508 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5509 
 
5510 
    always @ (idle or wbm_cyc_o)
5511 
    if (idle)
5512 
        casex (wbm_cyc_o)
5513 
        5'b1xxxx : select = 5'b10000;
5514 
        5'b01xxx : select = 5'b01000;
5515 
        5'b001xx : select = 5'b00100;
5516 
        5'b0001x : select = 5'b00010;
5517 
        5'b00001 : select = 5'b00001;
5518 
        default : select = {nr_of_ports{1'b0}};
5519 
        endcase
5520 
    else
5521 
        select = {nr_of_ports{1'b0}};
5522 
 
5523 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5524 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5525 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5526 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5527 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5528 
 
5529 
end
5530 
endgenerate
5531 
 
5532 
generate
5533 67 unneback 
if (nr_of_ports == 6) begin
5534 
 
5535 
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5536 
 
5537 
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5538 
 
5539 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5540 
 
5541 
    always @ (idle or wbm_cyc_o)
5542 
    if (idle)
5543 
        casex (wbm_cyc_o)
5544 
        6'b1xxxxx : select = 6'b100000;
5545 
        6'b01xxxx : select = 6'b010000;
5546 
        6'b001xxx : select = 6'b001000;
5547 
        6'b0001xx : select = 6'b000100;
5548 
        6'b00001x : select = 6'b000010;
5549 
        6'b000001 : select = 6'b000001;
5550 
        default : select = {nr_of_ports{1'b0}};
5551 
        endcase
5552 
    else
5553 
        select = {nr_of_ports{1'b0}};
5554 
 
5555 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5556 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5557 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5558 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5559 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5560 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5561 
 
5562 
end
5563 
endgenerate
5564 
 
5565 
generate
5566 
if (nr_of_ports == 7) begin
5567 
 
5568 
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5569 
 
5570 
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5571 
 
5572 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5573 
 
5574 
    always @ (idle or wbm_cyc_o)
5575 
    if (idle)
5576 
        casex (wbm_cyc_o)
5577 
        7'b1xxxxxx : select = 7'b1000000;
5578 
        7'b01xxxxx : select = 7'b0100000;
5579 
        7'b001xxxx : select = 7'b0010000;
5580 
        7'b0001xxx : select = 7'b0001000;
5581 
        7'b00001xx : select = 7'b0000100;
5582 
        7'b000001x : select = 7'b0000010;
5583 
        7'b0000001 : select = 7'b0000001;
5584 
        default : select = {nr_of_ports{1'b0}};
5585 
        endcase
5586 
    else
5587 
        select = {nr_of_ports{1'b0}};
5588 
 
5589 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5590 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5591 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5592 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5593 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5594 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5595 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5596 
 
5597 
end
5598 
endgenerate
5599 
 
5600 
generate
5601 
if (nr_of_ports == 8) begin
5602 
 
5603 
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5604 
 
5605 
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5606 
 
5607 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5608 
 
5609 
    always @ (idle or wbm_cyc_o)
5610 
    if (idle)
5611 
        casex (wbm_cyc_o)
5612 
        8'b1xxxxxxx : select = 8'b10000000;
5613 
        8'b01xxxxxx : select = 8'b01000000;
5614 
        8'b001xxxxx : select = 8'b00100000;
5615 
        8'b0001xxxx : select = 8'b00010000;
5616 
        8'b00001xxx : select = 8'b00001000;
5617 
        8'b000001xx : select = 8'b00000100;
5618 
        8'b0000001x : select = 8'b00000010;
5619 
        8'b00000001 : select = 8'b00000001;
5620 
        default : select = {nr_of_ports{1'b0}};
5621 
        endcase
5622 
    else
5623 
        select = {nr_of_ports{1'b0}};
5624 
 
5625 
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
5626 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5627 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5628 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5629 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5630 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5631 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5632 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5633 
 
5634 
end
5635 
endgenerate
5636 
 
5637 
generate
5638 63 unneback 
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
5639 42 unneback 
`define MODULE spr
5640 
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
5641 
`undef MODULE
5642 39 unneback 
end
5643 
endgenerate
5644 
 
5645 
    assign sel = select | state;
5646 
 
5647 40 unneback 
`define MODULE mux_andor
5648 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
5649 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
5650 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
5651 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
5652 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
5653 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
5654 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
5655 
`undef MODULE
5656 39 unneback 
    assign wbs_cyc_i = |sel;
5657 
 
5658 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
5659 
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
5660 
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
5661 
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
5662 
 
5663 
endmodule
5664 40 unneback 
`endif
5665 39 unneback 
 
5666 101 unneback 
`ifdef WB_RAM
5667 49 unneback 
// WB RAM with byte enable
5668 101 unneback 
`define MODULE wb_ram
5669 59 unneback 
module `BASE`MODULE (
5670 
`undef MODULE
5671 69 unneback 
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5672 101 unneback 
    wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
5673 59 unneback 
 
5674 101 unneback 
parameter adr_width = 16;
5675 
parameter mem_size = 1<<adr_width;
5676 
parameter dat_width = 32;
5677 
parameter max_burst_width = 4; // only used for B3
5678 
parameter mode = "B3"; // valid options: B3, B4
5679 60 unneback 
parameter memory_init = 1;
5680 
parameter memory_file = "vl_ram.vmem";
5681 59 unneback 
 
5682 101 unneback 
input [dat_width-1:0] wbs_dat_i;
5683 
input [adr_width-1:0] wbs_adr_i;
5684 
input [2:0] wbs_cti_i;
5685 
input [1:0] wbs_bte_i;
5686 
input [dat_width/8-1:0] wbs_sel_i;
5687 70 unneback 
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5688 101 unneback 
output [dat_width-1:0] wbs_dat_o;
5689 70 unneback 
output wbs_ack_o;
5690 101 unneback 
output wbs_stall_o;
5691 71 unneback 
input wb_clk, wb_rst;
5692 59 unneback 
 
5693 101 unneback 
wire [adr_width-1:0] adr;
5694 
wire we;
5695 59 unneback 
 
5696 101 unneback 
generate
5697 
if (mode=="B3") begin : B3_inst
5698 83 unneback 
`define MODULE wb_adr_inc
5699 101 unneback 
`BASE`MODULE # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
5700 83 unneback 
    .cyc_i(wbs_cyc_i),
5701 
    .stb_i(wbs_stb_i),
5702 
    .cti_i(wbs_cti_i),
5703 
    .bte_i(wbs_bte_i),
5704 
    .adr_i(wbs_adr_i),
5705 85 unneback 
    .we_i(wbs_we_i),
5706 83 unneback 
    .ack_o(wbs_ack_o),
5707 
    .adr_o(adr),
5708 
    .clk(wb_clk),
5709 
    .rst(wb_rst));
5710 
`undef MODULE
5711 101 unneback 
assign we = wbs_we_i & wbs_ack_o;
5712 
end else if (mode=="B4") begin : B4_inst
5713 
reg wbs_ack_o_reg;
5714 
always @ (posedge wb_clk or posedge wb_rst)
5715 
    if (wb_rst)
5716 
        wbs_ack_o_reg <= 1'b0;
5717 
    else
5718 
        wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
5719 
assign wbs_ack_o = wbs_ack_o_reg;
5720 
assign wbs_stall_o = 1'b0;
5721 
assign adr = wbs_adr_i;
5722 
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
5723 
end
5724 
endgenerate
5725 60 unneback 
 
5726 100 unneback 
`define MODULE ram_be
5727 
`BASE`MODULE # (
5728 
    .data_width(dat_width),
5729 
    .addr_width(adr_width),
5730 
    .mem_size(mem_size),
5731 
    .memory_init(memory_init),
5732 
    .memory_file(memory_file))
5733 
ram0(
5734 
`undef MODULE
5735 101 unneback 
    .d(wbs_dat_i),
5736 
    .adr(adr),
5737 
    .be(wbs_sel_i),
5738 
    .we(we),
5739 
    .q(wbs_dat_o),
5740 100 unneback 
    .clk(wb_clk)
5741 
);
5742 49 unneback 
 
5743 
endmodule
5744 
`endif
5745 
 
5746 48 unneback 
`ifdef WB_B4_ROM
5747 
// WB ROM
5748 
`define MODULE wb_b4_rom
5749 
module `BASE`MODULE (
5750 
`undef MODULE
5751 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5752 
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
5753 
 
5754 
    parameter dat_width = 32;
5755 
    parameter dat_default = 32'h15000000;
5756 
    parameter adr_width = 32;
5757 
 
5758 
/*
5759 
`ifndef ROM
5760 
`define ROM "rom.v"
5761 
`endif
5762 
*/
5763 
    input [adr_width-1:2]   wb_adr_i;
5764 
    input                   wb_stb_i;
5765 
    input                   wb_cyc_i;
5766 
    output [dat_width-1:0]  wb_dat_o;
5767 
    reg [dat_width-1:0]     wb_dat_o;
5768 
    output                  wb_ack_o;
5769 
    reg                     wb_ack_o;
5770 
    output                  stall_o;
5771 
    input                   wb_clk;
5772 
    input                   wb_rst;
5773 
 
5774 
always @ (posedge wb_clk or posedge wb_rst)
5775 
    if (wb_rst)
5776 
        wb_dat_o <= {dat_width{1'b0}};
5777 
    else
5778 
         case (wb_adr_i[adr_width-1:2])
5779 
`ifdef ROM
5780 
`include `ROM
5781 
`endif
5782 
           default:
5783 
             wb_dat_o <= dat_default;
5784 
 
5785 
         endcase // case (wb_adr_i)
5786 
 
5787 
 
5788 
always @ (posedge wb_clk or posedge wb_rst)
5789 
    if (wb_rst)
5790 
        wb_ack_o <= 1'b0;
5791 
    else
5792 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
5793 
 
5794 
assign stall_o = 1'b0;
5795 
 
5796 
endmodule
5797 
`endif
5798 
 
5799 
 
5800 40 unneback 
`ifdef WB_BOOT_ROM
5801 17 unneback 
// WB ROM
5802 40 unneback 
`define MODULE wb_boot_rom
5803 
module `BASE`MODULE (
5804 
`undef MODULE
5805 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5806 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
5807 17 unneback 
 
5808 18 unneback 
    parameter adr_hi = 31;
5809 
    parameter adr_lo = 28;
5810 
    parameter adr_sel = 4'hf;
5811 
    parameter addr_width = 5;
5812 33 unneback 
/*
5813 17 unneback 
`ifndef BOOT_ROM
5814 
`define BOOT_ROM "boot_rom.v"
5815 
`endif
5816 33 unneback 
*/
5817 18 unneback 
    input [adr_hi:2]    wb_adr_i;
5818 
    input               wb_stb_i;
5819 
    input               wb_cyc_i;
5820 
    output [31:0]        wb_dat_o;
5821 
    output              wb_ack_o;
5822 
    output              hit_o;
5823 
    input               wb_clk;
5824 
    input               wb_rst;
5825 
 
5826 
    wire hit;
5827 
    reg [31:0] wb_dat;
5828 
    reg wb_ack;
5829 
 
5830 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
5831 17 unneback 
 
5832 
always @ (posedge wb_clk or posedge wb_rst)
5833 
    if (wb_rst)
5834 18 unneback 
        wb_dat <= 32'h15000000;
5835 17 unneback 
    else
5836 18 unneback 
         case (wb_adr_i[addr_width-1:2])
5837 33 unneback 
`ifdef BOOT_ROM
5838 17 unneback 
`include `BOOT_ROM
5839 33 unneback 
`endif
5840 17 unneback 
           /*
5841 
            // Zero r0 and jump to 0x00000100
5842 18 unneback 
 
5843 
            1 : wb_dat <= 32'hA8200000;
5844 
            2 : wb_dat <= 32'hA8C00100;
5845 
            3 : wb_dat <= 32'h44003000;
5846 
            4 : wb_dat <= 32'h15000000;
5847 17 unneback 
            */
5848 
           default:
5849 18 unneback 
             wb_dat <= 32'h00000000;
5850 17 unneback 
 
5851 
         endcase // case (wb_adr_i)
5852 
 
5853 
 
5854 
always @ (posedge wb_clk or posedge wb_rst)
5855 
    if (wb_rst)
5856 18 unneback 
        wb_ack <= 1'b0;
5857 17 unneback 
    else
5858 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
5859 17 unneback 
 
5860 18 unneback 
assign hit_o = hit;
5861 
assign wb_dat_o = wb_dat & {32{wb_ack}};
5862 
assign wb_ack_o = wb_ack;
5863 
 
5864 17 unneback 
endmodule
5865 40 unneback 
`endif
5866 32 unneback 
 
5867 92 unneback 
`ifdef WB_B3_DPRAM
5868 
`define MODULE wb_b3_dpram
5869 40 unneback 
module `BASE`MODULE (
5870 
`undef MODULE
5871 32 unneback 
        // wishbone slave side a
5872 92 unneback 
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
5873 32 unneback 
        wbsa_clk, wbsa_rst,
5874 92 unneback 
        // wishbone slave side b
5875 
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
5876 32 unneback 
        wbsb_clk, wbsb_rst);
5877 
 
5878 92 unneback 
parameter data_width_a = 32;
5879 
parameter data_width_b = data_width_a;
5880 
parameter addr_width_a = 8;
5881 
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
5882 101 unneback 
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
5883 92 unneback 
parameter max_burst_width_a = 4;
5884 
parameter max_burst_width_b = max_burst_width_a;
5885 101 unneback 
parameter mode = "B3";
5886 92 unneback 
input [data_width_a-1:0] wbsa_dat_i;
5887 
input [addr_width_a-1:0] wbsa_adr_i;
5888 
input [data_width_a/8-1:0] wbsa_sel_i;
5889 
input [2:0] wbsa_cti_i;
5890 
input [1:0] wbsa_bte_i;
5891 32 unneback 
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
5892 92 unneback 
output [data_width_a-1:0] wbsa_dat_o;
5893 32 unneback 
output wbsa_ack_o;
5894 
input wbsa_clk, wbsa_rst;
5895 
 
5896 92 unneback 
input [data_width_b-1:0] wbsb_dat_i;
5897 
input [addr_width_b-1:0] wbsb_adr_i;
5898 
input [data_width_b/8-1:0] wbsb_sel_i;
5899 
input [2:0] wbsb_cti_i;
5900 
input [1:0] wbsb_bte_i;
5901 32 unneback 
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
5902 92 unneback 
output [data_width_b-1:0] wbsb_dat_o;
5903 32 unneback 
output wbsb_ack_o;
5904 
input wbsb_clk, wbsb_rst;
5905 
 
5906 92 unneback 
wire [addr_width_a-1:0] adr_a;
5907 
wire [addr_width_b-1:0] adr_b;
5908 101 unneback 
wire we_a, we_b;
5909 
generate
5910 
if (mode=="B3") begin : b3_inst
5911 92 unneback 
`define MODULE wb_adr_inc
5912 
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
5913 
    .cyc_i(wbsa_cyc_i),
5914 
    .stb_i(wbsa_stb_i),
5915 
    .cti_i(wbsa_cti_i),
5916 
    .bte_i(wbsa_bte_i),
5917 
    .adr_i(wbsa_adr_i),
5918 
    .we_i(wbsa_we_i),
5919 
    .ack_o(wbsa_ack_o),
5920 
    .adr_o(adr_a),
5921 
    .clk(wbsa_clk),
5922 
    .rst(wbsa_rst));
5923 101 unneback 
assign we_a = wbsa_we_i & wbsa_ack_o;
5924 92 unneback 
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
5925 
    .cyc_i(wbsb_cyc_i),
5926 
    .stb_i(wbsb_stb_i),
5927 
    .cti_i(wbsb_cti_i),
5928 
    .bte_i(wbsb_bte_i),
5929 
    .adr_i(wbsb_adr_i),
5930 
    .we_i(wbsb_we_i),
5931 
    .ack_o(wbsb_ack_o),
5932 
    .adr_o(adr_b),
5933 
    .clk(wbsb_clk),
5934 
    .rst(wbsb_rst));
5935 40 unneback 
`undef MODULE
5936 101 unneback 
assign we_b = wbsb_we_i & wbsb_ack_o;
5937 
end else if (mode=="B4") begin : b4_inst
5938 
always @ (posedge wbsa_clk or posedge wbsa_rst)
5939 
    if (wbsa_rst)
5940 
        wbsa_ack_o <= 1'b0;
5941 
    else
5942 
        wbsa_ack_o <= wbsa_stb_i & wbsa_cyc_i;
5943 
assign wbsa_stall_o = 1'b0;
5944 
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
5945 
always @ (posedge wbsb_clk or posedge wbsb_rst)
5946 
    if (wbsb_rst)
5947 
        wbsb_ack_o <= 1'b0;
5948 
    else
5949 
        wbsb_ack_o <= wbsb_stb_i & wbsb_cyc_i;
5950 
assign wbsb_stall_o = 1'b0;
5951 
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
5952 
end
5953 
endgenerate
5954 92 unneback 
 
5955 
`define MODULE dpram_be_2r2w
5956 
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
5957 
`undef MODULE
5958 
ram_i (
5959 32 unneback 
    .d_a(wbsa_dat_i),
5960 92 unneback 
    .q_a(wbsa_dat_o),
5961 
    .adr_a(adr_a),
5962 
    .be_a(wbsa_sel_i),
5963 101 unneback 
    .we_a(we_a),
5964 32 unneback 
    .clk_a(wbsa_clk),
5965 
    .d_b(wbsb_dat_i),
5966 92 unneback 
    .q_b(wbsb_dat_o),
5967 
    .adr_b(adr_b),
5968 
    .be_b(wbsb_sel_i),
5969 101 unneback 
    .we_b(we_b),
5970 32 unneback 
    .clk_b(wbsb_clk) );
5971 
 
5972 
endmodule
5973 40 unneback 
`endif
5974 94 unneback 
 
5975 101 unneback 
`ifdef WB_CACHE
5976 
`define MODULE wb_cache
5977 97 unneback 
module `BASE`MODULE (
5978 98 unneback 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5979 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
5980 97 unneback 
);
5981 
`undef MODULE
5982 
 
5983 
parameter dw_s = 32;
5984 
parameter aw_s = 24;
5985 
parameter dw_m = dw_s;
5986 100 unneback 
localparam aw_m = dw_s * aw_s / dw_m;
5987 
parameter wbs_max_burst_width = 4;
5988 97 unneback 
 
5989 
parameter async = 1; // wbs_clk != wbm_clk
5990 
 
5991 
parameter nr_of_ways = 1;
5992 
parameter aw_offset = 4; // 4 => 16 words per cache line
5993 
parameter aw_slot = 10;
5994 100 unneback 
 
5995 
parameter valid_mem = 0;
5996 
parameter debug = 0;
5997 
 
5998 
localparam aw_b_offset = aw_offset * dw_s / dw_m;
5999 98 unneback 
localparam aw_tag = aw_s - aw_slot - aw_offset;
6000 97 unneback 
parameter wbm_burst_size = 4; // valid options 4,8,16
6001 98 unneback 
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
6002 97 unneback 
`define SIZE2WIDTH wbm_burst_size
6003 
localparam wbm_burst_width `SIZE2WIDTH_EXPR
6004 
`undef SIZE2WIDTH
6005 
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
6006 
`define SIZE2WIDTH nr_of_wbm_burst
6007 
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
6008 
`undef SIZE2WIDTH
6009 100 unneback 
 
6010 97 unneback 
input [dw_s-1:0] wbs_dat_i;
6011 
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
6012 98 unneback 
input [dw_s/8-1:0] wbs_sel_i;
6013 97 unneback 
input [2:0] wbs_cti_i;
6014 
input [1:0] wbs_bte_i;
6015 98 unneback 
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
6016 97 unneback 
output [dw_s-1:0] wbs_dat_o;
6017 
output wbs_ack_o;
6018 
input wbs_clk, wbs_rst;
6019 
 
6020 
output [dw_m-1:0] wbm_dat_o;
6021 
output [aw_m-1:0] wbm_adr_o;
6022 
output [dw_m/8-1:0] wbm_sel_o;
6023 
output [2:0] wbm_cti_o;
6024 
output [1:0] wbm_bte_o;
6025 98 unneback 
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
6026 97 unneback 
input [dw_m-1:0] wbm_dat_i;
6027 
input wbm_ack_i;
6028 
input wbm_stall_i;
6029 
input wbm_clk, wbm_rst;
6030 
 
6031 100 unneback 
wire valid, dirty, hit;
6032 97 unneback 
wire [aw_tag-1:0] tag;
6033 
wire tag_mem_we;
6034 
wire [aw_tag-1:0] wbs_adr_tag;
6035 
wire [aw_slot-1:0] wbs_adr_slot;
6036 98 unneback 
wire [aw_offset-1:0] wbs_adr_word;
6037 
wire [aw_s-1:0] wbs_adr;
6038 97 unneback 
 
6039 
reg [1:0] state;
6040 
localparam idle = 2'h0;
6041 
localparam rdwr = 2'h1;
6042 
localparam push = 2'h2;
6043 
localparam pull = 2'h3;
6044 
wire eoc;
6045 
 
6046 
// cdc
6047 
wire done, mem_alert, mem_done;
6048 
 
6049 98 unneback 
// wbm side
6050 
reg [aw_m-1:0] wbm_radr;
6051 
reg [aw_m-1:0] wbm_wadr;
6052 100 unneback 
wire [aw_slot-1:0] wbm_adr;
6053 98 unneback 
wire wbm_radr_cke, wbm_wadr_cke;
6054 
 
6055 100 unneback 
reg [2:0] phase;
6056 
// phase = {we,stb,cyc}
6057 
localparam wbm_wait     = 3'b000;
6058 
localparam wbm_wr       = 3'b111;
6059 
localparam wbm_wr_drain = 3'b101;
6060 
localparam wbm_rd       = 3'b011;
6061 
localparam wbm_rd_drain = 3'b001;
6062 98 unneback 
 
6063 97 unneback 
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
6064 
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
6065 
 
6066 100 unneback 
generate
6067 
if (valid_mem==0) begin : no_valid_mem
6068 
assign valid = 1'b1;
6069 
end else begin : valid_mem_inst
6070 
`define MODULE dpram_1r1w
6071 97 unneback 
`BASE`MODULE
6072 100 unneback 
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6073 
    valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6074 
                .q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6075 97 unneback 
`undef MODULE
6076 100 unneback 
end
6077 
endgenerate
6078 97 unneback 
 
6079 100 unneback 
`define MODULE dpram_1r1w
6080 
`BASE`MODULE
6081 
    # ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6082 
    tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6083 
              .q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6084 
assign hit = wbs_adr_tag == tag;
6085 
`undef MODULE
6086 
 
6087 
`define MODULE dpram_1r2w
6088 
`BASE`MODULE
6089 
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6090 
    dirty_mem (
6091 
        .d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
6092 
        .d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
6093 
`undef MODULE
6094 
 
6095 97 unneback 
`define MODULE wb_adr_inc
6096 100 unneback 
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
6097 
    .cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
6098 
    .stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
6099 97 unneback 
    .cti_i(wbs_cti_i),
6100 
    .bte_i(wbs_bte_i),
6101 
    .adr_i(wbs_adr_i),
6102 
    .we_i (wbs_we_i),
6103 
    .ack_o(wbs_ack_o),
6104 
    .adr_o(wbs_adr),
6105 100 unneback 
    .clk(wbs_clk),
6106 
    .rst(wbs_rst));
6107 97 unneback 
`undef MODULE
6108 
 
6109 
`define MODULE dpram_be_2r2w
6110 
`BASE`MODULE
6111 100 unneback 
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
6112 
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(wbs_cyc_i &  wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
6113 
                .d_b(wbm_dat_i), .adr_b(wbm_adr_o[aw_slot+aw_offset-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
6114 
//                .d_b(wbm_dat_i), .adr_b(wbm_adr), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
6115 97 unneback 
`undef MODULE
6116 
 
6117 
always @ (posedge wbs_clk or posedge wbs_rst)
6118 
if (wbs_rst)
6119 98 unneback 
    state <= idle;
6120 97 unneback 
else
6121 
    case (state)
6122 
    idle:
6123 
        if (wbs_cyc_i)
6124 
            state <= rdwr;
6125 
    rdwr:
6126 100 unneback 
        casex ({valid, hit, dirty, eoc})
6127 
        4'b0xxx: state <= pull;
6128 
        4'b11x1: state <= idle;
6129 
        4'b101x: state <= push;
6130 
        4'b100x: state <= pull;
6131 
        endcase
6132 97 unneback 
    push:
6133 
        if (done)
6134 
            state <= rdwr;
6135 
    pull:
6136 
        if (done)
6137 
            state <= rdwr;
6138 
    default: state <= idle;
6139 
    endcase
6140 
 
6141 
// cdc
6142 
generate
6143 
if (async==1) begin : cdc0
6144 
`define MODULE cdc
6145 100 unneback 
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
6146 97 unneback 
`undef MODULE
6147 
end
6148 
else begin : nocdc
6149 100 unneback 
    assign mem_alert = state==rdwr & (!valid | !hit);
6150 97 unneback 
    assign done = mem_done;
6151 
end
6152 
endgenerate
6153 
 
6154 
// FSM generating a number of burts 4 cycles
6155 
// actual number depends on data width ratio
6156 
// nr_of_wbm_burst
6157 101 unneback 
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0]       cnt_rw, cnt_ack;
6158 97 unneback 
 
6159 
always @ (posedge wbm_clk or posedge wbm_rst)
6160 
if (wbm_rst)
6161 100 unneback 
    cnt_rw <= {wbm_burst_width{1'b0}};
6162 97 unneback 
else
6163 100 unneback 
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
6164 
        cnt_rw <= cnt_rw + 1;
6165 97 unneback 
 
6166 98 unneback 
always @ (posedge wbm_clk or posedge wbm_rst)
6167 
if (wbm_rst)
6168 100 unneback 
    cnt_ack <= {wbm_burst_width{1'b0}};
6169 98 unneback 
else
6170 100 unneback 
    if (wbm_ack_i)
6171 
        cnt_ack <= cnt_ack + 1;
6172 97 unneback 
 
6173 100 unneback 
generate
6174 101 unneback 
if (nr_of_wbm_burst==1) begin : one_burst
6175 100 unneback 
 
6176 98 unneback 
always @ (posedge wbm_clk or posedge wbm_rst)
6177 
if (wbm_rst)
6178 
    phase <= wbm_wait;
6179 
else
6180 
    case (phase)
6181 
    wbm_wait:
6182 
        if (mem_alert)
6183 100 unneback 
            if (state==push)
6184 
                phase <= wbm_wr;
6185 
            else
6186 
                phase <= wbm_rd;
6187 98 unneback 
    wbm_wr:
6188 100 unneback 
        if (&cnt_rw)
6189 
            phase <= wbm_wr_drain;
6190 
    wbm_wr_drain:
6191 
        if (&cnt_ack)
6192 98 unneback 
            phase <= wbm_rd;
6193 
    wbm_rd:
6194 100 unneback 
        if (&cnt_rw)
6195 
            phase <= wbm_rd_drain;
6196 
    wbm_rd_drain:
6197 
        if (&cnt_ack)
6198 
            phase <= wbm_wait;
6199 98 unneback 
    default: phase <= wbm_wait;
6200 
    endcase
6201 
 
6202 100 unneback 
end else begin : multiple_burst
6203 
 
6204 101 unneback 
always @ (posedge wbm_clk or posedge wbm_rst)
6205 
if (wbm_rst)
6206 
    phase <= wbm_wait;
6207 
else
6208 
    case (phase)
6209 
    wbm_wait:
6210 
        if (mem_alert)
6211 
            if (state==push)
6212 
                phase <= wbm_wr;
6213 
            else
6214 
                phase <= wbm_rd;
6215 
    wbm_wr:
6216 
        if (&cnt_rw[wbm_burst_width-1:0])
6217 
            phase <= wbm_wr_drain;
6218 
    wbm_wr_drain:
6219 
        if (&cnt_ack)
6220 
            phase <= wbm_rd;
6221 
        else if (&cnt_ack[wbm_burst_width-1:0])
6222 
            phase <= wbm_wr;
6223 
    wbm_rd:
6224 
        if (&cnt_rw[wbm_burst_width-1:0])
6225 
            phase <= wbm_rd_drain;
6226 
    wbm_rd_drain:
6227 
        if (&cnt_ack)
6228 
            phase <= wbm_wait;
6229 
        else if (&cnt_ack[wbm_burst_width-1:0])
6230 
            phase <= wbm_rd;
6231 
    default: phase <= wbm_wait;
6232 
    endcase
6233 100 unneback 
 
6234 101 unneback 
 
6235 100 unneback 
end
6236 
endgenerate
6237 
 
6238 101 unneback 
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
6239 100 unneback 
 
6240 
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
6241 
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
6242 
assign wbm_sel_o = {dw_m/8{1'b1}};
6243 
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
6244 98 unneback 
assign wbm_bte_o = bte;
6245 100 unneback 
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
6246 98 unneback 
 
6247 97 unneback 
endmodule
6248 
`endif
6249 18 unneback 
//////////////////////////////////////////////////////////////////////
6250 
////                                                              ////
6251 
////  Arithmetic functions                                        ////
6252 
////                                                              ////
6253 
////  Description                                                 ////
6254 
////  Arithmetic functions for ALU and DSP                        ////
6255 
////                                                              ////
6256 
////                                                              ////
6257 
////  To Do:                                                      ////
6258 
////   -                                                          ////
6259 
////                                                              ////
6260 
////  Author(s):                                                  ////
6261 
////      - Michael Unneback, unneback@opencores.org              ////
6262 
////        ORSoC AB                                              ////
6263 
////                                                              ////
6264 
//////////////////////////////////////////////////////////////////////
6265 
////                                                              ////
6266 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
6267 
////                                                              ////
6268 
//// This source file may be used and distributed without         ////
6269 
//// restriction provided that this copyright statement is not    ////
6270 
//// removed from the file and that any derivative work contains  ////
6271 
//// the original copyright notice and the associated disclaimer. ////
6272 
////                                                              ////
6273 
//// This source file is free software; you can redistribute it   ////
6274 
//// and/or modify it under the terms of the GNU Lesser General   ////
6275 
//// Public License as published by the Free Software Foundation; ////
6276 
//// either version 2.1 of the License, or (at your option) any   ////
6277 
//// later version.                                               ////
6278 
////                                                              ////
6279 
//// This source is distributed in the hope that it will be       ////
6280 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
6281 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
6282 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
6283 
//// details.                                                     ////
6284 
////                                                              ////
6285 
//// You should have received a copy of the GNU Lesser General    ////
6286 
//// Public License along with this source; if not, download it   ////
6287 
//// from http://www.opencores.org/lgpl.shtml                     ////
6288 
////                                                              ////
6289 
//////////////////////////////////////////////////////////////////////
6290 
 
6291 40 unneback 
`ifdef MULTS
6292 18 unneback 
// signed multiplication
6293 40 unneback 
`define MODULE mults
6294 
module `BASE`MODULE (a,b,p);
6295 
`undef MODULE
6296 18 unneback 
parameter operand_a_width = 18;
6297 
parameter operand_b_width = 18;
6298 
parameter result_hi = 35;
6299 
parameter result_lo = 0;
6300 
input [operand_a_width-1:0] a;
6301 
input [operand_b_width-1:0] b;
6302 
output [result_hi:result_lo] p;
6303 
wire signed [operand_a_width-1:0] ai;
6304 
wire signed [operand_b_width-1:0] bi;
6305 
wire signed [operand_a_width+operand_b_width-1:0] result;
6306 
 
6307 
    assign ai = a;
6308 
    assign bi = b;
6309 
    assign result = ai * bi;
6310 
    assign p = result[result_hi:result_lo];
6311 
 
6312 
endmodule
6313 40 unneback 
`endif
6314 
`ifdef MULTS18X18
6315 
`define MODULE mults18x18
6316 
module `BASE`MODULE (a,b,p);
6317 
`undef MODULE
6318 18 unneback 
input [17:0] a,b;
6319 
output [35:0] p;
6320 
vl_mult
6321 
    # (.operand_a_width(18), .operand_b_width(18))
6322 
    mult0 (.a(a), .b(b), .p(p));
6323 
endmodule
6324 40 unneback 
`endif
6325 18 unneback 
 
6326 40 unneback 
`ifdef MULT
6327 
`define MODULE mult
6328 18 unneback 
// unsigned multiplication
6329 40 unneback 
module `BASE`MODULE (a,b,p);
6330 
`undef MODULE
6331 18 unneback 
parameter operand_a_width = 18;
6332 
parameter operand_b_width = 18;
6333 
parameter result_hi = 35;
6334 
parameter result_lo = 0;
6335 
input [operand_a_width-1:0] a;
6336 
input [operand_b_width-1:0] b;
6337 
output [result_hi:result_hi] p;
6338 
 
6339 
wire [operand_a_width+operand_b_width-1:0] result;
6340 
 
6341 
    assign result = a * b;
6342 
    assign p = result[result_hi:result_lo];
6343 
 
6344 
endmodule
6345 40 unneback 
`endif
6346 18 unneback 
 
6347 40 unneback 
`ifdef SHIFT_UNIT_32
6348 
`define MODULE shift_unit_32
6349 18 unneback 
// shift unit
6350 
// supporting the following shift functions
6351 
//   SLL
6352 
//   SRL
6353 
//   SRA
6354 
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
6355 40 unneback 
module `BASE`MODULE( din, s, dout, opcode);
6356 
`undef MODULE
6357 18 unneback 
input [31:0] din; // data in operand
6358 
input [4:0] s; // shift operand
6359 
input [1:0] opcode;
6360 
output [31:0] dout;
6361 
 
6362 
parameter opcode_sll = 2'b00;
6363 
//parameter opcode_srl = 2'b01;
6364 
parameter opcode_sra = 2'b10;
6365 
//parameter opcode_ror = 2'b11;
6366 
 
6367 
wire sll, sra;
6368 
assign sll = opcode == opcode_sll;
6369 
assign sra = opcode == opcode_sra;
6370 
 
6371 
wire [15:1] s1;
6372 
wire [3:0] sign;
6373 
wire [7:0] tmp [0:3];
6374 
 
6375 
// first stage is multiplier based
6376 
// shift operand as fractional 8.7
6377 
assign s1[15] = sll & s[2:0]==3'd7;
6378 
assign s1[14] = sll & s[2:0]==3'd6;
6379 
assign s1[13] = sll & s[2:0]==3'd5;
6380 
assign s1[12] = sll & s[2:0]==3'd4;
6381 
assign s1[11] = sll & s[2:0]==3'd3;
6382 
assign s1[10] = sll & s[2:0]==3'd2;
6383 
assign s1[ 9] = sll & s[2:0]==3'd1;
6384 
assign s1[ 8] = s[2:0]==3'd0;
6385 
assign s1[ 7] = !sll & s[2:0]==3'd1;
6386 
assign s1[ 6] = !sll & s[2:0]==3'd2;
6387 
assign s1[ 5] = !sll & s[2:0]==3'd3;
6388 
assign s1[ 4] = !sll & s[2:0]==3'd4;
6389 
assign s1[ 3] = !sll & s[2:0]==3'd5;
6390 
assign s1[ 2] = !sll & s[2:0]==3'd6;
6391 
assign s1[ 1] = !sll & s[2:0]==3'd7;
6392 
 
6393 
assign sign[3] = din[31] & sra;
6394 
assign sign[2] = sign[3] & (&din[31:24]);
6395 
assign sign[1] = sign[2] & (&din[23:16]);
6396 
assign sign[0] = sign[1] & (&din[15:8]);
6397 40 unneback 
`define MODULE mults
6398 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
6399 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
6400 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
6401 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
6402 
`undef MODULE
6403 18 unneback 
// second stage is multiplexer based
6404 
// shift on byte level
6405 
 
6406 
// mux byte 3
6407 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
6408 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
6409 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
6410 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
6411 
                     {8{sign[3]}};
6412 
 
6413 
// mux byte 2
6414 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
6415 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
6416 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
6417 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
6418 
                     (s[4:3]==2'b01) ? tmp[3] :
6419 
                     {8{sign[3]}};
6420 
 
6421 
// mux byte 1
6422 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
6423 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
6424 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
6425 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
6426 
                     (s[4:3]==2'b01) ? tmp[2] :
6427 
                     (s[4:3]==2'b10) ? tmp[3] :
6428 
                     {8{sign[3]}};
6429 
 
6430 
// mux byte 0
6431 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
6432 
                     (sll) ?  {8{1'b0}}:
6433 
                     (s[4:3]==2'b01) ? tmp[1] :
6434 
                     (s[4:3]==2'b10) ? tmp[2] :
6435 
                     tmp[3];
6436 
 
6437 
endmodule
6438 40 unneback 
`endif
6439 18 unneback 
 
6440 40 unneback 
`ifdef LOGIC_UNIT
6441 18 unneback 
// logic unit
6442 
// supporting the following logic functions
6443 
//    a and b
6444 
//    a or  b
6445 
//    a xor b
6446 
//    not b
6447 40 unneback 
`define MODULE logic_unit
6448 
module `BASE`MODULE( a, b, result, opcode);
6449 
`undef MODULE
6450 18 unneback 
parameter width = 32;
6451 
parameter opcode_and = 2'b00;
6452 
parameter opcode_or  = 2'b01;
6453 
parameter opcode_xor = 2'b10;
6454 
input [width-1:0] a,b;
6455 
output [width-1:0] result;
6456 
input [1:0] opcode;
6457 
 
6458 
assign result = (opcode==opcode_and) ? a & b :
6459 
                (opcode==opcode_or)  ? a | b :
6460 
                (opcode==opcode_xor) ? a ^ b :
6461 
                b;
6462 
 
6463 
endmodule
6464 48 unneback 
`endif
6465 18 unneback 
 
6466 48 unneback 
`ifdef ARITH_UNIT
6467 
`define MODULE arith_unit
6468 
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
6469 
`undef MODULE
6470 18 unneback 
parameter width = 32;
6471 
parameter opcode_add = 1'b0;
6472 
parameter opcode_sub = 1'b1;
6473 
input [width-1:0] a,b;
6474 
input c_in, add_sub, sign;
6475 
output [width-1:0] result;
6476 
output c_out, z, ovfl;
6477 
 
6478 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
6479 
assign z = (result=={width{1'b0}});
6480 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
6481 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
6482 
endmodule
6483 40 unneback 
`endif
6484 48 unneback 
 
6485 
`ifdef COUNT_UNIT
6486 
`define MODULE count_unit
6487 
module `BASE`MODULE (din, dout, opcode);
6488 
`undef MODULE
6489 
parameter width = 32;
6490 
input [width-1:0] din;
6491 
output [width-1:0] dout;
6492 
input opcode;
6493 
 
6494 
integer i;
6495 58 unneback 
wire [width/32+4:0] ff1, fl1;
6496 48 unneback 
 
6497 57 unneback 
/*
6498 48 unneback 
always @(din) begin
6499 
    ff1 = 0; i = 0;
6500 
    while (din[i] == 0 && i < width) begin // complex condition
6501 
        ff1 = ff1 + 1;
6502 
        i = i + 1;
6503 
    end
6504 
end
6505 
 
6506 
always @(din) begin
6507 
    fl1 = width; i = width-1;
6508 
    while (din[i] == 0 && i >= width) begin // complex condition
6509 
        fl1 = fl1 - 1;
6510 
        i = i - 1;
6511 
    end
6512 
end
6513 57 unneback 
*/
6514 48 unneback 
 
6515 
generate
6516 
if (width==32) begin
6517 57 unneback 
 
6518 
    assign ff1 = din[0] ? 6'd1 :
6519 
                 din[1] ? 6'd2 :
6520 
                 din[2] ? 6'd3 :
6521 
                 din[3] ? 6'd4 :
6522 
                 din[4] ? 6'd5 :
6523 
                 din[5] ? 6'd6 :
6524 
                 din[6] ? 6'd7 :
6525 
                 din[7] ? 6'd8 :
6526 
                 din[8] ? 6'd9 :
6527 
                 din[9] ? 6'd10 :
6528 
                 din[10] ? 6'd11 :
6529 
                 din[11] ? 6'd12 :
6530 
                 din[12] ? 6'd13 :
6531 
                 din[13] ? 6'd14 :
6532 
                 din[14] ? 6'd15 :
6533 
                 din[15] ? 6'd16 :
6534 
                 din[16] ? 6'd17 :
6535 
                 din[17] ? 6'd18 :
6536 
                 din[18] ? 6'd19 :
6537 
                 din[19] ? 6'd20 :
6538 
                 din[20] ? 6'd21 :
6539 
                 din[21] ? 6'd22 :
6540 
                 din[22] ? 6'd23 :
6541 
                 din[23] ? 6'd24 :
6542 
                 din[24] ? 6'd25 :
6543 
                 din[25] ? 6'd26 :
6544 
                 din[26] ? 6'd27 :
6545 
                 din[27] ? 6'd28 :
6546 
                 din[28] ? 6'd29 :
6547 
                 din[29] ? 6'd30 :
6548 
                 din[30] ? 6'd31 :
6549 
                 din[31] ? 6'd32 :
6550 
                 6'd0;
6551 
 
6552 
    assign fl1 = din[31] ? 6'd32 :
6553 
                 din[30] ? 6'd31 :
6554 
                 din[29] ? 6'd30 :
6555 
                 din[28] ? 6'd29 :
6556 
                 din[27] ? 6'd28 :
6557 
                 din[26] ? 6'd27 :
6558 
                 din[25] ? 6'd26 :
6559 
                 din[24] ? 6'd25 :
6560 
                 din[23] ? 6'd24 :
6561 
                 din[22] ? 6'd23 :
6562 
                 din[21] ? 6'd22 :
6563 
                 din[20] ? 6'd21 :
6564 
                 din[19] ? 6'd20 :
6565 
                 din[18] ? 6'd19 :
6566 
                 din[17] ? 6'd18 :
6567 
                 din[16] ? 6'd17 :
6568 
                 din[15] ? 6'd16 :
6569 
                 din[14] ? 6'd15 :
6570 
                 din[13] ? 6'd14 :
6571 
                 din[12] ? 6'd13 :
6572 
                 din[11] ? 6'd12 :
6573 
                 din[10] ? 6'd11 :
6574 
                 din[9] ? 6'd10 :
6575 
                 din[8] ? 6'd9 :
6576 
                 din[7] ? 6'd8 :
6577 
                 din[6] ? 6'd7 :
6578 
                 din[5] ? 6'd6 :
6579 
                 din[4] ? 6'd5 :
6580 
                 din[3] ? 6'd4 :
6581 
                 din[2] ? 6'd3 :
6582 
                 din[1] ? 6'd2 :
6583 
                 din[0] ? 6'd1 :
6584 
                 6'd0;
6585 
 
6586 
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
6587 48 unneback 
end
6588 
endgenerate
6589 57 unneback 
 
6590 48 unneback 
generate
6591 
if (width==64) begin
6592 57 unneback 
    assign ff1 = 7'd0;
6593 
    assign fl1 = 7'd0;
6594 
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
6595 48 unneback 
end
6596 
endgenerate
6597 
 
6598 
endmodule
6599 
`endif
6600 
 
6601 
`ifdef EXT_UNIT
6602 
`define MODULE ext_unit
6603 
module `BASE`MODULE ( a, b, F, result, opcode);
6604 
`undef MODULE
6605 
parameter width = 32;
6606 
input [width-1:0] a, b;
6607 
input F;
6608 
output reg [width-1:0] result;
6609 
input [2:0] opcode;
6610 
 
6611 
generate
6612 
if (width==32) begin
6613 
always @ (a or b or F or opcode)
6614 
begin
6615 
    case (opcode)
6616 
    3'b000: result = {{24{1'b0}},a[7:0]};
6617 
    3'b001: result = {{24{a[7]}},a[7:0]};
6618 
    3'b010: result = {{16{1'b0}},a[7:0]};
6619 
    3'b011: result = {{16{a[15]}},a[15:0]};
6620 
    3'b110: result = (F) ? a : b;
6621 
    default: result = {b[15:0],16'h0000};
6622 
    endcase
6623 
end
6624 
end
6625 
endgenerate
6626 
 
6627 
generate
6628 
if (width==64) begin
6629 
always @ (a or b or F or opcode)
6630 
begin
6631 
    case (opcode)
6632 
    3'b000: result = {{56{1'b0}},a[7:0]};
6633 
    3'b001: result = {{56{a[7]}},a[7:0]};
6634 
    3'b010: result = {{48{1'b0}},a[7:0]};
6635 
    3'b011: result = {{48{a[15]}},a[15:0]};
6636 57 unneback 
    3'b110: result = (F) ? a : b;
6637 48 unneback 
    default: result = {32'h00000000,b[15:0],16'h0000};
6638 
    endcase
6639 
end
6640 
end
6641 
endgenerate
6642 
endmodule
6643 
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.