URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 111

Go to most recent revision | Details | Compare with Previous | View Log


`ifndef BASE
`define BASE vl_
`endif
 
// default SYN_KEEP definition
`define SYN_KEEP /*synthesis syn_keep = 1*/
 
`ifdef ACTEL
`undef SYN_KEEP
`define SYN_KEEP /*synthesis syn_keep = 1*/
`endif
 
`ifdef ACTEL
    // ACTEL FPGA should not use logic to handle rw collision
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
`else
    `define SYN_NO_RW_CHECK
`endif
 
`ifdef ALL
 
`define GBUF
`define SYNC_RST
`define PLL
 
`define MULTS
`define MULTS18X18
`define MULT
`define SHIFT_UNIT_32
`define LOGIC_UNIT
 
`define CNT_SHREG_WRAP
`define CNT_SHREG_CE_WRAP
`define CNT_SHREG_CLEAR
`define CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR_WRAP
 
`define MUX_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define PARITY
 
`define ROM_INIT
`define RAM
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_1R2W
`define DPRAM_2R2W
`define DPRAM_BE_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC
`define FIFO_2R2W_ASYNC_SIMPLEX
`define REG_FILE
 
`define DFF
`define DFF_ARRAY
`define DFF_CE
`define DFF_CE_CLEAR
`define DF_CE_SET
`define SPR
`define SRP
`define DFF_SR
`define LATCH
`define SHREG
`define SHREG_CE
`define DELAY
`define DELAY_EMPTYFLAG
`define PULSE2TOGGLE
`define TOGGLE2PULSE
`define SYNCHRONIZER
`define CDC
 
`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB_ADR_INC
`define WB_RAM
`define WB_SHADOW_RAM
`define WB_B4_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
`define WB_CACHE
`define WB_AVALON_BRIDGE
`define WB_AVALON_MEM_CACHE
 
`define IO_DFF_OE
`define O_DFF
 
`endif
 
`ifdef PLL
`ifndef SYNC_RST
`define SYNC_RST
`endif
`endif
 
`ifdef SYNC_RST
`ifndef GBUF
`define GBUF
`endif
`endif
 
`ifdef WB_DPRAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`endif
 
`ifdef WB_RAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef RAM_BE
`define RAM_BE
`endif
`endif
 
`ifdef WB3_ARBITER_TYPE1
`ifndef SPR
`define SPR
`endif
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef WB3AVALON_BRIDGE
`ifndef WB3WB3_BRIDGE
`define WB3WB3_BRIDGE
`endif
`endif
 
`ifdef WB3WB3_BRIDGE
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef DFF
`define DFF
`endif
`ifndef DFF_CE
`define DFF_CE
`endif
`ifndef CNT_SHREG_CE_CLEAR
`define CNT_SHREG_CE_CLEAR
`endif
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX
`endif
`endif
 
 
`ifdef WB_AVALON_MEM_CACHE
`ifndef WB_SHADOW_RAM
`define WB_SHADOW_RAM
`endif
`ifndef WB_CACHE
`define WB_CACHE
`endif
`ifndef WB_AVALON_BRIDGE
`define WB_AVALON_BRIDGE
`endif
`endif
 
`ifdef WB_CACHE
`ifndef RAM
`define RAM
`endif
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef DPRAM_1R2W
`define DPRAM_1R2W
`endif
`ifndef DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`endif
`ifndef CDC
`define CDC
`endif
`endif
 
`ifdef WB_SHADOW_RAM
`ifndef WB_RAM
`define WB_RAM
`endif
`endif
 
`ifdef WB_RAM
`ifndef WB_ADR_INC
`define WB_ADR_INC
`endif
`endif
 
`ifdef MULTS18X18
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef SHIFT_UNIT_32
`ifndef MULTS
`define MULTS
`endif
`endif
 
`ifdef MUX2_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX3_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX4_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX5_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef MUX6_ANDOR
`ifndef MUX_ANDOR
`define MUX_ANDOR
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_BIN_CE
`define CNT_BIN_CE
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
`define CNT_BIN_CE_REW_Q_ZQ_L1
`endif
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
`ifndef CNT_LFSR_CE
`define CNT_LFSR_CE
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef CNT_BIN_CE_REW_ZQ_L1
`define CNT_BIN_CE_REW_ZQ_L1
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_2R2W
`define DPRAM_2R2W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_2R2W_ASYNC
`ifndef FIFO_1R1W_ASYNC
`define FIFO_1R1W_ASYNC
`endif
`endif
 
`ifdef FIFO_1R1W_ASYNC
`ifndef CNT_GRAY_CE_BIN
`define CNT_GRAY_CE_BIN
`endif
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`ifndef FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
`endif
`endif
 
`ifdef FIFO_CMP_ASYNC
`ifndef DFF_SR
`define DFF_SR
`endif
`ifndef DFF
`define DFF
`endif
`endif
 
`ifdef REG_FILE
`ifndef DPRAM_1R1W
`define DPRAM_1R1W
`endif
`endif
 
`ifdef CDC
`ifndef PULSE2TOGGLE
`define PULSE2TOGGLE
`endif
`ifndef TOGGLE2PULSE
`define TOGGLE2PULSE
`endif
`ifndef SYNCHRONIZER
`define SYNCHRONIZER
`endif
`endif
 
// size to width
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile library, clock and reset                          ////
////                                                              ////
////  Description                                                 ////
////  Logic related to clock and reset                            ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////   - add more different registers                             ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`ifdef ACTEL
`ifdef GBUF
`timescale 1 ns/100 ps
// Global buffer
// usage:
// use to enable global buffers for high fan out signals such as clock and reset
// Version: 8.4 8.4.0.33
module gbuf(GL,CLK);
output GL;
input  CLK;
 
    wire GND;
 
    GND GND_1_net(.Y(GND));
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
 
endmodule
`timescale 1 ns/1 ns
`define MODULE gbuf
module `BASE`MODULE ( i, o);
`undef MODULE
input i;
output o;
`ifdef SIM_GBUF
assign o=i;
`else
gbuf gbuf_i0 ( .CLK(i), .GL(o));
`endif
endmodule
`endif
 
`else
 
`ifdef ALTERA
`ifdef GBUF
//altera
`define MODULE gbuf
module `BASE`MODULE ( i, o);
`undef MODULE
input i;
output o;
assign o = i;
endmodule
`endif
 
`else
 
`ifdef GBUF
`timescale 1 ns/100 ps
`define MODULE
module `BASE`MODULE ( i, o);
`undef MODULE
input i;
output o;
assign o = i;
endmodule
`endif
`endif // ALTERA
`endif //ACTEL
 
`ifdef SYNC_RST
// sync reset
// input active lo async reset, normally from external reset generator and/or switch
// output active high global reset sync with two DFFs 
`timescale 1 ns/100 ps
`define MODULE sync_rst
module `BASE`MODULE ( rst_n_i, rst_o, clk);
`undef MODULE
input rst_n_i, clk;
output rst_o;
reg [1:0] tmp;
always @ (posedge clk or negedge rst_n_i)
if (!rst_n_i)
        tmp <= 2'b11;
else
        tmp <= {1'b0,tmp[1]};
`define MODULE gbuf
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
`undef MODULE
endmodule
`endif
 
`ifdef PLL
// vl_pll
`ifdef ACTEL
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`define MODULE pll
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
`undef MODULE
parameter index = 0;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter lock_delay = 2000000;
input clk_i, rst_n_i;
output lock;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
 
`ifdef SIM_PLL
 
always
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
 
generate if (number_of_clk > 1)
always
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
endgenerate
 
generate if (number_of_clk > 2)
always
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
endgenerate
 
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
end
endgenerate
 
assign #lock_delay lock = rst_n_i;
 
endmodule
`else
generate if (number_of_clk==1 & index==0) begin
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
endgenerate // index==0
generate if (number_of_clk==1 & index==1) begin
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
endgenerate // index==1
generate if (number_of_clk==1 & index==2) begin
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
endgenerate // index==2
generate if (number_of_clk==1 & index==3) begin
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
endgenerate // index==0
 
generate if (number_of_clk==2 & index==0) begin
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
endgenerate // index==0
generate if (number_of_clk==2 & index==1) begin
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
endgenerate // index==1
generate if (number_of_clk==2 & index==2) begin
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
endgenerate // index==2
generate if (number_of_clk==2 & index==3) begin
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
endgenerate // index==0
 
generate if (number_of_clk==3 & index==0) begin
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
endgenerate // index==0
generate if (number_of_clk==3 & index==1) begin
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
endgenerate // index==1
generate if (number_of_clk==3 & index==2) begin
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
endgenerate // index==2
generate if (number_of_clk==3 & index==3) begin
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
endgenerate // index==0
 
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
`define MODULE sync_rst
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
`undef MODULE
end
endgenerate
endmodule
`endif
///////////////////////////////////////////////////////////////////////////////
 
`else
 
///////////////////////////////////////////////////////////////////////////////
`ifdef ALTERA
 
`timescale 1 ps/1 ps
`define MODULE pll
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
`undef MODULE
parameter index = 0;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter period_time_3 = 20000;
parameter period_time_4 = 20000;
parameter lock_delay = 2000000;
input clk_i, rst_n_i;
output lock;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
 
`ifdef SIM_PLL
 
always
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
 
generate if (number_of_clk > 1)
always
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
endgenerate
 
generate if (number_of_clk > 2)
always
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
endgenerate
 
generate if (number_of_clk > 3)
always
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
endgenerate
 
generate if (number_of_clk > 4)
always
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
endgenerate
 
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
end
endgenerate
 
//assign #lock_delay lock = rst_n_i;
assign lock = rst_n_i;
 
endmodule
`else
 
`ifdef VL_PLL0
`ifdef VL_PLL0_CLK1
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
`endif
`ifdef VL_PLL0_CLK2
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
`endif
`ifdef VL_PLL0_CLK3
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
`endif
`ifdef VL_PLL0_CLK4
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
`endif
`ifdef VL_PLL0_CLK5
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
`endif
`endif
 
`ifdef VL_PLL1
`ifdef VL_PLL1_CLK1
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
`endif
`ifdef VL_PLL1_CLK2
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
`endif
`ifdef VL_PLL1_CLK3
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
`endif
`ifdef VL_PLL1_CLK4
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
`endif
`ifdef VL_PLL1_CLK5
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
`endif
`endif
 
`ifdef VL_PLL2
`ifdef VL_PLL2_CLK1
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
`endif
`ifdef VL_PLL2_CLK2
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
`endif
`ifdef VL_PLL2_CLK3
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
`endif
`ifdef VL_PLL2_CLK4
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
`endif
`ifdef VL_PLL2_CLK5
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
`endif
`endif
 
`ifdef VL_PLL3
`ifdef VL_PLL3_CLK1
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
`endif
`ifdef VL_PLL3_CLK2
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
`endif
`ifdef VL_PLL3_CLK3
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
`endif
`ifdef VL_PLL3_CLK4
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
`endif
`ifdef VL_PLL3_CLK5
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
`endif
`endif
 
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
`define MODULE sync_rst
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
`undef MODULE
end
endgenerate
endmodule
`endif
///////////////////////////////////////////////////////////////////////////////
 
`else
 
// generic PLL
`timescale 1 ps/1 ps
`define MODULE pll
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
`undef MODULE
parameter index = 0;
parameter number_of_clk = 1;
parameter period_time_0 = 20000;
parameter period_time_1 = 20000;
parameter period_time_2 = 20000;
parameter lock_delay = 2000;
input clk_i, rst_n_i;
output lock;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
 
always
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
 
generate if (number_of_clk > 1)
always
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
endgenerate
 
generate if (number_of_clk > 2)
always
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
endgenerate
 
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
`define MODULE sync_rst
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
`undef MODULE
end
endgenerate
 
assign #lock_delay lock = rst_n_i;
 
endmodule
 
`endif //altera
`endif //actel
`undef MODULE
`endif//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile library, registers                                ////
////                                                              ////
////  Description                                                 ////
////  Different type of registers                                 ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////   - add more different registers                             ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`ifdef DFF
`define MODULE dff
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
        parameter width = 1;
        parameter reset_value = 0;
 
        input [width-1:0] d;
        input clk, rst;
        output reg [width-1:0] q;
 
        always @ (posedge clk or posedge rst)
        if (rst)
                q <= reset_value;
        else
                q <= d;
 
endmodule
`endif
 
`ifdef DFF_ARRAY
`define MODULE dff_array
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
 
        parameter width = 1;
        parameter depth = 2;
        parameter reset_value = 1'b0;
 
        input [width-1:0] d;
        input clk, rst;
        output [width-1:0] q;
        reg  [0:depth-1] q_tmp [width-1:0];
        integer i;
        always @ (posedge clk or posedge rst)
        if (rst) begin
            for (i=0;i<depth;i=i+1)
                q_tmp[i] <= {width{reset_value}};
        end else begin
            q_tmp[0] <= d;
            for (i=1;i<depth;i=i+1)
                q_tmp[i] <= q_tmp[i-1];
        end
 
    assign q = q_tmp[depth-1];
 
endmodule
`endif
 
`ifdef DFF_CE
`define MODULE dff_ce
module `BASE`MODULE ( d, ce, q, clk, rst);
`undef MODULE
 
        parameter width = 1;
        parameter reset_value = 0;
 
        input [width-1:0] d;
        input ce, clk, rst;
        output reg [width-1:0] q;
 
        always @ (posedge clk or posedge rst)
        if (rst)
                q <= reset_value;
        else
                if (ce)
                        q <= d;
 
endmodule
`endif
 
`ifdef DFF_CE_CLEAR
`define MODULE dff_ce_clear
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
`undef MODULE
 
        parameter width = 1;
        parameter reset_value = 0;
 
        input [width-1:0] d;
        input ce, clear, clk, rst;
        output reg [width-1:0] q;
 
        always @ (posedge clk or posedge rst)
        if (rst)
            q <= reset_value;
        else
            if (ce)
                if (clear)
                    q <= {width{1'b0}};
                else
                    q <= d;
 
endmodule
`endif
 
`ifdef DF_CE_SET
`define MODULE dff_ce_set
module `BASE`MODULE ( d, ce, set, q, clk, rst);
`undef MODULE
 
        parameter width = 1;
        parameter reset_value = 0;
 
        input [width-1:0] d;
        input ce, set, clk, rst;
        output reg [width-1:0] q;
 
        always @ (posedge clk or posedge rst)
        if (rst)
            q <= reset_value;
        else
            if (ce)
                if (set)
                    q <= {width{1'b1}};
                else
                    q <= d;
 
endmodule
`endif
 
`ifdef SPR
`define MODULE spr
module `BASE`MODULE ( sp, r, q, clk, rst);
`undef MODULE
 
        //parameter width = 1;
        parameter reset_value = 1'b0;
 
        input sp, r;
        output reg q;
        input clk, rst;
 
        always @ (posedge clk or posedge rst)
        if (rst)
            q <= reset_value;
        else
            if (sp)
                q <= 1'b1;
            else if (r)
                q <= 1'b0;
 
endmodule
`endif
 
`ifdef SRP
`define MODULE srp
module `BASE`MODULE ( s, rp, q, clk, rst);
`undef MODULE
 
        parameter width = 1;
        parameter reset_value = 0;
 
        input s, rp;
        output reg q;
        input clk, rst;
 
        always @ (posedge clk or posedge rst)
        if (rst)
            q <= reset_value;
        else
            if (rp)
                q <= 1'b0;
            else if (s)
                q <= 1'b1;
 
endmodule
`endif
 
`ifdef ALTERA
 
`ifdef DFF_SR
// megafunction wizard: %LPM_FF%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_ff 
 
// ============================================================
// File Name: dff_sr.v
// Megafunction Name(s):
//                      lpm_ff
//
// Simulation Library Files(s):
//                      lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
`define MODULE dff_sr
module `BASE`MODULE (
`undef MODULE
 
        aclr,
        aset,
        clock,
        data,
        q);
 
        input     aclr;
        input     aset;
        input     clock;
        input     data;
        output    q;
 
        wire [0:0] sub_wire0;
        wire [0:0] sub_wire1 = sub_wire0[0:0];
        wire  q = sub_wire1;
        wire  sub_wire2 = data;
        wire  sub_wire3 = sub_wire2;
 
        lpm_ff  lpm_ff_component (
                                .aclr (aclr),
                                .clock (clock),
                                .data (sub_wire3),
                                .aset (aset),
                                .q (sub_wire0)
                                // synopsys translate_off
                                ,
                                .aload (),
                                .enable (),
                                .sclr (),
                                .sload (),
                                .sset ()
                                // synopsys translate_on
                                );
        defparam
                lpm_ff_component.lpm_fftype = "DFF",
                lpm_ff_component.lpm_type = "LPM_FF",
                lpm_ff_component.lpm_width = 1;
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "1"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: DFF NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "1"
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
`endif
 
`else
 
`ifdef DFF_SR
`define MODULE dff_sr
module `BASE`MODULE ( aclr, aset, clock, data, q);
`undef MODULE
 
    input         aclr;
    input         aset;
    input         clock;
    input         data;
    output reg    q;
 
   always @ (posedge clock or posedge aclr or posedge aset)
     if (aclr)
       q <= 1'b0;
     else if (aset)
       q <= 1'b1;
     else
       q <= data;
 
endmodule
`endif
 
`endif
 
// LATCH
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
`ifdef ALTERA
 
`ifdef LATCH
`define MODULE latch
module `BASE`MODULE ( d, le, q, clk);
`undef MODULE
input d, le;
output q;
input clk;
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
endmodule
`endif
 
`else
 
`ifdef LATCH
`define MODULE latch
module `BASE`MODULE ( d, le, q, clk);
`undef MODULE
input d, le;
input clk;
always @ (le or d)
if (le)
    d <= q;
endmodule
`endif
 
`endif
 
`ifdef SHREG
`define MODULE shreg
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
 
parameter depth = 10;
input d;
output q;
input clk, rst;
 
reg [1:depth] dffs;
 
always @ (posedge clk or posedge rst)
if (rst)
    dffs <= {depth{1'b0}};
else
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
endmodule
`endif
 
`ifdef SHREG_CE
`define MODULE shreg_ce
module `BASE`MODULE ( d, ce, q, clk, rst);
`undef MODULE
parameter depth = 10;
input d, ce;
output q;
input clk, rst;
 
reg [1:depth] dffs;
 
always @ (posedge clk or posedge rst)
if (rst)
    dffs <= {depth{1'b0}};
else
    if (ce)
        dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
endmodule
`endif
 
`ifdef DELAY
`define MODULE delay
module `BASE`MODULE ( d, q, clk, rst);
`undef MODULE
parameter depth = 10;
input d;
output q;
input clk, rst;
 
reg [1:depth] dffs;
 
always @ (posedge clk or posedge rst)
if (rst)
    dffs <= {depth{1'b0}};
else
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
endmodule
`endif
 
`ifdef DELAY_EMPTYFLAG
`define MODULE delay_emptyflag
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
`undef MODULE
parameter depth = 10;
input d;
output q, emptyflag;
input clk, rst;
 
reg [1:depth] dffs;
 
always @ (posedge clk or posedge rst)
if (rst)
    dffs <= {depth{1'b0}};
else
    dffs <= {d,dffs[1:depth-1]};
assign q = dffs[depth];
assign emptyflag = !(|dffs);
endmodule
`endif
 
`ifdef PULSE2TOGGLE
`define MODULE pulse2toggle
module `BASE`MODULE ( pl, q, clk, rst);
`undef MODULE
input pl;
output reg q;
input clk, rst;
always @ (posedge clk or posedge rst)
if (rst)
    q <= 1'b0;
else
    q <= pl ^ q;
endmodule
`endif
 
`ifdef TOGGLE2PULSE
`define MODULE toggle2pulse
module `BASE`MODULE (d, pl, clk, rst);
`undef MODULE
input d;
output pl;
input clk, rst;
reg dff;
always @ (posedge clk or posedge rst)
if (rst)
    dff <= 1'b0;
else
    dff <= d;
assign pl = d ^ dff;
endmodule
`endif
 
`ifdef SYNCHRONIZER
`define MODULE synchronizer
module `BASE`MODULE (d, q, clk, rst);
`undef MODULE
input d;
output reg q;
output clk, rst;
reg dff;
always @ (posedge clk or posedge rst)
if (rst)
    {q,dff} <= 2'b00;
else
    {q,dff} <= {dff,d};
endmodule
`endif
 
`ifdef CDC
`define MODULE cdc
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
`undef MODULE
input start_pl;
output take_it_pl;
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
output got_it_pl;
input clk_src, rst_src;
input clk_dst, rst_dst;
wire take_it_tg, take_it_tg_sync;
wire got_it_tg, got_it_tg_sync;
// src -> dst
`define MODULE pulse2toggle
`BASE`MODULE p2t0 (
`undef MODULE
    .pl(start_pl),
    .q(take_it_tg),
    .clk(clk_src),
    .rst(rst_src));
 
`define MODULE synchronizer
`BASE`MODULE sync0 (
`undef MODULE
    .d(take_it_tg),
    .q(take_it_tg_sync),
    .clk(clk_dst),
    .rst(rst_dst));
 
`define MODULE toggle2pulse
`BASE`MODULE t2p0 (
`undef MODULE
    .d(take_it_tg_sync),
    .pl(take_it_pl),
    .clk(clk_dst),
    .rst(rst_dst));
 
// dst -> src
`define MODULE pulse2toggle
`BASE`MODULE p2t1 (
`undef MODULE
    .pl(take_it_grant_pl),
    .q(got_it_tg),
    .clk(clk_dst),
    .rst(rst_dst));
 
`define MODULE synchronizer
`BASE`MODULE sync1 (
`undef MODULE
    .d(got_it_tg),
    .q(got_it_tg_sync),
    .clk(clk_src),
    .rst(rst_src));
 
`define MODULE toggle2pulse
`BASE`MODULE t2p1 (
`undef MODULE
    .d(got_it_tg_sync),
    .pl(got_it_pl),
    .clk(clk_src),
    .rst(rst_src));
 
endmodule
`endif
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Logic functions                                             ////
////                                                              ////
////  Description                                                 ////
////  Logic functions such as multiplexers                        ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////   -                                                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
`ifdef MUX_ANDOR
`define MODULE mux_andor
module `BASE`MODULE ( a, sel, dout);
`undef MODULE
 
parameter width = 32;
parameter nr_of_ports = 4;
 
input [nr_of_ports*width-1:0] a;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
 
integer i,j;
 
always @ (a, sel)
begin
    dout = a[width-1:0] & {width{sel[0]}};
    for (i=1;i<nr_of_ports;i=i+1)
        for (j=0;j<width;j=j+1)
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
end
 
endmodule
`endif
 
`ifdef MUX2_ANDOR
`define MODULE mux2_andor
module `BASE`MODULE ( a1, a0, sel, dout);
`undef MODULE
 
parameter width = 32;
localparam nr_of_ports = 2;
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
`define MODULE mux_andor
`BASE`MODULE
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
`undef MODULE
 
endmodule
`endif
 
`ifdef MUX3_ANDOR
`define MODULE mux3_andor
module `BASE`MODULE ( a2, a1, a0, sel, dout);
`undef MODULE
 
parameter width = 32;
localparam nr_of_ports = 3;
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
`define MODULE mux_andor
`BASE`MODULE
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
`undef MODULE
endmodule
`endif
 
`ifdef MUX4_ANDOR
`define MODULE mux4_andor
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
`undef MODULE
 
parameter width = 32;
localparam nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
`define MODULE mux_andor
`BASE`MODULE
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
`undef MODULE
 
endmodule
`endif
 
`ifdef MUX5_ANDOR
`define MODULE mux5_andor
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
`undef MODULE
 
parameter width = 32;
localparam nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
`define MODULE mux_andor
`BASE`MODULE
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
`undef MODULE
 
endmodule
`endif
 
`ifdef MUX6_ANDOR
`define MODULE mux6_andor
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
`undef MODULE
 
parameter width = 32;
localparam nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
 
`define MODULE mux_andor
`BASE`MODULE
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
`undef MODULE
 
endmodule
`endif
 
`ifdef PARITY
 
`define MODULE parity_generate
module `BASE`MODULE (data, parity);
`undef MODULE
parameter word_size = 32;
parameter chunk_size = 8;
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
input [word_size-1:0] data;
output reg [word_size/chunk_size-1:0] parity;
integer i,j;
always @ (data)
for (i=0;i<word_size/chunk_size;i=i+1) begin
    parity[i] = parity_type;
    for (j=0;j<chunk_size;j=j+1) begin
        parity[i] = data[i*chunk_size+j] ^ parity[i];
    end
end
endmodule
 
`define MODULE parity_check
module `BASE`MODULE( data, parity, parity_error);
`undef MODULE
parameter word_size = 32;
parameter chunk_size = 8;
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
input [word_size-1:0] data;
input [word_size/chunk_size-1:0] parity;
output parity_error;
reg [word_size/chunk_size-1:0] error_flag;
integer i,j;
always @ (data or parity)
for (i=0;i<word_size/chunk_size;i=i+1) begin
    error_flag[i] = parity[i] ^ parity_type;
    for (j=0;j<chunk_size;j=j+1) begin
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
    end
end
assign parity_error = |error_flag;
endmodule
 
`endif//////////////////////////////////////////////////////////////////////
////                                                              ////
////  IO functions                                                ////
////                                                              ////
////  Description                                                 ////
////  IO functions such as IOB flip-flops                         ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////   -                                                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
`ifdef O_DFF
`define MODULE o_dff
module `BASE`MODULE (d_i, o_pad, clk, rst);
`undef MODULE
parameter width = 1;
parameter reset_value = {width{1'b0}};
input  [width-1:0]  d_i;
output [width-1:0] o_pad;
input clk, rst;
wire [width-1:0] d_i_int `SYN_KEEP;
reg  [width-1:0] o_pad_int;
assign d_i_int = d_i;
genvar i;
generate
for (i=0;i<width;i=i+1) begin
    always @ (posedge clk or posedge rst)
    if (rst)
        o_pad_int[i] <= reset_value[i];
    else
        o_pad_int[i] <= d_i_int[i];
    assign #1 o_pad[i] = o_pad_int[i];
end
endgenerate
endmodule
`endif
 
`timescale 1ns/1ns
`ifdef IO_DFF_OE
`define MODULE io_dff_oe
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
`undef MODULE
parameter width = 1;
input  [width-1:0] d_o;
output reg [width-1:0] d_i;
input oe;
inout [width-1:0] io_pad;
input clk, rst;
wire [width-1:0] oe_d `SYN_KEEP;
reg [width-1:0] oe_q;
reg [width-1:0] d_o_q;
assign oe_d = {width{oe}};
genvar i;
generate
for (i=0;i<width;i=i+1) begin
    always @ (posedge clk or posedge rst)
    if (rst)
        oe_q[i] <= 1'b0;
    else
        oe_q[i] <= oe_d[i];
    always @ (posedge clk or posedge rst)
    if (rst)
        d_o_q[i] <= 1'b0;
    else
        d_o_q[i] <= d_o[i];
    always @ (posedge clk or posedge rst)
    if (rst)
        d_i[i] <= 1'b0;
    else
        d_i[i] <= io_pad[i];
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
end
endgenerate
endmodule
`endif
`ifdef CNT_BIN
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// binary counter
 
`define MODULE cnt_bin
module `BASE`MODULE (
`undef MODULE
 q, rst, clk);
 
   parameter length = 4;
   output [length:1] q;
   input rst;
   input clk;
 
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter level1_value = 15;
 
   reg  [length:1] qi;
   wire [length:1] q_next;
   assign q_next = qi + {{length-1{1'b0}},1'b1};
 
   always @ (posedge clk or posedge rst)
     if (rst)
       qi <= {length{1'b0}};
     else
       qi <= q_next;
 
   assign q = qi;
 
endmodule
`endif
`ifdef CNT_BIN_CLEAR
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// binary counter
 
`define MODULE cnt_bin_clear
module `BASE`MODULE (
`undef MODULE
 clear, q, rst, clk);
 
   parameter length = 4;
   input clear;
   output [length:1] q;
   input rst;
   input clk;
 
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter level1_value = 15;
 
   reg  [length:1] qi;
   wire [length:1] q_next;
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
 
   always @ (posedge clk or posedge rst)
     if (rst)
       qi <= {length{1'b0}};
     else
       qi <= q_next;
 
   assign q = qi;
 
endmodule
`endif
`ifdef CNT_BIN_CE
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// binary counter
 
`define MODULE cnt_bin_ce
module `BASE`MODULE (
`undef MODULE
 cke, q, rst, clk);
 
   parameter length = 4;
   input cke;
   output [length:1] q;
   input rst;
   input clk;
 
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter level1_value = 15;
 
   reg  [length:1] qi;
   wire [length:1] q_next;
   assign q_next = qi + {{length-1{1'b0}},1'b1};
 
   always @ (posedge clk or posedge rst)
     if (rst)
       qi <= {length{1'b0}};
     else
     if (cke)
       qi <= q_next;
 
   assign q = qi;
 
endmodule
`endif
`ifdef CNT_BIN_CE_CLEAR
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// binary counter
 
`define MODULE cnt_bin_ce_clear
module `BASE`MODULE (
`undef MODULE
 clear, cke, q, rst, clk);
 
   parameter length = 4;
   input clear;
   input cke;
   output [length:1] q;
   input rst;
   input clk;
 
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter level1_value = 15;
 
   reg  [length:1] qi;
   wire [length:1] q_next;
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
 
   always @ (posedge clk or posedge rst)
     if (rst)
       qi <= {length{1'b0}};
     else
     if (cke)
       qi <= q_next;
 
   assign q = qi;
 
endmodule
`endif
`ifdef CNT_BIN_CE_CLEAR_L1_L2
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// binary counter
 
`define MODULE cnt_bin_ce_clear_l1_l2
module `BASE`MODULE (
`undef MODULE
 clear, cke, q, level1, level2, rst, clk);
 
   parameter length = 4;
   input clear;
   input cke;
   output [length:1] q;
   output reg level1;
   output reg level2;
   input rst;
   input clk;
 
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter wrap_value = 15;
   parameter level1_value = 8;
   parameter level2_value = 15;
 
   wire rew;
   assign rew = 1'b0;
   reg  [length:1] qi;
   wire [length:1] q_next;
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
 
   always @ (posedge clk or posedge rst)
     if (rst)
       qi <= {length{1'b0}};
     else
     if (cke)
       qi <= q_next;
 
   assign q = qi;
 
 
    always @ (posedge clk or posedge rst)
    if (rst)
        level1 <= 1'b0;
    else
    if (cke)
    if (clear)
        level1 <= 1'b0;
    else if (q_next == level1_value)
        level1 <= 1'b1;
    else if (qi == level1_value & rew)
        level1 <= 1'b0;
 
    always @ (posedge clk or posedge rst)
    if (rst)
        level2 <= 1'b0;
    else
    if (cke)
    if (clear)
        level2 <= 1'b0;
    else if (q_next == level2_value)
        level2 <= 1'b1;
    else if (qi == level2_value & rew)
        level2 <= 1'b0;
endmodule
`endif
`ifdef CNT_BIN_CE_CLEAR_SET_REW
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// binary counter
 
`define MODULE cnt_bin_ce_clear_set_rew
module `BASE`MODULE (
`undef MODULE
 clear, set, cke, rew, q, rst, clk);
 
   parameter length = 4;
   input clear;
   input set;
   input cke;
   input rew;
   output [length:1] q;
   input rst;
   input clk;
 
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter level1_value = 15;
 
   reg  [length:1] qi;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
   assign q_next = rew ? q_next_rew : q_next_fw;
 
   always @ (posedge clk or posedge rst)
     if (rst)
       qi <= {length{1'b0}};
     else
     if (cke)
       qi <= q_next;
 
   assign q = qi;
 
endmodule
`endif
`ifdef CNT_BIN_CE_REW_L1
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// binary counter
 
`define MODULE cnt_bin_ce_rew_l1
module `BASE`MODULE (
`undef MODULE
 cke, rew, level1, rst, clk);
 
   parameter length = 4;
   input cke;
   input rew;
   output reg level1;
   input rst;
   input clk;
 
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter wrap_value = 1;
   parameter level1_value = 15;
 
   wire clear;
   assign clear = 1'b0;
   reg  [length:1] qi;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
   assign q_next = rew ? q_next_rew : q_next_fw;
 
   always @ (posedge clk or posedge rst)
     if (rst)
       qi <= {length{1'b0}};
     else
     if (cke)
       qi <= q_next;
 
 
 
    always @ (posedge clk or posedge rst)
    if (rst)
        level1 <= 1'b0;
    else
    if (cke)
    if (clear)
        level1 <= 1'b0;
    else if (q_next == level1_value)
        level1 <= 1'b1;
    else if (qi == level1_value & rew)
        level1 <= 1'b0;
endmodule
`endif
`ifdef CNT_BIN_CE_REW_ZQ_L1
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// binary counter
 
`define MODULE cnt_bin_ce_rew_zq_l1
module `BASE`MODULE (
`undef MODULE
 cke, rew, zq, level1, rst, clk);
 
   parameter length = 4;
   input cke;
   input rew;
   output reg zq;
   output reg level1;
   input rst;
   input clk;
 
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter wrap_value = 1;
   parameter level1_value = 15;
 
   wire clear;
   assign clear = 1'b0;
   reg  [length:1] qi;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
   assign q_next = rew ? q_next_rew : q_next_fw;
 
   always @ (posedge clk or posedge rst)
     if (rst)
       qi <= {length{1'b0}};
     else
     if (cke)
       qi <= q_next;
 
 
 
   always @ (posedge clk or posedge rst)
     if (rst)
       zq <= 1'b1;
     else
     if (cke)
       zq <= q_next == {length{1'b0}};
 
    always @ (posedge clk or posedge rst)
    if (rst)
        level1 <= 1'b0;
    else
    if (cke)
    if (clear)
        level1 <= 1'b0;
    else if (q_next == level1_value)
        level1 <= 1'b1;
    else if (qi == level1_value & rew)
        level1 <= 1'b0;
endmodule
`endif
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// binary counter
 
`define MODULE cnt_bin_ce_rew_q_zq_l1
module `BASE`MODULE (
`undef MODULE
 cke, rew, q, zq, level1, rst, clk);
 
   parameter length = 4;
   input cke;
   input rew;
   output [length:1] q;
   output reg zq;
   output reg level1;
   input rst;
   input clk;
 
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter wrap_value = 1;
   parameter level1_value = 15;
 
   wire clear;
   assign clear = 1'b0;
   reg  [length:1] qi;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
   assign q_next = rew ? q_next_rew : q_next_fw;
 
   always @ (posedge clk or posedge rst)
     if (rst)
       qi <= {length{1'b0}};
     else
     if (cke)
       qi <= q_next;
 
   assign q = qi;
 
 
   always @ (posedge clk or posedge rst)
     if (rst)
       zq <= 1'b1;
     else
     if (cke)
       zq <= q_next == {length{1'b0}};
 
    always @ (posedge clk or posedge rst)
    if (rst)
        level1 <= 1'b0;
    else
    if (cke)
    if (clear)
        level1 <= 1'b0;
    else if (q_next == level1_value)
        level1 <= 1'b1;
    else if (qi == level1_value & rew)
        level1 <= 1'b0;
endmodule
`endif
`ifdef CNT_LFSR_ZQ
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// LFSR counter
 
`define MODULE cnt_lfsr_zq
module `BASE`MODULE (
`undef MODULE
 zq, rst, clk);
 
   parameter length = 4;
   output reg zq;
   input rst;
   input clk;
 
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter wrap_value = 8;
   parameter level1_value = 15;
 
   reg  [length:1] qi;
   reg lfsr_fb;
   wire [length:1] q_next;
   reg [32:1] polynom;
   integer i;
 
   always @ (qi)
   begin
        case (length)
         2: polynom = 32'b11;                               // 0x3
         3: polynom = 32'b110;                              // 0x6
         4: polynom = 32'b1100;                             // 0xC
         5: polynom = 32'b10100;                            // 0x14
         6: polynom = 32'b110000;                           // 0x30
         7: polynom = 32'b1100000;                          // 0x60
         8: polynom = 32'b10111000;                         // 0xb8
         9: polynom = 32'b100010000;                        // 0x110
        10: polynom = 32'b1001000000;                       // 0x240
        11: polynom = 32'b10100000000;                      // 0x500
        12: polynom = 32'b100000101001;                     // 0x829
        13: polynom = 32'b1000000001100;                    // 0x100C
        14: polynom = 32'b10000000010101;                   // 0x2015
        15: polynom = 32'b110000000000000;                  // 0x6000
        16: polynom = 32'b1101000000001000;                 // 0xD008
        17: polynom = 32'b10010000000000000;                // 0x12000
        18: polynom = 32'b100000010000000000;               // 0x20400
        19: polynom = 32'b1000000000000100011;              // 0x40023
        20: polynom = 32'b10010000000000000000;             // 0x90000
        21: polynom = 32'b101000000000000000000;            // 0x140000
        22: polynom = 32'b1100000000000000000000;           // 0x300000
        23: polynom = 32'b10000100000000000000000;          // 0x420000
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
        default: polynom = 32'b0;
        endcase
        lfsr_fb = qi[length];
        for (i=length-1; i>=1; i=i-1) begin
            if (polynom[i])
                lfsr_fb = lfsr_fb  ~^ qi[i];
        end
    end
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
 
   always @ (posedge clk or posedge rst)
     if (rst)
       qi <= {length{1'b0}};
     else
       qi <= q_next;
 
 
 
   always @ (posedge clk or posedge rst)
     if (rst)
       zq <= 1'b1;
     else
       zq <= q_next == {length{1'b0}};
endmodule
`endif
`ifdef CNT_LFSR_CE
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// LFSR counter
 
`define MODULE cnt_lfsr_ce
module `BASE`MODULE (
`undef MODULE
 cke, zq, rst, clk);
 
   parameter length = 4;
   input cke;
   output reg zq;
   input rst;
   input clk;
 
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter level1_value = 15;
 
   reg  [length:1] qi;
   reg lfsr_fb;
   wire [length:1] q_next;
   reg [32:1] polynom;
   integer i;
 
   always @ (qi)
   begin
        case (length)
         2: polynom = 32'b11;                               // 0x3
         3: polynom = 32'b110;                              // 0x6
         4: polynom = 32'b1100;                             // 0xC
         5: polynom = 32'b10100;                            // 0x14
         6: polynom = 32'b110000;                           // 0x30
         7: polynom = 32'b1100000;                          // 0x60
         8: polynom = 32'b10111000;                         // 0xb8
         9: polynom = 32'b100010000;                        // 0x110
        10: polynom = 32'b1001000000;                       // 0x240
        11: polynom = 32'b10100000000;                      // 0x500
        12: polynom = 32'b100000101001;                     // 0x829
        13: polynom = 32'b1000000001100;                    // 0x100C
        14: polynom = 32'b10000000010101;                   // 0x2015
        15: polynom = 32'b110000000000000;                  // 0x6000
        16: polynom = 32'b1101000000001000;                 // 0xD008
        17: polynom = 32'b10010000000000000;                // 0x12000
        18: polynom = 32'b100000010000000000;               // 0x20400
        19: polynom = 32'b1000000000000100011;              // 0x40023
        20: polynom = 32'b10010000000000000000;             // 0x90000
        21: polynom = 32'b101000000000000000000;            // 0x140000
        22: polynom = 32'b1100000000000000000000;           // 0x300000
        23: polynom = 32'b10000100000000000000000;          // 0x420000
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
        default: polynom = 32'b0;
        endcase
        lfsr_fb = qi[length];
        for (i=length-1; i>=1; i=i-1) begin
            if (polynom[i])
                lfsr_fb = lfsr_fb  ~^ qi[i];
        end
    end
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
 
   always @ (posedge clk or posedge rst)
     if (rst)
       qi <= {length{1'b0}};
     else
     if (cke)
       qi <= q_next;
 
 
 
   always @ (posedge clk or posedge rst)
     if (rst)
       zq <= 1'b1;
     else
     if (cke)
       zq <= q_next == {length{1'b0}};
endmodule
`endif
`ifdef CNT_LFSR_CE_ZQ
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// LFSR counter
 
`define MODULE cnt_lfsr_ce_zq
module `BASE`MODULE (
`undef MODULE
 cke, zq, rst, clk);
 
   parameter length = 4;
   input cke;
   output reg zq;
   input rst;
   input clk;
 
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter wrap_value = 8;
   parameter level1_value = 15;
 
   reg  [length:1] qi;
   reg lfsr_fb;
   wire [length:1] q_next;
   reg [32:1] polynom;
   integer i;
 
   always @ (qi)
   begin
        case (length)
         2: polynom = 32'b11;                               // 0x3
         3: polynom = 32'b110;                              // 0x6
         4: polynom = 32'b1100;                             // 0xC
         5: polynom = 32'b10100;                            // 0x14
         6: polynom = 32'b110000;                           // 0x30
         7: polynom = 32'b1100000;                          // 0x60
         8: polynom = 32'b10111000;                         // 0xb8
         9: polynom = 32'b100010000;                        // 0x110
        10: polynom = 32'b1001000000;                       // 0x240
        11: polynom = 32'b10100000000;                      // 0x500
        12: polynom = 32'b100000101001;                     // 0x829
        13: polynom = 32'b1000000001100;                    // 0x100C
        14: polynom = 32'b10000000010101;                   // 0x2015
        15: polynom = 32'b110000000000000;                  // 0x6000
        16: polynom = 32'b1101000000001000;                 // 0xD008
        17: polynom = 32'b10010000000000000;                // 0x12000
        18: polynom = 32'b100000010000000000;               // 0x20400
        19: polynom = 32'b1000000000000100011;              // 0x40023
        20: polynom = 32'b10010000000000000000;             // 0x90000
        21: polynom = 32'b101000000000000000000;            // 0x140000
        22: polynom = 32'b1100000000000000000000;           // 0x300000
        23: polynom = 32'b10000100000000000000000;          // 0x420000
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
        default: polynom = 32'b0;
        endcase
        lfsr_fb = qi[length];
        for (i=length-1; i>=1; i=i-1) begin
            if (polynom[i])
                lfsr_fb = lfsr_fb  ~^ qi[i];
        end
    end
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
 
   always @ (posedge clk or posedge rst)
     if (rst)
       qi <= {length{1'b0}};
     else
     if (cke)
       qi <= q_next;
 
 
 
   always @ (posedge clk or posedge rst)
     if (rst)
       zq <= 1'b1;
     else
     if (cke)
       zq <= q_next == {length{1'b0}};
endmodule
`endif
`ifdef CNT_LFSR_CE_Q
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile counter                                           ////
////                                                              ////


Line No.	Rev	Author	Line
1	40	unneback	`ifndef BASE
2			`define BASE vl_
3			`endif
4
5	60	unneback	`// default SYN_KEEP definition`
6			`define SYN_KEEP /synthesis syn_keep = 1/
7
8	44	unneback	`ifdef ACTEL
9	60	unneback	`undef SYN_KEEP
10	44	unneback	`define SYN_KEEP /synthesis syn_keep = 1/
11			`endif
12
13	98	unneback	`ifdef ACTEL
14			`// ACTEL FPGA should not use logic to handle rw collision`
15			`define SYN_NO_RW_CHECK /synthesis syn_ramstyle = "no_rw_check"/
16			`else
17			`define SYN_NO_RW_CHECK
18			`endif
19
20	40	unneback	`ifdef ALL
21
22			`define GBUF
23			`define SYNC_RST
24			`define PLL
25
26			`define MULTS
27			`define MULTS18X18
28			`define MULT
29			`define SHIFT_UNIT_32
30			`define LOGIC_UNIT
31
32			`define CNT_SHREG_WRAP
33			`define CNT_SHREG_CE_WRAP
34	105	unneback	`define CNT_SHREG_CLEAR
35	40	unneback	`define CNT_SHREG_CE_CLEAR
36			`define CNT_SHREG_CE_CLEAR_WRAP
37
38			`define MUX_ANDOR
39			`define MUX2_ANDOR
40			`define MUX3_ANDOR
41			`define MUX4_ANDOR
42			`define MUX5_ANDOR
43			`define MUX6_ANDOR
44	43	unneback	`define PARITY
45	40	unneback
46			`define ROM_INIT
47			`define RAM
48			`define RAM_BE
49			`define DPRAM_1R1W
50			`define DPRAM_2R1W
51	100	unneback	`define DPRAM_1R2W
52	40	unneback	`define DPRAM_2R2W
53	75	unneback	`define DPRAM_BE_2R2W
54	40	unneback	`define FIFO_1R1W_FILL_LEVEL_SYNC
55			`define FIFO_2R2W_SYNC_SIMPLEX
56			`define FIFO_CMP_ASYNC
57			`define FIFO_1R1W_ASYNC
58			`define FIFO_2R2W_ASYNC
59			`define FIFO_2R2W_ASYNC_SIMPLEX
60	48	unneback	`define REG_FILE
61	40	unneback
62			`define DFF
63			`define DFF_ARRAY
64			`define DFF_CE
65			`define DFF_CE_CLEAR
66			`define DF_CE_SET
67			`define SPR
68			`define SRP
69			`define DFF_SR
70			`define LATCH
71			`define SHREG
72			`define SHREG_CE
73			`define DELAY
74			`define DELAY_EMPTYFLAG
75	94	unneback	`define PULSE2TOGGLE
76			`define TOGGLE2PULSE
77			`define SYNCHRONIZER
78			`define CDC
79	40	unneback
80	75	unneback	`define WB3AVALON_BRIDGE
81	40	unneback	`define WB3WB3_BRIDGE
82			`define WB3_ARBITER_TYPE1
83	83	unneback	`define WB_ADR_INC
84	101	unneback	`define WB_RAM
85	103	unneback	`define WB_SHADOW_RAM
86	48	unneback	`define WB_B4_ROM
87	40	unneback	`define WB_BOOT_ROM
88			`define WB_DPRAM
89	101	unneback	`define WB_CACHE
90	103	unneback	`define WB_AVALON_BRIDGE
91			`define WB_AVALON_MEM_CACHE
92	40	unneback
93	44	unneback	`define IO_DFF_OE
94			`define O_DFF
95
96	40	unneback	`endif
97
98			`ifdef PLL
99			`ifndef SYNC_RST
100			`define SYNC_RST
101			`endif
102			`endif
103
104			`ifdef SYNC_RST
105			`ifndef GBUF
106			`define GBUF
107			`endif
108			`endif
109
110	108	unneback	`ifdef WB_DPRAM
111	92	unneback	`ifndef WB_ADR_INC
112			`define WB_ADR_INC
113	40	unneback	`endif
114	92	unneback	`ifndef DPRAM_BE_2R2W
115			`define DPRAM_BE_2R2W
116	40	unneback	`endif
117			`endif
118
119	101	unneback	`ifdef WB_RAM
120	83	unneback	`ifndef WB_ADR_INC
121			`define WB_ADR_INC
122	62	unneback	`endif
123			`ifndef RAM_BE
124			`define RAM_BE
125			`endif
126			`endif
127
128	40	unneback	`ifdef WB3_ARBITER_TYPE1
129	42	unneback	`ifndef SPR
130			`define SPR
131			`endif
132	40	unneback	`ifndef MUX_ANDOR
133			`define MUX_ANDOR
134			`endif
135			`endif
136
137	76	unneback	`ifdef WB3AVALON_BRIDGE
138			`ifndef WB3WB3_BRIDGE
139			`define WB3WB3_BRIDGE
140			`endif
141			`endif
142
143	40	unneback	`ifdef WB3WB3_BRIDGE
144			`ifndef CNT_SHREG_CE_CLEAR
145			`define CNT_SHREG_CE_CLEAR
146			`endif
147			`ifndef DFF
148			`define DFF
149			`endif
150			`ifndef DFF_CE
151			`define DFF_CE
152			`endif
153			`ifndef CNT_SHREG_CE_CLEAR
154			`define CNT_SHREG_CE_CLEAR
155			`endif
156			`ifndef FIFO_2R2W_ASYNC_SIMPLEX
157			`define FIFO_2R2W_ASYNC_SIMPLEX
158			`endif
159			`endif
160
161	103	unneback
162			`ifdef WB_AVALON_MEM_CACHE
163			`ifndef WB_SHADOW_RAM
164			`define WB_SHADOW_RAM
165			`endif
166			`ifndef WB_CACHE
167			`define WB_CACHE
168			`endif
169			`ifndef WB_AVALON_BRIDGE
170			`define WB_AVALON_BRIDGE
171			`endif
172			`endif
173
174	101	unneback	`ifdef WB_CACHE
175	100	unneback	`ifndef RAM
176			`define RAM
177			`endif
178			`ifndef WB_ADR_INC
179			`define WB_ADR_INC
180			`endif
181			`ifndef DPRAM_1R1W
182			`define DPRAM_1R1W
183			`endif
184			`ifndef DPRAM_1R2W
185			`define DPRAM_1R2W
186			`endif
187			`ifndef DPRAM_BE_2R2W
188			`define DPRAM_BE_2R2W
189			`endif
190			`ifndef CDC
191			`define CDC
192			`endif
193			`endif
194	103	unneback
195			`ifdef WB_SHADOW_RAM
196			`ifndef WB_RAM
197			`define WB_RAM
198			`endif
199			`endif
200
201			`ifdef WB_RAM
202			`ifndef WB_ADR_INC
203			`define WB_ADR_INC
204			`endif
205			`endif
206	97	unneback
207	40	unneback	`ifdef MULTS18X18
208			`ifndef MULTS
209			`define MULTS
210			`endif
211			`endif
212
213			`ifdef SHIFT_UNIT_32
214			`ifndef MULTS
215			`define MULTS
216			`endif
217			`endif
218
219			`ifdef MUX2_ANDOR
220			`ifndef MUX_ANDOR
221			`define MUX_ANDOR
222			`endif
223			`endif
224
225			`ifdef MUX3_ANDOR
226			`ifndef MUX_ANDOR
227			`define MUX_ANDOR
228			`endif
229			`endif
230
231			`ifdef MUX4_ANDOR
232			`ifndef MUX_ANDOR
233			`define MUX_ANDOR
234			`endif
235			`endif
236
237			`ifdef MUX5_ANDOR
238			`ifndef MUX_ANDOR
239			`define MUX_ANDOR
240			`endif
241			`endif
242
243			`ifdef MUX6_ANDOR
244			`ifndef MUX_ANDOR
245			`define MUX_ANDOR
246			`endif
247			`endif
248
249			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
250			`ifndef CNT_BIN_CE
251			`define CNT_BIN_CE
252			`endif
253			`ifndef DPRAM_1R1W
254			`define DPRAM_1R1W
255			`endif
256			`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
257			`define CNT_BIN_CE_REW_Q_ZQ_L1
258			`endif
259			`endif
260
261			`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
262			`ifndef CNT_LFSR_CE
263			`define CNT_LFSR_CE
264			`endif
265			`ifndef DPRAM_2R2W
266			`define DPRAM_2R2W
267			`endif
268			`ifndef CNT_BIN_CE_REW_ZQ_L1
269			`define CNT_BIN_CE_REW_ZQ_L1
270			`endif
271			`endif
272
273			`ifdef FIFO_2R2W_ASYNC_SIMPLEX
274			`ifndef CNT_GRAY_CE_BIN
275			`define CNT_GRAY_CE_BIN
276			`endif
277			`ifndef DPRAM_2R2W
278			`define DPRAM_2R2W
279			`endif
280			`ifndef FIFO_CMP_ASYNC
281			`define FIFO_CMP_ASYNC
282			`endif
283			`endif
284
285			`ifdef FIFO_2R2W_ASYNC
286			`ifndef FIFO_1R1W_ASYNC
287			`define FIFO_1R1W_ASYNC
288			`endif
289			`endif
290
291			`ifdef FIFO_1R1W_ASYNC
292			`ifndef CNT_GRAY_CE_BIN
293			`define CNT_GRAY_CE_BIN
294			`endif
295			`ifndef DPRAM_1R1W
296			`define DPRAM_1R1W
297			`endif
298			`ifndef FIFO_CMP_ASYNC
299			`define FIFO_CMP_ASYNC
300			`endif
301			`endif
302
303			`ifdef FIFO_CMP_ASYNC
304			`ifndef DFF_SR
305			`define DFF_SR
306			`endif
307			`ifndef DFF
308			`define DFF
309			`endif
310			`endif
311	48	unneback
312			`ifdef REG_FILE
313			`ifndef DPRAM_1R1W
314			`define DPRAM_1R1W
315			`endif
316			`endif
317	97	unneback
318	98	unneback	`ifdef CDC
319			`ifndef PULSE2TOGGLE
320			`define PULSE2TOGGLE
321			`endif
322			`ifndef TOGGLE2PULSE
323			`define TOGGLE2PULSE
324			`endif
325			`ifndef SYNCHRONIZER
326			`define SYNCHRONIZER
327			`endif
328			`endif
329
330	97	unneback	`// size to width`
331	100	unneback	`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
332	62	unneback	`//////////////////////////////////////////////////////////////////////`
333	6	unneback	`//// ////`
334			`//// Versatile library, clock and reset ////`
335			`//// ////`
336			`//// Description ////`
337			`//// Logic related to clock and reset ////`
338			`//// ////`
339			`//// ////`
340			`//// To Do: ////`
341			`//// - add more different registers ////`
342			`//// ////`
343			`//// Author(s): ////`
344			`//// - Michael Unneback, unneback@opencores.org ////`
345			`//// ORSoC AB ////`
346			`//// ////`
347			`//////////////////////////////////////////////////////////////////////`
348			`//// ////`
349			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
350			`//// ////`
351			`//// This source file may be used and distributed without ////`
352			`//// restriction provided that this copyright statement is not ////`
353			`//// removed from the file and that any derivative work contains ////`
354			`//// the original copyright notice and the associated disclaimer. ////`
355			`//// ////`
356			`//// This source file is free software; you can redistribute it ////`
357			`//// and/or modify it under the terms of the GNU Lesser General ////`
358			`//// Public License as published by the Free Software Foundation; ////`
359			`//// either version 2.1 of the License, or (at your option) any ////`
360			`//// later version. ////`
361			`//// ////`
362			`//// This source is distributed in the hope that it will be ////`
363			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
364			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
365			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
366			`//// details. ////`
367			`//// ////`
368			`//// You should have received a copy of the GNU Lesser General ////`
369			`//// Public License along with this source; if not, download it ////`
370			`//// from http://www.opencores.org/lgpl.shtml ////`
371			`//// ////`
372			`//////////////////////////////////////////////////////////////////////`
373
374	48	unneback	`ifdef ACTEL
375			`ifdef GBUF
376			`timescale 1 ns/100 ps
377	6	unneback	`// Global buffer`
378			`// usage:`
379			`// use to enable global buffers for high fan out signals such as clock and reset`
380			`// Version: 8.4 8.4.0.33`
381			`module gbuf(GL,CLK);`
382			`output GL;`
383			`input CLK;`
384
385			`wire GND;`
386
387			`GND GND_1_net(.Y(GND));`
388			`CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),`
389			`.DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;`
390
391			`endmodule`
392			`timescale 1 ns/1 ns
393	40	unneback	`define MODULE gbuf
394			module `BASE`MODULE ( i, o);
395			`undef MODULE
396	6	unneback	`input i;`
397			`output o;`
398			`ifdef SIM_GBUF
399			`assign o=i;`
400			`else
401			`gbuf gbuf_i0 ( .CLK(i), .GL(o));`
402			`endif
403			`endmodule`
404	40	unneback	`endif
405	33	unneback
406	6	unneback	`else
407	33	unneback
408	40	unneback	`ifdef ALTERA
409			`ifdef GBUF
410	21	unneback	`//altera`
411	40	unneback	`define MODULE gbuf
412			module `BASE`MODULE ( i, o);
413			`undef MODULE
414	33	unneback	`input i;`
415			`output o;`
416			`assign o = i;`
417			`endmodule`
418	40	unneback	`endif
419	33	unneback
420	6	unneback	`else
421
422	40	unneback	`ifdef GBUF
423	6	unneback	`timescale 1 ns/100 ps
424	40	unneback	`define MODULE
425			module `BASE`MODULE ( i, o);
426			`undef MODULE
427	6	unneback	`input i;`
428			`output o;`
429			`assign o = i;`
430			`endmodule`
431	40	unneback	`endif
432	6	unneback	`endif // ALTERA
433			`endif //ACTEL
434
435	40	unneback	`ifdef SYNC_RST
436	6	unneback	`// sync reset`
437	17	unneback	`// input active lo async reset, normally from external reset generator and/or switch`
438	6	unneback	`// output active high global reset sync with two DFFs`
439			`timescale 1 ns/100 ps
440	40	unneback	`define MODULE sync_rst
441			module `BASE`MODULE ( rst_n_i, rst_o, clk);
442			`undef MODULE
443	6	unneback	`input rst_n_i, clk;`
444			`output rst_o;`
445	18	unneback	`reg [1:0] tmp;`
446	6	unneback	`always @ (posedge clk or negedge rst_n_i)`
447			`if (!rst_n_i)`
448	17	unneback	`tmp <= 2'b11;`
449	6	unneback	`else`
450	33	unneback	`tmp <= {1'b0,tmp[1]};`
451	40	unneback	`define MODULE gbuf
452			`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
453			`undef MODULE
454	6	unneback	`endmodule`
455	40	unneback	`endif
456	6	unneback
457	40	unneback	`ifdef PLL
458	6	unneback	`// vl_pll`
459			`ifdef ACTEL
460	32	unneback	`///////////////////////////////////////////////////////////////////////////////`
461	17	unneback	`timescale 1 ps/1 ps
462	40	unneback	`define MODULE pll
463			module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
464			`undef MODULE
465	6	unneback	`parameter index = 0;`
466			`parameter number_of_clk = 1;`
467	17	unneback	`parameter period_time_0 = 20000;`
468			`parameter period_time_1 = 20000;`
469			`parameter period_time_2 = 20000;`
470			`parameter lock_delay = 2000000;`
471	6	unneback	`input clk_i, rst_n_i;`
472			`output lock;`
473			`output reg [0:number_of_clk-1] clk_o;`
474			`output [0:number_of_clk-1] rst_o;`
475
476			`ifdef SIM_PLL
477
478			`always`
479			`#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];`
480
481			`generate if (number_of_clk > 1)`
482			`always`
483			`#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];`
484			`endgenerate`
485
486			`generate if (number_of_clk > 2)`
487			`always`
488			`#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];`
489			`endgenerate`
490
491			`genvar i;`
492			`generate for (i=0;i<number_of_clk;i=i+1) begin: clock`
493			`vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i \| lock), .rst_o(rst_o[i]), .clk(clk_o[i]));`
494			`end`
495			`endgenerate`
496
497			`assign #lock_delay lock = rst_n_i;`
498
499			`endmodule`
500			`else

Browse

Tools

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 111