| 1 |
40 |
unneback |
`ifndef BASE
|
| 2 |
|
|
`define BASE vl_
|
| 3 |
|
|
`endif
|
| 4 |
|
|
|
| 5 |
60 |
unneback |
// default SYN_KEEP definition
|
| 6 |
|
|
`define SYN_KEEP /*synthesis syn_keep = 1*/
|
| 7 |
|
|
|
| 8 |
44 |
unneback |
`ifdef ACTEL
|
| 9 |
60 |
unneback |
`undef SYN_KEEP
|
| 10 |
44 |
unneback |
`define SYN_KEEP /*synthesis syn_keep = 1*/
|
| 11 |
|
|
`endif
|
| 12 |
|
|
|
| 13 |
98 |
unneback |
`ifdef ACTEL
|
| 14 |
|
|
// ACTEL FPGA should not use logic to handle rw collision
|
| 15 |
|
|
`define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
|
| 16 |
|
|
`else
|
| 17 |
|
|
`define SYN_NO_RW_CHECK
|
| 18 |
|
|
`endif
|
| 19 |
|
|
|
| 20 |
40 |
unneback |
`ifdef ALL
|
| 21 |
|
|
|
| 22 |
|
|
`define GBUF
|
| 23 |
|
|
`define SYNC_RST
|
| 24 |
|
|
`define PLL
|
| 25 |
|
|
|
| 26 |
|
|
`define MULTS
|
| 27 |
|
|
`define MULTS18X18
|
| 28 |
|
|
`define MULT
|
| 29 |
|
|
`define SHIFT_UNIT_32
|
| 30 |
|
|
`define LOGIC_UNIT
|
| 31 |
|
|
|
| 32 |
|
|
`define CNT_SHREG_WRAP
|
| 33 |
|
|
`define CNT_SHREG_CE_WRAP
|
| 34 |
105 |
unneback |
`define CNT_SHREG_CLEAR
|
| 35 |
40 |
unneback |
`define CNT_SHREG_CE_CLEAR
|
| 36 |
|
|
`define CNT_SHREG_CE_CLEAR_WRAP
|
| 37 |
|
|
|
| 38 |
|
|
`define MUX_ANDOR
|
| 39 |
|
|
`define MUX2_ANDOR
|
| 40 |
|
|
`define MUX3_ANDOR
|
| 41 |
|
|
`define MUX4_ANDOR
|
| 42 |
|
|
`define MUX5_ANDOR
|
| 43 |
|
|
`define MUX6_ANDOR
|
| 44 |
43 |
unneback |
`define PARITY
|
| 45 |
40 |
unneback |
|
| 46 |
|
|
`define ROM_INIT
|
| 47 |
|
|
`define RAM
|
| 48 |
|
|
`define RAM_BE
|
| 49 |
|
|
`define DPRAM_1R1W
|
| 50 |
|
|
`define DPRAM_2R1W
|
| 51 |
100 |
unneback |
`define DPRAM_1R2W
|
| 52 |
40 |
unneback |
`define DPRAM_2R2W
|
| 53 |
75 |
unneback |
`define DPRAM_BE_2R2W
|
| 54 |
40 |
unneback |
`define FIFO_1R1W_FILL_LEVEL_SYNC
|
| 55 |
|
|
`define FIFO_2R2W_SYNC_SIMPLEX
|
| 56 |
|
|
`define FIFO_CMP_ASYNC
|
| 57 |
|
|
`define FIFO_1R1W_ASYNC
|
| 58 |
|
|
`define FIFO_2R2W_ASYNC
|
| 59 |
|
|
`define FIFO_2R2W_ASYNC_SIMPLEX
|
| 60 |
48 |
unneback |
`define REG_FILE
|
| 61 |
40 |
unneback |
|
| 62 |
|
|
`define DFF
|
| 63 |
|
|
`define DFF_ARRAY
|
| 64 |
|
|
`define DFF_CE
|
| 65 |
|
|
`define DFF_CE_CLEAR
|
| 66 |
|
|
`define DF_CE_SET
|
| 67 |
|
|
`define SPR
|
| 68 |
|
|
`define SRP
|
| 69 |
|
|
`define DFF_SR
|
| 70 |
|
|
`define LATCH
|
| 71 |
|
|
`define SHREG
|
| 72 |
|
|
`define SHREG_CE
|
| 73 |
|
|
`define DELAY
|
| 74 |
|
|
`define DELAY_EMPTYFLAG
|
| 75 |
94 |
unneback |
`define PULSE2TOGGLE
|
| 76 |
|
|
`define TOGGLE2PULSE
|
| 77 |
|
|
`define SYNCHRONIZER
|
| 78 |
|
|
`define CDC
|
| 79 |
40 |
unneback |
|
| 80 |
75 |
unneback |
`define WB3AVALON_BRIDGE
|
| 81 |
40 |
unneback |
`define WB3WB3_BRIDGE
|
| 82 |
|
|
`define WB3_ARBITER_TYPE1
|
| 83 |
83 |
unneback |
`define WB_ADR_INC
|
| 84 |
101 |
unneback |
`define WB_RAM
|
| 85 |
103 |
unneback |
`define WB_SHADOW_RAM
|
| 86 |
48 |
unneback |
`define WB_B4_ROM
|
| 87 |
40 |
unneback |
`define WB_BOOT_ROM
|
| 88 |
|
|
`define WB_DPRAM
|
| 89 |
101 |
unneback |
`define WB_CACHE
|
| 90 |
103 |
unneback |
`define WB_AVALON_BRIDGE
|
| 91 |
|
|
`define WB_AVALON_MEM_CACHE
|
| 92 |
40 |
unneback |
|
| 93 |
44 |
unneback |
`define IO_DFF_OE
|
| 94 |
|
|
`define O_DFF
|
| 95 |
|
|
|
| 96 |
40 |
unneback |
`endif
|
| 97 |
|
|
|
| 98 |
|
|
`ifdef PLL
|
| 99 |
|
|
`ifndef SYNC_RST
|
| 100 |
|
|
`define SYNC_RST
|
| 101 |
|
|
`endif
|
| 102 |
|
|
`endif
|
| 103 |
|
|
|
| 104 |
|
|
`ifdef SYNC_RST
|
| 105 |
|
|
`ifndef GBUF
|
| 106 |
|
|
`define GBUF
|
| 107 |
|
|
`endif
|
| 108 |
|
|
`endif
|
| 109 |
|
|
|
| 110 |
108 |
unneback |
`ifdef WB_DPRAM
|
| 111 |
92 |
unneback |
`ifndef WB_ADR_INC
|
| 112 |
|
|
`define WB_ADR_INC
|
| 113 |
40 |
unneback |
`endif
|
| 114 |
92 |
unneback |
`ifndef DPRAM_BE_2R2W
|
| 115 |
|
|
`define DPRAM_BE_2R2W
|
| 116 |
40 |
unneback |
`endif
|
| 117 |
|
|
`endif
|
| 118 |
|
|
|
| 119 |
101 |
unneback |
`ifdef WB_RAM
|
| 120 |
83 |
unneback |
`ifndef WB_ADR_INC
|
| 121 |
|
|
`define WB_ADR_INC
|
| 122 |
62 |
unneback |
`endif
|
| 123 |
|
|
`ifndef RAM_BE
|
| 124 |
|
|
`define RAM_BE
|
| 125 |
|
|
`endif
|
| 126 |
|
|
`endif
|
| 127 |
|
|
|
| 128 |
40 |
unneback |
`ifdef WB3_ARBITER_TYPE1
|
| 129 |
42 |
unneback |
`ifndef SPR
|
| 130 |
|
|
`define SPR
|
| 131 |
|
|
`endif
|
| 132 |
40 |
unneback |
`ifndef MUX_ANDOR
|
| 133 |
|
|
`define MUX_ANDOR
|
| 134 |
|
|
`endif
|
| 135 |
|
|
`endif
|
| 136 |
|
|
|
| 137 |
76 |
unneback |
`ifdef WB3AVALON_BRIDGE
|
| 138 |
|
|
`ifndef WB3WB3_BRIDGE
|
| 139 |
|
|
`define WB3WB3_BRIDGE
|
| 140 |
|
|
`endif
|
| 141 |
|
|
`endif
|
| 142 |
|
|
|
| 143 |
40 |
unneback |
`ifdef WB3WB3_BRIDGE
|
| 144 |
|
|
`ifndef CNT_SHREG_CE_CLEAR
|
| 145 |
|
|
`define CNT_SHREG_CE_CLEAR
|
| 146 |
|
|
`endif
|
| 147 |
|
|
`ifndef DFF
|
| 148 |
|
|
`define DFF
|
| 149 |
|
|
`endif
|
| 150 |
|
|
`ifndef DFF_CE
|
| 151 |
|
|
`define DFF_CE
|
| 152 |
|
|
`endif
|
| 153 |
|
|
`ifndef CNT_SHREG_CE_CLEAR
|
| 154 |
|
|
`define CNT_SHREG_CE_CLEAR
|
| 155 |
|
|
`endif
|
| 156 |
|
|
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
|
| 157 |
|
|
`define FIFO_2R2W_ASYNC_SIMPLEX
|
| 158 |
|
|
`endif
|
| 159 |
|
|
`endif
|
| 160 |
|
|
|
| 161 |
103 |
unneback |
|
| 162 |
|
|
`ifdef WB_AVALON_MEM_CACHE
|
| 163 |
|
|
`ifndef WB_SHADOW_RAM
|
| 164 |
|
|
`define WB_SHADOW_RAM
|
| 165 |
|
|
`endif
|
| 166 |
|
|
`ifndef WB_CACHE
|
| 167 |
|
|
`define WB_CACHE
|
| 168 |
|
|
`endif
|
| 169 |
|
|
`ifndef WB_AVALON_BRIDGE
|
| 170 |
|
|
`define WB_AVALON_BRIDGE
|
| 171 |
|
|
`endif
|
| 172 |
|
|
`endif
|
| 173 |
|
|
|
| 174 |
101 |
unneback |
`ifdef WB_CACHE
|
| 175 |
100 |
unneback |
`ifndef RAM
|
| 176 |
|
|
`define RAM
|
| 177 |
|
|
`endif
|
| 178 |
|
|
`ifndef WB_ADR_INC
|
| 179 |
|
|
`define WB_ADR_INC
|
| 180 |
|
|
`endif
|
| 181 |
|
|
`ifndef DPRAM_1R1W
|
| 182 |
|
|
`define DPRAM_1R1W
|
| 183 |
|
|
`endif
|
| 184 |
|
|
`ifndef DPRAM_1R2W
|
| 185 |
|
|
`define DPRAM_1R2W
|
| 186 |
|
|
`endif
|
| 187 |
|
|
`ifndef DPRAM_BE_2R2W
|
| 188 |
|
|
`define DPRAM_BE_2R2W
|
| 189 |
|
|
`endif
|
| 190 |
|
|
`ifndef CDC
|
| 191 |
|
|
`define CDC
|
| 192 |
|
|
`endif
|
| 193 |
|
|
`endif
|
| 194 |
103 |
unneback |
|
| 195 |
|
|
`ifdef WB_SHADOW_RAM
|
| 196 |
|
|
`ifndef WB_RAM
|
| 197 |
|
|
`define WB_RAM
|
| 198 |
|
|
`endif
|
| 199 |
|
|
`endif
|
| 200 |
|
|
|
| 201 |
|
|
`ifdef WB_RAM
|
| 202 |
|
|
`ifndef WB_ADR_INC
|
| 203 |
|
|
`define WB_ADR_INC
|
| 204 |
|
|
`endif
|
| 205 |
|
|
`endif
|
| 206 |
97 |
unneback |
|
| 207 |
40 |
unneback |
`ifdef MULTS18X18
|
| 208 |
|
|
`ifndef MULTS
|
| 209 |
|
|
`define MULTS
|
| 210 |
|
|
`endif
|
| 211 |
|
|
`endif
|
| 212 |
|
|
|
| 213 |
|
|
`ifdef SHIFT_UNIT_32
|
| 214 |
|
|
`ifndef MULTS
|
| 215 |
|
|
`define MULTS
|
| 216 |
|
|
`endif
|
| 217 |
|
|
`endif
|
| 218 |
|
|
|
| 219 |
|
|
`ifdef MUX2_ANDOR
|
| 220 |
|
|
`ifndef MUX_ANDOR
|
| 221 |
|
|
`define MUX_ANDOR
|
| 222 |
|
|
`endif
|
| 223 |
|
|
`endif
|
| 224 |
|
|
|
| 225 |
|
|
`ifdef MUX3_ANDOR
|
| 226 |
|
|
`ifndef MUX_ANDOR
|
| 227 |
|
|
`define MUX_ANDOR
|
| 228 |
|
|
`endif
|
| 229 |
|
|
`endif
|
| 230 |
|
|
|
| 231 |
|
|
`ifdef MUX4_ANDOR
|
| 232 |
|
|
`ifndef MUX_ANDOR
|
| 233 |
|
|
`define MUX_ANDOR
|
| 234 |
|
|
`endif
|
| 235 |
|
|
`endif
|
| 236 |
|
|
|
| 237 |
|
|
`ifdef MUX5_ANDOR
|
| 238 |
|
|
`ifndef MUX_ANDOR
|
| 239 |
|
|
`define MUX_ANDOR
|
| 240 |
|
|
`endif
|
| 241 |
|
|
`endif
|
| 242 |
|
|
|
| 243 |
|
|
`ifdef MUX6_ANDOR
|
| 244 |
|
|
`ifndef MUX_ANDOR
|
| 245 |
|
|
`define MUX_ANDOR
|
| 246 |
|
|
`endif
|
| 247 |
|
|
`endif
|
| 248 |
|
|
|
| 249 |
|
|
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
|
| 250 |
|
|
`ifndef CNT_BIN_CE
|
| 251 |
|
|
`define CNT_BIN_CE
|
| 252 |
|
|
`endif
|
| 253 |
|
|
`ifndef DPRAM_1R1W
|
| 254 |
|
|
`define DPRAM_1R1W
|
| 255 |
|
|
`endif
|
| 256 |
|
|
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
|
| 257 |
|
|
`define CNT_BIN_CE_REW_Q_ZQ_L1
|
| 258 |
|
|
`endif
|
| 259 |
|
|
`endif
|
| 260 |
|
|
|
| 261 |
|
|
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
|
| 262 |
|
|
`ifndef CNT_LFSR_CE
|
| 263 |
|
|
`define CNT_LFSR_CE
|
| 264 |
|
|
`endif
|
| 265 |
|
|
`ifndef DPRAM_2R2W
|
| 266 |
|
|
`define DPRAM_2R2W
|
| 267 |
|
|
`endif
|
| 268 |
|
|
`ifndef CNT_BIN_CE_REW_ZQ_L1
|
| 269 |
|
|
`define CNT_BIN_CE_REW_ZQ_L1
|
| 270 |
|
|
`endif
|
| 271 |
|
|
`endif
|
| 272 |
|
|
|
| 273 |
|
|
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
|
| 274 |
|
|
`ifndef CNT_GRAY_CE_BIN
|
| 275 |
|
|
`define CNT_GRAY_CE_BIN
|
| 276 |
|
|
`endif
|
| 277 |
|
|
`ifndef DPRAM_2R2W
|
| 278 |
|
|
`define DPRAM_2R2W
|
| 279 |
|
|
`endif
|
| 280 |
|
|
`ifndef FIFO_CMP_ASYNC
|
| 281 |
|
|
`define FIFO_CMP_ASYNC
|
| 282 |
|
|
`endif
|
| 283 |
|
|
`endif
|
| 284 |
|
|
|
| 285 |
|
|
`ifdef FIFO_2R2W_ASYNC
|
| 286 |
|
|
`ifndef FIFO_1R1W_ASYNC
|
| 287 |
|
|
`define FIFO_1R1W_ASYNC
|
| 288 |
|
|
`endif
|
| 289 |
|
|
`endif
|
| 290 |
|
|
|
| 291 |
|
|
`ifdef FIFO_1R1W_ASYNC
|
| 292 |
|
|
`ifndef CNT_GRAY_CE_BIN
|
| 293 |
|
|
`define CNT_GRAY_CE_BIN
|
| 294 |
|
|
`endif
|
| 295 |
|
|
`ifndef DPRAM_1R1W
|
| 296 |
|
|
`define DPRAM_1R1W
|
| 297 |
|
|
`endif
|
| 298 |
|
|
`ifndef FIFO_CMP_ASYNC
|
| 299 |
|
|
`define FIFO_CMP_ASYNC
|
| 300 |
|
|
`endif
|
| 301 |
|
|
`endif
|
| 302 |
|
|
|
| 303 |
|
|
`ifdef FIFO_CMP_ASYNC
|
| 304 |
|
|
`ifndef DFF_SR
|
| 305 |
|
|
`define DFF_SR
|
| 306 |
|
|
`endif
|
| 307 |
|
|
`ifndef DFF
|
| 308 |
|
|
`define DFF
|
| 309 |
|
|
`endif
|
| 310 |
|
|
`endif
|
| 311 |
48 |
unneback |
|
| 312 |
|
|
`ifdef REG_FILE
|
| 313 |
|
|
`ifndef DPRAM_1R1W
|
| 314 |
|
|
`define DPRAM_1R1W
|
| 315 |
|
|
`endif
|
| 316 |
|
|
`endif
|
| 317 |
97 |
unneback |
|
| 318 |
98 |
unneback |
`ifdef CDC
|
| 319 |
|
|
`ifndef PULSE2TOGGLE
|
| 320 |
|
|
`define PULSE2TOGGLE
|
| 321 |
|
|
`endif
|
| 322 |
|
|
`ifndef TOGGLE2PULSE
|
| 323 |
|
|
`define TOGGLE2PULSE
|
| 324 |
|
|
`endif
|
| 325 |
|
|
`ifndef SYNCHRONIZER
|
| 326 |
|
|
`define SYNCHRONIZER
|
| 327 |
|
|
`endif
|
| 328 |
|
|
`endif
|
| 329 |
|
|
|
| 330 |
97 |
unneback |
// size to width
|
| 331 |
100 |
unneback |
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
|
| 332 |
62 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 333 |
6 |
unneback |
//// ////
|
| 334 |
|
|
//// Versatile library, clock and reset ////
|
| 335 |
|
|
//// ////
|
| 336 |
|
|
//// Description ////
|
| 337 |
|
|
//// Logic related to clock and reset ////
|
| 338 |
|
|
//// ////
|
| 339 |
|
|
//// ////
|
| 340 |
|
|
//// To Do: ////
|
| 341 |
|
|
//// - add more different registers ////
|
| 342 |
|
|
//// ////
|
| 343 |
|
|
//// Author(s): ////
|
| 344 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 345 |
|
|
//// ORSoC AB ////
|
| 346 |
|
|
//// ////
|
| 347 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 348 |
|
|
//// ////
|
| 349 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
| 350 |
|
|
//// ////
|
| 351 |
|
|
//// This source file may be used and distributed without ////
|
| 352 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 353 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 354 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 355 |
|
|
//// ////
|
| 356 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 357 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 358 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 359 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 360 |
|
|
//// later version. ////
|
| 361 |
|
|
//// ////
|
| 362 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 363 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 364 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 365 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 366 |
|
|
//// details. ////
|
| 367 |
|
|
//// ////
|
| 368 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 369 |
|
|
//// Public License along with this source; if not, download it ////
|
| 370 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 371 |
|
|
//// ////
|
| 372 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 373 |
|
|
|
| 374 |
48 |
unneback |
`ifdef ACTEL
|
| 375 |
|
|
`ifdef GBUF
|
| 376 |
|
|
`timescale 1 ns/100 ps
|
| 377 |
6 |
unneback |
// Global buffer
|
| 378 |
|
|
// usage:
|
| 379 |
|
|
// use to enable global buffers for high fan out signals such as clock and reset
|
| 380 |
|
|
// Version: 8.4 8.4.0.33
|
| 381 |
|
|
module gbuf(GL,CLK);
|
| 382 |
|
|
output GL;
|
| 383 |
|
|
input CLK;
|
| 384 |
|
|
|
| 385 |
|
|
wire GND;
|
| 386 |
|
|
|
| 387 |
|
|
GND GND_1_net(.Y(GND));
|
| 388 |
|
|
CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
|
| 389 |
|
|
.DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
|
| 390 |
|
|
|
| 391 |
|
|
endmodule
|
| 392 |
|
|
`timescale 1 ns/1 ns
|
| 393 |
40 |
unneback |
`define MODULE gbuf
|
| 394 |
|
|
module `BASE`MODULE ( i, o);
|
| 395 |
|
|
`undef MODULE
|
| 396 |
6 |
unneback |
input i;
|
| 397 |
|
|
output o;
|
| 398 |
|
|
`ifdef SIM_GBUF
|
| 399 |
|
|
assign o=i;
|
| 400 |
|
|
`else
|
| 401 |
|
|
gbuf gbuf_i0 ( .CLK(i), .GL(o));
|
| 402 |
|
|
`endif
|
| 403 |
|
|
endmodule
|
| 404 |
40 |
unneback |
`endif
|
| 405 |
33 |
unneback |
|
| 406 |
6 |
unneback |
`else
|
| 407 |
33 |
unneback |
|
| 408 |
40 |
unneback |
`ifdef ALTERA
|
| 409 |
|
|
`ifdef GBUF
|
| 410 |
21 |
unneback |
//altera
|
| 411 |
40 |
unneback |
`define MODULE gbuf
|
| 412 |
|
|
module `BASE`MODULE ( i, o);
|
| 413 |
|
|
`undef MODULE
|
| 414 |
33 |
unneback |
input i;
|
| 415 |
|
|
output o;
|
| 416 |
|
|
assign o = i;
|
| 417 |
|
|
endmodule
|
| 418 |
40 |
unneback |
`endif
|
| 419 |
33 |
unneback |
|
| 420 |
6 |
unneback |
`else
|
| 421 |
|
|
|
| 422 |
40 |
unneback |
`ifdef GBUF
|
| 423 |
6 |
unneback |
`timescale 1 ns/100 ps
|
| 424 |
40 |
unneback |
`define MODULE
|
| 425 |
|
|
module `BASE`MODULE ( i, o);
|
| 426 |
|
|
`undef MODULE
|
| 427 |
6 |
unneback |
input i;
|
| 428 |
|
|
output o;
|
| 429 |
|
|
assign o = i;
|
| 430 |
|
|
endmodule
|
| 431 |
40 |
unneback |
`endif
|
| 432 |
6 |
unneback |
`endif // ALTERA
|
| 433 |
|
|
`endif //ACTEL
|
| 434 |
|
|
|
| 435 |
40 |
unneback |
`ifdef SYNC_RST
|
| 436 |
6 |
unneback |
// sync reset
|
| 437 |
17 |
unneback |
// input active lo async reset, normally from external reset generator and/or switch
|
| 438 |
6 |
unneback |
// output active high global reset sync with two DFFs
|
| 439 |
|
|
`timescale 1 ns/100 ps
|
| 440 |
40 |
unneback |
`define MODULE sync_rst
|
| 441 |
|
|
module `BASE`MODULE ( rst_n_i, rst_o, clk);
|
| 442 |
|
|
`undef MODULE
|
| 443 |
6 |
unneback |
input rst_n_i, clk;
|
| 444 |
|
|
output rst_o;
|
| 445 |
18 |
unneback |
reg [1:0] tmp;
|
| 446 |
6 |
unneback |
always @ (posedge clk or negedge rst_n_i)
|
| 447 |
|
|
if (!rst_n_i)
|
| 448 |
17 |
unneback |
tmp <= 2'b11;
|
| 449 |
6 |
unneback |
else
|
| 450 |
33 |
unneback |
tmp <= {1'b0,tmp[1]};
|
| 451 |
40 |
unneback |
`define MODULE gbuf
|
| 452 |
|
|
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
|
| 453 |
|
|
`undef MODULE
|
| 454 |
6 |
unneback |
endmodule
|
| 455 |
40 |
unneback |
`endif
|
| 456 |
6 |
unneback |
|
| 457 |
40 |
unneback |
`ifdef PLL
|
| 458 |
6 |
unneback |
// vl_pll
|
| 459 |
|
|
`ifdef ACTEL
|
| 460 |
32 |
unneback |
///////////////////////////////////////////////////////////////////////////////
|
| 461 |
17 |
unneback |
`timescale 1 ps/1 ps
|
| 462 |
40 |
unneback |
`define MODULE pll
|
| 463 |
|
|
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
|
| 464 |
|
|
`undef MODULE
|
| 465 |
6 |
unneback |
parameter index = 0;
|
| 466 |
|
|
parameter number_of_clk = 1;
|
| 467 |
17 |
unneback |
parameter period_time_0 = 20000;
|
| 468 |
|
|
parameter period_time_1 = 20000;
|
| 469 |
|
|
parameter period_time_2 = 20000;
|
| 470 |
|
|
parameter lock_delay = 2000000;
|
| 471 |
6 |
unneback |
input clk_i, rst_n_i;
|
| 472 |
|
|
output lock;
|
| 473 |
|
|
output reg [0:number_of_clk-1] clk_o;
|
| 474 |
|
|
output [0:number_of_clk-1] rst_o;
|
| 475 |
|
|
|
| 476 |
|
|
`ifdef SIM_PLL
|
| 477 |
|
|
|
| 478 |
|
|
always
|
| 479 |
|
|
#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
|
| 480 |
|
|
|
| 481 |
|
|
generate if (number_of_clk > 1)
|
| 482 |
|
|
always
|
| 483 |
|
|
#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
|
| 484 |
|
|
endgenerate
|
| 485 |
|
|
|
| 486 |
|
|
generate if (number_of_clk > 2)
|
| 487 |
|
|
always
|
| 488 |
|
|
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
|
| 489 |
|
|
endgenerate
|
| 490 |
|
|
|
| 491 |
|
|
genvar i;
|
| 492 |
|
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
| 493 |
|
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
| 494 |
|
|
end
|
| 495 |
|
|
endgenerate
|
| 496 |
|
|
|
| 497 |
|
|
assign #lock_delay lock = rst_n_i;
|
| 498 |
|
|
|
| 499 |
|
|
endmodule
|
| 500 |
|
|
`else
|
| 501 |
|
|
generate if (number_of_clk==1 & index==0) begin
|
| 502 |
|
|
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
| 503 |
|
|
end
|
| 504 |
|
|
endgenerate // index==0
|
| 505 |
|
|
generate if (number_of_clk==1 & index==1) begin
|
| 506 |
|
|
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
| 507 |
|
|
end
|
| 508 |
|
|
endgenerate // index==1
|
| 509 |
|
|
generate if (number_of_clk==1 & index==2) begin
|
| 510 |
|
|
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
| 511 |
|
|
end
|
| 512 |
|
|
endgenerate // index==2
|
| 513 |
|
|
generate if (number_of_clk==1 & index==3) begin
|
| 514 |
|
|
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
| 515 |
|
|
end
|
| 516 |
|
|
endgenerate // index==0
|
| 517 |
|
|
|
| 518 |
|
|
generate if (number_of_clk==2 & index==0) begin
|
| 519 |
|
|
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
| 520 |
|
|
end
|
| 521 |
|
|
endgenerate // index==0
|
| 522 |
|
|
generate if (number_of_clk==2 & index==1) begin
|
| 523 |
|
|
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
| 524 |
|
|
end
|
| 525 |
|
|
endgenerate // index==1
|
| 526 |
|
|
generate if (number_of_clk==2 & index==2) begin
|
| 527 |
|
|
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
| 528 |
|
|
end
|
| 529 |
|
|
endgenerate // index==2
|
| 530 |
|
|
generate if (number_of_clk==2 & index==3) begin
|
| 531 |
|
|
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
| 532 |
|
|
end
|
| 533 |
|
|
endgenerate // index==0
|
| 534 |
|
|
|
| 535 |
|
|
generate if (number_of_clk==3 & index==0) begin
|
| 536 |
|
|
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
| 537 |
|
|
end
|
| 538 |
|
|
endgenerate // index==0
|
| 539 |
|
|
generate if (number_of_clk==3 & index==1) begin
|
| 540 |
|
|
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
| 541 |
|
|
end
|
| 542 |
|
|
endgenerate // index==1
|
| 543 |
|
|
generate if (number_of_clk==3 & index==2) begin
|
| 544 |
|
|
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
| 545 |
|
|
end
|
| 546 |
|
|
endgenerate // index==2
|
| 547 |
|
|
generate if (number_of_clk==3 & index==3) begin
|
| 548 |
|
|
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
| 549 |
|
|
end
|
| 550 |
|
|
endgenerate // index==0
|
| 551 |
|
|
|
| 552 |
|
|
genvar i;
|
| 553 |
|
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
| 554 |
40 |
unneback |
`define MODULE sync_rst
|
| 555 |
|
|
`BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
|
| 556 |
|
|
`undef MODULE
|
| 557 |
6 |
unneback |
end
|
| 558 |
|
|
endgenerate
|
| 559 |
|
|
endmodule
|
| 560 |
|
|
`endif
|
| 561 |
32 |
unneback |
///////////////////////////////////////////////////////////////////////////////
|
| 562 |
6 |
unneback |
|
| 563 |
|
|
`else
|
| 564 |
|
|
|
| 565 |
32 |
unneback |
///////////////////////////////////////////////////////////////////////////////
|
| 566 |
6 |
unneback |
`ifdef ALTERA
|
| 567 |
|
|
|
| 568 |
32 |
unneback |
`timescale 1 ps/1 ps
|
| 569 |
40 |
unneback |
`define MODULE pll
|
| 570 |
|
|
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
|
| 571 |
|
|
`undef MODULE
|
| 572 |
32 |
unneback |
parameter index = 0;
|
| 573 |
|
|
parameter number_of_clk = 1;
|
| 574 |
|
|
parameter period_time_0 = 20000;
|
| 575 |
|
|
parameter period_time_1 = 20000;
|
| 576 |
|
|
parameter period_time_2 = 20000;
|
| 577 |
|
|
parameter period_time_3 = 20000;
|
| 578 |
|
|
parameter period_time_4 = 20000;
|
| 579 |
|
|
parameter lock_delay = 2000000;
|
| 580 |
|
|
input clk_i, rst_n_i;
|
| 581 |
|
|
output lock;
|
| 582 |
|
|
output reg [0:number_of_clk-1] clk_o;
|
| 583 |
|
|
output [0:number_of_clk-1] rst_o;
|
| 584 |
|
|
|
| 585 |
|
|
`ifdef SIM_PLL
|
| 586 |
|
|
|
| 587 |
|
|
always
|
| 588 |
|
|
#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
|
| 589 |
|
|
|
| 590 |
|
|
generate if (number_of_clk > 1)
|
| 591 |
|
|
always
|
| 592 |
|
|
#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
|
| 593 |
|
|
endgenerate
|
| 594 |
|
|
|
| 595 |
|
|
generate if (number_of_clk > 2)
|
| 596 |
|
|
always
|
| 597 |
|
|
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
|
| 598 |
|
|
endgenerate
|
| 599 |
|
|
|
| 600 |
33 |
unneback |
generate if (number_of_clk > 3)
|
| 601 |
32 |
unneback |
always
|
| 602 |
|
|
#((period_time_3)/2) clk_o[3] <= (!rst_n_i) ? 0 : ~clk_o[3];
|
| 603 |
|
|
endgenerate
|
| 604 |
|
|
|
| 605 |
33 |
unneback |
generate if (number_of_clk > 4)
|
| 606 |
32 |
unneback |
always
|
| 607 |
|
|
#((period_time_4)/2) clk_o[4] <= (!rst_n_i) ? 0 : ~clk_o[4];
|
| 608 |
|
|
endgenerate
|
| 609 |
|
|
|
| 610 |
|
|
genvar i;
|
| 611 |
|
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
| 612 |
|
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
| 613 |
|
|
end
|
| 614 |
|
|
endgenerate
|
| 615 |
|
|
|
| 616 |
33 |
unneback |
//assign #lock_delay lock = rst_n_i;
|
| 617 |
|
|
assign lock = rst_n_i;
|
| 618 |
32 |
unneback |
|
| 619 |
|
|
endmodule
|
| 620 |
6 |
unneback |
`else
|
| 621 |
|
|
|
| 622 |
33 |
unneback |
`ifdef VL_PLL0
|
| 623 |
|
|
`ifdef VL_PLL0_CLK1
|
| 624 |
|
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
| 625 |
|
|
`endif
|
| 626 |
|
|
`ifdef VL_PLL0_CLK2
|
| 627 |
|
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
| 628 |
|
|
`endif
|
| 629 |
|
|
`ifdef VL_PLL0_CLK3
|
| 630 |
|
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
| 631 |
|
|
`endif
|
| 632 |
|
|
`ifdef VL_PLL0_CLK4
|
| 633 |
|
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
| 634 |
|
|
`endif
|
| 635 |
|
|
`ifdef VL_PLL0_CLK5
|
| 636 |
|
|
pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
| 637 |
|
|
`endif
|
| 638 |
|
|
`endif
|
| 639 |
32 |
unneback |
|
| 640 |
33 |
unneback |
`ifdef VL_PLL1
|
| 641 |
|
|
`ifdef VL_PLL1_CLK1
|
| 642 |
|
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
| 643 |
|
|
`endif
|
| 644 |
|
|
`ifdef VL_PLL1_CLK2
|
| 645 |
|
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
| 646 |
|
|
`endif
|
| 647 |
|
|
`ifdef VL_PLL1_CLK3
|
| 648 |
|
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
| 649 |
|
|
`endif
|
| 650 |
|
|
`ifdef VL_PLL1_CLK4
|
| 651 |
|
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
| 652 |
|
|
`endif
|
| 653 |
|
|
`ifdef VL_PLL1_CLK5
|
| 654 |
|
|
pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
| 655 |
|
|
`endif
|
| 656 |
|
|
`endif
|
| 657 |
32 |
unneback |
|
| 658 |
33 |
unneback |
`ifdef VL_PLL2
|
| 659 |
|
|
`ifdef VL_PLL2_CLK1
|
| 660 |
|
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
| 661 |
|
|
`endif
|
| 662 |
|
|
`ifdef VL_PLL2_CLK2
|
| 663 |
|
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
| 664 |
|
|
`endif
|
| 665 |
|
|
`ifdef VL_PLL2_CLK3
|
| 666 |
|
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
| 667 |
|
|
`endif
|
| 668 |
|
|
`ifdef VL_PLL2_CLK4
|
| 669 |
|
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
| 670 |
|
|
`endif
|
| 671 |
|
|
`ifdef VL_PLL2_CLK5
|
| 672 |
|
|
pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
| 673 |
|
|
`endif
|
| 674 |
|
|
`endif
|
| 675 |
32 |
unneback |
|
| 676 |
33 |
unneback |
`ifdef VL_PLL3
|
| 677 |
|
|
`ifdef VL_PLL3_CLK1
|
| 678 |
|
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
|
| 679 |
|
|
`endif
|
| 680 |
|
|
`ifdef VL_PLL3_CLK2
|
| 681 |
|
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
|
| 682 |
|
|
`endif
|
| 683 |
|
|
`ifdef VL_PLL3_CLK3
|
| 684 |
|
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
|
| 685 |
|
|
`endif
|
| 686 |
|
|
`ifdef VL_PLL3_CLK4
|
| 687 |
|
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
|
| 688 |
|
|
`endif
|
| 689 |
|
|
`ifdef VL_PLL3_CLK5
|
| 690 |
|
|
pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
|
| 691 |
|
|
`endif
|
| 692 |
|
|
`endif
|
| 693 |
32 |
unneback |
|
| 694 |
|
|
genvar i;
|
| 695 |
|
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
| 696 |
40 |
unneback |
`define MODULE sync_rst
|
| 697 |
|
|
`BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
| 698 |
|
|
`undef MODULE
|
| 699 |
32 |
unneback |
end
|
| 700 |
|
|
endgenerate
|
| 701 |
|
|
endmodule
|
| 702 |
|
|
`endif
|
| 703 |
|
|
///////////////////////////////////////////////////////////////////////////////
|
| 704 |
|
|
|
| 705 |
|
|
`else
|
| 706 |
|
|
|
| 707 |
6 |
unneback |
// generic PLL
|
| 708 |
17 |
unneback |
`timescale 1 ps/1 ps
|
| 709 |
40 |
unneback |
`define MODULE pll
|
| 710 |
|
|
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
|
| 711 |
|
|
`undef MODULE
|
| 712 |
6 |
unneback |
parameter index = 0;
|
| 713 |
|
|
parameter number_of_clk = 1;
|
| 714 |
17 |
unneback |
parameter period_time_0 = 20000;
|
| 715 |
|
|
parameter period_time_1 = 20000;
|
| 716 |
|
|
parameter period_time_2 = 20000;
|
| 717 |
6 |
unneback |
parameter lock_delay = 2000;
|
| 718 |
|
|
input clk_i, rst_n_i;
|
| 719 |
|
|
output lock;
|
| 720 |
|
|
output reg [0:number_of_clk-1] clk_o;
|
| 721 |
|
|
output [0:number_of_clk-1] rst_o;
|
| 722 |
|
|
|
| 723 |
|
|
always
|
| 724 |
|
|
#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
|
| 725 |
|
|
|
| 726 |
|
|
generate if (number_of_clk > 1)
|
| 727 |
|
|
always
|
| 728 |
|
|
#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
|
| 729 |
|
|
endgenerate
|
| 730 |
|
|
|
| 731 |
|
|
generate if (number_of_clk > 2)
|
| 732 |
|
|
always
|
| 733 |
|
|
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
|
| 734 |
|
|
endgenerate
|
| 735 |
|
|
|
| 736 |
|
|
genvar i;
|
| 737 |
|
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
| 738 |
40 |
unneback |
`define MODULE sync_rst
|
| 739 |
|
|
`BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
| 740 |
|
|
`undef MODULE
|
| 741 |
6 |
unneback |
end
|
| 742 |
|
|
endgenerate
|
| 743 |
|
|
|
| 744 |
|
|
assign #lock_delay lock = rst_n_i;
|
| 745 |
|
|
|
| 746 |
|
|
endmodule
|
| 747 |
|
|
|
| 748 |
|
|
`endif //altera
|
| 749 |
17 |
unneback |
`endif //actel
|
| 750 |
40 |
unneback |
`undef MODULE
|
| 751 |
|
|
`endif//////////////////////////////////////////////////////////////////////
|
| 752 |
6 |
unneback |
//// ////
|
| 753 |
|
|
//// Versatile library, registers ////
|
| 754 |
|
|
//// ////
|
| 755 |
|
|
//// Description ////
|
| 756 |
|
|
//// Different type of registers ////
|
| 757 |
|
|
//// ////
|
| 758 |
|
|
//// ////
|
| 759 |
|
|
//// To Do: ////
|
| 760 |
|
|
//// - add more different registers ////
|
| 761 |
|
|
//// ////
|
| 762 |
|
|
//// Author(s): ////
|
| 763 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 764 |
|
|
//// ORSoC AB ////
|
| 765 |
|
|
//// ////
|
| 766 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 767 |
|
|
//// ////
|
| 768 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
| 769 |
|
|
//// ////
|
| 770 |
|
|
//// This source file may be used and distributed without ////
|
| 771 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 772 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 773 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 774 |
|
|
//// ////
|
| 775 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 776 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 777 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 778 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 779 |
|
|
//// later version. ////
|
| 780 |
|
|
//// ////
|
| 781 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 782 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 783 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 784 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 785 |
|
|
//// details. ////
|
| 786 |
|
|
//// ////
|
| 787 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 788 |
|
|
//// Public License along with this source; if not, download it ////
|
| 789 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 790 |
|
|
//// ////
|
| 791 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 792 |
|
|
|
| 793 |
40 |
unneback |
`ifdef DFF
|
| 794 |
|
|
`define MODULE dff
|
| 795 |
|
|
module `BASE`MODULE ( d, q, clk, rst);
|
| 796 |
|
|
`undef MODULE
|
| 797 |
6 |
unneback |
parameter width = 1;
|
| 798 |
|
|
parameter reset_value = 0;
|
| 799 |
|
|
|
| 800 |
|
|
input [width-1:0] d;
|
| 801 |
|
|
input clk, rst;
|
| 802 |
|
|
output reg [width-1:0] q;
|
| 803 |
|
|
|
| 804 |
|
|
always @ (posedge clk or posedge rst)
|
| 805 |
|
|
if (rst)
|
| 806 |
|
|
q <= reset_value;
|
| 807 |
|
|
else
|
| 808 |
|
|
q <= d;
|
| 809 |
|
|
|
| 810 |
|
|
endmodule
|
| 811 |
40 |
unneback |
`endif
|
| 812 |
6 |
unneback |
|
| 813 |
40 |
unneback |
`ifdef DFF_ARRAY
|
| 814 |
|
|
`define MODULE dff_array
|
| 815 |
|
|
module `BASE`MODULE ( d, q, clk, rst);
|
| 816 |
|
|
`undef MODULE
|
| 817 |
6 |
unneback |
|
| 818 |
|
|
parameter width = 1;
|
| 819 |
|
|
parameter depth = 2;
|
| 820 |
|
|
parameter reset_value = 1'b0;
|
| 821 |
|
|
|
| 822 |
|
|
input [width-1:0] d;
|
| 823 |
|
|
input clk, rst;
|
| 824 |
|
|
output [width-1:0] q;
|
| 825 |
|
|
reg [0:depth-1] q_tmp [width-1:0];
|
| 826 |
|
|
integer i;
|
| 827 |
|
|
always @ (posedge clk or posedge rst)
|
| 828 |
|
|
if (rst) begin
|
| 829 |
|
|
for (i=0;i<depth;i=i+1)
|
| 830 |
|
|
q_tmp[i] <= {width{reset_value}};
|
| 831 |
|
|
end else begin
|
| 832 |
|
|
q_tmp[0] <= d;
|
| 833 |
|
|
for (i=1;i<depth;i=i+1)
|
| 834 |
|
|
q_tmp[i] <= q_tmp[i-1];
|
| 835 |
|
|
end
|
| 836 |
|
|
|
| 837 |
|
|
assign q = q_tmp[depth-1];
|
| 838 |
|
|
|
| 839 |
|
|
endmodule
|
| 840 |
40 |
unneback |
`endif
|
| 841 |
6 |
unneback |
|
| 842 |
40 |
unneback |
`ifdef DFF_CE
|
| 843 |
|
|
`define MODULE dff_ce
|
| 844 |
|
|
module `BASE`MODULE ( d, ce, q, clk, rst);
|
| 845 |
|
|
`undef MODULE
|
| 846 |
6 |
unneback |
|
| 847 |
|
|
parameter width = 1;
|
| 848 |
|
|
parameter reset_value = 0;
|
| 849 |
|
|
|
| 850 |
|
|
input [width-1:0] d;
|
| 851 |
|
|
input ce, clk, rst;
|
| 852 |
|
|
output reg [width-1:0] q;
|
| 853 |
|
|
|
| 854 |
|
|
always @ (posedge clk or posedge rst)
|
| 855 |
|
|
if (rst)
|
| 856 |
|
|
q <= reset_value;
|
| 857 |
|
|
else
|
| 858 |
|
|
if (ce)
|
| 859 |
|
|
q <= d;
|
| 860 |
|
|
|
| 861 |
|
|
endmodule
|
| 862 |
40 |
unneback |
`endif
|
| 863 |
6 |
unneback |
|
| 864 |
40 |
unneback |
`ifdef DFF_CE_CLEAR
|
| 865 |
|
|
`define MODULE dff_ce_clear
|
| 866 |
|
|
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
|
| 867 |
|
|
`undef MODULE
|
| 868 |
8 |
unneback |
|
| 869 |
|
|
parameter width = 1;
|
| 870 |
|
|
parameter reset_value = 0;
|
| 871 |
|
|
|
| 872 |
|
|
input [width-1:0] d;
|
| 873 |
10 |
unneback |
input ce, clear, clk, rst;
|
| 874 |
8 |
unneback |
output reg [width-1:0] q;
|
| 875 |
|
|
|
| 876 |
|
|
always @ (posedge clk or posedge rst)
|
| 877 |
|
|
if (rst)
|
| 878 |
|
|
q <= reset_value;
|
| 879 |
|
|
else
|
| 880 |
|
|
if (ce)
|
| 881 |
|
|
if (clear)
|
| 882 |
|
|
q <= {width{1'b0}};
|
| 883 |
|
|
else
|
| 884 |
|
|
q <= d;
|
| 885 |
|
|
|
| 886 |
|
|
endmodule
|
| 887 |
40 |
unneback |
`endif
|
| 888 |
8 |
unneback |
|
| 889 |
40 |
unneback |
`ifdef DF_CE_SET
|
| 890 |
|
|
`define MODULE dff_ce_set
|
| 891 |
|
|
module `BASE`MODULE ( d, ce, set, q, clk, rst);
|
| 892 |
|
|
`undef MODULE
|
| 893 |
24 |
unneback |
|
| 894 |
|
|
parameter width = 1;
|
| 895 |
|
|
parameter reset_value = 0;
|
| 896 |
|
|
|
| 897 |
|
|
input [width-1:0] d;
|
| 898 |
|
|
input ce, set, clk, rst;
|
| 899 |
|
|
output reg [width-1:0] q;
|
| 900 |
|
|
|
| 901 |
|
|
always @ (posedge clk or posedge rst)
|
| 902 |
|
|
if (rst)
|
| 903 |
|
|
q <= reset_value;
|
| 904 |
|
|
else
|
| 905 |
|
|
if (ce)
|
| 906 |
|
|
if (set)
|
| 907 |
|
|
q <= {width{1'b1}};
|
| 908 |
|
|
else
|
| 909 |
|
|
q <= d;
|
| 910 |
|
|
|
| 911 |
|
|
endmodule
|
| 912 |
40 |
unneback |
`endif
|
| 913 |
24 |
unneback |
|
| 914 |
40 |
unneback |
`ifdef SPR
|
| 915 |
|
|
`define MODULE spr
|
| 916 |
|
|
module `BASE`MODULE ( sp, r, q, clk, rst);
|
| 917 |
|
|
`undef MODULE
|
| 918 |
|
|
|
| 919 |
64 |
unneback |
//parameter width = 1;
|
| 920 |
|
|
parameter reset_value = 1'b0;
|
| 921 |
29 |
unneback |
|
| 922 |
|
|
input sp, r;
|
| 923 |
|
|
output reg q;
|
| 924 |
|
|
input clk, rst;
|
| 925 |
|
|
|
| 926 |
|
|
always @ (posedge clk or posedge rst)
|
| 927 |
|
|
if (rst)
|
| 928 |
|
|
q <= reset_value;
|
| 929 |
|
|
else
|
| 930 |
|
|
if (sp)
|
| 931 |
|
|
q <= 1'b1;
|
| 932 |
|
|
else if (r)
|
| 933 |
|
|
q <= 1'b0;
|
| 934 |
|
|
|
| 935 |
|
|
endmodule
|
| 936 |
40 |
unneback |
`endif
|
| 937 |
29 |
unneback |
|
| 938 |
40 |
unneback |
`ifdef SRP
|
| 939 |
|
|
`define MODULE srp
|
| 940 |
|
|
module `BASE`MODULE ( s, rp, q, clk, rst);
|
| 941 |
|
|
`undef MODULE
|
| 942 |
|
|
|
| 943 |
29 |
unneback |
parameter width = 1;
|
| 944 |
|
|
parameter reset_value = 0;
|
| 945 |
|
|
|
| 946 |
|
|
input s, rp;
|
| 947 |
|
|
output reg q;
|
| 948 |
|
|
input clk, rst;
|
| 949 |
|
|
|
| 950 |
|
|
always @ (posedge clk or posedge rst)
|
| 951 |
|
|
if (rst)
|
| 952 |
|
|
q <= reset_value;
|
| 953 |
|
|
else
|
| 954 |
|
|
if (rp)
|
| 955 |
|
|
q <= 1'b0;
|
| 956 |
|
|
else if (s)
|
| 957 |
|
|
q <= 1'b1;
|
| 958 |
|
|
|
| 959 |
|
|
endmodule
|
| 960 |
40 |
unneback |
`endif
|
| 961 |
29 |
unneback |
|
| 962 |
40 |
unneback |
`ifdef ALTERA
|
| 963 |
29 |
unneback |
|
| 964 |
40 |
unneback |
`ifdef DFF_SR
|
| 965 |
6 |
unneback |
// megafunction wizard: %LPM_FF%
|
| 966 |
|
|
// GENERATION: STANDARD
|
| 967 |
|
|
// VERSION: WM1.0
|
| 968 |
|
|
// MODULE: lpm_ff
|
| 969 |
|
|
|
| 970 |
|
|
// ============================================================
|
| 971 |
|
|
// File Name: dff_sr.v
|
| 972 |
|
|
// Megafunction Name(s):
|
| 973 |
|
|
// lpm_ff
|
| 974 |
|
|
//
|
| 975 |
|
|
// Simulation Library Files(s):
|
| 976 |
|
|
// lpm
|
| 977 |
|
|
// ============================================================
|
| 978 |
|
|
// ************************************************************
|
| 979 |
|
|
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
| 980 |
|
|
//
|
| 981 |
|
|
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
|
| 982 |
|
|
// ************************************************************
|
| 983 |
|
|
|
| 984 |
|
|
|
| 985 |
|
|
//Copyright (C) 1991-2010 Altera Corporation
|
| 986 |
|
|
//Your use of Altera Corporation's design tools, logic functions
|
| 987 |
|
|
//and other software and tools, and its AMPP partner logic
|
| 988 |
|
|
//functions, and any output files from any of the foregoing
|
| 989 |
|
|
//(including device programming or simulation files), and any
|
| 990 |
|
|
//associated documentation or information are expressly subject
|
| 991 |
|
|
//to the terms and conditions of the Altera Program License
|
| 992 |
|
|
//Subscription Agreement, Altera MegaCore Function License
|
| 993 |
|
|
//Agreement, or other applicable license agreement, including,
|
| 994 |
|
|
//without limitation, that your use is for the sole purpose of
|
| 995 |
|
|
//programming logic devices manufactured by Altera and sold by
|
| 996 |
|
|
//Altera or its authorized distributors. Please refer to the
|
| 997 |
|
|
//applicable agreement for further details.
|
| 998 |
|
|
|
| 999 |
|
|
|
| 1000 |
|
|
// synopsys translate_off
|
| 1001 |
|
|
`timescale 1 ps / 1 ps
|
| 1002 |
|
|
// synopsys translate_on
|
| 1003 |
40 |
unneback |
`define MODULE dff_sr
|
| 1004 |
|
|
module `BASE`MODULE (
|
| 1005 |
|
|
`undef MODULE
|
| 1006 |
|
|
|
| 1007 |
6 |
unneback |
aclr,
|
| 1008 |
|
|
aset,
|
| 1009 |
|
|
clock,
|
| 1010 |
|
|
data,
|
| 1011 |
|
|
q);
|
| 1012 |
|
|
|
| 1013 |
|
|
input aclr;
|
| 1014 |
|
|
input aset;
|
| 1015 |
|
|
input clock;
|
| 1016 |
|
|
input data;
|
| 1017 |
|
|
output q;
|
| 1018 |
|
|
|
| 1019 |
|
|
wire [0:0] sub_wire0;
|
| 1020 |
|
|
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
| 1021 |
|
|
wire q = sub_wire1;
|
| 1022 |
|
|
wire sub_wire2 = data;
|
| 1023 |
|
|
wire sub_wire3 = sub_wire2;
|
| 1024 |
|
|
|
| 1025 |
|
|
lpm_ff lpm_ff_component (
|
| 1026 |
|
|
.aclr (aclr),
|
| 1027 |
|
|
.clock (clock),
|
| 1028 |
|
|
.data (sub_wire3),
|
| 1029 |
|
|
.aset (aset),
|
| 1030 |
|
|
.q (sub_wire0)
|
| 1031 |
|
|
// synopsys translate_off
|
| 1032 |
|
|
,
|
| 1033 |
|
|
.aload (),
|
| 1034 |
|
|
.enable (),
|
| 1035 |
|
|
.sclr (),
|
| 1036 |
|
|
.sload (),
|
| 1037 |
|
|
.sset ()
|
| 1038 |
|
|
// synopsys translate_on
|
| 1039 |
|
|
);
|
| 1040 |
|
|
defparam
|
| 1041 |
|
|
lpm_ff_component.lpm_fftype = "DFF",
|
| 1042 |
|
|
lpm_ff_component.lpm_type = "LPM_FF",
|
| 1043 |
|
|
lpm_ff_component.lpm_width = 1;
|
| 1044 |
|
|
|
| 1045 |
|
|
|
| 1046 |
|
|
endmodule
|
| 1047 |
|
|
|
| 1048 |
|
|
// ============================================================
|
| 1049 |
|
|
// CNX file retrieval info
|
| 1050 |
|
|
// ============================================================
|
| 1051 |
|
|
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
|
| 1052 |
|
|
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
|
| 1053 |
|
|
// Retrieval info: PRIVATE: ASET NUMERIC "1"
|
| 1054 |
|
|
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
|
| 1055 |
|
|
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
|
| 1056 |
|
|
// Retrieval info: PRIVATE: DFF NUMERIC "1"
|
| 1057 |
|
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
| 1058 |
|
|
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
|
| 1059 |
|
|
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
|
| 1060 |
|
|
// Retrieval info: PRIVATE: SSET NUMERIC "0"
|
| 1061 |
|
|
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
|
| 1062 |
|
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
| 1063 |
|
|
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
|
| 1064 |
|
|
// Retrieval info: PRIVATE: nBit NUMERIC "1"
|
| 1065 |
|
|
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
|
| 1066 |
|
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
|
| 1067 |
|
|
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
|
| 1068 |
|
|
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
|
| 1069 |
|
|
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
|
| 1070 |
|
|
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
| 1071 |
|
|
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
|
| 1072 |
|
|
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
|
| 1073 |
|
|
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
| 1074 |
|
|
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
|
| 1075 |
|
|
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
| 1076 |
|
|
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
|
| 1077 |
|
|
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
|
| 1078 |
|
|
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
| 1079 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
|
| 1080 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
|
| 1081 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
|
| 1082 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
|
| 1083 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
|
| 1084 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
|
| 1085 |
|
|
// Retrieval info: LIB_FILE: lpm
|
| 1086 |
40 |
unneback |
`endif
|
| 1087 |
6 |
unneback |
|
| 1088 |
|
|
`else
|
| 1089 |
|
|
|
| 1090 |
40 |
unneback |
`ifdef DFF_SR
|
| 1091 |
|
|
`define MODULE dff_sr
|
| 1092 |
|
|
module `BASE`MODULE ( aclr, aset, clock, data, q);
|
| 1093 |
|
|
`undef MODULE
|
| 1094 |
6 |
unneback |
|
| 1095 |
|
|
input aclr;
|
| 1096 |
|
|
input aset;
|
| 1097 |
|
|
input clock;
|
| 1098 |
|
|
input data;
|
| 1099 |
|
|
output reg q;
|
| 1100 |
|
|
|
| 1101 |
|
|
always @ (posedge clock or posedge aclr or posedge aset)
|
| 1102 |
|
|
if (aclr)
|
| 1103 |
|
|
q <= 1'b0;
|
| 1104 |
|
|
else if (aset)
|
| 1105 |
|
|
q <= 1'b1;
|
| 1106 |
|
|
else
|
| 1107 |
|
|
q <= data;
|
| 1108 |
|
|
|
| 1109 |
|
|
endmodule
|
| 1110 |
40 |
unneback |
`endif
|
| 1111 |
6 |
unneback |
|
| 1112 |
|
|
`endif
|
| 1113 |
|
|
|
| 1114 |
|
|
// LATCH
|
| 1115 |
|
|
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
|
| 1116 |
|
|
`ifdef ALTERA
|
| 1117 |
40 |
unneback |
|
| 1118 |
|
|
`ifdef LATCH
|
| 1119 |
|
|
`define MODULE latch
|
| 1120 |
|
|
module `BASE`MODULE ( d, le, q, clk);
|
| 1121 |
|
|
`undef MODULE
|
| 1122 |
6 |
unneback |
input d, le;
|
| 1123 |
|
|
output q;
|
| 1124 |
|
|
input clk;
|
| 1125 |
|
|
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
|
| 1126 |
|
|
endmodule
|
| 1127 |
40 |
unneback |
`endif
|
| 1128 |
|
|
|
| 1129 |
6 |
unneback |
`else
|
| 1130 |
40 |
unneback |
|
| 1131 |
|
|
`ifdef LATCH
|
| 1132 |
|
|
`define MODULE latch
|
| 1133 |
|
|
module `BASE`MODULE ( d, le, q, clk);
|
| 1134 |
|
|
`undef MODULE
|
| 1135 |
6 |
unneback |
input d, le;
|
| 1136 |
48 |
unneback |
input clk;
|
| 1137 |
|
|
always @ (le or d)
|
| 1138 |
60 |
unneback |
if (le)
|
| 1139 |
48 |
unneback |
d <= q;
|
| 1140 |
6 |
unneback |
endmodule
|
| 1141 |
15 |
unneback |
`endif
|
| 1142 |
|
|
|
| 1143 |
40 |
unneback |
`endif
|
| 1144 |
|
|
|
| 1145 |
|
|
`ifdef SHREG
|
| 1146 |
|
|
`define MODULE shreg
|
| 1147 |
|
|
module `BASE`MODULE ( d, q, clk, rst);
|
| 1148 |
|
|
`undef MODULE
|
| 1149 |
|
|
|
| 1150 |
17 |
unneback |
parameter depth = 10;
|
| 1151 |
|
|
input d;
|
| 1152 |
|
|
output q;
|
| 1153 |
|
|
input clk, rst;
|
| 1154 |
|
|
|
| 1155 |
|
|
reg [1:depth] dffs;
|
| 1156 |
|
|
|
| 1157 |
|
|
always @ (posedge clk or posedge rst)
|
| 1158 |
|
|
if (rst)
|
| 1159 |
|
|
dffs <= {depth{1'b0}};
|
| 1160 |
|
|
else
|
| 1161 |
|
|
dffs <= {d,dffs[1:depth-1]};
|
| 1162 |
|
|
assign q = dffs[depth];
|
| 1163 |
|
|
endmodule
|
| 1164 |
40 |
unneback |
`endif
|
| 1165 |
17 |
unneback |
|
| 1166 |
40 |
unneback |
`ifdef SHREG_CE
|
| 1167 |
|
|
`define MODULE shreg_ce
|
| 1168 |
|
|
module `BASE`MODULE ( d, ce, q, clk, rst);
|
| 1169 |
|
|
`undef MODULE
|
| 1170 |
17 |
unneback |
parameter depth = 10;
|
| 1171 |
|
|
input d, ce;
|
| 1172 |
|
|
output q;
|
| 1173 |
|
|
input clk, rst;
|
| 1174 |
|
|
|
| 1175 |
|
|
reg [1:depth] dffs;
|
| 1176 |
|
|
|
| 1177 |
|
|
always @ (posedge clk or posedge rst)
|
| 1178 |
|
|
if (rst)
|
| 1179 |
|
|
dffs <= {depth{1'b0}};
|
| 1180 |
|
|
else
|
| 1181 |
|
|
if (ce)
|
| 1182 |
|
|
dffs <= {d,dffs[1:depth-1]};
|
| 1183 |
|
|
assign q = dffs[depth];
|
| 1184 |
|
|
endmodule
|
| 1185 |
40 |
unneback |
`endif
|
| 1186 |
17 |
unneback |
|
| 1187 |
40 |
unneback |
`ifdef DELAY
|
| 1188 |
|
|
`define MODULE delay
|
| 1189 |
|
|
module `BASE`MODULE ( d, q, clk, rst);
|
| 1190 |
|
|
`undef MODULE
|
| 1191 |
15 |
unneback |
parameter depth = 10;
|
| 1192 |
|
|
input d;
|
| 1193 |
|
|
output q;
|
| 1194 |
|
|
input clk, rst;
|
| 1195 |
|
|
|
| 1196 |
|
|
reg [1:depth] dffs;
|
| 1197 |
|
|
|
| 1198 |
|
|
always @ (posedge clk or posedge rst)
|
| 1199 |
|
|
if (rst)
|
| 1200 |
|
|
dffs <= {depth{1'b0}};
|
| 1201 |
|
|
else
|
| 1202 |
|
|
dffs <= {d,dffs[1:depth-1]};
|
| 1203 |
|
|
assign q = dffs[depth];
|
| 1204 |
17 |
unneback |
endmodule
|
| 1205 |
40 |
unneback |
`endif
|
| 1206 |
17 |
unneback |
|
| 1207 |
40 |
unneback |
`ifdef DELAY_EMPTYFLAG
|
| 1208 |
|
|
`define MODULE delay_emptyflag
|
| 1209 |
41 |
unneback |
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
|
| 1210 |
40 |
unneback |
`undef MODULE
|
| 1211 |
17 |
unneback |
parameter depth = 10;
|
| 1212 |
|
|
input d;
|
| 1213 |
|
|
output q, emptyflag;
|
| 1214 |
|
|
input clk, rst;
|
| 1215 |
|
|
|
| 1216 |
|
|
reg [1:depth] dffs;
|
| 1217 |
|
|
|
| 1218 |
|
|
always @ (posedge clk or posedge rst)
|
| 1219 |
|
|
if (rst)
|
| 1220 |
|
|
dffs <= {depth{1'b0}};
|
| 1221 |
|
|
else
|
| 1222 |
|
|
dffs <= {d,dffs[1:depth-1]};
|
| 1223 |
|
|
assign q = dffs[depth];
|
| 1224 |
|
|
assign emptyflag = !(|dffs);
|
| 1225 |
|
|
endmodule
|
| 1226 |
40 |
unneback |
`endif
|
| 1227 |
75 |
unneback |
|
| 1228 |
94 |
unneback |
`ifdef PULSE2TOGGLE
|
| 1229 |
98 |
unneback |
`define MODULE pulse2toggle
|
| 1230 |
|
|
module `BASE`MODULE ( pl, q, clk, rst);
|
| 1231 |
75 |
unneback |
`undef MODULE
|
| 1232 |
94 |
unneback |
input pl;
|
| 1233 |
98 |
unneback |
output reg q;
|
| 1234 |
94 |
unneback |
input clk, rst;
|
| 1235 |
|
|
always @ (posedge clk or posedge rst)
|
| 1236 |
75 |
unneback |
if (rst)
|
| 1237 |
94 |
unneback |
q <= 1'b0;
|
| 1238 |
75 |
unneback |
else
|
| 1239 |
94 |
unneback |
q <= pl ^ q;
|
| 1240 |
|
|
endmodule
|
| 1241 |
|
|
`endif
|
| 1242 |
75 |
unneback |
|
| 1243 |
94 |
unneback |
`ifdef TOGGLE2PULSE
|
| 1244 |
98 |
unneback |
`define MODULE toggle2pulse
|
| 1245 |
94 |
unneback |
module `BASE`MODULE (d, pl, clk, rst);
|
| 1246 |
97 |
unneback |
`undef MODULE
|
| 1247 |
94 |
unneback |
input d;
|
| 1248 |
|
|
output pl;
|
| 1249 |
|
|
input clk, rst;
|
| 1250 |
|
|
reg dff;
|
| 1251 |
|
|
always @ (posedge clk or posedge rst)
|
| 1252 |
|
|
if (rst)
|
| 1253 |
|
|
dff <= 1'b0;
|
| 1254 |
75 |
unneback |
else
|
| 1255 |
94 |
unneback |
dff <= d;
|
| 1256 |
98 |
unneback |
assign pl = d ^ dff;
|
| 1257 |
94 |
unneback |
endmodule
|
| 1258 |
|
|
`endif
|
| 1259 |
75 |
unneback |
|
| 1260 |
94 |
unneback |
`ifdef SYNCHRONIZER
|
| 1261 |
|
|
`define MODULE synchronizer
|
| 1262 |
|
|
module `BASE`MODULE (d, q, clk, rst);
|
| 1263 |
|
|
`undef MODULE
|
| 1264 |
|
|
input d;
|
| 1265 |
|
|
output reg q;
|
| 1266 |
|
|
output clk, rst;
|
| 1267 |
|
|
reg dff;
|
| 1268 |
|
|
always @ (posedge clk or posedge rst)
|
| 1269 |
|
|
if (rst)
|
| 1270 |
100 |
unneback |
{q,dff} <= 2'b00;
|
| 1271 |
75 |
unneback |
else
|
| 1272 |
100 |
unneback |
{q,dff} <= {dff,d};
|
| 1273 |
94 |
unneback |
endmodule
|
| 1274 |
|
|
`endif
|
| 1275 |
75 |
unneback |
|
| 1276 |
94 |
unneback |
`ifdef CDC
|
| 1277 |
|
|
`define MODULE cdc
|
| 1278 |
97 |
unneback |
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
|
| 1279 |
94 |
unneback |
`undef MODULE
|
| 1280 |
|
|
input start_pl;
|
| 1281 |
|
|
output take_it_pl;
|
| 1282 |
|
|
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
|
| 1283 |
|
|
output got_it_pl;
|
| 1284 |
|
|
input clk_src, rst_src;
|
| 1285 |
|
|
input clk_dst, rst_dst;
|
| 1286 |
|
|
wire take_it_tg, take_it_tg_sync;
|
| 1287 |
|
|
wire got_it_tg, got_it_tg_sync;
|
| 1288 |
|
|
// src -> dst
|
| 1289 |
|
|
`define MODULE pulse2toggle
|
| 1290 |
|
|
`BASE`MODULE p2t0 (
|
| 1291 |
|
|
`undef MODULE
|
| 1292 |
|
|
.pl(start_pl),
|
| 1293 |
|
|
.q(take_it_tg),
|
| 1294 |
|
|
.clk(clk_src),
|
| 1295 |
|
|
.rst(rst_src));
|
| 1296 |
75 |
unneback |
|
| 1297 |
94 |
unneback |
`define MODULE synchronizer
|
| 1298 |
|
|
`BASE`MODULE sync0 (
|
| 1299 |
|
|
`undef MODULE
|
| 1300 |
|
|
.d(take_it_tg),
|
| 1301 |
|
|
.q(take_it_tg_sync),
|
| 1302 |
|
|
.clk(clk_dst),
|
| 1303 |
|
|
.rst(rst_dst));
|
| 1304 |
|
|
|
| 1305 |
|
|
`define MODULE toggle2pulse
|
| 1306 |
|
|
`BASE`MODULE t2p0 (
|
| 1307 |
|
|
`undef MODULE
|
| 1308 |
100 |
unneback |
.d(take_it_tg_sync),
|
| 1309 |
94 |
unneback |
.pl(take_it_pl),
|
| 1310 |
|
|
.clk(clk_dst),
|
| 1311 |
|
|
.rst(rst_dst));
|
| 1312 |
|
|
|
| 1313 |
|
|
// dst -> src
|
| 1314 |
|
|
`define MODULE pulse2toggle
|
| 1315 |
98 |
unneback |
`BASE`MODULE p2t1 (
|
| 1316 |
94 |
unneback |
`undef MODULE
|
| 1317 |
|
|
.pl(take_it_grant_pl),
|
| 1318 |
|
|
.q(got_it_tg),
|
| 1319 |
|
|
.clk(clk_dst),
|
| 1320 |
|
|
.rst(rst_dst));
|
| 1321 |
|
|
|
| 1322 |
|
|
`define MODULE synchronizer
|
| 1323 |
|
|
`BASE`MODULE sync1 (
|
| 1324 |
|
|
`undef MODULE
|
| 1325 |
|
|
.d(got_it_tg),
|
| 1326 |
|
|
.q(got_it_tg_sync),
|
| 1327 |
|
|
.clk(clk_src),
|
| 1328 |
|
|
.rst(rst_src));
|
| 1329 |
|
|
|
| 1330 |
|
|
`define MODULE toggle2pulse
|
| 1331 |
|
|
`BASE`MODULE t2p1 (
|
| 1332 |
|
|
`undef MODULE
|
| 1333 |
100 |
unneback |
.d(got_it_tg_sync),
|
| 1334 |
94 |
unneback |
.pl(got_it_pl),
|
| 1335 |
|
|
.clk(clk_src),
|
| 1336 |
|
|
.rst(rst_src));
|
| 1337 |
|
|
|
| 1338 |
75 |
unneback |
endmodule
|
| 1339 |
|
|
`endif
|
| 1340 |
17 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 1341 |
6 |
unneback |
//// ////
|
| 1342 |
18 |
unneback |
//// Logic functions ////
|
| 1343 |
|
|
//// ////
|
| 1344 |
|
|
//// Description ////
|
| 1345 |
|
|
//// Logic functions such as multiplexers ////
|
| 1346 |
|
|
//// ////
|
| 1347 |
|
|
//// ////
|
| 1348 |
|
|
//// To Do: ////
|
| 1349 |
|
|
//// - ////
|
| 1350 |
|
|
//// ////
|
| 1351 |
|
|
//// Author(s): ////
|
| 1352 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 1353 |
|
|
//// ORSoC AB ////
|
| 1354 |
|
|
//// ////
|
| 1355 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 1356 |
|
|
//// ////
|
| 1357 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
| 1358 |
|
|
//// ////
|
| 1359 |
|
|
//// This source file may be used and distributed without ////
|
| 1360 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 1361 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 1362 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 1363 |
|
|
//// ////
|
| 1364 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 1365 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 1366 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 1367 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 1368 |
|
|
//// later version. ////
|
| 1369 |
|
|
//// ////
|
| 1370 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 1371 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 1372 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 1373 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 1374 |
|
|
//// details. ////
|
| 1375 |
|
|
//// ////
|
| 1376 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 1377 |
|
|
//// Public License along with this source; if not, download it ////
|
| 1378 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 1379 |
|
|
//// ////
|
| 1380 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 1381 |
40 |
unneback |
`ifdef MUX_ANDOR
|
| 1382 |
|
|
`define MODULE mux_andor
|
| 1383 |
|
|
module `BASE`MODULE ( a, sel, dout);
|
| 1384 |
|
|
`undef MODULE
|
| 1385 |
36 |
unneback |
|
| 1386 |
|
|
parameter width = 32;
|
| 1387 |
|
|
parameter nr_of_ports = 4;
|
| 1388 |
|
|
|
| 1389 |
|
|
input [nr_of_ports*width-1:0] a;
|
| 1390 |
|
|
input [nr_of_ports-1:0] sel;
|
| 1391 |
|
|
output reg [width-1:0] dout;
|
| 1392 |
|
|
|
| 1393 |
38 |
unneback |
integer i,j;
|
| 1394 |
|
|
|
| 1395 |
36 |
unneback |
always @ (a, sel)
|
| 1396 |
|
|
begin
|
| 1397 |
|
|
dout = a[width-1:0] & {width{sel[0]}};
|
| 1398 |
42 |
unneback |
for (i=1;i<nr_of_ports;i=i+1)
|
| 1399 |
|
|
for (j=0;j<width;j=j+1)
|
| 1400 |
|
|
dout[j] = (a[i*width + j] & sel[i]) | dout[j];
|
| 1401 |
36 |
unneback |
end
|
| 1402 |
|
|
|
| 1403 |
|
|
endmodule
|
| 1404 |
40 |
unneback |
`endif
|
| 1405 |
36 |
unneback |
|
| 1406 |
40 |
unneback |
`ifdef MUX2_ANDOR
|
| 1407 |
|
|
`define MODULE mux2_andor
|
| 1408 |
|
|
module `BASE`MODULE ( a1, a0, sel, dout);
|
| 1409 |
|
|
`undef MODULE
|
| 1410 |
18 |
unneback |
|
| 1411 |
34 |
unneback |
parameter width = 32;
|
| 1412 |
35 |
unneback |
localparam nr_of_ports = 2;
|
| 1413 |
34 |
unneback |
input [width-1:0] a1, a0;
|
| 1414 |
|
|
input [nr_of_ports-1:0] sel;
|
| 1415 |
|
|
output [width-1:0] dout;
|
| 1416 |
|
|
|
| 1417 |
40 |
unneback |
`define MODULE mux_andor
|
| 1418 |
|
|
`BASE`MODULE
|
| 1419 |
38 |
unneback |
# ( .width(width), .nr_of_ports(nr_of_ports))
|
| 1420 |
36 |
unneback |
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
|
| 1421 |
40 |
unneback |
`undef MODULE
|
| 1422 |
|
|
|
| 1423 |
34 |
unneback |
endmodule
|
| 1424 |
40 |
unneback |
`endif
|
| 1425 |
34 |
unneback |
|
| 1426 |
40 |
unneback |
`ifdef MUX3_ANDOR
|
| 1427 |
|
|
`define MODULE mux3_andor
|
| 1428 |
|
|
module `BASE`MODULE ( a2, a1, a0, sel, dout);
|
| 1429 |
|
|
`undef MODULE
|
| 1430 |
34 |
unneback |
|
| 1431 |
|
|
parameter width = 32;
|
| 1432 |
35 |
unneback |
localparam nr_of_ports = 3;
|
| 1433 |
34 |
unneback |
input [width-1:0] a2, a1, a0;
|
| 1434 |
|
|
input [nr_of_ports-1:0] sel;
|
| 1435 |
|
|
output [width-1:0] dout;
|
| 1436 |
|
|
|
| 1437 |
40 |
unneback |
`define MODULE mux_andor
|
| 1438 |
|
|
`BASE`MODULE
|
| 1439 |
38 |
unneback |
# ( .width(width), .nr_of_ports(nr_of_ports))
|
| 1440 |
36 |
unneback |
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
|
| 1441 |
40 |
unneback |
`undef MODULE
|
| 1442 |
34 |
unneback |
endmodule
|
| 1443 |
40 |
unneback |
`endif
|
| 1444 |
34 |
unneback |
|
| 1445 |
40 |
unneback |
`ifdef MUX4_ANDOR
|
| 1446 |
|
|
`define MODULE mux4_andor
|
| 1447 |
|
|
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
|
| 1448 |
|
|
`undef MODULE
|
| 1449 |
18 |
unneback |
|
| 1450 |
|
|
parameter width = 32;
|
| 1451 |
35 |
unneback |
localparam nr_of_ports = 4;
|
| 1452 |
18 |
unneback |
input [width-1:0] a3, a2, a1, a0;
|
| 1453 |
|
|
input [nr_of_ports-1:0] sel;
|
| 1454 |
22 |
unneback |
output [width-1:0] dout;
|
| 1455 |
18 |
unneback |
|
| 1456 |
40 |
unneback |
`define MODULE mux_andor
|
| 1457 |
|
|
`BASE`MODULE
|
| 1458 |
38 |
unneback |
# ( .width(width), .nr_of_ports(nr_of_ports))
|
| 1459 |
36 |
unneback |
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
| 1460 |
40 |
unneback |
`undef MODULE
|
| 1461 |
18 |
unneback |
|
| 1462 |
|
|
endmodule
|
| 1463 |
40 |
unneback |
`endif
|
| 1464 |
18 |
unneback |
|
| 1465 |
40 |
unneback |
`ifdef MUX5_ANDOR
|
| 1466 |
|
|
`define MODULE mux5_andor
|
| 1467 |
|
|
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
|
| 1468 |
|
|
`undef MODULE
|
| 1469 |
18 |
unneback |
|
| 1470 |
|
|
parameter width = 32;
|
| 1471 |
35 |
unneback |
localparam nr_of_ports = 5;
|
| 1472 |
18 |
unneback |
input [width-1:0] a4, a3, a2, a1, a0;
|
| 1473 |
|
|
input [nr_of_ports-1:0] sel;
|
| 1474 |
22 |
unneback |
output [width-1:0] dout;
|
| 1475 |
18 |
unneback |
|
| 1476 |
40 |
unneback |
`define MODULE mux_andor
|
| 1477 |
|
|
`BASE`MODULE
|
| 1478 |
38 |
unneback |
# ( .width(width), .nr_of_ports(nr_of_ports))
|
| 1479 |
36 |
unneback |
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
| 1480 |
40 |
unneback |
`undef MODULE
|
| 1481 |
18 |
unneback |
|
| 1482 |
|
|
endmodule
|
| 1483 |
40 |
unneback |
`endif
|
| 1484 |
18 |
unneback |
|
| 1485 |
40 |
unneback |
`ifdef MUX6_ANDOR
|
| 1486 |
|
|
`define MODULE mux6_andor
|
| 1487 |
|
|
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
|
| 1488 |
|
|
`undef MODULE
|
| 1489 |
18 |
unneback |
|
| 1490 |
|
|
parameter width = 32;
|
| 1491 |
35 |
unneback |
localparam nr_of_ports = 6;
|
| 1492 |
18 |
unneback |
input [width-1:0] a5, a4, a3, a2, a1, a0;
|
| 1493 |
|
|
input [nr_of_ports-1:0] sel;
|
| 1494 |
22 |
unneback |
output [width-1:0] dout;
|
| 1495 |
18 |
unneback |
|
| 1496 |
40 |
unneback |
`define MODULE mux_andor
|
| 1497 |
|
|
`BASE`MODULE
|
| 1498 |
38 |
unneback |
# ( .width(width), .nr_of_ports(nr_of_ports))
|
| 1499 |
36 |
unneback |
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
| 1500 |
40 |
unneback |
`undef MODULE
|
| 1501 |
18 |
unneback |
|
| 1502 |
|
|
endmodule
|
| 1503 |
40 |
unneback |
`endif
|
| 1504 |
43 |
unneback |
|
| 1505 |
|
|
`ifdef PARITY
|
| 1506 |
|
|
|
| 1507 |
|
|
`define MODULE parity_generate
|
| 1508 |
|
|
module `BASE`MODULE (data, parity);
|
| 1509 |
|
|
`undef MODULE
|
| 1510 |
|
|
parameter word_size = 32;
|
| 1511 |
|
|
parameter chunk_size = 8;
|
| 1512 |
|
|
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
|
| 1513 |
|
|
input [word_size-1:0] data;
|
| 1514 |
|
|
output reg [word_size/chunk_size-1:0] parity;
|
| 1515 |
|
|
integer i,j;
|
| 1516 |
|
|
always @ (data)
|
| 1517 |
|
|
for (i=0;i<word_size/chunk_size;i=i+1) begin
|
| 1518 |
|
|
parity[i] = parity_type;
|
| 1519 |
|
|
for (j=0;j<chunk_size;j=j+1) begin
|
| 1520 |
46 |
unneback |
parity[i] = data[i*chunk_size+j] ^ parity[i];
|
| 1521 |
43 |
unneback |
end
|
| 1522 |
|
|
end
|
| 1523 |
|
|
endmodule
|
| 1524 |
|
|
|
| 1525 |
|
|
`define MODULE parity_check
|
| 1526 |
|
|
module `BASE`MODULE( data, parity, parity_error);
|
| 1527 |
|
|
`undef MODULE
|
| 1528 |
|
|
parameter word_size = 32;
|
| 1529 |
|
|
parameter chunk_size = 8;
|
| 1530 |
|
|
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
|
| 1531 |
|
|
input [word_size-1:0] data;
|
| 1532 |
|
|
input [word_size/chunk_size-1:0] parity;
|
| 1533 |
|
|
output parity_error;
|
| 1534 |
44 |
unneback |
reg [word_size/chunk_size-1:0] error_flag;
|
| 1535 |
43 |
unneback |
integer i,j;
|
| 1536 |
|
|
always @ (data or parity)
|
| 1537 |
|
|
for (i=0;i<word_size/chunk_size;i=i+1) begin
|
| 1538 |
|
|
error_flag[i] = parity[i] ^ parity_type;
|
| 1539 |
|
|
for (j=0;j<chunk_size;j=j+1) begin
|
| 1540 |
46 |
unneback |
error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
|
| 1541 |
43 |
unneback |
end
|
| 1542 |
|
|
end
|
| 1543 |
|
|
assign parity_error = |error_flag;
|
| 1544 |
|
|
endmodule
|
| 1545 |
|
|
|
| 1546 |
44 |
unneback |
`endif//////////////////////////////////////////////////////////////////////
|
| 1547 |
|
|
//// ////
|
| 1548 |
|
|
//// IO functions ////
|
| 1549 |
|
|
//// ////
|
| 1550 |
|
|
//// Description ////
|
| 1551 |
|
|
//// IO functions such as IOB flip-flops ////
|
| 1552 |
|
|
//// ////
|
| 1553 |
|
|
//// ////
|
| 1554 |
|
|
//// To Do: ////
|
| 1555 |
|
|
//// - ////
|
| 1556 |
|
|
//// ////
|
| 1557 |
|
|
//// Author(s): ////
|
| 1558 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 1559 |
|
|
//// ORSoC AB ////
|
| 1560 |
|
|
//// ////
|
| 1561 |
18 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 1562 |
|
|
//// ////
|
| 1563 |
44 |
unneback |
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
| 1564 |
|
|
//// ////
|
| 1565 |
|
|
//// This source file may be used and distributed without ////
|
| 1566 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 1567 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 1568 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 1569 |
|
|
//// ////
|
| 1570 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 1571 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 1572 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 1573 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 1574 |
|
|
//// later version. ////
|
| 1575 |
|
|
//// ////
|
| 1576 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 1577 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 1578 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 1579 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 1580 |
|
|
//// details. ////
|
| 1581 |
|
|
//// ////
|
| 1582 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 1583 |
|
|
//// Public License along with this source; if not, download it ////
|
| 1584 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 1585 |
|
|
//// ////
|
| 1586 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 1587 |
45 |
unneback |
`timescale 1ns/1ns
|
| 1588 |
44 |
unneback |
`ifdef O_DFF
|
| 1589 |
|
|
`define MODULE o_dff
|
| 1590 |
|
|
module `BASE`MODULE (d_i, o_pad, clk, rst);
|
| 1591 |
|
|
`undef MODULE
|
| 1592 |
|
|
parameter width = 1;
|
| 1593 |
45 |
unneback |
parameter reset_value = {width{1'b0}};
|
| 1594 |
|
|
input [width-1:0] d_i;
|
| 1595 |
44 |
unneback |
output [width-1:0] o_pad;
|
| 1596 |
|
|
input clk, rst;
|
| 1597 |
|
|
wire [width-1:0] d_i_int `SYN_KEEP;
|
| 1598 |
45 |
unneback |
reg [width-1:0] o_pad_int;
|
| 1599 |
44 |
unneback |
assign d_i_int = d_i;
|
| 1600 |
|
|
genvar i;
|
| 1601 |
45 |
unneback |
generate
|
| 1602 |
44 |
unneback |
for (i=0;i<width;i=i+1) begin
|
| 1603 |
|
|
always @ (posedge clk or posedge rst)
|
| 1604 |
|
|
if (rst)
|
| 1605 |
45 |
unneback |
o_pad_int[i] <= reset_value[i];
|
| 1606 |
44 |
unneback |
else
|
| 1607 |
45 |
unneback |
o_pad_int[i] <= d_i_int[i];
|
| 1608 |
|
|
assign #1 o_pad[i] = o_pad_int[i];
|
| 1609 |
44 |
unneback |
end
|
| 1610 |
|
|
endgenerate
|
| 1611 |
|
|
endmodule
|
| 1612 |
|
|
`endif
|
| 1613 |
|
|
|
| 1614 |
45 |
unneback |
`timescale 1ns/1ns
|
| 1615 |
44 |
unneback |
`ifdef IO_DFF_OE
|
| 1616 |
|
|
`define MODULE io_dff_oe
|
| 1617 |
|
|
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
|
| 1618 |
|
|
`undef MODULE
|
| 1619 |
|
|
parameter width = 1;
|
| 1620 |
|
|
input [width-1:0] d_o;
|
| 1621 |
|
|
output reg [width-1:0] d_i;
|
| 1622 |
|
|
input oe;
|
| 1623 |
|
|
inout [width-1:0] io_pad;
|
| 1624 |
|
|
input clk, rst;
|
| 1625 |
|
|
wire [width-1:0] oe_d `SYN_KEEP;
|
| 1626 |
|
|
reg [width-1:0] oe_q;
|
| 1627 |
|
|
reg [width-1:0] d_o_q;
|
| 1628 |
|
|
assign oe_d = {width{oe}};
|
| 1629 |
|
|
genvar i;
|
| 1630 |
|
|
generate
|
| 1631 |
|
|
for (i=0;i<width;i=i+1) begin
|
| 1632 |
|
|
always @ (posedge clk or posedge rst)
|
| 1633 |
|
|
if (rst)
|
| 1634 |
|
|
oe_q[i] <= 1'b0;
|
| 1635 |
|
|
else
|
| 1636 |
|
|
oe_q[i] <= oe_d[i];
|
| 1637 |
|
|
always @ (posedge clk or posedge rst)
|
| 1638 |
|
|
if (rst)
|
| 1639 |
|
|
d_o_q[i] <= 1'b0;
|
| 1640 |
|
|
else
|
| 1641 |
|
|
d_o_q[i] <= d_o[i];
|
| 1642 |
|
|
always @ (posedge clk or posedge rst)
|
| 1643 |
|
|
if (rst)
|
| 1644 |
|
|
d_i[i] <= 1'b0;
|
| 1645 |
|
|
else
|
| 1646 |
|
|
d_i[i] <= io_pad[i];
|
| 1647 |
45 |
unneback |
assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
|
| 1648 |
44 |
unneback |
end
|
| 1649 |
|
|
endgenerate
|
| 1650 |
|
|
endmodule
|
| 1651 |
|
|
`endif
|
| 1652 |
|
|
`ifdef CNT_BIN
|
| 1653 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 1654 |
|
|
//// ////
|
| 1655 |
6 |
unneback |
//// Versatile counter ////
|
| 1656 |
|
|
//// ////
|
| 1657 |
|
|
//// Description ////
|
| 1658 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 1659 |
|
|
//// counter ////
|
| 1660 |
|
|
//// ////
|
| 1661 |
|
|
//// To Do: ////
|
| 1662 |
|
|
//// - add LFSR with more taps ////
|
| 1663 |
|
|
//// ////
|
| 1664 |
|
|
//// Author(s): ////
|
| 1665 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 1666 |
|
|
//// ORSoC AB ////
|
| 1667 |
|
|
//// ////
|
| 1668 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 1669 |
|
|
//// ////
|
| 1670 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 1671 |
|
|
//// ////
|
| 1672 |
|
|
//// This source file may be used and distributed without ////
|
| 1673 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 1674 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 1675 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 1676 |
|
|
//// ////
|
| 1677 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 1678 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 1679 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 1680 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 1681 |
|
|
//// later version. ////
|
| 1682 |
|
|
//// ////
|
| 1683 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 1684 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 1685 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 1686 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 1687 |
|
|
//// details. ////
|
| 1688 |
|
|
//// ////
|
| 1689 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 1690 |
|
|
//// Public License along with this source; if not, download it ////
|
| 1691 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 1692 |
|
|
//// ////
|
| 1693 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 1694 |
|
|
|
| 1695 |
|
|
// binary counter
|
| 1696 |
22 |
unneback |
|
| 1697 |
40 |
unneback |
`define MODULE cnt_bin
|
| 1698 |
|
|
module `BASE`MODULE (
|
| 1699 |
|
|
`undef MODULE
|
| 1700 |
|
|
q, rst, clk);
|
| 1701 |
|
|
|
| 1702 |
22 |
unneback |
parameter length = 4;
|
| 1703 |
|
|
output [length:1] q;
|
| 1704 |
|
|
input rst;
|
| 1705 |
|
|
input clk;
|
| 1706 |
|
|
|
| 1707 |
|
|
parameter clear_value = 0;
|
| 1708 |
|
|
parameter set_value = 1;
|
| 1709 |
|
|
parameter wrap_value = 0;
|
| 1710 |
|
|
parameter level1_value = 15;
|
| 1711 |
|
|
|
| 1712 |
|
|
reg [length:1] qi;
|
| 1713 |
|
|
wire [length:1] q_next;
|
| 1714 |
|
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
| 1715 |
|
|
|
| 1716 |
|
|
always @ (posedge clk or posedge rst)
|
| 1717 |
|
|
if (rst)
|
| 1718 |
|
|
qi <= {length{1'b0}};
|
| 1719 |
|
|
else
|
| 1720 |
|
|
qi <= q_next;
|
| 1721 |
|
|
|
| 1722 |
|
|
assign q = qi;
|
| 1723 |
|
|
|
| 1724 |
|
|
endmodule
|
| 1725 |
40 |
unneback |
`endif
|
| 1726 |
|
|
`ifdef CNT_BIN_CLEAR
|
| 1727 |
22 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 1728 |
|
|
//// ////
|
| 1729 |
|
|
//// Versatile counter ////
|
| 1730 |
|
|
//// ////
|
| 1731 |
|
|
//// Description ////
|
| 1732 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 1733 |
|
|
//// counter ////
|
| 1734 |
|
|
//// ////
|
| 1735 |
|
|
//// To Do: ////
|
| 1736 |
|
|
//// - add LFSR with more taps ////
|
| 1737 |
|
|
//// ////
|
| 1738 |
|
|
//// Author(s): ////
|
| 1739 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 1740 |
|
|
//// ORSoC AB ////
|
| 1741 |
|
|
//// ////
|
| 1742 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 1743 |
|
|
//// ////
|
| 1744 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 1745 |
|
|
//// ////
|
| 1746 |
|
|
//// This source file may be used and distributed without ////
|
| 1747 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 1748 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 1749 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 1750 |
|
|
//// ////
|
| 1751 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 1752 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 1753 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 1754 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 1755 |
|
|
//// later version. ////
|
| 1756 |
|
|
//// ////
|
| 1757 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 1758 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 1759 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 1760 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 1761 |
|
|
//// details. ////
|
| 1762 |
|
|
//// ////
|
| 1763 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 1764 |
|
|
//// Public License along with this source; if not, download it ////
|
| 1765 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 1766 |
|
|
//// ////
|
| 1767 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 1768 |
|
|
|
| 1769 |
|
|
// binary counter
|
| 1770 |
|
|
|
| 1771 |
40 |
unneback |
`define MODULE cnt_bin_clear
|
| 1772 |
|
|
module `BASE`MODULE (
|
| 1773 |
|
|
`undef MODULE
|
| 1774 |
|
|
clear, q, rst, clk);
|
| 1775 |
|
|
|
| 1776 |
22 |
unneback |
parameter length = 4;
|
| 1777 |
|
|
input clear;
|
| 1778 |
|
|
output [length:1] q;
|
| 1779 |
|
|
input rst;
|
| 1780 |
|
|
input clk;
|
| 1781 |
|
|
|
| 1782 |
|
|
parameter clear_value = 0;
|
| 1783 |
|
|
parameter set_value = 1;
|
| 1784 |
|
|
parameter wrap_value = 0;
|
| 1785 |
|
|
parameter level1_value = 15;
|
| 1786 |
|
|
|
| 1787 |
|
|
reg [length:1] qi;
|
| 1788 |
|
|
wire [length:1] q_next;
|
| 1789 |
|
|
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
|
| 1790 |
|
|
|
| 1791 |
|
|
always @ (posedge clk or posedge rst)
|
| 1792 |
|
|
if (rst)
|
| 1793 |
|
|
qi <= {length{1'b0}};
|
| 1794 |
|
|
else
|
| 1795 |
|
|
qi <= q_next;
|
| 1796 |
|
|
|
| 1797 |
|
|
assign q = qi;
|
| 1798 |
|
|
|
| 1799 |
|
|
endmodule
|
| 1800 |
40 |
unneback |
`endif
|
| 1801 |
|
|
`ifdef CNT_BIN_CE
|
| 1802 |
22 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 1803 |
|
|
//// ////
|
| 1804 |
|
|
//// Versatile counter ////
|
| 1805 |
|
|
//// ////
|
| 1806 |
|
|
//// Description ////
|
| 1807 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 1808 |
|
|
//// counter ////
|
| 1809 |
|
|
//// ////
|
| 1810 |
|
|
//// To Do: ////
|
| 1811 |
|
|
//// - add LFSR with more taps ////
|
| 1812 |
|
|
//// ////
|
| 1813 |
|
|
//// Author(s): ////
|
| 1814 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 1815 |
|
|
//// ORSoC AB ////
|
| 1816 |
|
|
//// ////
|
| 1817 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 1818 |
|
|
//// ////
|
| 1819 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 1820 |
|
|
//// ////
|
| 1821 |
|
|
//// This source file may be used and distributed without ////
|
| 1822 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 1823 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 1824 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 1825 |
|
|
//// ////
|
| 1826 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 1827 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 1828 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 1829 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 1830 |
|
|
//// later version. ////
|
| 1831 |
|
|
//// ////
|
| 1832 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 1833 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 1834 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 1835 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 1836 |
|
|
//// details. ////
|
| 1837 |
|
|
//// ////
|
| 1838 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 1839 |
|
|
//// Public License along with this source; if not, download it ////
|
| 1840 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 1841 |
|
|
//// ////
|
| 1842 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 1843 |
|
|
|
| 1844 |
|
|
// binary counter
|
| 1845 |
6 |
unneback |
|
| 1846 |
40 |
unneback |
`define MODULE cnt_bin_ce
|
| 1847 |
|
|
module `BASE`MODULE (
|
| 1848 |
|
|
`undef MODULE
|
| 1849 |
|
|
cke, q, rst, clk);
|
| 1850 |
|
|
|
| 1851 |
6 |
unneback |
parameter length = 4;
|
| 1852 |
|
|
input cke;
|
| 1853 |
|
|
output [length:1] q;
|
| 1854 |
|
|
input rst;
|
| 1855 |
|
|
input clk;
|
| 1856 |
|
|
|
| 1857 |
|
|
parameter clear_value = 0;
|
| 1858 |
|
|
parameter set_value = 1;
|
| 1859 |
|
|
parameter wrap_value = 0;
|
| 1860 |
|
|
parameter level1_value = 15;
|
| 1861 |
|
|
|
| 1862 |
|
|
reg [length:1] qi;
|
| 1863 |
|
|
wire [length:1] q_next;
|
| 1864 |
|
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
| 1865 |
|
|
|
| 1866 |
|
|
always @ (posedge clk or posedge rst)
|
| 1867 |
|
|
if (rst)
|
| 1868 |
|
|
qi <= {length{1'b0}};
|
| 1869 |
|
|
else
|
| 1870 |
|
|
if (cke)
|
| 1871 |
|
|
qi <= q_next;
|
| 1872 |
|
|
|
| 1873 |
|
|
assign q = qi;
|
| 1874 |
|
|
|
| 1875 |
|
|
endmodule
|
| 1876 |
40 |
unneback |
`endif
|
| 1877 |
|
|
`ifdef CNT_BIN_CE_CLEAR
|
| 1878 |
6 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 1879 |
|
|
//// ////
|
| 1880 |
|
|
//// Versatile counter ////
|
| 1881 |
|
|
//// ////
|
| 1882 |
|
|
//// Description ////
|
| 1883 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 1884 |
|
|
//// counter ////
|
| 1885 |
|
|
//// ////
|
| 1886 |
|
|
//// To Do: ////
|
| 1887 |
|
|
//// - add LFSR with more taps ////
|
| 1888 |
|
|
//// ////
|
| 1889 |
|
|
//// Author(s): ////
|
| 1890 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 1891 |
|
|
//// ORSoC AB ////
|
| 1892 |
|
|
//// ////
|
| 1893 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 1894 |
|
|
//// ////
|
| 1895 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 1896 |
|
|
//// ////
|
| 1897 |
|
|
//// This source file may be used and distributed without ////
|
| 1898 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 1899 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 1900 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 1901 |
|
|
//// ////
|
| 1902 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 1903 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 1904 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 1905 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 1906 |
|
|
//// later version. ////
|
| 1907 |
|
|
//// ////
|
| 1908 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 1909 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 1910 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 1911 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 1912 |
|
|
//// details. ////
|
| 1913 |
|
|
//// ////
|
| 1914 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 1915 |
|
|
//// Public License along with this source; if not, download it ////
|
| 1916 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 1917 |
|
|
//// ////
|
| 1918 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 1919 |
|
|
|
| 1920 |
|
|
// binary counter
|
| 1921 |
|
|
|
| 1922 |
40 |
unneback |
`define MODULE cnt_bin_ce_clear
|
| 1923 |
|
|
module `BASE`MODULE (
|
| 1924 |
|
|
`undef MODULE
|
| 1925 |
|
|
clear, cke, q, rst, clk);
|
| 1926 |
|
|
|
| 1927 |
6 |
unneback |
parameter length = 4;
|
| 1928 |
|
|
input clear;
|
| 1929 |
|
|
input cke;
|
| 1930 |
|
|
output [length:1] q;
|
| 1931 |
|
|
input rst;
|
| 1932 |
|
|
input clk;
|
| 1933 |
|
|
|
| 1934 |
|
|
parameter clear_value = 0;
|
| 1935 |
|
|
parameter set_value = 1;
|
| 1936 |
|
|
parameter wrap_value = 0;
|
| 1937 |
|
|
parameter level1_value = 15;
|
| 1938 |
|
|
|
| 1939 |
|
|
reg [length:1] qi;
|
| 1940 |
|
|
wire [length:1] q_next;
|
| 1941 |
|
|
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
|
| 1942 |
|
|
|
| 1943 |
|
|
always @ (posedge clk or posedge rst)
|
| 1944 |
|
|
if (rst)
|
| 1945 |
|
|
qi <= {length{1'b0}};
|
| 1946 |
|
|
else
|
| 1947 |
|
|
if (cke)
|
| 1948 |
|
|
qi <= q_next;
|
| 1949 |
|
|
|
| 1950 |
|
|
assign q = qi;
|
| 1951 |
|
|
|
| 1952 |
|
|
endmodule
|
| 1953 |
40 |
unneback |
`endif
|
| 1954 |
|
|
`ifdef CNT_BIN_CE_CLEAR_L1_L2
|
| 1955 |
6 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 1956 |
|
|
//// ////
|
| 1957 |
|
|
//// Versatile counter ////
|
| 1958 |
|
|
//// ////
|
| 1959 |
|
|
//// Description ////
|
| 1960 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 1961 |
|
|
//// counter ////
|
| 1962 |
|
|
//// ////
|
| 1963 |
|
|
//// To Do: ////
|
| 1964 |
|
|
//// - add LFSR with more taps ////
|
| 1965 |
|
|
//// ////
|
| 1966 |
|
|
//// Author(s): ////
|
| 1967 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 1968 |
|
|
//// ORSoC AB ////
|
| 1969 |
|
|
//// ////
|
| 1970 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 1971 |
|
|
//// ////
|
| 1972 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 1973 |
|
|
//// ////
|
| 1974 |
|
|
//// This source file may be used and distributed without ////
|
| 1975 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 1976 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 1977 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 1978 |
|
|
//// ////
|
| 1979 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 1980 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 1981 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 1982 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 1983 |
|
|
//// later version. ////
|
| 1984 |
|
|
//// ////
|
| 1985 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 1986 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 1987 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 1988 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 1989 |
|
|
//// details. ////
|
| 1990 |
|
|
//// ////
|
| 1991 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 1992 |
|
|
//// Public License along with this source; if not, download it ////
|
| 1993 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 1994 |
|
|
//// ////
|
| 1995 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 1996 |
|
|
|
| 1997 |
|
|
// binary counter
|
| 1998 |
29 |
unneback |
|
| 1999 |
40 |
unneback |
`define MODULE cnt_bin_ce_clear_l1_l2
|
| 2000 |
|
|
module `BASE`MODULE (
|
| 2001 |
|
|
`undef MODULE
|
| 2002 |
|
|
clear, cke, q, level1, level2, rst, clk);
|
| 2003 |
|
|
|
| 2004 |
29 |
unneback |
parameter length = 4;
|
| 2005 |
|
|
input clear;
|
| 2006 |
|
|
input cke;
|
| 2007 |
|
|
output [length:1] q;
|
| 2008 |
|
|
output reg level1;
|
| 2009 |
|
|
output reg level2;
|
| 2010 |
|
|
input rst;
|
| 2011 |
|
|
input clk;
|
| 2012 |
|
|
|
| 2013 |
|
|
parameter clear_value = 0;
|
| 2014 |
|
|
parameter set_value = 1;
|
| 2015 |
30 |
unneback |
parameter wrap_value = 15;
|
| 2016 |
|
|
parameter level1_value = 8;
|
| 2017 |
|
|
parameter level2_value = 15;
|
| 2018 |
29 |
unneback |
|
| 2019 |
|
|
wire rew;
|
| 2020 |
30 |
unneback |
assign rew = 1'b0;
|
| 2021 |
29 |
unneback |
reg [length:1] qi;
|
| 2022 |
|
|
wire [length:1] q_next;
|
| 2023 |
|
|
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
|
| 2024 |
|
|
|
| 2025 |
|
|
always @ (posedge clk or posedge rst)
|
| 2026 |
|
|
if (rst)
|
| 2027 |
|
|
qi <= {length{1'b0}};
|
| 2028 |
|
|
else
|
| 2029 |
|
|
if (cke)
|
| 2030 |
|
|
qi <= q_next;
|
| 2031 |
|
|
|
| 2032 |
|
|
assign q = qi;
|
| 2033 |
|
|
|
| 2034 |
|
|
|
| 2035 |
|
|
always @ (posedge clk or posedge rst)
|
| 2036 |
|
|
if (rst)
|
| 2037 |
|
|
level1 <= 1'b0;
|
| 2038 |
|
|
else
|
| 2039 |
|
|
if (cke)
|
| 2040 |
|
|
if (clear)
|
| 2041 |
|
|
level1 <= 1'b0;
|
| 2042 |
|
|
else if (q_next == level1_value)
|
| 2043 |
|
|
level1 <= 1'b1;
|
| 2044 |
|
|
else if (qi == level1_value & rew)
|
| 2045 |
|
|
level1 <= 1'b0;
|
| 2046 |
|
|
|
| 2047 |
|
|
always @ (posedge clk or posedge rst)
|
| 2048 |
|
|
if (rst)
|
| 2049 |
|
|
level2 <= 1'b0;
|
| 2050 |
|
|
else
|
| 2051 |
|
|
if (cke)
|
| 2052 |
|
|
if (clear)
|
| 2053 |
|
|
level2 <= 1'b0;
|
| 2054 |
|
|
else if (q_next == level2_value)
|
| 2055 |
|
|
level2 <= 1'b1;
|
| 2056 |
|
|
else if (qi == level2_value & rew)
|
| 2057 |
|
|
level2 <= 1'b0;
|
| 2058 |
|
|
endmodule
|
| 2059 |
40 |
unneback |
`endif
|
| 2060 |
|
|
`ifdef CNT_BIN_CE_CLEAR_SET_REW
|
| 2061 |
29 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 2062 |
|
|
//// ////
|
| 2063 |
|
|
//// Versatile counter ////
|
| 2064 |
|
|
//// ////
|
| 2065 |
|
|
//// Description ////
|
| 2066 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 2067 |
|
|
//// counter ////
|
| 2068 |
|
|
//// ////
|
| 2069 |
|
|
//// To Do: ////
|
| 2070 |
|
|
//// - add LFSR with more taps ////
|
| 2071 |
|
|
//// ////
|
| 2072 |
|
|
//// Author(s): ////
|
| 2073 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 2074 |
|
|
//// ORSoC AB ////
|
| 2075 |
|
|
//// ////
|
| 2076 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2077 |
|
|
//// ////
|
| 2078 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 2079 |
|
|
//// ////
|
| 2080 |
|
|
//// This source file may be used and distributed without ////
|
| 2081 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 2082 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 2083 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 2084 |
|
|
//// ////
|
| 2085 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 2086 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 2087 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 2088 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 2089 |
|
|
//// later version. ////
|
| 2090 |
|
|
//// ////
|
| 2091 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 2092 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 2093 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 2094 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 2095 |
|
|
//// details. ////
|
| 2096 |
|
|
//// ////
|
| 2097 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 2098 |
|
|
//// Public License along with this source; if not, download it ////
|
| 2099 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 2100 |
|
|
//// ////
|
| 2101 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2102 |
|
|
|
| 2103 |
|
|
// binary counter
|
| 2104 |
6 |
unneback |
|
| 2105 |
40 |
unneback |
`define MODULE cnt_bin_ce_clear_set_rew
|
| 2106 |
|
|
module `BASE`MODULE (
|
| 2107 |
|
|
`undef MODULE
|
| 2108 |
|
|
clear, set, cke, rew, q, rst, clk);
|
| 2109 |
|
|
|
| 2110 |
6 |
unneback |
parameter length = 4;
|
| 2111 |
|
|
input clear;
|
| 2112 |
|
|
input set;
|
| 2113 |
|
|
input cke;
|
| 2114 |
|
|
input rew;
|
| 2115 |
|
|
output [length:1] q;
|
| 2116 |
|
|
input rst;
|
| 2117 |
|
|
input clk;
|
| 2118 |
|
|
|
| 2119 |
|
|
parameter clear_value = 0;
|
| 2120 |
|
|
parameter set_value = 1;
|
| 2121 |
|
|
parameter wrap_value = 0;
|
| 2122 |
|
|
parameter level1_value = 15;
|
| 2123 |
|
|
|
| 2124 |
|
|
reg [length:1] qi;
|
| 2125 |
|
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
| 2126 |
|
|
assign q_next_fw = clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
|
| 2127 |
|
|
assign q_next_rew = clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
|
| 2128 |
|
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
| 2129 |
|
|
|
| 2130 |
|
|
always @ (posedge clk or posedge rst)
|
| 2131 |
|
|
if (rst)
|
| 2132 |
|
|
qi <= {length{1'b0}};
|
| 2133 |
|
|
else
|
| 2134 |
|
|
if (cke)
|
| 2135 |
|
|
qi <= q_next;
|
| 2136 |
|
|
|
| 2137 |
|
|
assign q = qi;
|
| 2138 |
|
|
|
| 2139 |
|
|
endmodule
|
| 2140 |
40 |
unneback |
`endif
|
| 2141 |
|
|
`ifdef CNT_BIN_CE_REW_L1
|
| 2142 |
6 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 2143 |
|
|
//// ////
|
| 2144 |
|
|
//// Versatile counter ////
|
| 2145 |
|
|
//// ////
|
| 2146 |
|
|
//// Description ////
|
| 2147 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 2148 |
|
|
//// counter ////
|
| 2149 |
|
|
//// ////
|
| 2150 |
|
|
//// To Do: ////
|
| 2151 |
|
|
//// - add LFSR with more taps ////
|
| 2152 |
|
|
//// ////
|
| 2153 |
|
|
//// Author(s): ////
|
| 2154 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 2155 |
|
|
//// ORSoC AB ////
|
| 2156 |
|
|
//// ////
|
| 2157 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2158 |
|
|
//// ////
|
| 2159 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 2160 |
|
|
//// ////
|
| 2161 |
|
|
//// This source file may be used and distributed without ////
|
| 2162 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 2163 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 2164 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 2165 |
|
|
//// ////
|
| 2166 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 2167 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 2168 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 2169 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 2170 |
|
|
//// later version. ////
|
| 2171 |
|
|
//// ////
|
| 2172 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 2173 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 2174 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 2175 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 2176 |
|
|
//// details. ////
|
| 2177 |
|
|
//// ////
|
| 2178 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 2179 |
|
|
//// Public License along with this source; if not, download it ////
|
| 2180 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 2181 |
|
|
//// ////
|
| 2182 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2183 |
|
|
|
| 2184 |
|
|
// binary counter
|
| 2185 |
|
|
|
| 2186 |
40 |
unneback |
`define MODULE cnt_bin_ce_rew_l1
|
| 2187 |
|
|
module `BASE`MODULE (
|
| 2188 |
|
|
`undef MODULE
|
| 2189 |
|
|
cke, rew, level1, rst, clk);
|
| 2190 |
|
|
|
| 2191 |
6 |
unneback |
parameter length = 4;
|
| 2192 |
|
|
input cke;
|
| 2193 |
|
|
input rew;
|
| 2194 |
|
|
output reg level1;
|
| 2195 |
|
|
input rst;
|
| 2196 |
|
|
input clk;
|
| 2197 |
|
|
|
| 2198 |
|
|
parameter clear_value = 0;
|
| 2199 |
|
|
parameter set_value = 1;
|
| 2200 |
|
|
parameter wrap_value = 1;
|
| 2201 |
|
|
parameter level1_value = 15;
|
| 2202 |
|
|
|
| 2203 |
29 |
unneback |
wire clear;
|
| 2204 |
30 |
unneback |
assign clear = 1'b0;
|
| 2205 |
6 |
unneback |
reg [length:1] qi;
|
| 2206 |
|
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
| 2207 |
|
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
| 2208 |
|
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
| 2209 |
|
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
| 2210 |
|
|
|
| 2211 |
|
|
always @ (posedge clk or posedge rst)
|
| 2212 |
|
|
if (rst)
|
| 2213 |
|
|
qi <= {length{1'b0}};
|
| 2214 |
|
|
else
|
| 2215 |
|
|
if (cke)
|
| 2216 |
|
|
qi <= q_next;
|
| 2217 |
|
|
|
| 2218 |
|
|
|
| 2219 |
|
|
|
| 2220 |
|
|
always @ (posedge clk or posedge rst)
|
| 2221 |
|
|
if (rst)
|
| 2222 |
|
|
level1 <= 1'b0;
|
| 2223 |
|
|
else
|
| 2224 |
|
|
if (cke)
|
| 2225 |
29 |
unneback |
if (clear)
|
| 2226 |
|
|
level1 <= 1'b0;
|
| 2227 |
|
|
else if (q_next == level1_value)
|
| 2228 |
6 |
unneback |
level1 <= 1'b1;
|
| 2229 |
|
|
else if (qi == level1_value & rew)
|
| 2230 |
|
|
level1 <= 1'b0;
|
| 2231 |
|
|
endmodule
|
| 2232 |
40 |
unneback |
`endif
|
| 2233 |
|
|
`ifdef CNT_BIN_CE_REW_ZQ_L1
|
| 2234 |
6 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 2235 |
|
|
//// ////
|
| 2236 |
|
|
//// Versatile counter ////
|
| 2237 |
|
|
//// ////
|
| 2238 |
|
|
//// Description ////
|
| 2239 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 2240 |
|
|
//// counter ////
|
| 2241 |
|
|
//// ////
|
| 2242 |
|
|
//// To Do: ////
|
| 2243 |
|
|
//// - add LFSR with more taps ////
|
| 2244 |
|
|
//// ////
|
| 2245 |
|
|
//// Author(s): ////
|
| 2246 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 2247 |
|
|
//// ORSoC AB ////
|
| 2248 |
|
|
//// ////
|
| 2249 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2250 |
|
|
//// ////
|
| 2251 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 2252 |
|
|
//// ////
|
| 2253 |
|
|
//// This source file may be used and distributed without ////
|
| 2254 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 2255 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 2256 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 2257 |
|
|
//// ////
|
| 2258 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 2259 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 2260 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 2261 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 2262 |
|
|
//// later version. ////
|
| 2263 |
|
|
//// ////
|
| 2264 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 2265 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 2266 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 2267 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 2268 |
|
|
//// details. ////
|
| 2269 |
|
|
//// ////
|
| 2270 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 2271 |
|
|
//// Public License along with this source; if not, download it ////
|
| 2272 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 2273 |
|
|
//// ////
|
| 2274 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2275 |
|
|
|
| 2276 |
25 |
unneback |
// binary counter
|
| 2277 |
|
|
|
| 2278 |
40 |
unneback |
`define MODULE cnt_bin_ce_rew_zq_l1
|
| 2279 |
|
|
module `BASE`MODULE (
|
| 2280 |
|
|
`undef MODULE
|
| 2281 |
|
|
cke, rew, zq, level1, rst, clk);
|
| 2282 |
|
|
|
| 2283 |
25 |
unneback |
parameter length = 4;
|
| 2284 |
|
|
input cke;
|
| 2285 |
|
|
input rew;
|
| 2286 |
|
|
output reg zq;
|
| 2287 |
|
|
output reg level1;
|
| 2288 |
|
|
input rst;
|
| 2289 |
|
|
input clk;
|
| 2290 |
|
|
|
| 2291 |
|
|
parameter clear_value = 0;
|
| 2292 |
|
|
parameter set_value = 1;
|
| 2293 |
|
|
parameter wrap_value = 1;
|
| 2294 |
|
|
parameter level1_value = 15;
|
| 2295 |
|
|
|
| 2296 |
29 |
unneback |
wire clear;
|
| 2297 |
30 |
unneback |
assign clear = 1'b0;
|
| 2298 |
25 |
unneback |
reg [length:1] qi;
|
| 2299 |
|
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
| 2300 |
|
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
| 2301 |
|
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
| 2302 |
|
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
| 2303 |
|
|
|
| 2304 |
|
|
always @ (posedge clk or posedge rst)
|
| 2305 |
|
|
if (rst)
|
| 2306 |
|
|
qi <= {length{1'b0}};
|
| 2307 |
|
|
else
|
| 2308 |
|
|
if (cke)
|
| 2309 |
|
|
qi <= q_next;
|
| 2310 |
|
|
|
| 2311 |
|
|
|
| 2312 |
|
|
|
| 2313 |
|
|
always @ (posedge clk or posedge rst)
|
| 2314 |
|
|
if (rst)
|
| 2315 |
|
|
zq <= 1'b1;
|
| 2316 |
|
|
else
|
| 2317 |
|
|
if (cke)
|
| 2318 |
|
|
zq <= q_next == {length{1'b0}};
|
| 2319 |
|
|
|
| 2320 |
|
|
always @ (posedge clk or posedge rst)
|
| 2321 |
|
|
if (rst)
|
| 2322 |
|
|
level1 <= 1'b0;
|
| 2323 |
|
|
else
|
| 2324 |
|
|
if (cke)
|
| 2325 |
29 |
unneback |
if (clear)
|
| 2326 |
|
|
level1 <= 1'b0;
|
| 2327 |
|
|
else if (q_next == level1_value)
|
| 2328 |
25 |
unneback |
level1 <= 1'b1;
|
| 2329 |
|
|
else if (qi == level1_value & rew)
|
| 2330 |
|
|
level1 <= 1'b0;
|
| 2331 |
|
|
endmodule
|
| 2332 |
40 |
unneback |
`endif
|
| 2333 |
|
|
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
|
| 2334 |
25 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 2335 |
|
|
//// ////
|
| 2336 |
|
|
//// Versatile counter ////
|
| 2337 |
|
|
//// ////
|
| 2338 |
|
|
//// Description ////
|
| 2339 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 2340 |
|
|
//// counter ////
|
| 2341 |
|
|
//// ////
|
| 2342 |
|
|
//// To Do: ////
|
| 2343 |
|
|
//// - add LFSR with more taps ////
|
| 2344 |
|
|
//// ////
|
| 2345 |
|
|
//// Author(s): ////
|
| 2346 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 2347 |
|
|
//// ORSoC AB ////
|
| 2348 |
|
|
//// ////
|
| 2349 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2350 |
|
|
//// ////
|
| 2351 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 2352 |
|
|
//// ////
|
| 2353 |
|
|
//// This source file may be used and distributed without ////
|
| 2354 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 2355 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 2356 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 2357 |
|
|
//// ////
|
| 2358 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 2359 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 2360 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 2361 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 2362 |
|
|
//// later version. ////
|
| 2363 |
|
|
//// ////
|
| 2364 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 2365 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 2366 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 2367 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 2368 |
|
|
//// details. ////
|
| 2369 |
|
|
//// ////
|
| 2370 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 2371 |
|
|
//// Public License along with this source; if not, download it ////
|
| 2372 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 2373 |
|
|
//// ////
|
| 2374 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2375 |
|
|
|
| 2376 |
|
|
// binary counter
|
| 2377 |
|
|
|
| 2378 |
40 |
unneback |
`define MODULE cnt_bin_ce_rew_q_zq_l1
|
| 2379 |
|
|
module `BASE`MODULE (
|
| 2380 |
|
|
`undef MODULE
|
| 2381 |
|
|
cke, rew, q, zq, level1, rst, clk);
|
| 2382 |
|
|
|
| 2383 |
25 |
unneback |
parameter length = 4;
|
| 2384 |
|
|
input cke;
|
| 2385 |
|
|
input rew;
|
| 2386 |
|
|
output [length:1] q;
|
| 2387 |
|
|
output reg zq;
|
| 2388 |
|
|
output reg level1;
|
| 2389 |
|
|
input rst;
|
| 2390 |
|
|
input clk;
|
| 2391 |
|
|
|
| 2392 |
|
|
parameter clear_value = 0;
|
| 2393 |
|
|
parameter set_value = 1;
|
| 2394 |
|
|
parameter wrap_value = 1;
|
| 2395 |
|
|
parameter level1_value = 15;
|
| 2396 |
|
|
|
| 2397 |
29 |
unneback |
wire clear;
|
| 2398 |
30 |
unneback |
assign clear = 1'b0;
|
| 2399 |
25 |
unneback |
reg [length:1] qi;
|
| 2400 |
|
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
| 2401 |
|
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
| 2402 |
|
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
| 2403 |
|
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
| 2404 |
|
|
|
| 2405 |
|
|
always @ (posedge clk or posedge rst)
|
| 2406 |
|
|
if (rst)
|
| 2407 |
|
|
qi <= {length{1'b0}};
|
| 2408 |
|
|
else
|
| 2409 |
|
|
if (cke)
|
| 2410 |
|
|
qi <= q_next;
|
| 2411 |
|
|
|
| 2412 |
|
|
assign q = qi;
|
| 2413 |
|
|
|
| 2414 |
|
|
|
| 2415 |
|
|
always @ (posedge clk or posedge rst)
|
| 2416 |
|
|
if (rst)
|
| 2417 |
|
|
zq <= 1'b1;
|
| 2418 |
|
|
else
|
| 2419 |
|
|
if (cke)
|
| 2420 |
|
|
zq <= q_next == {length{1'b0}};
|
| 2421 |
|
|
|
| 2422 |
|
|
always @ (posedge clk or posedge rst)
|
| 2423 |
|
|
if (rst)
|
| 2424 |
|
|
level1 <= 1'b0;
|
| 2425 |
|
|
else
|
| 2426 |
|
|
if (cke)
|
| 2427 |
29 |
unneback |
if (clear)
|
| 2428 |
|
|
level1 <= 1'b0;
|
| 2429 |
|
|
else if (q_next == level1_value)
|
| 2430 |
25 |
unneback |
level1 <= 1'b1;
|
| 2431 |
|
|
else if (qi == level1_value & rew)
|
| 2432 |
|
|
level1 <= 1'b0;
|
| 2433 |
|
|
endmodule
|
| 2434 |
40 |
unneback |
`endif
|
| 2435 |
|
|
`ifdef CNT_LFSR_ZQ
|
| 2436 |
25 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 2437 |
|
|
//// ////
|
| 2438 |
|
|
//// Versatile counter ////
|
| 2439 |
|
|
//// ////
|
| 2440 |
|
|
//// Description ////
|
| 2441 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 2442 |
|
|
//// counter ////
|
| 2443 |
|
|
//// ////
|
| 2444 |
|
|
//// To Do: ////
|
| 2445 |
|
|
//// - add LFSR with more taps ////
|
| 2446 |
|
|
//// ////
|
| 2447 |
|
|
//// Author(s): ////
|
| 2448 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 2449 |
|
|
//// ORSoC AB ////
|
| 2450 |
|
|
//// ////
|
| 2451 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2452 |
|
|
//// ////
|
| 2453 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 2454 |
|
|
//// ////
|
| 2455 |
|
|
//// This source file may be used and distributed without ////
|
| 2456 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 2457 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 2458 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 2459 |
|
|
//// ////
|
| 2460 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 2461 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 2462 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 2463 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 2464 |
|
|
//// later version. ////
|
| 2465 |
|
|
//// ////
|
| 2466 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 2467 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 2468 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 2469 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 2470 |
|
|
//// details. ////
|
| 2471 |
|
|
//// ////
|
| 2472 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 2473 |
|
|
//// Public License along with this source; if not, download it ////
|
| 2474 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 2475 |
|
|
//// ////
|
| 2476 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2477 |
|
|
|
| 2478 |
6 |
unneback |
// LFSR counter
|
| 2479 |
|
|
|
| 2480 |
40 |
unneback |
`define MODULE cnt_lfsr_zq
|
| 2481 |
|
|
module `BASE`MODULE (
|
| 2482 |
|
|
`undef MODULE
|
| 2483 |
|
|
zq, rst, clk);
|
| 2484 |
|
|
|
| 2485 |
6 |
unneback |
parameter length = 4;
|
| 2486 |
|
|
output reg zq;
|
| 2487 |
|
|
input rst;
|
| 2488 |
|
|
input clk;
|
| 2489 |
|
|
|
| 2490 |
|
|
parameter clear_value = 0;
|
| 2491 |
|
|
parameter set_value = 1;
|
| 2492 |
|
|
parameter wrap_value = 8;
|
| 2493 |
|
|
parameter level1_value = 15;
|
| 2494 |
|
|
|
| 2495 |
|
|
reg [length:1] qi;
|
| 2496 |
|
|
reg lfsr_fb;
|
| 2497 |
|
|
wire [length:1] q_next;
|
| 2498 |
|
|
reg [32:1] polynom;
|
| 2499 |
|
|
integer i;
|
| 2500 |
|
|
|
| 2501 |
|
|
always @ (qi)
|
| 2502 |
|
|
begin
|
| 2503 |
|
|
case (length)
|
| 2504 |
|
|
2: polynom = 32'b11; // 0x3
|
| 2505 |
|
|
3: polynom = 32'b110; // 0x6
|
| 2506 |
|
|
4: polynom = 32'b1100; // 0xC
|
| 2507 |
|
|
5: polynom = 32'b10100; // 0x14
|
| 2508 |
|
|
6: polynom = 32'b110000; // 0x30
|
| 2509 |
|
|
7: polynom = 32'b1100000; // 0x60
|
| 2510 |
|
|
8: polynom = 32'b10111000; // 0xb8
|
| 2511 |
|
|
9: polynom = 32'b100010000; // 0x110
|
| 2512 |
|
|
10: polynom = 32'b1001000000; // 0x240
|
| 2513 |
|
|
11: polynom = 32'b10100000000; // 0x500
|
| 2514 |
|
|
12: polynom = 32'b100000101001; // 0x829
|
| 2515 |
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
| 2516 |
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
| 2517 |
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
| 2518 |
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
| 2519 |
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
| 2520 |
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
| 2521 |
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
| 2522 |
37 |
unneback |
20: polynom = 32'b10010000000000000000; // 0x90000
|
| 2523 |
6 |
unneback |
21: polynom = 32'b101000000000000000000; // 0x140000
|
| 2524 |
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
| 2525 |
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
| 2526 |
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
| 2527 |
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
| 2528 |
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
| 2529 |
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
| 2530 |
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
| 2531 |
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
| 2532 |
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
| 2533 |
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
| 2534 |
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
| 2535 |
|
|
default: polynom = 32'b0;
|
| 2536 |
|
|
endcase
|
| 2537 |
|
|
lfsr_fb = qi[length];
|
| 2538 |
|
|
for (i=length-1; i>=1; i=i-1) begin
|
| 2539 |
|
|
if (polynom[i])
|
| 2540 |
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
| 2541 |
|
|
end
|
| 2542 |
|
|
end
|
| 2543 |
|
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
| 2544 |
|
|
|
| 2545 |
|
|
always @ (posedge clk or posedge rst)
|
| 2546 |
|
|
if (rst)
|
| 2547 |
|
|
qi <= {length{1'b0}};
|
| 2548 |
|
|
else
|
| 2549 |
|
|
qi <= q_next;
|
| 2550 |
|
|
|
| 2551 |
|
|
|
| 2552 |
|
|
|
| 2553 |
|
|
always @ (posedge clk or posedge rst)
|
| 2554 |
|
|
if (rst)
|
| 2555 |
|
|
zq <= 1'b1;
|
| 2556 |
|
|
else
|
| 2557 |
|
|
zq <= q_next == {length{1'b0}};
|
| 2558 |
|
|
endmodule
|
| 2559 |
40 |
unneback |
`endif
|
| 2560 |
75 |
unneback |
`ifdef CNT_LFSR_CE
|
| 2561 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2562 |
|
|
//// ////
|
| 2563 |
|
|
//// Versatile counter ////
|
| 2564 |
|
|
//// ////
|
| 2565 |
|
|
//// Description ////
|
| 2566 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 2567 |
|
|
//// counter ////
|
| 2568 |
|
|
//// ////
|
| 2569 |
|
|
//// To Do: ////
|
| 2570 |
|
|
//// - add LFSR with more taps ////
|
| 2571 |
|
|
//// ////
|
| 2572 |
|
|
//// Author(s): ////
|
| 2573 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 2574 |
|
|
//// ORSoC AB ////
|
| 2575 |
|
|
//// ////
|
| 2576 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2577 |
|
|
//// ////
|
| 2578 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 2579 |
|
|
//// ////
|
| 2580 |
|
|
//// This source file may be used and distributed without ////
|
| 2581 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 2582 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 2583 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 2584 |
|
|
//// ////
|
| 2585 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 2586 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 2587 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 2588 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 2589 |
|
|
//// later version. ////
|
| 2590 |
|
|
//// ////
|
| 2591 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 2592 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 2593 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 2594 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 2595 |
|
|
//// details. ////
|
| 2596 |
|
|
//// ////
|
| 2597 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 2598 |
|
|
//// Public License along with this source; if not, download it ////
|
| 2599 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 2600 |
|
|
//// ////
|
| 2601 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2602 |
|
|
|
| 2603 |
|
|
// LFSR counter
|
| 2604 |
|
|
|
| 2605 |
|
|
`define MODULE cnt_lfsr_ce
|
| 2606 |
|
|
module `BASE`MODULE (
|
| 2607 |
|
|
`undef MODULE
|
| 2608 |
|
|
cke, zq, rst, clk);
|
| 2609 |
|
|
|
| 2610 |
|
|
parameter length = 4;
|
| 2611 |
|
|
input cke;
|
| 2612 |
|
|
output reg zq;
|
| 2613 |
|
|
input rst;
|
| 2614 |
|
|
input clk;
|
| 2615 |
|
|
|
| 2616 |
|
|
parameter clear_value = 0;
|
| 2617 |
|
|
parameter set_value = 1;
|
| 2618 |
|
|
parameter wrap_value = 0;
|
| 2619 |
|
|
parameter level1_value = 15;
|
| 2620 |
|
|
|
| 2621 |
|
|
reg [length:1] qi;
|
| 2622 |
|
|
reg lfsr_fb;
|
| 2623 |
|
|
wire [length:1] q_next;
|
| 2624 |
|
|
reg [32:1] polynom;
|
| 2625 |
|
|
integer i;
|
| 2626 |
|
|
|
| 2627 |
|
|
always @ (qi)
|
| 2628 |
|
|
begin
|
| 2629 |
|
|
case (length)
|
| 2630 |
|
|
2: polynom = 32'b11; // 0x3
|
| 2631 |
|
|
3: polynom = 32'b110; // 0x6
|
| 2632 |
|
|
4: polynom = 32'b1100; // 0xC
|
| 2633 |
|
|
5: polynom = 32'b10100; // 0x14
|
| 2634 |
|
|
6: polynom = 32'b110000; // 0x30
|
| 2635 |
|
|
7: polynom = 32'b1100000; // 0x60
|
| 2636 |
|
|
8: polynom = 32'b10111000; // 0xb8
|
| 2637 |
|
|
9: polynom = 32'b100010000; // 0x110
|
| 2638 |
|
|
10: polynom = 32'b1001000000; // 0x240
|
| 2639 |
|
|
11: polynom = 32'b10100000000; // 0x500
|
| 2640 |
|
|
12: polynom = 32'b100000101001; // 0x829
|
| 2641 |
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
| 2642 |
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
| 2643 |
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
| 2644 |
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
| 2645 |
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
| 2646 |
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
| 2647 |
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
| 2648 |
|
|
20: polynom = 32'b10010000000000000000; // 0x90000
|
| 2649 |
|
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
| 2650 |
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
| 2651 |
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
| 2652 |
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
| 2653 |
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
| 2654 |
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
| 2655 |
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
| 2656 |
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
| 2657 |
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
| 2658 |
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
| 2659 |
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
| 2660 |
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
| 2661 |
|
|
default: polynom = 32'b0;
|
| 2662 |
|
|
endcase
|
| 2663 |
|
|
lfsr_fb = qi[length];
|
| 2664 |
|
|
for (i=length-1; i>=1; i=i-1) begin
|
| 2665 |
|
|
if (polynom[i])
|
| 2666 |
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
| 2667 |
|
|
end
|
| 2668 |
|
|
end
|
| 2669 |
|
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
| 2670 |
|
|
|
| 2671 |
|
|
always @ (posedge clk or posedge rst)
|
| 2672 |
|
|
if (rst)
|
| 2673 |
|
|
qi <= {length{1'b0}};
|
| 2674 |
|
|
else
|
| 2675 |
|
|
if (cke)
|
| 2676 |
|
|
qi <= q_next;
|
| 2677 |
|
|
|
| 2678 |
|
|
|
| 2679 |
|
|
|
| 2680 |
|
|
always @ (posedge clk or posedge rst)
|
| 2681 |
|
|
if (rst)
|
| 2682 |
|
|
zq <= 1'b1;
|
| 2683 |
|
|
else
|
| 2684 |
|
|
if (cke)
|
| 2685 |
|
|
zq <= q_next == {length{1'b0}};
|
| 2686 |
|
|
endmodule
|
| 2687 |
|
|
`endif
|
| 2688 |
40 |
unneback |
`ifdef CNT_LFSR_CE_ZQ
|
| 2689 |
6 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 2690 |
|
|
//// ////
|
| 2691 |
|
|
//// Versatile counter ////
|
| 2692 |
|
|
//// ////
|
| 2693 |
|
|
//// Description ////
|
| 2694 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 2695 |
|
|
//// counter ////
|
| 2696 |
|
|
//// ////
|
| 2697 |
|
|
//// To Do: ////
|
| 2698 |
|
|
//// - add LFSR with more taps ////
|
| 2699 |
|
|
//// ////
|
| 2700 |
|
|
//// Author(s): ////
|
| 2701 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 2702 |
|
|
//// ORSoC AB ////
|
| 2703 |
|
|
//// ////
|
| 2704 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2705 |
|
|
//// ////
|
| 2706 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 2707 |
|
|
//// ////
|
| 2708 |
|
|
//// This source file may be used and distributed without ////
|
| 2709 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 2710 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 2711 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 2712 |
|
|
//// ////
|
| 2713 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 2714 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 2715 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 2716 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 2717 |
|
|
//// later version. ////
|
| 2718 |
|
|
//// ////
|
| 2719 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 2720 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 2721 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 2722 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 2723 |
|
|
//// details. ////
|
| 2724 |
|
|
//// ////
|
| 2725 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 2726 |
|
|
//// Public License along with this source; if not, download it ////
|
| 2727 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 2728 |
|
|
//// ////
|
| 2729 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2730 |
|
|
|
| 2731 |
|
|
// LFSR counter
|
| 2732 |
|
|
|
| 2733 |
40 |
unneback |
`define MODULE cnt_lfsr_ce_zq
|
| 2734 |
|
|
module `BASE`MODULE (
|
| 2735 |
|
|
`undef MODULE
|
| 2736 |
|
|
cke, zq, rst, clk);
|
| 2737 |
|
|
|
| 2738 |
6 |
unneback |
parameter length = 4;
|
| 2739 |
|
|
input cke;
|
| 2740 |
|
|
output reg zq;
|
| 2741 |
|
|
input rst;
|
| 2742 |
|
|
input clk;
|
| 2743 |
|
|
|
| 2744 |
|
|
parameter clear_value = 0;
|
| 2745 |
|
|
parameter set_value = 1;
|
| 2746 |
|
|
parameter wrap_value = 8;
|
| 2747 |
|
|
parameter level1_value = 15;
|
| 2748 |
|
|
|
| 2749 |
|
|
reg [length:1] qi;
|
| 2750 |
|
|
reg lfsr_fb;
|
| 2751 |
|
|
wire [length:1] q_next;
|
| 2752 |
|
|
reg [32:1] polynom;
|
| 2753 |
|
|
integer i;
|
| 2754 |
|
|
|
| 2755 |
|
|
always @ (qi)
|
| 2756 |
|
|
begin
|
| 2757 |
|
|
case (length)
|
| 2758 |
|
|
2: polynom = 32'b11; // 0x3
|
| 2759 |
|
|
3: polynom = 32'b110; // 0x6
|
| 2760 |
|
|
4: polynom = 32'b1100; // 0xC
|
| 2761 |
|
|
5: polynom = 32'b10100; // 0x14
|
| 2762 |
|
|
6: polynom = 32'b110000; // 0x30
|
| 2763 |
|
|
7: polynom = 32'b1100000; // 0x60
|
| 2764 |
|
|
8: polynom = 32'b10111000; // 0xb8
|
| 2765 |
|
|
9: polynom = 32'b100010000; // 0x110
|
| 2766 |
|
|
10: polynom = 32'b1001000000; // 0x240
|
| 2767 |
|
|
11: polynom = 32'b10100000000; // 0x500
|
| 2768 |
|
|
12: polynom = 32'b100000101001; // 0x829
|
| 2769 |
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
| 2770 |
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
| 2771 |
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
| 2772 |
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
| 2773 |
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
| 2774 |
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
| 2775 |
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
| 2776 |
37 |
unneback |
20: polynom = 32'b10010000000000000000; // 0x90000
|
| 2777 |
6 |
unneback |
21: polynom = 32'b101000000000000000000; // 0x140000
|
| 2778 |
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
| 2779 |
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
| 2780 |
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
| 2781 |
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
| 2782 |
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
| 2783 |
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
| 2784 |
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
| 2785 |
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
| 2786 |
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
| 2787 |
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
| 2788 |
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
| 2789 |
|
|
default: polynom = 32'b0;
|
| 2790 |
|
|
endcase
|
| 2791 |
|
|
lfsr_fb = qi[length];
|
| 2792 |
|
|
for (i=length-1; i>=1; i=i-1) begin
|
| 2793 |
|
|
if (polynom[i])
|
| 2794 |
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
| 2795 |
|
|
end
|
| 2796 |
|
|
end
|
| 2797 |
|
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
| 2798 |
|
|
|
| 2799 |
|
|
always @ (posedge clk or posedge rst)
|
| 2800 |
|
|
if (rst)
|
| 2801 |
|
|
qi <= {length{1'b0}};
|
| 2802 |
|
|
else
|
| 2803 |
|
|
if (cke)
|
| 2804 |
|
|
qi <= q_next;
|
| 2805 |
|
|
|
| 2806 |
|
|
|
| 2807 |
|
|
|
| 2808 |
|
|
always @ (posedge clk or posedge rst)
|
| 2809 |
|
|
if (rst)
|
| 2810 |
|
|
zq <= 1'b1;
|
| 2811 |
|
|
else
|
| 2812 |
|
|
if (cke)
|
| 2813 |
|
|
zq <= q_next == {length{1'b0}};
|
| 2814 |
|
|
endmodule
|
| 2815 |
40 |
unneback |
`endif
|
| 2816 |
|
|
`ifdef CNT_LFSR_CE_Q
|
| 2817 |
6 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 2818 |
|
|
//// ////
|
| 2819 |
|
|
//// Versatile counter ////
|
| 2820 |
|
|
//// ////
|
| 2821 |
|
|
//// Description ////
|
| 2822 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 2823 |
|
|
//// counter ////
|
| 2824 |
|
|
//// ////
|
| 2825 |
|
|
//// To Do: ////
|
| 2826 |
|
|
//// - add LFSR with more taps ////
|
| 2827 |
|
|
//// ////
|
| 2828 |
|
|
//// Author(s): ////
|
| 2829 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 2830 |
|
|
//// ORSoC AB ////
|
| 2831 |
|
|
//// ////
|
| 2832 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2833 |
|
|
//// ////
|
| 2834 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 2835 |
|
|
//// ////
|
| 2836 |
|
|
//// This source file may be used and distributed without ////
|
| 2837 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 2838 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 2839 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 2840 |
|
|
//// ////
|
| 2841 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 2842 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 2843 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 2844 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 2845 |
|
|
//// later version. ////
|
| 2846 |
|
|
//// ////
|
| 2847 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 2848 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 2849 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 2850 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 2851 |
|
|
//// details. ////
|
| 2852 |
|
|
//// ////
|
| 2853 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 2854 |
|
|
//// Public License along with this source; if not, download it ////
|
| 2855 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 2856 |
|
|
//// ////
|
| 2857 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2858 |
22 |
unneback |
|
| 2859 |
|
|
// LFSR counter
|
| 2860 |
27 |
unneback |
|
| 2861 |
40 |
unneback |
`define MODULE cnt_lfsr_ce_q
|
| 2862 |
|
|
module `BASE`MODULE (
|
| 2863 |
|
|
`undef MODULE
|
| 2864 |
|
|
cke, q, rst, clk);
|
| 2865 |
|
|
|
| 2866 |
27 |
unneback |
parameter length = 4;
|
| 2867 |
|
|
input cke;
|
| 2868 |
|
|
output [length:1] q;
|
| 2869 |
|
|
input rst;
|
| 2870 |
|
|
input clk;
|
| 2871 |
|
|
|
| 2872 |
|
|
parameter clear_value = 0;
|
| 2873 |
|
|
parameter set_value = 1;
|
| 2874 |
|
|
parameter wrap_value = 8;
|
| 2875 |
|
|
parameter level1_value = 15;
|
| 2876 |
|
|
|
| 2877 |
|
|
reg [length:1] qi;
|
| 2878 |
|
|
reg lfsr_fb;
|
| 2879 |
|
|
wire [length:1] q_next;
|
| 2880 |
|
|
reg [32:1] polynom;
|
| 2881 |
|
|
integer i;
|
| 2882 |
|
|
|
| 2883 |
|
|
always @ (qi)
|
| 2884 |
|
|
begin
|
| 2885 |
|
|
case (length)
|
| 2886 |
|
|
2: polynom = 32'b11; // 0x3
|
| 2887 |
|
|
3: polynom = 32'b110; // 0x6
|
| 2888 |
|
|
4: polynom = 32'b1100; // 0xC
|
| 2889 |
|
|
5: polynom = 32'b10100; // 0x14
|
| 2890 |
|
|
6: polynom = 32'b110000; // 0x30
|
| 2891 |
|
|
7: polynom = 32'b1100000; // 0x60
|
| 2892 |
|
|
8: polynom = 32'b10111000; // 0xb8
|
| 2893 |
|
|
9: polynom = 32'b100010000; // 0x110
|
| 2894 |
|
|
10: polynom = 32'b1001000000; // 0x240
|
| 2895 |
|
|
11: polynom = 32'b10100000000; // 0x500
|
| 2896 |
|
|
12: polynom = 32'b100000101001; // 0x829
|
| 2897 |
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
| 2898 |
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
| 2899 |
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
| 2900 |
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
| 2901 |
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
| 2902 |
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
| 2903 |
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
| 2904 |
37 |
unneback |
20: polynom = 32'b10010000000000000000; // 0x90000
|
| 2905 |
27 |
unneback |
21: polynom = 32'b101000000000000000000; // 0x140000
|
| 2906 |
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
| 2907 |
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
| 2908 |
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
| 2909 |
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
| 2910 |
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
| 2911 |
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
| 2912 |
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
| 2913 |
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
| 2914 |
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
| 2915 |
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
| 2916 |
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
| 2917 |
|
|
default: polynom = 32'b0;
|
| 2918 |
|
|
endcase
|
| 2919 |
|
|
lfsr_fb = qi[length];
|
| 2920 |
|
|
for (i=length-1; i>=1; i=i-1) begin
|
| 2921 |
|
|
if (polynom[i])
|
| 2922 |
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
| 2923 |
|
|
end
|
| 2924 |
|
|
end
|
| 2925 |
|
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
| 2926 |
|
|
|
| 2927 |
|
|
always @ (posedge clk or posedge rst)
|
| 2928 |
|
|
if (rst)
|
| 2929 |
|
|
qi <= {length{1'b0}};
|
| 2930 |
|
|
else
|
| 2931 |
|
|
if (cke)
|
| 2932 |
|
|
qi <= q_next;
|
| 2933 |
|
|
|
| 2934 |
|
|
assign q = qi;
|
| 2935 |
|
|
|
| 2936 |
|
|
endmodule
|
| 2937 |
40 |
unneback |
`endif
|
| 2938 |
|
|
`ifdef CNT_LFSR_CE_CLEAR_Q
|
| 2939 |
27 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 2940 |
|
|
//// ////
|
| 2941 |
|
|
//// Versatile counter ////
|
| 2942 |
|
|
//// ////
|
| 2943 |
|
|
//// Description ////
|
| 2944 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 2945 |
|
|
//// counter ////
|
| 2946 |
|
|
//// ////
|
| 2947 |
|
|
//// To Do: ////
|
| 2948 |
|
|
//// - add LFSR with more taps ////
|
| 2949 |
|
|
//// ////
|
| 2950 |
|
|
//// Author(s): ////
|
| 2951 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 2952 |
|
|
//// ORSoC AB ////
|
| 2953 |
|
|
//// ////
|
| 2954 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2955 |
|
|
//// ////
|
| 2956 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 2957 |
|
|
//// ////
|
| 2958 |
|
|
//// This source file may be used and distributed without ////
|
| 2959 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 2960 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 2961 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 2962 |
|
|
//// ////
|
| 2963 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 2964 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 2965 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 2966 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 2967 |
|
|
//// later version. ////
|
| 2968 |
|
|
//// ////
|
| 2969 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 2970 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 2971 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 2972 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 2973 |
|
|
//// details. ////
|
| 2974 |
|
|
//// ////
|
| 2975 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 2976 |
|
|
//// Public License along with this source; if not, download it ////
|
| 2977 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 2978 |
|
|
//// ////
|
| 2979 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 2980 |
|
|
|
| 2981 |
|
|
// LFSR counter
|
| 2982 |
|
|
|
| 2983 |
40 |
unneback |
`define MODULE cnt_lfsr_ce_clear_q
|
| 2984 |
|
|
module `BASE`MODULE (
|
| 2985 |
|
|
`undef MODULE
|
| 2986 |
|
|
clear, cke, q, rst, clk);
|
| 2987 |
|
|
|
| 2988 |
27 |
unneback |
parameter length = 4;
|
| 2989 |
|
|
input clear;
|
| 2990 |
|
|
input cke;
|
| 2991 |
|
|
output [length:1] q;
|
| 2992 |
|
|
input rst;
|
| 2993 |
|
|
input clk;
|
| 2994 |
|
|
|
| 2995 |
|
|
parameter clear_value = 0;
|
| 2996 |
|
|
parameter set_value = 1;
|
| 2997 |
|
|
parameter wrap_value = 8;
|
| 2998 |
|
|
parameter level1_value = 15;
|
| 2999 |
|
|
|
| 3000 |
|
|
reg [length:1] qi;
|
| 3001 |
|
|
reg lfsr_fb;
|
| 3002 |
|
|
wire [length:1] q_next;
|
| 3003 |
|
|
reg [32:1] polynom;
|
| 3004 |
|
|
integer i;
|
| 3005 |
|
|
|
| 3006 |
|
|
always @ (qi)
|
| 3007 |
|
|
begin
|
| 3008 |
|
|
case (length)
|
| 3009 |
|
|
2: polynom = 32'b11; // 0x3
|
| 3010 |
|
|
3: polynom = 32'b110; // 0x6
|
| 3011 |
|
|
4: polynom = 32'b1100; // 0xC
|
| 3012 |
|
|
5: polynom = 32'b10100; // 0x14
|
| 3013 |
|
|
6: polynom = 32'b110000; // 0x30
|
| 3014 |
|
|
7: polynom = 32'b1100000; // 0x60
|
| 3015 |
|
|
8: polynom = 32'b10111000; // 0xb8
|
| 3016 |
|
|
9: polynom = 32'b100010000; // 0x110
|
| 3017 |
|
|
10: polynom = 32'b1001000000; // 0x240
|
| 3018 |
|
|
11: polynom = 32'b10100000000; // 0x500
|
| 3019 |
|
|
12: polynom = 32'b100000101001; // 0x829
|
| 3020 |
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
| 3021 |
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
| 3022 |
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
| 3023 |
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
| 3024 |
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
| 3025 |
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
| 3026 |
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
| 3027 |
37 |
unneback |
20: polynom = 32'b10010000000000000000; // 0x90000
|
| 3028 |
27 |
unneback |
21: polynom = 32'b101000000000000000000; // 0x140000
|
| 3029 |
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
| 3030 |
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
| 3031 |
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
| 3032 |
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
| 3033 |
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
| 3034 |
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
| 3035 |
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
| 3036 |
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
| 3037 |
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
| 3038 |
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
| 3039 |
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
| 3040 |
|
|
default: polynom = 32'b0;
|
| 3041 |
|
|
endcase
|
| 3042 |
|
|
lfsr_fb = qi[length];
|
| 3043 |
|
|
for (i=length-1; i>=1; i=i-1) begin
|
| 3044 |
|
|
if (polynom[i])
|
| 3045 |
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
| 3046 |
|
|
end
|
| 3047 |
|
|
end
|
| 3048 |
|
|
assign q_next = clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
| 3049 |
|
|
|
| 3050 |
|
|
always @ (posedge clk or posedge rst)
|
| 3051 |
|
|
if (rst)
|
| 3052 |
|
|
qi <= {length{1'b0}};
|
| 3053 |
|
|
else
|
| 3054 |
|
|
if (cke)
|
| 3055 |
|
|
qi <= q_next;
|
| 3056 |
|
|
|
| 3057 |
|
|
assign q = qi;
|
| 3058 |
|
|
|
| 3059 |
|
|
endmodule
|
| 3060 |
40 |
unneback |
`endif
|
| 3061 |
|
|
`ifdef CNT_LFSR_CE_Q_ZQ
|
| 3062 |
27 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 3063 |
|
|
//// ////
|
| 3064 |
|
|
//// Versatile counter ////
|
| 3065 |
|
|
//// ////
|
| 3066 |
|
|
//// Description ////
|
| 3067 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 3068 |
|
|
//// counter ////
|
| 3069 |
|
|
//// ////
|
| 3070 |
|
|
//// To Do: ////
|
| 3071 |
|
|
//// - add LFSR with more taps ////
|
| 3072 |
|
|
//// ////
|
| 3073 |
|
|
//// Author(s): ////
|
| 3074 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 3075 |
|
|
//// ORSoC AB ////
|
| 3076 |
|
|
//// ////
|
| 3077 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 3078 |
|
|
//// ////
|
| 3079 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 3080 |
|
|
//// ////
|
| 3081 |
|
|
//// This source file may be used and distributed without ////
|
| 3082 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 3083 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 3084 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 3085 |
|
|
//// ////
|
| 3086 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 3087 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 3088 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 3089 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 3090 |
|
|
//// later version. ////
|
| 3091 |
|
|
//// ////
|
| 3092 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 3093 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 3094 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 3095 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 3096 |
|
|
//// details. ////
|
| 3097 |
|
|
//// ////
|
| 3098 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 3099 |
|
|
//// Public License along with this source; if not, download it ////
|
| 3100 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 3101 |
|
|
//// ////
|
| 3102 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 3103 |
|
|
|
| 3104 |
|
|
// LFSR counter
|
| 3105 |
22 |
unneback |
|
| 3106 |
40 |
unneback |
`define MODULE cnt_lfsr_ce_q_zq
|
| 3107 |
|
|
module `BASE`MODULE (
|
| 3108 |
|
|
`undef MODULE
|
| 3109 |
|
|
cke, q, zq, rst, clk);
|
| 3110 |
|
|
|
| 3111 |
22 |
unneback |
parameter length = 4;
|
| 3112 |
|
|
input cke;
|
| 3113 |
|
|
output [length:1] q;
|
| 3114 |
|
|
output reg zq;
|
| 3115 |
|
|
input rst;
|
| 3116 |
|
|
input clk;
|
| 3117 |
|
|
|
| 3118 |
|
|
parameter clear_value = 0;
|
| 3119 |
|
|
parameter set_value = 1;
|
| 3120 |
|
|
parameter wrap_value = 8;
|
| 3121 |
|
|
parameter level1_value = 15;
|
| 3122 |
|
|
|
| 3123 |
|
|
reg [length:1] qi;
|
| 3124 |
|
|
reg lfsr_fb;
|
| 3125 |
|
|
wire [length:1] q_next;
|
| 3126 |
|
|
reg [32:1] polynom;
|
| 3127 |
|
|
integer i;
|
| 3128 |
|
|
|
| 3129 |
|
|
always @ (qi)
|
| 3130 |
|
|
begin
|
| 3131 |
|
|
case (length)
|
| 3132 |
|
|
2: polynom = 32'b11; // 0x3
|
| 3133 |
|
|
3: polynom = 32'b110; // 0x6
|
| 3134 |
|
|
4: polynom = 32'b1100; // 0xC
|
| 3135 |
|
|
5: polynom = 32'b10100; // 0x14
|
| 3136 |
|
|
6: polynom = 32'b110000; // 0x30
|
| 3137 |
|
|
7: polynom = 32'b1100000; // 0x60
|
| 3138 |
|
|
8: polynom = 32'b10111000; // 0xb8
|
| 3139 |
|
|
9: polynom = 32'b100010000; // 0x110
|
| 3140 |
|
|
10: polynom = 32'b1001000000; // 0x240
|
| 3141 |
|
|
11: polynom = 32'b10100000000; // 0x500
|
| 3142 |
|
|
12: polynom = 32'b100000101001; // 0x829
|
| 3143 |
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
| 3144 |
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
| 3145 |
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
| 3146 |
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
| 3147 |
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
| 3148 |
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
| 3149 |
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
| 3150 |
37 |
unneback |
20: polynom = 32'b10010000000000000000; // 0x90000
|
| 3151 |
22 |
unneback |
21: polynom = 32'b101000000000000000000; // 0x140000
|
| 3152 |
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
| 3153 |
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
| 3154 |
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
| 3155 |
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
| 3156 |
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
| 3157 |
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
| 3158 |
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
| 3159 |
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
| 3160 |
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
| 3161 |
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
| 3162 |
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
| 3163 |
|
|
default: polynom = 32'b0;
|
| 3164 |
|
|
endcase
|
| 3165 |
|
|
lfsr_fb = qi[length];
|
| 3166 |
|
|
for (i=length-1; i>=1; i=i-1) begin
|
| 3167 |
|
|
if (polynom[i])
|
| 3168 |
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
| 3169 |
|
|
end
|
| 3170 |
|
|
end
|
| 3171 |
|
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
| 3172 |
|
|
|
| 3173 |
|
|
always @ (posedge clk or posedge rst)
|
| 3174 |
|
|
if (rst)
|
| 3175 |
|
|
qi <= {length{1'b0}};
|
| 3176 |
|
|
else
|
| 3177 |
|
|
if (cke)
|
| 3178 |
|
|
qi <= q_next;
|
| 3179 |
|
|
|
| 3180 |
|
|
assign q = qi;
|
| 3181 |
|
|
|
| 3182 |
|
|
|
| 3183 |
|
|
always @ (posedge clk or posedge rst)
|
| 3184 |
|
|
if (rst)
|
| 3185 |
|
|
zq <= 1'b1;
|
| 3186 |
|
|
else
|
| 3187 |
|
|
if (cke)
|
| 3188 |
|
|
zq <= q_next == {length{1'b0}};
|
| 3189 |
|
|
endmodule
|
| 3190 |
40 |
unneback |
`endif
|
| 3191 |
|
|
`ifdef CNT_LFSR_CE_REW_L1
|
| 3192 |
22 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 3193 |
|
|
//// ////
|
| 3194 |
|
|
//// Versatile counter ////
|
| 3195 |
|
|
//// ////
|
| 3196 |
|
|
//// Description ////
|
| 3197 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 3198 |
|
|
//// counter ////
|
| 3199 |
|
|
//// ////
|
| 3200 |
|
|
//// To Do: ////
|
| 3201 |
|
|
//// - add LFSR with more taps ////
|
| 3202 |
|
|
//// ////
|
| 3203 |
|
|
//// Author(s): ////
|
| 3204 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 3205 |
|
|
//// ORSoC AB ////
|
| 3206 |
|
|
//// ////
|
| 3207 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 3208 |
|
|
//// ////
|
| 3209 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 3210 |
|
|
//// ////
|
| 3211 |
|
|
//// This source file may be used and distributed without ////
|
| 3212 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 3213 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 3214 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 3215 |
|
|
//// ////
|
| 3216 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 3217 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 3218 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 3219 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 3220 |
|
|
//// later version. ////
|
| 3221 |
|
|
//// ////
|
| 3222 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 3223 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 3224 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 3225 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 3226 |
|
|
//// details. ////
|
| 3227 |
|
|
//// ////
|
| 3228 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 3229 |
|
|
//// Public License along with this source; if not, download it ////
|
| 3230 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 3231 |
|
|
//// ////
|
| 3232 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 3233 |
6 |
unneback |
|
| 3234 |
|
|
// LFSR counter
|
| 3235 |
|
|
|
| 3236 |
40 |
unneback |
`define MODULE cnt_lfsr_ce_rew_l1
|
| 3237 |
|
|
module `BASE`MODULE (
|
| 3238 |
|
|
`undef MODULE
|
| 3239 |
|
|
cke, rew, level1, rst, clk);
|
| 3240 |
|
|
|
| 3241 |
6 |
unneback |
parameter length = 4;
|
| 3242 |
|
|
input cke;
|
| 3243 |
|
|
input rew;
|
| 3244 |
|
|
output reg level1;
|
| 3245 |
|
|
input rst;
|
| 3246 |
|
|
input clk;
|
| 3247 |
|
|
|
| 3248 |
|
|
parameter clear_value = 0;
|
| 3249 |
|
|
parameter set_value = 1;
|
| 3250 |
|
|
parameter wrap_value = 8;
|
| 3251 |
|
|
parameter level1_value = 15;
|
| 3252 |
|
|
|
| 3253 |
29 |
unneback |
wire clear;
|
| 3254 |
30 |
unneback |
assign clear = 1'b0;
|
| 3255 |
6 |
unneback |
reg [length:1] qi;
|
| 3256 |
|
|
reg lfsr_fb, lfsr_fb_rew;
|
| 3257 |
|
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
| 3258 |
|
|
reg [32:1] polynom_rew;
|
| 3259 |
|
|
integer j;
|
| 3260 |
|
|
reg [32:1] polynom;
|
| 3261 |
|
|
integer i;
|
| 3262 |
|
|
|
| 3263 |
|
|
always @ (qi)
|
| 3264 |
|
|
begin
|
| 3265 |
|
|
case (length)
|
| 3266 |
|
|
2: polynom = 32'b11; // 0x3
|
| 3267 |
|
|
3: polynom = 32'b110; // 0x6
|
| 3268 |
|
|
4: polynom = 32'b1100; // 0xC
|
| 3269 |
|
|
5: polynom = 32'b10100; // 0x14
|
| 3270 |
|
|
6: polynom = 32'b110000; // 0x30
|
| 3271 |
|
|
7: polynom = 32'b1100000; // 0x60
|
| 3272 |
|
|
8: polynom = 32'b10111000; // 0xb8
|
| 3273 |
|
|
9: polynom = 32'b100010000; // 0x110
|
| 3274 |
|
|
10: polynom = 32'b1001000000; // 0x240
|
| 3275 |
|
|
11: polynom = 32'b10100000000; // 0x500
|
| 3276 |
|
|
12: polynom = 32'b100000101001; // 0x829
|
| 3277 |
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
| 3278 |
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
| 3279 |
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
| 3280 |
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
| 3281 |
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
| 3282 |
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
| 3283 |
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
| 3284 |
37 |
unneback |
20: polynom = 32'b10010000000000000000; // 0x90000
|
| 3285 |
6 |
unneback |
21: polynom = 32'b101000000000000000000; // 0x140000
|
| 3286 |
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
| 3287 |
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
| 3288 |
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
| 3289 |
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
| 3290 |
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
| 3291 |
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
| 3292 |
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
| 3293 |
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
| 3294 |
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
| 3295 |
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
| 3296 |
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
| 3297 |
|
|
default: polynom = 32'b0;
|
| 3298 |
|
|
endcase
|
| 3299 |
|
|
lfsr_fb = qi[length];
|
| 3300 |
|
|
for (i=length-1; i>=1; i=i-1) begin
|
| 3301 |
|
|
if (polynom[i])
|
| 3302 |
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
| 3303 |
|
|
end
|
| 3304 |
|
|
end
|
| 3305 |
|
|
assign q_next_fw = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
| 3306 |
|
|
always @ (qi)
|
| 3307 |
|
|
begin
|
| 3308 |
|
|
case (length)
|
| 3309 |
|
|
2: polynom_rew = 32'b11;
|
| 3310 |
|
|
3: polynom_rew = 32'b110;
|
| 3311 |
|
|
4: polynom_rew = 32'b1100;
|
| 3312 |
|
|
5: polynom_rew = 32'b10100;
|
| 3313 |
|
|
6: polynom_rew = 32'b110000;
|
| 3314 |
|
|
7: polynom_rew = 32'b1100000;
|
| 3315 |
|
|
8: polynom_rew = 32'b10111000;
|
| 3316 |
|
|
9: polynom_rew = 32'b100010000;
|
| 3317 |
|
|
10: polynom_rew = 32'b1001000000;
|
| 3318 |
|
|
11: polynom_rew = 32'b10100000000;
|
| 3319 |
|
|
12: polynom_rew = 32'b100000101001;
|
| 3320 |
|
|
13: polynom_rew = 32'b1000000001100;
|
| 3321 |
|
|
14: polynom_rew = 32'b10000000010101;
|
| 3322 |
|
|
15: polynom_rew = 32'b110000000000000;
|
| 3323 |
|
|
16: polynom_rew = 32'b1101000000001000;
|
| 3324 |
|
|
17: polynom_rew = 32'b10010000000000000;
|
| 3325 |
|
|
18: polynom_rew = 32'b100000010000000000;
|
| 3326 |
|
|
19: polynom_rew = 32'b1000000000000100011;
|
| 3327 |
|
|
20: polynom_rew = 32'b10000010000000000000;
|
| 3328 |
|
|
21: polynom_rew = 32'b101000000000000000000;
|
| 3329 |
|
|
22: polynom_rew = 32'b1100000000000000000000;
|
| 3330 |
|
|
23: polynom_rew = 32'b10000100000000000000000;
|
| 3331 |
|
|
24: polynom_rew = 32'b111000010000000000000000;
|
| 3332 |
|
|
25: polynom_rew = 32'b1001000000000000000000000;
|
| 3333 |
|
|
26: polynom_rew = 32'b10000000000000000000100011;
|
| 3334 |
|
|
27: polynom_rew = 32'b100000000000000000000010011;
|
| 3335 |
|
|
28: polynom_rew = 32'b1100100000000000000000000000;
|
| 3336 |
|
|
29: polynom_rew = 32'b10100000000000000000000000000;
|
| 3337 |
|
|
30: polynom_rew = 32'b100000000000000000000000101001;
|
| 3338 |
|
|
31: polynom_rew = 32'b1001000000000000000000000000000;
|
| 3339 |
|
|
32: polynom_rew = 32'b10000000001000000000000000000011;
|
| 3340 |
|
|
default: polynom_rew = 32'b0;
|
| 3341 |
|
|
endcase
|
| 3342 |
|
|
// rotate left
|
| 3343 |
|
|
polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
|
| 3344 |
|
|
lfsr_fb_rew = qi[length];
|
| 3345 |
|
|
for (i=length-1; i>=1; i=i-1) begin
|
| 3346 |
|
|
if (polynom_rew[i])
|
| 3347 |
|
|
lfsr_fb_rew = lfsr_fb_rew ~^ qi[i];
|
| 3348 |
|
|
end
|
| 3349 |
|
|
end
|
| 3350 |
|
|
assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
|
| 3351 |
|
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
| 3352 |
|
|
|
| 3353 |
|
|
always @ (posedge clk or posedge rst)
|
| 3354 |
|
|
if (rst)
|
| 3355 |
|
|
qi <= {length{1'b0}};
|
| 3356 |
|
|
else
|
| 3357 |
|
|
if (cke)
|
| 3358 |
|
|
qi <= q_next;
|
| 3359 |
|
|
|
| 3360 |
|
|
|
| 3361 |
|
|
|
| 3362 |
|
|
always @ (posedge clk or posedge rst)
|
| 3363 |
|
|
if (rst)
|
| 3364 |
|
|
level1 <= 1'b0;
|
| 3365 |
|
|
else
|
| 3366 |
|
|
if (cke)
|
| 3367 |
29 |
unneback |
if (clear)
|
| 3368 |
|
|
level1 <= 1'b0;
|
| 3369 |
|
|
else if (q_next == level1_value)
|
| 3370 |
6 |
unneback |
level1 <= 1'b1;
|
| 3371 |
|
|
else if (qi == level1_value & rew)
|
| 3372 |
|
|
level1 <= 1'b0;
|
| 3373 |
|
|
endmodule
|
| 3374 |
40 |
unneback |
`endif
|
| 3375 |
|
|
`ifdef CNT_GRAY
|
| 3376 |
6 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 3377 |
|
|
//// ////
|
| 3378 |
|
|
//// Versatile counter ////
|
| 3379 |
|
|
//// ////
|
| 3380 |
|
|
//// Description ////
|
| 3381 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 3382 |
|
|
//// counter ////
|
| 3383 |
|
|
//// ////
|
| 3384 |
|
|
//// To Do: ////
|
| 3385 |
|
|
//// - add LFSR with more taps ////
|
| 3386 |
|
|
//// ////
|
| 3387 |
|
|
//// Author(s): ////
|
| 3388 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 3389 |
|
|
//// ORSoC AB ////
|
| 3390 |
|
|
//// ////
|
| 3391 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 3392 |
|
|
//// ////
|
| 3393 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 3394 |
|
|
//// ////
|
| 3395 |
|
|
//// This source file may be used and distributed without ////
|
| 3396 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 3397 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 3398 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 3399 |
|
|
//// ////
|
| 3400 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 3401 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 3402 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 3403 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 3404 |
|
|
//// later version. ////
|
| 3405 |
|
|
//// ////
|
| 3406 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 3407 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 3408 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 3409 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 3410 |
|
|
//// details. ////
|
| 3411 |
|
|
//// ////
|
| 3412 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 3413 |
|
|
//// Public License along with this source; if not, download it ////
|
| 3414 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 3415 |
|
|
//// ////
|
| 3416 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 3417 |
|
|
|
| 3418 |
|
|
// GRAY counter
|
| 3419 |
|
|
|
| 3420 |
40 |
unneback |
`define MODULE cnt_gray
|
| 3421 |
|
|
module `BASE`MODULE (
|
| 3422 |
|
|
`undef MODULE
|
| 3423 |
|
|
q, rst, clk);
|
| 3424 |
|
|
|
| 3425 |
6 |
unneback |
parameter length = 4;
|
| 3426 |
|
|
output reg [length:1] q;
|
| 3427 |
|
|
input rst;
|
| 3428 |
|
|
input clk;
|
| 3429 |
|
|
|
| 3430 |
|
|
parameter clear_value = 0;
|
| 3431 |
|
|
parameter set_value = 1;
|
| 3432 |
|
|
parameter wrap_value = 8;
|
| 3433 |
|
|
parameter level1_value = 15;
|
| 3434 |
|
|
|
| 3435 |
|
|
reg [length:1] qi;
|
| 3436 |
|
|
wire [length:1] q_next;
|
| 3437 |
|
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
| 3438 |
|
|
|
| 3439 |
|
|
always @ (posedge clk or posedge rst)
|
| 3440 |
|
|
if (rst)
|
| 3441 |
|
|
qi <= {length{1'b0}};
|
| 3442 |
|
|
else
|
| 3443 |
|
|
qi <= q_next;
|
| 3444 |
|
|
|
| 3445 |
|
|
always @ (posedge clk or posedge rst)
|
| 3446 |
|
|
if (rst)
|
| 3447 |
|
|
q <= {length{1'b0}};
|
| 3448 |
|
|
else
|
| 3449 |
|
|
q <= (q_next>>1) ^ q_next;
|
| 3450 |
|
|
|
| 3451 |
|
|
endmodule
|
| 3452 |
40 |
unneback |
`endif
|
| 3453 |
|
|
`ifdef CNT_GRAY_CE
|
| 3454 |
6 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 3455 |
|
|
//// ////
|
| 3456 |
|
|
//// Versatile counter ////
|
| 3457 |
|
|
//// ////
|
| 3458 |
|
|
//// Description ////
|
| 3459 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 3460 |
|
|
//// counter ////
|
| 3461 |
|
|
//// ////
|
| 3462 |
|
|
//// To Do: ////
|
| 3463 |
|
|
//// - add LFSR with more taps ////
|
| 3464 |
|
|
//// ////
|
| 3465 |
|
|
//// Author(s): ////
|
| 3466 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 3467 |
|
|
//// ORSoC AB ////
|
| 3468 |
|
|
//// ////
|
| 3469 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 3470 |
|
|
//// ////
|
| 3471 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 3472 |
|
|
//// ////
|
| 3473 |
|
|
//// This source file may be used and distributed without ////
|
| 3474 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 3475 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 3476 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 3477 |
|
|
//// ////
|
| 3478 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 3479 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 3480 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 3481 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 3482 |
|
|
//// later version. ////
|
| 3483 |
|
|
//// ////
|
| 3484 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 3485 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 3486 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 3487 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 3488 |
|
|
//// details. ////
|
| 3489 |
|
|
//// ////
|
| 3490 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 3491 |
|
|
//// Public License along with this source; if not, download it ////
|
| 3492 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 3493 |
|
|
//// ////
|
| 3494 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 3495 |
|
|
|
| 3496 |
|
|
// GRAY counter
|
| 3497 |
|
|
|
| 3498 |
40 |
unneback |
`define MODULE cnt_gray_ce
|
| 3499 |
|
|
module `BASE`MODULE (
|
| 3500 |
|
|
`undef MODULE
|
| 3501 |
|
|
cke, q, rst, clk);
|
| 3502 |
|
|
|
| 3503 |
6 |
unneback |
parameter length = 4;
|
| 3504 |
|
|
input cke;
|
| 3505 |
|
|
output reg [length:1] q;
|
| 3506 |
|
|
input rst;
|
| 3507 |
|
|
input clk;
|
| 3508 |
|
|
|
| 3509 |
|
|
parameter clear_value = 0;
|
| 3510 |
|
|
parameter set_value = 1;
|
| 3511 |
|
|
parameter wrap_value = 8;
|
| 3512 |
|
|
parameter level1_value = 15;
|
| 3513 |
|
|
|
| 3514 |
|
|
reg [length:1] qi;
|
| 3515 |
|
|
wire [length:1] q_next;
|
| 3516 |
|
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
| 3517 |
|
|
|
| 3518 |
|
|
always @ (posedge clk or posedge rst)
|
| 3519 |
|
|
if (rst)
|
| 3520 |
|
|
qi <= {length{1'b0}};
|
| 3521 |
|
|
else
|
| 3522 |
|
|
if (cke)
|
| 3523 |
|
|
qi <= q_next;
|
| 3524 |
|
|
|
| 3525 |
|
|
always @ (posedge clk or posedge rst)
|
| 3526 |
|
|
if (rst)
|
| 3527 |
|
|
q <= {length{1'b0}};
|
| 3528 |
|
|
else
|
| 3529 |
|
|
if (cke)
|
| 3530 |
|
|
q <= (q_next>>1) ^ q_next;
|
| 3531 |
|
|
|
| 3532 |
|
|
endmodule
|
| 3533 |
40 |
unneback |
`endif
|
| 3534 |
|
|
`ifdef CNT_GRAY_CE_BIN
|
| 3535 |
6 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 3536 |
|
|
//// ////
|
| 3537 |
|
|
//// Versatile counter ////
|
| 3538 |
|
|
//// ////
|
| 3539 |
|
|
//// Description ////
|
| 3540 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
| 3541 |
|
|
//// counter ////
|
| 3542 |
|
|
//// ////
|
| 3543 |
|
|
//// To Do: ////
|
| 3544 |
|
|
//// - add LFSR with more taps ////
|
| 3545 |
|
|
//// ////
|
| 3546 |
|
|
//// Author(s): ////
|
| 3547 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 3548 |
|
|
//// ORSoC AB ////
|
| 3549 |
|
|
//// ////
|
| 3550 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 3551 |
|
|
//// ////
|
| 3552 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
| 3553 |
|
|
//// ////
|
| 3554 |
|
|
//// This source file may be used and distributed without ////
|
| 3555 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 3556 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 3557 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 3558 |
|
|
//// ////
|
| 3559 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 3560 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 3561 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 3562 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 3563 |
|
|
//// later version. ////
|
| 3564 |
|
|
//// ////
|
| 3565 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 3566 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 3567 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 3568 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 3569 |
|
|
//// details. ////
|
| 3570 |
|
|
//// ////
|
| 3571 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 3572 |
|
|
//// Public License along with this source; if not, download it ////
|
| 3573 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 3574 |
|
|
//// ////
|
| 3575 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 3576 |
|
|
|
| 3577 |
|
|
// GRAY counter
|
| 3578 |
|
|
|
| 3579 |
40 |
unneback |
`define MODULE cnt_gray_ce_bin
|
| 3580 |
|
|
module `BASE`MODULE (
|
| 3581 |
|
|
`undef MODULE
|
| 3582 |
|
|
cke, q, q_bin, rst, clk);
|
| 3583 |
|
|
|
| 3584 |
6 |
unneback |
parameter length = 4;
|
| 3585 |
|
|
input cke;
|
| 3586 |
|
|
output reg [length:1] q;
|
| 3587 |
|
|
output [length:1] q_bin;
|
| 3588 |
|
|
input rst;
|
| 3589 |
|
|
input clk;
|
| 3590 |
|
|
|
| 3591 |
|
|
parameter clear_value = 0;
|
| 3592 |
|
|
parameter set_value = 1;
|
| 3593 |
|
|
parameter wrap_value = 8;
|
| 3594 |
|
|
parameter level1_value = 15;
|
| 3595 |
|
|
|
| 3596 |
|
|
reg [length:1] qi;
|
| 3597 |
|
|
wire [length:1] q_next;
|
| 3598 |
|
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
| 3599 |
|
|
|
| 3600 |
|
|
always @ (posedge clk or posedge rst)
|
| 3601 |
|
|
if (rst)
|
| 3602 |
|
|
qi <= {length{1'b0}};
|
| 3603 |
|
|
else
|
| 3604 |
|
|
if (cke)
|
| 3605 |
|
|
qi <= q_next;
|
| 3606 |
|
|
|
| 3607 |
|
|
always @ (posedge clk or posedge rst)
|
| 3608 |
|
|
if (rst)
|
| 3609 |
|
|
q <= {length{1'b0}};
|
| 3610 |
|
|
else
|
| 3611 |
|
|
if (cke)
|
| 3612 |
|
|
q <= (q_next>>1) ^ q_next;
|
| 3613 |
|
|
|
| 3614 |
|
|
assign q_bin = qi;
|
| 3615 |
|
|
|
| 3616 |
|
|
endmodule
|
| 3617 |
40 |
unneback |
`endif
|
| 3618 |
6 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 3619 |
|
|
//// ////
|
| 3620 |
|
|
//// Versatile library, counters ////
|
| 3621 |
|
|
//// ////
|
| 3622 |
|
|
//// Description ////
|
| 3623 |
|
|
//// counters ////
|
| 3624 |
|
|
//// ////
|
| 3625 |
|
|
//// ////
|
| 3626 |
|
|
//// To Do: ////
|
| 3627 |
|
|
//// - add more counters ////
|
| 3628 |
|
|
//// ////
|
| 3629 |
|
|
//// Author(s): ////
|
| 3630 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 3631 |
|
|
//// ORSoC AB ////
|
| 3632 |
|
|
//// ////
|
| 3633 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 3634 |
|
|
//// ////
|
| 3635 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
| 3636 |
|
|
//// ////
|
| 3637 |
|
|
//// This source file may be used and distributed without ////
|
| 3638 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 3639 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 3640 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 3641 |
|
|
//// ////
|
| 3642 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 3643 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 3644 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 3645 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 3646 |
|
|
//// later version. ////
|
| 3647 |
|
|
//// ////
|
| 3648 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 3649 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 3650 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 3651 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 3652 |
|
|
//// details. ////
|
| 3653 |
|
|
//// ////
|
| 3654 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 3655 |
|
|
//// Public License along with this source; if not, download it ////
|
| 3656 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 3657 |
|
|
//// ////
|
| 3658 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 3659 |
|
|
|
| 3660 |
40 |
unneback |
`ifdef CNT_SHREG_WRAP
|
| 3661 |
|
|
`define MODULE cnt_shreg_wrap
|
| 3662 |
|
|
module `BASE`MODULE ( q, rst, clk);
|
| 3663 |
|
|
`undef MODULE
|
| 3664 |
6 |
unneback |
|
| 3665 |
|
|
parameter length = 4;
|
| 3666 |
|
|
output reg [0:length-1] q;
|
| 3667 |
|
|
input rst;
|
| 3668 |
|
|
input clk;
|
| 3669 |
|
|
|
| 3670 |
|
|
always @ (posedge clk or posedge rst)
|
| 3671 |
|
|
if (rst)
|
| 3672 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
| 3673 |
|
|
else
|
| 3674 |
|
|
q <= {q[length-1],q[0:length-2]};
|
| 3675 |
|
|
|
| 3676 |
|
|
endmodule
|
| 3677 |
40 |
unneback |
`endif
|
| 3678 |
6 |
unneback |
|
| 3679 |
40 |
unneback |
`ifdef CNT_SHREG_CE_WRAP
|
| 3680 |
|
|
`define MODULE cnt_shreg_ce_wrap
|
| 3681 |
|
|
module `BASE`MODULE ( cke, q, rst, clk);
|
| 3682 |
|
|
`undef MODULE
|
| 3683 |
6 |
unneback |
|
| 3684 |
|
|
parameter length = 4;
|
| 3685 |
|
|
input cke;
|
| 3686 |
|
|
output reg [0:length-1] q;
|
| 3687 |
|
|
input rst;
|
| 3688 |
|
|
input clk;
|
| 3689 |
|
|
|
| 3690 |
|
|
always @ (posedge clk or posedge rst)
|
| 3691 |
|
|
if (rst)
|
| 3692 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
| 3693 |
|
|
else
|
| 3694 |
|
|
if (cke)
|
| 3695 |
|
|
q <= {q[length-1],q[0:length-2]};
|
| 3696 |
|
|
|
| 3697 |
|
|
endmodule
|
| 3698 |
40 |
unneback |
`endif
|
| 3699 |
6 |
unneback |
|
| 3700 |
105 |
unneback |
`ifdef CNT_SHREG_CLEAR
|
| 3701 |
|
|
`define MODULE cnt_shreg_clear
|
| 3702 |
|
|
module `BASE`MODULE ( clear, q, rst, clk);
|
| 3703 |
|
|
`undef MODULE
|
| 3704 |
|
|
|
| 3705 |
|
|
parameter length = 4;
|
| 3706 |
|
|
input clear;
|
| 3707 |
|
|
output reg [0:length-1] q;
|
| 3708 |
|
|
input rst;
|
| 3709 |
|
|
input clk;
|
| 3710 |
|
|
|
| 3711 |
|
|
always @ (posedge clk or posedge rst)
|
| 3712 |
|
|
if (rst)
|
| 3713 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
| 3714 |
|
|
else
|
| 3715 |
|
|
if (clear)
|
| 3716 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
| 3717 |
|
|
else
|
| 3718 |
|
|
q <= q >> 1;
|
| 3719 |
|
|
|
| 3720 |
|
|
endmodule
|
| 3721 |
|
|
`endif
|
| 3722 |
|
|
|
| 3723 |
40 |
unneback |
`ifdef CNT_SHREG_CE_CLEAR
|
| 3724 |
|
|
`define MODULE cnt_shreg_ce_clear
|
| 3725 |
|
|
module `BASE`MODULE ( cke, clear, q, rst, clk);
|
| 3726 |
|
|
`undef MODULE
|
| 3727 |
6 |
unneback |
|
| 3728 |
|
|
parameter length = 4;
|
| 3729 |
|
|
input cke, clear;
|
| 3730 |
|
|
output reg [0:length-1] q;
|
| 3731 |
|
|
input rst;
|
| 3732 |
|
|
input clk;
|
| 3733 |
|
|
|
| 3734 |
|
|
always @ (posedge clk or posedge rst)
|
| 3735 |
|
|
if (rst)
|
| 3736 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
| 3737 |
|
|
else
|
| 3738 |
|
|
if (cke)
|
| 3739 |
|
|
if (clear)
|
| 3740 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
| 3741 |
|
|
else
|
| 3742 |
|
|
q <= q >> 1;
|
| 3743 |
|
|
|
| 3744 |
|
|
endmodule
|
| 3745 |
40 |
unneback |
`endif
|
| 3746 |
6 |
unneback |
|
| 3747 |
40 |
unneback |
`ifdef CNT_SHREG_CE_CLEAR_WRAP
|
| 3748 |
|
|
`define MODULE cnt_shreg_ce_clear_wrap
|
| 3749 |
|
|
module `BASE`MODULE ( cke, clear, q, rst, clk);
|
| 3750 |
|
|
`undef MODULE
|
| 3751 |
6 |
unneback |
|
| 3752 |
|
|
parameter length = 4;
|
| 3753 |
|
|
input cke, clear;
|
| 3754 |
|
|
output reg [0:length-1] q;
|
| 3755 |
|
|
input rst;
|
| 3756 |
|
|
input clk;
|
| 3757 |
|
|
|
| 3758 |
|
|
always @ (posedge clk or posedge rst)
|
| 3759 |
|
|
if (rst)
|
| 3760 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
| 3761 |
|
|
else
|
| 3762 |
|
|
if (cke)
|
| 3763 |
|
|
if (clear)
|
| 3764 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
| 3765 |
|
|
else
|
| 3766 |
|
|
q <= {q[length-1],q[0:length-2]};
|
| 3767 |
|
|
|
| 3768 |
|
|
endmodule
|
| 3769 |
40 |
unneback |
`endif
|
| 3770 |
6 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 3771 |
|
|
//// ////
|
| 3772 |
|
|
//// Versatile library, memories ////
|
| 3773 |
|
|
//// ////
|
| 3774 |
|
|
//// Description ////
|
| 3775 |
|
|
//// memories ////
|
| 3776 |
|
|
//// ////
|
| 3777 |
|
|
//// ////
|
| 3778 |
|
|
//// To Do: ////
|
| 3779 |
|
|
//// - add more memory types ////
|
| 3780 |
|
|
//// ////
|
| 3781 |
|
|
//// Author(s): ////
|
| 3782 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 3783 |
|
|
//// ORSoC AB ////
|
| 3784 |
|
|
//// ////
|
| 3785 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 3786 |
|
|
//// ////
|
| 3787 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
| 3788 |
|
|
//// ////
|
| 3789 |
|
|
//// This source file may be used and distributed without ////
|
| 3790 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 3791 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 3792 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 3793 |
|
|
//// ////
|
| 3794 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 3795 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 3796 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 3797 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 3798 |
|
|
//// later version. ////
|
| 3799 |
|
|
//// ////
|
| 3800 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 3801 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 3802 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 3803 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 3804 |
|
|
//// details. ////
|
| 3805 |
|
|
//// ////
|
| 3806 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 3807 |
|
|
//// Public License along with this source; if not, download it ////
|
| 3808 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 3809 |
|
|
//// ////
|
| 3810 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 3811 |
|
|
|
| 3812 |
40 |
unneback |
`ifdef ROM_INIT
|
| 3813 |
6 |
unneback |
/// ROM
|
| 3814 |
40 |
unneback |
`define MODULE rom_init
|
| 3815 |
|
|
module `BASE`MODULE ( adr, q, clk);
|
| 3816 |
|
|
`undef MODULE
|
| 3817 |
6 |
unneback |
|
| 3818 |
7 |
unneback |
parameter data_width = 32;
|
| 3819 |
|
|
parameter addr_width = 8;
|
| 3820 |
75 |
unneback |
parameter mem_size = 1<<addr_width;
|
| 3821 |
7 |
unneback |
input [(addr_width-1):0] adr;
|
| 3822 |
|
|
output reg [(data_width-1):0] q;
|
| 3823 |
|
|
input clk;
|
| 3824 |
75 |
unneback |
reg [data_width-1:0] rom [mem_size-1:0];
|
| 3825 |
7 |
unneback |
parameter memory_file = "vl_rom.vmem";
|
| 3826 |
|
|
initial
|
| 3827 |
|
|
begin
|
| 3828 |
|
|
$readmemh(memory_file, rom);
|
| 3829 |
|
|
end
|
| 3830 |
|
|
|
| 3831 |
|
|
always @ (posedge clk)
|
| 3832 |
|
|
q <= rom[adr];
|
| 3833 |
6 |
unneback |
|
| 3834 |
7 |
unneback |
endmodule
|
| 3835 |
40 |
unneback |
`endif
|
| 3836 |
7 |
unneback |
|
| 3837 |
40 |
unneback |
`ifdef RAM
|
| 3838 |
|
|
`define MODULE ram
|
| 3839 |
6 |
unneback |
// Single port RAM
|
| 3840 |
40 |
unneback |
module `BASE`MODULE ( d, adr, we, q, clk);
|
| 3841 |
|
|
`undef MODULE
|
| 3842 |
6 |
unneback |
|
| 3843 |
|
|
parameter data_width = 32;
|
| 3844 |
|
|
parameter addr_width = 8;
|
| 3845 |
75 |
unneback |
parameter mem_size = 1<<addr_width;
|
| 3846 |
100 |
unneback |
parameter debug = 0;
|
| 3847 |
6 |
unneback |
input [(data_width-1):0] d;
|
| 3848 |
|
|
input [(addr_width-1):0] adr;
|
| 3849 |
|
|
input we;
|
| 3850 |
7 |
unneback |
output reg [(data_width-1):0] q;
|
| 3851 |
6 |
unneback |
input clk;
|
| 3852 |
98 |
unneback |
reg [data_width-1:0] ram [mem_size-1:0];
|
| 3853 |
100 |
unneback |
|
| 3854 |
|
|
parameter memory_init = 0;
|
| 3855 |
|
|
parameter memory_file = "vl_ram.vmem";
|
| 3856 |
|
|
generate
|
| 3857 |
|
|
if (memory_init == 1) begin : init_mem
|
| 3858 |
|
|
initial
|
| 3859 |
|
|
$readmemh(memory_file, ram);
|
| 3860 |
|
|
end else if (memory_init == 2) begin : init_zero
|
| 3861 |
|
|
integer k;
|
| 3862 |
|
|
initial
|
| 3863 |
|
|
for (k = 0; k < mem_size; k = k + 1)
|
| 3864 |
|
|
ram[k] = 0;
|
| 3865 |
7 |
unneback |
end
|
| 3866 |
|
|
endgenerate
|
| 3867 |
|
|
|
| 3868 |
100 |
unneback |
generate
|
| 3869 |
|
|
if (debug==1) begin : debug_we
|
| 3870 |
|
|
always @ (posedge clk)
|
| 3871 |
|
|
if (we)
|
| 3872 |
|
|
$display ("Value %h written at address %h : time %t", d, adr, $time);
|
| 3873 |
|
|
|
| 3874 |
|
|
end
|
| 3875 |
|
|
endgenerate
|
| 3876 |
|
|
|
| 3877 |
6 |
unneback |
always @ (posedge clk)
|
| 3878 |
|
|
begin
|
| 3879 |
|
|
if (we)
|
| 3880 |
|
|
ram[adr] <= d;
|
| 3881 |
|
|
q <= ram[adr];
|
| 3882 |
|
|
end
|
| 3883 |
|
|
|
| 3884 |
|
|
endmodule
|
| 3885 |
40 |
unneback |
`endif
|
| 3886 |
6 |
unneback |
|
| 3887 |
40 |
unneback |
`ifdef RAM_BE
|
| 3888 |
|
|
`define MODULE ram_be
|
| 3889 |
91 |
unneback |
module `BASE`MODULE ( d, adr, be, we, q, clk);
|
| 3890 |
40 |
unneback |
`undef MODULE
|
| 3891 |
|
|
|
| 3892 |
7 |
unneback |
parameter data_width = 32;
|
| 3893 |
72 |
unneback |
parameter addr_width = 6;
|
| 3894 |
75 |
unneback |
parameter mem_size = 1<<addr_width;
|
| 3895 |
7 |
unneback |
input [(data_width-1):0] d;
|
| 3896 |
|
|
input [(addr_width-1):0] adr;
|
| 3897 |
73 |
unneback |
input [(data_width/8)-1:0] be;
|
| 3898 |
7 |
unneback |
input we;
|
| 3899 |
|
|
output reg [(data_width-1):0] q;
|
| 3900 |
|
|
input clk;
|
| 3901 |
|
|
|
| 3902 |
85 |
unneback |
|
| 3903 |
65 |
unneback |
`ifdef SYSTEMVERILOG
|
| 3904 |
95 |
unneback |
// use a multi-dimensional packed array
|
| 3905 |
|
|
//t o model individual bytes within the word
|
| 3906 |
|
|
logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
|
| 3907 |
65 |
unneback |
`else
|
| 3908 |
85 |
unneback |
reg [data_width-1:0] ram [mem_size-1:0];
|
| 3909 |
|
|
wire [data_width/8-1:0] cke;
|
| 3910 |
65 |
unneback |
`endif
|
| 3911 |
|
|
|
| 3912 |
100 |
unneback |
parameter memory_init = 0;
|
| 3913 |
|
|
parameter memory_file = "vl_ram.vmem";
|
| 3914 |
|
|
generate
|
| 3915 |
|
|
if (memory_init == 1) begin : init_mem
|
| 3916 |
|
|
initial
|
| 3917 |
|
|
$readmemh(memory_file, ram);
|
| 3918 |
|
|
end else if (memory_init == 2) begin : init_zero
|
| 3919 |
|
|
integer k;
|
| 3920 |
|
|
initial
|
| 3921 |
|
|
for (k = 0; k < mem_size; k = k + 1)
|
| 3922 |
|
|
ram[k] = 0;
|
| 3923 |
|
|
end
|
| 3924 |
7 |
unneback |
endgenerate
|
| 3925 |
|
|
|
| 3926 |
60 |
unneback |
`ifdef SYSTEMVERILOG
|
| 3927 |
|
|
|
| 3928 |
|
|
always_ff@(posedge clk)
|
| 3929 |
|
|
begin
|
| 3930 |
95 |
unneback |
if(we) begin
|
| 3931 |
86 |
unneback |
if(be[3]) ram[adr][3] <= d[31:24];
|
| 3932 |
|
|
if(be[2]) ram[adr][2] <= d[23:16];
|
| 3933 |
|
|
if(be[1]) ram[adr][1] <= d[15:8];
|
| 3934 |
|
|
if(be[0]) ram[adr][0] <= d[7:0];
|
| 3935 |
60 |
unneback |
end
|
| 3936 |
90 |
unneback |
q <= ram[adr];
|
| 3937 |
60 |
unneback |
end
|
| 3938 |
|
|
|
| 3939 |
|
|
`else
|
| 3940 |
|
|
|
| 3941 |
85 |
unneback |
assign cke = {data_width/8{we}} & be;
|
| 3942 |
7 |
unneback |
genvar i;
|
| 3943 |
85 |
unneback |
generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
|
| 3944 |
7 |
unneback |
always @ (posedge clk)
|
| 3945 |
85 |
unneback |
if (cke[i])
|
| 3946 |
7 |
unneback |
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
|
| 3947 |
|
|
end
|
| 3948 |
|
|
endgenerate
|
| 3949 |
|
|
|
| 3950 |
|
|
always @ (posedge clk)
|
| 3951 |
|
|
q <= ram[adr];
|
| 3952 |
|
|
|
| 3953 |
60 |
unneback |
`endif
|
| 3954 |
|
|
|
| 3955 |
93 |
unneback |
`ifdef verilator
|
| 3956 |
85 |
unneback |
// Function to access RAM (for use by Verilator).
|
| 3957 |
|
|
function [31:0] get_mem;
|
| 3958 |
|
|
// verilator public
|
| 3959 |
90 |
unneback |
input [addr_width-1:0] addr;
|
| 3960 |
85 |
unneback |
get_mem = ram[addr];
|
| 3961 |
|
|
endfunction // get_mem
|
| 3962 |
|
|
|
| 3963 |
|
|
// Function to write RAM (for use by Verilator).
|
| 3964 |
|
|
function set_mem;
|
| 3965 |
|
|
// verilator public
|
| 3966 |
90 |
unneback |
input [addr_width-1:0] addr;
|
| 3967 |
|
|
input [data_width-1:0] data;
|
| 3968 |
85 |
unneback |
ram[addr] = data;
|
| 3969 |
|
|
endfunction // set_mem
|
| 3970 |
93 |
unneback |
`endif
|
| 3971 |
85 |
unneback |
|
| 3972 |
7 |
unneback |
endmodule
|
| 3973 |
40 |
unneback |
`endif
|
| 3974 |
7 |
unneback |
|
| 3975 |
40 |
unneback |
`ifdef DPRAM_1R1W
|
| 3976 |
|
|
`define MODULE dpram_1r1w
|
| 3977 |
|
|
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
| 3978 |
|
|
`undef MODULE
|
| 3979 |
6 |
unneback |
parameter data_width = 32;
|
| 3980 |
|
|
parameter addr_width = 8;
|
| 3981 |
75 |
unneback |
parameter mem_size = 1<<addr_width;
|
| 3982 |
6 |
unneback |
input [(data_width-1):0] d_a;
|
| 3983 |
|
|
input [(addr_width-1):0] adr_a;
|
| 3984 |
|
|
input [(addr_width-1):0] adr_b;
|
| 3985 |
|
|
input we_a;
|
| 3986 |
|
|
output [(data_width-1):0] q_b;
|
| 3987 |
|
|
input clk_a, clk_b;
|
| 3988 |
|
|
reg [(addr_width-1):0] adr_b_reg;
|
| 3989 |
100 |
unneback |
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
|
| 3990 |
7 |
unneback |
|
| 3991 |
100 |
unneback |
parameter memory_init = 0;
|
| 3992 |
|
|
parameter memory_file = "vl_ram.vmem";
|
| 3993 |
|
|
parameter debug = 0;
|
| 3994 |
|
|
|
| 3995 |
|
|
generate
|
| 3996 |
|
|
if (memory_init == 1) begin : init_mem
|
| 3997 |
|
|
initial
|
| 3998 |
|
|
$readmemh(memory_file, ram);
|
| 3999 |
|
|
end else if (memory_init == 2) begin : init_zero
|
| 4000 |
|
|
integer k;
|
| 4001 |
|
|
initial
|
| 4002 |
|
|
for (k = 0; k < mem_size; k = k + 1)
|
| 4003 |
|
|
ram[k] = 0;
|
| 4004 |
|
|
end
|
| 4005 |
7 |
unneback |
endgenerate
|
| 4006 |
|
|
|
| 4007 |
100 |
unneback |
generate
|
| 4008 |
|
|
if (debug==1) begin : debug_we
|
| 4009 |
|
|
always @ (posedge clk_a)
|
| 4010 |
|
|
if (we_a)
|
| 4011 |
|
|
$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
|
| 4012 |
|
|
|
| 4013 |
|
|
end
|
| 4014 |
|
|
endgenerate
|
| 4015 |
|
|
|
| 4016 |
6 |
unneback |
always @ (posedge clk_a)
|
| 4017 |
|
|
if (we_a)
|
| 4018 |
|
|
ram[adr_a] <= d_a;
|
| 4019 |
|
|
always @ (posedge clk_b)
|
| 4020 |
|
|
adr_b_reg <= adr_b;
|
| 4021 |
|
|
assign q_b = ram[adr_b_reg];
|
| 4022 |
40 |
unneback |
|
| 4023 |
6 |
unneback |
endmodule
|
| 4024 |
40 |
unneback |
`endif
|
| 4025 |
6 |
unneback |
|
| 4026 |
40 |
unneback |
`ifdef DPRAM_2R1W
|
| 4027 |
|
|
`define MODULE dpram_2r1w
|
| 4028 |
|
|
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
| 4029 |
|
|
`undef MODULE
|
| 4030 |
|
|
|
| 4031 |
6 |
unneback |
parameter data_width = 32;
|
| 4032 |
|
|
parameter addr_width = 8;
|
| 4033 |
75 |
unneback |
parameter mem_size = 1<<addr_width;
|
| 4034 |
6 |
unneback |
input [(data_width-1):0] d_a;
|
| 4035 |
|
|
input [(addr_width-1):0] adr_a;
|
| 4036 |
|
|
input [(addr_width-1):0] adr_b;
|
| 4037 |
|
|
input we_a;
|
| 4038 |
|
|
output [(data_width-1):0] q_b;
|
| 4039 |
|
|
output reg [(data_width-1):0] q_a;
|
| 4040 |
|
|
input clk_a, clk_b;
|
| 4041 |
|
|
reg [(data_width-1):0] q_b;
|
| 4042 |
98 |
unneback |
reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
|
| 4043 |
7 |
unneback |
|
| 4044 |
100 |
unneback |
parameter memory_init = 0;
|
| 4045 |
|
|
parameter memory_file = "vl_ram.vmem";
|
| 4046 |
|
|
parameter debug = 0;
|
| 4047 |
|
|
|
| 4048 |
|
|
generate
|
| 4049 |
|
|
if (memory_init == 1) begin : init_mem
|
| 4050 |
|
|
initial
|
| 4051 |
|
|
$readmemh(memory_file, ram);
|
| 4052 |
|
|
end else if (memory_init == 2) begin : init_zero
|
| 4053 |
|
|
integer k;
|
| 4054 |
|
|
initial
|
| 4055 |
|
|
for (k = 0; k < mem_size; k = k + 1)
|
| 4056 |
|
|
ram[k] = 0;
|
| 4057 |
|
|
end
|
| 4058 |
7 |
unneback |
endgenerate
|
| 4059 |
|
|
|
| 4060 |
100 |
unneback |
generate
|
| 4061 |
|
|
if (debug==1) begin : debug_we
|
| 4062 |
|
|
always @ (posedge clk_a)
|
| 4063 |
|
|
if (we_a)
|
| 4064 |
|
|
$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
|
| 4065 |
|
|
|
| 4066 |
|
|
end
|
| 4067 |
|
|
endgenerate
|
| 4068 |
|
|
|
| 4069 |
6 |
unneback |
always @ (posedge clk_a)
|
| 4070 |
|
|
begin
|
| 4071 |
|
|
q_a <= ram[adr_a];
|
| 4072 |
|
|
if (we_a)
|
| 4073 |
|
|
ram[adr_a] <= d_a;
|
| 4074 |
|
|
end
|
| 4075 |
|
|
always @ (posedge clk_b)
|
| 4076 |
|
|
q_b <= ram[adr_b];
|
| 4077 |
|
|
endmodule
|
| 4078 |
40 |
unneback |
`endif
|
| 4079 |
6 |
unneback |
|
| 4080 |
100 |
unneback |
`ifdef DPRAM_1R2W
|
| 4081 |
|
|
`define MODULE dpram_1r2w
|
| 4082 |
|
|
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
|
| 4083 |
|
|
`undef MODULE
|
| 4084 |
|
|
|
| 4085 |
|
|
parameter data_width = 32;
|
| 4086 |
|
|
parameter addr_width = 8;
|
| 4087 |
|
|
parameter mem_size = 1<<addr_width;
|
| 4088 |
|
|
input [(data_width-1):0] d_a;
|
| 4089 |
|
|
input [(addr_width-1):0] adr_a;
|
| 4090 |
|
|
input [(addr_width-1):0] adr_b;
|
| 4091 |
|
|
input we_a;
|
| 4092 |
|
|
input [(data_width-1):0] d_b;
|
| 4093 |
|
|
output reg [(data_width-1):0] q_a;
|
| 4094 |
|
|
input we_b;
|
| 4095 |
|
|
input clk_a, clk_b;
|
| 4096 |
|
|
reg [(data_width-1):0] q_b;
|
| 4097 |
|
|
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
|
| 4098 |
|
|
|
| 4099 |
|
|
parameter memory_init = 0;
|
| 4100 |
|
|
parameter memory_file = "vl_ram.vmem";
|
| 4101 |
|
|
parameter debug = 0;
|
| 4102 |
|
|
|
| 4103 |
|
|
generate
|
| 4104 |
|
|
if (memory_init == 1) begin : init_mem
|
| 4105 |
|
|
initial
|
| 4106 |
|
|
$readmemh(memory_file, ram);
|
| 4107 |
|
|
end else if (memory_init == 2) begin : init_zero
|
| 4108 |
|
|
integer k;
|
| 4109 |
|
|
initial
|
| 4110 |
|
|
for (k = 0; k < mem_size; k = k + 1)
|
| 4111 |
|
|
ram[k] = 0;
|
| 4112 |
|
|
end
|
| 4113 |
|
|
endgenerate
|
| 4114 |
|
|
|
| 4115 |
|
|
generate
|
| 4116 |
|
|
if (debug==1) begin : debug_we
|
| 4117 |
|
|
always @ (posedge clk_a)
|
| 4118 |
|
|
if (we_a)
|
| 4119 |
|
|
$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
|
| 4120 |
|
|
always @ (posedge clk_b)
|
| 4121 |
|
|
if (we_b)
|
| 4122 |
|
|
$display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
|
| 4123 |
|
|
end
|
| 4124 |
|
|
endgenerate
|
| 4125 |
|
|
|
| 4126 |
|
|
always @ (posedge clk_a)
|
| 4127 |
|
|
begin
|
| 4128 |
|
|
q_a <= ram[adr_a];
|
| 4129 |
|
|
if (we_a)
|
| 4130 |
|
|
ram[adr_a] <= d_a;
|
| 4131 |
|
|
end
|
| 4132 |
|
|
always @ (posedge clk_b)
|
| 4133 |
|
|
begin
|
| 4134 |
|
|
if (we_b)
|
| 4135 |
|
|
ram[adr_b] <= d_b;
|
| 4136 |
|
|
end
|
| 4137 |
|
|
endmodule
|
| 4138 |
|
|
`endif
|
| 4139 |
|
|
|
| 4140 |
40 |
unneback |
`ifdef DPRAM_2R2W
|
| 4141 |
|
|
`define MODULE dpram_2r2w
|
| 4142 |
|
|
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
|
| 4143 |
|
|
`undef MODULE
|
| 4144 |
|
|
|
| 4145 |
6 |
unneback |
parameter data_width = 32;
|
| 4146 |
|
|
parameter addr_width = 8;
|
| 4147 |
75 |
unneback |
parameter mem_size = 1<<addr_width;
|
| 4148 |
6 |
unneback |
input [(data_width-1):0] d_a;
|
| 4149 |
|
|
input [(addr_width-1):0] adr_a;
|
| 4150 |
|
|
input [(addr_width-1):0] adr_b;
|
| 4151 |
|
|
input we_a;
|
| 4152 |
|
|
output [(data_width-1):0] q_b;
|
| 4153 |
|
|
input [(data_width-1):0] d_b;
|
| 4154 |
|
|
output reg [(data_width-1):0] q_a;
|
| 4155 |
|
|
input we_b;
|
| 4156 |
|
|
input clk_a, clk_b;
|
| 4157 |
|
|
reg [(data_width-1):0] q_b;
|
| 4158 |
98 |
unneback |
reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
|
| 4159 |
7 |
unneback |
|
| 4160 |
100 |
unneback |
parameter memory_init = 0;
|
| 4161 |
|
|
parameter memory_file = "vl_ram.vmem";
|
| 4162 |
|
|
parameter debug = 0;
|
| 4163 |
|
|
|
| 4164 |
|
|
generate
|
| 4165 |
|
|
if (memory_init) begin : init_mem
|
| 4166 |
|
|
initial
|
| 4167 |
|
|
$readmemh(memory_file, ram);
|
| 4168 |
|
|
end else if (memory_init == 2) begin : init_zero
|
| 4169 |
|
|
integer k;
|
| 4170 |
|
|
initial
|
| 4171 |
|
|
for (k = 0; k < mem_size; k = k + 1)
|
| 4172 |
|
|
ram[k] = 0;
|
| 4173 |
|
|
end
|
| 4174 |
7 |
unneback |
endgenerate
|
| 4175 |
|
|
|
| 4176 |
100 |
unneback |
generate
|
| 4177 |
|
|
if (debug==1) begin : debug_we
|
| 4178 |
|
|
always @ (posedge clk_a)
|
| 4179 |
|
|
if (we_a)
|
| 4180 |
|
|
$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
|
| 4181 |
|
|
always @ (posedge clk_b)
|
| 4182 |
|
|
if (we_b)
|
| 4183 |
|
|
$display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
|
| 4184 |
|
|
end
|
| 4185 |
|
|
endgenerate
|
| 4186 |
|
|
|
| 4187 |
6 |
unneback |
always @ (posedge clk_a)
|
| 4188 |
|
|
begin
|
| 4189 |
|
|
q_a <= ram[adr_a];
|
| 4190 |
|
|
if (we_a)
|
| 4191 |
|
|
ram[adr_a] <= d_a;
|
| 4192 |
|
|
end
|
| 4193 |
|
|
always @ (posedge clk_b)
|
| 4194 |
|
|
begin
|
| 4195 |
|
|
q_b <= ram[adr_b];
|
| 4196 |
|
|
if (we_b)
|
| 4197 |
|
|
ram[adr_b] <= d_b;
|
| 4198 |
|
|
end
|
| 4199 |
|
|
endmodule
|
| 4200 |
40 |
unneback |
`endif
|
| 4201 |
6 |
unneback |
|
| 4202 |
83 |
unneback |
|
| 4203 |
75 |
unneback |
`ifdef DPRAM_BE_2R2W
|
| 4204 |
|
|
`define MODULE dpram_be_2r2w
|
| 4205 |
92 |
unneback |
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
|
| 4206 |
75 |
unneback |
`undef MODULE
|
| 4207 |
|
|
|
| 4208 |
|
|
parameter a_data_width = 32;
|
| 4209 |
|
|
parameter a_addr_width = 8;
|
| 4210 |
95 |
unneback |
parameter b_data_width = 64; //a_data_width;
|
| 4211 |
91 |
unneback |
localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
|
| 4212 |
95 |
unneback |
localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
|
| 4213 |
|
|
parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
|
| 4214 |
91 |
unneback |
|
| 4215 |
100 |
unneback |
parameter memory_init = 0;
|
| 4216 |
95 |
unneback |
parameter memory_file = "vl_ram.vmem";
|
| 4217 |
100 |
unneback |
parameter debug = 0;
|
| 4218 |
95 |
unneback |
|
| 4219 |
75 |
unneback |
input [(a_data_width-1):0] d_a;
|
| 4220 |
91 |
unneback |
input [(a_addr_width-1):0] adr_a;
|
| 4221 |
|
|
input [(a_data_width/8-1):0] be_a;
|
| 4222 |
|
|
input we_a;
|
| 4223 |
75 |
unneback |
output reg [(a_data_width-1):0] q_a;
|
| 4224 |
91 |
unneback |
input [(b_data_width-1):0] d_b;
|
| 4225 |
|
|
input [(b_addr_width-1):0] adr_b;
|
| 4226 |
92 |
unneback |
input [(b_data_width/8-1):0] be_b;
|
| 4227 |
|
|
input we_b;
|
| 4228 |
|
|
output reg [(b_data_width-1):0] q_b;
|
| 4229 |
91 |
unneback |
input clk_a, clk_b;
|
| 4230 |
75 |
unneback |
|
| 4231 |
100 |
unneback |
generate
|
| 4232 |
|
|
if (debug==1) begin : debug_we
|
| 4233 |
|
|
always @ (posedge clk_a)
|
| 4234 |
|
|
if (we_a)
|
| 4235 |
|
|
$display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
|
| 4236 |
|
|
always @ (posedge clk_b)
|
| 4237 |
|
|
if (we_b)
|
| 4238 |
|
|
$display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
|
| 4239 |
|
|
end
|
| 4240 |
|
|
endgenerate
|
| 4241 |
|
|
|
| 4242 |
|
|
|
| 4243 |
91 |
unneback |
`ifdef SYSTEMVERILOG
|
| 4244 |
|
|
// use a multi-dimensional packed array
|
| 4245 |
|
|
//to model individual bytes within the word
|
| 4246 |
|
|
|
| 4247 |
75 |
unneback |
generate
|
| 4248 |
91 |
unneback |
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
|
| 4249 |
75 |
unneback |
|
| 4250 |
98 |
unneback |
logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
|
| 4251 |
95 |
unneback |
|
| 4252 |
|
|
initial
|
| 4253 |
100 |
unneback |
if (memory_init==1)
|
| 4254 |
95 |
unneback |
$readmemh(memory_file, ram);
|
| 4255 |
100 |
unneback |
|
| 4256 |
|
|
integer k;
|
| 4257 |
|
|
initial
|
| 4258 |
|
|
if (memory_init==2)
|
| 4259 |
|
|
for (k = 0; k < mem_size; k = k + 1)
|
| 4260 |
|
|
ram[k] = 0;
|
| 4261 |
91 |
unneback |
|
| 4262 |
|
|
always_ff@(posedge clk_a)
|
| 4263 |
|
|
begin
|
| 4264 |
|
|
if(we_a) begin
|
| 4265 |
100 |
unneback |
if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
|
| 4266 |
|
|
if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
|
| 4267 |
|
|
if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
|
| 4268 |
|
|
if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
|
| 4269 |
91 |
unneback |
end
|
| 4270 |
|
|
end
|
| 4271 |
|
|
|
| 4272 |
92 |
unneback |
always@(posedge clk_a)
|
| 4273 |
|
|
q_a = ram[adr_a];
|
| 4274 |
91 |
unneback |
|
| 4275 |
|
|
always_ff@(posedge clk_b)
|
| 4276 |
92 |
unneback |
begin
|
| 4277 |
|
|
if(we_b) begin
|
| 4278 |
100 |
unneback |
if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
|
| 4279 |
|
|
if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
|
| 4280 |
|
|
if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
|
| 4281 |
|
|
if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
|
| 4282 |
92 |
unneback |
end
|
| 4283 |
|
|
end
|
| 4284 |
91 |
unneback |
|
| 4285 |
92 |
unneback |
always@(posedge clk_b)
|
| 4286 |
|
|
q_b = ram[adr_b];
|
| 4287 |
91 |
unneback |
|
| 4288 |
75 |
unneback |
end
|
| 4289 |
|
|
endgenerate
|
| 4290 |
|
|
|
| 4291 |
95 |
unneback |
generate
|
| 4292 |
|
|
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
|
| 4293 |
|
|
|
| 4294 |
98 |
unneback |
logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
|
| 4295 |
95 |
unneback |
|
| 4296 |
|
|
initial
|
| 4297 |
100 |
unneback |
if (memory_init==1)
|
| 4298 |
95 |
unneback |
$readmemh(memory_file, ram);
|
| 4299 |
100 |
unneback |
|
| 4300 |
|
|
integer k;
|
| 4301 |
|
|
initial
|
| 4302 |
|
|
if (memory_init==2)
|
| 4303 |
|
|
for (k = 0; k < mem_size; k = k + 1)
|
| 4304 |
|
|
ram[k] = 0;
|
| 4305 |
95 |
unneback |
|
| 4306 |
|
|
always_ff@(posedge clk_a)
|
| 4307 |
|
|
begin
|
| 4308 |
|
|
if(we_a) begin
|
| 4309 |
|
|
if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
|
| 4310 |
|
|
if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
|
| 4311 |
|
|
if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
|
| 4312 |
|
|
if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
|
| 4313 |
|
|
if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
|
| 4314 |
|
|
if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
|
| 4315 |
|
|
if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
|
| 4316 |
|
|
if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
|
| 4317 |
|
|
end
|
| 4318 |
|
|
end
|
| 4319 |
|
|
|
| 4320 |
|
|
always@(posedge clk_a)
|
| 4321 |
|
|
q_a = ram[adr_a];
|
| 4322 |
|
|
|
| 4323 |
|
|
always_ff@(posedge clk_b)
|
| 4324 |
|
|
begin
|
| 4325 |
|
|
if(we_b) begin
|
| 4326 |
|
|
if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
|
| 4327 |
|
|
if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
|
| 4328 |
|
|
if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
|
| 4329 |
|
|
if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
|
| 4330 |
|
|
if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
|
| 4331 |
|
|
if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
|
| 4332 |
|
|
if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
|
| 4333 |
|
|
if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
|
| 4334 |
|
|
end
|
| 4335 |
|
|
end
|
| 4336 |
|
|
|
| 4337 |
|
|
always@(posedge clk_b)
|
| 4338 |
|
|
q_b = ram[adr_b];
|
| 4339 |
|
|
|
| 4340 |
|
|
end
|
| 4341 |
|
|
endgenerate
|
| 4342 |
|
|
|
| 4343 |
|
|
generate
|
| 4344 |
|
|
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
|
| 4345 |
|
|
logic [31:0] temp;
|
| 4346 |
|
|
`define MODULE dpram_be_2r2w
|
| 4347 |
111 |
unneback |
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
|
| 4348 |
95 |
unneback |
`undef MODULE
|
| 4349 |
|
|
dpram6464 (
|
| 4350 |
|
|
.d_a(d_a),
|
| 4351 |
|
|
.q_a(q_a),
|
| 4352 |
|
|
.adr_a(adr_a),
|
| 4353 |
|
|
.be_a(be_a),
|
| 4354 |
|
|
.we_a(we_a),
|
| 4355 |
|
|
.clk_a(clk_a),
|
| 4356 |
|
|
.d_b({d_b,d_b}),
|
| 4357 |
|
|
.q_b(temp),
|
| 4358 |
|
|
.adr_b(adr_b),
|
| 4359 |
|
|
.be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
|
| 4360 |
|
|
.we_b(we_b),
|
| 4361 |
|
|
.clk_b(clk_b)
|
| 4362 |
|
|
);
|
| 4363 |
|
|
|
| 4364 |
100 |
unneback |
always @ (adr_b[0] or temp)
|
| 4365 |
95 |
unneback |
if (adr_b[0])
|
| 4366 |
|
|
q_b = temp[31:16];
|
| 4367 |
|
|
else
|
| 4368 |
|
|
q_b = temp[15:0];
|
| 4369 |
|
|
|
| 4370 |
|
|
end
|
| 4371 |
|
|
endgenerate
|
| 4372 |
|
|
|
| 4373 |
|
|
generate
|
| 4374 |
|
|
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
|
| 4375 |
|
|
logic [63:0] temp;
|
| 4376 |
|
|
`define MODULE dpram_be_2r2w
|
| 4377 |
111 |
unneback |
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
|
| 4378 |
95 |
unneback |
`undef MODULE
|
| 4379 |
|
|
dpram6464 (
|
| 4380 |
|
|
.d_a({d_a,d_a}),
|
| 4381 |
|
|
.q_a(temp),
|
| 4382 |
|
|
.adr_a(adr_a[a_addr_width-1:1]),
|
| 4383 |
|
|
.be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
|
| 4384 |
|
|
.we_a(we_a),
|
| 4385 |
|
|
.clk_a(clk_a),
|
| 4386 |
|
|
.d_b(d_b),
|
| 4387 |
|
|
.q_b(q_b),
|
| 4388 |
|
|
.adr_b(adr_b),
|
| 4389 |
|
|
.be_b(be_b),
|
| 4390 |
|
|
.we_b(we_b),
|
| 4391 |
|
|
.clk_b(clk_b)
|
| 4392 |
|
|
);
|
| 4393 |
|
|
|
| 4394 |
100 |
unneback |
always @ (adr_a[0] or temp)
|
| 4395 |
95 |
unneback |
if (adr_a[0])
|
| 4396 |
|
|
q_a = temp[63:32];
|
| 4397 |
|
|
else
|
| 4398 |
|
|
q_a = temp[31:0];
|
| 4399 |
|
|
|
| 4400 |
|
|
end
|
| 4401 |
|
|
endgenerate
|
| 4402 |
|
|
|
| 4403 |
91 |
unneback |
`else
|
| 4404 |
92 |
unneback |
// This modules requires SystemVerilog
|
| 4405 |
98 |
unneback |
// at this point anyway
|
| 4406 |
91 |
unneback |
`endif
|
| 4407 |
75 |
unneback |
endmodule
|
| 4408 |
|
|
`endif
|
| 4409 |
|
|
|
| 4410 |
91 |
unneback |
`ifdef CAM
|
| 4411 |
6 |
unneback |
// Content addresable memory, CAM
|
| 4412 |
91 |
unneback |
`endif
|
| 4413 |
6 |
unneback |
|
| 4414 |
40 |
unneback |
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
|
| 4415 |
6 |
unneback |
// FIFO
|
| 4416 |
40 |
unneback |
`define MODULE fifo_1r1w_fill_level_sync
|
| 4417 |
|
|
module `BASE`MODULE (
|
| 4418 |
|
|
`undef MODULE
|
| 4419 |
25 |
unneback |
d, wr, fifo_full,
|
| 4420 |
|
|
q, rd, fifo_empty,
|
| 4421 |
|
|
fill_level,
|
| 4422 |
|
|
clk, rst
|
| 4423 |
|
|
);
|
| 4424 |
|
|
|
| 4425 |
|
|
parameter data_width = 18;
|
| 4426 |
|
|
parameter addr_width = 4;
|
| 4427 |
6 |
unneback |
|
| 4428 |
25 |
unneback |
// write side
|
| 4429 |
|
|
input [data_width-1:0] d;
|
| 4430 |
|
|
input wr;
|
| 4431 |
|
|
output fifo_full;
|
| 4432 |
|
|
// read side
|
| 4433 |
|
|
output [data_width-1:0] q;
|
| 4434 |
|
|
input rd;
|
| 4435 |
|
|
output fifo_empty;
|
| 4436 |
|
|
// common
|
| 4437 |
|
|
output [addr_width:0] fill_level;
|
| 4438 |
|
|
input rst, clk;
|
| 4439 |
|
|
|
| 4440 |
|
|
wire [addr_width:1] wadr, radr;
|
| 4441 |
|
|
|
| 4442 |
40 |
unneback |
`define MODULE cnt_bin_ce
|
| 4443 |
|
|
`BASE`MODULE
|
| 4444 |
25 |
unneback |
# ( .length(addr_width))
|
| 4445 |
|
|
fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
|
| 4446 |
40 |
unneback |
`BASE`MODULE
|
| 4447 |
25 |
unneback |
# (.length(addr_width))
|
| 4448 |
|
|
fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
|
| 4449 |
40 |
unneback |
`undef MODULE
|
| 4450 |
25 |
unneback |
|
| 4451 |
40 |
unneback |
`define MODULE dpram_1r1w
|
| 4452 |
|
|
`BASE`MODULE
|
| 4453 |
25 |
unneback |
# (.data_width(data_width), .addr_width(addr_width))
|
| 4454 |
|
|
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
|
| 4455 |
40 |
unneback |
`undef MODULE
|
| 4456 |
25 |
unneback |
|
| 4457 |
40 |
unneback |
`define MODULE cnt_bin_ce_rew_q_zq_l1
|
| 4458 |
|
|
`BASE`MODULE
|
| 4459 |
27 |
unneback |
# (.length(addr_width+1), .level1_value(1<<addr_width))
|
| 4460 |
25 |
unneback |
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
|
| 4461 |
40 |
unneback |
`undef MODULE
|
| 4462 |
25 |
unneback |
endmodule
|
| 4463 |
40 |
unneback |
`endif
|
| 4464 |
25 |
unneback |
|
| 4465 |
40 |
unneback |
`ifdef FIFO_2R2W_SYNC_SIMPLEX
|
| 4466 |
27 |
unneback |
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
|
| 4467 |
|
|
// RAM is supposed to be larger than the two FIFOs
|
| 4468 |
|
|
// LFSR counters used adr pointers
|
| 4469 |
40 |
unneback |
`define MODULE fifo_2r2w_sync_simplex
|
| 4470 |
|
|
module `BASE`MODULE (
|
| 4471 |
|
|
`undef MODULE
|
| 4472 |
27 |
unneback |
// a side
|
| 4473 |
|
|
a_d, a_wr, a_fifo_full,
|
| 4474 |
|
|
a_q, a_rd, a_fifo_empty,
|
| 4475 |
|
|
a_fill_level,
|
| 4476 |
|
|
// b side
|
| 4477 |
|
|
b_d, b_wr, b_fifo_full,
|
| 4478 |
|
|
b_q, b_rd, b_fifo_empty,
|
| 4479 |
|
|
b_fill_level,
|
| 4480 |
|
|
// common
|
| 4481 |
|
|
clk, rst
|
| 4482 |
|
|
);
|
| 4483 |
|
|
parameter data_width = 8;
|
| 4484 |
|
|
parameter addr_width = 5;
|
| 4485 |
|
|
parameter fifo_full_level = (1<<addr_width)-1;
|
| 4486 |
|
|
|
| 4487 |
|
|
// a side
|
| 4488 |
|
|
input [data_width-1:0] a_d;
|
| 4489 |
|
|
input a_wr;
|
| 4490 |
|
|
output a_fifo_full;
|
| 4491 |
|
|
output [data_width-1:0] a_q;
|
| 4492 |
|
|
input a_rd;
|
| 4493 |
|
|
output a_fifo_empty;
|
| 4494 |
|
|
output [addr_width-1:0] a_fill_level;
|
| 4495 |
|
|
|
| 4496 |
|
|
// b side
|
| 4497 |
|
|
input [data_width-1:0] b_d;
|
| 4498 |
|
|
input b_wr;
|
| 4499 |
|
|
output b_fifo_full;
|
| 4500 |
|
|
output [data_width-1:0] b_q;
|
| 4501 |
|
|
input b_rd;
|
| 4502 |
|
|
output b_fifo_empty;
|
| 4503 |
|
|
output [addr_width-1:0] b_fill_level;
|
| 4504 |
|
|
|
| 4505 |
|
|
input clk;
|
| 4506 |
|
|
input rst;
|
| 4507 |
|
|
|
| 4508 |
|
|
// adr_gen
|
| 4509 |
|
|
wire [addr_width:1] a_wadr, a_radr;
|
| 4510 |
|
|
wire [addr_width:1] b_wadr, b_radr;
|
| 4511 |
|
|
// dpram
|
| 4512 |
|
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
| 4513 |
|
|
|
| 4514 |
40 |
unneback |
`define MODULE cnt_lfsr_ce
|
| 4515 |
|
|
`BASE`MODULE
|
| 4516 |
27 |
unneback |
# ( .length(addr_width))
|
| 4517 |
|
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
|
| 4518 |
|
|
|
| 4519 |
40 |
unneback |
`BASE`MODULE
|
| 4520 |
27 |
unneback |
# (.length(addr_width))
|
| 4521 |
|
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
|
| 4522 |
|
|
|
| 4523 |
40 |
unneback |
`BASE`MODULE
|
| 4524 |
27 |
unneback |
# ( .length(addr_width))
|
| 4525 |
|
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
|
| 4526 |
|
|
|
| 4527 |
40 |
unneback |
`BASE`MODULE
|
| 4528 |
27 |
unneback |
# (.length(addr_width))
|
| 4529 |
|
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
|
| 4530 |
40 |
unneback |
`undef MODULE
|
| 4531 |
27 |
unneback |
|
| 4532 |
|
|
// mux read or write adr to DPRAM
|
| 4533 |
|
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
|
| 4534 |
|
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
|
| 4535 |
|
|
|
| 4536 |
40 |
unneback |
`define MODULE dpram_2r2w
|
| 4537 |
|
|
`BASE`MODULE
|
| 4538 |
27 |
unneback |
# (.data_width(data_width), .addr_width(addr_width+1))
|
| 4539 |
|
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
| 4540 |
|
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
| 4541 |
40 |
unneback |
`undef MODULE
|
| 4542 |
|
|
|
| 4543 |
|
|
`define MODULE cnt_bin_ce_rew_zq_l1
|
| 4544 |
|
|
`BASE`MODULE
|
| 4545 |
28 |
unneback |
# (.length(addr_width), .level1_value(fifo_full_level))
|
| 4546 |
27 |
unneback |
a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
|
| 4547 |
|
|
|
| 4548 |
40 |
unneback |
`BASE`MODULE
|
| 4549 |
28 |
unneback |
# (.length(addr_width), .level1_value(fifo_full_level))
|
| 4550 |
27 |
unneback |
b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
|
| 4551 |
40 |
unneback |
`undef MODULE
|
| 4552 |
27 |
unneback |
|
| 4553 |
|
|
endmodule
|
| 4554 |
40 |
unneback |
`endif
|
| 4555 |
27 |
unneback |
|
| 4556 |
40 |
unneback |
`ifdef FIFO_CMP_ASYNC
|
| 4557 |
|
|
`define MODULE fifo_cmp_async
|
| 4558 |
|
|
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
|
| 4559 |
|
|
`undef MODULE
|
| 4560 |
6 |
unneback |
|
| 4561 |
11 |
unneback |
parameter addr_width = 4;
|
| 4562 |
|
|
parameter N = addr_width-1;
|
| 4563 |
6 |
unneback |
|
| 4564 |
|
|
parameter Q1 = 2'b00;
|
| 4565 |
|
|
parameter Q2 = 2'b01;
|
| 4566 |
|
|
parameter Q3 = 2'b11;
|
| 4567 |
|
|
parameter Q4 = 2'b10;
|
| 4568 |
|
|
|
| 4569 |
|
|
parameter going_empty = 1'b0;
|
| 4570 |
|
|
parameter going_full = 1'b1;
|
| 4571 |
|
|
|
| 4572 |
|
|
input [N:0] wptr, rptr;
|
| 4573 |
14 |
unneback |
output fifo_empty;
|
| 4574 |
6 |
unneback |
output fifo_full;
|
| 4575 |
|
|
input wclk, rclk, rst;
|
| 4576 |
|
|
|
| 4577 |
|
|
`ifndef GENERATE_DIRECTION_AS_LATCH
|
| 4578 |
|
|
wire direction;
|
| 4579 |
|
|
`endif
|
| 4580 |
|
|
`ifdef GENERATE_DIRECTION_AS_LATCH
|
| 4581 |
|
|
reg direction;
|
| 4582 |
|
|
`endif
|
| 4583 |
|
|
reg direction_set, direction_clr;
|
| 4584 |
|
|
|
| 4585 |
|
|
wire async_empty, async_full;
|
| 4586 |
|
|
wire fifo_full2;
|
| 4587 |
14 |
unneback |
wire fifo_empty2;
|
| 4588 |
6 |
unneback |
|
| 4589 |
|
|
// direction_set
|
| 4590 |
|
|
always @ (wptr[N:N-1] or rptr[N:N-1])
|
| 4591 |
|
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
| 4592 |
|
|
{Q1,Q2} : direction_set <= 1'b1;
|
| 4593 |
|
|
{Q2,Q3} : direction_set <= 1'b1;
|
| 4594 |
|
|
{Q3,Q4} : direction_set <= 1'b1;
|
| 4595 |
|
|
{Q4,Q1} : direction_set <= 1'b1;
|
| 4596 |
|
|
default : direction_set <= 1'b0;
|
| 4597 |
|
|
endcase
|
| 4598 |
|
|
|
| 4599 |
|
|
// direction_clear
|
| 4600 |
|
|
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
|
| 4601 |
|
|
if (rst)
|
| 4602 |
|
|
direction_clr <= 1'b1;
|
| 4603 |
|
|
else
|
| 4604 |
|
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
| 4605 |
|
|
{Q2,Q1} : direction_clr <= 1'b1;
|
| 4606 |
|
|
{Q3,Q2} : direction_clr <= 1'b1;
|
| 4607 |
|
|
{Q4,Q3} : direction_clr <= 1'b1;
|
| 4608 |
|
|
{Q1,Q4} : direction_clr <= 1'b1;
|
| 4609 |
|
|
default : direction_clr <= 1'b0;
|
| 4610 |
|
|
endcase
|
| 4611 |
|
|
|
| 4612 |
40 |
unneback |
`define MODULE dff_sr
|
| 4613 |
6 |
unneback |
`ifndef GENERATE_DIRECTION_AS_LATCH
|
| 4614 |
40 |
unneback |
`BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
|
| 4615 |
6 |
unneback |
`endif
|
| 4616 |
|
|
|
| 4617 |
|
|
`ifdef GENERATE_DIRECTION_AS_LATCH
|
| 4618 |
|
|
always @ (posedge direction_set or posedge direction_clr)
|
| 4619 |
|
|
if (direction_clr)
|
| 4620 |
|
|
direction <= going_empty;
|
| 4621 |
|
|
else
|
| 4622 |
|
|
direction <= going_full;
|
| 4623 |
|
|
`endif
|
| 4624 |
|
|
|
| 4625 |
|
|
assign async_empty = (wptr == rptr) && (direction==going_empty);
|
| 4626 |
|
|
assign async_full = (wptr == rptr) && (direction==going_full);
|
| 4627 |
|
|
|
| 4628 |
40 |
unneback |
`BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
|
| 4629 |
|
|
`BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
|
| 4630 |
|
|
`undef MODULE
|
| 4631 |
6 |
unneback |
|
| 4632 |
|
|
/*
|
| 4633 |
|
|
always @ (posedge wclk or posedge rst or posedge async_full)
|
| 4634 |
|
|
if (rst)
|
| 4635 |
|
|
{fifo_full, fifo_full2} <= 2'b00;
|
| 4636 |
|
|
else if (async_full)
|
| 4637 |
|
|
{fifo_full, fifo_full2} <= 2'b11;
|
| 4638 |
|
|
else
|
| 4639 |
|
|
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
|
| 4640 |
|
|
*/
|
| 4641 |
14 |
unneback |
/* always @ (posedge rclk or posedge async_empty)
|
| 4642 |
6 |
unneback |
if (async_empty)
|
| 4643 |
|
|
{fifo_empty, fifo_empty2} <= 2'b11;
|
| 4644 |
|
|
else
|
| 4645 |
14 |
unneback |
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
|
| 4646 |
40 |
unneback |
`define MODULE dff
|
| 4647 |
|
|
`BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
|
| 4648 |
|
|
`BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
|
| 4649 |
|
|
`undef MODULE
|
| 4650 |
27 |
unneback |
endmodule // async_compb
|
| 4651 |
40 |
unneback |
`endif
|
| 4652 |
6 |
unneback |
|
| 4653 |
40 |
unneback |
`ifdef FIFO_1R1W_ASYNC
|
| 4654 |
|
|
`define MODULE fifo_1r1w_async
|
| 4655 |
|
|
module `BASE`MODULE (
|
| 4656 |
|
|
`undef MODULE
|
| 4657 |
6 |
unneback |
d, wr, fifo_full, wr_clk, wr_rst,
|
| 4658 |
|
|
q, rd, fifo_empty, rd_clk, rd_rst
|
| 4659 |
|
|
);
|
| 4660 |
|
|
|
| 4661 |
|
|
parameter data_width = 18;
|
| 4662 |
|
|
parameter addr_width = 4;
|
| 4663 |
|
|
|
| 4664 |
|
|
// write side
|
| 4665 |
|
|
input [data_width-1:0] d;
|
| 4666 |
|
|
input wr;
|
| 4667 |
|
|
output fifo_full;
|
| 4668 |
|
|
input wr_clk;
|
| 4669 |
|
|
input wr_rst;
|
| 4670 |
|
|
// read side
|
| 4671 |
|
|
output [data_width-1:0] q;
|
| 4672 |
|
|
input rd;
|
| 4673 |
|
|
output fifo_empty;
|
| 4674 |
|
|
input rd_clk;
|
| 4675 |
|
|
input rd_rst;
|
| 4676 |
|
|
|
| 4677 |
|
|
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
|
| 4678 |
23 |
unneback |
|
| 4679 |
40 |
unneback |
`define MODULE cnt_gray_ce_bin
|
| 4680 |
|
|
`BASE`MODULE
|
| 4681 |
6 |
unneback |
# ( .length(addr_width))
|
| 4682 |
|
|
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
|
| 4683 |
|
|
|
| 4684 |
40 |
unneback |
`BASE`MODULE
|
| 4685 |
6 |
unneback |
# (.length(addr_width))
|
| 4686 |
23 |
unneback |
fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
|
| 4687 |
40 |
unneback |
`undef MODULE
|
| 4688 |
6 |
unneback |
|
| 4689 |
40 |
unneback |
`define MODULE dpram_1r1w
|
| 4690 |
|
|
`BASE`MODULE
|
| 4691 |
6 |
unneback |
# (.data_width(data_width), .addr_width(addr_width))
|
| 4692 |
|
|
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
|
| 4693 |
40 |
unneback |
`undef MODULE
|
| 4694 |
6 |
unneback |
|
| 4695 |
40 |
unneback |
`define MODULE fifo_cmp_async
|
| 4696 |
|
|
`BASE`MODULE
|
| 4697 |
6 |
unneback |
# (.addr_width(addr_width))
|
| 4698 |
|
|
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
|
| 4699 |
40 |
unneback |
`undef MODULE
|
| 4700 |
6 |
unneback |
|
| 4701 |
|
|
endmodule
|
| 4702 |
40 |
unneback |
`endif
|
| 4703 |
6 |
unneback |
|
| 4704 |
40 |
unneback |
`ifdef FIFO_2R2W_ASYNC
|
| 4705 |
|
|
`define MODULE fifo_2r2w_async
|
| 4706 |
|
|
module `BASE`MODULE (
|
| 4707 |
|
|
`undef MODULE
|
| 4708 |
6 |
unneback |
// a side
|
| 4709 |
|
|
a_d, a_wr, a_fifo_full,
|
| 4710 |
|
|
a_q, a_rd, a_fifo_empty,
|
| 4711 |
|
|
a_clk, a_rst,
|
| 4712 |
|
|
// b side
|
| 4713 |
|
|
b_d, b_wr, b_fifo_full,
|
| 4714 |
|
|
b_q, b_rd, b_fifo_empty,
|
| 4715 |
|
|
b_clk, b_rst
|
| 4716 |
|
|
);
|
| 4717 |
|
|
|
| 4718 |
|
|
parameter data_width = 18;
|
| 4719 |
|
|
parameter addr_width = 4;
|
| 4720 |
|
|
|
| 4721 |
|
|
// a side
|
| 4722 |
|
|
input [data_width-1:0] a_d;
|
| 4723 |
|
|
input a_wr;
|
| 4724 |
|
|
output a_fifo_full;
|
| 4725 |
|
|
output [data_width-1:0] a_q;
|
| 4726 |
|
|
input a_rd;
|
| 4727 |
|
|
output a_fifo_empty;
|
| 4728 |
|
|
input a_clk;
|
| 4729 |
|
|
input a_rst;
|
| 4730 |
|
|
|
| 4731 |
|
|
// b side
|
| 4732 |
|
|
input [data_width-1:0] b_d;
|
| 4733 |
|
|
input b_wr;
|
| 4734 |
|
|
output b_fifo_full;
|
| 4735 |
|
|
output [data_width-1:0] b_q;
|
| 4736 |
|
|
input b_rd;
|
| 4737 |
|
|
output b_fifo_empty;
|
| 4738 |
|
|
input b_clk;
|
| 4739 |
|
|
input b_rst;
|
| 4740 |
|
|
|
| 4741 |
40 |
unneback |
`define MODULE fifo_1r1w_async
|
| 4742 |
|
|
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
|
| 4743 |
6 |
unneback |
vl_fifo_1r1w_async_a (
|
| 4744 |
|
|
.d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
|
| 4745 |
|
|
.q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
|
| 4746 |
|
|
);
|
| 4747 |
|
|
|
| 4748 |
40 |
unneback |
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
|
| 4749 |
6 |
unneback |
vl_fifo_1r1w_async_b (
|
| 4750 |
|
|
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
|
| 4751 |
|
|
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
|
| 4752 |
|
|
);
|
| 4753 |
40 |
unneback |
`undef MODULE
|
| 4754 |
|
|
|
| 4755 |
6 |
unneback |
endmodule
|
| 4756 |
40 |
unneback |
`endif
|
| 4757 |
6 |
unneback |
|
| 4758 |
40 |
unneback |
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
|
| 4759 |
|
|
`define MODULE fifo_2r2w_async_simplex
|
| 4760 |
|
|
module `BASE`MODULE (
|
| 4761 |
|
|
`undef MODULE
|
| 4762 |
6 |
unneback |
// a side
|
| 4763 |
|
|
a_d, a_wr, a_fifo_full,
|
| 4764 |
|
|
a_q, a_rd, a_fifo_empty,
|
| 4765 |
|
|
a_clk, a_rst,
|
| 4766 |
|
|
// b side
|
| 4767 |
|
|
b_d, b_wr, b_fifo_full,
|
| 4768 |
|
|
b_q, b_rd, b_fifo_empty,
|
| 4769 |
|
|
b_clk, b_rst
|
| 4770 |
|
|
);
|
| 4771 |
|
|
|
| 4772 |
|
|
parameter data_width = 18;
|
| 4773 |
|
|
parameter addr_width = 4;
|
| 4774 |
|
|
|
| 4775 |
|
|
// a side
|
| 4776 |
|
|
input [data_width-1:0] a_d;
|
| 4777 |
|
|
input a_wr;
|
| 4778 |
|
|
output a_fifo_full;
|
| 4779 |
|
|
output [data_width-1:0] a_q;
|
| 4780 |
|
|
input a_rd;
|
| 4781 |
|
|
output a_fifo_empty;
|
| 4782 |
|
|
input a_clk;
|
| 4783 |
|
|
input a_rst;
|
| 4784 |
|
|
|
| 4785 |
|
|
// b side
|
| 4786 |
|
|
input [data_width-1:0] b_d;
|
| 4787 |
|
|
input b_wr;
|
| 4788 |
|
|
output b_fifo_full;
|
| 4789 |
|
|
output [data_width-1:0] b_q;
|
| 4790 |
|
|
input b_rd;
|
| 4791 |
|
|
output b_fifo_empty;
|
| 4792 |
|
|
input b_clk;
|
| 4793 |
|
|
input b_rst;
|
| 4794 |
|
|
|
| 4795 |
|
|
// adr_gen
|
| 4796 |
|
|
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
|
| 4797 |
|
|
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
|
| 4798 |
|
|
// dpram
|
| 4799 |
|
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
| 4800 |
|
|
|
| 4801 |
40 |
unneback |
`define MODULE cnt_gray_ce_bin
|
| 4802 |
|
|
`BASE`MODULE
|
| 4803 |
6 |
unneback |
# ( .length(addr_width))
|
| 4804 |
|
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
|
| 4805 |
|
|
|
| 4806 |
40 |
unneback |
`BASE`MODULE
|
| 4807 |
6 |
unneback |
# (.length(addr_width))
|
| 4808 |
|
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
|
| 4809 |
|
|
|
| 4810 |
40 |
unneback |
`BASE`MODULE
|
| 4811 |
6 |
unneback |
# ( .length(addr_width))
|
| 4812 |
|
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
|
| 4813 |
|
|
|
| 4814 |
40 |
unneback |
`BASE`MODULE
|
| 4815 |
6 |
unneback |
# (.length(addr_width))
|
| 4816 |
|
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
|
| 4817 |
40 |
unneback |
`undef MODULE
|
| 4818 |
6 |
unneback |
|
| 4819 |
|
|
// mux read or write adr to DPRAM
|
| 4820 |
|
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
|
| 4821 |
|
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
|
| 4822 |
|
|
|
| 4823 |
40 |
unneback |
`define MODULE dpram_2r2w
|
| 4824 |
|
|
`BASE`MODULE
|
| 4825 |
6 |
unneback |
# (.data_width(data_width), .addr_width(addr_width+1))
|
| 4826 |
|
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
| 4827 |
|
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
| 4828 |
40 |
unneback |
`undef MODULE
|
| 4829 |
6 |
unneback |
|
| 4830 |
40 |
unneback |
`define MODULE fifo_cmp_async
|
| 4831 |
|
|
`BASE`MODULE
|
| 4832 |
6 |
unneback |
# (.addr_width(addr_width))
|
| 4833 |
|
|
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
|
| 4834 |
|
|
|
| 4835 |
40 |
unneback |
`BASE`MODULE
|
| 4836 |
6 |
unneback |
# (.addr_width(addr_width))
|
| 4837 |
|
|
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
|
| 4838 |
40 |
unneback |
`undef MODULE
|
| 4839 |
6 |
unneback |
|
| 4840 |
|
|
endmodule
|
| 4841 |
40 |
unneback |
`endif
|
| 4842 |
48 |
unneback |
|
| 4843 |
|
|
`ifdef REG_FILE
|
| 4844 |
|
|
`define MODULE reg_file
|
| 4845 |
|
|
module `BASE`MODULE (
|
| 4846 |
|
|
`undef MODULE
|
| 4847 |
|
|
a1, a2, a3, wd3, we3, rd1, rd2, clk
|
| 4848 |
|
|
);
|
| 4849 |
|
|
parameter data_width = 32;
|
| 4850 |
|
|
parameter addr_width = 5;
|
| 4851 |
|
|
input [addr_width-1:0] a1, a2, a3;
|
| 4852 |
|
|
input [data_width-1:0] wd3;
|
| 4853 |
|
|
input we3;
|
| 4854 |
|
|
output [data_width-1:0] rd1, rd2;
|
| 4855 |
|
|
input clk;
|
| 4856 |
|
|
|
| 4857 |
|
|
`ifdef ACTEL
|
| 4858 |
|
|
reg [data_width-1:0] wd3_reg;
|
| 4859 |
|
|
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
|
| 4860 |
|
|
reg we3_reg;
|
| 4861 |
98 |
unneback |
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
|
| 4862 |
|
|
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
|
| 4863 |
48 |
unneback |
always @ (posedge clk or posedge rst)
|
| 4864 |
|
|
if (rst)
|
| 4865 |
|
|
{wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
|
| 4866 |
|
|
else
|
| 4867 |
|
|
{wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
|
| 4868 |
|
|
|
| 4869 |
|
|
always @ (negedge clk)
|
| 4870 |
|
|
if (we3_reg)
|
| 4871 |
|
|
ram1[a3_reg] <= wd3;
|
| 4872 |
|
|
always @ (posedge clk)
|
| 4873 |
|
|
a1_reg <= a1;
|
| 4874 |
|
|
assign rd1 = ram1[a1_reg];
|
| 4875 |
|
|
|
| 4876 |
|
|
always @ (negedge clk)
|
| 4877 |
|
|
if (we3_reg)
|
| 4878 |
|
|
ram2[a3_reg] <= wd3;
|
| 4879 |
|
|
always @ (posedge clk)
|
| 4880 |
|
|
a2_reg <= a2;
|
| 4881 |
|
|
assign rd2 = ram2[a2_reg];
|
| 4882 |
|
|
|
| 4883 |
|
|
`else
|
| 4884 |
|
|
|
| 4885 |
|
|
`define MODULE dpram_1r1w
|
| 4886 |
|
|
`BASE`MODULE
|
| 4887 |
|
|
# ( .data_width(data_width), .addr_width(addr_width))
|
| 4888 |
|
|
ram1 (
|
| 4889 |
|
|
.d_a(wd3),
|
| 4890 |
|
|
.adr_a(a3),
|
| 4891 |
|
|
.we_a(we3),
|
| 4892 |
|
|
.clk_a(clk),
|
| 4893 |
|
|
.q_b(rd1),
|
| 4894 |
|
|
.adr_b(a1),
|
| 4895 |
|
|
.clk_b(clk) );
|
| 4896 |
|
|
|
| 4897 |
|
|
`BASE`MODULE
|
| 4898 |
|
|
# ( .data_width(data_width), .addr_width(addr_width))
|
| 4899 |
|
|
ram2 (
|
| 4900 |
|
|
.d_a(wd3),
|
| 4901 |
|
|
.adr_a(a3),
|
| 4902 |
|
|
.we_a(we3),
|
| 4903 |
|
|
.clk_a(clk),
|
| 4904 |
|
|
.q_b(rd2),
|
| 4905 |
|
|
.adr_b(a2),
|
| 4906 |
|
|
.clk_b(clk) );
|
| 4907 |
|
|
`undef MODULE
|
| 4908 |
|
|
|
| 4909 |
|
|
`endif
|
| 4910 |
|
|
|
| 4911 |
|
|
endmodule
|
| 4912 |
|
|
`endif
|
| 4913 |
12 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 4914 |
|
|
//// ////
|
| 4915 |
|
|
//// Versatile library, wishbone stuff ////
|
| 4916 |
|
|
//// ////
|
| 4917 |
|
|
//// Description ////
|
| 4918 |
|
|
//// Wishbone compliant modules ////
|
| 4919 |
|
|
//// ////
|
| 4920 |
|
|
//// ////
|
| 4921 |
|
|
//// To Do: ////
|
| 4922 |
|
|
//// - ////
|
| 4923 |
|
|
//// ////
|
| 4924 |
|
|
//// Author(s): ////
|
| 4925 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 4926 |
|
|
//// ORSoC AB ////
|
| 4927 |
|
|
//// ////
|
| 4928 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 4929 |
|
|
//// ////
|
| 4930 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
| 4931 |
|
|
//// ////
|
| 4932 |
|
|
//// This source file may be used and distributed without ////
|
| 4933 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 4934 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 4935 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 4936 |
|
|
//// ////
|
| 4937 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 4938 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 4939 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 4940 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 4941 |
|
|
//// later version. ////
|
| 4942 |
|
|
//// ////
|
| 4943 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 4944 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 4945 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 4946 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 4947 |
|
|
//// details. ////
|
| 4948 |
|
|
//// ////
|
| 4949 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 4950 |
|
|
//// Public License along with this source; if not, download it ////
|
| 4951 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 4952 |
|
|
//// ////
|
| 4953 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 4954 |
|
|
|
| 4955 |
75 |
unneback |
`ifdef WB_ADR_INC
|
| 4956 |
|
|
`timescale 1ns/1ns
|
| 4957 |
|
|
`define MODULE wb_adr_inc
|
| 4958 |
85 |
unneback |
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
|
| 4959 |
75 |
unneback |
`undef MODULE
|
| 4960 |
83 |
unneback |
parameter adr_width = 10;
|
| 4961 |
|
|
parameter max_burst_width = 4;
|
| 4962 |
85 |
unneback |
input cyc_i, stb_i, we_i;
|
| 4963 |
83 |
unneback |
input [2:0] cti_i;
|
| 4964 |
|
|
input [1:0] bte_i;
|
| 4965 |
|
|
input [adr_width-1:0] adr_i;
|
| 4966 |
|
|
output [adr_width-1:0] adr_o;
|
| 4967 |
|
|
output ack_o;
|
| 4968 |
|
|
input clk, rst;
|
| 4969 |
75 |
unneback |
|
| 4970 |
83 |
unneback |
reg [adr_width-1:0] adr;
|
| 4971 |
90 |
unneback |
wire [max_burst_width-1:0] to_adr;
|
| 4972 |
91 |
unneback |
reg [max_burst_width-1:0] last_adr;
|
| 4973 |
92 |
unneback |
reg last_cycle;
|
| 4974 |
|
|
localparam idle_or_eoc = 1'b0;
|
| 4975 |
|
|
localparam cyc_or_ws = 1'b1;
|
| 4976 |
90 |
unneback |
|
| 4977 |
91 |
unneback |
always @ (posedge clk or posedge rst)
|
| 4978 |
|
|
if (rst)
|
| 4979 |
|
|
last_adr <= {max_burst_width{1'b0}};
|
| 4980 |
|
|
else
|
| 4981 |
|
|
if (stb_i)
|
| 4982 |
92 |
unneback |
last_adr <=adr_o[max_burst_width-1:0];
|
| 4983 |
91 |
unneback |
|
| 4984 |
83 |
unneback |
generate
|
| 4985 |
|
|
if (max_burst_width==0) begin : inst_0
|
| 4986 |
97 |
unneback |
|
| 4987 |
|
|
reg ack_o;
|
| 4988 |
|
|
assign adr_o = adr_i;
|
| 4989 |
|
|
always @ (posedge clk or posedge rst)
|
| 4990 |
|
|
if (rst)
|
| 4991 |
|
|
ack_o <= 1'b0;
|
| 4992 |
|
|
else
|
| 4993 |
|
|
ack_o <= cyc_i & stb_i & !ack_o;
|
| 4994 |
|
|
|
| 4995 |
83 |
unneback |
end else begin
|
| 4996 |
|
|
|
| 4997 |
|
|
always @ (posedge clk or posedge rst)
|
| 4998 |
|
|
if (rst)
|
| 4999 |
92 |
unneback |
last_cycle <= idle_or_eoc;
|
| 5000 |
83 |
unneback |
else
|
| 5001 |
92 |
unneback |
last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
|
| 5002 |
|
|
(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
|
| 5003 |
|
|
(cyc_i & !stb_i) ? cyc_or_ws : //ws
|
| 5004 |
|
|
cyc_or_ws; // cyc
|
| 5005 |
|
|
assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
|
| 5006 |
85 |
unneback |
assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
|
| 5007 |
91 |
unneback |
(!stb_i) ? last_adr :
|
| 5008 |
92 |
unneback |
(last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
|
| 5009 |
85 |
unneback |
adr[max_burst_width-1:0];
|
| 5010 |
92 |
unneback |
assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
|
| 5011 |
97 |
unneback |
|
| 5012 |
83 |
unneback |
end
|
| 5013 |
|
|
endgenerate
|
| 5014 |
|
|
|
| 5015 |
|
|
generate
|
| 5016 |
|
|
if (max_burst_width==2) begin : inst_2
|
| 5017 |
|
|
always @ (posedge clk or posedge rst)
|
| 5018 |
|
|
if (rst)
|
| 5019 |
|
|
adr <= 2'h0;
|
| 5020 |
|
|
else
|
| 5021 |
|
|
if (cyc_i & stb_i)
|
| 5022 |
|
|
adr[1:0] <= to_adr[1:0] + 2'd1;
|
| 5023 |
75 |
unneback |
else
|
| 5024 |
83 |
unneback |
adr <= to_adr[1:0];
|
| 5025 |
|
|
end
|
| 5026 |
|
|
endgenerate
|
| 5027 |
|
|
|
| 5028 |
|
|
generate
|
| 5029 |
|
|
if (max_burst_width==3) begin : inst_3
|
| 5030 |
|
|
always @ (posedge clk or posedge rst)
|
| 5031 |
|
|
if (rst)
|
| 5032 |
|
|
adr <= 3'h0;
|
| 5033 |
|
|
else
|
| 5034 |
|
|
if (cyc_i & stb_i)
|
| 5035 |
|
|
case (bte_i)
|
| 5036 |
|
|
2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
|
| 5037 |
|
|
default: adr[3:0] <= to_adr[2:0] + 3'd1;
|
| 5038 |
75 |
unneback |
endcase
|
| 5039 |
83 |
unneback |
else
|
| 5040 |
|
|
adr <= to_adr[2:0];
|
| 5041 |
|
|
end
|
| 5042 |
|
|
endgenerate
|
| 5043 |
|
|
|
| 5044 |
|
|
generate
|
| 5045 |
|
|
if (max_burst_width==4) begin : inst_4
|
| 5046 |
|
|
always @ (posedge clk or posedge rst)
|
| 5047 |
|
|
if (rst)
|
| 5048 |
|
|
adr <= 4'h0;
|
| 5049 |
|
|
else
|
| 5050 |
91 |
unneback |
if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
|
| 5051 |
83 |
unneback |
case (bte_i)
|
| 5052 |
|
|
2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
|
| 5053 |
|
|
2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
|
| 5054 |
|
|
default: adr[3:0] <= to_adr + 4'd1;
|
| 5055 |
|
|
endcase
|
| 5056 |
|
|
else
|
| 5057 |
|
|
adr <= to_adr[3:0];
|
| 5058 |
|
|
end
|
| 5059 |
|
|
endgenerate
|
| 5060 |
|
|
|
| 5061 |
|
|
generate
|
| 5062 |
|
|
if (adr_width > max_burst_width) begin : pass_through
|
| 5063 |
|
|
assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
|
| 5064 |
|
|
end
|
| 5065 |
|
|
endgenerate
|
| 5066 |
|
|
|
| 5067 |
|
|
endmodule
|
| 5068 |
75 |
unneback |
`endif
|
| 5069 |
|
|
|
| 5070 |
105 |
unneback |
`ifdef WB_B4_EOC
|
| 5071 |
|
|
`define MODULE wb_b4_eoc
|
| 5072 |
|
|
module `BASE`MODULE ( cyc_i, stb_i, stall_o, ack_o, busy, eoc, clk, rst);
|
| 5073 |
|
|
`undef MODULE
|
| 5074 |
|
|
input cyc_i, stb_i, ack_o;
|
| 5075 |
|
|
output busy, eoc;
|
| 5076 |
|
|
input clk, rst;
|
| 5077 |
|
|
|
| 5078 |
|
|
`define MODULE cnt_bin_ce_rew_zq_l1
|
| 5079 |
|
|
`BASE`MODULE # ( .length(4), level1_value(1))
|
| 5080 |
|
|
cnt0 (
|
| 5081 |
|
|
.cke(), .rew(), .zq(), .level1(), .rst(), clk);
|
| 5082 |
|
|
`undef MODULE
|
| 5083 |
|
|
|
| 5084 |
|
|
endmodule
|
| 5085 |
|
|
`endif
|
| 5086 |
|
|
|
| 5087 |
40 |
unneback |
`ifdef WB3WB3_BRIDGE
|
| 5088 |
12 |
unneback |
// async wb3 - wb3 bridge
|
| 5089 |
|
|
`timescale 1ns/1ns
|
| 5090 |
40 |
unneback |
`define MODULE wb3wb3_bridge
|
| 5091 |
|
|
module `BASE`MODULE (
|
| 5092 |
|
|
`undef MODULE
|
| 5093 |
12 |
unneback |
// wishbone slave side
|
| 5094 |
|
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
| 5095 |
|
|
// wishbone master side
|
| 5096 |
|
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
|
| 5097 |
|
|
|
| 5098 |
95 |
unneback |
parameter style = "FIFO"; // valid: simple, FIFO
|
| 5099 |
|
|
parameter addr_width = 4;
|
| 5100 |
|
|
|
| 5101 |
12 |
unneback |
input [31:0] wbs_dat_i;
|
| 5102 |
|
|
input [31:2] wbs_adr_i;
|
| 5103 |
|
|
input [3:0] wbs_sel_i;
|
| 5104 |
|
|
input [1:0] wbs_bte_i;
|
| 5105 |
|
|
input [2:0] wbs_cti_i;
|
| 5106 |
|
|
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
|
| 5107 |
|
|
output [31:0] wbs_dat_o;
|
| 5108 |
14 |
unneback |
output wbs_ack_o;
|
| 5109 |
12 |
unneback |
input wbs_clk, wbs_rst;
|
| 5110 |
|
|
|
| 5111 |
|
|
output [31:0] wbm_dat_o;
|
| 5112 |
|
|
output reg [31:2] wbm_adr_o;
|
| 5113 |
|
|
output [3:0] wbm_sel_o;
|
| 5114 |
|
|
output reg [1:0] wbm_bte_o;
|
| 5115 |
|
|
output reg [2:0] wbm_cti_o;
|
| 5116 |
14 |
unneback |
output reg wbm_we_o;
|
| 5117 |
|
|
output wbm_cyc_o;
|
| 5118 |
12 |
unneback |
output wbm_stb_o;
|
| 5119 |
|
|
input [31:0] wbm_dat_i;
|
| 5120 |
|
|
input wbm_ack_i;
|
| 5121 |
|
|
input wbm_clk, wbm_rst;
|
| 5122 |
|
|
|
| 5123 |
|
|
// bte
|
| 5124 |
|
|
parameter linear = 2'b00;
|
| 5125 |
|
|
parameter wrap4 = 2'b01;
|
| 5126 |
|
|
parameter wrap8 = 2'b10;
|
| 5127 |
|
|
parameter wrap16 = 2'b11;
|
| 5128 |
|
|
// cti
|
| 5129 |
|
|
parameter classic = 3'b000;
|
| 5130 |
|
|
parameter incburst = 3'b010;
|
| 5131 |
|
|
parameter endofburst = 3'b111;
|
| 5132 |
|
|
|
| 5133 |
95 |
unneback |
localparam wbs_adr = 1'b0;
|
| 5134 |
|
|
localparam wbs_data = 1'b1;
|
| 5135 |
12 |
unneback |
|
| 5136 |
95 |
unneback |
localparam wbm_adr0 = 2'b00;
|
| 5137 |
|
|
localparam wbm_adr1 = 2'b01;
|
| 5138 |
|
|
localparam wbm_data = 2'b10;
|
| 5139 |
|
|
localparam wbm_data_wait = 2'b11;
|
| 5140 |
12 |
unneback |
|
| 5141 |
|
|
reg [1:0] wbs_bte_reg;
|
| 5142 |
|
|
reg wbs;
|
| 5143 |
|
|
wire wbs_eoc_alert, wbm_eoc_alert;
|
| 5144 |
|
|
reg wbs_eoc, wbm_eoc;
|
| 5145 |
|
|
reg [1:0] wbm;
|
| 5146 |
|
|
|
| 5147 |
14 |
unneback |
wire [1:16] wbs_count, wbm_count;
|
| 5148 |
12 |
unneback |
|
| 5149 |
|
|
wire [35:0] a_d, a_q, b_d, b_q;
|
| 5150 |
|
|
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
|
| 5151 |
|
|
reg a_rd_reg;
|
| 5152 |
|
|
wire b_rd_adr, b_rd_data;
|
| 5153 |
14 |
unneback |
wire b_rd_data_reg;
|
| 5154 |
|
|
wire [35:0] temp;
|
| 5155 |
12 |
unneback |
|
| 5156 |
|
|
`define WE 5
|
| 5157 |
|
|
`define BTE 4:3
|
| 5158 |
|
|
`define CTI 2:0
|
| 5159 |
|
|
|
| 5160 |
|
|
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
|
| 5161 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
| 5162 |
|
|
if (wbs_rst)
|
| 5163 |
|
|
wbs_eoc <= 1'b0;
|
| 5164 |
|
|
else
|
| 5165 |
|
|
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
|
| 5166 |
78 |
unneback |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
|
| 5167 |
12 |
unneback |
else if (wbs_eoc_alert & (a_rd | a_wr))
|
| 5168 |
|
|
wbs_eoc <= 1'b1;
|
| 5169 |
|
|
|
| 5170 |
40 |
unneback |
`define MODULE cnt_shreg_ce_clear
|
| 5171 |
|
|
`BASE`MODULE # ( .length(16))
|
| 5172 |
|
|
`undef MODULE
|
| 5173 |
12 |
unneback |
cnt0 (
|
| 5174 |
|
|
.cke(wbs_ack_o),
|
| 5175 |
|
|
.clear(wbs_eoc),
|
| 5176 |
|
|
.q(wbs_count),
|
| 5177 |
|
|
.rst(wbs_rst),
|
| 5178 |
|
|
.clk(wbs_clk));
|
| 5179 |
|
|
|
| 5180 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
| 5181 |
|
|
if (wbs_rst)
|
| 5182 |
|
|
wbs <= wbs_adr;
|
| 5183 |
|
|
else
|
| 5184 |
75 |
unneback |
if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
|
| 5185 |
12 |
unneback |
wbs <= wbs_data;
|
| 5186 |
|
|
else if (wbs_eoc & wbs_ack_o)
|
| 5187 |
|
|
wbs <= wbs_adr;
|
| 5188 |
|
|
|
| 5189 |
|
|
// wbs FIFO
|
| 5190 |
75 |
unneback |
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
|
| 5191 |
|
|
assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
|
| 5192 |
12 |
unneback |
(wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full :
|
| 5193 |
|
|
1'b0;
|
| 5194 |
|
|
assign a_rd = !a_fifo_empty;
|
| 5195 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
| 5196 |
|
|
if (wbs_rst)
|
| 5197 |
|
|
a_rd_reg <= 1'b0;
|
| 5198 |
|
|
else
|
| 5199 |
|
|
a_rd_reg <= a_rd;
|
| 5200 |
|
|
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
|
| 5201 |
|
|
|
| 5202 |
|
|
assign wbs_dat_o = a_q[35:4];
|
| 5203 |
|
|
|
| 5204 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
| 5205 |
|
|
if (wbs_rst)
|
| 5206 |
13 |
unneback |
wbs_bte_reg <= 2'b00;
|
| 5207 |
12 |
unneback |
else
|
| 5208 |
13 |
unneback |
wbs_bte_reg <= wbs_bte_i;
|
| 5209 |
12 |
unneback |
|
| 5210 |
|
|
// wbm FIFO
|
| 5211 |
|
|
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
|
| 5212 |
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
| 5213 |
|
|
if (wbm_rst)
|
| 5214 |
|
|
wbm_eoc <= 1'b0;
|
| 5215 |
|
|
else
|
| 5216 |
|
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
| 5217 |
|
|
wbm_eoc <= b_q[`BTE] == linear;
|
| 5218 |
|
|
else if (wbm_eoc_alert & wbm_ack_i)
|
| 5219 |
|
|
wbm_eoc <= 1'b1;
|
| 5220 |
|
|
|
| 5221 |
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
| 5222 |
|
|
if (wbm_rst)
|
| 5223 |
|
|
wbm <= wbm_adr0;
|
| 5224 |
|
|
else
|
| 5225 |
33 |
unneback |
/*
|
| 5226 |
12 |
unneback |
if ((wbm==wbm_adr0 & !b_fifo_empty) |
|
| 5227 |
|
|
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
|
| 5228 |
|
|
(wbm==wbm_adr1 & !wbm_we_o) |
|
| 5229 |
|
|
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
|
| 5230 |
|
|
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
|
| 5231 |
33 |
unneback |
*/
|
| 5232 |
|
|
case (wbm)
|
| 5233 |
|
|
wbm_adr0:
|
| 5234 |
|
|
if (!b_fifo_empty)
|
| 5235 |
|
|
wbm <= wbm_adr1;
|
| 5236 |
|
|
wbm_adr1:
|
| 5237 |
|
|
if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
|
| 5238 |
|
|
wbm <= wbm_data;
|
| 5239 |
|
|
wbm_data:
|
| 5240 |
|
|
if (wbm_ack_i & wbm_eoc)
|
| 5241 |
|
|
wbm <= wbm_adr0;
|
| 5242 |
|
|
else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
|
| 5243 |
|
|
wbm <= wbm_data_wait;
|
| 5244 |
|
|
wbm_data_wait:
|
| 5245 |
|
|
if (!b_fifo_empty)
|
| 5246 |
|
|
wbm <= wbm_data;
|
| 5247 |
|
|
endcase
|
| 5248 |
12 |
unneback |
|
| 5249 |
|
|
assign b_d = {wbm_dat_i,4'b1111};
|
| 5250 |
|
|
assign b_wr = !wbm_we_o & wbm_ack_i;
|
| 5251 |
|
|
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
|
| 5252 |
|
|
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
|
| 5253 |
|
|
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
|
| 5254 |
33 |
unneback |
(wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
|
| 5255 |
12 |
unneback |
1'b0;
|
| 5256 |
|
|
assign b_rd = b_rd_adr | b_rd_data;
|
| 5257 |
|
|
|
| 5258 |
40 |
unneback |
`define MODULE dff
|
| 5259 |
|
|
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
|
| 5260 |
|
|
`undef MODULE
|
| 5261 |
|
|
`define MODULE dff_ce
|
| 5262 |
|
|
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
|
| 5263 |
|
|
`undef MODULE
|
| 5264 |
12 |
unneback |
|
| 5265 |
|
|
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
|
| 5266 |
|
|
|
| 5267 |
40 |
unneback |
`define MODULE cnt_shreg_ce_clear
|
| 5268 |
42 |
unneback |
`BASE`MODULE # ( .length(16))
|
| 5269 |
40 |
unneback |
`undef MODULE
|
| 5270 |
12 |
unneback |
cnt1 (
|
| 5271 |
|
|
.cke(wbm_ack_i),
|
| 5272 |
|
|
.clear(wbm_eoc),
|
| 5273 |
|
|
.q(wbm_count),
|
| 5274 |
|
|
.rst(wbm_rst),
|
| 5275 |
|
|
.clk(wbm_clk));
|
| 5276 |
|
|
|
| 5277 |
33 |
unneback |
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
|
| 5278 |
|
|
assign wbm_stb_o = (wbm==wbm_data);
|
| 5279 |
12 |
unneback |
|
| 5280 |
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
| 5281 |
|
|
if (wbm_rst)
|
| 5282 |
|
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
|
| 5283 |
|
|
else begin
|
| 5284 |
|
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
| 5285 |
|
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
|
| 5286 |
|
|
else if (wbm_eoc_alert & wbm_ack_i)
|
| 5287 |
|
|
wbm_cti_o <= endofburst;
|
| 5288 |
|
|
end
|
| 5289 |
|
|
|
| 5290 |
|
|
//async_fifo_dw_simplex_top
|
| 5291 |
40 |
unneback |
`define MODULE fifo_2r2w_async_simplex
|
| 5292 |
|
|
`BASE`MODULE
|
| 5293 |
|
|
`undef MODULE
|
| 5294 |
12 |
unneback |
# ( .data_width(36), .addr_width(addr_width))
|
| 5295 |
|
|
fifo (
|
| 5296 |
|
|
// a side
|
| 5297 |
|
|
.a_d(a_d),
|
| 5298 |
|
|
.a_wr(a_wr),
|
| 5299 |
|
|
.a_fifo_full(a_fifo_full),
|
| 5300 |
|
|
.a_q(a_q),
|
| 5301 |
|
|
.a_rd(a_rd),
|
| 5302 |
|
|
.a_fifo_empty(a_fifo_empty),
|
| 5303 |
|
|
.a_clk(wbs_clk),
|
| 5304 |
|
|
.a_rst(wbs_rst),
|
| 5305 |
|
|
// b side
|
| 5306 |
|
|
.b_d(b_d),
|
| 5307 |
|
|
.b_wr(b_wr),
|
| 5308 |
|
|
.b_fifo_full(b_fifo_full),
|
| 5309 |
|
|
.b_q(b_q),
|
| 5310 |
|
|
.b_rd(b_rd),
|
| 5311 |
|
|
.b_fifo_empty(b_fifo_empty),
|
| 5312 |
|
|
.b_clk(wbm_clk),
|
| 5313 |
|
|
.b_rst(wbm_rst)
|
| 5314 |
|
|
);
|
| 5315 |
|
|
|
| 5316 |
|
|
endmodule
|
| 5317 |
40 |
unneback |
`undef WE
|
| 5318 |
|
|
`undef BTE
|
| 5319 |
|
|
`undef CTI
|
| 5320 |
|
|
`endif
|
| 5321 |
17 |
unneback |
|
| 5322 |
75 |
unneback |
`ifdef WB3AVALON_BRIDGE
|
| 5323 |
|
|
`define MODULE wb3avalon_bridge
|
| 5324 |
|
|
module `BASE`MODULE (
|
| 5325 |
|
|
`undef MODULE
|
| 5326 |
|
|
// wishbone slave side
|
| 5327 |
|
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
| 5328 |
77 |
unneback |
// avalon master side
|
| 5329 |
75 |
unneback |
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
|
| 5330 |
|
|
|
| 5331 |
85 |
unneback |
parameter linewrapburst = 1'b0;
|
| 5332 |
|
|
|
| 5333 |
75 |
unneback |
input [31:0] wbs_dat_i;
|
| 5334 |
|
|
input [31:2] wbs_adr_i;
|
| 5335 |
|
|
input [3:0] wbs_sel_i;
|
| 5336 |
|
|
input [1:0] wbs_bte_i;
|
| 5337 |
|
|
input [2:0] wbs_cti_i;
|
| 5338 |
83 |
unneback |
input wbs_we_i;
|
| 5339 |
|
|
input wbs_cyc_i;
|
| 5340 |
|
|
input wbs_stb_i;
|
| 5341 |
75 |
unneback |
output [31:0] wbs_dat_o;
|
| 5342 |
|
|
output wbs_ack_o;
|
| 5343 |
|
|
input wbs_clk, wbs_rst;
|
| 5344 |
|
|
|
| 5345 |
|
|
input [31:0] readdata;
|
| 5346 |
|
|
output [31:0] writedata;
|
| 5347 |
|
|
output [31:2] address;
|
| 5348 |
|
|
output [3:0] be;
|
| 5349 |
|
|
output write;
|
| 5350 |
81 |
unneback |
output read;
|
| 5351 |
75 |
unneback |
output beginbursttransfer;
|
| 5352 |
|
|
output [3:0] burstcount;
|
| 5353 |
|
|
input readdatavalid;
|
| 5354 |
|
|
input waitrequest;
|
| 5355 |
|
|
input clk;
|
| 5356 |
|
|
input rst;
|
| 5357 |
|
|
|
| 5358 |
|
|
wire [1:0] wbm_bte_o;
|
| 5359 |
|
|
wire [2:0] wbm_cti_o;
|
| 5360 |
|
|
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
|
| 5361 |
|
|
reg last_cyc;
|
| 5362 |
79 |
unneback |
reg [3:0] counter;
|
| 5363 |
82 |
unneback |
reg read_busy;
|
| 5364 |
75 |
unneback |
|
| 5365 |
|
|
always @ (posedge clk or posedge rst)
|
| 5366 |
|
|
if (rst)
|
| 5367 |
|
|
last_cyc <= 1'b0;
|
| 5368 |
|
|
else
|
| 5369 |
|
|
last_cyc <= wbm_cyc_o;
|
| 5370 |
|
|
|
| 5371 |
79 |
unneback |
always @ (posedge clk or posedge rst)
|
| 5372 |
|
|
if (rst)
|
| 5373 |
82 |
unneback |
read_busy <= 1'b0;
|
| 5374 |
79 |
unneback |
else
|
| 5375 |
82 |
unneback |
if (read & !waitrequest)
|
| 5376 |
|
|
read_busy <= 1'b1;
|
| 5377 |
|
|
else if (wbm_ack_i & wbm_cti_o!=3'b010)
|
| 5378 |
|
|
read_busy <= 1'b0;
|
| 5379 |
|
|
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
|
| 5380 |
81 |
unneback |
|
| 5381 |
75 |
unneback |
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
|
| 5382 |
|
|
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
|
| 5383 |
|
|
(wbm_bte_o==2'b10) ? 4'd8 :
|
| 5384 |
78 |
unneback |
(wbm_bte_o==2'b11) ? 4'd16:
|
| 5385 |
|
|
4'd1;
|
| 5386 |
82 |
unneback |
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
|
| 5387 |
75 |
unneback |
|
| 5388 |
79 |
unneback |
always @ (posedge clk or posedge rst)
|
| 5389 |
|
|
if (rst) begin
|
| 5390 |
|
|
counter <= 4'd0;
|
| 5391 |
|
|
end else
|
| 5392 |
80 |
unneback |
if (wbm_we_o) begin
|
| 5393 |
|
|
if (!waitrequest & !last_cyc & wbm_cyc_o) begin
|
| 5394 |
85 |
unneback |
counter <= burstcount -4'd1;
|
| 5395 |
80 |
unneback |
end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
|
| 5396 |
|
|
counter <= burstcount;
|
| 5397 |
|
|
end else if (!waitrequest & wbm_stb_o) begin
|
| 5398 |
|
|
counter <= counter - 4'd1;
|
| 5399 |
|
|
end
|
| 5400 |
82 |
unneback |
end
|
| 5401 |
81 |
unneback |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
|
| 5402 |
79 |
unneback |
|
| 5403 |
75 |
unneback |
`define MODULE wb3wb3_bridge
|
| 5404 |
77 |
unneback |
`BASE`MODULE wbwb3inst (
|
| 5405 |
75 |
unneback |
`undef MODULE
|
| 5406 |
|
|
// wishbone slave side
|
| 5407 |
|
|
.wbs_dat_i(wbs_dat_i),
|
| 5408 |
|
|
.wbs_adr_i(wbs_adr_i),
|
| 5409 |
|
|
.wbs_sel_i(wbs_sel_i),
|
| 5410 |
|
|
.wbs_bte_i(wbs_bte_i),
|
| 5411 |
|
|
.wbs_cti_i(wbs_cti_i),
|
| 5412 |
|
|
.wbs_we_i(wbs_we_i),
|
| 5413 |
|
|
.wbs_cyc_i(wbs_cyc_i),
|
| 5414 |
|
|
.wbs_stb_i(wbs_stb_i),
|
| 5415 |
|
|
.wbs_dat_o(wbs_dat_o),
|
| 5416 |
|
|
.wbs_ack_o(wbs_ack_o),
|
| 5417 |
|
|
.wbs_clk(wbs_clk),
|
| 5418 |
|
|
.wbs_rst(wbs_rst),
|
| 5419 |
|
|
// wishbone master side
|
| 5420 |
|
|
.wbm_dat_o(writedata),
|
| 5421 |
78 |
unneback |
.wbm_adr_o(address),
|
| 5422 |
75 |
unneback |
.wbm_sel_o(be),
|
| 5423 |
|
|
.wbm_bte_o(wbm_bte_o),
|
| 5424 |
|
|
.wbm_cti_o(wbm_cti_o),
|
| 5425 |
|
|
.wbm_we_o(wbm_we_o),
|
| 5426 |
|
|
.wbm_cyc_o(wbm_cyc_o),
|
| 5427 |
|
|
.wbm_stb_o(wbm_stb_o),
|
| 5428 |
|
|
.wbm_dat_i(readdata),
|
| 5429 |
|
|
.wbm_ack_i(wbm_ack_i),
|
| 5430 |
|
|
.wbm_clk(clk),
|
| 5431 |
|
|
.wbm_rst(rst));
|
| 5432 |
|
|
|
| 5433 |
|
|
|
| 5434 |
|
|
endmodule
|
| 5435 |
|
|
`endif
|
| 5436 |
|
|
|
| 5437 |
105 |
unneback |
`ifdef WB_ARBITER
|
| 5438 |
|
|
`define MODULE wb_arbiter
|
| 5439 |
42 |
unneback |
module `BASE`MODULE (
|
| 5440 |
40 |
unneback |
`undef MODULE
|
| 5441 |
39 |
unneback |
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
|
| 5442 |
105 |
unneback |
wbm_dat_i, wbm_stall_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
|
| 5443 |
39 |
unneback |
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
| 5444 |
105 |
unneback |
wbs_dat_o, wbs_stall_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
|
| 5445 |
39 |
unneback |
wb_clk, wb_rst
|
| 5446 |
|
|
);
|
| 5447 |
|
|
|
| 5448 |
|
|
parameter nr_of_ports = 3;
|
| 5449 |
|
|
parameter adr_size = 26;
|
| 5450 |
|
|
parameter adr_lo = 2;
|
| 5451 |
|
|
parameter dat_size = 32;
|
| 5452 |
|
|
parameter sel_size = dat_size/8;
|
| 5453 |
|
|
|
| 5454 |
|
|
localparam aw = (adr_size - adr_lo) * nr_of_ports;
|
| 5455 |
|
|
localparam dw = dat_size * nr_of_ports;
|
| 5456 |
|
|
localparam sw = sel_size * nr_of_ports;
|
| 5457 |
|
|
localparam cw = 3 * nr_of_ports;
|
| 5458 |
|
|
localparam bw = 2 * nr_of_ports;
|
| 5459 |
|
|
|
| 5460 |
|
|
input [dw-1:0] wbm_dat_o;
|
| 5461 |
|
|
input [aw-1:0] wbm_adr_o;
|
| 5462 |
|
|
input [sw-1:0] wbm_sel_o;
|
| 5463 |
|
|
input [cw-1:0] wbm_cti_o;
|
| 5464 |
|
|
input [bw-1:0] wbm_bte_o;
|
| 5465 |
|
|
input [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
|
| 5466 |
|
|
output [dw-1:0] wbm_dat_i;
|
| 5467 |
105 |
unneback |
output [nr_of_ports-1:0] wbm_stall_o, wbm_ack_i, wbm_err_i, wbm_rty_i;
|
| 5468 |
39 |
unneback |
|
| 5469 |
|
|
output [dat_size-1:0] wbs_dat_i;
|
| 5470 |
|
|
output [adr_size-1:adr_lo] wbs_adr_i;
|
| 5471 |
|
|
output [sel_size-1:0] wbs_sel_i;
|
| 5472 |
|
|
output [2:0] wbs_cti_i;
|
| 5473 |
|
|
output [1:0] wbs_bte_i;
|
| 5474 |
|
|
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
| 5475 |
|
|
input [dat_size-1:0] wbs_dat_o;
|
| 5476 |
105 |
unneback |
input wbs_stall_o, wbs_ack_o, wbs_err_o, wbs_rty_o;
|
| 5477 |
39 |
unneback |
|
| 5478 |
|
|
input wb_clk, wb_rst;
|
| 5479 |
|
|
|
| 5480 |
44 |
unneback |
reg [nr_of_ports-1:0] select;
|
| 5481 |
39 |
unneback |
wire [nr_of_ports-1:0] state;
|
| 5482 |
|
|
wire [nr_of_ports-1:0] eoc; // end-of-cycle
|
| 5483 |
|
|
wire [nr_of_ports-1:0] sel;
|
| 5484 |
|
|
wire idle;
|
| 5485 |
|
|
|
| 5486 |
|
|
genvar i;
|
| 5487 |
|
|
|
| 5488 |
|
|
assign idle = !(|state);
|
| 5489 |
|
|
|
| 5490 |
|
|
generate
|
| 5491 |
|
|
if (nr_of_ports == 2) begin
|
| 5492 |
|
|
|
| 5493 |
|
|
wire [2:0] wbm1_cti_o, wbm0_cti_o;
|
| 5494 |
|
|
|
| 5495 |
|
|
assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
| 5496 |
|
|
|
| 5497 |
44 |
unneback |
//assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
| 5498 |
|
|
|
| 5499 |
|
|
always @ (idle or wbm_cyc_o)
|
| 5500 |
|
|
if (idle)
|
| 5501 |
|
|
casex (wbm_cyc_o)
|
| 5502 |
|
|
2'b1x : select = 2'b10;
|
| 5503 |
|
|
2'b01 : select = 2'b01;
|
| 5504 |
|
|
default : select = {nr_of_ports{1'b0}};
|
| 5505 |
|
|
endcase
|
| 5506 |
|
|
else
|
| 5507 |
|
|
select = {nr_of_ports{1'b0}};
|
| 5508 |
|
|
|
| 5509 |
39 |
unneback |
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
| 5510 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
| 5511 |
|
|
|
| 5512 |
|
|
end
|
| 5513 |
|
|
endgenerate
|
| 5514 |
|
|
|
| 5515 |
|
|
generate
|
| 5516 |
|
|
if (nr_of_ports == 3) begin
|
| 5517 |
|
|
|
| 5518 |
|
|
wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
| 5519 |
|
|
|
| 5520 |
|
|
assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
| 5521 |
|
|
|
| 5522 |
44 |
unneback |
always @ (idle or wbm_cyc_o)
|
| 5523 |
|
|
if (idle)
|
| 5524 |
|
|
casex (wbm_cyc_o)
|
| 5525 |
|
|
3'b1xx : select = 3'b100;
|
| 5526 |
|
|
3'b01x : select = 3'b010;
|
| 5527 |
|
|
3'b001 : select = 3'b001;
|
| 5528 |
|
|
default : select = {nr_of_ports{1'b0}};
|
| 5529 |
|
|
endcase
|
| 5530 |
|
|
else
|
| 5531 |
|
|
select = {nr_of_ports{1'b0}};
|
| 5532 |
|
|
|
| 5533 |
|
|
// assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
| 5534 |
39 |
unneback |
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
| 5535 |
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
| 5536 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
| 5537 |
|
|
|
| 5538 |
|
|
end
|
| 5539 |
|
|
endgenerate
|
| 5540 |
|
|
|
| 5541 |
|
|
generate
|
| 5542 |
44 |
unneback |
if (nr_of_ports == 4) begin
|
| 5543 |
|
|
|
| 5544 |
|
|
wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
| 5545 |
|
|
|
| 5546 |
|
|
assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
| 5547 |
|
|
|
| 5548 |
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
| 5549 |
|
|
|
| 5550 |
|
|
always @ (idle or wbm_cyc_o)
|
| 5551 |
|
|
if (idle)
|
| 5552 |
|
|
casex (wbm_cyc_o)
|
| 5553 |
|
|
4'b1xxx : select = 4'b1000;
|
| 5554 |
|
|
4'b01xx : select = 4'b0100;
|
| 5555 |
|
|
4'b001x : select = 4'b0010;
|
| 5556 |
|
|
4'b0001 : select = 4'b0001;
|
| 5557 |
|
|
default : select = {nr_of_ports{1'b0}};
|
| 5558 |
|
|
endcase
|
| 5559 |
|
|
else
|
| 5560 |
|
|
select = {nr_of_ports{1'b0}};
|
| 5561 |
|
|
|
| 5562 |
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
| 5563 |
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
| 5564 |
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
| 5565 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
| 5566 |
|
|
|
| 5567 |
|
|
end
|
| 5568 |
|
|
endgenerate
|
| 5569 |
|
|
|
| 5570 |
|
|
generate
|
| 5571 |
|
|
if (nr_of_ports == 5) begin
|
| 5572 |
|
|
|
| 5573 |
|
|
wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
| 5574 |
|
|
|
| 5575 |
|
|
assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
| 5576 |
|
|
|
| 5577 |
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
| 5578 |
|
|
|
| 5579 |
|
|
always @ (idle or wbm_cyc_o)
|
| 5580 |
|
|
if (idle)
|
| 5581 |
|
|
casex (wbm_cyc_o)
|
| 5582 |
|
|
5'b1xxxx : select = 5'b10000;
|
| 5583 |
|
|
5'b01xxx : select = 5'b01000;
|
| 5584 |
|
|
5'b001xx : select = 5'b00100;
|
| 5585 |
|
|
5'b0001x : select = 5'b00010;
|
| 5586 |
|
|
5'b00001 : select = 5'b00001;
|
| 5587 |
|
|
default : select = {nr_of_ports{1'b0}};
|
| 5588 |
|
|
endcase
|
| 5589 |
|
|
else
|
| 5590 |
|
|
select = {nr_of_ports{1'b0}};
|
| 5591 |
|
|
|
| 5592 |
|
|
assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
|
| 5593 |
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
| 5594 |
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
| 5595 |
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
| 5596 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
| 5597 |
|
|
|
| 5598 |
|
|
end
|
| 5599 |
|
|
endgenerate
|
| 5600 |
|
|
|
| 5601 |
|
|
generate
|
| 5602 |
67 |
unneback |
if (nr_of_ports == 6) begin
|
| 5603 |
|
|
|
| 5604 |
|
|
wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
| 5605 |
|
|
|
| 5606 |
|
|
assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
| 5607 |
|
|
|
| 5608 |
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
| 5609 |
|
|
|
| 5610 |
|
|
always @ (idle or wbm_cyc_o)
|
| 5611 |
|
|
if (idle)
|
| 5612 |
|
|
casex (wbm_cyc_o)
|
| 5613 |
|
|
6'b1xxxxx : select = 6'b100000;
|
| 5614 |
|
|
6'b01xxxx : select = 6'b010000;
|
| 5615 |
|
|
6'b001xxx : select = 6'b001000;
|
| 5616 |
|
|
6'b0001xx : select = 6'b000100;
|
| 5617 |
|
|
6'b00001x : select = 6'b000010;
|
| 5618 |
|
|
6'b000001 : select = 6'b000001;
|
| 5619 |
|
|
default : select = {nr_of_ports{1'b0}};
|
| 5620 |
|
|
endcase
|
| 5621 |
|
|
else
|
| 5622 |
|
|
select = {nr_of_ports{1'b0}};
|
| 5623 |
|
|
|
| 5624 |
|
|
assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
|
| 5625 |
|
|
assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
|
| 5626 |
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
| 5627 |
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
| 5628 |
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
| 5629 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
| 5630 |
|
|
|
| 5631 |
|
|
end
|
| 5632 |
|
|
endgenerate
|
| 5633 |
|
|
|
| 5634 |
|
|
generate
|
| 5635 |
|
|
if (nr_of_ports == 7) begin
|
| 5636 |
|
|
|
| 5637 |
|
|
wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
| 5638 |
|
|
|
| 5639 |
|
|
assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
| 5640 |
|
|
|
| 5641 |
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
| 5642 |
|
|
|
| 5643 |
|
|
always @ (idle or wbm_cyc_o)
|
| 5644 |
|
|
if (idle)
|
| 5645 |
|
|
casex (wbm_cyc_o)
|
| 5646 |
|
|
7'b1xxxxxx : select = 7'b1000000;
|
| 5647 |
|
|
7'b01xxxxx : select = 7'b0100000;
|
| 5648 |
|
|
7'b001xxxx : select = 7'b0010000;
|
| 5649 |
|
|
7'b0001xxx : select = 7'b0001000;
|
| 5650 |
|
|
7'b00001xx : select = 7'b0000100;
|
| 5651 |
|
|
7'b000001x : select = 7'b0000010;
|
| 5652 |
|
|
7'b0000001 : select = 7'b0000001;
|
| 5653 |
|
|
default : select = {nr_of_ports{1'b0}};
|
| 5654 |
|
|
endcase
|
| 5655 |
|
|
else
|
| 5656 |
|
|
select = {nr_of_ports{1'b0}};
|
| 5657 |
|
|
|
| 5658 |
|
|
assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
|
| 5659 |
|
|
assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
|
| 5660 |
|
|
assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
|
| 5661 |
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
| 5662 |
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
| 5663 |
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
| 5664 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
| 5665 |
|
|
|
| 5666 |
|
|
end
|
| 5667 |
|
|
endgenerate
|
| 5668 |
|
|
|
| 5669 |
|
|
generate
|
| 5670 |
|
|
if (nr_of_ports == 8) begin
|
| 5671 |
|
|
|
| 5672 |
|
|
wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
| 5673 |
|
|
|
| 5674 |
|
|
assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
| 5675 |
|
|
|
| 5676 |
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
| 5677 |
|
|
|
| 5678 |
|
|
always @ (idle or wbm_cyc_o)
|
| 5679 |
|
|
if (idle)
|
| 5680 |
|
|
casex (wbm_cyc_o)
|
| 5681 |
|
|
8'b1xxxxxxx : select = 8'b10000000;
|
| 5682 |
|
|
8'b01xxxxxx : select = 8'b01000000;
|
| 5683 |
|
|
8'b001xxxxx : select = 8'b00100000;
|
| 5684 |
|
|
8'b0001xxxx : select = 8'b00010000;
|
| 5685 |
|
|
8'b00001xxx : select = 8'b00001000;
|
| 5686 |
|
|
8'b000001xx : select = 8'b00000100;
|
| 5687 |
|
|
8'b0000001x : select = 8'b00000010;
|
| 5688 |
|
|
8'b00000001 : select = 8'b00000001;
|
| 5689 |
|
|
default : select = {nr_of_ports{1'b0}};
|
| 5690 |
|
|
endcase
|
| 5691 |
|
|
else
|
| 5692 |
|
|
select = {nr_of_ports{1'b0}};
|
| 5693 |
|
|
|
| 5694 |
|
|
assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
|
| 5695 |
|
|
assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
|
| 5696 |
|
|
assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
|
| 5697 |
|
|
assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
|
| 5698 |
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
| 5699 |
|
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
| 5700 |
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
| 5701 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
| 5702 |
|
|
|
| 5703 |
|
|
end
|
| 5704 |
|
|
endgenerate
|
| 5705 |
|
|
|
| 5706 |
|
|
generate
|
| 5707 |
63 |
unneback |
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
|
| 5708 |
42 |
unneback |
`define MODULE spr
|
| 5709 |
|
|
`BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
|
| 5710 |
|
|
`undef MODULE
|
| 5711 |
39 |
unneback |
end
|
| 5712 |
|
|
endgenerate
|
| 5713 |
|
|
|
| 5714 |
|
|
assign sel = select | state;
|
| 5715 |
|
|
|
| 5716 |
40 |
unneback |
`define MODULE mux_andor
|
| 5717 |
|
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
|
| 5718 |
|
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
|
| 5719 |
|
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
|
| 5720 |
|
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
|
| 5721 |
|
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
|
| 5722 |
|
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
|
| 5723 |
|
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
|
| 5724 |
|
|
`undef MODULE
|
| 5725 |
39 |
unneback |
assign wbs_cyc_i = |sel;
|
| 5726 |
|
|
|
| 5727 |
|
|
assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
|
| 5728 |
|
|
assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
|
| 5729 |
|
|
assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
|
| 5730 |
|
|
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
|
| 5731 |
|
|
|
| 5732 |
|
|
endmodule
|
| 5733 |
40 |
unneback |
`endif
|
| 5734 |
39 |
unneback |
|
| 5735 |
101 |
unneback |
`ifdef WB_RAM
|
| 5736 |
49 |
unneback |
// WB RAM with byte enable
|
| 5737 |
101 |
unneback |
`define MODULE wb_ram
|
| 5738 |
59 |
unneback |
module `BASE`MODULE (
|
| 5739 |
|
|
`undef MODULE
|
| 5740 |
69 |
unneback |
wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
| 5741 |
101 |
unneback |
wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
|
| 5742 |
59 |
unneback |
|
| 5743 |
101 |
unneback |
parameter adr_width = 16;
|
| 5744 |
|
|
parameter mem_size = 1<<adr_width;
|
| 5745 |
|
|
parameter dat_width = 32;
|
| 5746 |
|
|
parameter max_burst_width = 4; // only used for B3
|
| 5747 |
|
|
parameter mode = "B3"; // valid options: B3, B4
|
| 5748 |
60 |
unneback |
parameter memory_init = 1;
|
| 5749 |
|
|
parameter memory_file = "vl_ram.vmem";
|
| 5750 |
59 |
unneback |
|
| 5751 |
101 |
unneback |
input [dat_width-1:0] wbs_dat_i;
|
| 5752 |
|
|
input [adr_width-1:0] wbs_adr_i;
|
| 5753 |
|
|
input [2:0] wbs_cti_i;
|
| 5754 |
|
|
input [1:0] wbs_bte_i;
|
| 5755 |
|
|
input [dat_width/8-1:0] wbs_sel_i;
|
| 5756 |
70 |
unneback |
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
| 5757 |
101 |
unneback |
output [dat_width-1:0] wbs_dat_o;
|
| 5758 |
70 |
unneback |
output wbs_ack_o;
|
| 5759 |
101 |
unneback |
output wbs_stall_o;
|
| 5760 |
71 |
unneback |
input wb_clk, wb_rst;
|
| 5761 |
59 |
unneback |
|
| 5762 |
101 |
unneback |
wire [adr_width-1:0] adr;
|
| 5763 |
|
|
wire we;
|
| 5764 |
59 |
unneback |
|
| 5765 |
101 |
unneback |
generate
|
| 5766 |
|
|
if (mode=="B3") begin : B3_inst
|
| 5767 |
83 |
unneback |
`define MODULE wb_adr_inc
|
| 5768 |
101 |
unneback |
`BASE`MODULE # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
|
| 5769 |
83 |
unneback |
.cyc_i(wbs_cyc_i),
|
| 5770 |
|
|
.stb_i(wbs_stb_i),
|
| 5771 |
|
|
.cti_i(wbs_cti_i),
|
| 5772 |
|
|
.bte_i(wbs_bte_i),
|
| 5773 |
|
|
.adr_i(wbs_adr_i),
|
| 5774 |
85 |
unneback |
.we_i(wbs_we_i),
|
| 5775 |
83 |
unneback |
.ack_o(wbs_ack_o),
|
| 5776 |
|
|
.adr_o(adr),
|
| 5777 |
|
|
.clk(wb_clk),
|
| 5778 |
|
|
.rst(wb_rst));
|
| 5779 |
|
|
`undef MODULE
|
| 5780 |
101 |
unneback |
assign we = wbs_we_i & wbs_ack_o;
|
| 5781 |
|
|
end else if (mode=="B4") begin : B4_inst
|
| 5782 |
|
|
reg wbs_ack_o_reg;
|
| 5783 |
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
| 5784 |
|
|
if (wb_rst)
|
| 5785 |
|
|
wbs_ack_o_reg <= 1'b0;
|
| 5786 |
|
|
else
|
| 5787 |
|
|
wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
|
| 5788 |
|
|
assign wbs_ack_o = wbs_ack_o_reg;
|
| 5789 |
|
|
assign wbs_stall_o = 1'b0;
|
| 5790 |
|
|
assign adr = wbs_adr_i;
|
| 5791 |
|
|
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
|
| 5792 |
|
|
end
|
| 5793 |
|
|
endgenerate
|
| 5794 |
60 |
unneback |
|
| 5795 |
100 |
unneback |
`define MODULE ram_be
|
| 5796 |
|
|
`BASE`MODULE # (
|
| 5797 |
|
|
.data_width(dat_width),
|
| 5798 |
|
|
.addr_width(adr_width),
|
| 5799 |
|
|
.mem_size(mem_size),
|
| 5800 |
|
|
.memory_init(memory_init),
|
| 5801 |
|
|
.memory_file(memory_file))
|
| 5802 |
|
|
ram0(
|
| 5803 |
|
|
`undef MODULE
|
| 5804 |
101 |
unneback |
.d(wbs_dat_i),
|
| 5805 |
|
|
.adr(adr),
|
| 5806 |
|
|
.be(wbs_sel_i),
|
| 5807 |
|
|
.we(we),
|
| 5808 |
|
|
.q(wbs_dat_o),
|
| 5809 |
100 |
unneback |
.clk(wb_clk)
|
| 5810 |
|
|
);
|
| 5811 |
49 |
unneback |
|
| 5812 |
|
|
endmodule
|
| 5813 |
|
|
`endif
|
| 5814 |
|
|
|
| 5815 |
103 |
unneback |
`ifdef WB_SHADOW_RAM
|
| 5816 |
|
|
// A wishbone compliant RAM module that can be placed in front of other memory controllers
|
| 5817 |
|
|
`define MODULE wb_shadow_ram
|
| 5818 |
|
|
module `BASE`MODULE (
|
| 5819 |
|
|
`undef MODULE
|
| 5820 |
|
|
wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
| 5821 |
|
|
wbs_dat_o, wbs_ack_o, wbs_stall_o,
|
| 5822 |
|
|
wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
|
| 5823 |
|
|
wbm_dat_i, wbm_ack_i, wbm_stall_i,
|
| 5824 |
|
|
wb_clk, wb_rst);
|
| 5825 |
|
|
|
| 5826 |
|
|
parameter dat_width = 32;
|
| 5827 |
|
|
parameter mode = "B4";
|
| 5828 |
|
|
parameter max_burst_width = 4; // only used for B3
|
| 5829 |
|
|
|
| 5830 |
|
|
parameter shadow_mem_adr_width = 10;
|
| 5831 |
|
|
parameter shadow_mem_size = 1024;
|
| 5832 |
|
|
parameter shadow_mem_init = 2;
|
| 5833 |
|
|
parameter shadow_mem_file = "vl_ram.v";
|
| 5834 |
|
|
|
| 5835 |
|
|
parameter main_mem_adr_width = 24;
|
| 5836 |
|
|
|
| 5837 |
|
|
input [dat_width-1:0] wbs_dat_i;
|
| 5838 |
|
|
input [main_mem_adr_width-1:0] wbs_adr_i;
|
| 5839 |
|
|
input [2:0] wbs_cti_i;
|
| 5840 |
|
|
input [1:0] wbs_bte_i;
|
| 5841 |
|
|
input [dat_width/8-1:0] wbs_sel_i;
|
| 5842 |
|
|
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
| 5843 |
|
|
output [dat_width-1:0] wbs_dat_o;
|
| 5844 |
|
|
output wbs_ack_o;
|
| 5845 |
|
|
output wbs_stall_o;
|
| 5846 |
|
|
|
| 5847 |
|
|
output [dat_width-1:0] wbm_dat_o;
|
| 5848 |
|
|
output [main_mem_adr_width-1:0] wbm_adr_o;
|
| 5849 |
|
|
output [2:0] wbm_cti_o;
|
| 5850 |
|
|
output [1:0] wbm_bte_o;
|
| 5851 |
|
|
output [dat_width/8-1:0] wbm_sel_o;
|
| 5852 |
|
|
output wbm_we_o, wbm_stb_o, wbm_cyc_o;
|
| 5853 |
|
|
input [dat_width-1:0] wbm_dat_i;
|
| 5854 |
|
|
input wbm_ack_i, wbm_stall_i;
|
| 5855 |
|
|
|
| 5856 |
|
|
input wb_clk, wb_rst;
|
| 5857 |
|
|
|
| 5858 |
|
|
generate
|
| 5859 |
|
|
if (shadow_mem_size>0) begin : shadow_ram_inst
|
| 5860 |
|
|
|
| 5861 |
|
|
wire cyc;
|
| 5862 |
|
|
wire [dat_width-1:0] dat;
|
| 5863 |
|
|
wire stall, ack;
|
| 5864 |
|
|
|
| 5865 |
|
|
assign cyc = wbs_cyc_i & (wbs_adr_i<=shadow_mem_size);
|
| 5866 |
|
|
`define MODULE wb_ram
|
| 5867 |
|
|
`BASE`MODULE # (
|
| 5868 |
|
|
.dat_width(dat_width),
|
| 5869 |
|
|
.adr_width(shadow_mem_adr_width),
|
| 5870 |
|
|
.mem_size(shadow_mem_size),
|
| 5871 |
|
|
.memory_init(shadow_mem_init),
|
| 5872 |
|
|
.mode(mode))
|
| 5873 |
|
|
shadow_mem0 (
|
| 5874 |
|
|
.wbs_dat_i(wbs_dat_i),
|
| 5875 |
|
|
.wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),
|
| 5876 |
|
|
.wbs_sel_i(wbs_sel_i),
|
| 5877 |
|
|
.wbs_we_i (wbs_we_i),
|
| 5878 |
|
|
.wbs_bte_i(wbs_bte_i),
|
| 5879 |
|
|
.wbs_cti_i(wbs_cti_i),
|
| 5880 |
|
|
.wbs_stb_i(wbs_stb_i),
|
| 5881 |
|
|
.wbs_cyc_i(cyc),
|
| 5882 |
|
|
.wbs_dat_o(dat),
|
| 5883 |
|
|
.wbs_stall_o(stall),
|
| 5884 |
|
|
.wbs_ack_o(ack),
|
| 5885 |
|
|
.wb_clk(wb_clk),
|
| 5886 |
|
|
.wb_rst(wb_rst));
|
| 5887 |
|
|
`undef MODULE
|
| 5888 |
|
|
|
| 5889 |
|
|
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o} =
|
| 5890 |
|
|
{wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i};
|
| 5891 |
|
|
assign wbm_cyc_o = wbs_cyc_i & (wbs_adr_i>shadow_mem_size);
|
| 5892 |
|
|
|
| 5893 |
|
|
assign wbs_dat_o = (dat & {dat_width{cyc}}) | (wbm_dat_i & {dat_width{wbm_cyc_o}});
|
| 5894 |
|
|
assign wbs_ack_o = (ack & cyc) | (wbm_ack_i & wbm_cyc_o);
|
| 5895 |
|
|
assign wbs_stall_o = (stall & cyc) | (wbm_stall_i & wbm_cyc_o);
|
| 5896 |
|
|
|
| 5897 |
|
|
end else begin : no_shadow_ram_inst
|
| 5898 |
|
|
|
| 5899 |
|
|
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o} =
|
| 5900 |
|
|
{wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i};
|
| 5901 |
|
|
assign {wbs_dat_o, wbs_ack_o, wbs_stall_o} = {wbm_dat_i, wbm_ack_i, wbm_stall_i};
|
| 5902 |
|
|
|
| 5903 |
|
|
end
|
| 5904 |
|
|
endgenerate
|
| 5905 |
|
|
|
| 5906 |
|
|
endmodule
|
| 5907 |
|
|
`endif
|
| 5908 |
|
|
|
| 5909 |
48 |
unneback |
`ifdef WB_B4_ROM
|
| 5910 |
|
|
// WB ROM
|
| 5911 |
|
|
`define MODULE wb_b4_rom
|
| 5912 |
|
|
module `BASE`MODULE (
|
| 5913 |
|
|
`undef MODULE
|
| 5914 |
|
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
| 5915 |
|
|
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
|
| 5916 |
|
|
|
| 5917 |
|
|
parameter dat_width = 32;
|
| 5918 |
|
|
parameter dat_default = 32'h15000000;
|
| 5919 |
|
|
parameter adr_width = 32;
|
| 5920 |
|
|
|
| 5921 |
|
|
/*
|
| 5922 |
|
|
`ifndef ROM
|
| 5923 |
|
|
`define ROM "rom.v"
|
| 5924 |
|
|
`endif
|
| 5925 |
|
|
*/
|
| 5926 |
|
|
input [adr_width-1:2] wb_adr_i;
|
| 5927 |
|
|
input wb_stb_i;
|
| 5928 |
|
|
input wb_cyc_i;
|
| 5929 |
|
|
output [dat_width-1:0] wb_dat_o;
|
| 5930 |
|
|
reg [dat_width-1:0] wb_dat_o;
|
| 5931 |
|
|
output wb_ack_o;
|
| 5932 |
|
|
reg wb_ack_o;
|
| 5933 |
|
|
output stall_o;
|
| 5934 |
|
|
input wb_clk;
|
| 5935 |
|
|
input wb_rst;
|
| 5936 |
|
|
|
| 5937 |
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
| 5938 |
|
|
if (wb_rst)
|
| 5939 |
|
|
wb_dat_o <= {dat_width{1'b0}};
|
| 5940 |
|
|
else
|
| 5941 |
|
|
case (wb_adr_i[adr_width-1:2])
|
| 5942 |
|
|
`ifdef ROM
|
| 5943 |
|
|
`include `ROM
|
| 5944 |
|
|
`endif
|
| 5945 |
|
|
default:
|
| 5946 |
|
|
wb_dat_o <= dat_default;
|
| 5947 |
|
|
|
| 5948 |
|
|
endcase // case (wb_adr_i)
|
| 5949 |
|
|
|
| 5950 |
|
|
|
| 5951 |
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
| 5952 |
|
|
if (wb_rst)
|
| 5953 |
|
|
wb_ack_o <= 1'b0;
|
| 5954 |
|
|
else
|
| 5955 |
|
|
wb_ack_o <= wb_stb_i & wb_cyc_i;
|
| 5956 |
|
|
|
| 5957 |
|
|
assign stall_o = 1'b0;
|
| 5958 |
|
|
|
| 5959 |
|
|
endmodule
|
| 5960 |
|
|
`endif
|
| 5961 |
|
|
|
| 5962 |
|
|
|
| 5963 |
40 |
unneback |
`ifdef WB_BOOT_ROM
|
| 5964 |
17 |
unneback |
// WB ROM
|
| 5965 |
40 |
unneback |
`define MODULE wb_boot_rom
|
| 5966 |
|
|
module `BASE`MODULE (
|
| 5967 |
|
|
`undef MODULE
|
| 5968 |
17 |
unneback |
wb_adr_i, wb_stb_i, wb_cyc_i,
|
| 5969 |
18 |
unneback |
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
|
| 5970 |
17 |
unneback |
|
| 5971 |
18 |
unneback |
parameter adr_hi = 31;
|
| 5972 |
|
|
parameter adr_lo = 28;
|
| 5973 |
|
|
parameter adr_sel = 4'hf;
|
| 5974 |
|
|
parameter addr_width = 5;
|
| 5975 |
33 |
unneback |
/*
|
| 5976 |
17 |
unneback |
`ifndef BOOT_ROM
|
| 5977 |
|
|
`define BOOT_ROM "boot_rom.v"
|
| 5978 |
|
|
`endif
|
| 5979 |
33 |
unneback |
*/
|
| 5980 |
18 |
unneback |
input [adr_hi:2] wb_adr_i;
|
| 5981 |
|
|
input wb_stb_i;
|
| 5982 |
|
|
input wb_cyc_i;
|
| 5983 |
|
|
output [31:0] wb_dat_o;
|
| 5984 |
|
|
output wb_ack_o;
|
| 5985 |
|
|
output hit_o;
|
| 5986 |
|
|
input wb_clk;
|
| 5987 |
|
|
input wb_rst;
|
| 5988 |
|
|
|
| 5989 |
|
|
wire hit;
|
| 5990 |
|
|
reg [31:0] wb_dat;
|
| 5991 |
|
|
reg wb_ack;
|
| 5992 |
|
|
|
| 5993 |
|
|
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
|
| 5994 |
17 |
unneback |
|
| 5995 |
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
| 5996 |
|
|
if (wb_rst)
|
| 5997 |
18 |
unneback |
wb_dat <= 32'h15000000;
|
| 5998 |
17 |
unneback |
else
|
| 5999 |
18 |
unneback |
case (wb_adr_i[addr_width-1:2])
|
| 6000 |
33 |
unneback |
`ifdef BOOT_ROM
|
| 6001 |
17 |
unneback |
`include `BOOT_ROM
|
| 6002 |
33 |
unneback |
`endif
|
| 6003 |
17 |
unneback |
/*
|
| 6004 |
|
|
// Zero r0 and jump to 0x00000100
|
| 6005 |
18 |
unneback |
|
| 6006 |
|
|
1 : wb_dat <= 32'hA8200000;
|
| 6007 |
|
|
2 : wb_dat <= 32'hA8C00100;
|
| 6008 |
|
|
3 : wb_dat <= 32'h44003000;
|
| 6009 |
|
|
4 : wb_dat <= 32'h15000000;
|
| 6010 |
17 |
unneback |
*/
|
| 6011 |
|
|
default:
|
| 6012 |
18 |
unneback |
wb_dat <= 32'h00000000;
|
| 6013 |
17 |
unneback |
|
| 6014 |
|
|
endcase // case (wb_adr_i)
|
| 6015 |
|
|
|
| 6016 |
|
|
|
| 6017 |
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
| 6018 |
|
|
if (wb_rst)
|
| 6019 |
18 |
unneback |
wb_ack <= 1'b0;
|
| 6020 |
17 |
unneback |
else
|
| 6021 |
18 |
unneback |
wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
|
| 6022 |
17 |
unneback |
|
| 6023 |
18 |
unneback |
assign hit_o = hit;
|
| 6024 |
|
|
assign wb_dat_o = wb_dat & {32{wb_ack}};
|
| 6025 |
|
|
assign wb_ack_o = wb_ack;
|
| 6026 |
|
|
|
| 6027 |
17 |
unneback |
endmodule
|
| 6028 |
40 |
unneback |
`endif
|
| 6029 |
32 |
unneback |
|
| 6030 |
106 |
unneback |
`ifdef WB_DPRAM
|
| 6031 |
|
|
`define MODULE wb_dpram
|
| 6032 |
40 |
unneback |
module `BASE`MODULE (
|
| 6033 |
|
|
`undef MODULE
|
| 6034 |
32 |
unneback |
// wishbone slave side a
|
| 6035 |
106 |
unneback |
wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, wbsa_stall_o,
|
| 6036 |
32 |
unneback |
wbsa_clk, wbsa_rst,
|
| 6037 |
92 |
unneback |
// wishbone slave side b
|
| 6038 |
106 |
unneback |
wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, wbsb_stall_o,
|
| 6039 |
32 |
unneback |
wbsb_clk, wbsb_rst);
|
| 6040 |
|
|
|
| 6041 |
92 |
unneback |
parameter data_width_a = 32;
|
| 6042 |
|
|
parameter data_width_b = data_width_a;
|
| 6043 |
|
|
parameter addr_width_a = 8;
|
| 6044 |
|
|
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
|
| 6045 |
101 |
unneback |
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
|
| 6046 |
92 |
unneback |
parameter max_burst_width_a = 4;
|
| 6047 |
|
|
parameter max_burst_width_b = max_burst_width_a;
|
| 6048 |
101 |
unneback |
parameter mode = "B3";
|
| 6049 |
109 |
unneback |
parameter memory_init = 0;
|
| 6050 |
|
|
parameter memory_file = "vl_ram.v";
|
| 6051 |
92 |
unneback |
input [data_width_a-1:0] wbsa_dat_i;
|
| 6052 |
|
|
input [addr_width_a-1:0] wbsa_adr_i;
|
| 6053 |
|
|
input [data_width_a/8-1:0] wbsa_sel_i;
|
| 6054 |
|
|
input [2:0] wbsa_cti_i;
|
| 6055 |
|
|
input [1:0] wbsa_bte_i;
|
| 6056 |
32 |
unneback |
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
|
| 6057 |
92 |
unneback |
output [data_width_a-1:0] wbsa_dat_o;
|
| 6058 |
109 |
unneback |
output wbsa_ack_o;
|
| 6059 |
106 |
unneback |
output wbsa_stall_o;
|
| 6060 |
32 |
unneback |
input wbsa_clk, wbsa_rst;
|
| 6061 |
|
|
|
| 6062 |
92 |
unneback |
input [data_width_b-1:0] wbsb_dat_i;
|
| 6063 |
|
|
input [addr_width_b-1:0] wbsb_adr_i;
|
| 6064 |
|
|
input [data_width_b/8-1:0] wbsb_sel_i;
|
| 6065 |
|
|
input [2:0] wbsb_cti_i;
|
| 6066 |
|
|
input [1:0] wbsb_bte_i;
|
| 6067 |
32 |
unneback |
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
|
| 6068 |
92 |
unneback |
output [data_width_b-1:0] wbsb_dat_o;
|
| 6069 |
109 |
unneback |
output wbsb_ack_o;
|
| 6070 |
106 |
unneback |
output wbsb_stall_o;
|
| 6071 |
32 |
unneback |
input wbsb_clk, wbsb_rst;
|
| 6072 |
|
|
|
| 6073 |
92 |
unneback |
wire [addr_width_a-1:0] adr_a;
|
| 6074 |
|
|
wire [addr_width_b-1:0] adr_b;
|
| 6075 |
101 |
unneback |
wire we_a, we_b;
|
| 6076 |
|
|
generate
|
| 6077 |
|
|
if (mode=="B3") begin : b3_inst
|
| 6078 |
92 |
unneback |
`define MODULE wb_adr_inc
|
| 6079 |
|
|
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
|
| 6080 |
|
|
.cyc_i(wbsa_cyc_i),
|
| 6081 |
|
|
.stb_i(wbsa_stb_i),
|
| 6082 |
|
|
.cti_i(wbsa_cti_i),
|
| 6083 |
|
|
.bte_i(wbsa_bte_i),
|
| 6084 |
|
|
.adr_i(wbsa_adr_i),
|
| 6085 |
|
|
.we_i(wbsa_we_i),
|
| 6086 |
|
|
.ack_o(wbsa_ack_o),
|
| 6087 |
|
|
.adr_o(adr_a),
|
| 6088 |
|
|
.clk(wbsa_clk),
|
| 6089 |
|
|
.rst(wbsa_rst));
|
| 6090 |
101 |
unneback |
assign we_a = wbsa_we_i & wbsa_ack_o;
|
| 6091 |
92 |
unneback |
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
|
| 6092 |
|
|
.cyc_i(wbsb_cyc_i),
|
| 6093 |
|
|
.stb_i(wbsb_stb_i),
|
| 6094 |
|
|
.cti_i(wbsb_cti_i),
|
| 6095 |
|
|
.bte_i(wbsb_bte_i),
|
| 6096 |
|
|
.adr_i(wbsb_adr_i),
|
| 6097 |
|
|
.we_i(wbsb_we_i),
|
| 6098 |
|
|
.ack_o(wbsb_ack_o),
|
| 6099 |
|
|
.adr_o(adr_b),
|
| 6100 |
|
|
.clk(wbsb_clk),
|
| 6101 |
|
|
.rst(wbsb_rst));
|
| 6102 |
40 |
unneback |
`undef MODULE
|
| 6103 |
101 |
unneback |
assign we_b = wbsb_we_i & wbsb_ack_o;
|
| 6104 |
|
|
end else if (mode=="B4") begin : b4_inst
|
| 6105 |
109 |
unneback |
`define MODULE dff
|
| 6106 |
|
|
`BASE`MODULE dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
|
| 6107 |
101 |
unneback |
assign wbsa_stall_o = 1'b0;
|
| 6108 |
|
|
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
|
| 6109 |
109 |
unneback |
`BASE`MODULE dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
|
| 6110 |
|
|
`undef MODULE
|
| 6111 |
101 |
unneback |
assign wbsb_stall_o = 1'b0;
|
| 6112 |
|
|
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
|
| 6113 |
|
|
end
|
| 6114 |
|
|
endgenerate
|
| 6115 |
92 |
unneback |
|
| 6116 |
|
|
`define MODULE dpram_be_2r2w
|
| 6117 |
109 |
unneback |
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
|
| 6118 |
110 |
unneback |
.b_data_width(data_width_b),
|
| 6119 |
109 |
unneback |
.memory_init(memory_init), .memory_file(memory_file))
|
| 6120 |
92 |
unneback |
`undef MODULE
|
| 6121 |
|
|
ram_i (
|
| 6122 |
32 |
unneback |
.d_a(wbsa_dat_i),
|
| 6123 |
92 |
unneback |
.q_a(wbsa_dat_o),
|
| 6124 |
|
|
.adr_a(adr_a),
|
| 6125 |
|
|
.be_a(wbsa_sel_i),
|
| 6126 |
101 |
unneback |
.we_a(we_a),
|
| 6127 |
32 |
unneback |
.clk_a(wbsa_clk),
|
| 6128 |
|
|
.d_b(wbsb_dat_i),
|
| 6129 |
92 |
unneback |
.q_b(wbsb_dat_o),
|
| 6130 |
|
|
.adr_b(adr_b),
|
| 6131 |
|
|
.be_b(wbsb_sel_i),
|
| 6132 |
101 |
unneback |
.we_b(we_b),
|
| 6133 |
32 |
unneback |
.clk_b(wbsb_clk) );
|
| 6134 |
|
|
|
| 6135 |
|
|
endmodule
|
| 6136 |
40 |
unneback |
`endif
|
| 6137 |
94 |
unneback |
|
| 6138 |
101 |
unneback |
`ifdef WB_CACHE
|
| 6139 |
|
|
`define MODULE wb_cache
|
| 6140 |
97 |
unneback |
module `BASE`MODULE (
|
| 6141 |
103 |
unneback |
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
|
| 6142 |
98 |
unneback |
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
|
| 6143 |
97 |
unneback |
);
|
| 6144 |
|
|
`undef MODULE
|
| 6145 |
|
|
|
| 6146 |
|
|
parameter dw_s = 32;
|
| 6147 |
|
|
parameter aw_s = 24;
|
| 6148 |
|
|
parameter dw_m = dw_s;
|
| 6149 |
100 |
unneback |
localparam aw_m = dw_s * aw_s / dw_m;
|
| 6150 |
|
|
parameter wbs_max_burst_width = 4;
|
| 6151 |
103 |
unneback |
parameter wbs_mode = "B3";
|
| 6152 |
97 |
unneback |
|
| 6153 |
|
|
parameter async = 1; // wbs_clk != wbm_clk
|
| 6154 |
|
|
|
| 6155 |
|
|
parameter nr_of_ways = 1;
|
| 6156 |
|
|
parameter aw_offset = 4; // 4 => 16 words per cache line
|
| 6157 |
|
|
parameter aw_slot = 10;
|
| 6158 |
100 |
unneback |
|
| 6159 |
|
|
parameter valid_mem = 0;
|
| 6160 |
|
|
parameter debug = 0;
|
| 6161 |
|
|
|
| 6162 |
|
|
localparam aw_b_offset = aw_offset * dw_s / dw_m;
|
| 6163 |
98 |
unneback |
localparam aw_tag = aw_s - aw_slot - aw_offset;
|
| 6164 |
97 |
unneback |
parameter wbm_burst_size = 4; // valid options 4,8,16
|
| 6165 |
98 |
unneback |
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
|
| 6166 |
97 |
unneback |
`define SIZE2WIDTH wbm_burst_size
|
| 6167 |
|
|
localparam wbm_burst_width `SIZE2WIDTH_EXPR
|
| 6168 |
|
|
`undef SIZE2WIDTH
|
| 6169 |
|
|
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
|
| 6170 |
|
|
`define SIZE2WIDTH nr_of_wbm_burst
|
| 6171 |
|
|
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
|
| 6172 |
|
|
`undef SIZE2WIDTH
|
| 6173 |
100 |
unneback |
|
| 6174 |
97 |
unneback |
input [dw_s-1:0] wbs_dat_i;
|
| 6175 |
|
|
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
|
| 6176 |
98 |
unneback |
input [dw_s/8-1:0] wbs_sel_i;
|
| 6177 |
97 |
unneback |
input [2:0] wbs_cti_i;
|
| 6178 |
|
|
input [1:0] wbs_bte_i;
|
| 6179 |
98 |
unneback |
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
| 6180 |
97 |
unneback |
output [dw_s-1:0] wbs_dat_o;
|
| 6181 |
|
|
output wbs_ack_o;
|
| 6182 |
103 |
unneback |
output wbs_stall_o;
|
| 6183 |
97 |
unneback |
input wbs_clk, wbs_rst;
|
| 6184 |
|
|
|
| 6185 |
|
|
output [dw_m-1:0] wbm_dat_o;
|
| 6186 |
|
|
output [aw_m-1:0] wbm_adr_o;
|
| 6187 |
|
|
output [dw_m/8-1:0] wbm_sel_o;
|
| 6188 |
|
|
output [2:0] wbm_cti_o;
|
| 6189 |
|
|
output [1:0] wbm_bte_o;
|
| 6190 |
98 |
unneback |
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
|
| 6191 |
97 |
unneback |
input [dw_m-1:0] wbm_dat_i;
|
| 6192 |
|
|
input wbm_ack_i;
|
| 6193 |
|
|
input wbm_stall_i;
|
| 6194 |
|
|
input wbm_clk, wbm_rst;
|
| 6195 |
|
|
|
| 6196 |
100 |
unneback |
wire valid, dirty, hit;
|
| 6197 |
97 |
unneback |
wire [aw_tag-1:0] tag;
|
| 6198 |
|
|
wire tag_mem_we;
|
| 6199 |
|
|
wire [aw_tag-1:0] wbs_adr_tag;
|
| 6200 |
|
|
wire [aw_slot-1:0] wbs_adr_slot;
|
| 6201 |
98 |
unneback |
wire [aw_offset-1:0] wbs_adr_word;
|
| 6202 |
|
|
wire [aw_s-1:0] wbs_adr;
|
| 6203 |
97 |
unneback |
|
| 6204 |
|
|
reg [1:0] state;
|
| 6205 |
|
|
localparam idle = 2'h0;
|
| 6206 |
|
|
localparam rdwr = 2'h1;
|
| 6207 |
|
|
localparam push = 2'h2;
|
| 6208 |
|
|
localparam pull = 2'h3;
|
| 6209 |
|
|
wire eoc;
|
| 6210 |
103 |
unneback |
wire we;
|
| 6211 |
97 |
unneback |
|
| 6212 |
|
|
// cdc
|
| 6213 |
|
|
wire done, mem_alert, mem_done;
|
| 6214 |
|
|
|
| 6215 |
98 |
unneback |
// wbm side
|
| 6216 |
|
|
reg [aw_m-1:0] wbm_radr;
|
| 6217 |
|
|
reg [aw_m-1:0] wbm_wadr;
|
| 6218 |
100 |
unneback |
wire [aw_slot-1:0] wbm_adr;
|
| 6219 |
98 |
unneback |
wire wbm_radr_cke, wbm_wadr_cke;
|
| 6220 |
|
|
|
| 6221 |
100 |
unneback |
reg [2:0] phase;
|
| 6222 |
|
|
// phase = {we,stb,cyc}
|
| 6223 |
|
|
localparam wbm_wait = 3'b000;
|
| 6224 |
|
|
localparam wbm_wr = 3'b111;
|
| 6225 |
|
|
localparam wbm_wr_drain = 3'b101;
|
| 6226 |
|
|
localparam wbm_rd = 3'b011;
|
| 6227 |
|
|
localparam wbm_rd_drain = 3'b001;
|
| 6228 |
98 |
unneback |
|
| 6229 |
97 |
unneback |
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
|
| 6230 |
|
|
|
| 6231 |
100 |
unneback |
generate
|
| 6232 |
|
|
if (valid_mem==0) begin : no_valid_mem
|
| 6233 |
|
|
assign valid = 1'b1;
|
| 6234 |
|
|
end else begin : valid_mem_inst
|
| 6235 |
|
|
`define MODULE dpram_1r1w
|
| 6236 |
97 |
unneback |
`BASE`MODULE
|
| 6237 |
100 |
unneback |
# ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
|
| 6238 |
|
|
valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
|
| 6239 |
|
|
.q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
|
| 6240 |
97 |
unneback |
`undef MODULE
|
| 6241 |
100 |
unneback |
end
|
| 6242 |
|
|
endgenerate
|
| 6243 |
97 |
unneback |
|
| 6244 |
100 |
unneback |
`define MODULE dpram_1r1w
|
| 6245 |
|
|
`BASE`MODULE
|
| 6246 |
|
|
# ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
|
| 6247 |
|
|
tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
|
| 6248 |
|
|
.q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
|
| 6249 |
|
|
assign hit = wbs_adr_tag == tag;
|
| 6250 |
|
|
`undef MODULE
|
| 6251 |
|
|
|
| 6252 |
|
|
`define MODULE dpram_1r2w
|
| 6253 |
|
|
`BASE`MODULE
|
| 6254 |
|
|
# ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
|
| 6255 |
|
|
dirty_mem (
|
| 6256 |
|
|
.d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
|
| 6257 |
|
|
.d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
|
| 6258 |
|
|
`undef MODULE
|
| 6259 |
|
|
|
| 6260 |
103 |
unneback |
generate
|
| 6261 |
|
|
if (wbs_mode=="B3") begin : inst_b3
|
| 6262 |
97 |
unneback |
`define MODULE wb_adr_inc
|
| 6263 |
100 |
unneback |
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
|
| 6264 |
|
|
.cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
|
| 6265 |
|
|
.stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
|
| 6266 |
97 |
unneback |
.cti_i(wbs_cti_i),
|
| 6267 |
|
|
.bte_i(wbs_bte_i),
|
| 6268 |
|
|
.adr_i(wbs_adr_i),
|
| 6269 |
|
|
.we_i (wbs_we_i),
|
| 6270 |
|
|
.ack_o(wbs_ack_o),
|
| 6271 |
|
|
.adr_o(wbs_adr),
|
| 6272 |
100 |
unneback |
.clk(wbs_clk),
|
| 6273 |
|
|
.rst(wbs_rst));
|
| 6274 |
97 |
unneback |
`undef MODULE
|
| 6275 |
103 |
unneback |
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
|
| 6276 |
|
|
assign we = wbs_cyc_i & wbs_we_i & wbs_ack_o;
|
| 6277 |
|
|
end else if (wbs_mode=="B4") begin : inst_b4
|
| 6278 |
|
|
end
|
| 6279 |
97 |
unneback |
|
| 6280 |
103 |
unneback |
endgenerate
|
| 6281 |
|
|
|
| 6282 |
97 |
unneback |
`define MODULE dpram_be_2r2w
|
| 6283 |
|
|
`BASE`MODULE
|
| 6284 |
100 |
unneback |
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
|
| 6285 |
103 |
unneback |
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
|
| 6286 |
100 |
unneback |
.d_b(wbm_dat_i), .adr_b(wbm_adr_o[aw_slot+aw_offset-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
|
| 6287 |
97 |
unneback |
`undef MODULE
|
| 6288 |
|
|
|
| 6289 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
| 6290 |
|
|
if (wbs_rst)
|
| 6291 |
98 |
unneback |
state <= idle;
|
| 6292 |
97 |
unneback |
else
|
| 6293 |
|
|
case (state)
|
| 6294 |
|
|
idle:
|
| 6295 |
|
|
if (wbs_cyc_i)
|
| 6296 |
|
|
state <= rdwr;
|
| 6297 |
|
|
rdwr:
|
| 6298 |
100 |
unneback |
casex ({valid, hit, dirty, eoc})
|
| 6299 |
|
|
4'b0xxx: state <= pull;
|
| 6300 |
|
|
4'b11x1: state <= idle;
|
| 6301 |
|
|
4'b101x: state <= push;
|
| 6302 |
|
|
4'b100x: state <= pull;
|
| 6303 |
|
|
endcase
|
| 6304 |
97 |
unneback |
push:
|
| 6305 |
|
|
if (done)
|
| 6306 |
|
|
state <= rdwr;
|
| 6307 |
|
|
pull:
|
| 6308 |
|
|
if (done)
|
| 6309 |
|
|
state <= rdwr;
|
| 6310 |
|
|
default: state <= idle;
|
| 6311 |
|
|
endcase
|
| 6312 |
|
|
|
| 6313 |
|
|
// cdc
|
| 6314 |
|
|
generate
|
| 6315 |
|
|
if (async==1) begin : cdc0
|
| 6316 |
|
|
`define MODULE cdc
|
| 6317 |
100 |
unneback |
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
|
| 6318 |
97 |
unneback |
`undef MODULE
|
| 6319 |
|
|
end
|
| 6320 |
|
|
else begin : nocdc
|
| 6321 |
100 |
unneback |
assign mem_alert = state==rdwr & (!valid | !hit);
|
| 6322 |
97 |
unneback |
assign done = mem_done;
|
| 6323 |
|
|
end
|
| 6324 |
|
|
endgenerate
|
| 6325 |
|
|
|
| 6326 |
|
|
// FSM generating a number of burts 4 cycles
|
| 6327 |
|
|
// actual number depends on data width ratio
|
| 6328 |
|
|
// nr_of_wbm_burst
|
| 6329 |
101 |
unneback |
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt_rw, cnt_ack;
|
| 6330 |
97 |
unneback |
|
| 6331 |
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
| 6332 |
|
|
if (wbm_rst)
|
| 6333 |
100 |
unneback |
cnt_rw <= {wbm_burst_width{1'b0}};
|
| 6334 |
97 |
unneback |
else
|
| 6335 |
100 |
unneback |
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
|
| 6336 |
|
|
cnt_rw <= cnt_rw + 1;
|
| 6337 |
97 |
unneback |
|
| 6338 |
98 |
unneback |
always @ (posedge wbm_clk or posedge wbm_rst)
|
| 6339 |
|
|
if (wbm_rst)
|
| 6340 |
100 |
unneback |
cnt_ack <= {wbm_burst_width{1'b0}};
|
| 6341 |
98 |
unneback |
else
|
| 6342 |
100 |
unneback |
if (wbm_ack_i)
|
| 6343 |
|
|
cnt_ack <= cnt_ack + 1;
|
| 6344 |
97 |
unneback |
|
| 6345 |
100 |
unneback |
generate
|
| 6346 |
101 |
unneback |
if (nr_of_wbm_burst==1) begin : one_burst
|
| 6347 |
100 |
unneback |
|
| 6348 |
98 |
unneback |
always @ (posedge wbm_clk or posedge wbm_rst)
|
| 6349 |
|
|
if (wbm_rst)
|
| 6350 |
|
|
phase <= wbm_wait;
|
| 6351 |
|
|
else
|
| 6352 |
|
|
case (phase)
|
| 6353 |
|
|
wbm_wait:
|
| 6354 |
|
|
if (mem_alert)
|
| 6355 |
100 |
unneback |
if (state==push)
|
| 6356 |
|
|
phase <= wbm_wr;
|
| 6357 |
|
|
else
|
| 6358 |
|
|
phase <= wbm_rd;
|
| 6359 |
98 |
unneback |
wbm_wr:
|
| 6360 |
100 |
unneback |
if (&cnt_rw)
|
| 6361 |
|
|
phase <= wbm_wr_drain;
|
| 6362 |
|
|
wbm_wr_drain:
|
| 6363 |
|
|
if (&cnt_ack)
|
| 6364 |
98 |
unneback |
phase <= wbm_rd;
|
| 6365 |
|
|
wbm_rd:
|
| 6366 |
100 |
unneback |
if (&cnt_rw)
|
| 6367 |
|
|
phase <= wbm_rd_drain;
|
| 6368 |
|
|
wbm_rd_drain:
|
| 6369 |
|
|
if (&cnt_ack)
|
| 6370 |
|
|
phase <= wbm_wait;
|
| 6371 |
98 |
unneback |
default: phase <= wbm_wait;
|
| 6372 |
|
|
endcase
|
| 6373 |
|
|
|
| 6374 |
100 |
unneback |
end else begin : multiple_burst
|
| 6375 |
|
|
|
| 6376 |
101 |
unneback |
always @ (posedge wbm_clk or posedge wbm_rst)
|
| 6377 |
|
|
if (wbm_rst)
|
| 6378 |
|
|
phase <= wbm_wait;
|
| 6379 |
|
|
else
|
| 6380 |
|
|
case (phase)
|
| 6381 |
|
|
wbm_wait:
|
| 6382 |
|
|
if (mem_alert)
|
| 6383 |
|
|
if (state==push)
|
| 6384 |
|
|
phase <= wbm_wr;
|
| 6385 |
|
|
else
|
| 6386 |
|
|
phase <= wbm_rd;
|
| 6387 |
|
|
wbm_wr:
|
| 6388 |
|
|
if (&cnt_rw[wbm_burst_width-1:0])
|
| 6389 |
|
|
phase <= wbm_wr_drain;
|
| 6390 |
|
|
wbm_wr_drain:
|
| 6391 |
|
|
if (&cnt_ack)
|
| 6392 |
|
|
phase <= wbm_rd;
|
| 6393 |
|
|
else if (&cnt_ack[wbm_burst_width-1:0])
|
| 6394 |
|
|
phase <= wbm_wr;
|
| 6395 |
|
|
wbm_rd:
|
| 6396 |
|
|
if (&cnt_rw[wbm_burst_width-1:0])
|
| 6397 |
|
|
phase <= wbm_rd_drain;
|
| 6398 |
|
|
wbm_rd_drain:
|
| 6399 |
|
|
if (&cnt_ack)
|
| 6400 |
|
|
phase <= wbm_wait;
|
| 6401 |
|
|
else if (&cnt_ack[wbm_burst_width-1:0])
|
| 6402 |
|
|
phase <= wbm_rd;
|
| 6403 |
|
|
default: phase <= wbm_wait;
|
| 6404 |
|
|
endcase
|
| 6405 |
100 |
unneback |
|
| 6406 |
101 |
unneback |
|
| 6407 |
100 |
unneback |
end
|
| 6408 |
|
|
endgenerate
|
| 6409 |
|
|
|
| 6410 |
101 |
unneback |
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
|
| 6411 |
100 |
unneback |
|
| 6412 |
|
|
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
|
| 6413 |
|
|
assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
|
| 6414 |
|
|
assign wbm_sel_o = {dw_m/8{1'b1}};
|
| 6415 |
|
|
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
|
| 6416 |
98 |
unneback |
assign wbm_bte_o = bte;
|
| 6417 |
100 |
unneback |
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o} = phase;
|
| 6418 |
98 |
unneback |
|
| 6419 |
97 |
unneback |
endmodule
|
| 6420 |
|
|
`endif
|
| 6421 |
103 |
unneback |
|
| 6422 |
|
|
`ifdef WB_AVALON_BRIDGE
|
| 6423 |
|
|
// Wishbone to avalon bridge supporting one type of burst transfer only
|
| 6424 |
|
|
// intended use is together with cache above
|
| 6425 |
|
|
// WB B4 -> pipelined avalon
|
| 6426 |
|
|
`define MODULE wb_avalon_bridge
|
| 6427 |
|
|
module `BASE`MODULE (
|
| 6428 |
|
|
`undef MODULE
|
| 6429 |
|
|
// wishbone slave side
|
| 6430 |
|
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
|
| 6431 |
|
|
// avalon master side
|
| 6432 |
|
|
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
|
| 6433 |
|
|
// common
|
| 6434 |
|
|
clk, rst);
|
| 6435 |
|
|
|
| 6436 |
|
|
parameter adr_width = 30;
|
| 6437 |
|
|
parameter dat_width = 32;
|
| 6438 |
|
|
parameter burst_size = 4;
|
| 6439 |
|
|
|
| 6440 |
|
|
input [dat_width-1:0] wbs_dat_i;
|
| 6441 |
|
|
input [adr_width-1:0] wbs_adr_i;
|
| 6442 |
|
|
input [dat_width/8-1:0] wbs_sel_i;
|
| 6443 |
|
|
input [1:0] wbs_bte_i;
|
| 6444 |
|
|
input [2:0] wbs_cti_i;
|
| 6445 |
|
|
input wbs_we_i;
|
| 6446 |
|
|
input wbs_cyc_i;
|
| 6447 |
|
|
input wbs_stb_i;
|
| 6448 |
|
|
output [dat_width:0] wbs_dat_o;
|
| 6449 |
|
|
output wbs_ack_o;
|
| 6450 |
|
|
output wbs_stall_o;
|
| 6451 |
|
|
|
| 6452 |
|
|
input [dat_width-1:0] readdata;
|
| 6453 |
|
|
input readdatavalid;
|
| 6454 |
|
|
output [dat_width-1:0] writedata;
|
| 6455 |
|
|
output [adr_width-1:0] address;
|
| 6456 |
|
|
output [dat_width/8-1:0] be;
|
| 6457 |
|
|
output write;
|
| 6458 |
|
|
output read;
|
| 6459 |
|
|
output beginbursttransfer;
|
| 6460 |
|
|
output [3:0] burstcount;
|
| 6461 |
|
|
input waitrequest;
|
| 6462 |
|
|
input clk, rst;
|
| 6463 |
|
|
|
| 6464 |
|
|
reg last_cyc_idle_or_eoc;
|
| 6465 |
|
|
|
| 6466 |
|
|
reg [3:0] cnt;
|
| 6467 |
|
|
always @ (posedge clk or posedge rst)
|
| 6468 |
|
|
if (rst)
|
| 6469 |
|
|
cnt <= 4'h0;
|
| 6470 |
|
|
else
|
| 6471 |
|
|
if (beginbursttransfer & waitrequest)
|
| 6472 |
|
|
cnt <= burst_size - 1;
|
| 6473 |
|
|
else if (beginbursttransfer & !waitrequest)
|
| 6474 |
|
|
cnt <= burst_size - 2;
|
| 6475 |
|
|
else if (wbs_ack_o)
|
| 6476 |
|
|
cnt <= cnt - 1;
|
| 6477 |
|
|
|
| 6478 |
|
|
reg wr_ack;
|
| 6479 |
|
|
always @ (posedge clk or posedge rst)
|
| 6480 |
|
|
if (rst)
|
| 6481 |
|
|
wr_ack <= 1'b0;
|
| 6482 |
|
|
else
|
| 6483 |
|
|
wr_ack <= (wbs_we_i & wbs_cyc_i & wbs_stb_i & !wbs_stall_o);
|
| 6484 |
|
|
|
| 6485 |
|
|
// to avalon
|
| 6486 |
|
|
assign writedata = wbs_dat_i;
|
| 6487 |
|
|
assign address = wbs_adr_i;
|
| 6488 |
|
|
assign be = wbs_sel_i;
|
| 6489 |
|
|
assign write = cnt==(burst_size-1) & wbs_cyc_i & wbs_we_i;
|
| 6490 |
|
|
assign read = cnt==(burst_size-1) & wbs_cyc_i & !wbs_we_i;
|
| 6491 |
|
|
assign beginbursttransfer = cnt==4'h0 & wbs_cyc_i;
|
| 6492 |
|
|
assign burstcount = burst_size;
|
| 6493 |
|
|
|
| 6494 |
|
|
// to wishbone
|
| 6495 |
|
|
assign wbs_dat_o = readdata;
|
| 6496 |
|
|
assign wbs_ack_o = wr_ack | readdatavalid;
|
| 6497 |
|
|
assign wbs_stall_o = waitrequest;
|
| 6498 |
|
|
|
| 6499 |
|
|
endmodule
|
| 6500 |
|
|
`endif
|
| 6501 |
|
|
|
| 6502 |
|
|
`ifdef WB_AVALON_MEM_CACHE
|
| 6503 |
|
|
`define MODULE wb_avalon_mem_cache
|
| 6504 |
|
|
module `BASE`MODULE (
|
| 6505 |
|
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
|
| 6506 |
|
|
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst
|
| 6507 |
|
|
);
|
| 6508 |
|
|
`undef MODULE
|
| 6509 |
|
|
|
| 6510 |
|
|
// wishbone
|
| 6511 |
|
|
parameter wb_dat_width = 32;
|
| 6512 |
|
|
parameter wb_adr_width = 22;
|
| 6513 |
|
|
parameter wb_max_burst_width = 4;
|
| 6514 |
|
|
parameter wb_mode = "B4";
|
| 6515 |
|
|
// avalon
|
| 6516 |
|
|
parameter avalon_dat_width = 32;
|
| 6517 |
|
|
localparam avalon_adr_width = wb_dat_width * wb_adr_width / avalon_dat_width;
|
| 6518 |
|
|
parameter avalon_burst_size = 4;
|
| 6519 |
|
|
// cache
|
| 6520 |
|
|
parameter async = 1;
|
| 6521 |
|
|
parameter nr_of_ways = 1;
|
| 6522 |
|
|
parameter aw_offset = 4;
|
| 6523 |
|
|
parameter aw_slot = 10;
|
| 6524 |
|
|
parameter valid_mem = 1;
|
| 6525 |
|
|
// shadow RAM
|
| 6526 |
|
|
parameter shadow_ram = 0;
|
| 6527 |
|
|
parameter shadow_ram_adr_width = 10;
|
| 6528 |
|
|
parameter shadow_ram_size = 1024;
|
| 6529 |
|
|
parameter shadow_ram_init = 2; // 0: no init, 1: from file, 2: with zero
|
| 6530 |
|
|
parameter shadow_ram_file = "vl_ram.v";
|
| 6531 |
|
|
|
| 6532 |
|
|
input [wb_dat_width-1:0] wbs_dat_i;
|
| 6533 |
|
|
input [wb_adr_width-1:0] wbs_adr_i; // dont include a1,a0
|
| 6534 |
|
|
input [wb_dat_width/8-1:0] wbs_sel_i;
|
| 6535 |
|
|
input [2:0] wbs_cti_i;
|
| 6536 |
|
|
input [1:0] wbs_bte_i;
|
| 6537 |
|
|
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
| 6538 |
|
|
output [wb_dat_width-1:0] wbs_dat_o;
|
| 6539 |
|
|
output wbs_ack_o;
|
| 6540 |
|
|
output wbs_stall_o;
|
| 6541 |
|
|
input wbs_clk, wbs_rst;
|
| 6542 |
|
|
|
| 6543 |
|
|
input [avalon_dat_width-1:0] readdata;
|
| 6544 |
|
|
input readdatavalid;
|
| 6545 |
|
|
output [avalon_dat_width-1:0] writedata;
|
| 6546 |
|
|
output [avalon_adr_width-1:0] address;
|
| 6547 |
|
|
output [avalon_dat_width/8-1:0] be;
|
| 6548 |
|
|
output write;
|
| 6549 |
|
|
output read;
|
| 6550 |
|
|
output beginbursttransfer;
|
| 6551 |
|
|
output [3:0] burstcount;
|
| 6552 |
|
|
input waitrequest;
|
| 6553 |
|
|
input clk, rst;
|
| 6554 |
|
|
|
| 6555 |
|
|
`define DAT_WIDTH wb_dat_width
|
| 6556 |
|
|
`define ADR_WIDTH wb_adr_width
|
| 6557 |
|
|
`define WB wb1
|
| 6558 |
|
|
`include "wb_wires.v"
|
| 6559 |
|
|
`define WB wb2
|
| 6560 |
|
|
`include "wb_wires.v"
|
| 6561 |
|
|
`undef DAT_WIDTH
|
| 6562 |
|
|
`undef ADR_WIDTH
|
| 6563 |
|
|
|
| 6564 |
|
|
`define MODULE wb_shadow_ram
|
| 6565 |
|
|
`BASE`MODULE # ( .dat_width(wb_dat_width), .mode(wb_mode), .max_burst_width(wb_max_burst_width),
|
| 6566 |
|
|
.shadow_mem_adr_width(shadow_ram_adr_width), .shadow_mem_size(shadow_ram_adr_width), .shadow_mem_init(shadow_ram_init), .shadow_mem_file(shadow_ram_file),
|
| 6567 |
|
|
.main_mem_adr_width(wb_adr_width))
|
| 6568 |
|
|
shadow_ram0 (
|
| 6569 |
|
|
.wbs_dat_i(wbs_dat_i), .wbs_adr_i(wbs_adr_i), .wbs_cti_i(wbs_cti_i), .wbs_bte_i(wbs_bte_i), .wbs_sel_i(wbs_sel_i), .wbs_we_i(wbs_we_i), .wbs_stb_i(wbs_stb_i), .wbs_cyc_i(wbs_cyc_i),
|
| 6570 |
|
|
.wbs_dat_o(wbs_dat_o), .wbs_ack_o(wbs_ack_o), .wbs_stall_o(wbs_stall_o),
|
| 6571 |
|
|
.wbm_dat_o(wb1_dat_o), .wbm_adr_o(wb1_adr_o), .wbm_cti_o(wb1_cti_o), .wbm_bte_o(wb1_bte_o), .wbm_sel_o(wb1_sel_o), .wbm_we_o(wb1_we_o), .wbm_stb_o(wb1_stb_o), .wbm_cyc_o(wb1_cyc_o),
|
| 6572 |
|
|
.wbm_dat_i(wb1_dat_i), .wbm_ack_i(wb1_ack_i), .wbm_stall_i(wb1_stall_i),
|
| 6573 |
|
|
.wb_clk(wbs_clk), .wb_rst(wbs_rst));
|
| 6574 |
|
|
`undef MODULE
|
| 6575 |
|
|
|
| 6576 |
|
|
`define MODULE wb_cache
|
| 6577 |
|
|
`BASE`MODULE
|
| 6578 |
|
|
# ( .dw_s(wb_dat_width), .aw_s(wb_adr_width), .dw_m(avalon_dat_width), .wbs_mode(wb_mode), .wbs_max_burst_width(wb_max_burst_width), .async(async), .nr_of_ways(nr_of_ways), .aw_offset(aw_offset), .aw_slot(aw_slot), .valid_mem(valid_mem))
|
| 6579 |
|
|
cache0 (
|
| 6580 |
|
|
.wbs_dat_i(wb1_dat_o), .wbs_adr_i(wb1_adr_o), .wbs_sel_i(wb1_sel_o), .wbs_cti_i(wb1_cti_o), .wbs_bte_i(wb1_bte_o), .wbs_we_i(wb1_we_o), .wbs_stb_i(wb1_stb_o), .wbs_cyc_i(wb1_cyc_o),
|
| 6581 |
|
|
.wbs_dat_o(wb1_dat_i), .wbs_ack_o(wb1_ack_i), .wbs_stall_o(wb1_stall_i), .wbs_clk(wbs_clk), .wbs_rst(wbs_rst),
|
| 6582 |
|
|
.wbm_dat_o(wb2_dat_o), .wbm_adr_o(wb2_adr_o), .wbm_sel_o(wb2_sel_o), .wbm_cti_o(wb2_cti_o), .wbm_bte_o(wb2_bte_o), .wbm_we_o(wb2_we_o), .wbm_stb_o(wb2_stb_o), .wbm_cyc_o(wb2_cyc_o),
|
| 6583 |
|
|
.wbm_dat_i(wb2_dat_i), .wbm_ack_i(wb2_ack_i), .wbm_stall_i(wb2_stall_i), .wbm_clk(clk), .wbm_rst(rst));
|
| 6584 |
|
|
`undef MODULE
|
| 6585 |
|
|
|
| 6586 |
|
|
`define MODULE wb_avalon_bridge
|
| 6587 |
|
|
`BASE`MODULE # ( .adr_width(avalon_adr_width), .dat_width(avalon_dat_width), .burst_size(avalon_burst_size))
|
| 6588 |
|
|
bridge0 (
|
| 6589 |
|
|
// wishbone slave side
|
| 6590 |
|
|
.wbs_dat_i(wb2_dat_o), .wbs_adr_i(wb2_adr_o), .wbs_sel_i(wb2_sel_o), .wbs_bte_i(wb2_bte_o), .wbs_cti_i(wb2_cti_o), .wbs_we_i(wb2_we_o), .wbs_cyc_i(wb2_cyc_o), .wbs_stb_i(wb2_stb_o),
|
| 6591 |
|
|
.wbs_dat_o(wb2_dat_i), .wbs_ack_o(wb2_ack_i), .wbs_stall_o(wb2_stall_i),
|
| 6592 |
|
|
// avalon master side
|
| 6593 |
|
|
.readdata(readdata), .readdatavalid(readdatavalid), .address(address), .read(read), .be(be), .write(write), .burstcount(burstcount), .writedata(writedata), .waitrequest(waitrequest), .beginbursttransfer(beginbursttransfer),
|
| 6594 |
|
|
// common
|
| 6595 |
|
|
.clk(clk), .rst(rst));
|
| 6596 |
|
|
`undef MODULE
|
| 6597 |
|
|
|
| 6598 |
|
|
endmodule
|
| 6599 |
|
|
`endif
|
| 6600 |
105 |
unneback |
|
| 6601 |
|
|
`ifdef WB_SDR_SDRAM
|
| 6602 |
|
|
`define MODULE wb_sdr_sdram
|
| 6603 |
|
|
module `BASE`MODULE (
|
| 6604 |
|
|
`undef MODULE
|
| 6605 |
|
|
// wisbone i/f
|
| 6606 |
|
|
dat_i, adr_i, sel_i, we_i, cyc_i, stb_i, dat_o, ack_o, stall_o
|
| 6607 |
|
|
// SDR SDRAM
|
| 6608 |
|
|
ba, a, cmd, cke, cs_n, dqm, dq_i, dq_o, dq_oe,
|
| 6609 |
|
|
// system
|
| 6610 |
|
|
clk, rst);
|
| 6611 |
|
|
|
| 6612 |
|
|
// external data bus size
|
| 6613 |
|
|
parameter dat_size = 16;
|
| 6614 |
|
|
// memory geometry parameters
|
| 6615 |
|
|
parameter ba_size = `SDR_BA_SIZE;
|
| 6616 |
|
|
parameter row_size = `SDR_ROW_SIZE;
|
| 6617 |
|
|
parameter col_size = `SDR_COL_SIZE;
|
| 6618 |
|
|
parameter cl = 2;
|
| 6619 |
|
|
// memory timing parameters
|
| 6620 |
|
|
parameter tRFC = 9;
|
| 6621 |
|
|
parameter tRP = 2;
|
| 6622 |
|
|
parameter tRCD = 2;
|
| 6623 |
|
|
parameter tMRD = 2;
|
| 6624 |
|
|
|
| 6625 |
|
|
// LMR
|
| 6626 |
|
|
// [12:10] reserved
|
| 6627 |
|
|
// [9] WB, write burst; 0 - programmed burst length, 1 - single location
|
| 6628 |
|
|
// [8:7] OP Mode, 2'b00
|
| 6629 |
|
|
// [6:4] CAS Latency; 3'b010 - 2, 3'b011 - 3
|
| 6630 |
|
|
// [3] BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
|
| 6631 |
|
|
// [2:0] Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
|
| 6632 |
|
|
localparam init_wb = 1'b1;
|
| 6633 |
|
|
localparam init_cl = (cl==2) ? 3'b010 : 3'b011;
|
| 6634 |
|
|
localparam init_bt = 1'b0;
|
| 6635 |
|
|
localparam init_bl = 3'b000;
|
| 6636 |
|
|
|
| 6637 |
|
|
input [dat_size:0] dat_i;
|
| 6638 |
|
|
input [ba_size+col_size+row_size-1:0] adr_i;
|
| 6639 |
|
|
input [dat_size/8-1:0] sel_i;
|
| 6640 |
|
|
input we_i, cyc_i, stb_i;
|
| 6641 |
|
|
output [dat_size-1:0] dat_o;
|
| 6642 |
|
|
output ack_o;
|
| 6643 |
|
|
output reg stall_o;
|
| 6644 |
|
|
|
| 6645 |
|
|
output [ba_size-1:0] ba;
|
| 6646 |
|
|
output reg [12:0] a;
|
| 6647 |
|
|
output reg [2:0] cmd; // {ras,cas,we}
|
| 6648 |
|
|
output cke, cs_n;
|
| 6649 |
|
|
output reg [dat_size/8-1:0] dqm;
|
| 6650 |
|
|
output [dat_size-1:0] dq_o;
|
| 6651 |
|
|
output reg dq_oe;
|
| 6652 |
|
|
input [dat_size-1:0] dq_i;
|
| 6653 |
|
|
|
| 6654 |
|
|
input clk, rst;
|
| 6655 |
|
|
|
| 6656 |
|
|
wire [ba_size-1:0] bank;
|
| 6657 |
|
|
wire [row_size-1:0] row;
|
| 6658 |
|
|
wire [col_size-1:0] col;
|
| 6659 |
|
|
wire [0:31] shreg;
|
| 6660 |
|
|
wire ref_cnt_zero;
|
| 6661 |
|
|
reg refresh_req;
|
| 6662 |
|
|
|
| 6663 |
|
|
wire ack_rd, rd_ack_emptyflag;
|
| 6664 |
|
|
wire ack_wr;
|
| 6665 |
|
|
|
| 6666 |
|
|
// to keep track of open rows per bank
|
| 6667 |
|
|
reg [row_size-1:0] open_row[0:3];
|
| 6668 |
|
|
reg [0:3] open_ba;
|
| 6669 |
|
|
reg current_bank_closed, current_row_open;
|
| 6670 |
|
|
|
| 6671 |
|
|
parameter rfr_length = 10;
|
| 6672 |
|
|
parameter rfr_wrap_value = 1010;
|
| 6673 |
|
|
|
| 6674 |
|
|
parameter [2:0] cmd_nop = 3'b111,
|
| 6675 |
|
|
cmd_act = 3'b011,
|
| 6676 |
|
|
cmd_rd = 3'b101,
|
| 6677 |
|
|
cmd_wr = 3'b100,
|
| 6678 |
|
|
cmd_pch = 3'b010,
|
| 6679 |
|
|
cmd_rfr = 3'b001,
|
| 6680 |
|
|
cmd_lmr = 3'b000;
|
| 6681 |
|
|
|
| 6682 |
|
|
// ctrl FSM
|
| 6683 |
|
|
`define FSM_INIT 3'b000
|
| 6684 |
|
|
`define FSM_IDLE 3'b001
|
| 6685 |
|
|
`define FSM_RFR 3'b010
|
| 6686 |
|
|
`define FSM_ADR 3'b011
|
| 6687 |
|
|
`define FSM_PCH 3'b100
|
| 6688 |
|
|
`define FSM_ACT 3'b101
|
| 6689 |
|
|
`define FSM_RW 3'b111
|
| 6690 |
|
|
|
| 6691 |
|
|
assign cke = 1'b1;
|
| 6692 |
|
|
assign cs_n = 1'b0;
|
| 6693 |
|
|
|
| 6694 |
|
|
reg [2:0] state, next;
|
| 6695 |
|
|
|
| 6696 |
|
|
function [12:0] a10_fix;
|
| 6697 |
|
|
input [col_size-1:0] a;
|
| 6698 |
|
|
integer i;
|
| 6699 |
|
|
begin
|
| 6700 |
|
|
for (i=0;i<13;i=i+1) begin
|
| 6701 |
|
|
if (i<10)
|
| 6702 |
|
|
if (i<col_size)
|
| 6703 |
|
|
a10_fix[i] = a[i];
|
| 6704 |
|
|
else
|
| 6705 |
|
|
a10_fix[i] = 1'b0;
|
| 6706 |
|
|
else if (i==10)
|
| 6707 |
|
|
a10_fix[i] = 1'b0;
|
| 6708 |
|
|
else
|
| 6709 |
|
|
if (i<col_size)
|
| 6710 |
|
|
a10_fix[i] = a[i-1];
|
| 6711 |
|
|
else
|
| 6712 |
|
|
a10_fix[i] = 1'b0;
|
| 6713 |
|
|
end
|
| 6714 |
|
|
end
|
| 6715 |
|
|
endfunction
|
| 6716 |
|
|
|
| 6717 |
|
|
assign {bank,row,col} = adr_i;
|
| 6718 |
|
|
|
| 6719 |
|
|
always @ (posedge clk or posedge rst)
|
| 6720 |
|
|
if (rst)
|
| 6721 |
|
|
state <= `FSM_INIT;
|
| 6722 |
|
|
else
|
| 6723 |
|
|
state <= next;
|
| 6724 |
|
|
|
| 6725 |
|
|
always @*
|
| 6726 |
|
|
begin
|
| 6727 |
|
|
next = state;
|
| 6728 |
|
|
case (state)
|
| 6729 |
|
|
`FSM_INIT:
|
| 6730 |
|
|
if (shreg[3+tRP+tRFC+tRFC+tMRD]) next = `FSM_IDLE;
|
| 6731 |
|
|
`FSM_IDLE:
|
| 6732 |
|
|
if (refresh_req) next = `FSM_RFR;
|
| 6733 |
|
|
else if (cyc_i & stb_i & rd_ack_emptyflag) next = `FSM_ADR;
|
| 6734 |
|
|
`FSM_RFR:
|
| 6735 |
|
|
if (shreg[tRP+tRFC-2]) next = `FSM_IDLE; // take away two cycles because no cmd will be issued in idle and adr
|
| 6736 |
|
|
`FSM_ADR:
|
| 6737 |
|
|
if (current_bank_closed) next = `FSM_ACT;
|
| 6738 |
|
|
else if (current_row_open) next = `FSM_RW;
|
| 6739 |
|
|
else next = `FSM_PCH;
|
| 6740 |
|
|
`FSM_PCH:
|
| 6741 |
|
|
if (shreg[tRP]) next = `FSM_ACT;
|
| 6742 |
|
|
`FSM_ACT:
|
| 6743 |
|
|
if (shreg[tRCD]) next = `FSM_RW;
|
| 6744 |
|
|
`FSM_RW:
|
| 6745 |
|
|
if (!stb_i) next = `FSM_IDLE;
|
| 6746 |
|
|
endcase
|
| 6747 |
|
|
end
|
| 6748 |
|
|
|
| 6749 |
|
|
// counter
|
| 6750 |
|
|
`define MODULE cnt_shreg_ce_clear
|
| 6751 |
|
|
`VLBASE`MODULE # ( .length(32))
|
| 6752 |
|
|
`undef MODULE
|
| 6753 |
|
|
cnt0 (
|
| 6754 |
|
|
.clear(state!=next),
|
| 6755 |
|
|
.q(shreg),
|
| 6756 |
|
|
.rst(rst),
|
| 6757 |
|
|
.clk(clk));
|
| 6758 |
|
|
|
| 6759 |
|
|
// ba, a, cmd
|
| 6760 |
|
|
// outputs dependent on state vector
|
| 6761 |
|
|
always @ (*)
|
| 6762 |
|
|
begin
|
| 6763 |
|
|
{a,cmd} = {13'd0,cmd_nop};
|
| 6764 |
|
|
dqm = 2'b11;
|
| 6765 |
|
|
dq_oe = 1'b0;
|
| 6766 |
|
|
stall_o = 1'b1;
|
| 6767 |
|
|
case (state)
|
| 6768 |
|
|
`FSM_INIT:
|
| 6769 |
|
|
if (shreg[3]) begin
|
| 6770 |
|
|
{a,cmd} = {13'b0010000000000, cmd_pch};
|
| 6771 |
|
|
end else if (shreg[3+tRP] | shreg[3+tRP+tRFC])
|
| 6772 |
|
|
{a,cmd} = {13'd0, cmd_rfr};
|
| 6773 |
|
|
else if (shreg[3+tRP+tRFC+tRFC])
|
| 6774 |
|
|
{a,cmd} = {3'b000,init_wb,2'b00,init_cl,init_bt,init_bl,cmd_lmr};
|
| 6775 |
|
|
`FSM_RFR:
|
| 6776 |
|
|
if (shreg[0])
|
| 6777 |
|
|
{a,cmd} = {13'b0010000000000, cmd_pch};
|
| 6778 |
|
|
else if (shreg[tRP])
|
| 6779 |
|
|
{a,cmd} = {13'd0, cmd_rfr};
|
| 6780 |
|
|
`FSM_PCH:
|
| 6781 |
|
|
if (shreg[0])
|
| 6782 |
|
|
{a,cmd} = {13'd0,cmd_pch};
|
| 6783 |
|
|
`FSM_ACT:
|
| 6784 |
|
|
if (shreg[0])
|
| 6785 |
|
|
{a[row_size-1:0],cmd} = {row,cmd_act};
|
| 6786 |
|
|
`FSM_RW:
|
| 6787 |
|
|
begin
|
| 6788 |
|
|
if (we_i)
|
| 6789 |
|
|
cmd = cmd_wr;
|
| 6790 |
|
|
else
|
| 6791 |
|
|
cmd = cmd_rd;
|
| 6792 |
|
|
if (we_i)
|
| 6793 |
|
|
dqm = ~sel_i;
|
| 6794 |
|
|
else
|
| 6795 |
|
|
dqm = 2'b00;
|
| 6796 |
|
|
if (we_i)
|
| 6797 |
|
|
dq_oe = 1'b1;
|
| 6798 |
|
|
a = a10_fix(col);
|
| 6799 |
|
|
stall_o = 1'b1;
|
| 6800 |
|
|
end
|
| 6801 |
|
|
endcase
|
| 6802 |
|
|
end
|
| 6803 |
|
|
|
| 6804 |
|
|
assign ba = bank;
|
| 6805 |
|
|
|
| 6806 |
|
|
// precharge individual bank A10=0
|
| 6807 |
|
|
// precharge all bank A10=1
|
| 6808 |
|
|
genvar i;
|
| 6809 |
|
|
generate
|
| 6810 |
|
|
for (i=0;i<2<<ba_size-1;i=i+1) begin
|
| 6811 |
|
|
|
| 6812 |
|
|
always @ (posedge clk or posedge rst)
|
| 6813 |
|
|
if (rst)
|
| 6814 |
|
|
{open_ba[i],open_row[i]} <= {1'b0,{row_size{1'b0}}};
|
| 6815 |
|
|
else
|
| 6816 |
|
|
if (cmd==cmd_pch & (a[10] | bank==i))
|
| 6817 |
|
|
open_ba[i] <= 1'b0;
|
| 6818 |
|
|
else if (cmd==cmd_act & bank==i)
|
| 6819 |
|
|
{open_ba[i],open_row[i]} <= {1'b1,row};
|
| 6820 |
|
|
|
| 6821 |
|
|
end
|
| 6822 |
|
|
endgenerate
|
| 6823 |
|
|
|
| 6824 |
|
|
// bank and row open ?
|
| 6825 |
|
|
always @ (posedge clk or posedge rst)
|
| 6826 |
|
|
if (rst)
|
| 6827 |
|
|
{current_bank_closed, current_row_open} <= {1'b1, 1'b0};
|
| 6828 |
|
|
else
|
| 6829 |
|
|
{current_bank_closed, current_row_open} <= {!(open_ba[bank]), open_row[bank]==row};
|
| 6830 |
|
|
|
| 6831 |
|
|
// refresh counter
|
| 6832 |
|
|
`define MODULE cnt_lfsr_zq
|
| 6833 |
|
|
`VLBASE`MODULE # ( .length(rfr_length), .wrap_value (rfr_wrap_value)) ref_counter0( .zq(ref_cnt_zero), .rst(rst), .clk(clk));
|
| 6834 |
|
|
`undef MODULE
|
| 6835 |
|
|
|
| 6836 |
|
|
always @ (posedge clk or posedge rst)
|
| 6837 |
|
|
if (rst)
|
| 6838 |
|
|
refresh_req <= 1'b0;
|
| 6839 |
|
|
else
|
| 6840 |
|
|
if (ref_cnt_zero)
|
| 6841 |
|
|
refresh_req <= 1'b1;
|
| 6842 |
|
|
else if (state==`FSM_RFR)
|
| 6843 |
|
|
refresh_req <= 1'b0;
|
| 6844 |
|
|
|
| 6845 |
|
|
assign dat_o = dq_i;
|
| 6846 |
|
|
|
| 6847 |
|
|
assign ack_wr = (state==`FSM_RW & count0 & we_i);
|
| 6848 |
|
|
`define MODULE delay_emptyflag
|
| 6849 |
|
|
`VLBASE`MODULE # ( .depth(cl+2)) delay0 ( .d(state==`FSM_RW & stb_i & !we_i), .q(ack_rd), .emptyflag(rd_ack_emptyflag), .clk(clk), .rst(rst));
|
| 6850 |
|
|
`undef MODULE
|
| 6851 |
|
|
assign ack_o = ack_rd | ack_wr;
|
| 6852 |
|
|
|
| 6853 |
|
|
assign dq_o = dat_i;
|
| 6854 |
|
|
|
| 6855 |
|
|
endmodule
|
| 6856 |
|
|
`endif
|
| 6857 |
18 |
unneback |
//////////////////////////////////////////////////////////////////////
|
| 6858 |
|
|
//// ////
|
| 6859 |
|
|
//// Arithmetic functions ////
|
| 6860 |
|
|
//// ////
|
| 6861 |
|
|
//// Description ////
|
| 6862 |
|
|
//// Arithmetic functions for ALU and DSP ////
|
| 6863 |
|
|
//// ////
|
| 6864 |
|
|
//// ////
|
| 6865 |
|
|
//// To Do: ////
|
| 6866 |
|
|
//// - ////
|
| 6867 |
|
|
//// ////
|
| 6868 |
|
|
//// Author(s): ////
|
| 6869 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
| 6870 |
|
|
//// ORSoC AB ////
|
| 6871 |
|
|
//// ////
|
| 6872 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 6873 |
|
|
//// ////
|
| 6874 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
| 6875 |
|
|
//// ////
|
| 6876 |
|
|
//// This source file may be used and distributed without ////
|
| 6877 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 6878 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 6879 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 6880 |
|
|
//// ////
|
| 6881 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 6882 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 6883 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 6884 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 6885 |
|
|
//// later version. ////
|
| 6886 |
|
|
//// ////
|
| 6887 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 6888 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 6889 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 6890 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 6891 |
|
|
//// details. ////
|
| 6892 |
|
|
//// ////
|
| 6893 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 6894 |
|
|
//// Public License along with this source; if not, download it ////
|
| 6895 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 6896 |
|
|
//// ////
|
| 6897 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 6898 |
|
|
|
| 6899 |
40 |
unneback |
`ifdef MULTS
|
| 6900 |
18 |
unneback |
// signed multiplication
|
| 6901 |
40 |
unneback |
`define MODULE mults
|
| 6902 |
|
|
module `BASE`MODULE (a,b,p);
|
| 6903 |
|
|
`undef MODULE
|
| 6904 |
18 |
unneback |
parameter operand_a_width = 18;
|
| 6905 |
|
|
parameter operand_b_width = 18;
|
| 6906 |
|
|
parameter result_hi = 35;
|
| 6907 |
|
|
parameter result_lo = 0;
|
| 6908 |
|
|
input [operand_a_width-1:0] a;
|
| 6909 |
|
|
input [operand_b_width-1:0] b;
|
| 6910 |
|
|
output [result_hi:result_lo] p;
|
| 6911 |
|
|
wire signed [operand_a_width-1:0] ai;
|
| 6912 |
|
|
wire signed [operand_b_width-1:0] bi;
|
| 6913 |
|
|
wire signed [operand_a_width+operand_b_width-1:0] result;
|
| 6914 |
|
|
|
| 6915 |
|
|
assign ai = a;
|
| 6916 |
|
|
assign bi = b;
|
| 6917 |
|
|
assign result = ai * bi;
|
| 6918 |
|
|
assign p = result[result_hi:result_lo];
|
| 6919 |
|
|
|
| 6920 |
|
|
endmodule
|
| 6921 |
40 |
unneback |
`endif
|
| 6922 |
|
|
`ifdef MULTS18X18
|
| 6923 |
|
|
`define MODULE mults18x18
|
| 6924 |
|
|
module `BASE`MODULE (a,b,p);
|
| 6925 |
|
|
`undef MODULE
|
| 6926 |
18 |
unneback |
input [17:0] a,b;
|
| 6927 |
|
|
output [35:0] p;
|
| 6928 |
|
|
vl_mult
|
| 6929 |
|
|
# (.operand_a_width(18), .operand_b_width(18))
|
| 6930 |
|
|
mult0 (.a(a), .b(b), .p(p));
|
| 6931 |
|
|
endmodule
|
| 6932 |
40 |
unneback |
`endif
|
| 6933 |
18 |
unneback |
|
| 6934 |
40 |
unneback |
`ifdef MULT
|
| 6935 |
|
|
`define MODULE mult
|
| 6936 |
18 |
unneback |
// unsigned multiplication
|
| 6937 |
40 |
unneback |
module `BASE`MODULE (a,b,p);
|
| 6938 |
|
|
`undef MODULE
|
| 6939 |
18 |
unneback |
parameter operand_a_width = 18;
|
| 6940 |
|
|
parameter operand_b_width = 18;
|
| 6941 |
|
|
parameter result_hi = 35;
|
| 6942 |
|
|
parameter result_lo = 0;
|
| 6943 |
|
|
input [operand_a_width-1:0] a;
|
| 6944 |
|
|
input [operand_b_width-1:0] b;
|
| 6945 |
|
|
output [result_hi:result_hi] p;
|
| 6946 |
|
|
|
| 6947 |
|
|
wire [operand_a_width+operand_b_width-1:0] result;
|
| 6948 |
|
|
|
| 6949 |
|
|
assign result = a * b;
|
| 6950 |
|
|
assign p = result[result_hi:result_lo];
|
| 6951 |
|
|
|
| 6952 |
|
|
endmodule
|
| 6953 |
40 |
unneback |
`endif
|
| 6954 |
18 |
unneback |
|
| 6955 |
40 |
unneback |
`ifdef SHIFT_UNIT_32
|
| 6956 |
|
|
`define MODULE shift_unit_32
|
| 6957 |
18 |
unneback |
// shift unit
|
| 6958 |
|
|
// supporting the following shift functions
|
| 6959 |
|
|
// SLL
|
| 6960 |
|
|
// SRL
|
| 6961 |
|
|
// SRA
|
| 6962 |
|
|
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
|
| 6963 |
40 |
unneback |
module `BASE`MODULE( din, s, dout, opcode);
|
| 6964 |
|
|
`undef MODULE
|
| 6965 |
18 |
unneback |
input [31:0] din; // data in operand
|
| 6966 |
|
|
input [4:0] s; // shift operand
|
| 6967 |
|
|
input [1:0] opcode;
|
| 6968 |
|
|
output [31:0] dout;
|
| 6969 |
|
|
|
| 6970 |
|
|
parameter opcode_sll = 2'b00;
|
| 6971 |
|
|
//parameter opcode_srl = 2'b01;
|
| 6972 |
|
|
parameter opcode_sra = 2'b10;
|
| 6973 |
|
|
//parameter opcode_ror = 2'b11;
|
| 6974 |
|
|
|
| 6975 |
|
|
wire sll, sra;
|
| 6976 |
|
|
assign sll = opcode == opcode_sll;
|
| 6977 |
|
|
assign sra = opcode == opcode_sra;
|
| 6978 |
|
|
|
| 6979 |
|
|
wire [15:1] s1;
|
| 6980 |
|
|
wire [3:0] sign;
|
| 6981 |
|
|
wire [7:0] tmp [0:3];
|
| 6982 |
|
|
|
| 6983 |
|
|
// first stage is multiplier based
|
| 6984 |
|
|
// shift operand as fractional 8.7
|
| 6985 |
|
|
assign s1[15] = sll & s[2:0]==3'd7;
|
| 6986 |
|
|
assign s1[14] = sll & s[2:0]==3'd6;
|
| 6987 |
|
|
assign s1[13] = sll & s[2:0]==3'd5;
|
| 6988 |
|
|
assign s1[12] = sll & s[2:0]==3'd4;
|
| 6989 |
|
|
assign s1[11] = sll & s[2:0]==3'd3;
|
| 6990 |
|
|
assign s1[10] = sll & s[2:0]==3'd2;
|
| 6991 |
|
|
assign s1[ 9] = sll & s[2:0]==3'd1;
|
| 6992 |
|
|
assign s1[ 8] = s[2:0]==3'd0;
|
| 6993 |
|
|
assign s1[ 7] = !sll & s[2:0]==3'd1;
|
| 6994 |
|
|
assign s1[ 6] = !sll & s[2:0]==3'd2;
|
| 6995 |
|
|
assign s1[ 5] = !sll & s[2:0]==3'd3;
|
| 6996 |
|
|
assign s1[ 4] = !sll & s[2:0]==3'd4;
|
| 6997 |
|
|
assign s1[ 3] = !sll & s[2:0]==3'd5;
|
| 6998 |
|
|
assign s1[ 2] = !sll & s[2:0]==3'd6;
|
| 6999 |
|
|
assign s1[ 1] = !sll & s[2:0]==3'd7;
|
| 7000 |
|
|
|
| 7001 |
|
|
assign sign[3] = din[31] & sra;
|
| 7002 |
|
|
assign sign[2] = sign[3] & (&din[31:24]);
|
| 7003 |
|
|
assign sign[1] = sign[2] & (&din[23:16]);
|
| 7004 |
|
|
assign sign[0] = sign[1] & (&din[15:8]);
|
| 7005 |
40 |
unneback |
`define MODULE mults
|
| 7006 |
|
|
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
|
| 7007 |
|
|
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24] ,din[23:16], din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
|
| 7008 |
|
|
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16] ,din[15:8], din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
|
| 7009 |
|
|
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8] ,din[7:0], 8'h00}), .b({1'b0,s1}), .p(tmp[0]));
|
| 7010 |
|
|
`undef MODULE
|
| 7011 |
18 |
unneback |
// second stage is multiplexer based
|
| 7012 |
|
|
// shift on byte level
|
| 7013 |
|
|
|
| 7014 |
|
|
// mux byte 3
|
| 7015 |
|
|
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
|
| 7016 |
|
|
(sll & s[4:3]==2'b01) ? tmp[2] :
|
| 7017 |
|
|
(sll & s[4:3]==2'b10) ? tmp[1] :
|
| 7018 |
|
|
(sll & s[4:3]==2'b11) ? tmp[0] :
|
| 7019 |
|
|
{8{sign[3]}};
|
| 7020 |
|
|
|
| 7021 |
|
|
// mux byte 2
|
| 7022 |
|
|
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
|
| 7023 |
|
|
(sll & s[4:3]==2'b01) ? tmp[1] :
|
| 7024 |
|
|
(sll & s[4:3]==2'b10) ? tmp[0] :
|
| 7025 |
|
|
(sll & s[4:3]==2'b11) ? {8{1'b0}} :
|
| 7026 |
|
|
(s[4:3]==2'b01) ? tmp[3] :
|
| 7027 |
|
|
{8{sign[3]}};
|
| 7028 |
|
|
|
| 7029 |
|
|
// mux byte 1
|
| 7030 |
|
|
assign dout[15:8] = (s[4:3]==2'b00) ? tmp[1] :
|
| 7031 |
|
|
(sll & s[4:3]==2'b01) ? tmp[0] :
|
| 7032 |
|
|
(sll & s[4:3]==2'b10) ? {8{1'b0}} :
|
| 7033 |
|
|
(sll & s[4:3]==2'b11) ? {8{1'b0}} :
|
| 7034 |
|
|
(s[4:3]==2'b01) ? tmp[2] :
|
| 7035 |
|
|
(s[4:3]==2'b10) ? tmp[3] :
|
| 7036 |
|
|
{8{sign[3]}};
|
| 7037 |
|
|
|
| 7038 |
|
|
// mux byte 0
|
| 7039 |
|
|
assign dout[7:0] = (s[4:3]==2'b00) ? tmp[0] :
|
| 7040 |
|
|
(sll) ? {8{1'b0}}:
|
| 7041 |
|
|
(s[4:3]==2'b01) ? tmp[1] :
|
| 7042 |
|
|
(s[4:3]==2'b10) ? tmp[2] :
|
| 7043 |
|
|
tmp[3];
|
| 7044 |
|
|
|
| 7045 |
|
|
endmodule
|
| 7046 |
40 |
unneback |
`endif
|
| 7047 |
18 |
unneback |
|
| 7048 |
40 |
unneback |
`ifdef LOGIC_UNIT
|
| 7049 |
18 |
unneback |
// logic unit
|
| 7050 |
|
|
// supporting the following logic functions
|
| 7051 |
|
|
// a and b
|
| 7052 |
|
|
// a or b
|
| 7053 |
|
|
// a xor b
|
| 7054 |
|
|
// not b
|
| 7055 |
40 |
unneback |
`define MODULE logic_unit
|
| 7056 |
|
|
module `BASE`MODULE( a, b, result, opcode);
|
| 7057 |
|
|
`undef MODULE
|
| 7058 |
18 |
unneback |
parameter width = 32;
|
| 7059 |
|
|
parameter opcode_and = 2'b00;
|
| 7060 |
|
|
parameter opcode_or = 2'b01;
|
| 7061 |
|
|
parameter opcode_xor = 2'b10;
|
| 7062 |
|
|
input [width-1:0] a,b;
|
| 7063 |
|
|
output [width-1:0] result;
|
| 7064 |
|
|
input [1:0] opcode;
|
| 7065 |
|
|
|
| 7066 |
|
|
assign result = (opcode==opcode_and) ? a & b :
|
| 7067 |
|
|
(opcode==opcode_or) ? a | b :
|
| 7068 |
|
|
(opcode==opcode_xor) ? a ^ b :
|
| 7069 |
|
|
b;
|
| 7070 |
|
|
|
| 7071 |
|
|
endmodule
|
| 7072 |
48 |
unneback |
`endif
|
| 7073 |
18 |
unneback |
|
| 7074 |
48 |
unneback |
`ifdef ARITH_UNIT
|
| 7075 |
|
|
`define MODULE arith_unit
|
| 7076 |
|
|
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
|
| 7077 |
|
|
`undef MODULE
|
| 7078 |
18 |
unneback |
parameter width = 32;
|
| 7079 |
|
|
parameter opcode_add = 1'b0;
|
| 7080 |
|
|
parameter opcode_sub = 1'b1;
|
| 7081 |
|
|
input [width-1:0] a,b;
|
| 7082 |
|
|
input c_in, add_sub, sign;
|
| 7083 |
|
|
output [width-1:0] result;
|
| 7084 |
|
|
output c_out, z, ovfl;
|
| 7085 |
|
|
|
| 7086 |
|
|
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
|
| 7087 |
|
|
assign z = (result=={width{1'b0}});
|
| 7088 |
|
|
assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) |
|
| 7089 |
|
|
(~a[width-1] & ~b[width-1] & result[width-1]);
|
| 7090 |
|
|
endmodule
|
| 7091 |
40 |
unneback |
`endif
|
| 7092 |
48 |
unneback |
|
| 7093 |
|
|
`ifdef COUNT_UNIT
|
| 7094 |
|
|
`define MODULE count_unit
|
| 7095 |
|
|
module `BASE`MODULE (din, dout, opcode);
|
| 7096 |
|
|
`undef MODULE
|
| 7097 |
|
|
parameter width = 32;
|
| 7098 |
|
|
input [width-1:0] din;
|
| 7099 |
|
|
output [width-1:0] dout;
|
| 7100 |
|
|
input opcode;
|
| 7101 |
|
|
|
| 7102 |
|
|
integer i;
|
| 7103 |
58 |
unneback |
wire [width/32+4:0] ff1, fl1;
|
| 7104 |
48 |
unneback |
|
| 7105 |
57 |
unneback |
/*
|
| 7106 |
48 |
unneback |
always @(din) begin
|
| 7107 |
|
|
ff1 = 0; i = 0;
|
| 7108 |
|
|
while (din[i] == 0 && i < width) begin // complex condition
|
| 7109 |
|
|
ff1 = ff1 + 1;
|
| 7110 |
|
|
i = i + 1;
|
| 7111 |
|
|
end
|
| 7112 |
|
|
end
|
| 7113 |
|
|
|
| 7114 |
|
|
always @(din) begin
|
| 7115 |
|
|
fl1 = width; i = width-1;
|
| 7116 |
|
|
while (din[i] == 0 && i >= width) begin // complex condition
|
| 7117 |
|
|
fl1 = fl1 - 1;
|
| 7118 |
|
|
i = i - 1;
|
| 7119 |
|
|
end
|
| 7120 |
|
|
end
|
| 7121 |
57 |
unneback |
*/
|
| 7122 |
48 |
unneback |
|
| 7123 |
|
|
generate
|
| 7124 |
|
|
if (width==32) begin
|
| 7125 |
57 |
unneback |
|
| 7126 |
|
|
assign ff1 = din[0] ? 6'd1 :
|
| 7127 |
|
|
din[1] ? 6'd2 :
|
| 7128 |
|
|
din[2] ? 6'd3 :
|
| 7129 |
|
|
din[3] ? 6'd4 :
|
| 7130 |
|
|
din[4] ? 6'd5 :
|
| 7131 |
|
|
din[5] ? 6'd6 :
|
| 7132 |
|
|
din[6] ? 6'd7 :
|
| 7133 |
|
|
din[7] ? 6'd8 :
|
| 7134 |
|
|
din[8] ? 6'd9 :
|
| 7135 |
|
|
din[9] ? 6'd10 :
|
| 7136 |
|
|
din[10] ? 6'd11 :
|
| 7137 |
|
|
din[11] ? 6'd12 :
|
| 7138 |
|
|
din[12] ? 6'd13 :
|
| 7139 |
|
|
din[13] ? 6'd14 :
|
| 7140 |
|
|
din[14] ? 6'd15 :
|
| 7141 |
|
|
din[15] ? 6'd16 :
|
| 7142 |
|
|
din[16] ? 6'd17 :
|
| 7143 |
|
|
din[17] ? 6'd18 :
|
| 7144 |
|
|
din[18] ? 6'd19 :
|
| 7145 |
|
|
din[19] ? 6'd20 :
|
| 7146 |
|
|
din[20] ? 6'd21 :
|
| 7147 |
|
|
din[21] ? 6'd22 :
|
| 7148 |
|
|
din[22] ? 6'd23 :
|
| 7149 |
|
|
din[23] ? 6'd24 :
|
| 7150 |
|
|
din[24] ? 6'd25 :
|
| 7151 |
|
|
din[25] ? 6'd26 :
|
| 7152 |
|
|
din[26] ? 6'd27 :
|
| 7153 |
|
|
din[27] ? 6'd28 :
|
| 7154 |
|
|
din[28] ? 6'd29 :
|
| 7155 |
|
|
din[29] ? 6'd30 :
|
| 7156 |
|
|
din[30] ? 6'd31 :
|
| 7157 |
|
|
din[31] ? 6'd32 :
|
| 7158 |
|
|
6'd0;
|
| 7159 |
|
|
|
| 7160 |
|
|
assign fl1 = din[31] ? 6'd32 :
|
| 7161 |
|
|
din[30] ? 6'd31 :
|
| 7162 |
|
|
din[29] ? 6'd30 :
|
| 7163 |
|
|
din[28] ? 6'd29 :
|
| 7164 |
|
|
din[27] ? 6'd28 :
|
| 7165 |
|
|
din[26] ? 6'd27 :
|
| 7166 |
|
|
din[25] ? 6'd26 :
|
| 7167 |
|
|
din[24] ? 6'd25 :
|
| 7168 |
|
|
din[23] ? 6'd24 :
|
| 7169 |
|
|
din[22] ? 6'd23 :
|
| 7170 |
|
|
din[21] ? 6'd22 :
|
| 7171 |
|
|
din[20] ? 6'd21 :
|
| 7172 |
|
|
din[19] ? 6'd20 :
|
| 7173 |
|
|
din[18] ? 6'd19 :
|
| 7174 |
|
|
din[17] ? 6'd18 :
|
| 7175 |
|
|
din[16] ? 6'd17 :
|
| 7176 |
|
|
din[15] ? 6'd16 :
|
| 7177 |
|
|
din[14] ? 6'd15 :
|
| 7178 |
|
|
din[13] ? 6'd14 :
|
| 7179 |
|
|
din[12] ? 6'd13 :
|
| 7180 |
|
|
din[11] ? 6'd12 :
|
| 7181 |
|
|
din[10] ? 6'd11 :
|
| 7182 |
|
|
din[9] ? 6'd10 :
|
| 7183 |
|
|
din[8] ? 6'd9 :
|
| 7184 |
|
|
din[7] ? 6'd8 :
|
| 7185 |
|
|
din[6] ? 6'd7 :
|
| 7186 |
|
|
din[5] ? 6'd6 :
|
| 7187 |
|
|
din[4] ? 6'd5 :
|
| 7188 |
|
|
din[3] ? 6'd4 :
|
| 7189 |
|
|
din[2] ? 6'd3 :
|
| 7190 |
|
|
din[1] ? 6'd2 :
|
| 7191 |
|
|
din[0] ? 6'd1 :
|
| 7192 |
|
|
6'd0;
|
| 7193 |
|
|
|
| 7194 |
|
|
assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
|
| 7195 |
48 |
unneback |
end
|
| 7196 |
|
|
endgenerate
|
| 7197 |
57 |
unneback |
|
| 7198 |
48 |
unneback |
generate
|
| 7199 |
|
|
if (width==64) begin
|
| 7200 |
57 |
unneback |
assign ff1 = 7'd0;
|
| 7201 |
|
|
assign fl1 = 7'd0;
|
| 7202 |
|
|
assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
|
| 7203 |
48 |
unneback |
end
|
| 7204 |
|
|
endgenerate
|
| 7205 |
|
|
|
| 7206 |
|
|
endmodule
|
| 7207 |
|
|
`endif
|
| 7208 |
|
|
|
| 7209 |
|
|
`ifdef EXT_UNIT
|
| 7210 |
|
|
`define MODULE ext_unit
|
| 7211 |
|
|
module `BASE`MODULE ( a, b, F, result, opcode);
|
| 7212 |
|
|
`undef MODULE
|
| 7213 |
|
|
parameter width = 32;
|
| 7214 |
|
|
input [width-1:0] a, b;
|
| 7215 |
|
|
input F;
|
| 7216 |
|
|
output reg [width-1:0] result;
|
| 7217 |
|
|
input [2:0] opcode;
|
| 7218 |
|
|
|
| 7219 |
|
|
generate
|
| 7220 |
|
|
if (width==32) begin
|
| 7221 |
|
|
always @ (a or b or F or opcode)
|
| 7222 |
|
|
begin
|
| 7223 |
|
|
case (opcode)
|
| 7224 |
|
|
3'b000: result = {{24{1'b0}},a[7:0]};
|
| 7225 |
|
|
3'b001: result = {{24{a[7]}},a[7:0]};
|
| 7226 |
|
|
3'b010: result = {{16{1'b0}},a[7:0]};
|
| 7227 |
|
|
3'b011: result = {{16{a[15]}},a[15:0]};
|
| 7228 |
|
|
3'b110: result = (F) ? a : b;
|
| 7229 |
|
|
default: result = {b[15:0],16'h0000};
|
| 7230 |
|
|
endcase
|
| 7231 |
|
|
end
|
| 7232 |
|
|
end
|
| 7233 |
|
|
endgenerate
|
| 7234 |
|
|
|
| 7235 |
|
|
generate
|
| 7236 |
|
|
if (width==64) begin
|
| 7237 |
|
|
always @ (a or b or F or opcode)
|
| 7238 |
|
|
begin
|
| 7239 |
|
|
case (opcode)
|
| 7240 |
|
|
3'b000: result = {{56{1'b0}},a[7:0]};
|
| 7241 |
|
|
3'b001: result = {{56{a[7]}},a[7:0]};
|
| 7242 |
|
|
3'b010: result = {{48{1'b0}},a[7:0]};
|
| 7243 |
|
|
3'b011: result = {{48{a[15]}},a[15:0]};
|
| 7244 |
57 |
unneback |
3'b110: result = (F) ? a : b;
|
| 7245 |
48 |
unneback |
default: result = {32'h00000000,b[15:0],16'h0000};
|
| 7246 |
|
|
endcase
|
| 7247 |
|
|
end
|
| 7248 |
|
|
end
|
| 7249 |
|
|
endgenerate
|
| 7250 |
|
|
endmodule
|
| 7251 |
|
|
`endif
|
