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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 112

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
14
    // ACTEL FPGA should not use logic to handle rw collision
15
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16
`else
17
    `define SYN_NO_RW_CHECK
18
`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
23
`define SYNC_RST
24
`define PLL
25
 
26
`define MULTS
27
`define MULTS18X18
28
`define MULT
29
`define SHIFT_UNIT_32
30
`define LOGIC_UNIT
31
 
32
`define CNT_SHREG_WRAP
33
`define CNT_SHREG_CE_WRAP
34 105 unneback
`define CNT_SHREG_CLEAR
35 40 unneback
`define CNT_SHREG_CE_CLEAR
36
`define CNT_SHREG_CE_CLEAR_WRAP
37
 
38
`define MUX_ANDOR
39
`define MUX2_ANDOR
40
`define MUX3_ANDOR
41
`define MUX4_ANDOR
42
`define MUX5_ANDOR
43
`define MUX6_ANDOR
44 43 unneback
`define PARITY
45 40 unneback
 
46
`define ROM_INIT
47
`define RAM
48
`define RAM_BE
49
`define DPRAM_1R1W
50
`define DPRAM_2R1W
51 100 unneback
`define DPRAM_1R2W
52 40 unneback
`define DPRAM_2R2W
53 75 unneback
`define DPRAM_BE_2R2W
54 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
55
`define FIFO_2R2W_SYNC_SIMPLEX
56
`define FIFO_CMP_ASYNC
57
`define FIFO_1R1W_ASYNC
58
`define FIFO_2R2W_ASYNC
59
`define FIFO_2R2W_ASYNC_SIMPLEX
60 48 unneback
`define REG_FILE
61 40 unneback
 
62
`define DFF
63
`define DFF_ARRAY
64
`define DFF_CE
65
`define DFF_CE_CLEAR
66
`define DF_CE_SET
67
`define SPR
68
`define SRP
69
`define DFF_SR
70
`define LATCH
71
`define SHREG
72
`define SHREG_CE
73
`define DELAY
74
`define DELAY_EMPTYFLAG
75 94 unneback
`define PULSE2TOGGLE
76
`define TOGGLE2PULSE
77
`define SYNCHRONIZER
78
`define CDC
79 40 unneback
 
80 75 unneback
`define WB3AVALON_BRIDGE
81 40 unneback
`define WB3WB3_BRIDGE
82
`define WB3_ARBITER_TYPE1
83 83 unneback
`define WB_ADR_INC
84 101 unneback
`define WB_RAM
85 103 unneback
`define WB_SHADOW_RAM
86 48 unneback
`define WB_B4_ROM
87 40 unneback
`define WB_BOOT_ROM
88
`define WB_DPRAM
89 101 unneback
`define WB_CACHE
90 103 unneback
`define WB_AVALON_BRIDGE
91
`define WB_AVALON_MEM_CACHE
92 40 unneback
 
93 44 unneback
`define IO_DFF_OE
94
`define O_DFF
95
 
96 40 unneback
`endif
97
 
98
`ifdef PLL
99
`ifndef SYNC_RST
100
`define SYNC_RST
101
`endif
102
`endif
103
 
104
`ifdef SYNC_RST
105
`ifndef GBUF
106
`define GBUF
107
`endif
108
`endif
109
 
110 108 unneback
`ifdef WB_DPRAM
111 92 unneback
`ifndef WB_ADR_INC
112
`define WB_ADR_INC
113 40 unneback
`endif
114 92 unneback
`ifndef DPRAM_BE_2R2W
115
`define DPRAM_BE_2R2W
116 40 unneback
`endif
117
`endif
118
 
119 101 unneback
`ifdef WB_RAM
120 83 unneback
`ifndef WB_ADR_INC
121
`define WB_ADR_INC
122 62 unneback
`endif
123
`ifndef RAM_BE
124
`define RAM_BE
125
`endif
126
`endif
127
 
128 40 unneback
`ifdef WB3_ARBITER_TYPE1
129 42 unneback
`ifndef SPR
130
`define SPR
131
`endif
132 40 unneback
`ifndef MUX_ANDOR
133
`define MUX_ANDOR
134
`endif
135
`endif
136
 
137 76 unneback
`ifdef WB3AVALON_BRIDGE
138
`ifndef WB3WB3_BRIDGE
139
`define WB3WB3_BRIDGE
140
`endif
141
`endif
142
 
143 40 unneback
`ifdef WB3WB3_BRIDGE
144
`ifndef CNT_SHREG_CE_CLEAR
145
`define CNT_SHREG_CE_CLEAR
146
`endif
147
`ifndef DFF
148
`define DFF
149
`endif
150
`ifndef DFF_CE
151
`define DFF_CE
152
`endif
153
`ifndef CNT_SHREG_CE_CLEAR
154
`define CNT_SHREG_CE_CLEAR
155
`endif
156
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
157
`define FIFO_2R2W_ASYNC_SIMPLEX
158
`endif
159
`endif
160
 
161 103 unneback
 
162
`ifdef WB_AVALON_MEM_CACHE
163
`ifndef WB_SHADOW_RAM
164
`define WB_SHADOW_RAM
165
`endif
166
`ifndef WB_CACHE
167
`define WB_CACHE
168
`endif
169
`ifndef WB_AVALON_BRIDGE
170
`define WB_AVALON_BRIDGE
171
`endif
172
`endif
173
 
174 112 unneback
`ifdef WB_SHADOW_RAM
175
`ifndef WB_RAM
176
`define WB_RAM
177
`endif
178
`endif
179
 
180 101 unneback
`ifdef WB_CACHE
181 100 unneback
`ifndef RAM
182
`define RAM
183
`endif
184
`ifndef WB_ADR_INC
185
`define WB_ADR_INC
186
`endif
187
`ifndef DPRAM_1R1W
188
`define DPRAM_1R1W
189
`endif
190
`ifndef DPRAM_1R2W
191
`define DPRAM_1R2W
192
`endif
193
`ifndef DPRAM_BE_2R2W
194
`define DPRAM_BE_2R2W
195
`endif
196
`ifndef CDC
197
`define CDC
198
`endif
199
`endif
200 103 unneback
 
201
`ifdef WB_SHADOW_RAM
202
`ifndef WB_RAM
203
`define WB_RAM
204
`endif
205
`endif
206
 
207
`ifdef WB_RAM
208
`ifndef WB_ADR_INC
209
`define WB_ADR_INC
210
`endif
211
`endif
212 97 unneback
 
213 40 unneback
`ifdef MULTS18X18
214
`ifndef MULTS
215
`define MULTS
216
`endif
217
`endif
218
 
219
`ifdef SHIFT_UNIT_32
220
`ifndef MULTS
221
`define MULTS
222
`endif
223
`endif
224
 
225
`ifdef MUX2_ANDOR
226
`ifndef MUX_ANDOR
227
`define MUX_ANDOR
228
`endif
229
`endif
230
 
231
`ifdef MUX3_ANDOR
232
`ifndef MUX_ANDOR
233
`define MUX_ANDOR
234
`endif
235
`endif
236
 
237
`ifdef MUX4_ANDOR
238
`ifndef MUX_ANDOR
239
`define MUX_ANDOR
240
`endif
241
`endif
242
 
243
`ifdef MUX5_ANDOR
244
`ifndef MUX_ANDOR
245
`define MUX_ANDOR
246
`endif
247
`endif
248
 
249
`ifdef MUX6_ANDOR
250
`ifndef MUX_ANDOR
251
`define MUX_ANDOR
252
`endif
253
`endif
254
 
255
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
256
`ifndef CNT_BIN_CE
257
`define CNT_BIN_CE
258
`endif
259
`ifndef DPRAM_1R1W
260
`define DPRAM_1R1W
261
`endif
262
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
263
`define CNT_BIN_CE_REW_Q_ZQ_L1
264
`endif
265
`endif
266
 
267
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
268
`ifndef CNT_LFSR_CE
269
`define CNT_LFSR_CE
270
`endif
271
`ifndef DPRAM_2R2W
272
`define DPRAM_2R2W
273
`endif
274
`ifndef CNT_BIN_CE_REW_ZQ_L1
275
`define CNT_BIN_CE_REW_ZQ_L1
276
`endif
277
`endif
278
 
279
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
280
`ifndef CNT_GRAY_CE_BIN
281
`define CNT_GRAY_CE_BIN
282
`endif
283
`ifndef DPRAM_2R2W
284
`define DPRAM_2R2W
285
`endif
286
`ifndef FIFO_CMP_ASYNC
287
`define FIFO_CMP_ASYNC
288
`endif
289
`endif
290
 
291
`ifdef FIFO_2R2W_ASYNC
292
`ifndef FIFO_1R1W_ASYNC
293
`define FIFO_1R1W_ASYNC
294
`endif
295
`endif
296
 
297
`ifdef FIFO_1R1W_ASYNC
298
`ifndef CNT_GRAY_CE_BIN
299
`define CNT_GRAY_CE_BIN
300
`endif
301
`ifndef DPRAM_1R1W
302
`define DPRAM_1R1W
303
`endif
304
`ifndef FIFO_CMP_ASYNC
305
`define FIFO_CMP_ASYNC
306
`endif
307
`endif
308
 
309
`ifdef FIFO_CMP_ASYNC
310
`ifndef DFF_SR
311
`define DFF_SR
312
`endif
313
`ifndef DFF
314
`define DFF
315
`endif
316
`endif
317 48 unneback
 
318
`ifdef REG_FILE
319
`ifndef DPRAM_1R1W
320
`define DPRAM_1R1W
321
`endif
322
`endif
323 97 unneback
 
324 98 unneback
`ifdef CDC
325
`ifndef PULSE2TOGGLE
326
`define PULSE2TOGGLE
327
`endif
328
`ifndef TOGGLE2PULSE
329
`define TOGGLE2PULSE
330
`endif
331
`ifndef SYNCHRONIZER
332
`define SYNCHRONIZER
333
`endif
334
`endif
335
 
336 97 unneback
// size to width
337 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
338 62 unneback
//////////////////////////////////////////////////////////////////////
339 6 unneback
////                                                              ////
340
////  Versatile library, clock and reset                          ////
341
////                                                              ////
342
////  Description                                                 ////
343
////  Logic related to clock and reset                            ////
344
////                                                              ////
345
////                                                              ////
346
////  To Do:                                                      ////
347
////   - add more different registers                             ////
348
////                                                              ////
349
////  Author(s):                                                  ////
350
////      - Michael Unneback, unneback@opencores.org              ////
351
////        ORSoC AB                                              ////
352
////                                                              ////
353
//////////////////////////////////////////////////////////////////////
354
////                                                              ////
355
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
356
////                                                              ////
357
//// This source file may be used and distributed without         ////
358
//// restriction provided that this copyright statement is not    ////
359
//// removed from the file and that any derivative work contains  ////
360
//// the original copyright notice and the associated disclaimer. ////
361
////                                                              ////
362
//// This source file is free software; you can redistribute it   ////
363
//// and/or modify it under the terms of the GNU Lesser General   ////
364
//// Public License as published by the Free Software Foundation; ////
365
//// either version 2.1 of the License, or (at your option) any   ////
366
//// later version.                                               ////
367
////                                                              ////
368
//// This source is distributed in the hope that it will be       ////
369
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
370
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
371
//// PURPOSE.  See the GNU Lesser General Public License for more ////
372
//// details.                                                     ////
373
////                                                              ////
374
//// You should have received a copy of the GNU Lesser General    ////
375
//// Public License along with this source; if not, download it   ////
376
//// from http://www.opencores.org/lgpl.shtml                     ////
377
////                                                              ////
378
//////////////////////////////////////////////////////////////////////
379
 
380 48 unneback
`ifdef ACTEL
381
`ifdef GBUF
382
`timescale 1 ns/100 ps
383 6 unneback
// Global buffer
384
// usage:
385
// use to enable global buffers for high fan out signals such as clock and reset
386
// Version: 8.4 8.4.0.33
387
module gbuf(GL,CLK);
388
output GL;
389
input  CLK;
390
 
391
    wire GND;
392
 
393
    GND GND_1_net(.Y(GND));
394
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
395
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
396
 
397
endmodule
398
`timescale 1 ns/1 ns
399 40 unneback
`define MODULE gbuf
400
module `BASE`MODULE ( i, o);
401
`undef MODULE
402 6 unneback
input i;
403
output o;
404
`ifdef SIM_GBUF
405
assign o=i;
406
`else
407
gbuf gbuf_i0 ( .CLK(i), .GL(o));
408
`endif
409
endmodule
410 40 unneback
`endif
411 33 unneback
 
412 6 unneback
`else
413 33 unneback
 
414 40 unneback
`ifdef ALTERA
415
`ifdef GBUF
416 21 unneback
//altera
417 40 unneback
`define MODULE gbuf
418
module `BASE`MODULE ( i, o);
419
`undef MODULE
420 33 unneback
input i;
421
output o;
422
assign o = i;
423
endmodule
424 40 unneback
`endif
425 33 unneback
 
426 6 unneback
`else
427
 
428 40 unneback
`ifdef GBUF
429 6 unneback
`timescale 1 ns/100 ps
430 40 unneback
`define MODULE
431
module `BASE`MODULE ( i, o);
432
`undef MODULE
433 6 unneback
input i;
434
output o;
435
assign o = i;
436
endmodule
437 40 unneback
`endif
438 6 unneback
`endif // ALTERA
439
`endif //ACTEL
440
 
441 40 unneback
`ifdef SYNC_RST
442 6 unneback
// sync reset
443 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
444 6 unneback
// output active high global reset sync with two DFFs 
445
`timescale 1 ns/100 ps
446 40 unneback
`define MODULE sync_rst
447
module `BASE`MODULE ( rst_n_i, rst_o, clk);
448
`undef MODULE
449 6 unneback
input rst_n_i, clk;
450
output rst_o;
451 18 unneback
reg [1:0] tmp;
452 6 unneback
always @ (posedge clk or negedge rst_n_i)
453
if (!rst_n_i)
454 17 unneback
        tmp <= 2'b11;
455 6 unneback
else
456 33 unneback
        tmp <= {1'b0,tmp[1]};
457 40 unneback
`define MODULE gbuf
458
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
459
`undef MODULE
460 6 unneback
endmodule
461 40 unneback
`endif
462 6 unneback
 
463 40 unneback
`ifdef PLL
464 6 unneback
// vl_pll
465
`ifdef ACTEL
466 32 unneback
///////////////////////////////////////////////////////////////////////////////
467 17 unneback
`timescale 1 ps/1 ps
468 40 unneback
`define MODULE pll
469
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
470
`undef MODULE
471 6 unneback
parameter index = 0;
472
parameter number_of_clk = 1;
473 17 unneback
parameter period_time_0 = 20000;
474
parameter period_time_1 = 20000;
475
parameter period_time_2 = 20000;
476
parameter lock_delay = 2000000;
477 6 unneback
input clk_i, rst_n_i;
478
output lock;
479
output reg [0:number_of_clk-1] clk_o;
480
output [0:number_of_clk-1] rst_o;
481
 
482
`ifdef SIM_PLL
483
 
484
always
485
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
486
 
487
generate if (number_of_clk > 1)
488
always
489
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
490
endgenerate
491
 
492
generate if (number_of_clk > 2)
493
always
494
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
495
endgenerate
496
 
497
genvar i;
498
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
499
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
500
end
501
endgenerate
502
 
503
assign #lock_delay lock = rst_n_i;
504
 
505
endmodule
506
`else
507
generate if (number_of_clk==1 & index==0) begin
508
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
509
end
510
endgenerate // index==0
511
generate if (number_of_clk==1 & index==1) begin
512
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
513
end
514
endgenerate // index==1
515
generate if (number_of_clk==1 & index==2) begin
516
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
517
end
518
endgenerate // index==2
519
generate if (number_of_clk==1 & index==3) begin
520
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
521
end
522
endgenerate // index==0
523
 
524
generate if (number_of_clk==2 & index==0) begin
525
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
526
end
527
endgenerate // index==0
528
generate if (number_of_clk==2 & index==1) begin
529
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
530
end
531
endgenerate // index==1
532
generate if (number_of_clk==2 & index==2) begin
533
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
534
end
535
endgenerate // index==2
536
generate if (number_of_clk==2 & index==3) begin
537
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
538
end
539
endgenerate // index==0
540
 
541
generate if (number_of_clk==3 & index==0) begin
542
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
543
end
544
endgenerate // index==0
545
generate if (number_of_clk==3 & index==1) begin
546
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
547
end
548
endgenerate // index==1
549
generate if (number_of_clk==3 & index==2) begin
550
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
551
end
552
endgenerate // index==2
553
generate if (number_of_clk==3 & index==3) begin
554
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
555
end
556
endgenerate // index==0
557
 
558
genvar i;
559
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
560 40 unneback
`define MODULE sync_rst
561
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
562
`undef MODULE
563 6 unneback
end
564
endgenerate
565
endmodule
566
`endif
567 32 unneback
///////////////////////////////////////////////////////////////////////////////
568 6 unneback
 
569
`else
570
 
571 32 unneback
///////////////////////////////////////////////////////////////////////////////
572 6 unneback
`ifdef ALTERA
573
 
574 32 unneback
`timescale 1 ps/1 ps
575 40 unneback
`define MODULE pll
576
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
577
`undef MODULE
578 32 unneback
parameter index = 0;
579
parameter number_of_clk = 1;
580
parameter period_time_0 = 20000;
581
parameter period_time_1 = 20000;
582
parameter period_time_2 = 20000;
583
parameter period_time_3 = 20000;
584
parameter period_time_4 = 20000;
585
parameter lock_delay = 2000000;
586
input clk_i, rst_n_i;
587
output lock;
588
output reg [0:number_of_clk-1] clk_o;
589
output [0:number_of_clk-1] rst_o;
590
 
591
`ifdef SIM_PLL
592
 
593
always
594
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
595
 
596
generate if (number_of_clk > 1)
597
always
598
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
599
endgenerate
600
 
601
generate if (number_of_clk > 2)
602
always
603
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
604
endgenerate
605
 
606 33 unneback
generate if (number_of_clk > 3)
607 32 unneback
always
608
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
609
endgenerate
610
 
611 33 unneback
generate if (number_of_clk > 4)
612 32 unneback
always
613
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
614
endgenerate
615
 
616
genvar i;
617
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
618
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
619
end
620
endgenerate
621
 
622 33 unneback
//assign #lock_delay lock = rst_n_i;
623
assign lock = rst_n_i;
624 32 unneback
 
625
endmodule
626 6 unneback
`else
627
 
628 33 unneback
`ifdef VL_PLL0
629
`ifdef VL_PLL0_CLK1
630
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
631
`endif
632
`ifdef VL_PLL0_CLK2
633
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
634
`endif
635
`ifdef VL_PLL0_CLK3
636
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
637
`endif
638
`ifdef VL_PLL0_CLK4
639
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
640
`endif
641
`ifdef VL_PLL0_CLK5
642
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
643
`endif
644
`endif
645 32 unneback
 
646 33 unneback
`ifdef VL_PLL1
647
`ifdef VL_PLL1_CLK1
648
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
649
`endif
650
`ifdef VL_PLL1_CLK2
651
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
652
`endif
653
`ifdef VL_PLL1_CLK3
654
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
655
`endif
656
`ifdef VL_PLL1_CLK4
657
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
658
`endif
659
`ifdef VL_PLL1_CLK5
660
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
661
`endif
662
`endif
663 32 unneback
 
664 33 unneback
`ifdef VL_PLL2
665
`ifdef VL_PLL2_CLK1
666
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
667
`endif
668
`ifdef VL_PLL2_CLK2
669
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
670
`endif
671
`ifdef VL_PLL2_CLK3
672
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
673
`endif
674
`ifdef VL_PLL2_CLK4
675
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
676
`endif
677
`ifdef VL_PLL2_CLK5
678
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
679
`endif
680
`endif
681 32 unneback
 
682 33 unneback
`ifdef VL_PLL3
683
`ifdef VL_PLL3_CLK1
684
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
685
`endif
686
`ifdef VL_PLL3_CLK2
687
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
688
`endif
689
`ifdef VL_PLL3_CLK3
690
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
691
`endif
692
`ifdef VL_PLL3_CLK4
693
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
694
`endif
695
`ifdef VL_PLL3_CLK5
696
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
697
`endif
698
`endif
699 32 unneback
 
700
genvar i;
701
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
702 40 unneback
`define MODULE sync_rst
703
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
704
`undef MODULE
705 32 unneback
end
706
endgenerate
707
endmodule
708
`endif
709
///////////////////////////////////////////////////////////////////////////////
710
 
711
`else
712
 
713 6 unneback
// generic PLL
714 17 unneback
`timescale 1 ps/1 ps
715 40 unneback
`define MODULE pll
716
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
717
`undef MODULE
718 6 unneback
parameter index = 0;
719
parameter number_of_clk = 1;
720 17 unneback
parameter period_time_0 = 20000;
721
parameter period_time_1 = 20000;
722
parameter period_time_2 = 20000;
723 6 unneback
parameter lock_delay = 2000;
724
input clk_i, rst_n_i;
725
output lock;
726
output reg [0:number_of_clk-1] clk_o;
727
output [0:number_of_clk-1] rst_o;
728
 
729
always
730
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
731
 
732
generate if (number_of_clk > 1)
733
always
734
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
735
endgenerate
736
 
737
generate if (number_of_clk > 2)
738
always
739
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
740
endgenerate
741
 
742
genvar i;
743
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
744 40 unneback
`define MODULE sync_rst
745
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
746
`undef MODULE
747 6 unneback
end
748
endgenerate
749
 
750
assign #lock_delay lock = rst_n_i;
751
 
752
endmodule
753
 
754
`endif //altera
755 17 unneback
`endif //actel
756 40 unneback
`undef MODULE
757
`endif//////////////////////////////////////////////////////////////////////
758 6 unneback
////                                                              ////
759
////  Versatile library, registers                                ////
760
////                                                              ////
761
////  Description                                                 ////
762
////  Different type of registers                                 ////
763
////                                                              ////
764
////                                                              ////
765
////  To Do:                                                      ////
766
////   - add more different registers                             ////
767
////                                                              ////
768
////  Author(s):                                                  ////
769
////      - Michael Unneback, unneback@opencores.org              ////
770
////        ORSoC AB                                              ////
771
////                                                              ////
772
//////////////////////////////////////////////////////////////////////
773
////                                                              ////
774
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
775
////                                                              ////
776
//// This source file may be used and distributed without         ////
777
//// restriction provided that this copyright statement is not    ////
778
//// removed from the file and that any derivative work contains  ////
779
//// the original copyright notice and the associated disclaimer. ////
780
////                                                              ////
781
//// This source file is free software; you can redistribute it   ////
782
//// and/or modify it under the terms of the GNU Lesser General   ////
783
//// Public License as published by the Free Software Foundation; ////
784
//// either version 2.1 of the License, or (at your option) any   ////
785
//// later version.                                               ////
786
////                                                              ////
787
//// This source is distributed in the hope that it will be       ////
788
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
789
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
790
//// PURPOSE.  See the GNU Lesser General Public License for more ////
791
//// details.                                                     ////
792
////                                                              ////
793
//// You should have received a copy of the GNU Lesser General    ////
794
//// Public License along with this source; if not, download it   ////
795
//// from http://www.opencores.org/lgpl.shtml                     ////
796
////                                                              ////
797
//////////////////////////////////////////////////////////////////////
798
 
799 40 unneback
`ifdef DFF
800
`define MODULE dff
801
module `BASE`MODULE ( d, q, clk, rst);
802
`undef MODULE
803 6 unneback
        parameter width = 1;
804
        parameter reset_value = 0;
805
 
806
        input [width-1:0] d;
807
        input clk, rst;
808
        output reg [width-1:0] q;
809
 
810
        always @ (posedge clk or posedge rst)
811
        if (rst)
812
                q <= reset_value;
813
        else
814
                q <= d;
815
 
816
endmodule
817 40 unneback
`endif
818 6 unneback
 
819 40 unneback
`ifdef DFF_ARRAY
820
`define MODULE dff_array
821
module `BASE`MODULE ( d, q, clk, rst);
822
`undef MODULE
823 6 unneback
 
824
        parameter width = 1;
825
        parameter depth = 2;
826
        parameter reset_value = 1'b0;
827
 
828
        input [width-1:0] d;
829
        input clk, rst;
830
        output [width-1:0] q;
831
        reg  [0:depth-1] q_tmp [width-1:0];
832
        integer i;
833
        always @ (posedge clk or posedge rst)
834
        if (rst) begin
835
            for (i=0;i<depth;i=i+1)
836
                q_tmp[i] <= {width{reset_value}};
837
        end else begin
838
            q_tmp[0] <= d;
839
            for (i=1;i<depth;i=i+1)
840
                q_tmp[i] <= q_tmp[i-1];
841
        end
842
 
843
    assign q = q_tmp[depth-1];
844
 
845
endmodule
846 40 unneback
`endif
847 6 unneback
 
848 40 unneback
`ifdef DFF_CE
849
`define MODULE dff_ce
850
module `BASE`MODULE ( d, ce, q, clk, rst);
851
`undef MODULE
852 6 unneback
 
853
        parameter width = 1;
854
        parameter reset_value = 0;
855
 
856
        input [width-1:0] d;
857
        input ce, clk, rst;
858
        output reg [width-1:0] q;
859
 
860
        always @ (posedge clk or posedge rst)
861
        if (rst)
862
                q <= reset_value;
863
        else
864
                if (ce)
865
                        q <= d;
866
 
867
endmodule
868 40 unneback
`endif
869 6 unneback
 
870 40 unneback
`ifdef DFF_CE_CLEAR
871
`define MODULE dff_ce_clear
872
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
873
`undef MODULE
874 8 unneback
 
875
        parameter width = 1;
876
        parameter reset_value = 0;
877
 
878
        input [width-1:0] d;
879 10 unneback
        input ce, clear, clk, rst;
880 8 unneback
        output reg [width-1:0] q;
881
 
882
        always @ (posedge clk or posedge rst)
883
        if (rst)
884
            q <= reset_value;
885
        else
886
            if (ce)
887
                if (clear)
888
                    q <= {width{1'b0}};
889
                else
890
                    q <= d;
891
 
892
endmodule
893 40 unneback
`endif
894 8 unneback
 
895 40 unneback
`ifdef DF_CE_SET
896
`define MODULE dff_ce_set
897
module `BASE`MODULE ( d, ce, set, q, clk, rst);
898
`undef MODULE
899 24 unneback
 
900
        parameter width = 1;
901
        parameter reset_value = 0;
902
 
903
        input [width-1:0] d;
904
        input ce, set, clk, rst;
905
        output reg [width-1:0] q;
906
 
907
        always @ (posedge clk or posedge rst)
908
        if (rst)
909
            q <= reset_value;
910
        else
911
            if (ce)
912
                if (set)
913
                    q <= {width{1'b1}};
914
                else
915
                    q <= d;
916
 
917
endmodule
918 40 unneback
`endif
919 24 unneback
 
920 40 unneback
`ifdef SPR
921
`define MODULE spr
922
module `BASE`MODULE ( sp, r, q, clk, rst);
923
`undef MODULE
924
 
925 64 unneback
        //parameter width = 1;
926
        parameter reset_value = 1'b0;
927 29 unneback
 
928
        input sp, r;
929
        output reg q;
930
        input clk, rst;
931
 
932
        always @ (posedge clk or posedge rst)
933
        if (rst)
934
            q <= reset_value;
935
        else
936
            if (sp)
937
                q <= 1'b1;
938
            else if (r)
939
                q <= 1'b0;
940
 
941
endmodule
942 40 unneback
`endif
943 29 unneback
 
944 40 unneback
`ifdef SRP
945
`define MODULE srp
946
module `BASE`MODULE ( s, rp, q, clk, rst);
947
`undef MODULE
948
 
949 29 unneback
        parameter width = 1;
950
        parameter reset_value = 0;
951
 
952
        input s, rp;
953
        output reg q;
954
        input clk, rst;
955
 
956
        always @ (posedge clk or posedge rst)
957
        if (rst)
958
            q <= reset_value;
959
        else
960
            if (rp)
961
                q <= 1'b0;
962
            else if (s)
963
                q <= 1'b1;
964
 
965
endmodule
966 40 unneback
`endif
967 29 unneback
 
968 40 unneback
`ifdef ALTERA
969 29 unneback
 
970 40 unneback
`ifdef DFF_SR
971 6 unneback
// megafunction wizard: %LPM_FF%
972
// GENERATION: STANDARD
973
// VERSION: WM1.0
974
// MODULE: lpm_ff 
975
 
976
// ============================================================
977
// File Name: dff_sr.v
978
// Megafunction Name(s):
979
//                      lpm_ff
980
//
981
// Simulation Library Files(s):
982
//                      lpm
983
// ============================================================
984
// ************************************************************
985
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
986
//
987
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
988
// ************************************************************
989
 
990
 
991
//Copyright (C) 1991-2010 Altera Corporation
992
//Your use of Altera Corporation's design tools, logic functions 
993
//and other software and tools, and its AMPP partner logic 
994
//functions, and any output files from any of the foregoing 
995
//(including device programming or simulation files), and any 
996
//associated documentation or information are expressly subject 
997
//to the terms and conditions of the Altera Program License 
998
//Subscription Agreement, Altera MegaCore Function License 
999
//Agreement, or other applicable license agreement, including, 
1000
//without limitation, that your use is for the sole purpose of 
1001
//programming logic devices manufactured by Altera and sold by 
1002
//Altera or its authorized distributors.  Please refer to the 
1003
//applicable agreement for further details.
1004
 
1005
 
1006
// synopsys translate_off
1007
`timescale 1 ps / 1 ps
1008
// synopsys translate_on
1009 40 unneback
`define MODULE dff_sr
1010
module `BASE`MODULE (
1011
`undef MODULE
1012
 
1013 6 unneback
        aclr,
1014
        aset,
1015
        clock,
1016
        data,
1017
        q);
1018
 
1019
        input     aclr;
1020
        input     aset;
1021
        input     clock;
1022
        input     data;
1023
        output    q;
1024
 
1025
        wire [0:0] sub_wire0;
1026
        wire [0:0] sub_wire1 = sub_wire0[0:0];
1027
        wire  q = sub_wire1;
1028
        wire  sub_wire2 = data;
1029
        wire  sub_wire3 = sub_wire2;
1030
 
1031
        lpm_ff  lpm_ff_component (
1032
                                .aclr (aclr),
1033
                                .clock (clock),
1034
                                .data (sub_wire3),
1035
                                .aset (aset),
1036
                                .q (sub_wire0)
1037
                                // synopsys translate_off
1038
                                ,
1039
                                .aload (),
1040
                                .enable (),
1041
                                .sclr (),
1042
                                .sload (),
1043
                                .sset ()
1044
                                // synopsys translate_on
1045
                                );
1046
        defparam
1047
                lpm_ff_component.lpm_fftype = "DFF",
1048
                lpm_ff_component.lpm_type = "LPM_FF",
1049
                lpm_ff_component.lpm_width = 1;
1050
 
1051
 
1052
endmodule
1053
 
1054
// ============================================================
1055
// CNX file retrieval info
1056
// ============================================================
1057
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1058
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1059
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1060
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1061
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1062
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1063
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1064
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1065
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1066
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1067
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1068
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1069
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1070
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1071
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1072
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1073
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1074
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1075
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1076
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1077
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1078
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1079
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1080
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1081
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1082
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1083
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1084
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1085
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1086
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1087
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1088
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1089
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1090
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1091
// Retrieval info: LIB_FILE: lpm
1092 40 unneback
`endif
1093 6 unneback
 
1094
`else
1095
 
1096 40 unneback
`ifdef DFF_SR
1097
`define MODULE dff_sr
1098
module `BASE`MODULE ( aclr, aset, clock, data, q);
1099
`undef MODULE
1100 6 unneback
 
1101
    input         aclr;
1102
    input         aset;
1103
    input         clock;
1104
    input         data;
1105
    output reg    q;
1106
 
1107
   always @ (posedge clock or posedge aclr or posedge aset)
1108
     if (aclr)
1109
       q <= 1'b0;
1110
     else if (aset)
1111
       q <= 1'b1;
1112
     else
1113
       q <= data;
1114
 
1115
endmodule
1116 40 unneback
`endif
1117 6 unneback
 
1118
`endif
1119
 
1120
// LATCH
1121
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1122
`ifdef ALTERA
1123 40 unneback
 
1124
`ifdef LATCH
1125
`define MODULE latch
1126
module `BASE`MODULE ( d, le, q, clk);
1127
`undef MODULE
1128 6 unneback
input d, le;
1129
output q;
1130
input clk;
1131
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1132
endmodule
1133 40 unneback
`endif
1134
 
1135 6 unneback
`else
1136 40 unneback
 
1137
`ifdef LATCH
1138
`define MODULE latch
1139
module `BASE`MODULE ( d, le, q, clk);
1140
`undef MODULE
1141 6 unneback
input d, le;
1142 48 unneback
input clk;
1143
always @ (le or d)
1144 60 unneback
if (le)
1145 48 unneback
    d <= q;
1146 6 unneback
endmodule
1147 15 unneback
`endif
1148
 
1149 40 unneback
`endif
1150
 
1151
`ifdef SHREG
1152
`define MODULE shreg
1153
module `BASE`MODULE ( d, q, clk, rst);
1154
`undef MODULE
1155
 
1156 17 unneback
parameter depth = 10;
1157
input d;
1158
output q;
1159
input clk, rst;
1160
 
1161
reg [1:depth] dffs;
1162
 
1163
always @ (posedge clk or posedge rst)
1164
if (rst)
1165
    dffs <= {depth{1'b0}};
1166
else
1167
    dffs <= {d,dffs[1:depth-1]};
1168
assign q = dffs[depth];
1169
endmodule
1170 40 unneback
`endif
1171 17 unneback
 
1172 40 unneback
`ifdef SHREG_CE
1173
`define MODULE shreg_ce
1174
module `BASE`MODULE ( d, ce, q, clk, rst);
1175
`undef MODULE
1176 17 unneback
parameter depth = 10;
1177
input d, ce;
1178
output q;
1179
input clk, rst;
1180
 
1181
reg [1:depth] dffs;
1182
 
1183
always @ (posedge clk or posedge rst)
1184
if (rst)
1185
    dffs <= {depth{1'b0}};
1186
else
1187
    if (ce)
1188
        dffs <= {d,dffs[1:depth-1]};
1189
assign q = dffs[depth];
1190
endmodule
1191 40 unneback
`endif
1192 17 unneback
 
1193 40 unneback
`ifdef DELAY
1194
`define MODULE delay
1195
module `BASE`MODULE ( d, q, clk, rst);
1196
`undef MODULE
1197 15 unneback
parameter depth = 10;
1198
input d;
1199
output q;
1200
input clk, rst;
1201
 
1202
reg [1:depth] dffs;
1203
 
1204
always @ (posedge clk or posedge rst)
1205
if (rst)
1206
    dffs <= {depth{1'b0}};
1207
else
1208
    dffs <= {d,dffs[1:depth-1]};
1209
assign q = dffs[depth];
1210 17 unneback
endmodule
1211 40 unneback
`endif
1212 17 unneback
 
1213 40 unneback
`ifdef DELAY_EMPTYFLAG
1214
`define MODULE delay_emptyflag
1215 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1216 40 unneback
`undef MODULE
1217 17 unneback
parameter depth = 10;
1218
input d;
1219
output q, emptyflag;
1220
input clk, rst;
1221
 
1222
reg [1:depth] dffs;
1223
 
1224
always @ (posedge clk or posedge rst)
1225
if (rst)
1226
    dffs <= {depth{1'b0}};
1227
else
1228
    dffs <= {d,dffs[1:depth-1]};
1229
assign q = dffs[depth];
1230
assign emptyflag = !(|dffs);
1231
endmodule
1232 40 unneback
`endif
1233 75 unneback
 
1234 94 unneback
`ifdef PULSE2TOGGLE
1235 98 unneback
`define MODULE pulse2toggle
1236
module `BASE`MODULE ( pl, q, clk, rst);
1237 75 unneback
`undef MODULE
1238 94 unneback
input pl;
1239 98 unneback
output reg q;
1240 94 unneback
input clk, rst;
1241
always @ (posedge clk or posedge rst)
1242 75 unneback
if (rst)
1243 94 unneback
    q <= 1'b0;
1244 75 unneback
else
1245 94 unneback
    q <= pl ^ q;
1246
endmodule
1247
`endif
1248 75 unneback
 
1249 94 unneback
`ifdef TOGGLE2PULSE
1250 98 unneback
`define MODULE toggle2pulse
1251 94 unneback
module `BASE`MODULE (d, pl, clk, rst);
1252 97 unneback
`undef MODULE
1253 94 unneback
input d;
1254
output pl;
1255
input clk, rst;
1256
reg dff;
1257
always @ (posedge clk or posedge rst)
1258
if (rst)
1259
    dff <= 1'b0;
1260 75 unneback
else
1261 94 unneback
    dff <= d;
1262 98 unneback
assign pl = d ^ dff;
1263 94 unneback
endmodule
1264
`endif
1265 75 unneback
 
1266 94 unneback
`ifdef SYNCHRONIZER
1267
`define MODULE synchronizer
1268
module `BASE`MODULE (d, q, clk, rst);
1269
`undef MODULE
1270
input d;
1271
output reg q;
1272
output clk, rst;
1273
reg dff;
1274
always @ (posedge clk or posedge rst)
1275
if (rst)
1276 100 unneback
    {q,dff} <= 2'b00;
1277 75 unneback
else
1278 100 unneback
    {q,dff} <= {dff,d};
1279 94 unneback
endmodule
1280
`endif
1281 75 unneback
 
1282 94 unneback
`ifdef CDC
1283
`define MODULE cdc
1284 97 unneback
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1285 94 unneback
`undef MODULE
1286
input start_pl;
1287
output take_it_pl;
1288
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1289
output got_it_pl;
1290
input clk_src, rst_src;
1291
input clk_dst, rst_dst;
1292
wire take_it_tg, take_it_tg_sync;
1293
wire got_it_tg, got_it_tg_sync;
1294
// src -> dst
1295
`define MODULE pulse2toggle
1296
`BASE`MODULE p2t0 (
1297
`undef MODULE
1298
    .pl(start_pl),
1299
    .q(take_it_tg),
1300
    .clk(clk_src),
1301
    .rst(rst_src));
1302 75 unneback
 
1303 94 unneback
`define MODULE synchronizer
1304
`BASE`MODULE sync0 (
1305
`undef MODULE
1306
    .d(take_it_tg),
1307
    .q(take_it_tg_sync),
1308
    .clk(clk_dst),
1309
    .rst(rst_dst));
1310
 
1311
`define MODULE toggle2pulse
1312
`BASE`MODULE t2p0 (
1313
`undef MODULE
1314 100 unneback
    .d(take_it_tg_sync),
1315 94 unneback
    .pl(take_it_pl),
1316
    .clk(clk_dst),
1317
    .rst(rst_dst));
1318
 
1319
// dst -> src
1320
`define MODULE pulse2toggle
1321 98 unneback
`BASE`MODULE p2t1 (
1322 94 unneback
`undef MODULE
1323
    .pl(take_it_grant_pl),
1324
    .q(got_it_tg),
1325
    .clk(clk_dst),
1326
    .rst(rst_dst));
1327
 
1328
`define MODULE synchronizer
1329
`BASE`MODULE sync1 (
1330
`undef MODULE
1331
    .d(got_it_tg),
1332
    .q(got_it_tg_sync),
1333
    .clk(clk_src),
1334
    .rst(rst_src));
1335
 
1336
`define MODULE toggle2pulse
1337
`BASE`MODULE t2p1 (
1338
`undef MODULE
1339 100 unneback
    .d(got_it_tg_sync),
1340 94 unneback
    .pl(got_it_pl),
1341
    .clk(clk_src),
1342
    .rst(rst_src));
1343
 
1344 75 unneback
endmodule
1345
`endif
1346 17 unneback
//////////////////////////////////////////////////////////////////////
1347 6 unneback
////                                                              ////
1348 18 unneback
////  Logic functions                                             ////
1349
////                                                              ////
1350
////  Description                                                 ////
1351
////  Logic functions such as multiplexers                        ////
1352
////                                                              ////
1353
////                                                              ////
1354
////  To Do:                                                      ////
1355
////   -                                                          ////
1356
////                                                              ////
1357
////  Author(s):                                                  ////
1358
////      - Michael Unneback, unneback@opencores.org              ////
1359
////        ORSoC AB                                              ////
1360
////                                                              ////
1361
//////////////////////////////////////////////////////////////////////
1362
////                                                              ////
1363
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1364
////                                                              ////
1365
//// This source file may be used and distributed without         ////
1366
//// restriction provided that this copyright statement is not    ////
1367
//// removed from the file and that any derivative work contains  ////
1368
//// the original copyright notice and the associated disclaimer. ////
1369
////                                                              ////
1370
//// This source file is free software; you can redistribute it   ////
1371
//// and/or modify it under the terms of the GNU Lesser General   ////
1372
//// Public License as published by the Free Software Foundation; ////
1373
//// either version 2.1 of the License, or (at your option) any   ////
1374
//// later version.                                               ////
1375
////                                                              ////
1376
//// This source is distributed in the hope that it will be       ////
1377
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1378
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1379
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1380
//// details.                                                     ////
1381
////                                                              ////
1382
//// You should have received a copy of the GNU Lesser General    ////
1383
//// Public License along with this source; if not, download it   ////
1384
//// from http://www.opencores.org/lgpl.shtml                     ////
1385
////                                                              ////
1386
//////////////////////////////////////////////////////////////////////
1387 40 unneback
`ifdef MUX_ANDOR
1388
`define MODULE mux_andor
1389
module `BASE`MODULE ( a, sel, dout);
1390
`undef MODULE
1391 36 unneback
 
1392
parameter width = 32;
1393
parameter nr_of_ports = 4;
1394
 
1395
input [nr_of_ports*width-1:0] a;
1396
input [nr_of_ports-1:0] sel;
1397
output reg [width-1:0] dout;
1398
 
1399 38 unneback
integer i,j;
1400
 
1401 36 unneback
always @ (a, sel)
1402
begin
1403
    dout = a[width-1:0] & {width{sel[0]}};
1404 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1405
        for (j=0;j<width;j=j+1)
1406
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1407 36 unneback
end
1408
 
1409
endmodule
1410 40 unneback
`endif
1411 36 unneback
 
1412 40 unneback
`ifdef MUX2_ANDOR
1413
`define MODULE mux2_andor
1414
module `BASE`MODULE ( a1, a0, sel, dout);
1415
`undef MODULE
1416 18 unneback
 
1417 34 unneback
parameter width = 32;
1418 35 unneback
localparam nr_of_ports = 2;
1419 34 unneback
input [width-1:0] a1, a0;
1420
input [nr_of_ports-1:0] sel;
1421
output [width-1:0] dout;
1422
 
1423 40 unneback
`define MODULE mux_andor
1424
`BASE`MODULE
1425 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1426 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1427 40 unneback
`undef MODULE
1428
 
1429 34 unneback
endmodule
1430 40 unneback
`endif
1431 34 unneback
 
1432 40 unneback
`ifdef MUX3_ANDOR
1433
`define MODULE mux3_andor
1434
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1435
`undef MODULE
1436 34 unneback
 
1437
parameter width = 32;
1438 35 unneback
localparam nr_of_ports = 3;
1439 34 unneback
input [width-1:0] a2, a1, a0;
1440
input [nr_of_ports-1:0] sel;
1441
output [width-1:0] dout;
1442
 
1443 40 unneback
`define MODULE mux_andor
1444
`BASE`MODULE
1445 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1446 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1447 40 unneback
`undef MODULE
1448 34 unneback
endmodule
1449 40 unneback
`endif
1450 34 unneback
 
1451 40 unneback
`ifdef MUX4_ANDOR
1452
`define MODULE mux4_andor
1453
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1454
`undef MODULE
1455 18 unneback
 
1456
parameter width = 32;
1457 35 unneback
localparam nr_of_ports = 4;
1458 18 unneback
input [width-1:0] a3, a2, a1, a0;
1459
input [nr_of_ports-1:0] sel;
1460 22 unneback
output [width-1:0] dout;
1461 18 unneback
 
1462 40 unneback
`define MODULE mux_andor
1463
`BASE`MODULE
1464 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1465 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1466 40 unneback
`undef MODULE
1467 18 unneback
 
1468
endmodule
1469 40 unneback
`endif
1470 18 unneback
 
1471 40 unneback
`ifdef MUX5_ANDOR
1472
`define MODULE mux5_andor
1473
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1474
`undef MODULE
1475 18 unneback
 
1476
parameter width = 32;
1477 35 unneback
localparam nr_of_ports = 5;
1478 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1479
input [nr_of_ports-1:0] sel;
1480 22 unneback
output [width-1:0] dout;
1481 18 unneback
 
1482 40 unneback
`define MODULE mux_andor
1483
`BASE`MODULE
1484 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1485 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1486 40 unneback
`undef MODULE
1487 18 unneback
 
1488
endmodule
1489 40 unneback
`endif
1490 18 unneback
 
1491 40 unneback
`ifdef MUX6_ANDOR
1492
`define MODULE mux6_andor
1493
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1494
`undef MODULE
1495 18 unneback
 
1496
parameter width = 32;
1497 35 unneback
localparam nr_of_ports = 6;
1498 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1499
input [nr_of_ports-1:0] sel;
1500 22 unneback
output [width-1:0] dout;
1501 18 unneback
 
1502 40 unneback
`define MODULE mux_andor
1503
`BASE`MODULE
1504 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1505 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1506 40 unneback
`undef MODULE
1507 18 unneback
 
1508
endmodule
1509 40 unneback
`endif
1510 43 unneback
 
1511
`ifdef PARITY
1512
 
1513
`define MODULE parity_generate
1514
module `BASE`MODULE (data, parity);
1515
`undef MODULE
1516
parameter word_size = 32;
1517
parameter chunk_size = 8;
1518
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1519
input [word_size-1:0] data;
1520
output reg [word_size/chunk_size-1:0] parity;
1521
integer i,j;
1522
always @ (data)
1523
for (i=0;i<word_size/chunk_size;i=i+1) begin
1524
    parity[i] = parity_type;
1525
    for (j=0;j<chunk_size;j=j+1) begin
1526 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1527 43 unneback
    end
1528
end
1529
endmodule
1530
 
1531
`define MODULE parity_check
1532
module `BASE`MODULE( data, parity, parity_error);
1533
`undef MODULE
1534
parameter word_size = 32;
1535
parameter chunk_size = 8;
1536
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1537
input [word_size-1:0] data;
1538
input [word_size/chunk_size-1:0] parity;
1539
output parity_error;
1540 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1541 43 unneback
integer i,j;
1542
always @ (data or parity)
1543
for (i=0;i<word_size/chunk_size;i=i+1) begin
1544
    error_flag[i] = parity[i] ^ parity_type;
1545
    for (j=0;j<chunk_size;j=j+1) begin
1546 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1547 43 unneback
    end
1548
end
1549
assign parity_error = |error_flag;
1550
endmodule
1551
 
1552 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1553
////                                                              ////
1554
////  IO functions                                                ////
1555
////                                                              ////
1556
////  Description                                                 ////
1557
////  IO functions such as IOB flip-flops                         ////
1558
////                                                              ////
1559
////                                                              ////
1560
////  To Do:                                                      ////
1561
////   -                                                          ////
1562
////                                                              ////
1563
////  Author(s):                                                  ////
1564
////      - Michael Unneback, unneback@opencores.org              ////
1565
////        ORSoC AB                                              ////
1566
////                                                              ////
1567 18 unneback
//////////////////////////////////////////////////////////////////////
1568
////                                                              ////
1569 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1570
////                                                              ////
1571
//// This source file may be used and distributed without         ////
1572
//// restriction provided that this copyright statement is not    ////
1573
//// removed from the file and that any derivative work contains  ////
1574
//// the original copyright notice and the associated disclaimer. ////
1575
////                                                              ////
1576
//// This source file is free software; you can redistribute it   ////
1577
//// and/or modify it under the terms of the GNU Lesser General   ////
1578
//// Public License as published by the Free Software Foundation; ////
1579
//// either version 2.1 of the License, or (at your option) any   ////
1580
//// later version.                                               ////
1581
////                                                              ////
1582
//// This source is distributed in the hope that it will be       ////
1583
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1584
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1585
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1586
//// details.                                                     ////
1587
////                                                              ////
1588
//// You should have received a copy of the GNU Lesser General    ////
1589
//// Public License along with this source; if not, download it   ////
1590
//// from http://www.opencores.org/lgpl.shtml                     ////
1591
////                                                              ////
1592
//////////////////////////////////////////////////////////////////////
1593 45 unneback
`timescale 1ns/1ns
1594 44 unneback
`ifdef O_DFF
1595
`define MODULE o_dff
1596
module `BASE`MODULE (d_i, o_pad, clk, rst);
1597
`undef MODULE
1598
parameter width = 1;
1599 45 unneback
parameter reset_value = {width{1'b0}};
1600
input  [width-1:0]  d_i;
1601 44 unneback
output [width-1:0] o_pad;
1602
input clk, rst;
1603
wire [width-1:0] d_i_int `SYN_KEEP;
1604 45 unneback
reg  [width-1:0] o_pad_int;
1605 44 unneback
assign d_i_int = d_i;
1606
genvar i;
1607 45 unneback
generate
1608 44 unneback
for (i=0;i<width;i=i+1) begin
1609
    always @ (posedge clk or posedge rst)
1610
    if (rst)
1611 45 unneback
        o_pad_int[i] <= reset_value[i];
1612 44 unneback
    else
1613 45 unneback
        o_pad_int[i] <= d_i_int[i];
1614
    assign #1 o_pad[i] = o_pad_int[i];
1615 44 unneback
end
1616
endgenerate
1617
endmodule
1618
`endif
1619
 
1620 45 unneback
`timescale 1ns/1ns
1621 44 unneback
`ifdef IO_DFF_OE
1622
`define MODULE io_dff_oe
1623
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1624
`undef MODULE
1625
parameter width = 1;
1626
input  [width-1:0] d_o;
1627
output reg [width-1:0] d_i;
1628
input oe;
1629
inout [width-1:0] io_pad;
1630
input clk, rst;
1631
wire [width-1:0] oe_d `SYN_KEEP;
1632
reg [width-1:0] oe_q;
1633
reg [width-1:0] d_o_q;
1634
assign oe_d = {width{oe}};
1635
genvar i;
1636
generate
1637
for (i=0;i<width;i=i+1) begin
1638
    always @ (posedge clk or posedge rst)
1639
    if (rst)
1640
        oe_q[i] <= 1'b0;
1641
    else
1642
        oe_q[i] <= oe_d[i];
1643
    always @ (posedge clk or posedge rst)
1644
    if (rst)
1645
        d_o_q[i] <= 1'b0;
1646
    else
1647
        d_o_q[i] <= d_o[i];
1648
    always @ (posedge clk or posedge rst)
1649
    if (rst)
1650
        d_i[i] <= 1'b0;
1651
    else
1652
        d_i[i] <= io_pad[i];
1653 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1654 44 unneback
end
1655
endgenerate
1656
endmodule
1657
`endif
1658
`ifdef CNT_BIN
1659
//////////////////////////////////////////////////////////////////////
1660
////                                                              ////
1661 6 unneback
////  Versatile counter                                           ////
1662
////                                                              ////
1663
////  Description                                                 ////
1664
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1665
////  counter                                                     ////
1666
////                                                              ////
1667
////  To Do:                                                      ////
1668
////   - add LFSR with more taps                                  ////
1669
////                                                              ////
1670
////  Author(s):                                                  ////
1671
////      - Michael Unneback, unneback@opencores.org              ////
1672
////        ORSoC AB                                              ////
1673
////                                                              ////
1674
//////////////////////////////////////////////////////////////////////
1675
////                                                              ////
1676
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1677
////                                                              ////
1678
//// This source file may be used and distributed without         ////
1679
//// restriction provided that this copyright statement is not    ////
1680
//// removed from the file and that any derivative work contains  ////
1681
//// the original copyright notice and the associated disclaimer. ////
1682
////                                                              ////
1683
//// This source file is free software; you can redistribute it   ////
1684
//// and/or modify it under the terms of the GNU Lesser General   ////
1685
//// Public License as published by the Free Software Foundation; ////
1686
//// either version 2.1 of the License, or (at your option) any   ////
1687
//// later version.                                               ////
1688
////                                                              ////
1689
//// This source is distributed in the hope that it will be       ////
1690
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1691
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1692
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1693
//// details.                                                     ////
1694
////                                                              ////
1695
//// You should have received a copy of the GNU Lesser General    ////
1696
//// Public License along with this source; if not, download it   ////
1697
//// from http://www.opencores.org/lgpl.shtml                     ////
1698
////                                                              ////
1699
//////////////////////////////////////////////////////////////////////
1700
 
1701
// binary counter
1702 22 unneback
 
1703 40 unneback
`define MODULE cnt_bin
1704
module `BASE`MODULE (
1705
`undef MODULE
1706
 q, rst, clk);
1707
 
1708 22 unneback
   parameter length = 4;
1709
   output [length:1] q;
1710
   input rst;
1711
   input clk;
1712
 
1713
   parameter clear_value = 0;
1714
   parameter set_value = 1;
1715
   parameter wrap_value = 0;
1716
   parameter level1_value = 15;
1717
 
1718
   reg  [length:1] qi;
1719
   wire [length:1] q_next;
1720
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1721
 
1722
   always @ (posedge clk or posedge rst)
1723
     if (rst)
1724
       qi <= {length{1'b0}};
1725
     else
1726
       qi <= q_next;
1727
 
1728
   assign q = qi;
1729
 
1730
endmodule
1731 40 unneback
`endif
1732
`ifdef CNT_BIN_CLEAR
1733 22 unneback
//////////////////////////////////////////////////////////////////////
1734
////                                                              ////
1735
////  Versatile counter                                           ////
1736
////                                                              ////
1737
////  Description                                                 ////
1738
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1739
////  counter                                                     ////
1740
////                                                              ////
1741
////  To Do:                                                      ////
1742
////   - add LFSR with more taps                                  ////
1743
////                                                              ////
1744
////  Author(s):                                                  ////
1745
////      - Michael Unneback, unneback@opencores.org              ////
1746
////        ORSoC AB                                              ////
1747
////                                                              ////
1748
//////////////////////////////////////////////////////////////////////
1749
////                                                              ////
1750
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1751
////                                                              ////
1752
//// This source file may be used and distributed without         ////
1753
//// restriction provided that this copyright statement is not    ////
1754
//// removed from the file and that any derivative work contains  ////
1755
//// the original copyright notice and the associated disclaimer. ////
1756
////                                                              ////
1757
//// This source file is free software; you can redistribute it   ////
1758
//// and/or modify it under the terms of the GNU Lesser General   ////
1759
//// Public License as published by the Free Software Foundation; ////
1760
//// either version 2.1 of the License, or (at your option) any   ////
1761
//// later version.                                               ////
1762
////                                                              ////
1763
//// This source is distributed in the hope that it will be       ////
1764
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1765
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1766
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1767
//// details.                                                     ////
1768
////                                                              ////
1769
//// You should have received a copy of the GNU Lesser General    ////
1770
//// Public License along with this source; if not, download it   ////
1771
//// from http://www.opencores.org/lgpl.shtml                     ////
1772
////                                                              ////
1773
//////////////////////////////////////////////////////////////////////
1774
 
1775
// binary counter
1776
 
1777 40 unneback
`define MODULE cnt_bin_clear
1778
module `BASE`MODULE (
1779
`undef MODULE
1780
 clear, q, rst, clk);
1781
 
1782 22 unneback
   parameter length = 4;
1783
   input clear;
1784
   output [length:1] q;
1785
   input rst;
1786
   input clk;
1787
 
1788
   parameter clear_value = 0;
1789
   parameter set_value = 1;
1790
   parameter wrap_value = 0;
1791
   parameter level1_value = 15;
1792
 
1793
   reg  [length:1] qi;
1794
   wire [length:1] q_next;
1795
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1796
 
1797
   always @ (posedge clk or posedge rst)
1798
     if (rst)
1799
       qi <= {length{1'b0}};
1800
     else
1801
       qi <= q_next;
1802
 
1803
   assign q = qi;
1804
 
1805
endmodule
1806 40 unneback
`endif
1807
`ifdef CNT_BIN_CE
1808 22 unneback
//////////////////////////////////////////////////////////////////////
1809
////                                                              ////
1810
////  Versatile counter                                           ////
1811
////                                                              ////
1812
////  Description                                                 ////
1813
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1814
////  counter                                                     ////
1815
////                                                              ////
1816
////  To Do:                                                      ////
1817
////   - add LFSR with more taps                                  ////
1818
////                                                              ////
1819
////  Author(s):                                                  ////
1820
////      - Michael Unneback, unneback@opencores.org              ////
1821
////        ORSoC AB                                              ////
1822
////                                                              ////
1823
//////////////////////////////////////////////////////////////////////
1824
////                                                              ////
1825
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1826
////                                                              ////
1827
//// This source file may be used and distributed without         ////
1828
//// restriction provided that this copyright statement is not    ////
1829
//// removed from the file and that any derivative work contains  ////
1830
//// the original copyright notice and the associated disclaimer. ////
1831
////                                                              ////
1832
//// This source file is free software; you can redistribute it   ////
1833
//// and/or modify it under the terms of the GNU Lesser General   ////
1834
//// Public License as published by the Free Software Foundation; ////
1835
//// either version 2.1 of the License, or (at your option) any   ////
1836
//// later version.                                               ////
1837
////                                                              ////
1838
//// This source is distributed in the hope that it will be       ////
1839
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1840
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1841
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1842
//// details.                                                     ////
1843
////                                                              ////
1844
//// You should have received a copy of the GNU Lesser General    ////
1845
//// Public License along with this source; if not, download it   ////
1846
//// from http://www.opencores.org/lgpl.shtml                     ////
1847
////                                                              ////
1848
//////////////////////////////////////////////////////////////////////
1849
 
1850
// binary counter
1851 6 unneback
 
1852 40 unneback
`define MODULE cnt_bin_ce
1853
module `BASE`MODULE (
1854
`undef MODULE
1855
 cke, q, rst, clk);
1856
 
1857 6 unneback
   parameter length = 4;
1858
   input cke;
1859
   output [length:1] q;
1860
   input rst;
1861
   input clk;
1862
 
1863
   parameter clear_value = 0;
1864
   parameter set_value = 1;
1865
   parameter wrap_value = 0;
1866
   parameter level1_value = 15;
1867
 
1868
   reg  [length:1] qi;
1869
   wire [length:1] q_next;
1870
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1871
 
1872
   always @ (posedge clk or posedge rst)
1873
     if (rst)
1874
       qi <= {length{1'b0}};
1875
     else
1876
     if (cke)
1877
       qi <= q_next;
1878
 
1879
   assign q = qi;
1880
 
1881
endmodule
1882 40 unneback
`endif
1883
`ifdef CNT_BIN_CE_CLEAR
1884 6 unneback
//////////////////////////////////////////////////////////////////////
1885
////                                                              ////
1886
////  Versatile counter                                           ////
1887
////                                                              ////
1888
////  Description                                                 ////
1889
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1890
////  counter                                                     ////
1891
////                                                              ////
1892
////  To Do:                                                      ////
1893
////   - add LFSR with more taps                                  ////
1894
////                                                              ////
1895
////  Author(s):                                                  ////
1896
////      - Michael Unneback, unneback@opencores.org              ////
1897
////        ORSoC AB                                              ////
1898
////                                                              ////
1899
//////////////////////////////////////////////////////////////////////
1900
////                                                              ////
1901
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1902
////                                                              ////
1903
//// This source file may be used and distributed without         ////
1904
//// restriction provided that this copyright statement is not    ////
1905
//// removed from the file and that any derivative work contains  ////
1906
//// the original copyright notice and the associated disclaimer. ////
1907
////                                                              ////
1908
//// This source file is free software; you can redistribute it   ////
1909
//// and/or modify it under the terms of the GNU Lesser General   ////
1910
//// Public License as published by the Free Software Foundation; ////
1911
//// either version 2.1 of the License, or (at your option) any   ////
1912
//// later version.                                               ////
1913
////                                                              ////
1914
//// This source is distributed in the hope that it will be       ////
1915
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1916
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1917
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1918
//// details.                                                     ////
1919
////                                                              ////
1920
//// You should have received a copy of the GNU Lesser General    ////
1921
//// Public License along with this source; if not, download it   ////
1922
//// from http://www.opencores.org/lgpl.shtml                     ////
1923
////                                                              ////
1924
//////////////////////////////////////////////////////////////////////
1925
 
1926
// binary counter
1927
 
1928 40 unneback
`define MODULE cnt_bin_ce_clear
1929
module `BASE`MODULE (
1930
`undef MODULE
1931
 clear, cke, q, rst, clk);
1932
 
1933 6 unneback
   parameter length = 4;
1934
   input clear;
1935
   input cke;
1936
   output [length:1] q;
1937
   input rst;
1938
   input clk;
1939
 
1940
   parameter clear_value = 0;
1941
   parameter set_value = 1;
1942
   parameter wrap_value = 0;
1943
   parameter level1_value = 15;
1944
 
1945
   reg  [length:1] qi;
1946
   wire [length:1] q_next;
1947
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1948
 
1949
   always @ (posedge clk or posedge rst)
1950
     if (rst)
1951
       qi <= {length{1'b0}};
1952
     else
1953
     if (cke)
1954
       qi <= q_next;
1955
 
1956
   assign q = qi;
1957
 
1958
endmodule
1959 40 unneback
`endif
1960
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1961 6 unneback
//////////////////////////////////////////////////////////////////////
1962
////                                                              ////
1963
////  Versatile counter                                           ////
1964
////                                                              ////
1965
////  Description                                                 ////
1966
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1967
////  counter                                                     ////
1968
////                                                              ////
1969
////  To Do:                                                      ////
1970
////   - add LFSR with more taps                                  ////
1971
////                                                              ////
1972
////  Author(s):                                                  ////
1973
////      - Michael Unneback, unneback@opencores.org              ////
1974
////        ORSoC AB                                              ////
1975
////                                                              ////
1976
//////////////////////////////////////////////////////////////////////
1977
////                                                              ////
1978
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1979
////                                                              ////
1980
//// This source file may be used and distributed without         ////
1981
//// restriction provided that this copyright statement is not    ////
1982
//// removed from the file and that any derivative work contains  ////
1983
//// the original copyright notice and the associated disclaimer. ////
1984
////                                                              ////
1985
//// This source file is free software; you can redistribute it   ////
1986
//// and/or modify it under the terms of the GNU Lesser General   ////
1987
//// Public License as published by the Free Software Foundation; ////
1988
//// either version 2.1 of the License, or (at your option) any   ////
1989
//// later version.                                               ////
1990
////                                                              ////
1991
//// This source is distributed in the hope that it will be       ////
1992
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1993
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1994
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1995
//// details.                                                     ////
1996
////                                                              ////
1997
//// You should have received a copy of the GNU Lesser General    ////
1998
//// Public License along with this source; if not, download it   ////
1999
//// from http://www.opencores.org/lgpl.shtml                     ////
2000
////                                                              ////
2001
//////////////////////////////////////////////////////////////////////
2002
 
2003
// binary counter
2004 29 unneback
 
2005 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
2006
module `BASE`MODULE (
2007
`undef MODULE
2008
 clear, cke, q, level1, level2, rst, clk);
2009
 
2010 29 unneback
   parameter length = 4;
2011
   input clear;
2012
   input cke;
2013
   output [length:1] q;
2014
   output reg level1;
2015
   output reg level2;
2016
   input rst;
2017
   input clk;
2018
 
2019
   parameter clear_value = 0;
2020
   parameter set_value = 1;
2021 30 unneback
   parameter wrap_value = 15;
2022
   parameter level1_value = 8;
2023
   parameter level2_value = 15;
2024 29 unneback
 
2025
   wire rew;
2026 30 unneback
   assign rew = 1'b0;
2027 29 unneback
   reg  [length:1] qi;
2028
   wire [length:1] q_next;
2029
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2030
 
2031
   always @ (posedge clk or posedge rst)
2032
     if (rst)
2033
       qi <= {length{1'b0}};
2034
     else
2035
     if (cke)
2036
       qi <= q_next;
2037
 
2038
   assign q = qi;
2039
 
2040
 
2041
    always @ (posedge clk or posedge rst)
2042
    if (rst)
2043
        level1 <= 1'b0;
2044
    else
2045
    if (cke)
2046
    if (clear)
2047
        level1 <= 1'b0;
2048
    else if (q_next == level1_value)
2049
        level1 <= 1'b1;
2050
    else if (qi == level1_value & rew)
2051
        level1 <= 1'b0;
2052
 
2053
    always @ (posedge clk or posedge rst)
2054
    if (rst)
2055
        level2 <= 1'b0;
2056
    else
2057
    if (cke)
2058
    if (clear)
2059
        level2 <= 1'b0;
2060
    else if (q_next == level2_value)
2061
        level2 <= 1'b1;
2062
    else if (qi == level2_value & rew)
2063
        level2 <= 1'b0;
2064
endmodule
2065 40 unneback
`endif
2066
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2067 29 unneback
//////////////////////////////////////////////////////////////////////
2068
////                                                              ////
2069
////  Versatile counter                                           ////
2070
////                                                              ////
2071
////  Description                                                 ////
2072
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2073
////  counter                                                     ////
2074
////                                                              ////
2075
////  To Do:                                                      ////
2076
////   - add LFSR with more taps                                  ////
2077
////                                                              ////
2078
////  Author(s):                                                  ////
2079
////      - Michael Unneback, unneback@opencores.org              ////
2080
////        ORSoC AB                                              ////
2081
////                                                              ////
2082
//////////////////////////////////////////////////////////////////////
2083
////                                                              ////
2084
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2085
////                                                              ////
2086
//// This source file may be used and distributed without         ////
2087
//// restriction provided that this copyright statement is not    ////
2088
//// removed from the file and that any derivative work contains  ////
2089
//// the original copyright notice and the associated disclaimer. ////
2090
////                                                              ////
2091
//// This source file is free software; you can redistribute it   ////
2092
//// and/or modify it under the terms of the GNU Lesser General   ////
2093
//// Public License as published by the Free Software Foundation; ////
2094
//// either version 2.1 of the License, or (at your option) any   ////
2095
//// later version.                                               ////
2096
////                                                              ////
2097
//// This source is distributed in the hope that it will be       ////
2098
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2099
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2100
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2101
//// details.                                                     ////
2102
////                                                              ////
2103
//// You should have received a copy of the GNU Lesser General    ////
2104
//// Public License along with this source; if not, download it   ////
2105
//// from http://www.opencores.org/lgpl.shtml                     ////
2106
////                                                              ////
2107
//////////////////////////////////////////////////////////////////////
2108
 
2109
// binary counter
2110 6 unneback
 
2111 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2112
module `BASE`MODULE (
2113
`undef MODULE
2114
 clear, set, cke, rew, q, rst, clk);
2115
 
2116 6 unneback
   parameter length = 4;
2117
   input clear;
2118
   input set;
2119
   input cke;
2120
   input rew;
2121
   output [length:1] q;
2122
   input rst;
2123
   input clk;
2124
 
2125
   parameter clear_value = 0;
2126
   parameter set_value = 1;
2127
   parameter wrap_value = 0;
2128
   parameter level1_value = 15;
2129
 
2130
   reg  [length:1] qi;
2131
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2132
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2133
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2134
   assign q_next = rew ? q_next_rew : q_next_fw;
2135
 
2136
   always @ (posedge clk or posedge rst)
2137
     if (rst)
2138
       qi <= {length{1'b0}};
2139
     else
2140
     if (cke)
2141
       qi <= q_next;
2142
 
2143
   assign q = qi;
2144
 
2145
endmodule
2146 40 unneback
`endif
2147
`ifdef CNT_BIN_CE_REW_L1
2148 6 unneback
//////////////////////////////////////////////////////////////////////
2149
////                                                              ////
2150
////  Versatile counter                                           ////
2151
////                                                              ////
2152
////  Description                                                 ////
2153
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2154
////  counter                                                     ////
2155
////                                                              ////
2156
////  To Do:                                                      ////
2157
////   - add LFSR with more taps                                  ////
2158
////                                                              ////
2159
////  Author(s):                                                  ////
2160
////      - Michael Unneback, unneback@opencores.org              ////
2161
////        ORSoC AB                                              ////
2162
////                                                              ////
2163
//////////////////////////////////////////////////////////////////////
2164
////                                                              ////
2165
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2166
////                                                              ////
2167
//// This source file may be used and distributed without         ////
2168
//// restriction provided that this copyright statement is not    ////
2169
//// removed from the file and that any derivative work contains  ////
2170
//// the original copyright notice and the associated disclaimer. ////
2171
////                                                              ////
2172
//// This source file is free software; you can redistribute it   ////
2173
//// and/or modify it under the terms of the GNU Lesser General   ////
2174
//// Public License as published by the Free Software Foundation; ////
2175
//// either version 2.1 of the License, or (at your option) any   ////
2176
//// later version.                                               ////
2177
////                                                              ////
2178
//// This source is distributed in the hope that it will be       ////
2179
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2180
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2181
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2182
//// details.                                                     ////
2183
////                                                              ////
2184
//// You should have received a copy of the GNU Lesser General    ////
2185
//// Public License along with this source; if not, download it   ////
2186
//// from http://www.opencores.org/lgpl.shtml                     ////
2187
////                                                              ////
2188
//////////////////////////////////////////////////////////////////////
2189
 
2190
// binary counter
2191
 
2192 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2193
module `BASE`MODULE (
2194
`undef MODULE
2195
 cke, rew, level1, rst, clk);
2196
 
2197 6 unneback
   parameter length = 4;
2198
   input cke;
2199
   input rew;
2200
   output reg level1;
2201
   input rst;
2202
   input clk;
2203
 
2204
   parameter clear_value = 0;
2205
   parameter set_value = 1;
2206
   parameter wrap_value = 1;
2207
   parameter level1_value = 15;
2208
 
2209 29 unneback
   wire clear;
2210 30 unneback
   assign clear = 1'b0;
2211 6 unneback
   reg  [length:1] qi;
2212
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2213
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2214
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2215
   assign q_next = rew ? q_next_rew : q_next_fw;
2216
 
2217
   always @ (posedge clk or posedge rst)
2218
     if (rst)
2219
       qi <= {length{1'b0}};
2220
     else
2221
     if (cke)
2222
       qi <= q_next;
2223
 
2224
 
2225
 
2226
    always @ (posedge clk or posedge rst)
2227
    if (rst)
2228
        level1 <= 1'b0;
2229
    else
2230
    if (cke)
2231 29 unneback
    if (clear)
2232
        level1 <= 1'b0;
2233
    else if (q_next == level1_value)
2234 6 unneback
        level1 <= 1'b1;
2235
    else if (qi == level1_value & rew)
2236
        level1 <= 1'b0;
2237
endmodule
2238 40 unneback
`endif
2239
`ifdef CNT_BIN_CE_REW_ZQ_L1
2240 6 unneback
//////////////////////////////////////////////////////////////////////
2241
////                                                              ////
2242
////  Versatile counter                                           ////
2243
////                                                              ////
2244
////  Description                                                 ////
2245
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2246
////  counter                                                     ////
2247
////                                                              ////
2248
////  To Do:                                                      ////
2249
////   - add LFSR with more taps                                  ////
2250
////                                                              ////
2251
////  Author(s):                                                  ////
2252
////      - Michael Unneback, unneback@opencores.org              ////
2253
////        ORSoC AB                                              ////
2254
////                                                              ////
2255
//////////////////////////////////////////////////////////////////////
2256
////                                                              ////
2257
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2258
////                                                              ////
2259
//// This source file may be used and distributed without         ////
2260
//// restriction provided that this copyright statement is not    ////
2261
//// removed from the file and that any derivative work contains  ////
2262
//// the original copyright notice and the associated disclaimer. ////
2263
////                                                              ////
2264
//// This source file is free software; you can redistribute it   ////
2265
//// and/or modify it under the terms of the GNU Lesser General   ////
2266
//// Public License as published by the Free Software Foundation; ////
2267
//// either version 2.1 of the License, or (at your option) any   ////
2268
//// later version.                                               ////
2269
////                                                              ////
2270
//// This source is distributed in the hope that it will be       ////
2271
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2272
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2273
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2274
//// details.                                                     ////
2275
////                                                              ////
2276
//// You should have received a copy of the GNU Lesser General    ////
2277
//// Public License along with this source; if not, download it   ////
2278
//// from http://www.opencores.org/lgpl.shtml                     ////
2279
////                                                              ////
2280
//////////////////////////////////////////////////////////////////////
2281
 
2282 25 unneback
// binary counter
2283
 
2284 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2285
module `BASE`MODULE (
2286
`undef MODULE
2287
 cke, rew, zq, level1, rst, clk);
2288
 
2289 25 unneback
   parameter length = 4;
2290
   input cke;
2291
   input rew;
2292
   output reg zq;
2293
   output reg level1;
2294
   input rst;
2295
   input clk;
2296
 
2297
   parameter clear_value = 0;
2298
   parameter set_value = 1;
2299
   parameter wrap_value = 1;
2300
   parameter level1_value = 15;
2301
 
2302 29 unneback
   wire clear;
2303 30 unneback
   assign clear = 1'b0;
2304 25 unneback
   reg  [length:1] qi;
2305
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2306
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2307
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2308
   assign q_next = rew ? q_next_rew : q_next_fw;
2309
 
2310
   always @ (posedge clk or posedge rst)
2311
     if (rst)
2312
       qi <= {length{1'b0}};
2313
     else
2314
     if (cke)
2315
       qi <= q_next;
2316
 
2317
 
2318
 
2319
   always @ (posedge clk or posedge rst)
2320
     if (rst)
2321
       zq <= 1'b1;
2322
     else
2323
     if (cke)
2324
       zq <= q_next == {length{1'b0}};
2325
 
2326
    always @ (posedge clk or posedge rst)
2327
    if (rst)
2328
        level1 <= 1'b0;
2329
    else
2330
    if (cke)
2331 29 unneback
    if (clear)
2332
        level1 <= 1'b0;
2333
    else if (q_next == level1_value)
2334 25 unneback
        level1 <= 1'b1;
2335
    else if (qi == level1_value & rew)
2336
        level1 <= 1'b0;
2337
endmodule
2338 40 unneback
`endif
2339
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2340 25 unneback
//////////////////////////////////////////////////////////////////////
2341
////                                                              ////
2342
////  Versatile counter                                           ////
2343
////                                                              ////
2344
////  Description                                                 ////
2345
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2346
////  counter                                                     ////
2347
////                                                              ////
2348
////  To Do:                                                      ////
2349
////   - add LFSR with more taps                                  ////
2350
////                                                              ////
2351
////  Author(s):                                                  ////
2352
////      - Michael Unneback, unneback@opencores.org              ////
2353
////        ORSoC AB                                              ////
2354
////                                                              ////
2355
//////////////////////////////////////////////////////////////////////
2356
////                                                              ////
2357
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2358
////                                                              ////
2359
//// This source file may be used and distributed without         ////
2360
//// restriction provided that this copyright statement is not    ////
2361
//// removed from the file and that any derivative work contains  ////
2362
//// the original copyright notice and the associated disclaimer. ////
2363
////                                                              ////
2364
//// This source file is free software; you can redistribute it   ////
2365
//// and/or modify it under the terms of the GNU Lesser General   ////
2366
//// Public License as published by the Free Software Foundation; ////
2367
//// either version 2.1 of the License, or (at your option) any   ////
2368
//// later version.                                               ////
2369
////                                                              ////
2370
//// This source is distributed in the hope that it will be       ////
2371
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2372
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2373
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2374
//// details.                                                     ////
2375
////                                                              ////
2376
//// You should have received a copy of the GNU Lesser General    ////
2377
//// Public License along with this source; if not, download it   ////
2378
//// from http://www.opencores.org/lgpl.shtml                     ////
2379
////                                                              ////
2380
//////////////////////////////////////////////////////////////////////
2381
 
2382
// binary counter
2383
 
2384 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2385
module `BASE`MODULE (
2386
`undef MODULE
2387
 cke, rew, q, zq, level1, rst, clk);
2388
 
2389 25 unneback
   parameter length = 4;
2390
   input cke;
2391
   input rew;
2392
   output [length:1] q;
2393
   output reg zq;
2394
   output reg level1;
2395
   input rst;
2396
   input clk;
2397
 
2398
   parameter clear_value = 0;
2399
   parameter set_value = 1;
2400
   parameter wrap_value = 1;
2401
   parameter level1_value = 15;
2402
 
2403 29 unneback
   wire clear;
2404 30 unneback
   assign clear = 1'b0;
2405 25 unneback
   reg  [length:1] qi;
2406
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2407
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2408
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2409
   assign q_next = rew ? q_next_rew : q_next_fw;
2410
 
2411
   always @ (posedge clk or posedge rst)
2412
     if (rst)
2413
       qi <= {length{1'b0}};
2414
     else
2415
     if (cke)
2416
       qi <= q_next;
2417
 
2418
   assign q = qi;
2419
 
2420
 
2421
   always @ (posedge clk or posedge rst)
2422
     if (rst)
2423
       zq <= 1'b1;
2424
     else
2425
     if (cke)
2426
       zq <= q_next == {length{1'b0}};
2427
 
2428
    always @ (posedge clk or posedge rst)
2429
    if (rst)
2430
        level1 <= 1'b0;
2431
    else
2432
    if (cke)
2433 29 unneback
    if (clear)
2434
        level1 <= 1'b0;
2435
    else if (q_next == level1_value)
2436 25 unneback
        level1 <= 1'b1;
2437
    else if (qi == level1_value & rew)
2438
        level1 <= 1'b0;
2439
endmodule
2440 40 unneback
`endif
2441
`ifdef CNT_LFSR_ZQ
2442 25 unneback
//////////////////////////////////////////////////////////////////////
2443
////                                                              ////
2444
////  Versatile counter                                           ////
2445
////                                                              ////
2446
////  Description                                                 ////
2447
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2448
////  counter                                                     ////
2449
////                                                              ////
2450
////  To Do:                                                      ////
2451
////   - add LFSR with more taps                                  ////
2452
////                                                              ////
2453
////  Author(s):                                                  ////
2454
////      - Michael Unneback, unneback@opencores.org              ////
2455
////        ORSoC AB                                              ////
2456
////                                                              ////
2457
//////////////////////////////////////////////////////////////////////
2458
////                                                              ////
2459
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2460
////                                                              ////
2461
//// This source file may be used and distributed without         ////
2462
//// restriction provided that this copyright statement is not    ////
2463
//// removed from the file and that any derivative work contains  ////
2464
//// the original copyright notice and the associated disclaimer. ////
2465
////                                                              ////
2466
//// This source file is free software; you can redistribute it   ////
2467
//// and/or modify it under the terms of the GNU Lesser General   ////
2468
//// Public License as published by the Free Software Foundation; ////
2469
//// either version 2.1 of the License, or (at your option) any   ////
2470
//// later version.                                               ////
2471
////                                                              ////
2472
//// This source is distributed in the hope that it will be       ////
2473
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2474
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2475
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2476
//// details.                                                     ////
2477
////                                                              ////
2478
//// You should have received a copy of the GNU Lesser General    ////
2479
//// Public License along with this source; if not, download it   ////
2480
//// from http://www.opencores.org/lgpl.shtml                     ////
2481
////                                                              ////
2482
//////////////////////////////////////////////////////////////////////
2483
 
2484 6 unneback
// LFSR counter
2485
 
2486 40 unneback
`define MODULE cnt_lfsr_zq
2487
module `BASE`MODULE (
2488
`undef MODULE
2489
 zq, rst, clk);
2490
 
2491 6 unneback
   parameter length = 4;
2492
   output reg zq;
2493
   input rst;
2494
   input clk;
2495
 
2496
   parameter clear_value = 0;
2497
   parameter set_value = 1;
2498
   parameter wrap_value = 8;
2499
   parameter level1_value = 15;
2500
 
2501
   reg  [length:1] qi;
2502
   reg lfsr_fb;
2503
   wire [length:1] q_next;
2504
   reg [32:1] polynom;
2505
   integer i;
2506
 
2507
   always @ (qi)
2508
   begin
2509
        case (length)
2510
         2: polynom = 32'b11;                               // 0x3
2511
         3: polynom = 32'b110;                              // 0x6
2512
         4: polynom = 32'b1100;                             // 0xC
2513
         5: polynom = 32'b10100;                            // 0x14
2514
         6: polynom = 32'b110000;                           // 0x30
2515
         7: polynom = 32'b1100000;                          // 0x60
2516
         8: polynom = 32'b10111000;                         // 0xb8
2517
         9: polynom = 32'b100010000;                        // 0x110
2518
        10: polynom = 32'b1001000000;                       // 0x240
2519
        11: polynom = 32'b10100000000;                      // 0x500
2520
        12: polynom = 32'b100000101001;                     // 0x829
2521
        13: polynom = 32'b1000000001100;                    // 0x100C
2522
        14: polynom = 32'b10000000010101;                   // 0x2015
2523
        15: polynom = 32'b110000000000000;                  // 0x6000
2524
        16: polynom = 32'b1101000000001000;                 // 0xD008
2525
        17: polynom = 32'b10010000000000000;                // 0x12000
2526
        18: polynom = 32'b100000010000000000;               // 0x20400
2527
        19: polynom = 32'b1000000000000100011;              // 0x40023
2528 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2529 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2530
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2531
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2532
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2533
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2534
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2535
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2536
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2537
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2538
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2539
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2540
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2541
        default: polynom = 32'b0;
2542
        endcase
2543
        lfsr_fb = qi[length];
2544
        for (i=length-1; i>=1; i=i-1) begin
2545
            if (polynom[i])
2546
                lfsr_fb = lfsr_fb  ~^ qi[i];
2547
        end
2548
    end
2549
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2550
 
2551
   always @ (posedge clk or posedge rst)
2552
     if (rst)
2553
       qi <= {length{1'b0}};
2554
     else
2555
       qi <= q_next;
2556
 
2557
 
2558
 
2559
   always @ (posedge clk or posedge rst)
2560
     if (rst)
2561
       zq <= 1'b1;
2562
     else
2563
       zq <= q_next == {length{1'b0}};
2564
endmodule
2565 40 unneback
`endif
2566 75 unneback
`ifdef CNT_LFSR_CE
2567
//////////////////////////////////////////////////////////////////////
2568
////                                                              ////
2569
////  Versatile counter                                           ////
2570
////                                                              ////
2571
////  Description                                                 ////
2572
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2573
////  counter                                                     ////
2574
////                                                              ////
2575
////  To Do:                                                      ////
2576
////   - add LFSR with more taps                                  ////
2577
////                                                              ////
2578
////  Author(s):                                                  ////
2579
////      - Michael Unneback, unneback@opencores.org              ////
2580
////        ORSoC AB                                              ////
2581
////                                                              ////
2582
//////////////////////////////////////////////////////////////////////
2583
////                                                              ////
2584
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2585
////                                                              ////
2586
//// This source file may be used and distributed without         ////
2587
//// restriction provided that this copyright statement is not    ////
2588
//// removed from the file and that any derivative work contains  ////
2589
//// the original copyright notice and the associated disclaimer. ////
2590
////                                                              ////
2591
//// This source file is free software; you can redistribute it   ////
2592
//// and/or modify it under the terms of the GNU Lesser General   ////
2593
//// Public License as published by the Free Software Foundation; ////
2594
//// either version 2.1 of the License, or (at your option) any   ////
2595
//// later version.                                               ////
2596
////                                                              ////
2597
//// This source is distributed in the hope that it will be       ////
2598
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2599
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2600
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2601
//// details.                                                     ////
2602
////                                                              ////
2603
//// You should have received a copy of the GNU Lesser General    ////
2604
//// Public License along with this source; if not, download it   ////
2605
//// from http://www.opencores.org/lgpl.shtml                     ////
2606
////                                                              ////
2607
//////////////////////////////////////////////////////////////////////
2608
 
2609
// LFSR counter
2610
 
2611
`define MODULE cnt_lfsr_ce
2612
module `BASE`MODULE (
2613
`undef MODULE
2614
 cke, zq, rst, clk);
2615
 
2616
   parameter length = 4;
2617
   input cke;
2618
   output reg zq;
2619
   input rst;
2620
   input clk;
2621
 
2622
   parameter clear_value = 0;
2623
   parameter set_value = 1;
2624
   parameter wrap_value = 0;
2625
   parameter level1_value = 15;
2626
 
2627
   reg  [length:1] qi;
2628
   reg lfsr_fb;
2629
   wire [length:1] q_next;
2630
   reg [32:1] polynom;
2631
   integer i;
2632
 
2633
   always @ (qi)
2634
   begin
2635
        case (length)
2636
         2: polynom = 32'b11;                               // 0x3
2637
         3: polynom = 32'b110;                              // 0x6
2638
         4: polynom = 32'b1100;                             // 0xC
2639
         5: polynom = 32'b10100;                            // 0x14
2640
         6: polynom = 32'b110000;                           // 0x30
2641
         7: polynom = 32'b1100000;                          // 0x60
2642
         8: polynom = 32'b10111000;                         // 0xb8
2643
         9: polynom = 32'b100010000;                        // 0x110
2644
        10: polynom = 32'b1001000000;                       // 0x240
2645
        11: polynom = 32'b10100000000;                      // 0x500
2646
        12: polynom = 32'b100000101001;                     // 0x829
2647
        13: polynom = 32'b1000000001100;                    // 0x100C
2648
        14: polynom = 32'b10000000010101;                   // 0x2015
2649
        15: polynom = 32'b110000000000000;                  // 0x6000
2650
        16: polynom = 32'b1101000000001000;                 // 0xD008
2651
        17: polynom = 32'b10010000000000000;                // 0x12000
2652
        18: polynom = 32'b100000010000000000;               // 0x20400
2653
        19: polynom = 32'b1000000000000100011;              // 0x40023
2654
        20: polynom = 32'b10010000000000000000;             // 0x90000
2655
        21: polynom = 32'b101000000000000000000;            // 0x140000
2656
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2657
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2658
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2659
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2660
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2661
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2662
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2663
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2664
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2665
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2666
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2667
        default: polynom = 32'b0;
2668
        endcase
2669
        lfsr_fb = qi[length];
2670
        for (i=length-1; i>=1; i=i-1) begin
2671
            if (polynom[i])
2672
                lfsr_fb = lfsr_fb  ~^ qi[i];
2673
        end
2674
    end
2675
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2676
 
2677
   always @ (posedge clk or posedge rst)
2678
     if (rst)
2679
       qi <= {length{1'b0}};
2680
     else
2681
     if (cke)
2682
       qi <= q_next;
2683
 
2684
 
2685
 
2686
   always @ (posedge clk or posedge rst)
2687
     if (rst)
2688
       zq <= 1'b1;
2689
     else
2690
     if (cke)
2691
       zq <= q_next == {length{1'b0}};
2692
endmodule
2693
`endif
2694 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2695 6 unneback
//////////////////////////////////////////////////////////////////////
2696
////                                                              ////
2697
////  Versatile counter                                           ////
2698
////                                                              ////
2699
////  Description                                                 ////
2700
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2701
////  counter                                                     ////
2702
////                                                              ////
2703
////  To Do:                                                      ////
2704
////   - add LFSR with more taps                                  ////
2705
////                                                              ////
2706
////  Author(s):                                                  ////
2707
////      - Michael Unneback, unneback@opencores.org              ////
2708
////        ORSoC AB                                              ////
2709
////                                                              ////
2710
//////////////////////////////////////////////////////////////////////
2711
////                                                              ////
2712
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2713
////                                                              ////
2714
//// This source file may be used and distributed without         ////
2715
//// restriction provided that this copyright statement is not    ////
2716
//// removed from the file and that any derivative work contains  ////
2717
//// the original copyright notice and the associated disclaimer. ////
2718
////                                                              ////
2719
//// This source file is free software; you can redistribute it   ////
2720
//// and/or modify it under the terms of the GNU Lesser General   ////
2721
//// Public License as published by the Free Software Foundation; ////
2722
//// either version 2.1 of the License, or (at your option) any   ////
2723
//// later version.                                               ////
2724
////                                                              ////
2725
//// This source is distributed in the hope that it will be       ////
2726
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2727
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2728
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2729
//// details.                                                     ////
2730
////                                                              ////
2731
//// You should have received a copy of the GNU Lesser General    ////
2732
//// Public License along with this source; if not, download it   ////
2733
//// from http://www.opencores.org/lgpl.shtml                     ////
2734
////                                                              ////
2735
//////////////////////////////////////////////////////////////////////
2736
 
2737
// LFSR counter
2738
 
2739 40 unneback
`define MODULE cnt_lfsr_ce_zq
2740
module `BASE`MODULE (
2741
`undef MODULE
2742
 cke, zq, rst, clk);
2743
 
2744 6 unneback
   parameter length = 4;
2745
   input cke;
2746
   output reg zq;
2747
   input rst;
2748
   input clk;
2749
 
2750
   parameter clear_value = 0;
2751
   parameter set_value = 1;
2752
   parameter wrap_value = 8;
2753
   parameter level1_value = 15;
2754
 
2755
   reg  [length:1] qi;
2756
   reg lfsr_fb;
2757
   wire [length:1] q_next;
2758
   reg [32:1] polynom;
2759
   integer i;
2760
 
2761
   always @ (qi)
2762
   begin
2763
        case (length)
2764
         2: polynom = 32'b11;                               // 0x3
2765
         3: polynom = 32'b110;                              // 0x6
2766
         4: polynom = 32'b1100;                             // 0xC
2767
         5: polynom = 32'b10100;                            // 0x14
2768
         6: polynom = 32'b110000;                           // 0x30
2769
         7: polynom = 32'b1100000;                          // 0x60
2770
         8: polynom = 32'b10111000;                         // 0xb8
2771
         9: polynom = 32'b100010000;                        // 0x110
2772
        10: polynom = 32'b1001000000;                       // 0x240
2773
        11: polynom = 32'b10100000000;                      // 0x500
2774
        12: polynom = 32'b100000101001;                     // 0x829
2775
        13: polynom = 32'b1000000001100;                    // 0x100C
2776
        14: polynom = 32'b10000000010101;                   // 0x2015
2777
        15: polynom = 32'b110000000000000;                  // 0x6000
2778
        16: polynom = 32'b1101000000001000;                 // 0xD008
2779
        17: polynom = 32'b10010000000000000;                // 0x12000
2780
        18: polynom = 32'b100000010000000000;               // 0x20400
2781
        19: polynom = 32'b1000000000000100011;              // 0x40023
2782 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2783 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2784
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2785
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2786
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2787
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2788
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2789
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2790
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2791
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2792
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2793
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2794
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2795
        default: polynom = 32'b0;
2796
        endcase
2797
        lfsr_fb = qi[length];
2798
        for (i=length-1; i>=1; i=i-1) begin
2799
            if (polynom[i])
2800
                lfsr_fb = lfsr_fb  ~^ qi[i];
2801
        end
2802
    end
2803
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2804
 
2805
   always @ (posedge clk or posedge rst)
2806
     if (rst)
2807
       qi <= {length{1'b0}};
2808
     else
2809
     if (cke)
2810
       qi <= q_next;
2811
 
2812
 
2813
 
2814
   always @ (posedge clk or posedge rst)
2815
     if (rst)
2816
       zq <= 1'b1;
2817
     else
2818
     if (cke)
2819
       zq <= q_next == {length{1'b0}};
2820
endmodule
2821 40 unneback
`endif
2822
`ifdef CNT_LFSR_CE_Q
2823 6 unneback
//////////////////////////////////////////////////////////////////////
2824
////                                                              ////
2825
////  Versatile counter                                           ////
2826
////                                                              ////
2827
////  Description                                                 ////
2828
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2829
////  counter                                                     ////
2830
////                                                              ////
2831
////  To Do:                                                      ////
2832
////   - add LFSR with more taps                                  ////
2833
////                                                              ////
2834
////  Author(s):                                                  ////
2835
////      - Michael Unneback, unneback@opencores.org              ////
2836
////        ORSoC AB                                              ////
2837
////                                                              ////
2838
//////////////////////////////////////////////////////////////////////
2839
////                                                              ////
2840
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2841
////                                                              ////
2842
//// This source file may be used and distributed without         ////
2843
//// restriction provided that this copyright statement is not    ////
2844
//// removed from the file and that any derivative work contains  ////
2845
//// the original copyright notice and the associated disclaimer. ////
2846
////                                                              ////
2847
//// This source file is free software; you can redistribute it   ////
2848
//// and/or modify it under the terms of the GNU Lesser General   ////
2849
//// Public License as published by the Free Software Foundation; ////
2850
//// either version 2.1 of the License, or (at your option) any   ////
2851
//// later version.                                               ////
2852
////                                                              ////
2853
//// This source is distributed in the hope that it will be       ////
2854
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2855
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2856
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2857
//// details.                                                     ////
2858
////                                                              ////
2859
//// You should have received a copy of the GNU Lesser General    ////
2860
//// Public License along with this source; if not, download it   ////
2861
//// from http://www.opencores.org/lgpl.shtml                     ////
2862
////                                                              ////
2863
//////////////////////////////////////////////////////////////////////
2864 22 unneback
 
2865
// LFSR counter
2866 27 unneback
 
2867 40 unneback
`define MODULE cnt_lfsr_ce_q
2868
module `BASE`MODULE (
2869
`undef MODULE
2870
 cke, q, rst, clk);
2871
 
2872 27 unneback
   parameter length = 4;
2873
   input cke;
2874
   output [length:1] q;
2875
   input rst;
2876
   input clk;
2877
 
2878
   parameter clear_value = 0;
2879
   parameter set_value = 1;
2880
   parameter wrap_value = 8;
2881
   parameter level1_value = 15;
2882
 
2883
   reg  [length:1] qi;
2884
   reg lfsr_fb;
2885
   wire [length:1] q_next;
2886
   reg [32:1] polynom;
2887
   integer i;
2888
 
2889
   always @ (qi)
2890
   begin
2891
        case (length)
2892
         2: polynom = 32'b11;                               // 0x3
2893
         3: polynom = 32'b110;                              // 0x6
2894
         4: polynom = 32'b1100;                             // 0xC
2895
         5: polynom = 32'b10100;                            // 0x14
2896
         6: polynom = 32'b110000;                           // 0x30
2897
         7: polynom = 32'b1100000;                          // 0x60
2898
         8: polynom = 32'b10111000;                         // 0xb8
2899
         9: polynom = 32'b100010000;                        // 0x110
2900
        10: polynom = 32'b1001000000;                       // 0x240
2901
        11: polynom = 32'b10100000000;                      // 0x500
2902
        12: polynom = 32'b100000101001;                     // 0x829
2903
        13: polynom = 32'b1000000001100;                    // 0x100C
2904
        14: polynom = 32'b10000000010101;                   // 0x2015
2905
        15: polynom = 32'b110000000000000;                  // 0x6000
2906
        16: polynom = 32'b1101000000001000;                 // 0xD008
2907
        17: polynom = 32'b10010000000000000;                // 0x12000
2908
        18: polynom = 32'b100000010000000000;               // 0x20400
2909
        19: polynom = 32'b1000000000000100011;              // 0x40023
2910 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2911 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2912
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2913
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2914
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2915
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2916
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2917
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2918
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2919
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2920
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2921
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2922
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2923
        default: polynom = 32'b0;
2924
        endcase
2925
        lfsr_fb = qi[length];
2926
        for (i=length-1; i>=1; i=i-1) begin
2927
            if (polynom[i])
2928
                lfsr_fb = lfsr_fb  ~^ qi[i];
2929
        end
2930
    end
2931
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2932
 
2933
   always @ (posedge clk or posedge rst)
2934
     if (rst)
2935
       qi <= {length{1'b0}};
2936
     else
2937
     if (cke)
2938
       qi <= q_next;
2939
 
2940
   assign q = qi;
2941
 
2942
endmodule
2943 40 unneback
`endif
2944
`ifdef CNT_LFSR_CE_CLEAR_Q
2945 27 unneback
//////////////////////////////////////////////////////////////////////
2946
////                                                              ////
2947
////  Versatile counter                                           ////
2948
////                                                              ////
2949
////  Description                                                 ////
2950
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2951
////  counter                                                     ////
2952
////                                                              ////
2953
////  To Do:                                                      ////
2954
////   - add LFSR with more taps                                  ////
2955
////                                                              ////
2956
////  Author(s):                                                  ////
2957
////      - Michael Unneback, unneback@opencores.org              ////
2958
////        ORSoC AB                                              ////
2959
////                                                              ////
2960
//////////////////////////////////////////////////////////////////////
2961
////                                                              ////
2962
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2963
////                                                              ////
2964
//// This source file may be used and distributed without         ////
2965
//// restriction provided that this copyright statement is not    ////
2966
//// removed from the file and that any derivative work contains  ////
2967
//// the original copyright notice and the associated disclaimer. ////
2968
////                                                              ////
2969
//// This source file is free software; you can redistribute it   ////
2970
//// and/or modify it under the terms of the GNU Lesser General   ////
2971
//// Public License as published by the Free Software Foundation; ////
2972
//// either version 2.1 of the License, or (at your option) any   ////
2973
//// later version.                                               ////
2974
////                                                              ////
2975
//// This source is distributed in the hope that it will be       ////
2976
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2977
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2978
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2979
//// details.                                                     ////
2980
////                                                              ////
2981
//// You should have received a copy of the GNU Lesser General    ////
2982
//// Public License along with this source; if not, download it   ////
2983
//// from http://www.opencores.org/lgpl.shtml                     ////
2984
////                                                              ////
2985
//////////////////////////////////////////////////////////////////////
2986
 
2987
// LFSR counter
2988
 
2989 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2990
module `BASE`MODULE (
2991
`undef MODULE
2992
 clear, cke, q, rst, clk);
2993
 
2994 27 unneback
   parameter length = 4;
2995
   input clear;
2996
   input cke;
2997
   output [length:1] q;
2998
   input rst;
2999
   input clk;
3000
 
3001
   parameter clear_value = 0;
3002
   parameter set_value = 1;
3003
   parameter wrap_value = 8;
3004
   parameter level1_value = 15;
3005
 
3006
   reg  [length:1] qi;
3007
   reg lfsr_fb;
3008
   wire [length:1] q_next;
3009
   reg [32:1] polynom;
3010
   integer i;
3011
 
3012
   always @ (qi)
3013
   begin
3014
        case (length)
3015
         2: polynom = 32'b11;                               // 0x3
3016
         3: polynom = 32'b110;                              // 0x6
3017
         4: polynom = 32'b1100;                             // 0xC
3018
         5: polynom = 32'b10100;                            // 0x14
3019
         6: polynom = 32'b110000;                           // 0x30
3020
         7: polynom = 32'b1100000;                          // 0x60
3021
         8: polynom = 32'b10111000;                         // 0xb8
3022
         9: polynom = 32'b100010000;                        // 0x110
3023
        10: polynom = 32'b1001000000;                       // 0x240
3024
        11: polynom = 32'b10100000000;                      // 0x500
3025
        12: polynom = 32'b100000101001;                     // 0x829
3026
        13: polynom = 32'b1000000001100;                    // 0x100C
3027
        14: polynom = 32'b10000000010101;                   // 0x2015
3028
        15: polynom = 32'b110000000000000;                  // 0x6000
3029
        16: polynom = 32'b1101000000001000;                 // 0xD008
3030
        17: polynom = 32'b10010000000000000;                // 0x12000
3031
        18: polynom = 32'b100000010000000000;               // 0x20400
3032
        19: polynom = 32'b1000000000000100011;              // 0x40023
3033 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3034 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3035
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3036
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3037
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3038
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3039
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3040
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3041
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3042
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3043
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3044
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3045
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3046
        default: polynom = 32'b0;
3047
        endcase
3048
        lfsr_fb = qi[length];
3049
        for (i=length-1; i>=1; i=i-1) begin
3050
            if (polynom[i])
3051
                lfsr_fb = lfsr_fb  ~^ qi[i];
3052
        end
3053
    end
3054
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3055
 
3056
   always @ (posedge clk or posedge rst)
3057
     if (rst)
3058
       qi <= {length{1'b0}};
3059
     else
3060
     if (cke)
3061
       qi <= q_next;
3062
 
3063
   assign q = qi;
3064
 
3065
endmodule
3066 40 unneback
`endif
3067
`ifdef CNT_LFSR_CE_Q_ZQ
3068 27 unneback
//////////////////////////////////////////////////////////////////////
3069
////                                                              ////
3070
////  Versatile counter                                           ////
3071
////                                                              ////
3072
////  Description                                                 ////
3073
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3074
////  counter                                                     ////
3075
////                                                              ////
3076
////  To Do:                                                      ////
3077
////   - add LFSR with more taps                                  ////
3078
////                                                              ////
3079
////  Author(s):                                                  ////
3080
////      - Michael Unneback, unneback@opencores.org              ////
3081
////        ORSoC AB                                              ////
3082
////                                                              ////
3083
//////////////////////////////////////////////////////////////////////
3084
////                                                              ////
3085
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3086
////                                                              ////
3087
//// This source file may be used and distributed without         ////
3088
//// restriction provided that this copyright statement is not    ////
3089
//// removed from the file and that any derivative work contains  ////
3090
//// the original copyright notice and the associated disclaimer. ////
3091
////                                                              ////
3092
//// This source file is free software; you can redistribute it   ////
3093
//// and/or modify it under the terms of the GNU Lesser General   ////
3094
//// Public License as published by the Free Software Foundation; ////
3095
//// either version 2.1 of the License, or (at your option) any   ////
3096
//// later version.                                               ////
3097
////                                                              ////
3098
//// This source is distributed in the hope that it will be       ////
3099
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3100
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3101
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3102
//// details.                                                     ////
3103
////                                                              ////
3104
//// You should have received a copy of the GNU Lesser General    ////
3105
//// Public License along with this source; if not, download it   ////
3106
//// from http://www.opencores.org/lgpl.shtml                     ////
3107
////                                                              ////
3108
//////////////////////////////////////////////////////////////////////
3109
 
3110
// LFSR counter
3111 22 unneback
 
3112 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
3113
module `BASE`MODULE (
3114
`undef MODULE
3115
 cke, q, zq, rst, clk);
3116
 
3117 22 unneback
   parameter length = 4;
3118
   input cke;
3119
   output [length:1] q;
3120
   output reg zq;
3121
   input rst;
3122
   input clk;
3123
 
3124
   parameter clear_value = 0;
3125
   parameter set_value = 1;
3126
   parameter wrap_value = 8;
3127
   parameter level1_value = 15;
3128
 
3129
   reg  [length:1] qi;
3130
   reg lfsr_fb;
3131
   wire [length:1] q_next;
3132
   reg [32:1] polynom;
3133
   integer i;
3134
 
3135
   always @ (qi)
3136
   begin
3137
        case (length)
3138
         2: polynom = 32'b11;                               // 0x3
3139
         3: polynom = 32'b110;                              // 0x6
3140
         4: polynom = 32'b1100;                             // 0xC
3141
         5: polynom = 32'b10100;                            // 0x14
3142
         6: polynom = 32'b110000;                           // 0x30
3143
         7: polynom = 32'b1100000;                          // 0x60
3144
         8: polynom = 32'b10111000;                         // 0xb8
3145
         9: polynom = 32'b100010000;                        // 0x110
3146
        10: polynom = 32'b1001000000;                       // 0x240
3147
        11: polynom = 32'b10100000000;                      // 0x500
3148
        12: polynom = 32'b100000101001;                     // 0x829
3149
        13: polynom = 32'b1000000001100;                    // 0x100C
3150
        14: polynom = 32'b10000000010101;                   // 0x2015
3151
        15: polynom = 32'b110000000000000;                  // 0x6000
3152
        16: polynom = 32'b1101000000001000;                 // 0xD008
3153
        17: polynom = 32'b10010000000000000;                // 0x12000
3154
        18: polynom = 32'b100000010000000000;               // 0x20400
3155
        19: polynom = 32'b1000000000000100011;              // 0x40023
3156 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3157 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3158
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3159
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3160
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3161
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3162
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3163
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3164
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3165
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3166
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3167
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3168
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3169
        default: polynom = 32'b0;
3170
        endcase
3171
        lfsr_fb = qi[length];
3172
        for (i=length-1; i>=1; i=i-1) begin
3173
            if (polynom[i])
3174
                lfsr_fb = lfsr_fb  ~^ qi[i];
3175
        end
3176
    end
3177
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3178
 
3179
   always @ (posedge clk or posedge rst)
3180
     if (rst)
3181
       qi <= {length{1'b0}};
3182
     else
3183
     if (cke)
3184
       qi <= q_next;
3185
 
3186
   assign q = qi;
3187
 
3188
 
3189
   always @ (posedge clk or posedge rst)
3190
     if (rst)
3191
       zq <= 1'b1;
3192
     else
3193
     if (cke)
3194
       zq <= q_next == {length{1'b0}};
3195
endmodule
3196 40 unneback
`endif
3197
`ifdef CNT_LFSR_CE_REW_L1
3198 22 unneback
//////////////////////////////////////////////////////////////////////
3199
////                                                              ////
3200
////  Versatile counter                                           ////
3201
////                                                              ////
3202
////  Description                                                 ////
3203
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3204
////  counter                                                     ////
3205
////                                                              ////
3206
////  To Do:                                                      ////
3207
////   - add LFSR with more taps                                  ////
3208
////                                                              ////
3209
////  Author(s):                                                  ////
3210
////      - Michael Unneback, unneback@opencores.org              ////
3211
////        ORSoC AB                                              ////
3212
////                                                              ////
3213
//////////////////////////////////////////////////////////////////////
3214
////                                                              ////
3215
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3216
////                                                              ////
3217
//// This source file may be used and distributed without         ////
3218
//// restriction provided that this copyright statement is not    ////
3219
//// removed from the file and that any derivative work contains  ////
3220
//// the original copyright notice and the associated disclaimer. ////
3221
////                                                              ////
3222
//// This source file is free software; you can redistribute it   ////
3223
//// and/or modify it under the terms of the GNU Lesser General   ////
3224
//// Public License as published by the Free Software Foundation; ////
3225
//// either version 2.1 of the License, or (at your option) any   ////
3226
//// later version.                                               ////
3227
////                                                              ////
3228
//// This source is distributed in the hope that it will be       ////
3229
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3230
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3231
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3232
//// details.                                                     ////
3233
////                                                              ////
3234
//// You should have received a copy of the GNU Lesser General    ////
3235
//// Public License along with this source; if not, download it   ////
3236
//// from http://www.opencores.org/lgpl.shtml                     ////
3237
////                                                              ////
3238
//////////////////////////////////////////////////////////////////////
3239 6 unneback
 
3240
// LFSR counter
3241
 
3242 40 unneback
`define MODULE cnt_lfsr_ce_rew_l1
3243
module `BASE`MODULE (
3244
`undef MODULE
3245
 cke, rew, level1, rst, clk);
3246
 
3247 6 unneback
   parameter length = 4;
3248
   input cke;
3249
   input rew;
3250
   output reg level1;
3251
   input rst;
3252
   input clk;
3253
 
3254
   parameter clear_value = 0;
3255
   parameter set_value = 1;
3256
   parameter wrap_value = 8;
3257
   parameter level1_value = 15;
3258
 
3259 29 unneback
   wire clear;
3260 30 unneback
   assign clear = 1'b0;
3261 6 unneback
   reg  [length:1] qi;
3262
   reg lfsr_fb, lfsr_fb_rew;
3263
   wire  [length:1] q_next, q_next_fw, q_next_rew;
3264
   reg [32:1] polynom_rew;
3265
   integer j;
3266
   reg [32:1] polynom;
3267
   integer i;
3268
 
3269
   always @ (qi)
3270
   begin
3271
        case (length)
3272
         2: polynom = 32'b11;                               // 0x3
3273
         3: polynom = 32'b110;                              // 0x6
3274
         4: polynom = 32'b1100;                             // 0xC
3275
         5: polynom = 32'b10100;                            // 0x14
3276
         6: polynom = 32'b110000;                           // 0x30
3277
         7: polynom = 32'b1100000;                          // 0x60
3278
         8: polynom = 32'b10111000;                         // 0xb8
3279
         9: polynom = 32'b100010000;                        // 0x110
3280
        10: polynom = 32'b1001000000;                       // 0x240
3281
        11: polynom = 32'b10100000000;                      // 0x500
3282
        12: polynom = 32'b100000101001;                     // 0x829
3283
        13: polynom = 32'b1000000001100;                    // 0x100C
3284
        14: polynom = 32'b10000000010101;                   // 0x2015
3285
        15: polynom = 32'b110000000000000;                  // 0x6000
3286
        16: polynom = 32'b1101000000001000;                 // 0xD008
3287
        17: polynom = 32'b10010000000000000;                // 0x12000
3288
        18: polynom = 32'b100000010000000000;               // 0x20400
3289
        19: polynom = 32'b1000000000000100011;              // 0x40023
3290 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3291 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3292
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3293
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3294
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3295
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3296
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3297
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3298
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3299
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3300
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3301
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3302
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3303
        default: polynom = 32'b0;
3304
        endcase
3305
        lfsr_fb = qi[length];
3306
        for (i=length-1; i>=1; i=i-1) begin
3307
            if (polynom[i])
3308
                lfsr_fb = lfsr_fb  ~^ qi[i];
3309
        end
3310
    end
3311
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3312
   always @ (qi)
3313
   begin
3314
        case (length)
3315
         2: polynom_rew = 32'b11;
3316
         3: polynom_rew = 32'b110;
3317
         4: polynom_rew = 32'b1100;
3318
         5: polynom_rew = 32'b10100;
3319
         6: polynom_rew = 32'b110000;
3320
         7: polynom_rew = 32'b1100000;
3321
         8: polynom_rew = 32'b10111000;
3322
         9: polynom_rew = 32'b100010000;
3323
        10: polynom_rew = 32'b1001000000;
3324
        11: polynom_rew = 32'b10100000000;
3325
        12: polynom_rew = 32'b100000101001;
3326
        13: polynom_rew = 32'b1000000001100;
3327
        14: polynom_rew = 32'b10000000010101;
3328
        15: polynom_rew = 32'b110000000000000;
3329
        16: polynom_rew = 32'b1101000000001000;
3330
        17: polynom_rew = 32'b10010000000000000;
3331
        18: polynom_rew = 32'b100000010000000000;
3332
        19: polynom_rew = 32'b1000000000000100011;
3333
        20: polynom_rew = 32'b10000010000000000000;
3334
        21: polynom_rew = 32'b101000000000000000000;
3335
        22: polynom_rew = 32'b1100000000000000000000;
3336
        23: polynom_rew = 32'b10000100000000000000000;
3337
        24: polynom_rew = 32'b111000010000000000000000;
3338
        25: polynom_rew = 32'b1001000000000000000000000;
3339
        26: polynom_rew = 32'b10000000000000000000100011;
3340
        27: polynom_rew = 32'b100000000000000000000010011;
3341
        28: polynom_rew = 32'b1100100000000000000000000000;
3342
        29: polynom_rew = 32'b10100000000000000000000000000;
3343
        30: polynom_rew = 32'b100000000000000000000000101001;
3344
        31: polynom_rew = 32'b1001000000000000000000000000000;
3345
        32: polynom_rew = 32'b10000000001000000000000000000011;
3346
        default: polynom_rew = 32'b0;
3347
        endcase
3348
        // rotate left
3349
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3350
        lfsr_fb_rew = qi[length];
3351
        for (i=length-1; i>=1; i=i-1) begin
3352
            if (polynom_rew[i])
3353
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3354
        end
3355
    end
3356
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3357
   assign q_next = rew ? q_next_rew : q_next_fw;
3358
 
3359
   always @ (posedge clk or posedge rst)
3360
     if (rst)
3361
       qi <= {length{1'b0}};
3362
     else
3363
     if (cke)
3364
       qi <= q_next;
3365
 
3366
 
3367
 
3368
    always @ (posedge clk or posedge rst)
3369
    if (rst)
3370
        level1 <= 1'b0;
3371
    else
3372
    if (cke)
3373 29 unneback
    if (clear)
3374
        level1 <= 1'b0;
3375
    else if (q_next == level1_value)
3376 6 unneback
        level1 <= 1'b1;
3377
    else if (qi == level1_value & rew)
3378
        level1 <= 1'b0;
3379
endmodule
3380 40 unneback
`endif
3381
`ifdef CNT_GRAY
3382 6 unneback
//////////////////////////////////////////////////////////////////////
3383
////                                                              ////
3384
////  Versatile counter                                           ////
3385
////                                                              ////
3386
////  Description                                                 ////
3387
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3388
////  counter                                                     ////
3389
////                                                              ////
3390
////  To Do:                                                      ////
3391
////   - add LFSR with more taps                                  ////
3392
////                                                              ////
3393
////  Author(s):                                                  ////
3394
////      - Michael Unneback, unneback@opencores.org              ////
3395
////        ORSoC AB                                              ////
3396
////                                                              ////
3397
//////////////////////////////////////////////////////////////////////
3398
////                                                              ////
3399
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3400
////                                                              ////
3401
//// This source file may be used and distributed without         ////
3402
//// restriction provided that this copyright statement is not    ////
3403
//// removed from the file and that any derivative work contains  ////
3404
//// the original copyright notice and the associated disclaimer. ////
3405
////                                                              ////
3406
//// This source file is free software; you can redistribute it   ////
3407
//// and/or modify it under the terms of the GNU Lesser General   ////
3408
//// Public License as published by the Free Software Foundation; ////
3409
//// either version 2.1 of the License, or (at your option) any   ////
3410
//// later version.                                               ////
3411
////                                                              ////
3412
//// This source is distributed in the hope that it will be       ////
3413
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3414
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3415
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3416
//// details.                                                     ////
3417
////                                                              ////
3418
//// You should have received a copy of the GNU Lesser General    ////
3419
//// Public License along with this source; if not, download it   ////
3420
//// from http://www.opencores.org/lgpl.shtml                     ////
3421
////                                                              ////
3422
//////////////////////////////////////////////////////////////////////
3423
 
3424
// GRAY counter
3425
 
3426 40 unneback
`define MODULE cnt_gray
3427
module `BASE`MODULE (
3428
`undef MODULE
3429
 q, rst, clk);
3430
 
3431 6 unneback
   parameter length = 4;
3432
   output reg [length:1] q;
3433
   input rst;
3434
   input clk;
3435
 
3436
   parameter clear_value = 0;
3437
   parameter set_value = 1;
3438
   parameter wrap_value = 8;
3439
   parameter level1_value = 15;
3440
 
3441
   reg  [length:1] qi;
3442
   wire [length:1] q_next;
3443
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3444
 
3445
   always @ (posedge clk or posedge rst)
3446
     if (rst)
3447
       qi <= {length{1'b0}};
3448
     else
3449
       qi <= q_next;
3450
 
3451
   always @ (posedge clk or posedge rst)
3452
     if (rst)
3453
       q <= {length{1'b0}};
3454
     else
3455
         q <= (q_next>>1) ^ q_next;
3456
 
3457
endmodule
3458 40 unneback
`endif
3459
`ifdef CNT_GRAY_CE
3460 6 unneback
//////////////////////////////////////////////////////////////////////
3461
////                                                              ////
3462
////  Versatile counter                                           ////
3463
////                                                              ////
3464
////  Description                                                 ////
3465
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3466
////  counter                                                     ////
3467
////                                                              ////
3468
////  To Do:                                                      ////
3469
////   - add LFSR with more taps                                  ////
3470
////                                                              ////
3471
////  Author(s):                                                  ////
3472
////      - Michael Unneback, unneback@opencores.org              ////
3473
////        ORSoC AB                                              ////
3474
////                                                              ////
3475
//////////////////////////////////////////////////////////////////////
3476
////                                                              ////
3477
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3478
////                                                              ////
3479
//// This source file may be used and distributed without         ////
3480
//// restriction provided that this copyright statement is not    ////
3481
//// removed from the file and that any derivative work contains  ////
3482
//// the original copyright notice and the associated disclaimer. ////
3483
////                                                              ////
3484
//// This source file is free software; you can redistribute it   ////
3485
//// and/or modify it under the terms of the GNU Lesser General   ////
3486
//// Public License as published by the Free Software Foundation; ////
3487
//// either version 2.1 of the License, or (at your option) any   ////
3488
//// later version.                                               ////
3489
////                                                              ////
3490
//// This source is distributed in the hope that it will be       ////
3491
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3492
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3493
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3494
//// details.                                                     ////
3495
////                                                              ////
3496
//// You should have received a copy of the GNU Lesser General    ////
3497
//// Public License along with this source; if not, download it   ////
3498
//// from http://www.opencores.org/lgpl.shtml                     ////
3499
////                                                              ////
3500
//////////////////////////////////////////////////////////////////////
3501
 
3502
// GRAY counter
3503
 
3504 40 unneback
`define MODULE cnt_gray_ce
3505
module `BASE`MODULE (
3506
`undef MODULE
3507
 cke, q, rst, clk);
3508
 
3509 6 unneback
   parameter length = 4;
3510
   input cke;
3511
   output reg [length:1] q;
3512
   input rst;
3513
   input clk;
3514
 
3515
   parameter clear_value = 0;
3516
   parameter set_value = 1;
3517
   parameter wrap_value = 8;
3518
   parameter level1_value = 15;
3519
 
3520
   reg  [length:1] qi;
3521
   wire [length:1] q_next;
3522
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3523
 
3524
   always @ (posedge clk or posedge rst)
3525
     if (rst)
3526
       qi <= {length{1'b0}};
3527
     else
3528
     if (cke)
3529
       qi <= q_next;
3530
 
3531
   always @ (posedge clk or posedge rst)
3532
     if (rst)
3533
       q <= {length{1'b0}};
3534
     else
3535
       if (cke)
3536
         q <= (q_next>>1) ^ q_next;
3537
 
3538
endmodule
3539 40 unneback
`endif
3540
`ifdef CNT_GRAY_CE_BIN
3541 6 unneback
//////////////////////////////////////////////////////////////////////
3542
////                                                              ////
3543
////  Versatile counter                                           ////
3544
////                                                              ////
3545
////  Description                                                 ////
3546
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3547
////  counter                                                     ////
3548
////                                                              ////
3549
////  To Do:                                                      ////
3550
////   - add LFSR with more taps                                  ////
3551
////                                                              ////
3552
////  Author(s):                                                  ////
3553
////      - Michael Unneback, unneback@opencores.org              ////
3554
////        ORSoC AB                                              ////
3555
////                                                              ////
3556
//////////////////////////////////////////////////////////////////////
3557
////                                                              ////
3558
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3559
////                                                              ////
3560
//// This source file may be used and distributed without         ////
3561
//// restriction provided that this copyright statement is not    ////
3562
//// removed from the file and that any derivative work contains  ////
3563
//// the original copyright notice and the associated disclaimer. ////
3564
////                                                              ////
3565
//// This source file is free software; you can redistribute it   ////
3566
//// and/or modify it under the terms of the GNU Lesser General   ////
3567
//// Public License as published by the Free Software Foundation; ////
3568
//// either version 2.1 of the License, or (at your option) any   ////
3569
//// later version.                                               ////
3570
////                                                              ////
3571
//// This source is distributed in the hope that it will be       ////
3572
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3573
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3574
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3575
//// details.                                                     ////
3576
////                                                              ////
3577
//// You should have received a copy of the GNU Lesser General    ////
3578
//// Public License along with this source; if not, download it   ////
3579
//// from http://www.opencores.org/lgpl.shtml                     ////
3580
////                                                              ////
3581
//////////////////////////////////////////////////////////////////////
3582
 
3583
// GRAY counter
3584
 
3585 40 unneback
`define MODULE cnt_gray_ce_bin
3586
module `BASE`MODULE (
3587
`undef MODULE
3588
 cke, q, q_bin, rst, clk);
3589
 
3590 6 unneback
   parameter length = 4;
3591
   input cke;
3592
   output reg [length:1] q;
3593
   output [length:1] q_bin;
3594
   input rst;
3595
   input clk;
3596
 
3597
   parameter clear_value = 0;
3598
   parameter set_value = 1;
3599
   parameter wrap_value = 8;
3600
   parameter level1_value = 15;
3601
 
3602
   reg  [length:1] qi;
3603
   wire [length:1] q_next;
3604
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3605
 
3606
   always @ (posedge clk or posedge rst)
3607
     if (rst)
3608
       qi <= {length{1'b0}};
3609
     else
3610
     if (cke)
3611
       qi <= q_next;
3612
 
3613
   always @ (posedge clk or posedge rst)
3614
     if (rst)
3615
       q <= {length{1'b0}};
3616
     else
3617
       if (cke)
3618
         q <= (q_next>>1) ^ q_next;
3619
 
3620
   assign q_bin = qi;
3621
 
3622
endmodule
3623 40 unneback
`endif
3624 6 unneback
//////////////////////////////////////////////////////////////////////
3625
////                                                              ////
3626
////  Versatile library, counters                                 ////
3627
////                                                              ////
3628
////  Description                                                 ////
3629
////  counters                                                    ////
3630
////                                                              ////
3631
////                                                              ////
3632
////  To Do:                                                      ////
3633
////   - add more counters                                        ////
3634
////                                                              ////
3635
////  Author(s):                                                  ////
3636
////      - Michael Unneback, unneback@opencores.org              ////
3637
////        ORSoC AB                                              ////
3638
////                                                              ////
3639
//////////////////////////////////////////////////////////////////////
3640
////                                                              ////
3641
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3642
////                                                              ////
3643
//// This source file may be used and distributed without         ////
3644
//// restriction provided that this copyright statement is not    ////
3645
//// removed from the file and that any derivative work contains  ////
3646
//// the original copyright notice and the associated disclaimer. ////
3647
////                                                              ////
3648
//// This source file is free software; you can redistribute it   ////
3649
//// and/or modify it under the terms of the GNU Lesser General   ////
3650
//// Public License as published by the Free Software Foundation; ////
3651
//// either version 2.1 of the License, or (at your option) any   ////
3652
//// later version.                                               ////
3653
////                                                              ////
3654
//// This source is distributed in the hope that it will be       ////
3655
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3656
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3657
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3658
//// details.                                                     ////
3659
////                                                              ////
3660
//// You should have received a copy of the GNU Lesser General    ////
3661
//// Public License along with this source; if not, download it   ////
3662
//// from http://www.opencores.org/lgpl.shtml                     ////
3663
////                                                              ////
3664
//////////////////////////////////////////////////////////////////////
3665
 
3666 40 unneback
`ifdef CNT_SHREG_WRAP
3667
`define MODULE cnt_shreg_wrap
3668
module `BASE`MODULE ( q, rst, clk);
3669
`undef MODULE
3670 6 unneback
 
3671
   parameter length = 4;
3672
   output reg [0:length-1] q;
3673
   input rst;
3674
   input clk;
3675
 
3676
    always @ (posedge clk or posedge rst)
3677
    if (rst)
3678
        q <= {1'b1,{length-1{1'b0}}};
3679
    else
3680
        q <= {q[length-1],q[0:length-2]};
3681
 
3682
endmodule
3683 40 unneback
`endif
3684 6 unneback
 
3685 40 unneback
`ifdef CNT_SHREG_CE_WRAP
3686
`define MODULE cnt_shreg_ce_wrap
3687
module `BASE`MODULE ( cke, q, rst, clk);
3688
`undef MODULE
3689 6 unneback
 
3690
   parameter length = 4;
3691
   input cke;
3692
   output reg [0:length-1] q;
3693
   input rst;
3694
   input clk;
3695
 
3696
    always @ (posedge clk or posedge rst)
3697
    if (rst)
3698
        q <= {1'b1,{length-1{1'b0}}};
3699
    else
3700
        if (cke)
3701
            q <= {q[length-1],q[0:length-2]};
3702
 
3703
endmodule
3704 40 unneback
`endif
3705 6 unneback
 
3706 105 unneback
`ifdef CNT_SHREG_CLEAR
3707
`define MODULE cnt_shreg_clear
3708
module `BASE`MODULE ( clear, q, rst, clk);
3709
`undef MODULE
3710
 
3711
   parameter length = 4;
3712
   input clear;
3713
   output reg [0:length-1] q;
3714
   input rst;
3715
   input clk;
3716
 
3717
    always @ (posedge clk or posedge rst)
3718
    if (rst)
3719
        q <= {1'b1,{length-1{1'b0}}};
3720
    else
3721
        if (clear)
3722
            q <= {1'b1,{length-1{1'b0}}};
3723
        else
3724
            q <= q >> 1;
3725
 
3726
endmodule
3727
`endif
3728
 
3729 40 unneback
`ifdef CNT_SHREG_CE_CLEAR
3730
`define MODULE cnt_shreg_ce_clear
3731
module `BASE`MODULE ( cke, clear, q, rst, clk);
3732
`undef MODULE
3733 6 unneback
 
3734
   parameter length = 4;
3735
   input cke, clear;
3736
   output reg [0:length-1] q;
3737
   input rst;
3738
   input clk;
3739
 
3740
    always @ (posedge clk or posedge rst)
3741
    if (rst)
3742
        q <= {1'b1,{length-1{1'b0}}};
3743
    else
3744
        if (cke)
3745
            if (clear)
3746
                q <= {1'b1,{length-1{1'b0}}};
3747
            else
3748
                q <= q >> 1;
3749
 
3750
endmodule
3751 40 unneback
`endif
3752 6 unneback
 
3753 40 unneback
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3754
`define MODULE cnt_shreg_ce_clear_wrap
3755
module `BASE`MODULE ( cke, clear, q, rst, clk);
3756
`undef MODULE
3757 6 unneback
 
3758
   parameter length = 4;
3759
   input cke, clear;
3760
   output reg [0:length-1] q;
3761
   input rst;
3762
   input clk;
3763
 
3764
    always @ (posedge clk or posedge rst)
3765
    if (rst)
3766
        q <= {1'b1,{length-1{1'b0}}};
3767
    else
3768
        if (cke)
3769
            if (clear)
3770
                q <= {1'b1,{length-1{1'b0}}};
3771
            else
3772
            q <= {q[length-1],q[0:length-2]};
3773
 
3774
endmodule
3775 40 unneback
`endif
3776 6 unneback
//////////////////////////////////////////////////////////////////////
3777
////                                                              ////
3778
////  Versatile library, memories                                 ////
3779
////                                                              ////
3780
////  Description                                                 ////
3781
////  memories                                                    ////
3782
////                                                              ////
3783
////                                                              ////
3784
////  To Do:                                                      ////
3785
////   - add more memory types                                    ////
3786
////                                                              ////
3787
////  Author(s):                                                  ////
3788
////      - Michael Unneback, unneback@opencores.org              ////
3789
////        ORSoC AB                                              ////
3790
////                                                              ////
3791
//////////////////////////////////////////////////////////////////////
3792
////                                                              ////
3793
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3794
////                                                              ////
3795
//// This source file may be used and distributed without         ////
3796
//// restriction provided that this copyright statement is not    ////
3797
//// removed from the file and that any derivative work contains  ////
3798
//// the original copyright notice and the associated disclaimer. ////
3799
////                                                              ////
3800
//// This source file is free software; you can redistribute it   ////
3801
//// and/or modify it under the terms of the GNU Lesser General   ////
3802
//// Public License as published by the Free Software Foundation; ////
3803
//// either version 2.1 of the License, or (at your option) any   ////
3804
//// later version.                                               ////
3805
////                                                              ////
3806
//// This source is distributed in the hope that it will be       ////
3807
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3808
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3809
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3810
//// details.                                                     ////
3811
////                                                              ////
3812
//// You should have received a copy of the GNU Lesser General    ////
3813
//// Public License along with this source; if not, download it   ////
3814
//// from http://www.opencores.org/lgpl.shtml                     ////
3815
////                                                              ////
3816
//////////////////////////////////////////////////////////////////////
3817
 
3818 40 unneback
`ifdef ROM_INIT
3819 6 unneback
/// ROM
3820 40 unneback
`define MODULE rom_init
3821
module `BASE`MODULE ( adr, q, clk);
3822
`undef MODULE
3823 6 unneback
 
3824 7 unneback
   parameter data_width = 32;
3825
   parameter addr_width = 8;
3826 75 unneback
   parameter mem_size = 1<<addr_width;
3827 7 unneback
   input [(addr_width-1):0]       adr;
3828
   output reg [(data_width-1):0] q;
3829
   input                         clk;
3830 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
3831 7 unneback
   parameter memory_file = "vl_rom.vmem";
3832
   initial
3833
     begin
3834
        $readmemh(memory_file, rom);
3835
     end
3836
 
3837
   always @ (posedge clk)
3838
     q <= rom[adr];
3839 6 unneback
 
3840 7 unneback
endmodule
3841 40 unneback
`endif
3842 7 unneback
 
3843 40 unneback
`ifdef RAM
3844
`define MODULE ram
3845 6 unneback
// Single port RAM
3846 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
3847
`undef MODULE
3848 6 unneback
 
3849
   parameter data_width = 32;
3850
   parameter addr_width = 8;
3851 75 unneback
   parameter mem_size = 1<<addr_width;
3852 100 unneback
   parameter debug = 0;
3853 6 unneback
   input [(data_width-1):0]      d;
3854
   input [(addr_width-1):0]       adr;
3855
   input                         we;
3856 7 unneback
   output reg [(data_width-1):0] q;
3857 6 unneback
   input                         clk;
3858 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
3859 100 unneback
 
3860
    parameter memory_init = 0;
3861
    parameter memory_file = "vl_ram.vmem";
3862
    generate
3863
    if (memory_init == 1) begin : init_mem
3864
        initial
3865
            $readmemh(memory_file, ram);
3866
   end else if (memory_init == 2) begin : init_zero
3867
        integer k;
3868
        initial
3869
            for (k = 0; k < mem_size; k = k + 1)
3870
                ram[k] = 0;
3871 7 unneback
   end
3872
   endgenerate
3873
 
3874 100 unneback
    generate
3875
    if (debug==1) begin : debug_we
3876
        always @ (posedge clk)
3877
        if (we)
3878
            $display ("Value %h written at address %h : time %t", d, adr, $time);
3879
 
3880
    end
3881
    endgenerate
3882
 
3883 6 unneback
   always @ (posedge clk)
3884
   begin
3885
   if (we)
3886
     ram[adr] <= d;
3887
   q <= ram[adr];
3888
   end
3889
 
3890
endmodule
3891 40 unneback
`endif
3892 6 unneback
 
3893 40 unneback
`ifdef RAM_BE
3894
`define MODULE ram_be
3895 91 unneback
module `BASE`MODULE ( d, adr, be, we, q, clk);
3896 40 unneback
`undef MODULE
3897
 
3898 7 unneback
   parameter data_width = 32;
3899 72 unneback
   parameter addr_width = 6;
3900 75 unneback
   parameter mem_size = 1<<addr_width;
3901 7 unneback
   input [(data_width-1):0]      d;
3902
   input [(addr_width-1):0]       adr;
3903 73 unneback
   input [(data_width/8)-1:0]    be;
3904 7 unneback
   input                         we;
3905
   output reg [(data_width-1):0] q;
3906
   input                         clk;
3907
 
3908 85 unneback
 
3909 65 unneback
`ifdef SYSTEMVERILOG
3910 95 unneback
    // use a multi-dimensional packed array
3911
    //t o model individual bytes within the word
3912
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
3913 65 unneback
`else
3914 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
3915
    wire [data_width/8-1:0] cke;
3916 65 unneback
`endif
3917
 
3918 100 unneback
    parameter memory_init = 0;
3919
    parameter memory_file = "vl_ram.vmem";
3920
    generate
3921
    if (memory_init == 1) begin : init_mem
3922
        initial
3923
            $readmemh(memory_file, ram);
3924
    end else if (memory_init == 2) begin : init_zero
3925
        integer k;
3926
        initial
3927
            for (k = 0; k < mem_size; k = k + 1)
3928
                ram[k] = 0;
3929
    end
3930 7 unneback
   endgenerate
3931
 
3932 60 unneback
`ifdef SYSTEMVERILOG
3933
 
3934
always_ff@(posedge clk)
3935
begin
3936 95 unneback
    if(we) begin
3937 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
3938
        if(be[2]) ram[adr][2] <= d[23:16];
3939
        if(be[1]) ram[adr][1] <= d[15:8];
3940
        if(be[0]) ram[adr][0] <= d[7:0];
3941 60 unneback
    end
3942 90 unneback
        q <= ram[adr];
3943 60 unneback
end
3944
 
3945
`else
3946
 
3947 85 unneback
assign cke = {data_width/8{we}} & be;
3948 7 unneback
   genvar i;
3949 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
3950 7 unneback
      always @ (posedge clk)
3951 85 unneback
      if (cke[i])
3952 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3953
   end
3954
   endgenerate
3955
 
3956
   always @ (posedge clk)
3957
      q <= ram[adr];
3958
 
3959 60 unneback
`endif
3960
 
3961 93 unneback
`ifdef verilator
3962 85 unneback
   // Function to access RAM (for use by Verilator).
3963
   function [31:0] get_mem;
3964
      // verilator public
3965 90 unneback
      input [addr_width-1:0]             addr;
3966 85 unneback
      get_mem = ram[addr];
3967
   endfunction // get_mem
3968
 
3969
   // Function to write RAM (for use by Verilator).
3970
   function set_mem;
3971
      // verilator public
3972 90 unneback
      input [addr_width-1:0]             addr;
3973
      input [data_width-1:0]             data;
3974 85 unneback
      ram[addr] = data;
3975
   endfunction // set_mem
3976 93 unneback
`endif
3977 85 unneback
 
3978 7 unneback
endmodule
3979 40 unneback
`endif
3980 7 unneback
 
3981 40 unneback
`ifdef DPRAM_1R1W
3982
`define MODULE dpram_1r1w
3983
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3984
`undef MODULE
3985 6 unneback
   parameter data_width = 32;
3986
   parameter addr_width = 8;
3987 75 unneback
   parameter mem_size = 1<<addr_width;
3988 6 unneback
   input [(data_width-1):0]      d_a;
3989
   input [(addr_width-1):0]       adr_a;
3990
   input [(addr_width-1):0]       adr_b;
3991
   input                         we_a;
3992
   output [(data_width-1):0]      q_b;
3993
   input                         clk_a, clk_b;
3994
   reg [(addr_width-1):0]         adr_b_reg;
3995 100 unneback
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
3996 7 unneback
 
3997 100 unneback
    parameter memory_init = 0;
3998
    parameter memory_file = "vl_ram.vmem";
3999
    parameter debug = 0;
4000
 
4001
    generate
4002
    if (memory_init == 1) begin : init_mem
4003
        initial
4004
            $readmemh(memory_file, ram);
4005
    end else if (memory_init == 2) begin : init_zero
4006
        integer k;
4007
        initial
4008
            for (k = 0; k < mem_size; k = k + 1)
4009
                ram[k] = 0;
4010
    end
4011 7 unneback
   endgenerate
4012
 
4013 100 unneback
    generate
4014
    if (debug==1) begin : debug_we
4015
        always @ (posedge clk_a)
4016
        if (we_a)
4017
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4018
 
4019
    end
4020
    endgenerate
4021
 
4022 6 unneback
   always @ (posedge clk_a)
4023
   if (we_a)
4024
     ram[adr_a] <= d_a;
4025
   always @ (posedge clk_b)
4026
   adr_b_reg <= adr_b;
4027
   assign q_b = ram[adr_b_reg];
4028 40 unneback
 
4029 6 unneback
endmodule
4030 40 unneback
`endif
4031 6 unneback
 
4032 40 unneback
`ifdef DPRAM_2R1W
4033
`define MODULE dpram_2r1w
4034
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
4035
`undef MODULE
4036
 
4037 6 unneback
   parameter data_width = 32;
4038
   parameter addr_width = 8;
4039 75 unneback
   parameter mem_size = 1<<addr_width;
4040 6 unneback
   input [(data_width-1):0]      d_a;
4041
   input [(addr_width-1):0]       adr_a;
4042
   input [(addr_width-1):0]       adr_b;
4043
   input                         we_a;
4044
   output [(data_width-1):0]      q_b;
4045
   output reg [(data_width-1):0] q_a;
4046
   input                         clk_a, clk_b;
4047
   reg [(data_width-1):0]         q_b;
4048 98 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
4049 7 unneback
 
4050 100 unneback
    parameter memory_init = 0;
4051
    parameter memory_file = "vl_ram.vmem";
4052
    parameter debug = 0;
4053
 
4054
    generate
4055
    if (memory_init == 1) begin : init_mem
4056
        initial
4057
            $readmemh(memory_file, ram);
4058
    end else if (memory_init == 2) begin : init_zero
4059
        integer k;
4060
        initial
4061
            for (k = 0; k < mem_size; k = k + 1)
4062
                ram[k] = 0;
4063
    end
4064 7 unneback
   endgenerate
4065
 
4066 100 unneback
    generate
4067
    if (debug==1) begin : debug_we
4068
        always @ (posedge clk_a)
4069
        if (we_a)
4070
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4071
 
4072
    end
4073
    endgenerate
4074
 
4075 6 unneback
   always @ (posedge clk_a)
4076
     begin
4077
        q_a <= ram[adr_a];
4078
        if (we_a)
4079
             ram[adr_a] <= d_a;
4080
     end
4081
   always @ (posedge clk_b)
4082
          q_b <= ram[adr_b];
4083
endmodule
4084 40 unneback
`endif
4085 6 unneback
 
4086 100 unneback
`ifdef DPRAM_1R2W
4087
`define MODULE dpram_1r2w
4088
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
4089
`undef MODULE
4090
 
4091
   parameter data_width = 32;
4092
   parameter addr_width = 8;
4093
   parameter mem_size = 1<<addr_width;
4094
   input [(data_width-1):0]      d_a;
4095
   input [(addr_width-1):0]       adr_a;
4096
   input [(addr_width-1):0]       adr_b;
4097
   input                         we_a;
4098
   input [(data_width-1):0]       d_b;
4099
   output reg [(data_width-1):0] q_a;
4100
   input                         we_b;
4101
   input                         clk_a, clk_b;
4102
   reg [(data_width-1):0]         q_b;
4103
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
4104
 
4105
    parameter memory_init = 0;
4106
    parameter memory_file = "vl_ram.vmem";
4107
    parameter debug = 0;
4108
 
4109
    generate
4110
    if (memory_init == 1) begin : init_mem
4111
        initial
4112
            $readmemh(memory_file, ram);
4113
    end else if (memory_init == 2) begin : init_zero
4114
        integer k;
4115
        initial
4116
            for (k = 0; k < mem_size; k = k + 1)
4117
                ram[k] = 0;
4118
    end
4119
   endgenerate
4120
 
4121
    generate
4122
    if (debug==1) begin : debug_we
4123
        always @ (posedge clk_a)
4124
        if (we_a)
4125
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4126
        always @ (posedge clk_b)
4127
        if (we_b)
4128
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4129
    end
4130
    endgenerate
4131
 
4132
   always @ (posedge clk_a)
4133
     begin
4134
        q_a <= ram[adr_a];
4135
        if (we_a)
4136
             ram[adr_a] <= d_a;
4137
     end
4138
   always @ (posedge clk_b)
4139
     begin
4140
        if (we_b)
4141
          ram[adr_b] <= d_b;
4142
     end
4143
endmodule
4144
`endif
4145
 
4146 40 unneback
`ifdef DPRAM_2R2W
4147
`define MODULE dpram_2r2w
4148
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
4149
`undef MODULE
4150
 
4151 6 unneback
   parameter data_width = 32;
4152
   parameter addr_width = 8;
4153 75 unneback
   parameter mem_size = 1<<addr_width;
4154 6 unneback
   input [(data_width-1):0]      d_a;
4155
   input [(addr_width-1):0]       adr_a;
4156
   input [(addr_width-1):0]       adr_b;
4157
   input                         we_a;
4158
   output [(data_width-1):0]      q_b;
4159
   input [(data_width-1):0]       d_b;
4160
   output reg [(data_width-1):0] q_a;
4161
   input                         we_b;
4162
   input                         clk_a, clk_b;
4163
   reg [(data_width-1):0]         q_b;
4164 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
4165 7 unneback
 
4166 100 unneback
    parameter memory_init = 0;
4167
    parameter memory_file = "vl_ram.vmem";
4168
    parameter debug = 0;
4169
 
4170
    generate
4171
    if (memory_init) begin : init_mem
4172
        initial
4173
            $readmemh(memory_file, ram);
4174
    end else if (memory_init == 2) begin : init_zero
4175
        integer k;
4176
        initial
4177
            for (k = 0; k < mem_size; k = k + 1)
4178
                ram[k] = 0;
4179
    end
4180 7 unneback
   endgenerate
4181
 
4182 100 unneback
    generate
4183
    if (debug==1) begin : debug_we
4184
        always @ (posedge clk_a)
4185
        if (we_a)
4186
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4187
        always @ (posedge clk_b)
4188
        if (we_b)
4189
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4190
    end
4191
    endgenerate
4192
 
4193 6 unneback
   always @ (posedge clk_a)
4194
     begin
4195
        q_a <= ram[adr_a];
4196
        if (we_a)
4197
             ram[adr_a] <= d_a;
4198
     end
4199
   always @ (posedge clk_b)
4200
     begin
4201
        q_b <= ram[adr_b];
4202
        if (we_b)
4203
          ram[adr_b] <= d_b;
4204
     end
4205
endmodule
4206 40 unneback
`endif
4207 6 unneback
 
4208 83 unneback
 
4209 75 unneback
`ifdef DPRAM_BE_2R2W
4210
`define MODULE dpram_be_2r2w
4211 92 unneback
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
4212 75 unneback
`undef MODULE
4213
 
4214
   parameter a_data_width = 32;
4215
   parameter a_addr_width = 8;
4216 95 unneback
   parameter b_data_width = 64; //a_data_width;
4217 91 unneback
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
4218 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
4219
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
4220 91 unneback
 
4221 100 unneback
   parameter memory_init = 0;
4222 95 unneback
   parameter memory_file = "vl_ram.vmem";
4223 100 unneback
   parameter debug = 0;
4224 95 unneback
 
4225 75 unneback
   input [(a_data_width-1):0]      d_a;
4226 91 unneback
   input [(a_addr_width-1):0]       adr_a;
4227
   input [(a_data_width/8-1):0]    be_a;
4228
   input                           we_a;
4229 75 unneback
   output reg [(a_data_width-1):0] q_a;
4230 91 unneback
   input [(b_data_width-1):0]       d_b;
4231
   input [(b_addr_width-1):0]       adr_b;
4232 92 unneback
   input [(b_data_width/8-1):0]    be_b;
4233
   input                           we_b;
4234
   output reg [(b_data_width-1):0]          q_b;
4235 91 unneback
   input                           clk_a, clk_b;
4236 75 unneback
 
4237 100 unneback
    generate
4238
    if (debug==1) begin : debug_we
4239
        always @ (posedge clk_a)
4240
        if (we_a)
4241
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4242
        always @ (posedge clk_b)
4243
        if (we_b)
4244
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4245
    end
4246
    endgenerate
4247
 
4248
 
4249 91 unneback
`ifdef SYSTEMVERILOG
4250
// use a multi-dimensional packed array
4251
//to model individual bytes within the word
4252
 
4253 75 unneback
generate
4254 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
4255 75 unneback
 
4256 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4257 95 unneback
 
4258
    initial
4259 100 unneback
        if (memory_init==1)
4260 95 unneback
            $readmemh(memory_file, ram);
4261 100 unneback
 
4262
    integer k;
4263
    initial
4264
        if (memory_init==2)
4265
            for (k = 0; k < mem_size; k = k + 1)
4266
                ram[k] = 0;
4267 91 unneback
 
4268
    always_ff@(posedge clk_a)
4269
    begin
4270
        if(we_a) begin
4271 100 unneback
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
4272
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
4273
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
4274
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
4275 91 unneback
        end
4276
    end
4277
 
4278 92 unneback
    always@(posedge clk_a)
4279
        q_a = ram[adr_a];
4280 91 unneback
 
4281
    always_ff@(posedge clk_b)
4282 92 unneback
    begin
4283
        if(we_b) begin
4284 100 unneback
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
4285
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
4286
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
4287
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
4288 92 unneback
        end
4289
    end
4290 91 unneback
 
4291 92 unneback
    always@(posedge clk_b)
4292
        q_b = ram[adr_b];
4293 91 unneback
 
4294 75 unneback
end
4295
endgenerate
4296
 
4297 95 unneback
generate
4298
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
4299
 
4300 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4301 95 unneback
 
4302
    initial
4303 100 unneback
        if (memory_init==1)
4304 95 unneback
            $readmemh(memory_file, ram);
4305 100 unneback
 
4306
    integer k;
4307
    initial
4308
        if (memory_init==2)
4309
            for (k = 0; k < mem_size; k = k + 1)
4310
                ram[k] = 0;
4311 95 unneback
 
4312
    always_ff@(posedge clk_a)
4313
    begin
4314
        if(we_a) begin
4315
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
4316
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
4317
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
4318
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
4319
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
4320
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
4321
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
4322
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
4323
        end
4324
    end
4325
 
4326
    always@(posedge clk_a)
4327
        q_a = ram[adr_a];
4328
 
4329
    always_ff@(posedge clk_b)
4330
    begin
4331
        if(we_b) begin
4332
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
4333
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
4334
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
4335
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
4336
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
4337
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
4338
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
4339
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
4340
        end
4341
    end
4342
 
4343
    always@(posedge clk_b)
4344
        q_b = ram[adr_b];
4345
 
4346
end
4347
endgenerate
4348
 
4349
generate
4350
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
4351
logic [31:0] temp;
4352
`define MODULE dpram_be_2r2w
4353 111 unneback
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
4354 95 unneback
`undef MODULE
4355
dpram6464 (
4356
    .d_a(d_a),
4357
    .q_a(q_a),
4358
    .adr_a(adr_a),
4359
    .be_a(be_a),
4360
    .we_a(we_a),
4361
    .clk_a(clk_a),
4362
    .d_b({d_b,d_b}),
4363
    .q_b(temp),
4364
    .adr_b(adr_b),
4365
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
4366
    .we_b(we_b),
4367
    .clk_b(clk_b)
4368
);
4369
 
4370 100 unneback
always @ (adr_b[0] or temp)
4371 95 unneback
    if (adr_b[0])
4372
        q_b = temp[31:16];
4373
    else
4374
        q_b = temp[15:0];
4375
 
4376
end
4377
endgenerate
4378
 
4379
generate
4380
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
4381
logic [63:0] temp;
4382
`define MODULE dpram_be_2r2w
4383 111 unneback
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
4384 95 unneback
`undef MODULE
4385
dpram6464 (
4386
    .d_a({d_a,d_a}),
4387
    .q_a(temp),
4388
    .adr_a(adr_a[a_addr_width-1:1]),
4389
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
4390
    .we_a(we_a),
4391
    .clk_a(clk_a),
4392
    .d_b(d_b),
4393
    .q_b(q_b),
4394
    .adr_b(adr_b),
4395
    .be_b(be_b),
4396
    .we_b(we_b),
4397
    .clk_b(clk_b)
4398
);
4399
 
4400 100 unneback
always @ (adr_a[0] or temp)
4401 95 unneback
    if (adr_a[0])
4402
        q_a = temp[63:32];
4403
    else
4404
        q_a = temp[31:0];
4405
 
4406
end
4407
endgenerate
4408
 
4409 91 unneback
`else
4410 92 unneback
    // This modules requires SystemVerilog
4411 98 unneback
    // at this point anyway
4412 91 unneback
`endif
4413 75 unneback
endmodule
4414
`endif
4415
 
4416 91 unneback
`ifdef CAM
4417 6 unneback
// Content addresable memory, CAM
4418 91 unneback
`endif
4419 6 unneback
 
4420 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
4421 6 unneback
// FIFO
4422 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
4423
module `BASE`MODULE (
4424
`undef MODULE
4425 25 unneback
    d, wr, fifo_full,
4426
    q, rd, fifo_empty,
4427
    fill_level,
4428
    clk, rst
4429
    );
4430
 
4431
parameter data_width = 18;
4432
parameter addr_width = 4;
4433 6 unneback
 
4434 25 unneback
// write side
4435
input  [data_width-1:0] d;
4436
input                   wr;
4437
output                  fifo_full;
4438
// read side
4439
output [data_width-1:0] q;
4440
input                   rd;
4441
output                  fifo_empty;
4442
// common
4443
output [addr_width:0]   fill_level;
4444
input rst, clk;
4445
 
4446
wire [addr_width:1] wadr, radr;
4447
 
4448 40 unneback
`define MODULE cnt_bin_ce
4449
`BASE`MODULE
4450 25 unneback
    # ( .length(addr_width))
4451
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
4452 40 unneback
`BASE`MODULE
4453 25 unneback
    # (.length(addr_width))
4454
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
4455 40 unneback
`undef MODULE
4456 25 unneback
 
4457 40 unneback
`define MODULE dpram_1r1w
4458
`BASE`MODULE
4459 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
4460
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
4461 40 unneback
`undef MODULE
4462 25 unneback
 
4463 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
4464
`BASE`MODULE
4465 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
4466 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
4467 40 unneback
`undef MODULE
4468 25 unneback
endmodule
4469 40 unneback
`endif
4470 25 unneback
 
4471 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
4472 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
4473
// RAM is supposed to be larger than the two FIFOs
4474
// LFSR counters used adr pointers
4475 40 unneback
`define MODULE fifo_2r2w_sync_simplex
4476
module `BASE`MODULE (
4477
`undef MODULE
4478 27 unneback
    // a side
4479
    a_d, a_wr, a_fifo_full,
4480
    a_q, a_rd, a_fifo_empty,
4481
    a_fill_level,
4482
    // b side
4483
    b_d, b_wr, b_fifo_full,
4484
    b_q, b_rd, b_fifo_empty,
4485
    b_fill_level,
4486
    // common
4487
    clk, rst
4488
    );
4489
parameter data_width = 8;
4490
parameter addr_width = 5;
4491
parameter fifo_full_level = (1<<addr_width)-1;
4492
 
4493
// a side
4494
input  [data_width-1:0] a_d;
4495
input                   a_wr;
4496
output                  a_fifo_full;
4497
output [data_width-1:0] a_q;
4498
input                   a_rd;
4499
output                  a_fifo_empty;
4500
output [addr_width-1:0] a_fill_level;
4501
 
4502
// b side
4503
input  [data_width-1:0] b_d;
4504
input                   b_wr;
4505
output                  b_fifo_full;
4506
output [data_width-1:0] b_q;
4507
input                   b_rd;
4508
output                  b_fifo_empty;
4509
output [addr_width-1:0] b_fill_level;
4510
 
4511
input                   clk;
4512
input                   rst;
4513
 
4514
// adr_gen
4515
wire [addr_width:1] a_wadr, a_radr;
4516
wire [addr_width:1] b_wadr, b_radr;
4517
// dpram
4518
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4519
 
4520 40 unneback
`define MODULE cnt_lfsr_ce
4521
`BASE`MODULE
4522 27 unneback
    # ( .length(addr_width))
4523
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
4524
 
4525 40 unneback
`BASE`MODULE
4526 27 unneback
    # (.length(addr_width))
4527
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
4528
 
4529 40 unneback
`BASE`MODULE
4530 27 unneback
    # ( .length(addr_width))
4531
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
4532
 
4533 40 unneback
`BASE`MODULE
4534 27 unneback
    # (.length(addr_width))
4535
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
4536 40 unneback
`undef MODULE
4537 27 unneback
 
4538
// mux read or write adr to DPRAM
4539
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
4540
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
4541
 
4542 40 unneback
`define MODULE dpram_2r2w
4543
`BASE`MODULE
4544 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
4545
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4546
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4547 40 unneback
`undef MODULE
4548
 
4549
`define MODULE cnt_bin_ce_rew_zq_l1
4550
`BASE`MODULE
4551 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
4552 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
4553
 
4554 40 unneback
`BASE`MODULE
4555 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
4556 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
4557 40 unneback
`undef MODULE
4558 27 unneback
 
4559
endmodule
4560 40 unneback
`endif
4561 27 unneback
 
4562 40 unneback
`ifdef FIFO_CMP_ASYNC
4563
`define MODULE fifo_cmp_async
4564
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
4565
`undef MODULE
4566 6 unneback
 
4567 11 unneback
   parameter addr_width = 4;
4568
   parameter N = addr_width-1;
4569 6 unneback
 
4570
   parameter Q1 = 2'b00;
4571
   parameter Q2 = 2'b01;
4572
   parameter Q3 = 2'b11;
4573
   parameter Q4 = 2'b10;
4574
 
4575
   parameter going_empty = 1'b0;
4576
   parameter going_full  = 1'b1;
4577
 
4578
   input [N:0]  wptr, rptr;
4579 14 unneback
   output       fifo_empty;
4580 6 unneback
   output       fifo_full;
4581
   input        wclk, rclk, rst;
4582
 
4583
`ifndef GENERATE_DIRECTION_AS_LATCH
4584
   wire direction;
4585
`endif
4586
`ifdef GENERATE_DIRECTION_AS_LATCH
4587
   reg direction;
4588
`endif
4589
   reg  direction_set, direction_clr;
4590
 
4591
   wire async_empty, async_full;
4592
   wire fifo_full2;
4593 14 unneback
   wire fifo_empty2;
4594 6 unneback
 
4595
   // direction_set
4596
   always @ (wptr[N:N-1] or rptr[N:N-1])
4597
     case ({wptr[N:N-1],rptr[N:N-1]})
4598
       {Q1,Q2} : direction_set <= 1'b1;
4599
       {Q2,Q3} : direction_set <= 1'b1;
4600
       {Q3,Q4} : direction_set <= 1'b1;
4601
       {Q4,Q1} : direction_set <= 1'b1;
4602
       default : direction_set <= 1'b0;
4603
     endcase
4604
 
4605
   // direction_clear
4606
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
4607
     if (rst)
4608
       direction_clr <= 1'b1;
4609
     else
4610
       case ({wptr[N:N-1],rptr[N:N-1]})
4611
         {Q2,Q1} : direction_clr <= 1'b1;
4612
         {Q3,Q2} : direction_clr <= 1'b1;
4613
         {Q4,Q3} : direction_clr <= 1'b1;
4614
         {Q1,Q4} : direction_clr <= 1'b1;
4615
         default : direction_clr <= 1'b0;
4616
       endcase
4617
 
4618 40 unneback
`define MODULE dff_sr
4619 6 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
4620 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
4621 6 unneback
`endif
4622
 
4623
`ifdef GENERATE_DIRECTION_AS_LATCH
4624
   always @ (posedge direction_set or posedge direction_clr)
4625
     if (direction_clr)
4626
       direction <= going_empty;
4627
     else
4628
       direction <= going_full;
4629
`endif
4630
 
4631
   assign async_empty = (wptr == rptr) && (direction==going_empty);
4632
   assign async_full  = (wptr == rptr) && (direction==going_full);
4633
 
4634 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
4635
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
4636
`undef MODULE
4637 6 unneback
 
4638
/*
4639
   always @ (posedge wclk or posedge rst or posedge async_full)
4640
     if (rst)
4641
       {fifo_full, fifo_full2} <= 2'b00;
4642
     else if (async_full)
4643
       {fifo_full, fifo_full2} <= 2'b11;
4644
     else
4645
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
4646
*/
4647 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
4648 6 unneback
     if (async_empty)
4649
       {fifo_empty, fifo_empty2} <= 2'b11;
4650
     else
4651 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
4652 40 unneback
`define MODULE dff
4653
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
4654
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
4655
`undef MODULE
4656 27 unneback
endmodule // async_compb
4657 40 unneback
`endif
4658 6 unneback
 
4659 40 unneback
`ifdef FIFO_1R1W_ASYNC
4660
`define MODULE fifo_1r1w_async
4661
module `BASE`MODULE (
4662
`undef MODULE
4663 6 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
4664
    q, rd, fifo_empty, rd_clk, rd_rst
4665
    );
4666
 
4667
parameter data_width = 18;
4668
parameter addr_width = 4;
4669
 
4670
// write side
4671
input  [data_width-1:0] d;
4672
input                   wr;
4673
output                  fifo_full;
4674
input                   wr_clk;
4675
input                   wr_rst;
4676
// read side
4677
output [data_width-1:0] q;
4678
input                   rd;
4679
output                  fifo_empty;
4680
input                   rd_clk;
4681
input                   rd_rst;
4682
 
4683
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
4684 23 unneback
 
4685 40 unneback
`define MODULE cnt_gray_ce_bin
4686
`BASE`MODULE
4687 6 unneback
    # ( .length(addr_width))
4688
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
4689
 
4690 40 unneback
`BASE`MODULE
4691 6 unneback
    # (.length(addr_width))
4692 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
4693 40 unneback
`undef MODULE
4694 6 unneback
 
4695 40 unneback
`define MODULE dpram_1r1w
4696
`BASE`MODULE
4697 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
4698
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
4699 40 unneback
`undef MODULE
4700 6 unneback
 
4701 40 unneback
`define MODULE fifo_cmp_async
4702
`BASE`MODULE
4703 6 unneback
    # (.addr_width(addr_width))
4704
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
4705 40 unneback
`undef MODULE
4706 6 unneback
 
4707
endmodule
4708 40 unneback
`endif
4709 6 unneback
 
4710 40 unneback
`ifdef FIFO_2R2W_ASYNC
4711
`define MODULE fifo_2r2w_async
4712
module `BASE`MODULE (
4713
`undef MODULE
4714 6 unneback
    // a side
4715
    a_d, a_wr, a_fifo_full,
4716
    a_q, a_rd, a_fifo_empty,
4717
    a_clk, a_rst,
4718
    // b side
4719
    b_d, b_wr, b_fifo_full,
4720
    b_q, b_rd, b_fifo_empty,
4721
    b_clk, b_rst
4722
    );
4723
 
4724
parameter data_width = 18;
4725
parameter addr_width = 4;
4726
 
4727
// a side
4728
input  [data_width-1:0] a_d;
4729
input                   a_wr;
4730
output                  a_fifo_full;
4731
output [data_width-1:0] a_q;
4732
input                   a_rd;
4733
output                  a_fifo_empty;
4734
input                   a_clk;
4735
input                   a_rst;
4736
 
4737
// b side
4738
input  [data_width-1:0] b_d;
4739
input                   b_wr;
4740
output                  b_fifo_full;
4741
output [data_width-1:0] b_q;
4742
input                   b_rd;
4743
output                  b_fifo_empty;
4744
input                   b_clk;
4745
input                   b_rst;
4746
 
4747 40 unneback
`define MODULE fifo_1r1w_async
4748
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4749 6 unneback
vl_fifo_1r1w_async_a (
4750
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4751
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4752
    );
4753
 
4754 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4755 6 unneback
vl_fifo_1r1w_async_b (
4756
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4757
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4758
    );
4759 40 unneback
`undef MODULE
4760
 
4761 6 unneback
endmodule
4762 40 unneback
`endif
4763 6 unneback
 
4764 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4765
`define MODULE fifo_2r2w_async_simplex
4766
module `BASE`MODULE (
4767
`undef MODULE
4768 6 unneback
    // a side
4769
    a_d, a_wr, a_fifo_full,
4770
    a_q, a_rd, a_fifo_empty,
4771
    a_clk, a_rst,
4772
    // b side
4773
    b_d, b_wr, b_fifo_full,
4774
    b_q, b_rd, b_fifo_empty,
4775
    b_clk, b_rst
4776
    );
4777
 
4778
parameter data_width = 18;
4779
parameter addr_width = 4;
4780
 
4781
// a side
4782
input  [data_width-1:0] a_d;
4783
input                   a_wr;
4784
output                  a_fifo_full;
4785
output [data_width-1:0] a_q;
4786
input                   a_rd;
4787
output                  a_fifo_empty;
4788
input                   a_clk;
4789
input                   a_rst;
4790
 
4791
// b side
4792
input  [data_width-1:0] b_d;
4793
input                   b_wr;
4794
output                  b_fifo_full;
4795
output [data_width-1:0] b_q;
4796
input                   b_rd;
4797
output                  b_fifo_empty;
4798
input                   b_clk;
4799
input                   b_rst;
4800
 
4801
// adr_gen
4802
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4803
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4804
// dpram
4805
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4806
 
4807 40 unneback
`define MODULE cnt_gray_ce_bin
4808
`BASE`MODULE
4809 6 unneback
    # ( .length(addr_width))
4810
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4811
 
4812 40 unneback
`BASE`MODULE
4813 6 unneback
    # (.length(addr_width))
4814
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4815
 
4816 40 unneback
`BASE`MODULE
4817 6 unneback
    # ( .length(addr_width))
4818
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4819
 
4820 40 unneback
`BASE`MODULE
4821 6 unneback
    # (.length(addr_width))
4822
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4823 40 unneback
`undef MODULE
4824 6 unneback
 
4825
// mux read or write adr to DPRAM
4826
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4827
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4828
 
4829 40 unneback
`define MODULE dpram_2r2w
4830
`BASE`MODULE
4831 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
4832
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4833
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4834 40 unneback
`undef MODULE
4835 6 unneback
 
4836 40 unneback
`define MODULE fifo_cmp_async
4837
`BASE`MODULE
4838 6 unneback
    # (.addr_width(addr_width))
4839
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4840
 
4841 40 unneback
`BASE`MODULE
4842 6 unneback
    # (.addr_width(addr_width))
4843
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4844 40 unneback
`undef MODULE
4845 6 unneback
 
4846
endmodule
4847 40 unneback
`endif
4848 48 unneback
 
4849
`ifdef REG_FILE
4850
`define MODULE reg_file
4851
module `BASE`MODULE (
4852
`undef MODULE
4853
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4854
);
4855
parameter data_width = 32;
4856
parameter addr_width = 5;
4857
input [addr_width-1:0] a1, a2, a3;
4858
input [data_width-1:0] wd3;
4859
input we3;
4860
output [data_width-1:0] rd1, rd2;
4861
input clk;
4862
 
4863
`ifdef ACTEL
4864
reg [data_width-1:0] wd3_reg;
4865
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4866
reg we3_reg;
4867 98 unneback
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
4868
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
4869 48 unneback
always @ (posedge clk or posedge rst)
4870
if (rst)
4871
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4872
else
4873
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4874
 
4875
    always @ (negedge clk)
4876
    if (we3_reg)
4877
        ram1[a3_reg] <= wd3;
4878
    always @ (posedge clk)
4879
        a1_reg <= a1;
4880
    assign rd1 = ram1[a1_reg];
4881
 
4882
    always @ (negedge clk)
4883
    if (we3_reg)
4884
        ram2[a3_reg] <= wd3;
4885
    always @ (posedge clk)
4886
        a2_reg <= a2;
4887
    assign rd2 = ram2[a2_reg];
4888
 
4889
`else
4890
 
4891
`define MODULE dpram_1r1w
4892
`BASE`MODULE
4893
    # ( .data_width(data_width), .addr_width(addr_width))
4894
    ram1 (
4895
        .d_a(wd3),
4896
        .adr_a(a3),
4897
        .we_a(we3),
4898
        .clk_a(clk),
4899
        .q_b(rd1),
4900
        .adr_b(a1),
4901
        .clk_b(clk) );
4902
 
4903
`BASE`MODULE
4904
    # ( .data_width(data_width), .addr_width(addr_width))
4905
    ram2 (
4906
        .d_a(wd3),
4907
        .adr_a(a3),
4908
        .we_a(we3),
4909
        .clk_a(clk),
4910
        .q_b(rd2),
4911
        .adr_b(a2),
4912
        .clk_b(clk) );
4913
`undef MODULE
4914
 
4915
`endif
4916
 
4917
endmodule
4918
`endif
4919 12 unneback
//////////////////////////////////////////////////////////////////////
4920
////                                                              ////
4921
////  Versatile library, wishbone stuff                           ////
4922
////                                                              ////
4923
////  Description                                                 ////
4924
////  Wishbone compliant modules                                  ////
4925
////                                                              ////
4926
////                                                              ////
4927
////  To Do:                                                      ////
4928
////   -                                                          ////
4929
////                                                              ////
4930
////  Author(s):                                                  ////
4931
////      - Michael Unneback, unneback@opencores.org              ////
4932
////        ORSoC AB                                              ////
4933
////                                                              ////
4934
//////////////////////////////////////////////////////////////////////
4935
////                                                              ////
4936
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4937
////                                                              ////
4938
//// This source file may be used and distributed without         ////
4939
//// restriction provided that this copyright statement is not    ////
4940
//// removed from the file and that any derivative work contains  ////
4941
//// the original copyright notice and the associated disclaimer. ////
4942
////                                                              ////
4943
//// This source file is free software; you can redistribute it   ////
4944
//// and/or modify it under the terms of the GNU Lesser General   ////
4945
//// Public License as published by the Free Software Foundation; ////
4946
//// either version 2.1 of the License, or (at your option) any   ////
4947
//// later version.                                               ////
4948
////                                                              ////
4949
//// This source is distributed in the hope that it will be       ////
4950
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4951
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4952
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4953
//// details.                                                     ////
4954
////                                                              ////
4955
//// You should have received a copy of the GNU Lesser General    ////
4956
//// Public License along with this source; if not, download it   ////
4957
//// from http://www.opencores.org/lgpl.shtml                     ////
4958
////                                                              ////
4959
//////////////////////////////////////////////////////////////////////
4960
 
4961 75 unneback
`ifdef WB_ADR_INC
4962
`timescale 1ns/1ns
4963
`define MODULE wb_adr_inc
4964 85 unneback
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
4965 75 unneback
`undef MODULE
4966 83 unneback
parameter adr_width = 10;
4967
parameter max_burst_width = 4;
4968 85 unneback
input cyc_i, stb_i, we_i;
4969 83 unneback
input [2:0] cti_i;
4970
input [1:0] bte_i;
4971
input [adr_width-1:0] adr_i;
4972
output [adr_width-1:0] adr_o;
4973
output ack_o;
4974
input clk, rst;
4975 75 unneback
 
4976 83 unneback
reg [adr_width-1:0] adr;
4977 90 unneback
wire [max_burst_width-1:0] to_adr;
4978 91 unneback
reg [max_burst_width-1:0] last_adr;
4979 92 unneback
reg last_cycle;
4980
localparam idle_or_eoc = 1'b0;
4981
localparam cyc_or_ws   = 1'b1;
4982 90 unneback
 
4983 91 unneback
always @ (posedge clk or posedge rst)
4984
if (rst)
4985
    last_adr <= {max_burst_width{1'b0}};
4986
else
4987
    if (stb_i)
4988 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
4989 91 unneback
 
4990 83 unneback
generate
4991
if (max_burst_width==0) begin : inst_0
4992 97 unneback
 
4993
        reg ack_o;
4994
        assign adr_o = adr_i;
4995
        always @ (posedge clk or posedge rst)
4996
        if (rst)
4997
            ack_o <= 1'b0;
4998
        else
4999
            ack_o <= cyc_i & stb_i & !ack_o;
5000
 
5001 83 unneback
end else begin
5002
 
5003
    always @ (posedge clk or posedge rst)
5004
    if (rst)
5005 92 unneback
        last_cycle <= idle_or_eoc;
5006 83 unneback
    else
5007 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
5008
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
5009
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
5010
                      cyc_or_ws; // cyc
5011
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
5012 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
5013 91 unneback
                                        (!stb_i) ? last_adr :
5014 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
5015 85 unneback
                                        adr[max_burst_width-1:0];
5016 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
5017 97 unneback
 
5018 83 unneback
end
5019
endgenerate
5020
 
5021
generate
5022
if (max_burst_width==2) begin : inst_2
5023
    always @ (posedge clk or posedge rst)
5024
    if (rst)
5025
        adr <= 2'h0;
5026
    else
5027
        if (cyc_i & stb_i)
5028
            adr[1:0] <= to_adr[1:0] + 2'd1;
5029 75 unneback
        else
5030 83 unneback
            adr <= to_adr[1:0];
5031
end
5032
endgenerate
5033
 
5034
generate
5035
if (max_burst_width==3) begin : inst_3
5036
    always @ (posedge clk or posedge rst)
5037
    if (rst)
5038
        adr <= 3'h0;
5039
    else
5040
        if (cyc_i & stb_i)
5041
            case (bte_i)
5042
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
5043
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
5044 75 unneback
            endcase
5045 83 unneback
        else
5046
            adr <= to_adr[2:0];
5047
end
5048
endgenerate
5049
 
5050
generate
5051
if (max_burst_width==4) begin : inst_4
5052
    always @ (posedge clk or posedge rst)
5053
    if (rst)
5054
        adr <= 4'h0;
5055
    else
5056 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
5057 83 unneback
            case (bte_i)
5058
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
5059
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
5060
            default: adr[3:0] <= to_adr + 4'd1;
5061
            endcase
5062
        else
5063
            adr <= to_adr[3:0];
5064
end
5065
endgenerate
5066
 
5067
generate
5068
if (adr_width > max_burst_width) begin : pass_through
5069
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
5070
end
5071
endgenerate
5072
 
5073
endmodule
5074 75 unneback
`endif
5075
 
5076 105 unneback
`ifdef WB_B4_EOC
5077
`define MODULE wb_b4_eoc
5078
module `BASE`MODULE ( cyc_i, stb_i, stall_o, ack_o, busy, eoc, clk, rst);
5079
`undef MODULE
5080
input cyc_i, stb_i, ack_o;
5081
output busy, eoc;
5082
input clk, rst;
5083
 
5084
`define MODULE cnt_bin_ce_rew_zq_l1
5085
`BASE`MODULE # ( .length(4), level1_value(1))
5086
cnt0 (
5087
    .cke(), .rew(), .zq(), .level1(), .rst(), clk);
5088
`undef MODULE
5089
 
5090
endmodule
5091
`endif
5092
 
5093 40 unneback
`ifdef WB3WB3_BRIDGE
5094 12 unneback
// async wb3 - wb3 bridge
5095
`timescale 1ns/1ns
5096 40 unneback
`define MODULE wb3wb3_bridge
5097
module `BASE`MODULE (
5098
`undef MODULE
5099 12 unneback
        // wishbone slave side
5100
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5101
        // wishbone master side
5102
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
5103
 
5104 95 unneback
parameter style = "FIFO"; // valid: simple, FIFO
5105
parameter addr_width = 4;
5106
 
5107 12 unneback
input [31:0] wbs_dat_i;
5108
input [31:2] wbs_adr_i;
5109
input [3:0]  wbs_sel_i;
5110
input [1:0]  wbs_bte_i;
5111
input [2:0]  wbs_cti_i;
5112
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
5113
output [31:0] wbs_dat_o;
5114 14 unneback
output wbs_ack_o;
5115 12 unneback
input wbs_clk, wbs_rst;
5116
 
5117
output [31:0] wbm_dat_o;
5118
output reg [31:2] wbm_adr_o;
5119
output [3:0]  wbm_sel_o;
5120
output reg [1:0]  wbm_bte_o;
5121
output reg [2:0]  wbm_cti_o;
5122 14 unneback
output reg wbm_we_o;
5123
output wbm_cyc_o;
5124 12 unneback
output wbm_stb_o;
5125
input [31:0]  wbm_dat_i;
5126
input wbm_ack_i;
5127
input wbm_clk, wbm_rst;
5128
 
5129
// bte
5130
parameter linear       = 2'b00;
5131
parameter wrap4        = 2'b01;
5132
parameter wrap8        = 2'b10;
5133
parameter wrap16       = 2'b11;
5134
// cti
5135
parameter classic      = 3'b000;
5136
parameter incburst     = 3'b010;
5137
parameter endofburst   = 3'b111;
5138
 
5139 95 unneback
localparam wbs_adr  = 1'b0;
5140
localparam wbs_data = 1'b1;
5141 12 unneback
 
5142 95 unneback
localparam wbm_adr0      = 2'b00;
5143
localparam wbm_adr1      = 2'b01;
5144
localparam wbm_data      = 2'b10;
5145
localparam wbm_data_wait = 2'b11;
5146 12 unneback
 
5147
reg [1:0] wbs_bte_reg;
5148
reg wbs;
5149
wire wbs_eoc_alert, wbm_eoc_alert;
5150
reg wbs_eoc, wbm_eoc;
5151
reg [1:0] wbm;
5152
 
5153 14 unneback
wire [1:16] wbs_count, wbm_count;
5154 12 unneback
 
5155
wire [35:0] a_d, a_q, b_d, b_q;
5156
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
5157
reg a_rd_reg;
5158
wire b_rd_adr, b_rd_data;
5159 14 unneback
wire b_rd_data_reg;
5160
wire [35:0] temp;
5161 12 unneback
 
5162
`define WE 5
5163
`define BTE 4:3
5164
`define CTI 2:0
5165
 
5166
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
5167
always @ (posedge wbs_clk or posedge wbs_rst)
5168
if (wbs_rst)
5169
        wbs_eoc <= 1'b0;
5170
else
5171
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
5172 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
5173 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
5174
                wbs_eoc <= 1'b1;
5175
 
5176 40 unneback
`define MODULE cnt_shreg_ce_clear
5177
`BASE`MODULE # ( .length(16))
5178
`undef MODULE
5179 12 unneback
    cnt0 (
5180
        .cke(wbs_ack_o),
5181
        .clear(wbs_eoc),
5182
        .q(wbs_count),
5183
        .rst(wbs_rst),
5184
        .clk(wbs_clk));
5185
 
5186
always @ (posedge wbs_clk or posedge wbs_rst)
5187
if (wbs_rst)
5188
        wbs <= wbs_adr;
5189
else
5190 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
5191 12 unneback
                wbs <= wbs_data;
5192
        else if (wbs_eoc & wbs_ack_o)
5193
                wbs <= wbs_adr;
5194
 
5195
// wbs FIFO
5196 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
5197
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
5198 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
5199
              1'b0;
5200
assign a_rd = !a_fifo_empty;
5201
always @ (posedge wbs_clk or posedge wbs_rst)
5202
if (wbs_rst)
5203
        a_rd_reg <= 1'b0;
5204
else
5205
        a_rd_reg <= a_rd;
5206
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
5207
 
5208
assign wbs_dat_o = a_q[35:4];
5209
 
5210
always @ (posedge wbs_clk or posedge wbs_rst)
5211
if (wbs_rst)
5212 13 unneback
        wbs_bte_reg <= 2'b00;
5213 12 unneback
else
5214 13 unneback
        wbs_bte_reg <= wbs_bte_i;
5215 12 unneback
 
5216
// wbm FIFO
5217
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
5218
always @ (posedge wbm_clk or posedge wbm_rst)
5219
if (wbm_rst)
5220
        wbm_eoc <= 1'b0;
5221
else
5222
        if (wbm==wbm_adr0 & !b_fifo_empty)
5223
                wbm_eoc <= b_q[`BTE] == linear;
5224
        else if (wbm_eoc_alert & wbm_ack_i)
5225
                wbm_eoc <= 1'b1;
5226
 
5227
always @ (posedge wbm_clk or posedge wbm_rst)
5228
if (wbm_rst)
5229
        wbm <= wbm_adr0;
5230
else
5231 33 unneback
/*
5232 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
5233
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
5234
        (wbm==wbm_adr1 & !wbm_we_o) |
5235
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
5236
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
5237 33 unneback
*/
5238
    case (wbm)
5239
    wbm_adr0:
5240
        if (!b_fifo_empty)
5241
            wbm <= wbm_adr1;
5242
    wbm_adr1:
5243
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
5244
            wbm <= wbm_data;
5245
    wbm_data:
5246
        if (wbm_ack_i & wbm_eoc)
5247
            wbm <= wbm_adr0;
5248
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
5249
            wbm <= wbm_data_wait;
5250
    wbm_data_wait:
5251
        if (!b_fifo_empty)
5252
            wbm <= wbm_data;
5253
    endcase
5254 12 unneback
 
5255
assign b_d = {wbm_dat_i,4'b1111};
5256
assign b_wr = !wbm_we_o & wbm_ack_i;
5257
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
5258
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
5259
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
5260 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
5261 12 unneback
                   1'b0;
5262
assign b_rd = b_rd_adr | b_rd_data;
5263
 
5264 40 unneback
`define MODULE dff
5265
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
5266
`undef MODULE
5267
`define MODULE dff_ce
5268
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
5269
`undef MODULE
5270 12 unneback
 
5271
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
5272
 
5273 40 unneback
`define MODULE cnt_shreg_ce_clear
5274 42 unneback
`BASE`MODULE # ( .length(16))
5275 40 unneback
`undef MODULE
5276 12 unneback
    cnt1 (
5277
        .cke(wbm_ack_i),
5278
        .clear(wbm_eoc),
5279
        .q(wbm_count),
5280
        .rst(wbm_rst),
5281
        .clk(wbm_clk));
5282
 
5283 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
5284
assign wbm_stb_o = (wbm==wbm_data);
5285 12 unneback
 
5286
always @ (posedge wbm_clk or posedge wbm_rst)
5287
if (wbm_rst)
5288
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
5289
else begin
5290
        if (wbm==wbm_adr0 & !b_fifo_empty)
5291
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
5292
        else if (wbm_eoc_alert & wbm_ack_i)
5293
                wbm_cti_o <= endofburst;
5294
end
5295
 
5296
//async_fifo_dw_simplex_top
5297 40 unneback
`define MODULE fifo_2r2w_async_simplex
5298
`BASE`MODULE
5299
`undef MODULE
5300 12 unneback
# ( .data_width(36), .addr_width(addr_width))
5301
fifo (
5302
    // a side
5303
    .a_d(a_d),
5304
    .a_wr(a_wr),
5305
    .a_fifo_full(a_fifo_full),
5306
    .a_q(a_q),
5307
    .a_rd(a_rd),
5308
    .a_fifo_empty(a_fifo_empty),
5309
    .a_clk(wbs_clk),
5310
    .a_rst(wbs_rst),
5311
    // b side
5312
    .b_d(b_d),
5313
    .b_wr(b_wr),
5314
    .b_fifo_full(b_fifo_full),
5315
    .b_q(b_q),
5316
    .b_rd(b_rd),
5317
    .b_fifo_empty(b_fifo_empty),
5318
    .b_clk(wbm_clk),
5319
    .b_rst(wbm_rst)
5320
    );
5321
 
5322
endmodule
5323 40 unneback
`undef WE
5324
`undef BTE
5325
`undef CTI
5326
`endif
5327 17 unneback
 
5328 75 unneback
`ifdef WB3AVALON_BRIDGE
5329
`define MODULE wb3avalon_bridge
5330
module `BASE`MODULE (
5331
`undef MODULE
5332
        // wishbone slave side
5333
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5334 77 unneback
        // avalon master side
5335 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
5336
 
5337 85 unneback
parameter linewrapburst = 1'b0;
5338
 
5339 75 unneback
input [31:0] wbs_dat_i;
5340
input [31:2] wbs_adr_i;
5341
input [3:0]  wbs_sel_i;
5342
input [1:0]  wbs_bte_i;
5343
input [2:0]  wbs_cti_i;
5344 83 unneback
input wbs_we_i;
5345
input wbs_cyc_i;
5346
input wbs_stb_i;
5347 75 unneback
output [31:0] wbs_dat_o;
5348
output wbs_ack_o;
5349
input wbs_clk, wbs_rst;
5350
 
5351
input [31:0] readdata;
5352
output [31:0] writedata;
5353
output [31:2] address;
5354
output [3:0]  be;
5355
output write;
5356 81 unneback
output read;
5357 75 unneback
output beginbursttransfer;
5358
output [3:0] burstcount;
5359
input readdatavalid;
5360
input waitrequest;
5361
input clk;
5362
input rst;
5363
 
5364
wire [1:0] wbm_bte_o;
5365
wire [2:0] wbm_cti_o;
5366
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
5367
reg last_cyc;
5368 79 unneback
reg [3:0] counter;
5369 82 unneback
reg read_busy;
5370 75 unneback
 
5371
always @ (posedge clk or posedge rst)
5372
if (rst)
5373
    last_cyc <= 1'b0;
5374
else
5375
    last_cyc <= wbm_cyc_o;
5376
 
5377 79 unneback
always @ (posedge clk or posedge rst)
5378
if (rst)
5379 82 unneback
    read_busy <= 1'b0;
5380 79 unneback
else
5381 82 unneback
    if (read & !waitrequest)
5382
        read_busy <= 1'b1;
5383
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
5384
        read_busy <= 1'b0;
5385
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
5386 81 unneback
 
5387 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
5388
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
5389
                    (wbm_bte_o==2'b10) ? 4'd8 :
5390 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
5391
                    4'd1;
5392 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
5393 75 unneback
 
5394 79 unneback
always @ (posedge clk or posedge rst)
5395
if (rst) begin
5396
    counter <= 4'd0;
5397
end else
5398 80 unneback
    if (wbm_we_o) begin
5399
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
5400 85 unneback
            counter <= burstcount -4'd1;
5401 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
5402
            counter <= burstcount;
5403
        end else if (!waitrequest & wbm_stb_o) begin
5404
            counter <= counter - 4'd1;
5405
        end
5406 82 unneback
    end
5407 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
5408 79 unneback
 
5409 75 unneback
`define MODULE wb3wb3_bridge
5410 77 unneback
`BASE`MODULE wbwb3inst (
5411 75 unneback
`undef MODULE
5412
    // wishbone slave side
5413
    .wbs_dat_i(wbs_dat_i),
5414
    .wbs_adr_i(wbs_adr_i),
5415
    .wbs_sel_i(wbs_sel_i),
5416
    .wbs_bte_i(wbs_bte_i),
5417
    .wbs_cti_i(wbs_cti_i),
5418
    .wbs_we_i(wbs_we_i),
5419
    .wbs_cyc_i(wbs_cyc_i),
5420
    .wbs_stb_i(wbs_stb_i),
5421
    .wbs_dat_o(wbs_dat_o),
5422
    .wbs_ack_o(wbs_ack_o),
5423
    .wbs_clk(wbs_clk),
5424
    .wbs_rst(wbs_rst),
5425
    // wishbone master side
5426
    .wbm_dat_o(writedata),
5427 78 unneback
    .wbm_adr_o(address),
5428 75 unneback
    .wbm_sel_o(be),
5429
    .wbm_bte_o(wbm_bte_o),
5430
    .wbm_cti_o(wbm_cti_o),
5431
    .wbm_we_o(wbm_we_o),
5432
    .wbm_cyc_o(wbm_cyc_o),
5433
    .wbm_stb_o(wbm_stb_o),
5434
    .wbm_dat_i(readdata),
5435
    .wbm_ack_i(wbm_ack_i),
5436
    .wbm_clk(clk),
5437
    .wbm_rst(rst));
5438
 
5439
 
5440
endmodule
5441
`endif
5442
 
5443 105 unneback
`ifdef WB_ARBITER
5444
`define MODULE wb_arbiter
5445 42 unneback
module `BASE`MODULE (
5446 40 unneback
`undef MODULE
5447 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5448 105 unneback
    wbm_dat_i, wbm_stall_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
5449 39 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5450 105 unneback
    wbs_dat_o, wbs_stall_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
5451 39 unneback
    wb_clk, wb_rst
5452
);
5453
 
5454
parameter nr_of_ports = 3;
5455
parameter adr_size = 26;
5456
parameter adr_lo   = 2;
5457
parameter dat_size = 32;
5458
parameter sel_size = dat_size/8;
5459
 
5460
localparam aw = (adr_size - adr_lo) * nr_of_ports;
5461
localparam dw = dat_size * nr_of_ports;
5462
localparam sw = sel_size * nr_of_ports;
5463
localparam cw = 3 * nr_of_ports;
5464
localparam bw = 2 * nr_of_ports;
5465
 
5466
input  [dw-1:0] wbm_dat_o;
5467
input  [aw-1:0] wbm_adr_o;
5468
input  [sw-1:0] wbm_sel_o;
5469
input  [cw-1:0] wbm_cti_o;
5470
input  [bw-1:0] wbm_bte_o;
5471
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
5472
output [dw-1:0] wbm_dat_i;
5473 105 unneback
output [nr_of_ports-1:0] wbm_stall_o, wbm_ack_i, wbm_err_i, wbm_rty_i;
5474 39 unneback
 
5475
output [dat_size-1:0] wbs_dat_i;
5476
output [adr_size-1:adr_lo] wbs_adr_i;
5477
output [sel_size-1:0] wbs_sel_i;
5478
output [2:0] wbs_cti_i;
5479
output [1:0] wbs_bte_i;
5480
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
5481
input  [dat_size-1:0] wbs_dat_o;
5482 105 unneback
input  wbs_stall_o, wbs_ack_o, wbs_err_o, wbs_rty_o;
5483 39 unneback
 
5484
input wb_clk, wb_rst;
5485
 
5486 44 unneback
reg  [nr_of_ports-1:0] select;
5487 39 unneback
wire [nr_of_ports-1:0] state;
5488
wire [nr_of_ports-1:0] eoc; // end-of-cycle
5489
wire [nr_of_ports-1:0] sel;
5490
wire idle;
5491
 
5492
genvar i;
5493
 
5494
assign idle = !(|state);
5495
 
5496
generate
5497
if (nr_of_ports == 2) begin
5498
 
5499
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
5500
 
5501
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5502
 
5503 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5504
 
5505
    always @ (idle or wbm_cyc_o)
5506
    if (idle)
5507
        casex (wbm_cyc_o)
5508
        2'b1x : select = 2'b10;
5509
        2'b01 : select = 2'b01;
5510
        default : select = {nr_of_ports{1'b0}};
5511
        endcase
5512
    else
5513
        select = {nr_of_ports{1'b0}};
5514
 
5515 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5516
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5517
 
5518
end
5519
endgenerate
5520
 
5521
generate
5522
if (nr_of_ports == 3) begin
5523
 
5524
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5525
 
5526
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5527
 
5528 44 unneback
    always @ (idle or wbm_cyc_o)
5529
    if (idle)
5530
        casex (wbm_cyc_o)
5531
        3'b1xx : select = 3'b100;
5532
        3'b01x : select = 3'b010;
5533
        3'b001 : select = 3'b001;
5534
        default : select = {nr_of_ports{1'b0}};
5535
        endcase
5536
    else
5537
        select = {nr_of_ports{1'b0}};
5538
 
5539
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5540 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5541
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5542
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5543
 
5544
end
5545
endgenerate
5546
 
5547
generate
5548 44 unneback
if (nr_of_ports == 4) begin
5549
 
5550
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5551
 
5552
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5553
 
5554
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5555
 
5556
    always @ (idle or wbm_cyc_o)
5557
    if (idle)
5558
        casex (wbm_cyc_o)
5559
        4'b1xxx : select = 4'b1000;
5560
        4'b01xx : select = 4'b0100;
5561
        4'b001x : select = 4'b0010;
5562
        4'b0001 : select = 4'b0001;
5563
        default : select = {nr_of_ports{1'b0}};
5564
        endcase
5565
    else
5566
        select = {nr_of_ports{1'b0}};
5567
 
5568
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5569
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5570
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5571
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5572
 
5573
end
5574
endgenerate
5575
 
5576
generate
5577
if (nr_of_ports == 5) begin
5578
 
5579
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5580
 
5581
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5582
 
5583
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5584
 
5585
    always @ (idle or wbm_cyc_o)
5586
    if (idle)
5587
        casex (wbm_cyc_o)
5588
        5'b1xxxx : select = 5'b10000;
5589
        5'b01xxx : select = 5'b01000;
5590
        5'b001xx : select = 5'b00100;
5591
        5'b0001x : select = 5'b00010;
5592
        5'b00001 : select = 5'b00001;
5593
        default : select = {nr_of_ports{1'b0}};
5594
        endcase
5595
    else
5596
        select = {nr_of_ports{1'b0}};
5597
 
5598
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5599
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5600
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5601
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5602
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5603
 
5604
end
5605
endgenerate
5606
 
5607
generate
5608 67 unneback
if (nr_of_ports == 6) begin
5609
 
5610
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5611
 
5612
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5613
 
5614
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5615
 
5616
    always @ (idle or wbm_cyc_o)
5617
    if (idle)
5618
        casex (wbm_cyc_o)
5619
        6'b1xxxxx : select = 6'b100000;
5620
        6'b01xxxx : select = 6'b010000;
5621
        6'b001xxx : select = 6'b001000;
5622
        6'b0001xx : select = 6'b000100;
5623
        6'b00001x : select = 6'b000010;
5624
        6'b000001 : select = 6'b000001;
5625
        default : select = {nr_of_ports{1'b0}};
5626
        endcase
5627
    else
5628
        select = {nr_of_ports{1'b0}};
5629
 
5630
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5631
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5632
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5633
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5634
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5635
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5636
 
5637
end
5638
endgenerate
5639
 
5640
generate
5641
if (nr_of_ports == 7) begin
5642
 
5643
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5644
 
5645
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5646
 
5647
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5648
 
5649
    always @ (idle or wbm_cyc_o)
5650
    if (idle)
5651
        casex (wbm_cyc_o)
5652
        7'b1xxxxxx : select = 7'b1000000;
5653
        7'b01xxxxx : select = 7'b0100000;
5654
        7'b001xxxx : select = 7'b0010000;
5655
        7'b0001xxx : select = 7'b0001000;
5656
        7'b00001xx : select = 7'b0000100;
5657
        7'b000001x : select = 7'b0000010;
5658
        7'b0000001 : select = 7'b0000001;
5659
        default : select = {nr_of_ports{1'b0}};
5660
        endcase
5661
    else
5662
        select = {nr_of_ports{1'b0}};
5663
 
5664
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5665
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5666
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5667
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5668
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5669
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5670
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5671
 
5672
end
5673
endgenerate
5674
 
5675
generate
5676
if (nr_of_ports == 8) begin
5677
 
5678
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5679
 
5680
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5681
 
5682
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5683
 
5684
    always @ (idle or wbm_cyc_o)
5685
    if (idle)
5686
        casex (wbm_cyc_o)
5687
        8'b1xxxxxxx : select = 8'b10000000;
5688
        8'b01xxxxxx : select = 8'b01000000;
5689
        8'b001xxxxx : select = 8'b00100000;
5690
        8'b0001xxxx : select = 8'b00010000;
5691
        8'b00001xxx : select = 8'b00001000;
5692
        8'b000001xx : select = 8'b00000100;
5693
        8'b0000001x : select = 8'b00000010;
5694
        8'b00000001 : select = 8'b00000001;
5695
        default : select = {nr_of_ports{1'b0}};
5696
        endcase
5697
    else
5698
        select = {nr_of_ports{1'b0}};
5699
 
5700
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
5701
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5702
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5703
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5704
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5705
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5706
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5707
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5708
 
5709
end
5710
endgenerate
5711
 
5712
generate
5713 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
5714 42 unneback
`define MODULE spr
5715
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
5716
`undef MODULE
5717 39 unneback
end
5718
endgenerate
5719
 
5720
    assign sel = select | state;
5721
 
5722 40 unneback
`define MODULE mux_andor
5723
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
5724
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
5725
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
5726
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
5727
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
5728
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
5729
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
5730
`undef MODULE
5731 39 unneback
    assign wbs_cyc_i = |sel;
5732
 
5733
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
5734
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
5735
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
5736
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
5737
 
5738
endmodule
5739 40 unneback
`endif
5740 39 unneback
 
5741 101 unneback
`ifdef WB_RAM
5742 49 unneback
// WB RAM with byte enable
5743 101 unneback
`define MODULE wb_ram
5744 59 unneback
module `BASE`MODULE (
5745
`undef MODULE
5746 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5747 101 unneback
    wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
5748 59 unneback
 
5749 101 unneback
parameter adr_width = 16;
5750
parameter mem_size = 1<<adr_width;
5751
parameter dat_width = 32;
5752
parameter max_burst_width = 4; // only used for B3
5753
parameter mode = "B3"; // valid options: B3, B4
5754 60 unneback
parameter memory_init = 1;
5755
parameter memory_file = "vl_ram.vmem";
5756 59 unneback
 
5757 101 unneback
input [dat_width-1:0] wbs_dat_i;
5758
input [adr_width-1:0] wbs_adr_i;
5759
input [2:0] wbs_cti_i;
5760
input [1:0] wbs_bte_i;
5761
input [dat_width/8-1:0] wbs_sel_i;
5762 70 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5763 101 unneback
output [dat_width-1:0] wbs_dat_o;
5764 70 unneback
output wbs_ack_o;
5765 101 unneback
output wbs_stall_o;
5766 71 unneback
input wb_clk, wb_rst;
5767 59 unneback
 
5768 101 unneback
wire [adr_width-1:0] adr;
5769
wire we;
5770 59 unneback
 
5771 101 unneback
generate
5772
if (mode=="B3") begin : B3_inst
5773 83 unneback
`define MODULE wb_adr_inc
5774 101 unneback
`BASE`MODULE # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
5775 83 unneback
    .cyc_i(wbs_cyc_i),
5776
    .stb_i(wbs_stb_i),
5777
    .cti_i(wbs_cti_i),
5778
    .bte_i(wbs_bte_i),
5779
    .adr_i(wbs_adr_i),
5780 85 unneback
    .we_i(wbs_we_i),
5781 83 unneback
    .ack_o(wbs_ack_o),
5782
    .adr_o(adr),
5783
    .clk(wb_clk),
5784
    .rst(wb_rst));
5785
`undef MODULE
5786 101 unneback
assign we = wbs_we_i & wbs_ack_o;
5787
end else if (mode=="B4") begin : B4_inst
5788
reg wbs_ack_o_reg;
5789
always @ (posedge wb_clk or posedge wb_rst)
5790
    if (wb_rst)
5791
        wbs_ack_o_reg <= 1'b0;
5792
    else
5793
        wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
5794
assign wbs_ack_o = wbs_ack_o_reg;
5795
assign wbs_stall_o = 1'b0;
5796
assign adr = wbs_adr_i;
5797
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
5798
end
5799
endgenerate
5800 60 unneback
 
5801 100 unneback
`define MODULE ram_be
5802
`BASE`MODULE # (
5803
    .data_width(dat_width),
5804
    .addr_width(adr_width),
5805
    .mem_size(mem_size),
5806
    .memory_init(memory_init),
5807
    .memory_file(memory_file))
5808
ram0(
5809
`undef MODULE
5810 101 unneback
    .d(wbs_dat_i),
5811
    .adr(adr),
5812
    .be(wbs_sel_i),
5813
    .we(we),
5814
    .q(wbs_dat_o),
5815 100 unneback
    .clk(wb_clk)
5816
);
5817 49 unneback
 
5818
endmodule
5819
`endif
5820
 
5821 103 unneback
`ifdef WB_SHADOW_RAM
5822
// A wishbone compliant RAM module that can be placed in front of other memory controllers
5823
`define MODULE wb_shadow_ram
5824
module `BASE`MODULE (
5825
`undef MODULE
5826
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5827
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
5828
    wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5829
    wbm_dat_i, wbm_ack_i, wbm_stall_i,
5830
    wb_clk, wb_rst);
5831
 
5832
parameter dat_width = 32;
5833
parameter mode = "B4";
5834
parameter max_burst_width = 4; // only used for B3
5835
 
5836
parameter shadow_mem_adr_width = 10;
5837
parameter shadow_mem_size = 1024;
5838
parameter shadow_mem_init = 2;
5839
parameter shadow_mem_file = "vl_ram.v";
5840
 
5841
parameter main_mem_adr_width = 24;
5842
 
5843
input [dat_width-1:0] wbs_dat_i;
5844
input [main_mem_adr_width-1:0] wbs_adr_i;
5845
input [2:0] wbs_cti_i;
5846
input [1:0] wbs_bte_i;
5847
input [dat_width/8-1:0] wbs_sel_i;
5848
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5849
output [dat_width-1:0] wbs_dat_o;
5850
output wbs_ack_o;
5851
output wbs_stall_o;
5852
 
5853
output [dat_width-1:0] wbm_dat_o;
5854
output [main_mem_adr_width-1:0] wbm_adr_o;
5855
output [2:0] wbm_cti_o;
5856
output [1:0] wbm_bte_o;
5857
output [dat_width/8-1:0] wbm_sel_o;
5858
output wbm_we_o, wbm_stb_o, wbm_cyc_o;
5859
input [dat_width-1:0] wbm_dat_i;
5860
input wbm_ack_i, wbm_stall_i;
5861
 
5862
input wb_clk, wb_rst;
5863
 
5864
generate
5865
if (shadow_mem_size>0) begin : shadow_ram_inst
5866
 
5867
wire cyc;
5868
wire [dat_width-1:0] dat;
5869
wire stall, ack;
5870
 
5871
assign cyc = wbs_cyc_i & (wbs_adr_i<=shadow_mem_size);
5872
`define MODULE wb_ram
5873
`BASE`MODULE # (
5874
    .dat_width(dat_width),
5875
    .adr_width(shadow_mem_adr_width),
5876
    .mem_size(shadow_mem_size),
5877
    .memory_init(shadow_mem_init),
5878
    .mode(mode))
5879
shadow_mem0 (
5880
    .wbs_dat_i(wbs_dat_i),
5881
    .wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),
5882
    .wbs_sel_i(wbs_sel_i),
5883
    .wbs_we_i (wbs_we_i),
5884
    .wbs_bte_i(wbs_bte_i),
5885
    .wbs_cti_i(wbs_cti_i),
5886
    .wbs_stb_i(wbs_stb_i),
5887
    .wbs_cyc_i(cyc),
5888
    .wbs_dat_o(dat),
5889
    .wbs_stall_o(stall),
5890
    .wbs_ack_o(ack),
5891
    .wb_clk(wb_clk),
5892
    .wb_rst(wb_rst));
5893
`undef MODULE
5894
 
5895
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o} =
5896
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i};
5897
assign wbm_cyc_o = wbs_cyc_i & (wbs_adr_i>shadow_mem_size);
5898
 
5899
assign wbs_dat_o = (dat & {dat_width{cyc}}) | (wbm_dat_i & {dat_width{wbm_cyc_o}});
5900
assign wbs_ack_o = (ack & cyc) | (wbm_ack_i & wbm_cyc_o);
5901
assign wbs_stall_o = (stall & cyc) | (wbm_stall_i & wbm_cyc_o);
5902
 
5903
end else begin : no_shadow_ram_inst
5904
 
5905
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o} =
5906
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i};
5907
assign {wbs_dat_o, wbs_ack_o, wbs_stall_o} = {wbm_dat_i, wbm_ack_i, wbm_stall_i};
5908
 
5909
end
5910
endgenerate
5911
 
5912
endmodule
5913
`endif
5914
 
5915 48 unneback
`ifdef WB_B4_ROM
5916
// WB ROM
5917
`define MODULE wb_b4_rom
5918
module `BASE`MODULE (
5919
`undef MODULE
5920
    wb_adr_i, wb_stb_i, wb_cyc_i,
5921
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
5922
 
5923
    parameter dat_width = 32;
5924
    parameter dat_default = 32'h15000000;
5925
    parameter adr_width = 32;
5926
 
5927
/*
5928
`ifndef ROM
5929
`define ROM "rom.v"
5930
`endif
5931
*/
5932
    input [adr_width-1:2]   wb_adr_i;
5933
    input                   wb_stb_i;
5934
    input                   wb_cyc_i;
5935
    output [dat_width-1:0]  wb_dat_o;
5936
    reg [dat_width-1:0]     wb_dat_o;
5937
    output                  wb_ack_o;
5938
    reg                     wb_ack_o;
5939
    output                  stall_o;
5940
    input                   wb_clk;
5941
    input                   wb_rst;
5942
 
5943
always @ (posedge wb_clk or posedge wb_rst)
5944
    if (wb_rst)
5945
        wb_dat_o <= {dat_width{1'b0}};
5946
    else
5947
         case (wb_adr_i[adr_width-1:2])
5948
`ifdef ROM
5949
`include `ROM
5950
`endif
5951
           default:
5952
             wb_dat_o <= dat_default;
5953
 
5954
         endcase // case (wb_adr_i)
5955
 
5956
 
5957
always @ (posedge wb_clk or posedge wb_rst)
5958
    if (wb_rst)
5959
        wb_ack_o <= 1'b0;
5960
    else
5961
        wb_ack_o <= wb_stb_i & wb_cyc_i;
5962
 
5963
assign stall_o = 1'b0;
5964
 
5965
endmodule
5966
`endif
5967
 
5968
 
5969 40 unneback
`ifdef WB_BOOT_ROM
5970 17 unneback
// WB ROM
5971 40 unneback
`define MODULE wb_boot_rom
5972
module `BASE`MODULE (
5973
`undef MODULE
5974 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
5975 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
5976 17 unneback
 
5977 18 unneback
    parameter adr_hi = 31;
5978
    parameter adr_lo = 28;
5979
    parameter adr_sel = 4'hf;
5980
    parameter addr_width = 5;
5981 33 unneback
/*
5982 17 unneback
`ifndef BOOT_ROM
5983
`define BOOT_ROM "boot_rom.v"
5984
`endif
5985 33 unneback
*/
5986 18 unneback
    input [adr_hi:2]    wb_adr_i;
5987
    input               wb_stb_i;
5988
    input               wb_cyc_i;
5989
    output [31:0]        wb_dat_o;
5990
    output              wb_ack_o;
5991
    output              hit_o;
5992
    input               wb_clk;
5993
    input               wb_rst;
5994
 
5995
    wire hit;
5996
    reg [31:0] wb_dat;
5997
    reg wb_ack;
5998
 
5999
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
6000 17 unneback
 
6001
always @ (posedge wb_clk or posedge wb_rst)
6002
    if (wb_rst)
6003 18 unneback
        wb_dat <= 32'h15000000;
6004 17 unneback
    else
6005 18 unneback
         case (wb_adr_i[addr_width-1:2])
6006 33 unneback
`ifdef BOOT_ROM
6007 17 unneback
`include `BOOT_ROM
6008 33 unneback
`endif
6009 17 unneback
           /*
6010
            // Zero r0 and jump to 0x00000100
6011 18 unneback
 
6012
            1 : wb_dat <= 32'hA8200000;
6013
            2 : wb_dat <= 32'hA8C00100;
6014
            3 : wb_dat <= 32'h44003000;
6015
            4 : wb_dat <= 32'h15000000;
6016 17 unneback
            */
6017
           default:
6018 18 unneback
             wb_dat <= 32'h00000000;
6019 17 unneback
 
6020
         endcase // case (wb_adr_i)
6021
 
6022
 
6023
always @ (posedge wb_clk or posedge wb_rst)
6024
    if (wb_rst)
6025 18 unneback
        wb_ack <= 1'b0;
6026 17 unneback
    else
6027 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
6028 17 unneback
 
6029 18 unneback
assign hit_o = hit;
6030
assign wb_dat_o = wb_dat & {32{wb_ack}};
6031
assign wb_ack_o = wb_ack;
6032
 
6033 17 unneback
endmodule
6034 40 unneback
`endif
6035 32 unneback
 
6036 106 unneback
`ifdef WB_DPRAM
6037
`define MODULE wb_dpram
6038 40 unneback
module `BASE`MODULE (
6039
`undef MODULE
6040 32 unneback
        // wishbone slave side a
6041 106 unneback
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, wbsa_stall_o,
6042 32 unneback
        wbsa_clk, wbsa_rst,
6043 92 unneback
        // wishbone slave side b
6044 106 unneback
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, wbsb_stall_o,
6045 32 unneback
        wbsb_clk, wbsb_rst);
6046
 
6047 92 unneback
parameter data_width_a = 32;
6048
parameter data_width_b = data_width_a;
6049
parameter addr_width_a = 8;
6050
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
6051 101 unneback
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
6052 92 unneback
parameter max_burst_width_a = 4;
6053
parameter max_burst_width_b = max_burst_width_a;
6054 101 unneback
parameter mode = "B3";
6055 109 unneback
parameter memory_init = 0;
6056
parameter memory_file = "vl_ram.v";
6057 92 unneback
input [data_width_a-1:0] wbsa_dat_i;
6058
input [addr_width_a-1:0] wbsa_adr_i;
6059
input [data_width_a/8-1:0] wbsa_sel_i;
6060
input [2:0] wbsa_cti_i;
6061
input [1:0] wbsa_bte_i;
6062 32 unneback
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
6063 92 unneback
output [data_width_a-1:0] wbsa_dat_o;
6064 109 unneback
output wbsa_ack_o;
6065 106 unneback
output wbsa_stall_o;
6066 32 unneback
input wbsa_clk, wbsa_rst;
6067
 
6068 92 unneback
input [data_width_b-1:0] wbsb_dat_i;
6069
input [addr_width_b-1:0] wbsb_adr_i;
6070
input [data_width_b/8-1:0] wbsb_sel_i;
6071
input [2:0] wbsb_cti_i;
6072
input [1:0] wbsb_bte_i;
6073 32 unneback
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
6074 92 unneback
output [data_width_b-1:0] wbsb_dat_o;
6075 109 unneback
output wbsb_ack_o;
6076 106 unneback
output wbsb_stall_o;
6077 32 unneback
input wbsb_clk, wbsb_rst;
6078
 
6079 92 unneback
wire [addr_width_a-1:0] adr_a;
6080
wire [addr_width_b-1:0] adr_b;
6081 101 unneback
wire we_a, we_b;
6082
generate
6083
if (mode=="B3") begin : b3_inst
6084 92 unneback
`define MODULE wb_adr_inc
6085
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
6086
    .cyc_i(wbsa_cyc_i),
6087
    .stb_i(wbsa_stb_i),
6088
    .cti_i(wbsa_cti_i),
6089
    .bte_i(wbsa_bte_i),
6090
    .adr_i(wbsa_adr_i),
6091
    .we_i(wbsa_we_i),
6092
    .ack_o(wbsa_ack_o),
6093
    .adr_o(adr_a),
6094
    .clk(wbsa_clk),
6095
    .rst(wbsa_rst));
6096 101 unneback
assign we_a = wbsa_we_i & wbsa_ack_o;
6097 92 unneback
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
6098
    .cyc_i(wbsb_cyc_i),
6099
    .stb_i(wbsb_stb_i),
6100
    .cti_i(wbsb_cti_i),
6101
    .bte_i(wbsb_bte_i),
6102
    .adr_i(wbsb_adr_i),
6103
    .we_i(wbsb_we_i),
6104
    .ack_o(wbsb_ack_o),
6105
    .adr_o(adr_b),
6106
    .clk(wbsb_clk),
6107
    .rst(wbsb_rst));
6108 40 unneback
`undef MODULE
6109 101 unneback
assign we_b = wbsb_we_i & wbsb_ack_o;
6110
end else if (mode=="B4") begin : b4_inst
6111 109 unneback
`define MODULE dff
6112
`BASE`MODULE dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
6113 101 unneback
assign wbsa_stall_o = 1'b0;
6114
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
6115 109 unneback
`BASE`MODULE dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
6116
`undef MODULE
6117 101 unneback
assign wbsb_stall_o = 1'b0;
6118
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
6119
end
6120
endgenerate
6121 92 unneback
 
6122
`define MODULE dpram_be_2r2w
6123 109 unneback
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
6124 110 unneback
                 .b_data_width(data_width_b),
6125 109 unneback
                 .memory_init(memory_init), .memory_file(memory_file))
6126 92 unneback
`undef MODULE
6127
ram_i (
6128 32 unneback
    .d_a(wbsa_dat_i),
6129 92 unneback
    .q_a(wbsa_dat_o),
6130
    .adr_a(adr_a),
6131
    .be_a(wbsa_sel_i),
6132 101 unneback
    .we_a(we_a),
6133 32 unneback
    .clk_a(wbsa_clk),
6134
    .d_b(wbsb_dat_i),
6135 92 unneback
    .q_b(wbsb_dat_o),
6136
    .adr_b(adr_b),
6137
    .be_b(wbsb_sel_i),
6138 101 unneback
    .we_b(we_b),
6139 32 unneback
    .clk_b(wbsb_clk) );
6140
 
6141
endmodule
6142 40 unneback
`endif
6143 94 unneback
 
6144 101 unneback
`ifdef WB_CACHE
6145
`define MODULE wb_cache
6146 97 unneback
module `BASE`MODULE (
6147 103 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
6148 98 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
6149 97 unneback
);
6150
`undef MODULE
6151
 
6152
parameter dw_s = 32;
6153
parameter aw_s = 24;
6154
parameter dw_m = dw_s;
6155 100 unneback
localparam aw_m = dw_s * aw_s / dw_m;
6156
parameter wbs_max_burst_width = 4;
6157 103 unneback
parameter wbs_mode = "B3";
6158 97 unneback
 
6159
parameter async = 1; // wbs_clk != wbm_clk
6160
 
6161
parameter nr_of_ways = 1;
6162
parameter aw_offset = 4; // 4 => 16 words per cache line
6163
parameter aw_slot = 10;
6164 100 unneback
 
6165
parameter valid_mem = 0;
6166
parameter debug = 0;
6167
 
6168
localparam aw_b_offset = aw_offset * dw_s / dw_m;
6169 98 unneback
localparam aw_tag = aw_s - aw_slot - aw_offset;
6170 97 unneback
parameter wbm_burst_size = 4; // valid options 4,8,16
6171 98 unneback
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
6172 97 unneback
`define SIZE2WIDTH wbm_burst_size
6173
localparam wbm_burst_width `SIZE2WIDTH_EXPR
6174
`undef SIZE2WIDTH
6175
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
6176
`define SIZE2WIDTH nr_of_wbm_burst
6177
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
6178
`undef SIZE2WIDTH
6179 100 unneback
 
6180 97 unneback
input [dw_s-1:0] wbs_dat_i;
6181
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
6182 98 unneback
input [dw_s/8-1:0] wbs_sel_i;
6183 97 unneback
input [2:0] wbs_cti_i;
6184
input [1:0] wbs_bte_i;
6185 98 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
6186 97 unneback
output [dw_s-1:0] wbs_dat_o;
6187
output wbs_ack_o;
6188 103 unneback
output wbs_stall_o;
6189 97 unneback
input wbs_clk, wbs_rst;
6190
 
6191
output [dw_m-1:0] wbm_dat_o;
6192
output [aw_m-1:0] wbm_adr_o;
6193
output [dw_m/8-1:0] wbm_sel_o;
6194
output [2:0] wbm_cti_o;
6195
output [1:0] wbm_bte_o;
6196 98 unneback
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
6197 97 unneback
input [dw_m-1:0] wbm_dat_i;
6198
input wbm_ack_i;
6199
input wbm_stall_i;
6200
input wbm_clk, wbm_rst;
6201
 
6202 100 unneback
wire valid, dirty, hit;
6203 97 unneback
wire [aw_tag-1:0] tag;
6204
wire tag_mem_we;
6205
wire [aw_tag-1:0] wbs_adr_tag;
6206
wire [aw_slot-1:0] wbs_adr_slot;
6207 98 unneback
wire [aw_offset-1:0] wbs_adr_word;
6208
wire [aw_s-1:0] wbs_adr;
6209 97 unneback
 
6210
reg [1:0] state;
6211
localparam idle = 2'h0;
6212
localparam rdwr = 2'h1;
6213
localparam push = 2'h2;
6214
localparam pull = 2'h3;
6215
wire eoc;
6216 103 unneback
wire we;
6217 97 unneback
 
6218
// cdc
6219
wire done, mem_alert, mem_done;
6220
 
6221 98 unneback
// wbm side
6222
reg [aw_m-1:0] wbm_radr;
6223
reg [aw_m-1:0] wbm_wadr;
6224 100 unneback
wire [aw_slot-1:0] wbm_adr;
6225 98 unneback
wire wbm_radr_cke, wbm_wadr_cke;
6226
 
6227 100 unneback
reg [2:0] phase;
6228
// phase = {we,stb,cyc}
6229
localparam wbm_wait     = 3'b000;
6230
localparam wbm_wr       = 3'b111;
6231
localparam wbm_wr_drain = 3'b101;
6232
localparam wbm_rd       = 3'b011;
6233
localparam wbm_rd_drain = 3'b001;
6234 98 unneback
 
6235 97 unneback
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
6236
 
6237 100 unneback
generate
6238
if (valid_mem==0) begin : no_valid_mem
6239
assign valid = 1'b1;
6240
end else begin : valid_mem_inst
6241
`define MODULE dpram_1r1w
6242 97 unneback
`BASE`MODULE
6243 100 unneback
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6244
    valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6245
                .q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6246 97 unneback
`undef MODULE
6247 100 unneback
end
6248
endgenerate
6249 97 unneback
 
6250 100 unneback
`define MODULE dpram_1r1w
6251
`BASE`MODULE
6252
    # ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6253
    tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6254
              .q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6255
assign hit = wbs_adr_tag == tag;
6256
`undef MODULE
6257
 
6258
`define MODULE dpram_1r2w
6259
`BASE`MODULE
6260
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6261
    dirty_mem (
6262
        .d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
6263
        .d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
6264
`undef MODULE
6265
 
6266 103 unneback
generate
6267
if (wbs_mode=="B3") begin : inst_b3
6268 97 unneback
`define MODULE wb_adr_inc
6269 100 unneback
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
6270
    .cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
6271
    .stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
6272 97 unneback
    .cti_i(wbs_cti_i),
6273
    .bte_i(wbs_bte_i),
6274
    .adr_i(wbs_adr_i),
6275
    .we_i (wbs_we_i),
6276
    .ack_o(wbs_ack_o),
6277
    .adr_o(wbs_adr),
6278 100 unneback
    .clk(wbs_clk),
6279
    .rst(wbs_rst));
6280 97 unneback
`undef MODULE
6281 103 unneback
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
6282
assign we = wbs_cyc_i &  wbs_we_i & wbs_ack_o;
6283
end else if (wbs_mode=="B4") begin : inst_b4
6284
end
6285 97 unneback
 
6286 103 unneback
endgenerate
6287
 
6288 97 unneback
`define MODULE dpram_be_2r2w
6289
`BASE`MODULE
6290 100 unneback
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
6291 103 unneback
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
6292 100 unneback
                .d_b(wbm_dat_i), .adr_b(wbm_adr_o[aw_slot+aw_offset-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
6293 97 unneback
`undef MODULE
6294
 
6295
always @ (posedge wbs_clk or posedge wbs_rst)
6296
if (wbs_rst)
6297 98 unneback
    state <= idle;
6298 97 unneback
else
6299
    case (state)
6300
    idle:
6301
        if (wbs_cyc_i)
6302
            state <= rdwr;
6303
    rdwr:
6304 100 unneback
        casex ({valid, hit, dirty, eoc})
6305
        4'b0xxx: state <= pull;
6306
        4'b11x1: state <= idle;
6307
        4'b101x: state <= push;
6308
        4'b100x: state <= pull;
6309
        endcase
6310 97 unneback
    push:
6311
        if (done)
6312
            state <= rdwr;
6313
    pull:
6314
        if (done)
6315
            state <= rdwr;
6316
    default: state <= idle;
6317
    endcase
6318
 
6319
// cdc
6320
generate
6321
if (async==1) begin : cdc0
6322
`define MODULE cdc
6323 100 unneback
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
6324 97 unneback
`undef MODULE
6325
end
6326
else begin : nocdc
6327 100 unneback
    assign mem_alert = state==rdwr & (!valid | !hit);
6328 97 unneback
    assign done = mem_done;
6329
end
6330
endgenerate
6331
 
6332
// FSM generating a number of burts 4 cycles
6333
// actual number depends on data width ratio
6334
// nr_of_wbm_burst
6335 101 unneback
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0]       cnt_rw, cnt_ack;
6336 97 unneback
 
6337
always @ (posedge wbm_clk or posedge wbm_rst)
6338
if (wbm_rst)
6339 100 unneback
    cnt_rw <= {wbm_burst_width{1'b0}};
6340 97 unneback
else
6341 100 unneback
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
6342
        cnt_rw <= cnt_rw + 1;
6343 97 unneback
 
6344 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6345
if (wbm_rst)
6346 100 unneback
    cnt_ack <= {wbm_burst_width{1'b0}};
6347 98 unneback
else
6348 100 unneback
    if (wbm_ack_i)
6349
        cnt_ack <= cnt_ack + 1;
6350 97 unneback
 
6351 100 unneback
generate
6352 101 unneback
if (nr_of_wbm_burst==1) begin : one_burst
6353 100 unneback
 
6354 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6355
if (wbm_rst)
6356
    phase <= wbm_wait;
6357
else
6358
    case (phase)
6359
    wbm_wait:
6360
        if (mem_alert)
6361 100 unneback
            if (state==push)
6362
                phase <= wbm_wr;
6363
            else
6364
                phase <= wbm_rd;
6365 98 unneback
    wbm_wr:
6366 100 unneback
        if (&cnt_rw)
6367
            phase <= wbm_wr_drain;
6368
    wbm_wr_drain:
6369
        if (&cnt_ack)
6370 98 unneback
            phase <= wbm_rd;
6371
    wbm_rd:
6372 100 unneback
        if (&cnt_rw)
6373
            phase <= wbm_rd_drain;
6374
    wbm_rd_drain:
6375
        if (&cnt_ack)
6376
            phase <= wbm_wait;
6377 98 unneback
    default: phase <= wbm_wait;
6378
    endcase
6379
 
6380 100 unneback
end else begin : multiple_burst
6381
 
6382 101 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6383
if (wbm_rst)
6384
    phase <= wbm_wait;
6385
else
6386
    case (phase)
6387
    wbm_wait:
6388
        if (mem_alert)
6389
            if (state==push)
6390
                phase <= wbm_wr;
6391
            else
6392
                phase <= wbm_rd;
6393
    wbm_wr:
6394
        if (&cnt_rw[wbm_burst_width-1:0])
6395
            phase <= wbm_wr_drain;
6396
    wbm_wr_drain:
6397
        if (&cnt_ack)
6398
            phase <= wbm_rd;
6399
        else if (&cnt_ack[wbm_burst_width-1:0])
6400
            phase <= wbm_wr;
6401
    wbm_rd:
6402
        if (&cnt_rw[wbm_burst_width-1:0])
6403
            phase <= wbm_rd_drain;
6404
    wbm_rd_drain:
6405
        if (&cnt_ack)
6406
            phase <= wbm_wait;
6407
        else if (&cnt_ack[wbm_burst_width-1:0])
6408
            phase <= wbm_rd;
6409
    default: phase <= wbm_wait;
6410
    endcase
6411 100 unneback
 
6412 101 unneback
 
6413 100 unneback
end
6414
endgenerate
6415
 
6416 101 unneback
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
6417 100 unneback
 
6418
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
6419
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
6420
assign wbm_sel_o = {dw_m/8{1'b1}};
6421
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
6422 98 unneback
assign wbm_bte_o = bte;
6423 100 unneback
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
6424 98 unneback
 
6425 97 unneback
endmodule
6426
`endif
6427 103 unneback
 
6428
`ifdef WB_AVALON_BRIDGE
6429
// Wishbone to avalon bridge supporting one type of burst transfer only
6430
// intended use is together with cache above
6431
// WB B4 -> pipelined avalon
6432
`define MODULE wb_avalon_bridge
6433
module `BASE`MODULE (
6434
`undef MODULE
6435
        // wishbone slave side
6436
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
6437
        // avalon master side
6438
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
6439
        // common
6440
        clk, rst);
6441
 
6442
parameter adr_width = 30;
6443
parameter dat_width = 32;
6444
parameter burst_size = 4;
6445
 
6446
input [dat_width-1:0] wbs_dat_i;
6447
input [adr_width-1:0] wbs_adr_i;
6448
input [dat_width/8-1:0]  wbs_sel_i;
6449
input [1:0]  wbs_bte_i;
6450
input [2:0]  wbs_cti_i;
6451
input wbs_we_i;
6452
input wbs_cyc_i;
6453
input wbs_stb_i;
6454
output [dat_width:0] wbs_dat_o;
6455
output wbs_ack_o;
6456
output wbs_stall_o;
6457
 
6458
input [dat_width-1:0] readdata;
6459
input readdatavalid;
6460
output [dat_width-1:0] writedata;
6461
output [adr_width-1:0] address;
6462
output [dat_width/8-1:0]  be;
6463
output write;
6464
output read;
6465
output beginbursttransfer;
6466
output [3:0] burstcount;
6467
input waitrequest;
6468
input clk, rst;
6469
 
6470
reg last_cyc_idle_or_eoc;
6471
 
6472
reg [3:0] cnt;
6473
always @ (posedge clk or posedge rst)
6474
if (rst)
6475
    cnt <= 4'h0;
6476
else
6477
    if (beginbursttransfer & waitrequest)
6478
        cnt <= burst_size - 1;
6479
    else if (beginbursttransfer & !waitrequest)
6480
        cnt <= burst_size - 2;
6481
    else if (wbs_ack_o)
6482
        cnt <= cnt - 1;
6483
 
6484
reg wr_ack;
6485
always @ (posedge clk or posedge rst)
6486
if (rst)
6487
    wr_ack <= 1'b0;
6488
else
6489
    wr_ack <=  (wbs_we_i & wbs_cyc_i & wbs_stb_i & !wbs_stall_o);
6490
 
6491
// to avalon
6492
assign writedata = wbs_dat_i;
6493
assign address = wbs_adr_i;
6494
assign be = wbs_sel_i;
6495
assign write = cnt==(burst_size-1) & wbs_cyc_i &  wbs_we_i;
6496
assign read  = cnt==(burst_size-1) & wbs_cyc_i & !wbs_we_i;
6497
assign beginbursttransfer = cnt==4'h0 & wbs_cyc_i;
6498
assign burstcount = burst_size;
6499
 
6500
// to wishbone
6501
assign wbs_dat_o = readdata;
6502
assign wbs_ack_o = wr_ack | readdatavalid;
6503
assign wbs_stall_o = waitrequest;
6504
 
6505
endmodule
6506
`endif
6507
 
6508
`ifdef WB_AVALON_MEM_CACHE
6509
`define MODULE wb_avalon_mem_cache
6510
module `BASE`MODULE (
6511
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
6512
    readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst
6513
);
6514
`undef MODULE
6515
 
6516
// wishbone
6517
parameter wb_dat_width = 32;
6518
parameter wb_adr_width = 22;
6519
parameter wb_max_burst_width = 4;
6520
parameter wb_mode = "B4";
6521
// avalon
6522
parameter avalon_dat_width = 32;
6523
localparam avalon_adr_width = wb_dat_width * wb_adr_width / avalon_dat_width;
6524
parameter avalon_burst_size = 4;
6525
// cache
6526
parameter async = 1;
6527
parameter nr_of_ways = 1;
6528
parameter aw_offset = 4;
6529
parameter aw_slot = 10;
6530
parameter valid_mem = 1;
6531
// shadow RAM
6532
parameter shadow_ram = 0;
6533
parameter shadow_ram_adr_width = 10;
6534
parameter shadow_ram_size = 1024;
6535
parameter shadow_ram_init = 2; // 0: no init, 1: from file, 2: with zero
6536
parameter shadow_ram_file = "vl_ram.v";
6537
 
6538
input [wb_dat_width-1:0] wbs_dat_i;
6539
input [wb_adr_width-1:0] wbs_adr_i; // dont include a1,a0
6540
input [wb_dat_width/8-1:0] wbs_sel_i;
6541
input [2:0] wbs_cti_i;
6542
input [1:0] wbs_bte_i;
6543
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
6544
output [wb_dat_width-1:0] wbs_dat_o;
6545
output wbs_ack_o;
6546
output wbs_stall_o;
6547
input wbs_clk, wbs_rst;
6548
 
6549
input [avalon_dat_width-1:0] readdata;
6550
input readdatavalid;
6551
output [avalon_dat_width-1:0] writedata;
6552
output [avalon_adr_width-1:0] address;
6553
output [avalon_dat_width/8-1:0]  be;
6554
output write;
6555
output read;
6556
output beginbursttransfer;
6557
output [3:0] burstcount;
6558
input waitrequest;
6559
input clk, rst;
6560
 
6561
`define DAT_WIDTH wb_dat_width
6562
`define ADR_WIDTH wb_adr_width
6563
`define WB wb1
6564
`include "wb_wires.v"
6565
`define WB wb2
6566
`include "wb_wires.v"
6567
`undef DAT_WIDTH
6568
`undef ADR_WIDTH
6569
 
6570
`define MODULE wb_shadow_ram
6571
`BASE`MODULE # ( .dat_width(wb_dat_width), .mode(wb_mode), .max_burst_width(wb_max_burst_width),
6572
                 .shadow_mem_adr_width(shadow_ram_adr_width), .shadow_mem_size(shadow_ram_adr_width), .shadow_mem_init(shadow_ram_init), .shadow_mem_file(shadow_ram_file),
6573
                 .main_mem_adr_width(wb_adr_width))
6574
shadow_ram0 (
6575
    .wbs_dat_i(wbs_dat_i), .wbs_adr_i(wbs_adr_i), .wbs_cti_i(wbs_cti_i), .wbs_bte_i(wbs_bte_i), .wbs_sel_i(wbs_sel_i), .wbs_we_i(wbs_we_i), .wbs_stb_i(wbs_stb_i), .wbs_cyc_i(wbs_cyc_i),
6576
    .wbs_dat_o(wbs_dat_o), .wbs_ack_o(wbs_ack_o), .wbs_stall_o(wbs_stall_o),
6577
    .wbm_dat_o(wb1_dat_o), .wbm_adr_o(wb1_adr_o), .wbm_cti_o(wb1_cti_o), .wbm_bte_o(wb1_bte_o), .wbm_sel_o(wb1_sel_o), .wbm_we_o(wb1_we_o), .wbm_stb_o(wb1_stb_o), .wbm_cyc_o(wb1_cyc_o),
6578
    .wbm_dat_i(wb1_dat_i), .wbm_ack_i(wb1_ack_i), .wbm_stall_i(wb1_stall_i),
6579
    .wb_clk(wbs_clk), .wb_rst(wbs_rst));
6580
`undef MODULE
6581
 
6582
`define MODULE wb_cache
6583
`BASE`MODULE
6584
# ( .dw_s(wb_dat_width), .aw_s(wb_adr_width), .dw_m(avalon_dat_width), .wbs_mode(wb_mode), .wbs_max_burst_width(wb_max_burst_width), .async(async), .nr_of_ways(nr_of_ways), .aw_offset(aw_offset), .aw_slot(aw_slot), .valid_mem(valid_mem))
6585
cache0 (
6586
    .wbs_dat_i(wb1_dat_o), .wbs_adr_i(wb1_adr_o), .wbs_sel_i(wb1_sel_o), .wbs_cti_i(wb1_cti_o), .wbs_bte_i(wb1_bte_o), .wbs_we_i(wb1_we_o), .wbs_stb_i(wb1_stb_o), .wbs_cyc_i(wb1_cyc_o),
6587
    .wbs_dat_o(wb1_dat_i), .wbs_ack_o(wb1_ack_i), .wbs_stall_o(wb1_stall_i), .wbs_clk(wbs_clk), .wbs_rst(wbs_rst),
6588
    .wbm_dat_o(wb2_dat_o), .wbm_adr_o(wb2_adr_o), .wbm_sel_o(wb2_sel_o), .wbm_cti_o(wb2_cti_o), .wbm_bte_o(wb2_bte_o), .wbm_we_o(wb2_we_o), .wbm_stb_o(wb2_stb_o), .wbm_cyc_o(wb2_cyc_o),
6589
    .wbm_dat_i(wb2_dat_i), .wbm_ack_i(wb2_ack_i), .wbm_stall_i(wb2_stall_i), .wbm_clk(clk), .wbm_rst(rst));
6590
`undef MODULE
6591
 
6592
`define MODULE wb_avalon_bridge
6593
`BASE`MODULE # ( .adr_width(avalon_adr_width), .dat_width(avalon_dat_width), .burst_size(avalon_burst_size))
6594
bridge0 (
6595
        // wishbone slave side
6596
        .wbs_dat_i(wb2_dat_o), .wbs_adr_i(wb2_adr_o), .wbs_sel_i(wb2_sel_o), .wbs_bte_i(wb2_bte_o), .wbs_cti_i(wb2_cti_o), .wbs_we_i(wb2_we_o), .wbs_cyc_i(wb2_cyc_o), .wbs_stb_i(wb2_stb_o),
6597
        .wbs_dat_o(wb2_dat_i), .wbs_ack_o(wb2_ack_i), .wbs_stall_o(wb2_stall_i),
6598
        // avalon master side
6599
        .readdata(readdata), .readdatavalid(readdatavalid), .address(address), .read(read), .be(be), .write(write), .burstcount(burstcount), .writedata(writedata), .waitrequest(waitrequest), .beginbursttransfer(beginbursttransfer),
6600
        // common
6601
        .clk(clk), .rst(rst));
6602
`undef MODULE
6603
 
6604
endmodule
6605
`endif
6606 105 unneback
 
6607
`ifdef WB_SDR_SDRAM
6608
`define MODULE wb_sdr_sdram
6609
module `BASE`MODULE (
6610
`undef MODULE
6611
    // wisbone i/f
6612
    dat_i, adr_i, sel_i, we_i, cyc_i, stb_i, dat_o, ack_o, stall_o
6613
    // SDR SDRAM
6614
    ba, a, cmd, cke, cs_n, dqm, dq_i, dq_o, dq_oe,
6615
    // system
6616
    clk, rst);
6617
 
6618
    // external data bus size
6619
    parameter dat_size = 16;
6620
    // memory geometry parameters
6621
    parameter ba_size  = `SDR_BA_SIZE;
6622
    parameter row_size = `SDR_ROW_SIZE;
6623
    parameter col_size = `SDR_COL_SIZE;
6624
    parameter cl = 2;
6625
    // memory timing parameters
6626
    parameter tRFC = 9;
6627
    parameter tRP  = 2;
6628
    parameter tRCD = 2;
6629
    parameter tMRD = 2;
6630
 
6631
    // LMR
6632
    // [12:10] reserved
6633
    // [9]     WB, write burst; 0 - programmed burst length, 1 - single location
6634
    // [8:7]   OP Mode, 2'b00
6635
    // [6:4]   CAS Latency; 3'b010 - 2, 3'b011 - 3
6636
    // [3]     BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
6637
    // [2:0]   Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
6638
    localparam init_wb = 1'b1;
6639
    localparam init_cl = (cl==2) ? 3'b010 : 3'b011;
6640
    localparam init_bt = 1'b0;
6641
    localparam init_bl = 3'b000;
6642
 
6643
    input [dat_size:0] dat_i;
6644
    input [ba_size+col_size+row_size-1:0] adr_i;
6645
    input [dat_size/8-1:0] sel_i;
6646
    input we_i, cyc_i, stb_i;
6647
    output [dat_size-1:0] dat_o;
6648
    output ack_o;
6649
    output reg stall_o;
6650
 
6651
    output [ba_size-1:0]    ba;
6652
    output reg [12:0]   a;
6653
    output reg [2:0]    cmd; // {ras,cas,we}
6654
    output cke, cs_n;
6655
    output reg [dat_size/8-1:0]    dqm;
6656
    output [dat_size-1:0]       dq_o;
6657
    output reg          dq_oe;
6658
    input  [dat_size-1:0]       dq_i;
6659
 
6660
    input clk, rst;
6661
 
6662
    wire [ba_size-1:0]   bank;
6663
    wire [row_size-1:0] row;
6664
    wire [col_size-1:0] col;
6665
    wire [0:31]  shreg;
6666
    wire                ref_cnt_zero;
6667
    reg                 refresh_req;
6668
 
6669
    wire ack_rd, rd_ack_emptyflag;
6670
    wire ack_wr;
6671
 
6672
    // to keep track of open rows per bank
6673
    reg [row_size-1:0]   open_row[0:3];
6674
    reg [0:3]            open_ba;
6675
    reg                 current_bank_closed, current_row_open;
6676
 
6677
    parameter rfr_length = 10;
6678
    parameter rfr_wrap_value = 1010;
6679
 
6680
    parameter [2:0] cmd_nop = 3'b111,
6681
                    cmd_act = 3'b011,
6682
                    cmd_rd  = 3'b101,
6683
                    cmd_wr  = 3'b100,
6684
                    cmd_pch = 3'b010,
6685
                    cmd_rfr = 3'b001,
6686
                    cmd_lmr = 3'b000;
6687
 
6688
// ctrl FSM
6689
`define FSM_INIT 3'b000
6690
`define FSM_IDLE 3'b001
6691
`define FSM_RFR  3'b010
6692
`define FSM_ADR  3'b011
6693
`define FSM_PCH  3'b100
6694
`define FSM_ACT  3'b101
6695
`define FSM_RW   3'b111
6696
 
6697
    assign cke = 1'b1;
6698
    assign cs_n = 1'b0;
6699
 
6700
    reg [2:0] state, next;
6701
 
6702
    function [12:0] a10_fix;
6703
        input [col_size-1:0] a;
6704
        integer i;
6705
    begin
6706
        for (i=0;i<13;i=i+1) begin
6707
            if (i<10)
6708
              if (i<col_size)
6709
                a10_fix[i] = a[i];
6710
              else
6711
                a10_fix[i] = 1'b0;
6712
            else if (i==10)
6713
              a10_fix[i] = 1'b0;
6714
            else
6715
              if (i<col_size)
6716
                a10_fix[i] = a[i-1];
6717
              else
6718
                a10_fix[i] = 1'b0;
6719
        end
6720
    end
6721
    endfunction
6722
 
6723
    assign {bank,row,col} = adr_i;
6724
 
6725
    always @ (posedge clk or posedge rst)
6726
    if (rst)
6727
       state <= `FSM_INIT;
6728
    else
6729
       state <= next;
6730
 
6731
    always @*
6732
    begin
6733
        next = state;
6734
        case (state)
6735
        `FSM_INIT:
6736
            if (shreg[3+tRP+tRFC+tRFC+tMRD]) next = `FSM_IDLE;
6737
        `FSM_IDLE:
6738
            if (refresh_req) next = `FSM_RFR;
6739
            else if (cyc_i & stb_i & rd_ack_emptyflag) next = `FSM_ADR;
6740
        `FSM_RFR:
6741
            if (shreg[tRP+tRFC-2]) next = `FSM_IDLE; // take away two cycles because no cmd will be issued in idle and adr
6742
        `FSM_ADR:
6743
            if (current_bank_closed) next = `FSM_ACT;
6744
            else if (current_row_open) next = `FSM_RW;
6745
            else next = `FSM_PCH;
6746
        `FSM_PCH:
6747
            if (shreg[tRP]) next = `FSM_ACT;
6748
        `FSM_ACT:
6749
            if (shreg[tRCD]) next = `FSM_RW;
6750
        `FSM_RW:
6751
            if (!stb_i) next = `FSM_IDLE;
6752
        endcase
6753
    end
6754
 
6755
    // counter
6756
`define MODULE cnt_shreg_ce_clear
6757
    `VLBASE`MODULE # ( .length(32))
6758
`undef MODULE
6759
        cnt0 (
6760
            .clear(state!=next),
6761
            .q(shreg),
6762
            .rst(rst),
6763
            .clk(clk));
6764
 
6765
    // ba, a, cmd
6766
    // outputs dependent on state vector
6767
    always @ (*)
6768
        begin
6769
            {a,cmd} = {13'd0,cmd_nop};
6770
            dqm = 2'b11;
6771
            dq_oe = 1'b0;
6772
            stall_o = 1'b1;
6773
            case (state)
6774
            `FSM_INIT:
6775
                if (shreg[3]) begin
6776
                    {a,cmd} = {13'b0010000000000, cmd_pch};
6777
                end else if (shreg[3+tRP] | shreg[3+tRP+tRFC])
6778
                    {a,cmd} = {13'd0, cmd_rfr};
6779
                else if (shreg[3+tRP+tRFC+tRFC])
6780
                    {a,cmd} = {3'b000,init_wb,2'b00,init_cl,init_bt,init_bl,cmd_lmr};
6781
            `FSM_RFR:
6782
                if (shreg[0])
6783
                    {a,cmd} = {13'b0010000000000, cmd_pch};
6784
                else if (shreg[tRP])
6785
                    {a,cmd} = {13'd0, cmd_rfr};
6786
            `FSM_PCH:
6787
                if (shreg[0])
6788
                    {a,cmd} = {13'd0,cmd_pch};
6789
            `FSM_ACT:
6790
                if (shreg[0])
6791
                    {a[row_size-1:0],cmd} = {row,cmd_act};
6792
            `FSM_RW:
6793
                begin
6794
                    if (we_i)
6795
                        cmd = cmd_wr;
6796
                    else
6797
                        cmd = cmd_rd;
6798
                    if (we_i)
6799
                        dqm = ~sel_i;
6800
                    else
6801
                        dqm = 2'b00;
6802
                    if (we_i)
6803
                        dq_oe = 1'b1;
6804
                    a = a10_fix(col);
6805
                    stall_o = 1'b1;
6806
                end
6807
            endcase
6808
        end
6809
 
6810
    assign ba = bank;
6811
 
6812
    // precharge individual bank A10=0
6813
    // precharge all bank A10=1
6814
    genvar i;
6815
    generate
6816
    for (i=0;i<2<<ba_size-1;i=i+1) begin
6817
 
6818
        always @ (posedge clk or posedge rst)
6819
        if (rst)
6820
            {open_ba[i],open_row[i]} <= {1'b0,{row_size{1'b0}}};
6821
        else
6822
            if (cmd==cmd_pch & (a[10] | bank==i))
6823
                open_ba[i] <= 1'b0;
6824
            else if (cmd==cmd_act & bank==i)
6825
                {open_ba[i],open_row[i]} <= {1'b1,row};
6826
 
6827
    end
6828
    endgenerate
6829
 
6830
    // bank and row open ?
6831
    always @ (posedge clk or posedge rst)
6832
    if (rst)
6833
       {current_bank_closed, current_row_open} <= {1'b1, 1'b0};
6834
    else
6835
       {current_bank_closed, current_row_open} <= {!(open_ba[bank]), open_row[bank]==row};
6836
 
6837
    // refresh counter
6838
`define MODULE cnt_lfsr_zq
6839
    `VLBASE`MODULE # ( .length(rfr_length), .wrap_value (rfr_wrap_value)) ref_counter0( .zq(ref_cnt_zero), .rst(rst), .clk(clk));
6840
`undef MODULE
6841
 
6842
    always @ (posedge clk or posedge rst)
6843
    if (rst)
6844
        refresh_req <= 1'b0;
6845
    else
6846
        if (ref_cnt_zero)
6847
            refresh_req <= 1'b1;
6848
        else if (state==`FSM_RFR)
6849
            refresh_req <= 1'b0;
6850
 
6851
    assign dat_o = dq_i;
6852
 
6853
    assign ack_wr = (state==`FSM_RW & count0 & we_i);
6854
`define MODULE delay_emptyflag
6855
    `VLBASE`MODULE # ( .depth(cl+2)) delay0 ( .d(state==`FSM_RW & stb_i & !we_i), .q(ack_rd), .emptyflag(rd_ack_emptyflag), .clk(clk), .rst(rst));
6856
`undef MODULE
6857
    assign ack_o = ack_rd | ack_wr;
6858
 
6859
    assign dq_o = dat_i;
6860
 
6861
endmodule
6862
`endif
6863 18 unneback
//////////////////////////////////////////////////////////////////////
6864
////                                                              ////
6865
////  Arithmetic functions                                        ////
6866
////                                                              ////
6867
////  Description                                                 ////
6868
////  Arithmetic functions for ALU and DSP                        ////
6869
////                                                              ////
6870
////                                                              ////
6871
////  To Do:                                                      ////
6872
////   -                                                          ////
6873
////                                                              ////
6874
////  Author(s):                                                  ////
6875
////      - Michael Unneback, unneback@opencores.org              ////
6876
////        ORSoC AB                                              ////
6877
////                                                              ////
6878
//////////////////////////////////////////////////////////////////////
6879
////                                                              ////
6880
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
6881
////                                                              ////
6882
//// This source file may be used and distributed without         ////
6883
//// restriction provided that this copyright statement is not    ////
6884
//// removed from the file and that any derivative work contains  ////
6885
//// the original copyright notice and the associated disclaimer. ////
6886
////                                                              ////
6887
//// This source file is free software; you can redistribute it   ////
6888
//// and/or modify it under the terms of the GNU Lesser General   ////
6889
//// Public License as published by the Free Software Foundation; ////
6890
//// either version 2.1 of the License, or (at your option) any   ////
6891
//// later version.                                               ////
6892
////                                                              ////
6893
//// This source is distributed in the hope that it will be       ////
6894
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
6895
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
6896
//// PURPOSE.  See the GNU Lesser General Public License for more ////
6897
//// details.                                                     ////
6898
////                                                              ////
6899
//// You should have received a copy of the GNU Lesser General    ////
6900
//// Public License along with this source; if not, download it   ////
6901
//// from http://www.opencores.org/lgpl.shtml                     ////
6902
////                                                              ////
6903
//////////////////////////////////////////////////////////////////////
6904
 
6905 40 unneback
`ifdef MULTS
6906 18 unneback
// signed multiplication
6907 40 unneback
`define MODULE mults
6908
module `BASE`MODULE (a,b,p);
6909
`undef MODULE
6910 18 unneback
parameter operand_a_width = 18;
6911
parameter operand_b_width = 18;
6912
parameter result_hi = 35;
6913
parameter result_lo = 0;
6914
input [operand_a_width-1:0] a;
6915
input [operand_b_width-1:0] b;
6916
output [result_hi:result_lo] p;
6917
wire signed [operand_a_width-1:0] ai;
6918
wire signed [operand_b_width-1:0] bi;
6919
wire signed [operand_a_width+operand_b_width-1:0] result;
6920
 
6921
    assign ai = a;
6922
    assign bi = b;
6923
    assign result = ai * bi;
6924
    assign p = result[result_hi:result_lo];
6925
 
6926
endmodule
6927 40 unneback
`endif
6928
`ifdef MULTS18X18
6929
`define MODULE mults18x18
6930
module `BASE`MODULE (a,b,p);
6931
`undef MODULE
6932 18 unneback
input [17:0] a,b;
6933
output [35:0] p;
6934
vl_mult
6935
    # (.operand_a_width(18), .operand_b_width(18))
6936
    mult0 (.a(a), .b(b), .p(p));
6937
endmodule
6938 40 unneback
`endif
6939 18 unneback
 
6940 40 unneback
`ifdef MULT
6941
`define MODULE mult
6942 18 unneback
// unsigned multiplication
6943 40 unneback
module `BASE`MODULE (a,b,p);
6944
`undef MODULE
6945 18 unneback
parameter operand_a_width = 18;
6946
parameter operand_b_width = 18;
6947
parameter result_hi = 35;
6948
parameter result_lo = 0;
6949
input [operand_a_width-1:0] a;
6950
input [operand_b_width-1:0] b;
6951
output [result_hi:result_hi] p;
6952
 
6953
wire [operand_a_width+operand_b_width-1:0] result;
6954
 
6955
    assign result = a * b;
6956
    assign p = result[result_hi:result_lo];
6957
 
6958
endmodule
6959 40 unneback
`endif
6960 18 unneback
 
6961 40 unneback
`ifdef SHIFT_UNIT_32
6962
`define MODULE shift_unit_32
6963 18 unneback
// shift unit
6964
// supporting the following shift functions
6965
//   SLL
6966
//   SRL
6967
//   SRA
6968
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
6969 40 unneback
module `BASE`MODULE( din, s, dout, opcode);
6970
`undef MODULE
6971 18 unneback
input [31:0] din; // data in operand
6972
input [4:0] s; // shift operand
6973
input [1:0] opcode;
6974
output [31:0] dout;
6975
 
6976
parameter opcode_sll = 2'b00;
6977
//parameter opcode_srl = 2'b01;
6978
parameter opcode_sra = 2'b10;
6979
//parameter opcode_ror = 2'b11;
6980
 
6981
wire sll, sra;
6982
assign sll = opcode == opcode_sll;
6983
assign sra = opcode == opcode_sra;
6984
 
6985
wire [15:1] s1;
6986
wire [3:0] sign;
6987
wire [7:0] tmp [0:3];
6988
 
6989
// first stage is multiplier based
6990
// shift operand as fractional 8.7
6991
assign s1[15] = sll & s[2:0]==3'd7;
6992
assign s1[14] = sll & s[2:0]==3'd6;
6993
assign s1[13] = sll & s[2:0]==3'd5;
6994
assign s1[12] = sll & s[2:0]==3'd4;
6995
assign s1[11] = sll & s[2:0]==3'd3;
6996
assign s1[10] = sll & s[2:0]==3'd2;
6997
assign s1[ 9] = sll & s[2:0]==3'd1;
6998
assign s1[ 8] = s[2:0]==3'd0;
6999
assign s1[ 7] = !sll & s[2:0]==3'd1;
7000
assign s1[ 6] = !sll & s[2:0]==3'd2;
7001
assign s1[ 5] = !sll & s[2:0]==3'd3;
7002
assign s1[ 4] = !sll & s[2:0]==3'd4;
7003
assign s1[ 3] = !sll & s[2:0]==3'd5;
7004
assign s1[ 2] = !sll & s[2:0]==3'd6;
7005
assign s1[ 1] = !sll & s[2:0]==3'd7;
7006
 
7007
assign sign[3] = din[31] & sra;
7008
assign sign[2] = sign[3] & (&din[31:24]);
7009
assign sign[1] = sign[2] & (&din[23:16]);
7010
assign sign[0] = sign[1] & (&din[15:8]);
7011 40 unneback
`define MODULE mults
7012
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
7013
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
7014
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
7015
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
7016
`undef MODULE
7017 18 unneback
// second stage is multiplexer based
7018
// shift on byte level
7019
 
7020
// mux byte 3
7021
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
7022
                     (sll & s[4:3]==2'b01) ? tmp[2] :
7023
                     (sll & s[4:3]==2'b10) ? tmp[1] :
7024
                     (sll & s[4:3]==2'b11) ? tmp[0] :
7025
                     {8{sign[3]}};
7026
 
7027
// mux byte 2
7028
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
7029
                     (sll & s[4:3]==2'b01) ? tmp[1] :
7030
                     (sll & s[4:3]==2'b10) ? tmp[0] :
7031
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
7032
                     (s[4:3]==2'b01) ? tmp[3] :
7033
                     {8{sign[3]}};
7034
 
7035
// mux byte 1
7036
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
7037
                     (sll & s[4:3]==2'b01) ? tmp[0] :
7038
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
7039
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
7040
                     (s[4:3]==2'b01) ? tmp[2] :
7041
                     (s[4:3]==2'b10) ? tmp[3] :
7042
                     {8{sign[3]}};
7043
 
7044
// mux byte 0
7045
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
7046
                     (sll) ?  {8{1'b0}}:
7047
                     (s[4:3]==2'b01) ? tmp[1] :
7048
                     (s[4:3]==2'b10) ? tmp[2] :
7049
                     tmp[3];
7050
 
7051
endmodule
7052 40 unneback
`endif
7053 18 unneback
 
7054 40 unneback
`ifdef LOGIC_UNIT
7055 18 unneback
// logic unit
7056
// supporting the following logic functions
7057
//    a and b
7058
//    a or  b
7059
//    a xor b
7060
//    not b
7061 40 unneback
`define MODULE logic_unit
7062
module `BASE`MODULE( a, b, result, opcode);
7063
`undef MODULE
7064 18 unneback
parameter width = 32;
7065
parameter opcode_and = 2'b00;
7066
parameter opcode_or  = 2'b01;
7067
parameter opcode_xor = 2'b10;
7068
input [width-1:0] a,b;
7069
output [width-1:0] result;
7070
input [1:0] opcode;
7071
 
7072
assign result = (opcode==opcode_and) ? a & b :
7073
                (opcode==opcode_or)  ? a | b :
7074
                (opcode==opcode_xor) ? a ^ b :
7075
                b;
7076
 
7077
endmodule
7078 48 unneback
`endif
7079 18 unneback
 
7080 48 unneback
`ifdef ARITH_UNIT
7081
`define MODULE arith_unit
7082
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
7083
`undef MODULE
7084 18 unneback
parameter width = 32;
7085
parameter opcode_add = 1'b0;
7086
parameter opcode_sub = 1'b1;
7087
input [width-1:0] a,b;
7088
input c_in, add_sub, sign;
7089
output [width-1:0] result;
7090
output c_out, z, ovfl;
7091
 
7092
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
7093
assign z = (result=={width{1'b0}});
7094
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
7095
               (~a[width-1] & ~b[width-1] &  result[width-1]);
7096
endmodule
7097 40 unneback
`endif
7098 48 unneback
 
7099
`ifdef COUNT_UNIT
7100
`define MODULE count_unit
7101
module `BASE`MODULE (din, dout, opcode);
7102
`undef MODULE
7103
parameter width = 32;
7104
input [width-1:0] din;
7105
output [width-1:0] dout;
7106
input opcode;
7107
 
7108
integer i;
7109 58 unneback
wire [width/32+4:0] ff1, fl1;
7110 48 unneback
 
7111 57 unneback
/*
7112 48 unneback
always @(din) begin
7113
    ff1 = 0; i = 0;
7114
    while (din[i] == 0 && i < width) begin // complex condition
7115
        ff1 = ff1 + 1;
7116
        i = i + 1;
7117
    end
7118
end
7119
 
7120
always @(din) begin
7121
    fl1 = width; i = width-1;
7122
    while (din[i] == 0 && i >= width) begin // complex condition
7123
        fl1 = fl1 - 1;
7124
        i = i - 1;
7125
    end
7126
end
7127 57 unneback
*/
7128 48 unneback
 
7129
generate
7130
if (width==32) begin
7131 57 unneback
 
7132
    assign ff1 = din[0] ? 6'd1 :
7133
                 din[1] ? 6'd2 :
7134
                 din[2] ? 6'd3 :
7135
                 din[3] ? 6'd4 :
7136
                 din[4] ? 6'd5 :
7137
                 din[5] ? 6'd6 :
7138
                 din[6] ? 6'd7 :
7139
                 din[7] ? 6'd8 :
7140
                 din[8] ? 6'd9 :
7141
                 din[9] ? 6'd10 :
7142
                 din[10] ? 6'd11 :
7143
                 din[11] ? 6'd12 :
7144
                 din[12] ? 6'd13 :
7145
                 din[13] ? 6'd14 :
7146
                 din[14] ? 6'd15 :
7147
                 din[15] ? 6'd16 :
7148
                 din[16] ? 6'd17 :
7149
                 din[17] ? 6'd18 :
7150
                 din[18] ? 6'd19 :
7151
                 din[19] ? 6'd20 :
7152
                 din[20] ? 6'd21 :
7153
                 din[21] ? 6'd22 :
7154
                 din[22] ? 6'd23 :
7155
                 din[23] ? 6'd24 :
7156
                 din[24] ? 6'd25 :
7157
                 din[25] ? 6'd26 :
7158
                 din[26] ? 6'd27 :
7159
                 din[27] ? 6'd28 :
7160
                 din[28] ? 6'd29 :
7161
                 din[29] ? 6'd30 :
7162
                 din[30] ? 6'd31 :
7163
                 din[31] ? 6'd32 :
7164
                 6'd0;
7165
 
7166
    assign fl1 = din[31] ? 6'd32 :
7167
                 din[30] ? 6'd31 :
7168
                 din[29] ? 6'd30 :
7169
                 din[28] ? 6'd29 :
7170
                 din[27] ? 6'd28 :
7171
                 din[26] ? 6'd27 :
7172
                 din[25] ? 6'd26 :
7173
                 din[24] ? 6'd25 :
7174
                 din[23] ? 6'd24 :
7175
                 din[22] ? 6'd23 :
7176
                 din[21] ? 6'd22 :
7177
                 din[20] ? 6'd21 :
7178
                 din[19] ? 6'd20 :
7179
                 din[18] ? 6'd19 :
7180
                 din[17] ? 6'd18 :
7181
                 din[16] ? 6'd17 :
7182
                 din[15] ? 6'd16 :
7183
                 din[14] ? 6'd15 :
7184
                 din[13] ? 6'd14 :
7185
                 din[12] ? 6'd13 :
7186
                 din[11] ? 6'd12 :
7187
                 din[10] ? 6'd11 :
7188
                 din[9] ? 6'd10 :
7189
                 din[8] ? 6'd9 :
7190
                 din[7] ? 6'd8 :
7191
                 din[6] ? 6'd7 :
7192
                 din[5] ? 6'd6 :
7193
                 din[4] ? 6'd5 :
7194
                 din[3] ? 6'd4 :
7195
                 din[2] ? 6'd3 :
7196
                 din[1] ? 6'd2 :
7197
                 din[0] ? 6'd1 :
7198
                 6'd0;
7199
 
7200
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
7201 48 unneback
end
7202
endgenerate
7203 57 unneback
 
7204 48 unneback
generate
7205
if (width==64) begin
7206 57 unneback
    assign ff1 = 7'd0;
7207
    assign fl1 = 7'd0;
7208
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
7209 48 unneback
end
7210
endgenerate
7211
 
7212
endmodule
7213
`endif
7214
 
7215
`ifdef EXT_UNIT
7216
`define MODULE ext_unit
7217
module `BASE`MODULE ( a, b, F, result, opcode);
7218
`undef MODULE
7219
parameter width = 32;
7220
input [width-1:0] a, b;
7221
input F;
7222
output reg [width-1:0] result;
7223
input [2:0] opcode;
7224
 
7225
generate
7226
if (width==32) begin
7227
always @ (a or b or F or opcode)
7228
begin
7229
    case (opcode)
7230
    3'b000: result = {{24{1'b0}},a[7:0]};
7231
    3'b001: result = {{24{a[7]}},a[7:0]};
7232
    3'b010: result = {{16{1'b0}},a[7:0]};
7233
    3'b011: result = {{16{a[15]}},a[15:0]};
7234
    3'b110: result = (F) ? a : b;
7235
    default: result = {b[15:0],16'h0000};
7236
    endcase
7237
end
7238
end
7239
endgenerate
7240
 
7241
generate
7242
if (width==64) begin
7243
always @ (a or b or F or opcode)
7244
begin
7245
    case (opcode)
7246
    3'b000: result = {{56{1'b0}},a[7:0]};
7247
    3'b001: result = {{56{a[7]}},a[7:0]};
7248
    3'b010: result = {{48{1'b0}},a[7:0]};
7249
    3'b011: result = {{48{a[15]}},a[15:0]};
7250 57 unneback
    3'b110: result = (F) ? a : b;
7251 48 unneback
    default: result = {32'h00000000,b[15:0],16'h0000};
7252
    endcase
7253
end
7254
end
7255
endgenerate
7256
endmodule
7257
`endif

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