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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 112

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
14
    // ACTEL FPGA should not use logic to handle rw collision
15
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16
`else
17
    `define SYN_NO_RW_CHECK
18
`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
23
`define SYNC_RST
24
`define PLL
25
 
26
`define MULTS
27
`define MULTS18X18
28
`define MULT
29
`define SHIFT_UNIT_32
30
`define LOGIC_UNIT
31
 
32
`define CNT_SHREG_WRAP
33
`define CNT_SHREG_CE_WRAP
34 105 unneback
`define CNT_SHREG_CLEAR
35 40 unneback
`define CNT_SHREG_CE_CLEAR
36
`define CNT_SHREG_CE_CLEAR_WRAP
37
 
38
`define MUX_ANDOR
39
`define MUX2_ANDOR
40
`define MUX3_ANDOR
41
`define MUX4_ANDOR
42
`define MUX5_ANDOR
43
`define MUX6_ANDOR
44 43 unneback
`define PARITY
45 40 unneback
 
46
`define ROM_INIT
47
`define RAM
48
`define RAM_BE
49
`define DPRAM_1R1W
50
`define DPRAM_2R1W
51 100 unneback
`define DPRAM_1R2W
52 40 unneback
`define DPRAM_2R2W
53 75 unneback
`define DPRAM_BE_2R2W
54 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
55
`define FIFO_2R2W_SYNC_SIMPLEX
56
`define FIFO_CMP_ASYNC
57
`define FIFO_1R1W_ASYNC
58
`define FIFO_2R2W_ASYNC
59
`define FIFO_2R2W_ASYNC_SIMPLEX
60 48 unneback
`define REG_FILE
61 40 unneback
 
62
`define DFF
63
`define DFF_ARRAY
64
`define DFF_CE
65
`define DFF_CE_CLEAR
66
`define DF_CE_SET
67
`define SPR
68
`define SRP
69
`define DFF_SR
70
`define LATCH
71
`define SHREG
72
`define SHREG_CE
73
`define DELAY
74
`define DELAY_EMPTYFLAG
75 94 unneback
`define PULSE2TOGGLE
76
`define TOGGLE2PULSE
77
`define SYNCHRONIZER
78
`define CDC
79 40 unneback
 
80 75 unneback
`define WB3AVALON_BRIDGE
81 40 unneback
`define WB3WB3_BRIDGE
82
`define WB3_ARBITER_TYPE1
83 83 unneback
`define WB_ADR_INC
84 101 unneback
`define WB_RAM
85 103 unneback
`define WB_SHADOW_RAM
86 48 unneback
`define WB_B4_ROM
87 40 unneback
`define WB_BOOT_ROM
88
`define WB_DPRAM
89 101 unneback
`define WB_CACHE
90 103 unneback
`define WB_AVALON_BRIDGE
91
`define WB_AVALON_MEM_CACHE
92 40 unneback
 
93 44 unneback
`define IO_DFF_OE
94
`define O_DFF
95
 
96 40 unneback
`endif
97
 
98
`ifdef PLL
99
`ifndef SYNC_RST
100
`define SYNC_RST
101
`endif
102
`endif
103
 
104
`ifdef SYNC_RST
105
`ifndef GBUF
106
`define GBUF
107
`endif
108
`endif
109
 
110 108 unneback
`ifdef WB_DPRAM
111 92 unneback
`ifndef WB_ADR_INC
112
`define WB_ADR_INC
113 40 unneback
`endif
114 92 unneback
`ifndef DPRAM_BE_2R2W
115
`define DPRAM_BE_2R2W
116 40 unneback
`endif
117
`endif
118
 
119 101 unneback
`ifdef WB_RAM
120 83 unneback
`ifndef WB_ADR_INC
121
`define WB_ADR_INC
122 62 unneback
`endif
123
`ifndef RAM_BE
124
`define RAM_BE
125
`endif
126
`endif
127
 
128 40 unneback
`ifdef WB3_ARBITER_TYPE1
129 42 unneback
`ifndef SPR
130
`define SPR
131
`endif
132 40 unneback
`ifndef MUX_ANDOR
133
`define MUX_ANDOR
134
`endif
135
`endif
136
 
137 76 unneback
`ifdef WB3AVALON_BRIDGE
138
`ifndef WB3WB3_BRIDGE
139
`define WB3WB3_BRIDGE
140
`endif
141
`endif
142
 
143 40 unneback
`ifdef WB3WB3_BRIDGE
144
`ifndef CNT_SHREG_CE_CLEAR
145
`define CNT_SHREG_CE_CLEAR
146
`endif
147
`ifndef DFF
148
`define DFF
149
`endif
150
`ifndef DFF_CE
151
`define DFF_CE
152
`endif
153
`ifndef CNT_SHREG_CE_CLEAR
154
`define CNT_SHREG_CE_CLEAR
155
`endif
156
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
157
`define FIFO_2R2W_ASYNC_SIMPLEX
158
`endif
159
`endif
160
 
161 103 unneback
 
162
`ifdef WB_AVALON_MEM_CACHE
163
`ifndef WB_SHADOW_RAM
164
`define WB_SHADOW_RAM
165
`endif
166
`ifndef WB_CACHE
167
`define WB_CACHE
168
`endif
169
`ifndef WB_AVALON_BRIDGE
170
`define WB_AVALON_BRIDGE
171
`endif
172
`endif
173
 
174 112 unneback
`ifdef WB_SHADOW_RAM
175
`ifndef WB_RAM
176
`define WB_RAM
177
`endif
178
`endif
179
 
180 101 unneback
`ifdef WB_CACHE
181 100 unneback
`ifndef RAM
182
`define RAM
183
`endif
184
`ifndef WB_ADR_INC
185
`define WB_ADR_INC
186
`endif
187
`ifndef DPRAM_1R1W
188
`define DPRAM_1R1W
189
`endif
190
`ifndef DPRAM_1R2W
191
`define DPRAM_1R2W
192
`endif
193
`ifndef DPRAM_BE_2R2W
194
`define DPRAM_BE_2R2W
195
`endif
196
`ifndef CDC
197
`define CDC
198
`endif
199
`endif
200 103 unneback
 
201
`ifdef WB_SHADOW_RAM
202
`ifndef WB_RAM
203
`define WB_RAM
204
`endif
205
`endif
206
 
207
`ifdef WB_RAM
208
`ifndef WB_ADR_INC
209
`define WB_ADR_INC
210
`endif
211
`endif
212 97 unneback
 
213 40 unneback
`ifdef MULTS18X18
214
`ifndef MULTS
215
`define MULTS
216
`endif
217
`endif
218
 
219
`ifdef SHIFT_UNIT_32
220
`ifndef MULTS
221
`define MULTS
222
`endif
223
`endif
224
 
225
`ifdef MUX2_ANDOR
226
`ifndef MUX_ANDOR
227
`define MUX_ANDOR
228
`endif
229
`endif
230
 
231
`ifdef MUX3_ANDOR
232
`ifndef MUX_ANDOR
233
`define MUX_ANDOR
234
`endif
235
`endif
236
 
237
`ifdef MUX4_ANDOR
238
`ifndef MUX_ANDOR
239
`define MUX_ANDOR
240
`endif
241
`endif
242
 
243
`ifdef MUX5_ANDOR
244
`ifndef MUX_ANDOR
245
`define MUX_ANDOR
246
`endif
247
`endif
248
 
249
`ifdef MUX6_ANDOR
250
`ifndef MUX_ANDOR
251
`define MUX_ANDOR
252
`endif
253
`endif
254
 
255
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
256
`ifndef CNT_BIN_CE
257
`define CNT_BIN_CE
258
`endif
259
`ifndef DPRAM_1R1W
260
`define DPRAM_1R1W
261
`endif
262
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
263
`define CNT_BIN_CE_REW_Q_ZQ_L1
264
`endif
265
`endif
266
 
267
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
268
`ifndef CNT_LFSR_CE
269
`define CNT_LFSR_CE
270
`endif
271
`ifndef DPRAM_2R2W
272
`define DPRAM_2R2W
273
`endif
274
`ifndef CNT_BIN_CE_REW_ZQ_L1
275
`define CNT_BIN_CE_REW_ZQ_L1
276
`endif
277
`endif
278
 
279
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
280
`ifndef CNT_GRAY_CE_BIN
281
`define CNT_GRAY_CE_BIN
282
`endif
283
`ifndef DPRAM_2R2W
284
`define DPRAM_2R2W
285
`endif
286
`ifndef FIFO_CMP_ASYNC
287
`define FIFO_CMP_ASYNC
288
`endif
289
`endif
290
 
291
`ifdef FIFO_2R2W_ASYNC
292
`ifndef FIFO_1R1W_ASYNC
293
`define FIFO_1R1W_ASYNC
294
`endif
295
`endif
296
 
297
`ifdef FIFO_1R1W_ASYNC
298
`ifndef CNT_GRAY_CE_BIN
299
`define CNT_GRAY_CE_BIN
300
`endif
301
`ifndef DPRAM_1R1W
302
`define DPRAM_1R1W
303
`endif
304
`ifndef FIFO_CMP_ASYNC
305
`define FIFO_CMP_ASYNC
306
`endif
307
`endif
308
 
309
`ifdef FIFO_CMP_ASYNC
310
`ifndef DFF_SR
311
`define DFF_SR
312
`endif
313
`ifndef DFF
314
`define DFF
315
`endif
316
`endif
317 48 unneback
 
318
`ifdef REG_FILE
319
`ifndef DPRAM_1R1W
320
`define DPRAM_1R1W
321
`endif
322
`endif
323 97 unneback
 
324 98 unneback
`ifdef CDC
325
`ifndef PULSE2TOGGLE
326
`define PULSE2TOGGLE
327
`endif
328
`ifndef TOGGLE2PULSE
329
`define TOGGLE2PULSE
330
`endif
331
`ifndef SYNCHRONIZER
332
`define SYNCHRONIZER
333
`endif
334
`endif
335
 
336 97 unneback
// size to width
337 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
338 62 unneback
//////////////////////////////////////////////////////////////////////
339 6 unneback
////                                                              ////
340
////  Versatile library, clock and reset                          ////
341
////                                                              ////
342
////  Description                                                 ////
343
////  Logic related to clock and reset                            ////
344
////                                                              ////
345
////                                                              ////
346
////  To Do:                                                      ////
347
////   - add more different registers                             ////
348
////                                                              ////
349
////  Author(s):                                                  ////
350
////      - Michael Unneback, unneback@opencores.org              ////
351
////        ORSoC AB                                              ////
352
////                                                              ////
353
//////////////////////////////////////////////////////////////////////
354
////                                                              ////
355
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
356
////                                                              ////
357
//// This source file may be used and distributed without         ////
358
//// restriction provided that this copyright statement is not    ////
359
//// removed from the file and that any derivative work contains  ////
360
//// the original copyright notice and the associated disclaimer. ////
361
////                                                              ////
362
//// This source file is free software; you can redistribute it   ////
363
//// and/or modify it under the terms of the GNU Lesser General   ////
364
//// Public License as published by the Free Software Foundation; ////
365
//// either version 2.1 of the License, or (at your option) any   ////
366
//// later version.                                               ////
367
////                                                              ////
368
//// This source is distributed in the hope that it will be       ////
369
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
370
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
371
//// PURPOSE.  See the GNU Lesser General Public License for more ////
372
//// details.                                                     ////
373
////                                                              ////
374
//// You should have received a copy of the GNU Lesser General    ////
375
//// Public License along with this source; if not, download it   ////
376
//// from http://www.opencores.org/lgpl.shtml                     ////
377
////                                                              ////
378
//////////////////////////////////////////////////////////////////////
379
 
380 48 unneback
`ifdef ACTEL
381
`ifdef GBUF
382
`timescale 1 ns/100 ps
383 6 unneback
// Global buffer
384
// usage:
385
// use to enable global buffers for high fan out signals such as clock and reset
386
// Version: 8.4 8.4.0.33
387
module gbuf(GL,CLK);
388
output GL;
389
input  CLK;
390
 
391
    wire GND;
392
 
393
    GND GND_1_net(.Y(GND));
394
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
395
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
396
 
397
endmodule
398
`timescale 1 ns/1 ns
399 40 unneback
`define MODULE gbuf
400
module `BASE`MODULE ( i, o);
401
`undef MODULE
402 6 unneback
input i;
403
output o;
404
`ifdef SIM_GBUF
405
assign o=i;
406
`else
407
gbuf gbuf_i0 ( .CLK(i), .GL(o));
408
`endif
409
endmodule
410 40 unneback
`endif
411 33 unneback
 
412 6 unneback
`else
413 33 unneback
 
414 40 unneback
`ifdef ALTERA
415
`ifdef GBUF
416 21 unneback
//altera
417 40 unneback
`define MODULE gbuf
418
module `BASE`MODULE ( i, o);
419
`undef MODULE
420 33 unneback
input i;
421
output o;
422
assign o = i;
423
endmodule
424 40 unneback
`endif
425 33 unneback
 
426 6 unneback
`else
427
 
428 40 unneback
`ifdef GBUF
429 6 unneback
`timescale 1 ns/100 ps
430 40 unneback
`define MODULE
431
module `BASE`MODULE ( i, o);
432
`undef MODULE
433 6 unneback
input i;
434
output o;
435
assign o = i;
436
endmodule
437 40 unneback
`endif
438 6 unneback
`endif // ALTERA
439
`endif //ACTEL
440
 
441 40 unneback
`ifdef SYNC_RST
442 6 unneback
// sync reset
443 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
444 6 unneback
// output active high global reset sync with two DFFs 
445
`timescale 1 ns/100 ps
446 40 unneback
`define MODULE sync_rst
447
module `BASE`MODULE ( rst_n_i, rst_o, clk);
448
`undef MODULE
449 6 unneback
input rst_n_i, clk;
450
output rst_o;
451 18 unneback
reg [1:0] tmp;
452 6 unneback
always @ (posedge clk or negedge rst_n_i)
453
if (!rst_n_i)
454 17 unneback
        tmp <= 2'b11;
455 6 unneback
else
456 33 unneback
        tmp <= {1'b0,tmp[1]};
457 40 unneback
`define MODULE gbuf
458
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
459
`undef MODULE
460 6 unneback
endmodule
461 40 unneback
`endif
462 6 unneback
 
463 40 unneback
`ifdef PLL
464 6 unneback
// vl_pll
465
`ifdef ACTEL
466 32 unneback
///////////////////////////////////////////////////////////////////////////////
467 17 unneback
`timescale 1 ps/1 ps
468 40 unneback
`define MODULE pll
469
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
470
`undef MODULE
471 6 unneback
parameter index = 0;
472
parameter number_of_clk = 1;
473 17 unneback
parameter period_time_0 = 20000;
474
parameter period_time_1 = 20000;
475
parameter period_time_2 = 20000;
476
parameter lock_delay = 2000000;
477 6 unneback
input clk_i, rst_n_i;
478
output lock;
479
output reg [0:number_of_clk-1] clk_o;
480
output [0:number_of_clk-1] rst_o;
481
 
482
`ifdef SIM_PLL
483
 
484
always
485
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
486
 
487
generate if (number_of_clk > 1)
488
always
489
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
490
endgenerate
491
 
492
generate if (number_of_clk > 2)
493
always
494
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
495
endgenerate
496
 
497
genvar i;
498
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
499
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
500
end
501
endgenerate
502
 
503
assign #lock_delay lock = rst_n_i;
504
 
505
endmodule
506
`else
507
generate if (number_of_clk==1 & index==0) begin
508
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
509
end
510
endgenerate // index==0
511
generate if (number_of_clk==1 & index==1) begin
512
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
513
end
514
endgenerate // index==1
515
generate if (number_of_clk==1 & index==2) begin
516
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
517
end
518
endgenerate // index==2
519
generate if (number_of_clk==1 & index==3) begin
520
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
521
end
522
endgenerate // index==0
523
 
524
generate if (number_of_clk==2 & index==0) begin
525
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
526
end
527
endgenerate // index==0
528
generate if (number_of_clk==2 & index==1) begin
529
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
530
end
531
endgenerate // index==1
532
generate if (number_of_clk==2 & index==2) begin
533
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
534
end
535
endgenerate // index==2
536
generate if (number_of_clk==2 & index==3) begin
537
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
538
end
539
endgenerate // index==0
540
 
541
generate if (number_of_clk==3 & index==0) begin
542
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
543
end
544
endgenerate // index==0
545
generate if (number_of_clk==3 & index==1) begin
546
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
547
end
548
endgenerate // index==1
549
generate if (number_of_clk==3 & index==2) begin
550
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
551
end
552
endgenerate // index==2
553
generate if (number_of_clk==3 & index==3) begin
554
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
555
end
556
endgenerate // index==0
557
 
558
genvar i;
559
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
560 40 unneback
`define MODULE sync_rst
561
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
562
`undef MODULE
563 6 unneback
end
564
endgenerate
565
endmodule
566
`endif
567 32 unneback
///////////////////////////////////////////////////////////////////////////////
568 6 unneback
 
569
`else
570
 
571 32 unneback
///////////////////////////////////////////////////////////////////////////////
572 6 unneback
`ifdef ALTERA
573
 
574 32 unneback
`timescale 1 ps/1 ps
575 40 unneback
`define MODULE pll
576
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
577
`undef MODULE
578 32 unneback
parameter index = 0;
579
parameter number_of_clk = 1;
580
parameter period_time_0 = 20000;
581
parameter period_time_1 = 20000;
582
parameter period_time_2 = 20000;
583
parameter period_time_3 = 20000;
584
parameter period_time_4 = 20000;
585
parameter lock_delay = 2000000;
586
input clk_i, rst_n_i;
587
output lock;
588
output reg [0:number_of_clk-1] clk_o;
589
output [0:number_of_clk-1] rst_o;
590
 
591
`ifdef SIM_PLL
592
 
593
always
594
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
595
 
596
generate if (number_of_clk > 1)
597
always
598
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
599
endgenerate
600
 
601
generate if (number_of_clk > 2)
602
always
603
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
604
endgenerate
605
 
606 33 unneback
generate if (number_of_clk > 3)
607 32 unneback
always
608
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
609
endgenerate
610
 
611 33 unneback
generate if (number_of_clk > 4)
612 32 unneback
always
613
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
614
endgenerate
615
 
616
genvar i;
617
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
618
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
619
end
620
endgenerate
621
 
622 33 unneback
//assign #lock_delay lock = rst_n_i;
623
assign lock = rst_n_i;
624 32 unneback
 
625
endmodule
626 6 unneback
`else
627
 
628 33 unneback
`ifdef VL_PLL0
629
`ifdef VL_PLL0_CLK1
630
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
631
`endif
632
`ifdef VL_PLL0_CLK2
633
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
634
`endif
635
`ifdef VL_PLL0_CLK3
636
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
637
`endif
638
`ifdef VL_PLL0_CLK4
639
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
640
`endif
641
`ifdef VL_PLL0_CLK5
642
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
643
`endif
644
`endif
645 32 unneback
 
646 33 unneback
`ifdef VL_PLL1
647
`ifdef VL_PLL1_CLK1
648
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
649
`endif
650
`ifdef VL_PLL1_CLK2
651
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
652
`endif
653
`ifdef VL_PLL1_CLK3
654
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
655
`endif
656
`ifdef VL_PLL1_CLK4
657
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
658
`endif
659
`ifdef VL_PLL1_CLK5
660
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
661
`endif
662
`endif
663 32 unneback
 
664 33 unneback
`ifdef VL_PLL2
665
`ifdef VL_PLL2_CLK1
666
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
667
`endif
668
`ifdef VL_PLL2_CLK2
669
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
670
`endif
671
`ifdef VL_PLL2_CLK3
672
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
673
`endif
674
`ifdef VL_PLL2_CLK4
675
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
676
`endif
677
`ifdef VL_PLL2_CLK5
678
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
679
`endif
680
`endif
681 32 unneback
 
682 33 unneback
`ifdef VL_PLL3
683
`ifdef VL_PLL3_CLK1
684
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
685
`endif
686
`ifdef VL_PLL3_CLK2
687
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
688
`endif
689
`ifdef VL_PLL3_CLK3
690
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
691
`endif
692
`ifdef VL_PLL3_CLK4
693
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
694
`endif
695
`ifdef VL_PLL3_CLK5
696
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
697
`endif
698
`endif
699 32 unneback
 
700
genvar i;
701
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
702 40 unneback
`define MODULE sync_rst
703
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
704
`undef MODULE
705 32 unneback
end
706
endgenerate
707
endmodule
708
`endif
709
///////////////////////////////////////////////////////////////////////////////
710
 
711
`else
712
 
713 6 unneback
// generic PLL
714 17 unneback
`timescale 1 ps/1 ps
715 40 unneback
`define MODULE pll
716
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
717
`undef MODULE
718 6 unneback
parameter index = 0;
719
parameter number_of_clk = 1;
720 17 unneback
parameter period_time_0 = 20000;
721
parameter period_time_1 = 20000;
722
parameter period_time_2 = 20000;
723 6 unneback
parameter lock_delay = 2000;
724
input clk_i, rst_n_i;
725
output lock;
726
output reg [0:number_of_clk-1] clk_o;
727
output [0:number_of_clk-1] rst_o;
728
 
729
always
730
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
731
 
732
generate if (number_of_clk > 1)
733
always
734
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
735
endgenerate
736
 
737
generate if (number_of_clk > 2)
738
always
739
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
740
endgenerate
741
 
742
genvar i;
743
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
744 40 unneback
`define MODULE sync_rst
745
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
746
`undef MODULE
747 6 unneback
end
748
endgenerate
749
 
750
assign #lock_delay lock = rst_n_i;
751
 
752
endmodule
753
 
754
`endif //altera
755 17 unneback
`endif //actel
756 40 unneback
`undef MODULE
757
`endif//////////////////////////////////////////////////////////////////////
758 6 unneback
////                                                              ////
759
////  Versatile library, registers                                ////
760
////                                                              ////
761
////  Description                                                 ////
762
////  Different type of registers                                 ////
763
////                                                              ////
764
////                                                              ////
765
////  To Do:                                                      ////
766
////   - add more different registers                             ////
767
////                                                              ////
768
////  Author(s):                                                  ////
769
////      - Michael Unneback, unneback@opencores.org              ////
770
////        ORSoC AB                                              ////
771
////                                                              ////
772
//////////////////////////////////////////////////////////////////////
773
////                                                              ////
774
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
775
////                                                              ////
776
//// This source file may be used and distributed without         ////
777
//// restriction provided that this copyright statement is not    ////
778
//// removed from the file and that any derivative work contains  ////
779
//// the original copyright notice and the associated disclaimer. ////
780
////                                                              ////
781
//// This source file is free software; you can redistribute it   ////
782
//// and/or modify it under the terms of the GNU Lesser General   ////
783
//// Public License as published by the Free Software Foundation; ////
784
//// either version 2.1 of the License, or (at your option) any   ////
785
//// later version.                                               ////
786
////                                                              ////
787
//// This source is distributed in the hope that it will be       ////
788
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
789
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
790
//// PURPOSE.  See the GNU Lesser General Public License for more ////
791
//// details.                                                     ////
792
////                                                              ////
793
//// You should have received a copy of the GNU Lesser General    ////
794
//// Public License along with this source; if not, download it   ////
795
//// from http://www.opencores.org/lgpl.shtml                     ////
796
////                                                              ////
797
//////////////////////////////////////////////////////////////////////
798
 
799 40 unneback
`ifdef DFF
800
`define MODULE dff
801
module `BASE`MODULE ( d, q, clk, rst);
802
`undef MODULE
803 6 unneback
        parameter width = 1;
804
        parameter reset_value = 0;
805
 
806
        input [width-1:0] d;
807
        input clk, rst;
808
        output reg [width-1:0] q;
809
 
810
        always @ (posedge clk or posedge rst)
811
        if (rst)
812
                q <= reset_value;
813
        else
814
                q <= d;
815
 
816
endmodule
817 40 unneback
`endif
818 6 unneback
 
819 40 unneback
`ifdef DFF_ARRAY
820
`define MODULE dff_array
821
module `BASE`MODULE ( d, q, clk, rst);
822
`undef MODULE
823 6 unneback
 
824
        parameter width = 1;
825
        parameter depth = 2;
826
        parameter reset_value = 1'b0;
827
 
828
        input [width-1:0] d;
829
        input clk, rst;
830
        output [width-1:0] q;
831
        reg  [0:depth-1] q_tmp [width-1:0];
832
        integer i;
833
        always @ (posedge clk or posedge rst)
834
        if (rst) begin
835
            for (i=0;i<depth;i=i+1)
836
                q_tmp[i] <= {width{reset_value}};
837
        end else begin
838
            q_tmp[0] <= d;
839
            for (i=1;i<depth;i=i+1)
840
                q_tmp[i] <= q_tmp[i-1];
841
        end
842
 
843
    assign q = q_tmp[depth-1];
844
 
845
endmodule
846 40 unneback
`endif
847 6 unneback
 
848 40 unneback
`ifdef DFF_CE
849
`define MODULE dff_ce
850
module `BASE`MODULE ( d, ce, q, clk, rst);
851
`undef MODULE
852 6 unneback
 
853
        parameter width = 1;
854
        parameter reset_value = 0;
855
 
856
        input [width-1:0] d;
857
        input ce, clk, rst;
858
        output reg [width-1:0] q;
859
 
860
        always @ (posedge clk or posedge rst)
861
        if (rst)
862
                q <= reset_value;
863
        else
864
                if (ce)
865
                        q <= d;
866
 
867
endmodule
868 40 unneback
`endif
869 6 unneback
 
870 40 unneback
`ifdef DFF_CE_CLEAR
871
`define MODULE dff_ce_clear
872
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
873
`undef MODULE
874 8 unneback
 
875
        parameter width = 1;
876
        parameter reset_value = 0;
877
 
878
        input [width-1:0] d;
879 10 unneback
        input ce, clear, clk, rst;
880 8 unneback
        output reg [width-1:0] q;
881
 
882
        always @ (posedge clk or posedge rst)
883
        if (rst)
884
            q <= reset_value;
885
        else
886
            if (ce)
887
                if (clear)
888
                    q <= {width{1'b0}};
889
                else
890
                    q <= d;
891
 
892
endmodule
893 40 unneback
`endif
894 8 unneback
 
895 40 unneback
`ifdef DF_CE_SET
896
`define MODULE dff_ce_set
897
module `BASE`MODULE ( d, ce, set, q, clk, rst);
898
`undef MODULE
899 24 unneback
 
900
        parameter width = 1;
901
        parameter reset_value = 0;
902
 
903
        input [width-1:0] d;
904
        input ce, set, clk, rst;
905
        output reg [width-1:0] q;
906
 
907
        always @ (posedge clk or posedge rst)
908
        if (rst)
909
            q <= reset_value;
910
        else
911
            if (ce)
912
                if (set)
913
                    q <= {width{1'b1}};
914
                else
915
                    q <= d;
916
 
917
endmodule
918 40 unneback
`endif
919 24 unneback
 
920 40 unneback
`ifdef SPR
921
`define MODULE spr
922
module `BASE`MODULE ( sp, r, q, clk, rst);
923
`undef MODULE
924
 
925 64 unneback
        //parameter width = 1;
926
        parameter reset_value = 1'b0;
927 29 unneback
 
928
        input sp, r;
929
        output reg q;
930
        input clk, rst;
931
 
932
        always @ (posedge clk or posedge rst)
933
        if (rst)
934
            q <= reset_value;
935
        else
936
            if (sp)
937
                q <= 1'b1;
938
            else if (r)
939
                q <= 1'b0;
940
 
941
endmodule
942 40 unneback
`endif
943 29 unneback
 
944 40 unneback
`ifdef SRP
945
`define MODULE srp
946
module `BASE`MODULE ( s, rp, q, clk, rst);
947
`undef MODULE
948
 
949 29 unneback
        parameter width = 1;
950
        parameter reset_value = 0;
951
 
952
        input s, rp;
953
        output reg q;
954
        input clk, rst;
955
 
956
        always @ (posedge clk or posedge rst)
957
        if (rst)
958
            q <= reset_value;
959
        else
960
            if (rp)
961
                q <= 1'b0;
962
            else if (s)
963
                q <= 1'b1;
964
 
965
endmodule
966 40 unneback
`endif
967 29 unneback
 
968 40 unneback
`ifdef ALTERA
969 29 unneback
 
970 40 unneback
`ifdef DFF_SR
971 6 unneback
// megafunction wizard: %LPM_FF%
972
// GENERATION: STANDARD
973
// VERSION: WM1.0
974
// MODULE: lpm_ff 
975
 
976
// ============================================================
977
// File Name: dff_sr.v
978
// Megafunction Name(s):
979
//                      lpm_ff
980
//
981
// Simulation Library Files(s):
982
//                      lpm
983
// ============================================================
984
// ************************************************************
985
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
986
//
987
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
988
// ************************************************************
989
 
990
 
991
//Copyright (C) 1991-2010 Altera Corporation
992
//Your use of Altera Corporation's design tools, logic functions 
993
//and other software and tools, and its AMPP partner logic 
994
//functions, and any output files from any of the foregoing 
995
//(including device programming or simulation files), and any 
996
//associated documentation or information are expressly subject 
997
//to the terms and conditions of the Altera Program License 
998
//Subscription Agreement, Altera MegaCore Function License 
999
//Agreement, or other applicable license agreement, including, 
1000
//without limitation, that your use is for the sole purpose of 
1001
//programming logic devices manufactured by Altera and sold by 
1002
//Altera or its authorized distributors.  Please refer to the 
1003
//applicable agreement for further details.
1004
 
1005
 
1006
// synopsys translate_off
1007
`timescale 1 ps / 1 ps
1008
// synopsys translate_on
1009 40 unneback
`define MODULE dff_sr
1010
module `BASE`MODULE (
1011
`undef MODULE
1012
 
1013 6 unneback
        aclr,
1014
        aset,
1015
        clock,
1016
        data,
1017
        q);
1018
 
1019
        input     aclr;
1020
        input     aset;
1021
        input     clock;
1022
        input     data;
1023
        output    q;
1024
 
1025
        wire [0:0] sub_wire0;
1026
        wire [0:0] sub_wire1 = sub_wire0[0:0];
1027
        wire  q = sub_wire1;
1028
        wire  sub_wire2 = data;
1029
        wire  sub_wire3 = sub_wire2;
1030
 
1031
        lpm_ff  lpm_ff_component (
1032
                                .aclr (aclr),
1033
                                .clock (clock),
1034
                                .data (sub_wire3),
1035
                                .aset (aset),
1036
                                .q (sub_wire0)
1037
                                // synopsys translate_off
1038
                                ,
1039
                                .aload (),
1040
                                .enable (),
1041
                                .sclr (),
1042
                                .sload (),
1043
                                .sset ()
1044
                                // synopsys translate_on
1045
                                );
1046
        defparam
1047
                lpm_ff_component.lpm_fftype = "DFF",
1048
                lpm_ff_component.lpm_type = "LPM_FF",
1049
                lpm_ff_component.lpm_width = 1;
1050
 
1051
 
1052
endmodule
1053
 
1054
// ============================================================
1055
// CNX file retrieval info
1056
// ============================================================
1057
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1058
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1059
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1060
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1061
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1062
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1063
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1064
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1065
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1066
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1067
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1068
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1069
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1070
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1071
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1072
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1073
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1074
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1075
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1076
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1077
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1078
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1079
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1080
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1081
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1082
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1083
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1084
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1085
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1086
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1087
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1088
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1089
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1090
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1091
// Retrieval info: LIB_FILE: lpm
1092 40 unneback
`endif
1093 6 unneback
 
1094
`else
1095
 
1096 40 unneback
`ifdef DFF_SR
1097
`define MODULE dff_sr
1098
module `BASE`MODULE ( aclr, aset, clock, data, q);
1099
`undef MODULE
1100 6 unneback
 
1101
    input         aclr;
1102
    input         aset;
1103
    input         clock;
1104
    input         data;
1105
    output reg    q;
1106
 
1107
   always @ (posedge clock or posedge aclr or posedge aset)
1108
     if (aclr)
1109
       q <= 1'b0;
1110
     else if (aset)
1111
       q <= 1'b1;
1112
     else
1113
       q <= data;
1114
 
1115
endmodule
1116 40 unneback
`endif
1117 6 unneback
 
1118
`endif
1119
 
1120
// LATCH
1121
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1122
`ifdef ALTERA
1123 40 unneback
 
1124
`ifdef LATCH
1125
`define MODULE latch
1126
module `BASE`MODULE ( d, le, q, clk);
1127
`undef MODULE
1128 6 unneback
input d, le;
1129
output q;
1130
input clk;
1131
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1132
endmodule
1133 40 unneback
`endif
1134
 
1135 6 unneback
`else
1136 40 unneback
 
1137
`ifdef LATCH
1138
`define MODULE latch
1139
module `BASE`MODULE ( d, le, q, clk);
1140
`undef MODULE
1141 6 unneback
input d, le;
1142 48 unneback
input clk;
1143
always @ (le or d)
1144 60 unneback
if (le)
1145 48 unneback
    d <= q;
1146 6 unneback
endmodule
1147 15 unneback
`endif
1148
 
1149 40 unneback
`endif
1150
 
1151
`ifdef SHREG
1152
`define MODULE shreg
1153
module `BASE`MODULE ( d, q, clk, rst);
1154
`undef MODULE
1155
 
1156 17 unneback
parameter depth = 10;
1157
input d;
1158
output q;
1159
input clk, rst;
1160
 
1161
reg [1:depth] dffs;
1162
 
1163
always @ (posedge clk or posedge rst)
1164
if (rst)
1165
    dffs <= {depth{1'b0}};
1166
else
1167
    dffs <= {d,dffs[1:depth-1]};
1168
assign q = dffs[depth];
1169
endmodule
1170 40 unneback
`endif
1171 17 unneback
 
1172 40 unneback
`ifdef SHREG_CE
1173
`define MODULE shreg_ce
1174
module `BASE`MODULE ( d, ce, q, clk, rst);
1175
`undef MODULE
1176 17 unneback
parameter depth = 10;
1177
input d, ce;
1178
output q;
1179
input clk, rst;
1180
 
1181
reg [1:depth] dffs;
1182
 
1183
always @ (posedge clk or posedge rst)
1184
if (rst)
1185
    dffs <= {depth{1'b0}};
1186
else
1187
    if (ce)
1188
        dffs <= {d,dffs[1:depth-1]};
1189
assign q = dffs[depth];
1190
endmodule
1191 40 unneback
`endif
1192 17 unneback
 
1193 40 unneback
`ifdef DELAY
1194
`define MODULE delay
1195
module `BASE`MODULE ( d, q, clk, rst);
1196
`undef MODULE
1197 15 unneback
parameter depth = 10;
1198
input d;
1199
output q;
1200
input clk, rst;
1201
 
1202
reg [1:depth] dffs;
1203
 
1204
always @ (posedge clk or posedge rst)
1205
if (rst)
1206
    dffs <= {depth{1'b0}};
1207
else
1208
    dffs <= {d,dffs[1:depth-1]};
1209
assign q = dffs[depth];
1210 17 unneback
endmodule
1211 40 unneback
`endif
1212 17 unneback
 
1213 40 unneback
`ifdef DELAY_EMPTYFLAG
1214
`define MODULE delay_emptyflag
1215 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1216 40 unneback
`undef MODULE
1217 17 unneback
parameter depth = 10;
1218
input d;
1219
output q, emptyflag;
1220
input clk, rst;
1221
 
1222
reg [1:depth] dffs;
1223
 
1224
always @ (posedge clk or posedge rst)
1225
if (rst)
1226
    dffs <= {depth{1'b0}};
1227
else
1228
    dffs <= {d,dffs[1:depth-1]};
1229
assign q = dffs[depth];
1230
assign emptyflag = !(|dffs);
1231
endmodule
1232 40 unneback
`endif
1233 75 unneback
 
1234 94 unneback
`ifdef PULSE2TOGGLE
1235 98 unneback
`define MODULE pulse2toggle
1236
module `BASE`MODULE ( pl, q, clk, rst);
1237 75 unneback
`undef MODULE
1238 94 unneback
input pl;
1239 98 unneback
output reg q;
1240 94 unneback
input clk, rst;
1241
always @ (posedge clk or posedge rst)
1242 75 unneback
if (rst)
1243 94 unneback
    q <= 1'b0;
1244 75 unneback
else
1245 94 unneback
    q <= pl ^ q;
1246
endmodule
1247
`endif
1248 75 unneback
 
1249 94 unneback
`ifdef TOGGLE2PULSE
1250 98 unneback
`define MODULE toggle2pulse
1251 94 unneback
module `BASE`MODULE (d, pl, clk, rst);
1252 97 unneback
`undef MODULE
1253 94 unneback
input d;
1254
output pl;
1255
input clk, rst;
1256
reg dff;
1257
always @ (posedge clk or posedge rst)
1258
if (rst)
1259
    dff <= 1'b0;
1260 75 unneback
else
1261 94 unneback
    dff <= d;
1262 98 unneback
assign pl = d ^ dff;
1263 94 unneback
endmodule
1264
`endif
1265 75 unneback
 
1266 94 unneback
`ifdef SYNCHRONIZER
1267
`define MODULE synchronizer
1268
module `BASE`MODULE (d, q, clk, rst);
1269
`undef MODULE
1270
input d;
1271
output reg q;
1272
output clk, rst;
1273
reg dff;
1274
always @ (posedge clk or posedge rst)
1275
if (rst)
1276 100 unneback
    {q,dff} <= 2'b00;
1277 75 unneback
else
1278 100 unneback
    {q,dff} <= {dff,d};
1279 94 unneback
endmodule
1280
`endif
1281 75 unneback
 
1282 94 unneback
`ifdef CDC
1283
`define MODULE cdc
1284 97 unneback
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1285 94 unneback
`undef MODULE
1286
input start_pl;
1287
output take_it_pl;
1288
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1289
output got_it_pl;
1290
input clk_src, rst_src;
1291
input clk_dst, rst_dst;
1292
wire take_it_tg, take_it_tg_sync;
1293
wire got_it_tg, got_it_tg_sync;
1294
// src -> dst
1295
`define MODULE pulse2toggle
1296
`BASE`MODULE p2t0 (
1297
`undef MODULE
1298
    .pl(start_pl),
1299
    .q(take_it_tg),
1300
    .clk(clk_src),
1301
    .rst(rst_src));
1302 75 unneback
 
1303 94 unneback
`define MODULE synchronizer
1304
`BASE`MODULE sync0 (
1305
`undef MODULE
1306
    .d(take_it_tg),
1307
    .q(take_it_tg_sync),
1308
    .clk(clk_dst),
1309
    .rst(rst_dst));
1310
 
1311
`define MODULE toggle2pulse
1312
`BASE`MODULE t2p0 (
1313
`undef MODULE
1314 100 unneback
    .d(take_it_tg_sync),
1315 94 unneback
    .pl(take_it_pl),
1316
    .clk(clk_dst),
1317
    .rst(rst_dst));
1318
 
1319
// dst -> src
1320
`define MODULE pulse2toggle
1321 98 unneback
`BASE`MODULE p2t1 (
1322 94 unneback
`undef MODULE
1323
    .pl(take_it_grant_pl),
1324
    .q(got_it_tg),
1325
    .clk(clk_dst),
1326
    .rst(rst_dst));
1327
 
1328
`define MODULE synchronizer
1329
`BASE`MODULE sync1 (
1330
`undef MODULE
1331
    .d(got_it_tg),
1332
    .q(got_it_tg_sync),
1333
    .clk(clk_src),
1334
    .rst(rst_src));
1335
 
1336
`define MODULE toggle2pulse
1337
`BASE`MODULE t2p1 (
1338
`undef MODULE
1339 100 unneback
    .d(got_it_tg_sync),
1340 94 unneback
    .pl(got_it_pl),
1341
    .clk(clk_src),
1342
    .rst(rst_src));
1343
 
1344 75 unneback
endmodule
1345
`endif
1346 17 unneback
//////////////////////////////////////////////////////////////////////
1347 6 unneback
////                                                              ////
1348 18 unneback
////  Logic functions                                             ////
1349
////                                                              ////
1350
////  Description                                                 ////
1351
////  Logic functions such as multiplexers                        ////
1352
////                                                              ////
1353
////                                                              ////
1354
////  To Do:                                                      ////
1355
////   -                                                          ////
1356
////                                                              ////
1357
////  Author(s):                                                  ////
1358
////      - Michael Unneback, unneback@opencores.org              ////
1359
////        ORSoC AB                                              ////
1360
////                                                              ////
1361
//////////////////////////////////////////////////////////////////////
1362
////                                                              ////
1363
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1364
////                                                              ////
1365
//// This source file may be used and distributed without         ////
1366
//// restriction provided that this copyright statement is not    ////
1367
//// removed from the file and that any derivative work contains  ////
1368
//// the original copyright notice and the associated disclaimer. ////
1369
////                                                              ////
1370
//// This source file is free software; you can redistribute it   ////
1371
//// and/or modify it under the terms of the GNU Lesser General   ////
1372
//// Public License as published by the Free Software Foundation; ////
1373
//// either version 2.1 of the License, or (at your option) any   ////
1374
//// later version.                                               ////
1375
////                                                              ////
1376
//// This source is distributed in the hope that it will be       ////
1377
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1378
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1379
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1380
//// details.                                                     ////
1381
////                                                              ////
1382
//// You should have received a copy of the GNU Lesser General    ////
1383
//// Public License along with this source; if not, download it   ////
1384
//// from http://www.opencores.org/lgpl.shtml                     ////
1385
////                                                              ////
1386
//////////////////////////////////////////////////////////////////////
1387 40 unneback
`ifdef MUX_ANDOR
1388
`define MODULE mux_andor
1389
module `BASE`MODULE ( a, sel, dout);
1390
`undef MODULE
1391 36 unneback
 
1392
parameter width = 32;
1393
parameter nr_of_ports = 4;
1394
 
1395
input [nr_of_ports*width-1:0] a;
1396
input [nr_of_ports-1:0] sel;
1397
output reg [width-1:0] dout;
1398
 
1399 38 unneback
integer i,j;
1400
 
1401 36 unneback
always @ (a, sel)
1402
begin
1403
    dout = a[width-1:0] & {width{sel[0]}};
1404 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1405
        for (j=0;j<width;j=j+1)
1406
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1407 36 unneback
end
1408
 
1409
endmodule
1410 40 unneback
`endif
1411 36 unneback
 
1412 40 unneback
`ifdef MUX2_ANDOR
1413
`define MODULE mux2_andor
1414
module `BASE`MODULE ( a1, a0, sel, dout);
1415
`undef MODULE
1416 18 unneback
 
1417 34 unneback
parameter width = 32;
1418 35 unneback
localparam nr_of_ports = 2;
1419 34 unneback
input [width-1:0] a1, a0;
1420
input [nr_of_ports-1:0] sel;
1421
output [width-1:0] dout;
1422
 
1423 40 unneback
`define MODULE mux_andor
1424
`BASE`MODULE
1425 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1426 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1427 40 unneback
`undef MODULE
1428
 
1429 34 unneback
endmodule
1430 40 unneback
`endif
1431 34 unneback
 
1432 40 unneback
`ifdef MUX3_ANDOR
1433
`define MODULE mux3_andor
1434
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1435
`undef MODULE
1436 34 unneback
 
1437
parameter width = 32;
1438 35 unneback
localparam nr_of_ports = 3;
1439 34 unneback
input [width-1:0] a2, a1, a0;
1440
input [nr_of_ports-1:0] sel;
1441
output [width-1:0] dout;
1442
 
1443 40 unneback
`define MODULE mux_andor
1444
`BASE`MODULE
1445 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1446 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1447 40 unneback
`undef MODULE
1448 34 unneback
endmodule
1449 40 unneback
`endif
1450 34 unneback
 
1451 40 unneback
`ifdef MUX4_ANDOR
1452
`define MODULE mux4_andor
1453
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1454
`undef MODULE
1455 18 unneback
 
1456
parameter width = 32;
1457 35 unneback
localparam nr_of_ports = 4;
1458 18 unneback
input [width-1:0] a3, a2, a1, a0;
1459
input [nr_of_ports-1:0] sel;
1460 22 unneback
output [width-1:0] dout;
1461 18 unneback
 
1462 40 unneback
`define MODULE mux_andor
1463
`BASE`MODULE
1464 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1465 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1466 40 unneback
`undef MODULE
1467 18 unneback
 
1468
endmodule
1469 40 unneback
`endif
1470 18 unneback
 
1471 40 unneback
`ifdef MUX5_ANDOR
1472
`define MODULE mux5_andor
1473
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1474
`undef MODULE
1475 18 unneback
 
1476
parameter width = 32;
1477 35 unneback
localparam nr_of_ports = 5;
1478 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1479
input [nr_of_ports-1:0] sel;
1480 22 unneback
output [width-1:0] dout;
1481 18 unneback
 
1482 40 unneback
`define MODULE mux_andor
1483
`BASE`MODULE
1484 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1485 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1486 40 unneback
`undef MODULE
1487 18 unneback
 
1488
endmodule
1489 40 unneback
`endif
1490 18 unneback
 
1491 40 unneback
`ifdef MUX6_ANDOR
1492
`define MODULE mux6_andor
1493
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1494
`undef MODULE
1495 18 unneback
 
1496
parameter width = 32;
1497 35 unneback
localparam nr_of_ports = 6;
1498 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1499
input [nr_of_ports-1:0] sel;
1500 22 unneback
output [width-1:0] dout;
1501 18 unneback
 
1502 40 unneback
`define MODULE mux_andor
1503
`BASE`MODULE
1504 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1505 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1506 40 unneback
`undef MODULE
1507 18 unneback
 
1508
endmodule
1509 40 unneback
`endif
1510 43 unneback
 
1511
`ifdef PARITY
1512
 
1513
`define MODULE parity_generate
1514
module `BASE`MODULE (data, parity);
1515
`undef MODULE
1516
parameter word_size = 32;
1517
parameter chunk_size = 8;
1518
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1519
input [word_size-1:0] data;
1520
output reg [word_size/chunk_size-1:0] parity;
1521
integer i,j;
1522
always @ (data)
1523
for (i=0;i<word_size/chunk_size;i=i+1) begin
1524
    parity[i] = parity_type;
1525
    for (j=0;j<chunk_size;j=j+1) begin
1526 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1527 43 unneback
    end
1528
end
1529
endmodule
1530
 
1531
`define MODULE parity_check
1532
module `BASE`MODULE( data, parity, parity_error);
1533
`undef MODULE
1534
parameter word_size = 32;
1535
parameter chunk_size = 8;
1536
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1537
input [word_size-1:0] data;
1538
input [word_size/chunk_size-1:0] parity;
1539
output parity_error;
1540 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1541 43 unneback
integer i,j;
1542
always @ (data or parity)
1543
for (i=0;i<word_size/chunk_size;i=i+1) begin
1544
    error_flag[i] = parity[i] ^ parity_type;
1545
    for (j=0;j<chunk_size;j=j+1) begin
1546 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1547 43 unneback
    end
1548
end
1549
assign parity_error = |error_flag;
1550
endmodule
1551
 
1552 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1553
////                                                              ////
1554
////  IO functions                                                ////
1555
////                                                              ////
1556
////  Description                                                 ////
1557
////  IO functions such as IOB flip-flops                         ////
1558
////                                                              ////
1559
////                                                              ////
1560
////  To Do:                                                      ////
1561
////   -                                                          ////
1562
////                                                              ////
1563
////  Author(s):                                                  ////
1564
////      - Michael Unneback, unneback@opencores.org              ////
1565
////        ORSoC AB                                              ////
1566
////                                                              ////
1567 18 unneback
//////////////////////////////////////////////////////////////////////
1568
////                                                              ////
1569 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1570
////                                                              ////
1571
//// This source file may be used and distributed without         ////
1572
//// restriction provided that this copyright statement is not    ////
1573
//// removed from the file and that any derivative work contains  ////
1574
//// the original copyright notice and the associated disclaimer. ////
1575
////                                                              ////
1576
//// This source file is free software; you can redistribute it   ////
1577
//// and/or modify it under the terms of the GNU Lesser General   ////
1578
//// Public License as published by the Free Software Foundation; ////
1579
//// either version 2.1 of the License, or (at your option) any   ////
1580
//// later version.                                               ////
1581
////                                                              ////
1582
//// This source is distributed in the hope that it will be       ////
1583
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1584
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1585
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1586
//// details.                                                     ////
1587
////                                                              ////
1588
//// You should have received a copy of the GNU Lesser General    ////
1589
//// Public License along with this source; if not, download it   ////
1590
//// from http://www.opencores.org/lgpl.shtml                     ////
1591
////                                                              ////
1592
//////////////////////////////////////////////////////////////////////
1593 45 unneback
`timescale 1ns/1ns
1594 44 unneback
`ifdef O_DFF
1595
`define MODULE o_dff
1596
module `BASE`MODULE (d_i, o_pad, clk, rst);
1597
`undef MODULE
1598
parameter width = 1;
1599 45 unneback
parameter reset_value = {width{1'b0}};
1600
input  [width-1:0]  d_i;
1601 44 unneback
output [width-1:0] o_pad;
1602
input clk, rst;
1603
wire [width-1:0] d_i_int `SYN_KEEP;
1604 45 unneback
reg  [width-1:0] o_pad_int;
1605 44 unneback
assign d_i_int = d_i;
1606
genvar i;
1607 45 unneback
generate
1608 44 unneback
for (i=0;i<width;i=i+1) begin
1609
    always @ (posedge clk or posedge rst)
1610
    if (rst)
1611 45 unneback
        o_pad_int[i] <= reset_value[i];
1612 44 unneback
    else
1613 45 unneback
        o_pad_int[i] <= d_i_int[i];
1614
    assign #1 o_pad[i] = o_pad_int[i];
1615 44 unneback
end
1616
endgenerate
1617
endmodule
1618
`endif
1619
 
1620 45 unneback
`timescale 1ns/1ns
1621 44 unneback
`ifdef IO_DFF_OE
1622
`define MODULE io_dff_oe
1623
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1624
`undef MODULE
1625
parameter width = 1;
1626
input  [width-1:0] d_o;
1627
output reg [width-1:0] d_i;
1628
input oe;
1629
inout [width-1:0] io_pad;
1630
input clk, rst;
1631
wire [width-1:0] oe_d `SYN_KEEP;
1632
reg [width-1:0] oe_q;
1633
reg [width-1:0] d_o_q;
1634
assign oe_d = {width{oe}};
1635
genvar i;
1636
generate
1637
for (i=0;i<width;i=i+1) begin
1638
    always @ (posedge clk or posedge rst)
1639
    if (rst)
1640
        oe_q[i] <= 1'b0;
1641
    else
1642
        oe_q[i] <= oe_d[i];
1643
    always @ (posedge clk or posedge rst)
1644
    if (rst)
1645
        d_o_q[i] <= 1'b0;
1646
    else
1647
        d_o_q[i] <= d_o[i];
1648
    always @ (posedge clk or posedge rst)
1649
    if (rst)
1650
        d_i[i] <= 1'b0;
1651
    else
1652
        d_i[i] <= io_pad[i];
1653 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1654 44 unneback
end
1655
endgenerate
1656
endmodule
1657
`endif
1658
`ifdef CNT_BIN
1659
//////////////////////////////////////////////////////////////////////
1660
////                                                              ////
1661 6 unneback
////  Versatile counter                                           ////
1662
////                                                              ////
1663
////  Description                                                 ////
1664
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1665
////  counter                                                     ////
1666
////                                                              ////
1667
////  To Do:                                                      ////
1668
////   - add LFSR with more taps                                  ////
1669
////                                                              ////
1670
////  Author(s):                                                  ////
1671
////      - Michael Unneback, unneback@opencores.org              ////
1672
////        ORSoC AB                                              ////
1673
////                                                              ////
1674
//////////////////////////////////////////////////////////////////////
1675
////                                                              ////
1676
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1677
////                                                              ////
1678
//// This source file may be used and distributed without         ////
1679
//// restriction provided that this copyright statement is not    ////
1680
//// removed from the file and that any derivative work contains  ////
1681
//// the original copyright notice and the associated disclaimer. ////
1682
////                                                              ////
1683
//// This source file is free software; you can redistribute it   ////
1684
//// and/or modify it under the terms of the GNU Lesser General   ////
1685
//// Public License as published by the Free Software Foundation; ////
1686
//// either version 2.1 of the License, or (at your option) any   ////
1687
//// later version.                                               ////
1688
////                                                              ////
1689
//// This source is distributed in the hope that it will be       ////
1690
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1691
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1692
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1693
//// details.                                                     ////
1694
////                                                              ////
1695
//// You should have received a copy of the GNU Lesser General    ////
1696
//// Public License along with this source; if not, download it   ////
1697
//// from http://www.opencores.org/lgpl.shtml                     ////
1698
////                                                              ////
1699
//////////////////////////////////////////////////////////////////////
1700
 
1701
// binary counter
1702 22 unneback
 
1703 40 unneback
`define MODULE cnt_bin
1704
module `BASE`MODULE (
1705
`undef MODULE
1706
 q, rst, clk);
1707
 
1708 22 unneback
   parameter length = 4;
1709
   output [length:1] q;
1710
   input rst;
1711
   input clk;
1712
 
1713
   parameter clear_value = 0;
1714
   parameter set_value = 1;
1715
   parameter wrap_value = 0;
1716
   parameter level1_value = 15;
1717
 
1718
   reg  [length:1] qi;
1719
   wire [length:1] q_next;
1720
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1721
 
1722
   always @ (posedge clk or posedge rst)
1723
     if (rst)
1724
       qi <= {length{1'b0}};
1725
     else
1726
       qi <= q_next;
1727
 
1728
   assign q = qi;
1729
 
1730
endmodule
1731 40 unneback
`endif
1732
`ifdef CNT_BIN_CLEAR
1733 22 unneback
//////////////////////////////////////////////////////////////////////
1734
////                                                              ////
1735
////  Versatile counter                                           ////
1736
////                                                              ////
1737
////  Description                                                 ////
1738
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1739
////  counter                                                     ////
1740
////                                                              ////
1741
////  To Do:                                                      ////
1742
////   - add LFSR with more taps                                  ////
1743
////                                                              ////
1744
////  Author(s):                                                  ////
1745
////      - Michael Unneback, unneback@opencores.org              ////
1746
////        ORSoC AB                                              ////
1747
////                                                              ////
1748
//////////////////////////////////////////////////////////////////////
1749
////                                                              ////
1750
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1751
////                                                              ////
1752
//// This source file may be used and distributed without         ////
1753
//// restriction provided that this copyright statement is not    ////
1754
//// removed from the file and that any derivative work contains  ////
1755
//// the original copyright notice and the associated disclaimer. ////
1756
////                                                              ////
1757
//// This source file is free software; you can redistribute it   ////
1758
//// and/or modify it under the terms of the GNU Lesser General   ////
1759
//// Public License as published by the Free Software Foundation; ////
1760
//// either version 2.1 of the License, or (at your option) any   ////
1761
//// later version.                                               ////
1762
////                                                              ////
1763
//// This source is distributed in the hope that it will be       ////
1764
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1765
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1766
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1767
//// details.                                                     ////
1768
////                                                              ////
1769
//// You should have received a copy of the GNU Lesser General    ////
1770
//// Public License along with this source; if not, download it   ////
1771
//// from http://www.opencores.org/lgpl.shtml                     ////
1772
////                                                              ////
1773
//////////////////////////////////////////////////////////////////////
1774
 
1775
// binary counter
1776
 
1777 40 unneback
`define MODULE cnt_bin_clear
1778
module `BASE`MODULE (
1779
`undef MODULE
1780
 clear, q, rst, clk);
1781
 
1782 22 unneback
   parameter length = 4;
1783
   input clear;
1784
   output [length:1] q;
1785
   input rst;
1786
   input clk;
1787
 
1788
   parameter clear_value = 0;
1789
   parameter set_value = 1;
1790
   parameter wrap_value = 0;
1791
   parameter level1_value = 15;
1792
 
1793
   reg  [length:1] qi;
1794
   wire [length:1] q_next;
1795
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1796
 
1797
   always @ (posedge clk or posedge rst)
1798
     if (rst)
1799
       qi <= {length{1'b0}};
1800
     else
1801
       qi <= q_next;
1802
 
1803
   assign q = qi;
1804
 
1805
endmodule
1806 40 unneback
`endif
1807
`ifdef CNT_BIN_CE
1808 22 unneback
//////////////////////////////////////////////////////////////////////
1809
////                                                              ////
1810
////  Versatile counter                                           ////
1811
////                                                              ////
1812
////  Description                                                 ////
1813
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1814
////  counter                                                     ////
1815
////                                                              ////
1816
////  To Do:                                                      ////
1817
////   - add LFSR with more taps                                  ////
1818
////                                                              ////
1819
////  Author(s):                                                  ////
1820
////      - Michael Unneback, unneback@opencores.org              ////
1821
////        ORSoC AB                                              ////
1822
////                                                              ////
1823
//////////////////////////////////////////////////////////////////////
1824
////                                                              ////
1825
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1826
////                                                              ////
1827
//// This source file may be used and distributed without         ////
1828
//// restriction provided that this copyright statement is not    ////
1829
//// removed from the file and that any derivative work contains  ////
1830
//// the original copyright notice and the associated disclaimer. ////
1831
////                                                              ////
1832
//// This source file is free software; you can redistribute it   ////
1833
//// and/or modify it under the terms of the GNU Lesser General   ////
1834
//// Public License as published by the Free Software Foundation; ////
1835
//// either version 2.1 of the License, or (at your option) any   ////
1836
//// later version.                                               ////
1837
////                                                              ////
1838
//// This source is distributed in the hope that it will be       ////
1839
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1840
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1841
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1842
//// details.                                                     ////
1843
////                                                              ////
1844
//// You should have received a copy of the GNU Lesser General    ////
1845
//// Public License along with this source; if not, download it   ////
1846
//// from http://www.opencores.org/lgpl.shtml                     ////
1847
////                                                              ////
1848
//////////////////////////////////////////////////////////////////////
1849
 
1850
// binary counter
1851 6 unneback
 
1852 40 unneback
`define MODULE cnt_bin_ce
1853
module `BASE`MODULE (
1854
`undef MODULE
1855
 cke, q, rst, clk);
1856
 
1857 6 unneback
   parameter length = 4;
1858
   input cke;
1859
   output [length:1] q;
1860
   input rst;
1861
   input clk;
1862
 
1863
   parameter clear_value = 0;
1864
   parameter set_value = 1;
1865
   parameter wrap_value = 0;
1866
   parameter level1_value = 15;
1867
 
1868
   reg  [length:1] qi;
1869
   wire [length:1] q_next;
1870
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1871
 
1872
   always @ (posedge clk or posedge rst)
1873
     if (rst)
1874
       qi <= {length{1'b0}};
1875
     else
1876
     if (cke)
1877
       qi <= q_next;
1878
 
1879
   assign q = qi;
1880
 
1881
endmodule
1882 40 unneback
`endif
1883
`ifdef CNT_BIN_CE_CLEAR
1884 6 unneback
//////////////////////////////////////////////////////////////////////
1885
////                                                              ////
1886
////  Versatile counter                                           ////
1887
////                                                              ////
1888
////  Description                                                 ////
1889
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1890
////  counter                                                     ////
1891
////                                                              ////
1892
////  To Do:                                                      ////
1893
////   - add LFSR with more taps                                  ////
1894
////                                                              ////
1895
////  Author(s):                                                  ////
1896
////      - Michael Unneback, unneback@opencores.org              ////
1897
////        ORSoC AB                                              ////
1898
////                                                              ////
1899
//////////////////////////////////////////////////////////////////////
1900
////                                                              ////
1901
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1902
////                                                              ////
1903
//// This source file may be used and distributed without         ////
1904
//// restriction provided that this copyright statement is not    ////
1905
//// removed from the file and that any derivative work contains  ////
1906
//// the original copyright notice and the associated disclaimer. ////
1907
////                                                              ////
1908
//// This source file is free software; you can redistribute it   ////
1909
//// and/or modify it under the terms of the GNU Lesser General   ////
1910
//// Public License as published by the Free Software Foundation; ////
1911
//// either version 2.1 of the License, or (at your option) any   ////
1912
//// later version.                                               ////
1913
////                                                              ////
1914
//// This source is distributed in the hope that it will be       ////
1915
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1916
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1917
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1918
//// details.                                                     ////
1919
////                                                              ////
1920
//// You should have received a copy of the GNU Lesser General    ////
1921
//// Public License along with this source; if not, download it   ////
1922
//// from http://www.opencores.org/lgpl.shtml                     ////
1923
////                                                              ////
1924
//////////////////////////////////////////////////////////////////////
1925
 
1926
// binary counter
1927
 
1928 40 unneback
`define MODULE cnt_bin_ce_clear
1929
module `BASE`MODULE (
1930
`undef MODULE
1931
 clear, cke, q, rst, clk);
1932
 
1933 6 unneback
   parameter length = 4;
1934
   input clear;
1935
   input cke;
1936
   output [length:1] q;
1937
   input rst;
1938
   input clk;
1939
 
1940
   parameter clear_value = 0;
1941
   parameter set_value = 1;
1942
   parameter wrap_value = 0;
1943
   parameter level1_value = 15;
1944
 
1945
   reg  [length:1] qi;
1946
   wire [length:1] q_next;
1947
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1948
 
1949
   always @ (posedge clk or posedge rst)
1950
     if (rst)
1951
       qi <= {length{1'b0}};
1952
     else
1953
     if (cke)
1954
       qi <= q_next;
1955
 
1956
   assign q = qi;
1957
 
1958
endmodule
1959 40 unneback
`endif
1960
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1961 6 unneback
//////////////////////////////////////////////////////////////////////
1962
////                                                              ////
1963
////  Versatile counter                                           ////
1964
////                                                              ////
1965
////  Description                                                 ////
1966
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1967
////  counter                                                     ////
1968
////                                                              ////
1969
////  To Do:                                                      ////
1970
////   - add LFSR with more taps                                  ////
1971
////                                                              ////
1972
////  Author(s):                                                  ////
1973
////      - Michael Unneback, unneback@opencores.org              ////
1974
////        ORSoC AB                                              ////
1975
////                                                              ////
1976
//////////////////////////////////////////////////////////////////////
1977
////                                                              ////
1978
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1979
////                                                              ////
1980
//// This source file may be used and distributed without         ////
1981
//// restriction provided that this copyright statement is not    ////
1982
//// removed from the file and that any derivative work contains  ////
1983
//// the original copyright notice and the associated disclaimer. ////
1984
////                                                              ////
1985
//// This source file is free software; you can redistribute it   ////
1986
//// and/or modify it under the terms of the GNU Lesser General   ////
1987
//// Public License as published by the Free Software Foundation; ////
1988
//// either version 2.1 of the License, or (at your option) any   ////
1989
//// later version.                                               ////
1990
////                                                              ////
1991
//// This source is distributed in the hope that it will be       ////
1992
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1993
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1994
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1995
//// details.                                                     ////
1996
////                                                              ////
1997
//// You should have received a copy of the GNU Lesser General    ////
1998
//// Public License along with this source; if not, download it   ////
1999
//// from http://www.opencores.org/lgpl.shtml                     ////
2000
////                                                              ////
2001
//////////////////////////////////////////////////////////////////////
2002
 
2003
// binary counter
2004 29 unneback
 
2005 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
2006
module `BASE`MODULE (
2007
`undef MODULE
2008
 clear, cke, q, level1, level2, rst, clk);
2009
 
2010 29 unneback
   parameter length = 4;
2011
   input clear;
2012
   input cke;
2013
   output [length:1] q;
2014
   output reg level1;
2015
   output reg level2;
2016
   input rst;
2017
   input clk;
2018
 
2019
   parameter clear_value = 0;
2020
   parameter set_value = 1;
2021 30 unneback
   parameter wrap_value = 15;
2022
   parameter level1_value = 8;
2023
   parameter level2_value = 15;
2024 29 unneback
 
2025
   wire rew;
2026 30 unneback
   assign rew = 1'b0;
2027 29 unneback
   reg  [length:1] qi;
2028
   wire [length:1] q_next;
2029
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2030
 
2031
   always @ (posedge clk or posedge rst)
2032
     if (rst)
2033
       qi <= {length{1'b0}};
2034
     else
2035
     if (cke)
2036
       qi <= q_next;
2037
 
2038
   assign q = qi;
2039
 
2040
 
2041
    always @ (posedge clk or posedge rst)
2042
    if (rst)
2043
        level1 <= 1'b0;
2044
    else
2045
    if (cke)
2046
    if (clear)
2047
        level1 <= 1'b0;
2048
    else if (q_next == level1_value)
2049
        level1 <= 1'b1;
2050
    else if (qi == level1_value & rew)
2051
        level1 <= 1'b0;
2052
 
2053
    always @ (posedge clk or posedge rst)
2054
    if (rst)
2055
        level2 <= 1'b0;
2056
    else
2057
    if (cke)
2058
    if (clear)
2059
        level2 <= 1'b0;
2060
    else if (q_next == level2_value)
2061
        level2 <= 1'b1;
2062
    else if (qi == level2_value & rew)
2063
        level2 <= 1'b0;
2064
endmodule
2065 40 unneback
`endif
2066
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2067 29 unneback
//////////////////////////////////////////////////////////////////////
2068
////                                                              ////
2069
////  Versatile counter                                           ////
2070
////                                                              ////
2071
////  Description                                                 ////
2072
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2073
////  counter                                                     ////
2074
////                                                              ////
2075
////  To Do:                                                      ////
2076
////   - add LFSR with more taps                                  ////
2077
////                                                              ////
2078
////  Author(s):                                                  ////
2079
////      - Michael Unneback, unneback@opencores.org              ////
2080
////        ORSoC AB                                              ////
2081
////                                                              ////
2082
//////////////////////////////////////////////////////////////////////
2083
////                                                              ////
2084
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2085
////                                                              ////
2086
//// This source file may be used and distributed without         ////
2087
//// restriction provided that this copyright statement is not    ////
2088
//// removed from the file and that any derivative work contains  ////
2089
//// the original copyright notice and the associated disclaimer. ////
2090
////                                                              ////
2091
//// This source file is free software; you can redistribute it   ////
2092
//// and/or modify it under the terms of the GNU Lesser General   ////
2093
//// Public License as published by the Free Software Foundation; ////
2094
//// either version 2.1 of the License, or (at your option) any   ////
2095
//// later version.                                               ////
2096
////                                                              ////
2097
//// This source is distributed in the hope that it will be       ////
2098
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2099
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2100
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2101
//// details.                                                     ////
2102
////                                                              ////
2103
//// You should have received a copy of the GNU Lesser General    ////
2104
//// Public License along with this source; if not, download it   ////
2105
//// from http://www.opencores.org/lgpl.shtml                     ////
2106
////                                                              ////
2107
//////////////////////////////////////////////////////////////////////
2108
 
2109
// binary counter
2110 6 unneback
 
2111 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2112
module `BASE`MODULE (
2113
`undef MODULE
2114
 clear, set, cke, rew, q, rst, clk);
2115
 
2116 6 unneback
   parameter length = 4;
2117
   input clear;
2118
   input set;
2119
   input cke;
2120
   input rew;
2121
   output [length:1] q;
2122
   input rst;
2123
   input clk;
2124
 
2125
   parameter clear_value = 0;
2126
   parameter set_value = 1;
2127
   parameter wrap_value = 0;
2128
   parameter level1_value = 15;
2129
 
2130
   reg  [length:1] qi;
2131
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2132
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2133
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2134
   assign q_next = rew ? q_next_rew : q_next_fw;
2135
 
2136
   always @ (posedge clk or posedge rst)
2137
     if (rst)
2138
       qi <= {length{1'b0}};
2139
     else
2140
     if (cke)
2141
       qi <= q_next;
2142
 
2143
   assign q = qi;
2144
 
2145
endmodule
2146 40 unneback
`endif
2147
`ifdef CNT_BIN_CE_REW_L1
2148 6 unneback
//////////////////////////////////////////////////////////////////////
2149
////                                                              ////
2150
////  Versatile counter                                           ////
2151
////                                                              ////
2152
////  Description                                                 ////
2153
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2154
////  counter                                                     ////
2155
////                                                              ////
2156
////  To Do:                                                      ////
2157
////   - add LFSR with more taps                                  ////
2158
////                                                              ////
2159
////  Author(s):                                                  ////
2160
////      - Michael Unneback, unneback@opencores.org              ////
2161
////        ORSoC AB                                              ////
2162
////                                                              ////
2163
//////////////////////////////////////////////////////////////////////
2164
////                                                              ////
2165
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2166
////                                                              ////
2167
//// This source file may be used and distributed without         ////
2168
//// restriction provided that this copyright statement is not    ////
2169
//// removed from the file and that any derivative work contains  ////
2170
//// the original copyright notice and the associated disclaimer. ////
2171
////                                                              ////
2172
//// This source file is free software; you can redistribute it   ////
2173
//// and/or modify it under the terms of the GNU Lesser General   ////
2174
//// Public License as published by the Free Software Foundation; ////
2175
//// either version 2.1 of the License, or (at your option) any   ////
2176
//// later version.                                               ////
2177
////                                                              ////
2178
//// This source is distributed in the hope that it will be       ////
2179
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2180
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2181
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2182
//// details.                                                     ////
2183
////                                                              ////
2184
//// You should have received a copy of the GNU Lesser General    ////
2185
//// Public License along with this source; if not, download it   ////
2186
//// from http://www.opencores.org/lgpl.shtml                     ////
2187
////                                                              ////
2188
//////////////////////////////////////////////////////////////////////
2189
 
2190
// binary counter
2191
 
2192 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2193
module `BASE`MODULE (
2194
`undef MODULE
2195
 cke, rew, level1, rst, clk);
2196
 
2197 6 unneback
   parameter length = 4;
2198
   input cke;
2199
   input rew;
2200
   output reg level1;
2201
   input rst;
2202
   input clk;
2203
 
2204
   parameter clear_value = 0;
2205
   parameter set_value = 1;
2206
   parameter wrap_value = 1;
2207
   parameter level1_value = 15;
2208
 
2209 29 unneback
   wire clear;
2210 30 unneback
   assign clear = 1'b0;
2211 6 unneback
   reg  [length:1] qi;
2212
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2213
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2214
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2215
   assign q_next = rew ? q_next_rew : q_next_fw;
2216
 
2217
   always @ (posedge clk or posedge rst)
2218
     if (rst)
2219
       qi <= {length{1'b0}};
2220
     else
2221
     if (cke)
2222
       qi <= q_next;
2223
 
2224
 
2225
 
2226
    always @ (posedge clk or posedge rst)
2227
    if (rst)
2228
        level1 <= 1'b0;
2229
    else
2230
    if (cke)
2231 29 unneback
    if (clear)
2232
        level1 <= 1'b0;
2233
    else if (q_next == level1_value)
2234 6 unneback
        level1 <= 1'b1;
2235
    else if (qi == level1_value & rew)
2236
        level1 <= 1'b0;
2237
endmodule
2238 40 unneback
`endif
2239
`ifdef CNT_BIN_CE_REW_ZQ_L1
2240 6 unneback
//////////////////////////////////////////////////////////////////////
2241
////                                                              ////
2242
////  Versatile counter                                           ////
2243
////                                                              ////
2244
////  Description                                                 ////
2245
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2246
////  counter                                                     ////
2247
////                                                              ////
2248
////  To Do:                                                      ////
2249
////   - add LFSR with more taps                                  ////
2250
////                                                              ////
2251
////  Author(s):                                                  ////
2252
////      - Michael Unneback, unneback@opencores.org              ////
2253
////        ORSoC AB                                              ////
2254
////                                                              ////
2255
//////////////////////////////////////////////////////////////////////
2256
////                                                              ////
2257
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2258
////                                                              ////
2259
//// This source file may be used and distributed without         ////
2260
//// restriction provided that this copyright statement is not    ////
2261
//// removed from the file and that any derivative work contains  ////
2262
//// the original copyright notice and the associated disclaimer. ////
2263
////                                                              ////
2264
//// This source file is free software; you can redistribute it   ////
2265
//// and/or modify it under the terms of the GNU Lesser General   ////
2266
//// Public License as published by the Free Software Foundation; ////
2267
//// either version 2.1 of the License, or (at your option) any   ////
2268
//// later version.                                               ////
2269
////                                                              ////
2270
//// This source is distributed in the hope that it will be       ////
2271
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2272
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2273
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2274
//// details.                                                     ////
2275
////                                                              ////
2276
//// You should have received a copy of the GNU Lesser General    ////
2277
//// Public License along with this source; if not, download it   ////
2278
//// from http://www.opencores.org/lgpl.shtml                     ////
2279
////                                                              ////
2280
//////////////////////////////////////////////////////////////////////
2281
 
2282 25 unneback
// binary counter
2283
 
2284 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2285
module `BASE`MODULE (
2286
`undef MODULE
2287
 cke, rew, zq, level1, rst, clk);
2288
 
2289 25 unneback
   parameter length = 4;
2290
   input cke;
2291
   input rew;
2292
   output reg zq;
2293
   output reg level1;
2294
   input rst;
2295
   input clk;
2296
 
2297
   parameter clear_value = 0;
2298
   parameter set_value = 1;
2299
   parameter wrap_value = 1;
2300
   parameter level1_value = 15;
2301
 
2302 29 unneback
   wire clear;
2303 30 unneback
   assign clear = 1'b0;
2304 25 unneback
   reg  [length:1] qi;
2305
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2306
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2307
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2308
   assign q_next = rew ? q_next_rew : q_next_fw;
2309
 
2310
   always @ (posedge clk or posedge rst)
2311
     if (rst)
2312
       qi <= {length{1'b0}};
2313
     else
2314
     if (cke)
2315
       qi <= q_next;
2316
 
2317
 
2318
 
2319
   always @ (posedge clk or posedge rst)
2320
     if (rst)
2321
       zq <= 1'b1;
2322
     else
2323
     if (cke)
2324
       zq <= q_next == {length{1'b0}};
2325
 
2326
    always @ (posedge clk or posedge rst)
2327
    if (rst)
2328
        level1 <= 1'b0;
2329
    else
2330
    if (cke)
2331 29 unneback
    if (clear)
2332
        level1 <= 1'b0;
2333
    else if (q_next == level1_value)
2334 25 unneback
        level1 <= 1'b1;
2335
    else if (qi == level1_value & rew)
2336
        level1 <= 1'b0;
2337
endmodule
2338 40 unneback
`endif
2339
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2340 25 unneback
//////////////////////////////////////////////////////////////////////
2341
////                                                              ////
2342
////  Versatile counter                                           ////
2343
////                                                              ////
2344
////  Description                                                 ////
2345
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2346
////  counter                                                     ////
2347
////                                                              ////
2348
////  To Do:                                                      ////
2349
////   - add LFSR with more taps                                  ////
2350
////                                                              ////
2351
////  Author(s):                                                  ////
2352
////      - Michael Unneback, unneback@opencores.org              ////
2353
////        ORSoC AB                                              ////
2354
////                                                              ////
2355
//////////////////////////////////////////////////////////////////////
2356
////                                                              ////
2357
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2358
////                                                              ////
2359
//// This source file may be used and distributed without         ////
2360
//// restriction provided that this copyright statement is not    ////
2361
//// removed from the file and that any derivative work contains  ////
2362
//// the original copyright notice and the associated disclaimer. ////
2363
////                                                              ////
2364
//// This source file is free software; you can redistribute it   ////
2365
//// and/or modify it under the terms of the GNU Lesser General   ////
2366
//// Public License as published by the Free Software Foundation; ////
2367
//// either version 2.1 of the License, or (at your option) any   ////
2368
//// later version.                                               ////
2369
////                                                              ////
2370
//// This source is distributed in the hope that it will be       ////
2371
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2372
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2373
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2374
//// details.                                                     ////
2375
////                                                              ////
2376
//// You should have received a copy of the GNU Lesser General    ////
2377
//// Public License along with this source; if not, download it   ////
2378
//// from http://www.opencores.org/lgpl.shtml                     ////
2379
////                                                              ////
2380
//////////////////////////////////////////////////////////////////////
2381
 
2382
// binary counter
2383
 
2384 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2385
module `BASE`MODULE (
2386
`undef MODULE
2387
 cke, rew, q, zq, level1, rst, clk);
2388
 
2389 25 unneback
   parameter length = 4;
2390
   input cke;
2391
   input rew;
2392
   output [length:1] q;
2393
   output reg zq;
2394
   output reg level1;
2395
   input rst;
2396
   input clk;
2397
 
2398
   parameter clear_value = 0;
2399
   parameter set_value = 1;
2400
   parameter wrap_value = 1;
2401
   parameter level1_value = 15;
2402
 
2403 29 unneback
   wire clear;
2404 30 unneback
   assign clear = 1'b0;
2405 25 unneback
   reg  [length:1] qi;
2406
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2407
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2408
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2409
   assign q_next = rew ? q_next_rew : q_next_fw;
2410
 
2411
   always @ (posedge clk or posedge rst)
2412
     if (rst)
2413
       qi <= {length{1'b0}};
2414
     else
2415
     if (cke)
2416
       qi <= q_next;
2417
 
2418
   assign q = qi;
2419
 
2420
 
2421
   always @ (posedge clk or posedge rst)
2422
     if (rst)
2423
       zq <= 1'b1;
2424
     else
2425
     if (cke)
2426
       zq <= q_next == {length{1'b0}};
2427
 
2428
    always @ (posedge clk or posedge rst)
2429
    if (rst)
2430
        level1 <= 1'b0;
2431
    else
2432
    if (cke)
2433 29 unneback
    if (clear)
2434
        level1 <= 1'b0;
2435
    else if (q_next == level1_value)
2436 25 unneback
        level1 <= 1'b1;
2437
    else if (qi == level1_value & rew)
2438
        level1 <= 1'b0;
2439
endmodule
2440 40 unneback
`endif
2441
`ifdef CNT_LFSR_ZQ
2442 25 unneback
//////////////////////////////////////////////////////////////////////
2443
////                                                              ////
2444
////  Versatile counter                                           ////
2445
////                                                              ////
2446
////  Description                                                 ////
2447
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2448
////  counter                                                     ////
2449
////                                                              ////
2450
////  To Do:                                                      ////
2451
////   - add LFSR with more taps                                  ////
2452
////                                                              ////
2453
////  Author(s):                                                  ////
2454
////      - Michael Unneback, unneback@opencores.org              ////
2455
////        ORSoC AB                                              ////
2456
////                                                              ////
2457
//////////////////////////////////////////////////////////////////////
2458
////                                                              ////
2459
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2460
////                                                              ////
2461
//// This source file may be used and distributed without         ////
2462
//// restriction provided that this copyright statement is not    ////
2463
//// removed from the file and that any derivative work contains  ////
2464
//// the original copyright notice and the associated disclaimer. ////
2465
////                                                              ////
2466
//// This source file is free software; you can redistribute it   ////
2467
//// and/or modify it under the terms of the GNU Lesser General   ////
2468
//// Public License as published by the Free Software Foundation; ////
2469
//// either version 2.1 of the License, or (at your option) any   ////
2470
//// later version.                                               ////
2471
////                                                              ////
2472
//// This source is distributed in the hope that it will be       ////
2473
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2474
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2475
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2476
//// details.                                                     ////
2477
////                                                              ////
2478
//// You should have received a copy of the GNU Lesser General    ////
2479
//// Public License along with this source; if not, download it   ////
2480
//// from http://www.opencores.org/lgpl.shtml                     ////
2481
////                                                              ////
2482
//////////////////////////////////////////////////////////////////////
2483
 
2484 6 unneback
// LFSR counter
2485
 
2486 40 unneback
`define MODULE cnt_lfsr_zq
2487
module `BASE`MODULE (
2488
`undef MODULE
2489
 zq, rst, clk);
2490
 
2491 6 unneback
   parameter length = 4;
2492
   output reg zq;
2493
   input rst;
2494
   input clk;
2495
 
2496
   parameter clear_value = 0;
2497
   parameter set_value = 1;
2498
   parameter wrap_value = 8;
2499
   parameter level1_value = 15;
2500
 
2501
   reg  [length:1] qi;
2502
   reg lfsr_fb;
2503
   wire [length:1] q_next;
2504
   reg [32:1] polynom;
2505
   integer i;
2506
 
2507
   always @ (qi)
2508
   begin
2509
        case (length)
2510
         2: polynom = 32'b11;                               // 0x3
2511
         3: polynom = 32'b110;                              // 0x6
2512
         4: polynom = 32'b1100;                             // 0xC
2513
         5: polynom = 32'b10100;                            // 0x14
2514
         6: polynom = 32'b110000;                           // 0x30
2515
         7: polynom = 32'b1100000;                          // 0x60
2516
         8: polynom = 32'b10111000;                         // 0xb8
2517
         9: polynom = 32'b100010000;                        // 0x110
2518
        10: polynom = 32'b1001000000;                       // 0x240
2519
        11: polynom = 32'b10100000000;                      // 0x500
2520
        12: polynom = 32'b100000101001;                     // 0x829
2521
        13: polynom = 32'b1000000001100;                    // 0x100C
2522
        14: polynom = 32'b10000000010101;                   // 0x2015
2523
        15: polynom = 32'b110000000000000;                  // 0x6000
2524
        16: polynom = 32'b1101000000001000;                 // 0xD008
2525
        17: polynom = 32'b10010000000000000;                // 0x12000
2526
        18: polynom = 32'b100000010000000000;               // 0x20400
2527
        19: polynom = 32'b1000000000000100011;              // 0x40023
2528 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2529 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2530
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2531
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2532
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2533
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2534
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2535
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2536
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2537
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2538
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2539
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2540
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2541
        default: polynom = 32'b0;
2542
        endcase
2543
        lfsr_fb = qi[length];
2544
        for (i=length-1; i>=1; i=i-1) begin
2545
            if (polynom[i])
2546
                lfsr_fb = lfsr_fb  ~^ qi[i];
2547
        end
2548
    end
2549
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2550
 
2551
   always @ (posedge clk or posedge rst)
2552
     if (rst)
2553
       qi <= {length{1'b0}};
2554
     else
2555
       qi <= q_next;
2556
 
2557
 
2558
 
2559
   always @ (posedge clk or posedge rst)
2560
     if (rst)
2561
       zq <= 1'b1;
2562
     else
2563
       zq <= q_next == {length{1'b0}};
2564
endmodule
2565 40 unneback
`endif
2566 75 unneback
`ifdef CNT_LFSR_CE
2567
//////////////////////////////////////////////////////////////////////
2568
////                                                              ////
2569
////  Versatile counter                                           ////
2570
////                                                              ////
2571
////  Description                                                 ////
2572
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2573
////  counter                                                     ////
2574
////                                                              ////
2575
////  To Do:                                                      ////
2576
////   - add LFSR with more taps                                  ////
2577
////                                                              ////
2578
////  Author(s):                                                  ////
2579
////      - Michael Unneback, unneback@opencores.org              ////
2580
////        ORSoC AB                                              ////
2581
////                                                              ////
2582
//////////////////////////////////////////////////////////////////////
2583
////                                                              ////
2584
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2585
////                                                              ////
2586
//// This source file may be used and distributed without         ////
2587
//// restriction provided that this copyright statement is not    ////
2588
//// removed from the file and that any derivative work contains  ////
2589
//// the original copyright notice and the associated disclaimer. ////
2590
////                                                              ////
2591
//// This source file is free software; you can redistribute it   ////
2592
//// and/or modify it under the terms of the GNU Lesser General   ////
2593
//// Public License as published by the Free Software Foundation; ////
2594
//// either version 2.1 of the License, or (at your option) any   ////
2595
//// later version.                                               ////
2596
////                                                              ////
2597
//// This source is distributed in the hope that it will be       ////
2598
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2599
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2600
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2601
//// details.                                                     ////
2602
////                                                              ////
2603
//// You should have received a copy of the GNU Lesser General    ////
2604
//// Public License along with this source; if not, download it   ////
2605
//// from http://www.opencores.org/lgpl.shtml                     ////
2606
////                                                              ////
2607
//////////////////////////////////////////////////////////////////////
2608
 
2609
// LFSR counter
2610
 
2611
`define MODULE cnt_lfsr_ce
2612
module `BASE`MODULE (
2613
`undef MODULE
2614
 cke, zq, rst, clk);
2615
 
2616
   parameter length = 4;
2617
   input cke;
2618
   output reg zq;
2619
   input rst;
2620
   input clk;
2621
 
2622
   parameter clear_value = 0;
2623
   parameter set_value = 1;
2624
   parameter wrap_value = 0;
2625
   parameter level1_value = 15;
2626
 
2627
   reg  [length:1] qi;
2628
   reg lfsr_fb;
2629
   wire [length:1] q_next;
2630
   reg [32:1] polynom;
2631
   integer i;
2632
 
2633
   always @ (qi)
2634
   begin
2635
        case (length)
2636
         2: polynom = 32'b11;                               // 0x3
2637
         3: polynom = 32'b110;                              // 0x6
2638
         4: polynom = 32'b1100;                             // 0xC
2639
         5: polynom = 32'b10100;                            // 0x14
2640
         6: polynom = 32'b110000;                           // 0x30
2641
         7: polynom = 32'b1100000;                          // 0x60
2642
         8: polynom = 32'b10111000;                         // 0xb8
2643
         9: polynom = 32'b100010000;                        // 0x110
2644
        10: polynom = 32'b1001000000;                       // 0x240
2645
        11: polynom = 32'b10100000000;                      // 0x500
2646
        12: polynom = 32'b100000101001;                     // 0x829
2647
        13: polynom = 32'b1000000001100;                    // 0x100C
2648
        14: polynom = 32'b10000000010101;                   // 0x2015
2649
        15: polynom = 32'b110000000000000;                  // 0x6000
2650
        16: polynom = 32'b1101000000001000;                 // 0xD008
2651
        17: polynom = 32'b10010000000000000;                // 0x12000
2652
        18: polynom = 32'b100000010000000000;               // 0x20400
2653
        19: polynom = 32'b1000000000000100011;              // 0x40023
2654
        20: polynom = 32'b10010000000000000000;             // 0x90000
2655
        21: polynom = 32'b101000000000000000000;            // 0x140000
2656
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2657
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2658
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2659
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2660
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2661
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2662
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2663
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2664
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2665
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2666
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2667
        default: polynom = 32'b0;
2668
        endcase
2669
        lfsr_fb = qi[length];
2670
        for (i=length-1; i>=1; i=i-1) begin
2671
            if (polynom[i])
2672
                lfsr_fb = lfsr_fb  ~^ qi[i];
2673
        end
2674
    end
2675
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2676
 
2677
   always @ (posedge clk or posedge rst)
2678
     if (rst)
2679
       qi <= {length{1'b0}};
2680
     else
2681
     if (cke)
2682
       qi <= q_next;
2683
 
2684
 
2685
 
2686
   always @ (posedge clk or posedge rst)
2687
     if (rst)
2688
       zq <= 1'b1;
2689
     else
2690
     if (cke)
2691
       zq <= q_next == {length{1'b0}};
2692
endmodule
2693
`endif
2694 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2695 6 unneback
//////////////////////////////////////////////////////////////////////
2696
////                                                              ////
2697
////  Versatile counter                                           ////
2698
////                                                              ////
2699
////  Description                                                 ////
2700
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2701
////  counter                                                     ////
2702
////                                                              ////
2703
////  To Do:                                                      ////
2704
////   - add LFSR with more taps                                  ////
2705
////                                                              ////
2706
////  Author(s):                                                  ////
2707
////      - Michael Unneback, unneback@opencores.org              ////
2708
////        ORSoC AB                                              ////
2709
////                                                              ////
2710
//////////////////////////////////////////////////////////////////////
2711
////                                                              ////
2712
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2713
////                                                              ////
2714
//// This source file may be used and distributed without         ////
2715
//// restriction provided that this copyright statement is not    ////
2716
//// removed from the file and that any derivative work contains  ////
2717
//// the original copyright notice and the associated disclaimer. ////
2718
////                                                              ////
2719
//// This source file is free software; you can redistribute it   ////
2720
//// and/or modify it under the terms of the GNU Lesser General   ////
2721
//// Public License as published by the Free Software Foundation; ////
2722
//// either version 2.1 of the License, or (at your option) any   ////
2723
//// later version.                                               ////
2724
////                                                              ////
2725
//// This source is distributed in the hope that it will be       ////
2726
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2727
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2728
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2729
//// details.                                                     ////
2730
////                                                              ////
2731
//// You should have received a copy of the GNU Lesser General    ////
2732
//// Public License along with this source; if not, download it   ////
2733
//// from http://www.opencores.org/lgpl.shtml                     ////
2734
////                                                              ////
2735
//////////////////////////////////////////////////////////////////////
2736
 
2737
// LFSR counter
2738
 
2739 40 unneback
`define MODULE cnt_lfsr_ce_zq
2740
module `BASE`MODULE (
2741
`undef MODULE
2742
 cke, zq, rst, clk);
2743
 
2744 6 unneback
   parameter length = 4;
2745
   input cke;
2746
   output reg zq;
2747
   input rst;
2748
   input clk;
2749
 
2750
   parameter clear_value = 0;
2751
   parameter set_value = 1;
2752
   parameter wrap_value = 8;
2753
   parameter level1_value = 15;
2754
 
2755
   reg  [length:1] qi;
2756
   reg lfsr_fb;
2757
   wire [length:1] q_next;
2758
   reg [32:1] polynom;
2759
   integer i;
2760
 
2761
   always @ (qi)
2762
   begin
2763
        case (length)
2764
         2: polynom = 32'b11;                               // 0x3
2765
         3: polynom = 32'b110;                              // 0x6
2766
         4: polynom = 32'b1100;                             // 0xC
2767
         5: polynom = 32'b10100;                            // 0x14
2768
         6: polynom = 32'b110000;                           // 0x30
2769
         7: polynom = 32'b1100000;                          // 0x60
2770
         8: polynom = 32'b10111000;                         // 0xb8
2771
         9: polynom = 32'b100010000;                        // 0x110
2772
        10: polynom = 32'b1001000000;                       // 0x240
2773
        11: polynom = 32'b10100000000;                      // 0x500
2774
        12: polynom = 32'b100000101001;                     // 0x829
2775
        13: polynom = 32'b1000000001100;                    // 0x100C
2776
        14: polynom = 32'b10000000010101;                   // 0x2015
2777
        15: polynom = 32'b110000000000000;                  // 0x6000
2778
        16: polynom = 32'b1101000000001000;                 // 0xD008
2779
        17: polynom = 32'b10010000000000000;                // 0x12000
2780
        18: polynom = 32'b100000010000000000;               // 0x20400
2781
        19: polynom = 32'b1000000000000100011;              // 0x40023
2782 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2783 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2784
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2785
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2786
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2787
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2788
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2789
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2790
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2791
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2792
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2793
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2794
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2795
        default: polynom = 32'b0;
2796
        endcase
2797
        lfsr_fb = qi[length];
2798
        for (i=length-1; i>=1; i=i-1) begin
2799
            if (polynom[i])
2800
                lfsr_fb = lfsr_fb  ~^ qi[i];
2801
        end
2802
    end
2803
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2804
 
2805
   always @ (posedge clk or posedge rst)
2806
     if (rst)
2807
       qi <= {length{1'b0}};
2808
     else
2809
     if (cke)
2810
       qi <= q_next;
2811
 
2812
 
2813
 
2814
   always @ (posedge clk or posedge rst)
2815
     if (rst)
2816
       zq <= 1'b1;
2817
     else
2818
     if (cke)
2819
       zq <= q_next == {length{1'b0}};
2820
endmodule
2821 40 unneback
`endif
2822
`ifdef CNT_LFSR_CE_Q
2823 6 unneback
//////////////////////////////////////////////////////////////////////
2824
////                                                              ////
2825
////  Versatile counter                                           ////
2826
////                                                              ////
2827
////  Description                                                 ////
2828
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2829
////  counter                                                     ////
2830
////                                                              ////
2831
////  To Do:                                                      ////
2832
////   - add LFSR with more taps                                  ////
2833
////