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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 124

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 98 unneback 
`ifdef ACTEL
14 
    // ACTEL FPGA should not use logic to handle rw collision
15 
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16 
`else
17 
    `define SYN_NO_RW_CHECK
18 
`endif
19 
 
20 40 unneback 
`ifdef ALL
21 
 
22 
`define GBUF
23 
`define SYNC_RST
24 
`define PLL
25 
 
26 
`define MULTS
27 
`define MULTS18X18
28 
`define MULT
29 
`define SHIFT_UNIT_32
30 
`define LOGIC_UNIT
31 
 
32 
`define CNT_SHREG_WRAP
33 
`define CNT_SHREG_CE_WRAP
34 105 unneback 
`define CNT_SHREG_CLEAR
35 40 unneback 
`define CNT_SHREG_CE_CLEAR
36 
`define CNT_SHREG_CE_CLEAR_WRAP
37 
 
38 
`define MUX_ANDOR
39 
`define MUX2_ANDOR
40 
`define MUX3_ANDOR
41 
`define MUX4_ANDOR
42 
`define MUX5_ANDOR
43 
`define MUX6_ANDOR
44 43 unneback 
`define PARITY
45 40 unneback 
 
46 
`define ROM_INIT
47 
`define RAM
48 
`define RAM_BE
49 
`define DPRAM_1R1W
50 
`define DPRAM_2R1W
51 100 unneback 
`define DPRAM_1R2W
52 40 unneback 
`define DPRAM_2R2W
53 75 unneback 
`define DPRAM_BE_2R2W
54 40 unneback 
`define FIFO_1R1W_FILL_LEVEL_SYNC
55 
`define FIFO_2R2W_SYNC_SIMPLEX
56 
`define FIFO_CMP_ASYNC
57 
`define FIFO_1R1W_ASYNC
58 
`define FIFO_2R2W_ASYNC
59 
`define FIFO_2R2W_ASYNC_SIMPLEX
60 48 unneback 
`define REG_FILE
61 40 unneback 
 
62 
`define DFF
63 
`define DFF_ARRAY
64 
`define DFF_CE
65 
`define DFF_CE_CLEAR
66 
`define DF_CE_SET
67 
`define SPR
68 
`define SRP
69 
`define DFF_SR
70 
`define LATCH
71 
`define SHREG
72 
`define SHREG_CE
73 
`define DELAY
74 
`define DELAY_EMPTYFLAG
75 94 unneback 
`define PULSE2TOGGLE
76 
`define TOGGLE2PULSE
77 
`define SYNCHRONIZER
78 
`define CDC
79 40 unneback 
 
80 75 unneback 
`define WB3AVALON_BRIDGE
81 40 unneback 
`define WB3WB3_BRIDGE
82 
`define WB3_ARBITER_TYPE1
83 83 unneback 
`define WB_ADR_INC
84 101 unneback 
`define WB_RAM
85 103 unneback 
`define WB_SHADOW_RAM
86 48 unneback 
`define WB_B4_ROM
87 40 unneback 
`define WB_BOOT_ROM
88 
`define WB_DPRAM
89 101 unneback 
`define WB_CACHE
90 103 unneback 
`define WB_AVALON_BRIDGE
91 
`define WB_AVALON_MEM_CACHE
92 40 unneback 
 
93 44 unneback 
`define IO_DFF_OE
94 
`define O_DFF
95 
 
96 40 unneback 
`endif
97 
 
98 
`ifdef PLL
99 
`ifndef SYNC_RST
100 
`define SYNC_RST
101 
`endif
102 
`endif
103 
 
104 
`ifdef SYNC_RST
105 
`ifndef GBUF
106 
`define GBUF
107 
`endif
108 
`endif
109 
 
110 108 unneback 
`ifdef WB_DPRAM
111 92 unneback 
`ifndef WB_ADR_INC
112 
`define WB_ADR_INC
113 40 unneback 
`endif
114 92 unneback 
`ifndef DPRAM_BE_2R2W
115 
`define DPRAM_BE_2R2W
116 40 unneback 
`endif
117 
`endif
118 
 
119 
`ifdef WB3_ARBITER_TYPE1
120 42 unneback 
`ifndef SPR
121 
`define SPR
122 
`endif
123 40 unneback 
`ifndef MUX_ANDOR
124 
`define MUX_ANDOR
125 
`endif
126 
`endif
127 
 
128 76 unneback 
`ifdef WB3AVALON_BRIDGE
129 
`ifndef WB3WB3_BRIDGE
130 
`define WB3WB3_BRIDGE
131 
`endif
132 
`endif
133 
 
134 40 unneback 
`ifdef WB3WB3_BRIDGE
135 
`ifndef CNT_SHREG_CE_CLEAR
136 
`define CNT_SHREG_CE_CLEAR
137 
`endif
138 
`ifndef DFF
139 
`define DFF
140 
`endif
141 
`ifndef DFF_CE
142 
`define DFF_CE
143 
`endif
144 
`ifndef CNT_SHREG_CE_CLEAR
145 
`define CNT_SHREG_CE_CLEAR
146 
`endif
147 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
148 
`define FIFO_2R2W_ASYNC_SIMPLEX
149 
`endif
150 
`endif
151 
 
152 103 unneback 
 
153 
`ifdef WB_AVALON_MEM_CACHE
154 
`ifndef WB_SHADOW_RAM
155 
`define WB_SHADOW_RAM
156 
`endif
157 
`ifndef WB_CACHE
158 
`define WB_CACHE
159 
`endif
160 
`ifndef WB_AVALON_BRIDGE
161 
`define WB_AVALON_BRIDGE
162 
`endif
163 
`endif
164 
 
165 101 unneback 
`ifdef WB_CACHE
166 100 unneback 
`ifndef RAM
167 
`define RAM
168 
`endif
169 
`ifndef WB_ADR_INC
170 
`define WB_ADR_INC
171 
`endif
172 
`ifndef DPRAM_1R1W
173 
`define DPRAM_1R1W
174 
`endif
175 
`ifndef DPRAM_1R2W
176 
`define DPRAM_1R2W
177 
`endif
178 
`ifndef DPRAM_BE_2R2W
179 
`define DPRAM_BE_2R2W
180 
`endif
181 
`ifndef CDC
182 
`define CDC
183 
`endif
184 
`endif
185 103 unneback 
 
186 
`ifdef WB_SHADOW_RAM
187 115 unneback 
`ifndef WB_RAM
188 
`define WB_RAM
189 103 unneback 
`endif
190 
`endif
191 
 
192 
`ifdef WB_RAM
193 
`ifndef WB_ADR_INC
194 
`define WB_ADR_INC
195 
`endif
196 114 unneback 
`ifndef RAM_BE
197 
`define RAM_BE
198 103 unneback 
`endif
199 114 unneback 
`endif
200 
 
201 40 unneback 
`ifdef MULTS18X18
202 
`ifndef MULTS
203 
`define MULTS
204 
`endif
205 
`endif
206 
 
207 
`ifdef SHIFT_UNIT_32
208 
`ifndef MULTS
209 
`define MULTS
210 
`endif
211 
`endif
212 
 
213 
`ifdef MUX2_ANDOR
214 
`ifndef MUX_ANDOR
215 
`define MUX_ANDOR
216 
`endif
217 
`endif
218 
 
219 
`ifdef MUX3_ANDOR
220 
`ifndef MUX_ANDOR
221 
`define MUX_ANDOR
222 
`endif
223 
`endif
224 
 
225 
`ifdef MUX4_ANDOR
226 
`ifndef MUX_ANDOR
227 
`define MUX_ANDOR
228 
`endif
229 
`endif
230 
 
231 
`ifdef MUX5_ANDOR
232 
`ifndef MUX_ANDOR
233 
`define MUX_ANDOR
234 
`endif
235 
`endif
236 
 
237 
`ifdef MUX6_ANDOR
238 
`ifndef MUX_ANDOR
239 
`define MUX_ANDOR
240 
`endif
241 
`endif
242 
 
243 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
244 
`ifndef CNT_BIN_CE
245 
`define CNT_BIN_CE
246 
`endif
247 
`ifndef DPRAM_1R1W
248 
`define DPRAM_1R1W
249 
`endif
250 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
251 
`define CNT_BIN_CE_REW_Q_ZQ_L1
252 
`endif
253 
`endif
254 
 
255 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
256 
`ifndef CNT_LFSR_CE
257 
`define CNT_LFSR_CE
258 
`endif
259 
`ifndef DPRAM_2R2W
260 
`define DPRAM_2R2W
261 
`endif
262 
`ifndef CNT_BIN_CE_REW_ZQ_L1
263 
`define CNT_BIN_CE_REW_ZQ_L1
264 
`endif
265 
`endif
266 
 
267 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
268 
`ifndef CNT_GRAY_CE_BIN
269 
`define CNT_GRAY_CE_BIN
270 
`endif
271 
`ifndef DPRAM_2R2W
272 
`define DPRAM_2R2W
273 
`endif
274 
`ifndef FIFO_CMP_ASYNC
275 
`define FIFO_CMP_ASYNC
276 
`endif
277 
`endif
278 
 
279 
`ifdef FIFO_2R2W_ASYNC
280 
`ifndef FIFO_1R1W_ASYNC
281 
`define FIFO_1R1W_ASYNC
282 
`endif
283 
`endif
284 
 
285 
`ifdef FIFO_1R1W_ASYNC
286 
`ifndef CNT_GRAY_CE_BIN
287 
`define CNT_GRAY_CE_BIN
288 
`endif
289 
`ifndef DPRAM_1R1W
290 
`define DPRAM_1R1W
291 
`endif
292 
`ifndef FIFO_CMP_ASYNC
293 
`define FIFO_CMP_ASYNC
294 
`endif
295 
`endif
296 
 
297 
`ifdef FIFO_CMP_ASYNC
298 
`ifndef DFF_SR
299 
`define DFF_SR
300 
`endif
301 
`ifndef DFF
302 
`define DFF
303 
`endif
304 
`endif
305 48 unneback 
 
306 
`ifdef REG_FILE
307 
`ifndef DPRAM_1R1W
308 
`define DPRAM_1R1W
309 
`endif
310 
`endif
311 97 unneback 
 
312 98 unneback 
`ifdef CDC
313 
`ifndef PULSE2TOGGLE
314 
`define PULSE2TOGGLE
315 
`endif
316 
`ifndef TOGGLE2PULSE
317 
`define TOGGLE2PULSE
318 
`endif
319 
`ifndef SYNCHRONIZER
320 
`define SYNCHRONIZER
321 
`endif
322 
`endif
323 
 
324 97 unneback 
// size to width
325 100 unneback 
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
326 62 unneback 
//////////////////////////////////////////////////////////////////////
327 6 unneback 
////                                                              ////
328 
////  Versatile library, clock and reset                          ////
329 
////                                                              ////
330 
////  Description                                                 ////
331 
////  Logic related to clock and reset                            ////
332 
////                                                              ////
333 
////                                                              ////
334 
////  To Do:                                                      ////
335 
////   - add more different registers                             ////
336 
////                                                              ////
337 
////  Author(s):                                                  ////
338 
////      - Michael Unneback, unneback@opencores.org              ////
339 
////        ORSoC AB                                              ////
340 
////                                                              ////
341 
//////////////////////////////////////////////////////////////////////
342 
////                                                              ////
343 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
344 
////                                                              ////
345 
//// This source file may be used and distributed without         ////
346 
//// restriction provided that this copyright statement is not    ////
347 
//// removed from the file and that any derivative work contains  ////
348 
//// the original copyright notice and the associated disclaimer. ////
349 
////                                                              ////
350 
//// This source file is free software; you can redistribute it   ////
351 
//// and/or modify it under the terms of the GNU Lesser General   ////
352 
//// Public License as published by the Free Software Foundation; ////
353 
//// either version 2.1 of the License, or (at your option) any   ////
354 
//// later version.                                               ////
355 
////                                                              ////
356 
//// This source is distributed in the hope that it will be       ////
357 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
358 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
359 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
360 
//// details.                                                     ////
361 
////                                                              ////
362 
//// You should have received a copy of the GNU Lesser General    ////
363 
//// Public License along with this source; if not, download it   ////
364 
//// from http://www.opencores.org/lgpl.shtml                     ////
365 
////                                                              ////
366 
//////////////////////////////////////////////////////////////////////
367 
 
368 48 unneback 
`ifdef ACTEL
369 
`ifdef GBUF
370 
`timescale 1 ns/100 ps
371 6 unneback 
// Global buffer
372 
// usage:
373 
// use to enable global buffers for high fan out signals such as clock and reset
374 
// Version: 8.4 8.4.0.33
375 
module gbuf(GL,CLK);
376 
output GL;
377 
input  CLK;
378 
 
379 
    wire GND;
380 
 
381 
    GND GND_1_net(.Y(GND));
382 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
383 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
384 
 
385 
endmodule
386 
`timescale 1 ns/1 ns
387 40 unneback 
`define MODULE gbuf
388 
module `BASE`MODULE ( i, o);
389 
`undef MODULE
390 6 unneback 
input i;
391 
output o;
392 
`ifdef SIM_GBUF
393 
assign o=i;
394 
`else
395 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
396 
`endif
397 
endmodule
398 40 unneback 
`endif
399 33 unneback 
 
400 6 unneback 
`else
401 33 unneback 
 
402 40 unneback 
`ifdef ALTERA
403 
`ifdef GBUF
404 21 unneback 
//altera
405 40 unneback 
`define MODULE gbuf
406 
module `BASE`MODULE ( i, o);
407 
`undef MODULE
408 33 unneback 
input i;
409 
output o;
410 
assign o = i;
411 
endmodule
412 40 unneback 
`endif
413 33 unneback 
 
414 6 unneback 
`else
415 
 
416 40 unneback 
`ifdef GBUF
417 6 unneback 
`timescale 1 ns/100 ps
418 40 unneback 
`define MODULE
419 
module `BASE`MODULE ( i, o);
420 
`undef MODULE
421 6 unneback 
input i;
422 
output o;
423 
assign o = i;
424 
endmodule
425 40 unneback 
`endif
426 6 unneback 
`endif // ALTERA
427 
`endif //ACTEL
428 
 
429 40 unneback 
`ifdef SYNC_RST
430 6 unneback 
// sync reset
431 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
432 6 unneback 
// output active high global reset sync with two DFFs
433 
`timescale 1 ns/100 ps
434 40 unneback 
`define MODULE sync_rst
435 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
436 
`undef MODULE
437 6 unneback 
input rst_n_i, clk;
438 
output rst_o;
439 18 unneback 
reg [1:0] tmp;
440 6 unneback 
always @ (posedge clk or negedge rst_n_i)
441 
if (!rst_n_i)
442 17 unneback 
        tmp <= 2'b11;
443 6 unneback 
else
444 33 unneback 
        tmp <= {1'b0,tmp[1]};
445 40 unneback 
`define MODULE gbuf
446 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
447 
`undef MODULE
448 6 unneback 
endmodule
449 40 unneback 
`endif
450 6 unneback 
 
451 40 unneback 
`ifdef PLL
452 6 unneback 
// vl_pll
453 
`ifdef ACTEL
454 32 unneback 
///////////////////////////////////////////////////////////////////////////////
455 17 unneback 
`timescale 1 ps/1 ps
456 40 unneback 
`define MODULE pll
457 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
458 
`undef MODULE
459 6 unneback 
parameter index = 0;
460 
parameter number_of_clk = 1;
461 17 unneback 
parameter period_time_0 = 20000;
462 
parameter period_time_1 = 20000;
463 
parameter period_time_2 = 20000;
464 
parameter lock_delay = 2000000;
465 6 unneback 
input clk_i, rst_n_i;
466 
output lock;
467 
output reg [0:number_of_clk-1] clk_o;
468 
output [0:number_of_clk-1] rst_o;
469 
 
470 
`ifdef SIM_PLL
471 
 
472 
always
473 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
474 
 
475 
generate if (number_of_clk > 1)
476 
always
477 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
478 
endgenerate
479 
 
480 
generate if (number_of_clk > 2)
481 
always
482 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
483 
endgenerate
484 
 
485 
genvar i;
486 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
487 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
488 
end
489 
endgenerate
490 
 
491 
assign #lock_delay lock = rst_n_i;
492 
 
493 
endmodule
494 
`else
495 
generate if (number_of_clk==1 & index==0) begin
496 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
497 
end
498 
endgenerate // index==0
499 
generate if (number_of_clk==1 & index==1) begin
500 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
501 
end
502 
endgenerate // index==1
503 
generate if (number_of_clk==1 & index==2) begin
504 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
505 
end
506 
endgenerate // index==2
507 
generate if (number_of_clk==1 & index==3) begin
508 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
509 
end
510 
endgenerate // index==0
511 
 
512 
generate if (number_of_clk==2 & index==0) begin
513 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
514 
end
515 
endgenerate // index==0
516 
generate if (number_of_clk==2 & index==1) begin
517 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
518 
end
519 
endgenerate // index==1
520 
generate if (number_of_clk==2 & index==2) begin
521 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
522 
end
523 
endgenerate // index==2
524 
generate if (number_of_clk==2 & index==3) begin
525 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
526 
end
527 
endgenerate // index==0
528 
 
529 
generate if (number_of_clk==3 & index==0) begin
530 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
531 
end
532 
endgenerate // index==0
533 
generate if (number_of_clk==3 & index==1) begin
534 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
535 
end
536 
endgenerate // index==1
537 
generate if (number_of_clk==3 & index==2) begin
538 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
539 
end
540 
endgenerate // index==2
541 
generate if (number_of_clk==3 & index==3) begin
542 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
543 
end
544 
endgenerate // index==0
545 
 
546 
genvar i;
547 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
548 40 unneback 
`define MODULE sync_rst
549 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
550 
`undef MODULE
551 6 unneback 
end
552 
endgenerate
553 
endmodule
554 
`endif
555 32 unneback 
///////////////////////////////////////////////////////////////////////////////
556 6 unneback 
 
557 
`else
558 
 
559 32 unneback 
///////////////////////////////////////////////////////////////////////////////
560 6 unneback 
`ifdef ALTERA
561 
 
562 32 unneback 
`timescale 1 ps/1 ps
563 40 unneback 
`define MODULE pll
564 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
565 
`undef MODULE
566 32 unneback 
parameter index = 0;
567 
parameter number_of_clk = 1;
568 
parameter period_time_0 = 20000;
569 
parameter period_time_1 = 20000;
570 
parameter period_time_2 = 20000;
571 
parameter period_time_3 = 20000;
572 
parameter period_time_4 = 20000;
573 
parameter lock_delay = 2000000;
574 
input clk_i, rst_n_i;
575 
output lock;
576 
output reg [0:number_of_clk-1] clk_o;
577 
output [0:number_of_clk-1] rst_o;
578 
 
579 
`ifdef SIM_PLL
580 
 
581 
always
582 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
583 
 
584 
generate if (number_of_clk > 1)
585 
always
586 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
587 
endgenerate
588 
 
589 
generate if (number_of_clk > 2)
590 
always
591 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
592 
endgenerate
593 
 
594 33 unneback 
generate if (number_of_clk > 3)
595 32 unneback 
always
596 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
597 
endgenerate
598 
 
599 33 unneback 
generate if (number_of_clk > 4)
600 32 unneback 
always
601 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
602 
endgenerate
603 
 
604 
genvar i;
605 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
606 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
607 
end
608 
endgenerate
609 
 
610 33 unneback 
//assign #lock_delay lock = rst_n_i;
611 
assign lock = rst_n_i;
612 32 unneback 
 
613 
endmodule
614 6 unneback 
`else
615 
 
616 33 unneback 
`ifdef VL_PLL0
617 
`ifdef VL_PLL0_CLK1
618 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
619 
`endif
620 
`ifdef VL_PLL0_CLK2
621 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
622 
`endif
623 
`ifdef VL_PLL0_CLK3
624 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
625 
`endif
626 
`ifdef VL_PLL0_CLK4
627 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
628 
`endif
629 
`ifdef VL_PLL0_CLK5
630 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
631 
`endif
632 
`endif
633 32 unneback 
 
634 33 unneback 
`ifdef VL_PLL1
635 
`ifdef VL_PLL1_CLK1
636 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
637 
`endif
638 
`ifdef VL_PLL1_CLK2
639 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
640 
`endif
641 
`ifdef VL_PLL1_CLK3
642 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
643 
`endif
644 
`ifdef VL_PLL1_CLK4
645 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
646 
`endif
647 
`ifdef VL_PLL1_CLK5
648 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
649 
`endif
650 
`endif
651 32 unneback 
 
652 33 unneback 
`ifdef VL_PLL2
653 
`ifdef VL_PLL2_CLK1
654 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
655 
`endif
656 
`ifdef VL_PLL2_CLK2
657 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
658 
`endif
659 
`ifdef VL_PLL2_CLK3
660 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
661 
`endif
662 
`ifdef VL_PLL2_CLK4
663 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
664 
`endif
665 
`ifdef VL_PLL2_CLK5
666 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
667 
`endif
668 
`endif
669 32 unneback 
 
670 33 unneback 
`ifdef VL_PLL3
671 
`ifdef VL_PLL3_CLK1
672 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
673 
`endif
674 
`ifdef VL_PLL3_CLK2
675 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
676 
`endif
677 
`ifdef VL_PLL3_CLK3
678 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
679 
`endif
680 
`ifdef VL_PLL3_CLK4
681 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
682 
`endif
683 
`ifdef VL_PLL3_CLK5
684 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
685 
`endif
686 
`endif
687 32 unneback 
 
688 
genvar i;
689 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
690 40 unneback 
`define MODULE sync_rst
691 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
692 
`undef MODULE
693 32 unneback 
end
694 
endgenerate
695 
endmodule
696 
`endif
697 
///////////////////////////////////////////////////////////////////////////////
698 
 
699 
`else
700 
 
701 6 unneback 
// generic PLL
702 17 unneback 
`timescale 1 ps/1 ps
703 40 unneback 
`define MODULE pll
704 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
705 
`undef MODULE
706 6 unneback 
parameter index = 0;
707 
parameter number_of_clk = 1;
708 17 unneback 
parameter period_time_0 = 20000;
709 
parameter period_time_1 = 20000;
710 
parameter period_time_2 = 20000;
711 6 unneback 
parameter lock_delay = 2000;
712 
input clk_i, rst_n_i;
713 
output lock;
714 
output reg [0:number_of_clk-1] clk_o;
715 
output [0:number_of_clk-1] rst_o;
716 
 
717 
always
718 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
719 
 
720 
generate if (number_of_clk > 1)
721 
always
722 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
723 
endgenerate
724 
 
725 
generate if (number_of_clk > 2)
726 
always
727 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
728 
endgenerate
729 
 
730 
genvar i;
731 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
732 40 unneback 
`define MODULE sync_rst
733 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
734 
`undef MODULE
735 6 unneback 
end
736 
endgenerate
737 
 
738 
assign #lock_delay lock = rst_n_i;
739 
 
740 
endmodule
741 
 
742 
`endif //altera
743 17 unneback 
`endif //actel
744 40 unneback 
`undef MODULE
745 
`endif//////////////////////////////////////////////////////////////////////
746 6 unneback 
////                                                              ////
747 
////  Versatile library, registers                                ////
748 
////                                                              ////
749 
////  Description                                                 ////
750 
////  Different type of registers                                 ////
751 
////                                                              ////
752 
////                                                              ////
753 
////  To Do:                                                      ////
754 
////   - add more different registers                             ////
755 
////                                                              ////
756 
////  Author(s):                                                  ////
757 
////      - Michael Unneback, unneback@opencores.org              ////
758 
////        ORSoC AB                                              ////
759 
////                                                              ////
760 
//////////////////////////////////////////////////////////////////////
761 
////                                                              ////
762 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
763 
////                                                              ////
764 
//// This source file may be used and distributed without         ////
765 
//// restriction provided that this copyright statement is not    ////
766 
//// removed from the file and that any derivative work contains  ////
767 
//// the original copyright notice and the associated disclaimer. ////
768 
////                                                              ////
769 
//// This source file is free software; you can redistribute it   ////
770 
//// and/or modify it under the terms of the GNU Lesser General   ////
771 
//// Public License as published by the Free Software Foundation; ////
772 
//// either version 2.1 of the License, or (at your option) any   ////
773 
//// later version.                                               ////
774 
////                                                              ////
775 
//// This source is distributed in the hope that it will be       ////
776 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
777 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
778 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
779 
//// details.                                                     ////
780 
////                                                              ////
781 
//// You should have received a copy of the GNU Lesser General    ////
782 
//// Public License along with this source; if not, download it   ////
783 
//// from http://www.opencores.org/lgpl.shtml                     ////
784 
////                                                              ////
785 
//////////////////////////////////////////////////////////////////////
786 
 
787 40 unneback 
`ifdef DFF
788 
`define MODULE dff
789 
module `BASE`MODULE ( d, q, clk, rst);
790 
`undef MODULE
791 6 unneback 
        parameter width = 1;
792 
        parameter reset_value = 0;
793 
 
794 
        input [width-1:0] d;
795 
        input clk, rst;
796 
        output reg [width-1:0] q;
797 
 
798 
        always @ (posedge clk or posedge rst)
799 
        if (rst)
800 
                q <= reset_value;
801 
        else
802 
                q <= d;
803 
 
804 
endmodule
805 40 unneback 
`endif
806 6 unneback 
 
807 40 unneback 
`ifdef DFF_ARRAY
808 
`define MODULE dff_array
809 
module `BASE`MODULE ( d, q, clk, rst);
810 
`undef MODULE
811 6 unneback 
 
812 
        parameter width = 1;
813 
        parameter depth = 2;
814 
        parameter reset_value = 1'b0;
815 
 
816 
        input [width-1:0] d;
817 
        input clk, rst;
818 
        output [width-1:0] q;
819 
        reg  [0:depth-1] q_tmp [width-1:0];
820 
        integer i;
821 
        always @ (posedge clk or posedge rst)
822 
        if (rst) begin
823 
            for (i=0;i<depth;i=i+1)
824 
                q_tmp[i] <= {width{reset_value}};
825 
        end else begin
826 
            q_tmp[0] <= d;
827 
            for (i=1;i<depth;i=i+1)
828 
                q_tmp[i] <= q_tmp[i-1];
829 
        end
830 
 
831 
    assign q = q_tmp[depth-1];
832 
 
833 
endmodule
834 40 unneback 
`endif
835 6 unneback 
 
836 40 unneback 
`ifdef DFF_CE
837 
`define MODULE dff_ce
838 
module `BASE`MODULE ( d, ce, q, clk, rst);
839 
`undef MODULE
840 6 unneback 
 
841 
        parameter width = 1;
842 
        parameter reset_value = 0;
843 
 
844 
        input [width-1:0] d;
845 
        input ce, clk, rst;
846 
        output reg [width-1:0] q;
847 
 
848 
        always @ (posedge clk or posedge rst)
849 
        if (rst)
850 
                q <= reset_value;
851 
        else
852 
                if (ce)
853 
                        q <= d;
854 
 
855 
endmodule
856 40 unneback 
`endif
857 6 unneback 
 
858 40 unneback 
`ifdef DFF_CE_CLEAR
859 
`define MODULE dff_ce_clear
860 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
861 
`undef MODULE
862 8 unneback 
 
863 
        parameter width = 1;
864 
        parameter reset_value = 0;
865 
 
866 
        input [width-1:0] d;
867 10 unneback 
        input ce, clear, clk, rst;
868 8 unneback 
        output reg [width-1:0] q;
869 
 
870 
        always @ (posedge clk or posedge rst)
871 
        if (rst)
872 
            q <= reset_value;
873 
        else
874 
            if (ce)
875 
                if (clear)
876 
                    q <= {width{1'b0}};
877 
                else
878 
                    q <= d;
879 
 
880 
endmodule
881 40 unneback 
`endif
882 8 unneback 
 
883 40 unneback 
`ifdef DF_CE_SET
884 
`define MODULE dff_ce_set
885 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
886 
`undef MODULE
887 24 unneback 
 
888 
        parameter width = 1;
889 
        parameter reset_value = 0;
890 
 
891 
        input [width-1:0] d;
892 
        input ce, set, clk, rst;
893 
        output reg [width-1:0] q;
894 
 
895 
        always @ (posedge clk or posedge rst)
896 
        if (rst)
897 
            q <= reset_value;
898 
        else
899 
            if (ce)
900 
                if (set)
901 
                    q <= {width{1'b1}};
902 
                else
903 
                    q <= d;
904 
 
905 
endmodule
906 40 unneback 
`endif
907 24 unneback 
 
908 40 unneback 
`ifdef SPR
909 
`define MODULE spr
910 
module `BASE`MODULE ( sp, r, q, clk, rst);
911 
`undef MODULE
912 
 
913 64 unneback 
        //parameter width = 1;
914 
        parameter reset_value = 1'b0;
915 29 unneback 
 
916 
        input sp, r;
917 
        output reg q;
918 
        input clk, rst;
919 
 
920 
        always @ (posedge clk or posedge rst)
921 
        if (rst)
922 
            q <= reset_value;
923 
        else
924 
            if (sp)
925 
                q <= 1'b1;
926 
            else if (r)
927 
                q <= 1'b0;
928 
 
929 
endmodule
930 40 unneback 
`endif
931 29 unneback 
 
932 40 unneback 
`ifdef SRP
933 
`define MODULE srp
934 
module `BASE`MODULE ( s, rp, q, clk, rst);
935 
`undef MODULE
936 
 
937 29 unneback 
        parameter width = 1;
938 
        parameter reset_value = 0;
939 
 
940 
        input s, rp;
941 
        output reg q;
942 
        input clk, rst;
943 
 
944 
        always @ (posedge clk or posedge rst)
945 
        if (rst)
946 
            q <= reset_value;
947 
        else
948 
            if (rp)
949 
                q <= 1'b0;
950 
            else if (s)
951 
                q <= 1'b1;
952 
 
953 
endmodule
954 40 unneback 
`endif
955 29 unneback 
 
956 40 unneback 
`ifdef ALTERA
957 29 unneback 
 
958 40 unneback 
`ifdef DFF_SR
959 6 unneback 
// megafunction wizard: %LPM_FF%
960 
// GENERATION: STANDARD
961 
// VERSION: WM1.0
962 
// MODULE: lpm_ff
963 
 
964 
// ============================================================
965 
// File Name: dff_sr.v
966 
// Megafunction Name(s):
967 
//                      lpm_ff
968 
//
969 
// Simulation Library Files(s):
970 
//                      lpm
971 
// ============================================================
972 
// ************************************************************
973 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
974 
//
975 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
976 
// ************************************************************
977 
 
978 
 
979 
//Copyright (C) 1991-2010 Altera Corporation
980 
//Your use of Altera Corporation's design tools, logic functions
981 
//and other software and tools, and its AMPP partner logic
982 
//functions, and any output files from any of the foregoing
983 
//(including device programming or simulation files), and any
984 
//associated documentation or information are expressly subject
985 
//to the terms and conditions of the Altera Program License
986 
//Subscription Agreement, Altera MegaCore Function License
987 
//Agreement, or other applicable license agreement, including,
988 
//without limitation, that your use is for the sole purpose of
989 
//programming logic devices manufactured by Altera and sold by
990 
//Altera or its authorized distributors.  Please refer to the
991 
//applicable agreement for further details.
992 
 
993 
 
994 
// synopsys translate_off
995 
`timescale 1 ps / 1 ps
996 
// synopsys translate_on
997 40 unneback 
`define MODULE dff_sr
998 
module `BASE`MODULE (
999 
`undef MODULE
1000 
 
1001 6 unneback 
        aclr,
1002 
        aset,
1003 
        clock,
1004 
        data,
1005 
        q);
1006 
 
1007 
        input     aclr;
1008 
        input     aset;
1009 
        input     clock;
1010 
        input     data;
1011 
        output    q;
1012 
 
1013 
        wire [0:0] sub_wire0;
1014 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
1015 
        wire  q = sub_wire1;
1016 
        wire  sub_wire2 = data;
1017 
        wire  sub_wire3 = sub_wire2;
1018 
 
1019 
        lpm_ff  lpm_ff_component (
1020 
                                .aclr (aclr),
1021 
                                .clock (clock),
1022 
                                .data (sub_wire3),
1023 
                                .aset (aset),
1024 
                                .q (sub_wire0)
1025 
                                // synopsys translate_off
1026 
                                ,
1027 
                                .aload (),
1028 
                                .enable (),
1029 
                                .sclr (),
1030 
                                .sload (),
1031 
                                .sset ()
1032 
                                // synopsys translate_on
1033 
                                );
1034 
        defparam
1035 
                lpm_ff_component.lpm_fftype = "DFF",
1036 
                lpm_ff_component.lpm_type = "LPM_FF",
1037 
                lpm_ff_component.lpm_width = 1;
1038 
 
1039 
 
1040 
endmodule
1041 
 
1042 
// ============================================================
1043 
// CNX file retrieval info
1044 
// ============================================================
1045 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1046 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1047 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1048 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1049 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1050 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1051 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1052 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1053 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1054 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1055 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1056 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1057 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1058 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1059 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1060 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1061 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1062 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1063 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1064 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1065 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1066 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1067 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1068 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1069 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1070 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1071 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1072 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1073 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1074 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1075 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1076 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1077 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1078 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1079 
// Retrieval info: LIB_FILE: lpm
1080 40 unneback 
`endif
1081 6 unneback 
 
1082 
`else
1083 
 
1084 40 unneback 
`ifdef DFF_SR
1085 
`define MODULE dff_sr
1086 
module `BASE`MODULE ( aclr, aset, clock, data, q);
1087 
`undef MODULE
1088 6 unneback 
 
1089 
    input         aclr;
1090 
    input         aset;
1091 
    input         clock;
1092 
    input         data;
1093 
    output reg    q;
1094 
 
1095 
   always @ (posedge clock or posedge aclr or posedge aset)
1096 
     if (aclr)
1097 
       q <= 1'b0;
1098 
     else if (aset)
1099 
       q <= 1'b1;
1100 
     else
1101 
       q <= data;
1102 
 
1103 
endmodule
1104 40 unneback 
`endif
1105 6 unneback 
 
1106 
`endif
1107 
 
1108 
// LATCH
1109 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1110 
`ifdef ALTERA
1111 40 unneback 
 
1112 
`ifdef LATCH
1113 
`define MODULE latch
1114 
module `BASE`MODULE ( d, le, q, clk);
1115 
`undef MODULE
1116 6 unneback 
input d, le;
1117 
output q;
1118 
input clk;
1119 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1120 
endmodule
1121 40 unneback 
`endif
1122 
 
1123 6 unneback 
`else
1124 40 unneback 
 
1125 
`ifdef LATCH
1126 
`define MODULE latch
1127 
module `BASE`MODULE ( d, le, q, clk);
1128 
`undef MODULE
1129 6 unneback 
input d, le;
1130 48 unneback 
input clk;
1131 
always @ (le or d)
1132 60 unneback 
if (le)
1133 48 unneback 
    d <= q;
1134 6 unneback 
endmodule
1135 15 unneback 
`endif
1136 
 
1137 40 unneback 
`endif
1138 
 
1139 
`ifdef SHREG
1140 
`define MODULE shreg
1141 
module `BASE`MODULE ( d, q, clk, rst);
1142 
`undef MODULE
1143 
 
1144 17 unneback 
parameter depth = 10;
1145 
input d;
1146 
output q;
1147 
input clk, rst;
1148 
 
1149 
reg [1:depth] dffs;
1150 
 
1151 
always @ (posedge clk or posedge rst)
1152 
if (rst)
1153 
    dffs <= {depth{1'b0}};
1154 
else
1155 
    dffs <= {d,dffs[1:depth-1]};
1156 
assign q = dffs[depth];
1157 
endmodule
1158 40 unneback 
`endif
1159 17 unneback 
 
1160 40 unneback 
`ifdef SHREG_CE
1161 
`define MODULE shreg_ce
1162 
module `BASE`MODULE ( d, ce, q, clk, rst);
1163 
`undef MODULE
1164 17 unneback 
parameter depth = 10;
1165 
input d, ce;
1166 
output q;
1167 
input clk, rst;
1168 
 
1169 
reg [1:depth] dffs;
1170 
 
1171 
always @ (posedge clk or posedge rst)
1172 
if (rst)
1173 
    dffs <= {depth{1'b0}};
1174 
else
1175 
    if (ce)
1176 
        dffs <= {d,dffs[1:depth-1]};
1177 
assign q = dffs[depth];
1178 
endmodule
1179 40 unneback 
`endif
1180 17 unneback 
 
1181 40 unneback 
`ifdef DELAY
1182 
`define MODULE delay
1183 
module `BASE`MODULE ( d, q, clk, rst);
1184 
`undef MODULE
1185 15 unneback 
parameter depth = 10;
1186 
input d;
1187 
output q;
1188 
input clk, rst;
1189 
 
1190 
reg [1:depth] dffs;
1191 
 
1192 
always @ (posedge clk or posedge rst)
1193 
if (rst)
1194 
    dffs <= {depth{1'b0}};
1195 
else
1196 
    dffs <= {d,dffs[1:depth-1]};
1197 
assign q = dffs[depth];
1198 17 unneback 
endmodule
1199 40 unneback 
`endif
1200 17 unneback 
 
1201 40 unneback 
`ifdef DELAY_EMPTYFLAG
1202 
`define MODULE delay_emptyflag
1203 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1204 40 unneback 
`undef MODULE
1205 17 unneback 
parameter depth = 10;
1206 
input d;
1207 
output q, emptyflag;
1208 
input clk, rst;
1209 
 
1210 
reg [1:depth] dffs;
1211 
 
1212 
always @ (posedge clk or posedge rst)
1213 
if (rst)
1214 
    dffs <= {depth{1'b0}};
1215 
else
1216 
    dffs <= {d,dffs[1:depth-1]};
1217 
assign q = dffs[depth];
1218 
assign emptyflag = !(|dffs);
1219 
endmodule
1220 40 unneback 
`endif
1221 75 unneback 
 
1222 94 unneback 
`ifdef PULSE2TOGGLE
1223 98 unneback 
`define MODULE pulse2toggle
1224 
module `BASE`MODULE ( pl, q, clk, rst);
1225 75 unneback 
`undef MODULE
1226 94 unneback 
input pl;
1227 98 unneback 
output reg q;
1228 94 unneback 
input clk, rst;
1229 
always @ (posedge clk or posedge rst)
1230 75 unneback 
if (rst)
1231 94 unneback 
    q <= 1'b0;
1232 75 unneback 
else
1233 94 unneback 
    q <= pl ^ q;
1234 
endmodule
1235 
`endif
1236 75 unneback 
 
1237 94 unneback 
`ifdef TOGGLE2PULSE
1238 98 unneback 
`define MODULE toggle2pulse
1239 94 unneback 
module `BASE`MODULE (d, pl, clk, rst);
1240 97 unneback 
`undef MODULE
1241 94 unneback 
input d;
1242 
output pl;
1243 
input clk, rst;
1244 
reg dff;
1245 
always @ (posedge clk or posedge rst)
1246 
if (rst)
1247 
    dff <= 1'b0;
1248 75 unneback 
else
1249 94 unneback 
    dff <= d;
1250 98 unneback 
assign pl = d ^ dff;
1251 94 unneback 
endmodule
1252 
`endif
1253 75 unneback 
 
1254 94 unneback 
`ifdef SYNCHRONIZER
1255 
`define MODULE synchronizer
1256 
module `BASE`MODULE (d, q, clk, rst);
1257 
`undef MODULE
1258 
input d;
1259 
output reg q;
1260 116 unneback 
input clk, rst;
1261 94 unneback 
reg dff;
1262 
always @ (posedge clk or posedge rst)
1263 
if (rst)
1264 100 unneback 
    {q,dff} <= 2'b00;
1265 75 unneback 
else
1266 100 unneback 
    {q,dff} <= {dff,d};
1267 94 unneback 
endmodule
1268 
`endif
1269 75 unneback 
 
1270 94 unneback 
`ifdef CDC
1271 
`define MODULE cdc
1272 97 unneback 
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1273 94 unneback 
`undef MODULE
1274 
input start_pl;
1275 
output take_it_pl;
1276 
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1277 
output got_it_pl;
1278 
input clk_src, rst_src;
1279 
input clk_dst, rst_dst;
1280 
wire take_it_tg, take_it_tg_sync;
1281 
wire got_it_tg, got_it_tg_sync;
1282 
// src -> dst
1283 
`define MODULE pulse2toggle
1284 
`BASE`MODULE p2t0 (
1285 
`undef MODULE
1286 
    .pl(start_pl),
1287 
    .q(take_it_tg),
1288 
    .clk(clk_src),
1289 
    .rst(rst_src));
1290 75 unneback 
 
1291 94 unneback 
`define MODULE synchronizer
1292 
`BASE`MODULE sync0 (
1293 
`undef MODULE
1294 
    .d(take_it_tg),
1295 
    .q(take_it_tg_sync),
1296 
    .clk(clk_dst),
1297 
    .rst(rst_dst));
1298 
 
1299 
`define MODULE toggle2pulse
1300 
`BASE`MODULE t2p0 (
1301 
`undef MODULE
1302 100 unneback 
    .d(take_it_tg_sync),
1303 94 unneback 
    .pl(take_it_pl),
1304 
    .clk(clk_dst),
1305 
    .rst(rst_dst));
1306 
 
1307 
// dst -> src
1308 
`define MODULE pulse2toggle
1309 98 unneback 
`BASE`MODULE p2t1 (
1310 94 unneback 
`undef MODULE
1311 
    .pl(take_it_grant_pl),
1312 
    .q(got_it_tg),
1313 
    .clk(clk_dst),
1314 
    .rst(rst_dst));
1315 
 
1316 
`define MODULE synchronizer
1317 
`BASE`MODULE sync1 (
1318 
`undef MODULE
1319 
    .d(got_it_tg),
1320 
    .q(got_it_tg_sync),
1321 
    .clk(clk_src),
1322 
    .rst(rst_src));
1323 
 
1324 
`define MODULE toggle2pulse
1325 
`BASE`MODULE t2p1 (
1326 
`undef MODULE
1327 100 unneback 
    .d(got_it_tg_sync),
1328 94 unneback 
    .pl(got_it_pl),
1329 
    .clk(clk_src),
1330 
    .rst(rst_src));
1331 
 
1332 75 unneback 
endmodule
1333 
`endif
1334 17 unneback 
//////////////////////////////////////////////////////////////////////
1335 6 unneback 
////                                                              ////
1336 18 unneback 
////  Logic functions                                             ////
1337 
////                                                              ////
1338 
////  Description                                                 ////
1339 
////  Logic functions such as multiplexers                        ////
1340 
////                                                              ////
1341 
////                                                              ////
1342 
////  To Do:                                                      ////
1343 
////   -                                                          ////
1344 
////                                                              ////
1345 
////  Author(s):                                                  ////
1346 
////      - Michael Unneback, unneback@opencores.org              ////
1347 
////        ORSoC AB                                              ////
1348 
////                                                              ////
1349 
//////////////////////////////////////////////////////////////////////
1350 
////                                                              ////
1351 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1352 
////                                                              ////
1353 
//// This source file may be used and distributed without         ////
1354 
//// restriction provided that this copyright statement is not    ////
1355 
//// removed from the file and that any derivative work contains  ////
1356 
//// the original copyright notice and the associated disclaimer. ////
1357 
////                                                              ////
1358 
//// This source file is free software; you can redistribute it   ////
1359 
//// and/or modify it under the terms of the GNU Lesser General   ////
1360 
//// Public License as published by the Free Software Foundation; ////
1361 
//// either version 2.1 of the License, or (at your option) any   ////
1362 
//// later version.                                               ////
1363 
////                                                              ////
1364 
//// This source is distributed in the hope that it will be       ////
1365 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1366 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1367 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1368 
//// details.                                                     ////
1369 
////                                                              ////
1370 
//// You should have received a copy of the GNU Lesser General    ////
1371 
//// Public License along with this source; if not, download it   ////
1372 
//// from http://www.opencores.org/lgpl.shtml                     ////
1373 
////                                                              ////
1374 
//////////////////////////////////////////////////////////////////////
1375 40 unneback 
`ifdef MUX_ANDOR
1376 
`define MODULE mux_andor
1377 
module `BASE`MODULE ( a, sel, dout);
1378 
`undef MODULE
1379 36 unneback 
 
1380 
parameter width = 32;
1381 
parameter nr_of_ports = 4;
1382 
 
1383 
input [nr_of_ports*width-1:0] a;
1384 
input [nr_of_ports-1:0] sel;
1385 
output reg [width-1:0] dout;
1386 
 
1387 38 unneback 
integer i,j;
1388 
 
1389 36 unneback 
always @ (a, sel)
1390 
begin
1391 
    dout = a[width-1:0] & {width{sel[0]}};
1392 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1393 
        for (j=0;j<width;j=j+1)
1394 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1395 36 unneback 
end
1396 
 
1397 
endmodule
1398 40 unneback 
`endif
1399 36 unneback 
 
1400 40 unneback 
`ifdef MUX2_ANDOR
1401 
`define MODULE mux2_andor
1402 
module `BASE`MODULE ( a1, a0, sel, dout);
1403 
`undef MODULE
1404 18 unneback 
 
1405 34 unneback 
parameter width = 32;
1406 35 unneback 
localparam nr_of_ports = 2;
1407 34 unneback 
input [width-1:0] a1, a0;
1408 
input [nr_of_ports-1:0] sel;
1409 
output [width-1:0] dout;
1410 
 
1411 40 unneback 
`define MODULE mux_andor
1412 
`BASE`MODULE
1413 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1414 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1415 40 unneback 
`undef MODULE
1416 
 
1417 34 unneback 
endmodule
1418 40 unneback 
`endif
1419 34 unneback 
 
1420 40 unneback 
`ifdef MUX3_ANDOR
1421 
`define MODULE mux3_andor
1422 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1423 
`undef MODULE
1424 34 unneback 
 
1425 
parameter width = 32;
1426 35 unneback 
localparam nr_of_ports = 3;
1427 34 unneback 
input [width-1:0] a2, a1, a0;
1428 
input [nr_of_ports-1:0] sel;
1429 
output [width-1:0] dout;
1430 
 
1431 40 unneback 
`define MODULE mux_andor
1432 
`BASE`MODULE
1433 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1434 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1435 40 unneback 
`undef MODULE
1436 34 unneback 
endmodule
1437 40 unneback 
`endif
1438 34 unneback 
 
1439 40 unneback 
`ifdef MUX4_ANDOR
1440 
`define MODULE mux4_andor
1441 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1442 
`undef MODULE
1443 18 unneback 
 
1444 
parameter width = 32;
1445 35 unneback 
localparam nr_of_ports = 4;
1446 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1447 
input [nr_of_ports-1:0] sel;
1448 22 unneback 
output [width-1:0] dout;
1449 18 unneback 
 
1450 40 unneback 
`define MODULE mux_andor
1451 
`BASE`MODULE
1452 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1453 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1454 40 unneback 
`undef MODULE
1455 18 unneback 
 
1456 
endmodule
1457 40 unneback 
`endif
1458 18 unneback 
 
1459 40 unneback 
`ifdef MUX5_ANDOR
1460 
`define MODULE mux5_andor
1461 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1462 
`undef MODULE
1463 18 unneback 
 
1464 
parameter width = 32;
1465 35 unneback 
localparam nr_of_ports = 5;
1466 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1467 
input [nr_of_ports-1:0] sel;
1468 22 unneback 
output [width-1:0] dout;
1469 18 unneback 
 
1470 40 unneback 
`define MODULE mux_andor
1471 
`BASE`MODULE
1472 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1473 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1474 40 unneback 
`undef MODULE
1475 18 unneback 
 
1476 
endmodule
1477 40 unneback 
`endif
1478 18 unneback 
 
1479 40 unneback 
`ifdef MUX6_ANDOR
1480 
`define MODULE mux6_andor
1481 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1482 
`undef MODULE
1483 18 unneback 
 
1484 
parameter width = 32;
1485 35 unneback 
localparam nr_of_ports = 6;
1486 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1487 
input [nr_of_ports-1:0] sel;
1488 22 unneback 
output [width-1:0] dout;
1489 18 unneback 
 
1490 40 unneback 
`define MODULE mux_andor
1491 
`BASE`MODULE
1492 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1493 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1494 40 unneback 
`undef MODULE
1495 18 unneback 
 
1496 
endmodule
1497 40 unneback 
`endif
1498 43 unneback 
 
1499 
`ifdef PARITY
1500 
 
1501 
`define MODULE parity_generate
1502 
module `BASE`MODULE (data, parity);
1503 
`undef MODULE
1504 
parameter word_size = 32;
1505 
parameter chunk_size = 8;
1506 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1507 
input [word_size-1:0] data;
1508 
output reg [word_size/chunk_size-1:0] parity;
1509 
integer i,j;
1510 
always @ (data)
1511 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1512 
    parity[i] = parity_type;
1513 
    for (j=0;j<chunk_size;j=j+1) begin
1514 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1515 43 unneback 
    end
1516 
end
1517 
endmodule
1518 
 
1519 
`define MODULE parity_check
1520 
module `BASE`MODULE( data, parity, parity_error);
1521 
`undef MODULE
1522 
parameter word_size = 32;
1523 
parameter chunk_size = 8;
1524 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1525 
input [word_size-1:0] data;
1526 
input [word_size/chunk_size-1:0] parity;
1527 
output parity_error;
1528 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1529 43 unneback 
integer i,j;
1530 
always @ (data or parity)
1531 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1532 
    error_flag[i] = parity[i] ^ parity_type;
1533 
    for (j=0;j<chunk_size;j=j+1) begin
1534 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1535 43 unneback 
    end
1536 
end
1537 
assign parity_error = |error_flag;
1538 
endmodule
1539 
 
1540 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1541 
////                                                              ////
1542 
////  IO functions                                                ////
1543 
////                                                              ////
1544 
////  Description                                                 ////
1545 
////  IO functions such as IOB flip-flops                         ////
1546 
////                                                              ////
1547 
////                                                              ////
1548 
////  To Do:                                                      ////
1549 
////   -                                                          ////
1550 
////                                                              ////
1551 
////  Author(s):                                                  ////
1552 
////      - Michael Unneback, unneback@opencores.org              ////
1553 
////        ORSoC AB                                              ////
1554 
////                                                              ////
1555 18 unneback 
//////////////////////////////////////////////////////////////////////
1556 
////                                                              ////
1557 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1558 
////                                                              ////
1559 
//// This source file may be used and distributed without         ////
1560 
//// restriction provided that this copyright statement is not    ////
1561 
//// removed from the file and that any derivative work contains  ////
1562 
//// the original copyright notice and the associated disclaimer. ////
1563 
////                                                              ////
1564 
//// This source file is free software; you can redistribute it   ////
1565 
//// and/or modify it under the terms of the GNU Lesser General   ////
1566 
//// Public License as published by the Free Software Foundation; ////
1567 
//// either version 2.1 of the License, or (at your option) any   ////
1568 
//// later version.                                               ////
1569 
////                                                              ////
1570 
//// This source is distributed in the hope that it will be       ////
1571 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1572 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1573 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1574 
//// details.                                                     ////
1575 
////                                                              ////
1576 
//// You should have received a copy of the GNU Lesser General    ////
1577 
//// Public License along with this source; if not, download it   ////
1578 
//// from http://www.opencores.org/lgpl.shtml                     ////
1579 
////                                                              ////
1580 
//////////////////////////////////////////////////////////////////////
1581 45 unneback 
`timescale 1ns/1ns
1582 44 unneback 
`ifdef O_DFF
1583 
`define MODULE o_dff
1584 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1585 
`undef MODULE
1586 
parameter width = 1;
1587 45 unneback 
parameter reset_value = {width{1'b0}};
1588 
input  [width-1:0]  d_i;
1589 44 unneback 
output [width-1:0] o_pad;
1590 
input clk, rst;
1591 
wire [width-1:0] d_i_int `SYN_KEEP;
1592 45 unneback 
reg  [width-1:0] o_pad_int;
1593 44 unneback 
assign d_i_int = d_i;
1594 
genvar i;
1595 45 unneback 
generate
1596 44 unneback 
for (i=0;i<width;i=i+1) begin
1597 
    always @ (posedge clk or posedge rst)
1598 
    if (rst)
1599 45 unneback 
        o_pad_int[i] <= reset_value[i];
1600 44 unneback 
    else
1601 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1602 
    assign #1 o_pad[i] = o_pad_int[i];
1603 44 unneback 
end
1604 
endgenerate
1605 
endmodule
1606 
`endif
1607 
 
1608 45 unneback 
`timescale 1ns/1ns
1609 44 unneback 
`ifdef IO_DFF_OE
1610 
`define MODULE io_dff_oe
1611 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1612 
`undef MODULE
1613 
parameter width = 1;
1614 
input  [width-1:0] d_o;
1615 
output reg [width-1:0] d_i;
1616 
input oe;
1617 
inout [width-1:0] io_pad;
1618 
input clk, rst;
1619 
wire [width-1:0] oe_d `SYN_KEEP;
1620 
reg [width-1:0] oe_q;
1621 
reg [width-1:0] d_o_q;
1622 
assign oe_d = {width{oe}};
1623 
genvar i;
1624 
generate
1625 
for (i=0;i<width;i=i+1) begin
1626 
    always @ (posedge clk or posedge rst)
1627 
    if (rst)
1628 
        oe_q[i] <= 1'b0;
1629 
    else
1630 
        oe_q[i] <= oe_d[i];
1631 
    always @ (posedge clk or posedge rst)
1632 
    if (rst)
1633 
        d_o_q[i] <= 1'b0;
1634 
    else
1635 
        d_o_q[i] <= d_o[i];
1636 
    always @ (posedge clk or posedge rst)
1637 
    if (rst)
1638 
        d_i[i] <= 1'b0;
1639 
    else
1640 
        d_i[i] <= io_pad[i];
1641 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1642 44 unneback 
end
1643 
endgenerate
1644 
endmodule
1645 
`endif
1646 
`ifdef CNT_BIN
1647 
//////////////////////////////////////////////////////////////////////
1648 
////                                                              ////
1649 6 unneback 
////  Versatile counter                                           ////
1650 
////                                                              ////
1651 
////  Description                                                 ////
1652 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1653 
////  counter                                                     ////
1654 
////                                                              ////
1655 
////  To Do:                                                      ////
1656 
////   - add LFSR with more taps                                  ////
1657 
////                                                              ////
1658 
////  Author(s):                                                  ////
1659 
////      - Michael Unneback, unneback@opencores.org              ////
1660 
////        ORSoC AB                                              ////
1661 
////                                                              ////
1662 
//////////////////////////////////////////////////////////////////////
1663 
////                                                              ////
1664 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1665 
////                                                              ////
1666 
//// This source file may be used and distributed without         ////
1667 
//// restriction provided that this copyright statement is not    ////
1668 
//// removed from the file and that any derivative work contains  ////
1669 
//// the original copyright notice and the associated disclaimer. ////
1670 
////                                                              ////
1671 
//// This source file is free software; you can redistribute it   ////
1672 
//// and/or modify it under the terms of the GNU Lesser General   ////
1673 
//// Public License as published by the Free Software Foundation; ////
1674 
//// either version 2.1 of the License, or (at your option) any   ////
1675 
//// later version.                                               ////
1676 
////                                                              ////
1677 
//// This source is distributed in the hope that it will be       ////
1678 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1679 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1680 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1681 
//// details.                                                     ////
1682 
////                                                              ////
1683 
//// You should have received a copy of the GNU Lesser General    ////
1684 
//// Public License along with this source; if not, download it   ////
1685 
//// from http://www.opencores.org/lgpl.shtml                     ////
1686 
////                                                              ////
1687 
//////////////////////////////////////////////////////////////////////
1688 
 
1689 
// binary counter
1690 22 unneback 
 
1691 40 unneback 
`define MODULE cnt_bin
1692 
module `BASE`MODULE (
1693 
`undef MODULE
1694 
 q, rst, clk);
1695 
 
1696 22 unneback 
   parameter length = 4;
1697 
   output [length:1] q;
1698 
   input rst;
1699 
   input clk;
1700 
 
1701 
   parameter clear_value = 0;
1702 
   parameter set_value = 1;
1703 
   parameter wrap_value = 0;
1704 
   parameter level1_value = 15;
1705 
 
1706 
   reg  [length:1] qi;
1707 
   wire [length:1] q_next;
1708 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1709 
 
1710 
   always @ (posedge clk or posedge rst)
1711 
     if (rst)
1712 
       qi <= {length{1'b0}};
1713 
     else
1714 
       qi <= q_next;
1715 
 
1716 
   assign q = qi;
1717 
 
1718 
endmodule
1719 40 unneback 
`endif
1720 
`ifdef CNT_BIN_CLEAR
1721 22 unneback 
//////////////////////////////////////////////////////////////////////
1722 
////                                                              ////
1723 
////  Versatile counter                                           ////
1724 
////                                                              ////
1725 
////  Description                                                 ////
1726 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1727 
////  counter                                                     ////
1728 
////                                                              ////
1729 
////  To Do:                                                      ////
1730 
////   - add LFSR with more taps                                  ////
1731 
////                                                              ////
1732 
////  Author(s):                                                  ////
1733 
////      - Michael Unneback, unneback@opencores.org              ////
1734 
////        ORSoC AB                                              ////
1735 
////                                                              ////
1736 
//////////////////////////////////////////////////////////////////////
1737 
////                                                              ////
1738 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1739 
////                                                              ////
1740 
//// This source file may be used and distributed without         ////
1741 
//// restriction provided that this copyright statement is not    ////
1742 
//// removed from the file and that any derivative work contains  ////
1743 
//// the original copyright notice and the associated disclaimer. ////
1744 
////                                                              ////
1745 
//// This source file is free software; you can redistribute it   ////
1746 
//// and/or modify it under the terms of the GNU Lesser General   ////
1747 
//// Public License as published by the Free Software Foundation; ////
1748 
//// either version 2.1 of the License, or (at your option) any   ////
1749 
//// later version.                                               ////
1750 
////                                                              ////
1751 
//// This source is distributed in the hope that it will be       ////
1752 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1753 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1754 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1755 
//// details.                                                     ////
1756 
////                                                              ////
1757 
//// You should have received a copy of the GNU Lesser General    ////
1758 
//// Public License along with this source; if not, download it   ////
1759 
//// from http://www.opencores.org/lgpl.shtml                     ////
1760 
////                                                              ////
1761 
//////////////////////////////////////////////////////////////////////
1762 
 
1763 
// binary counter
1764 
 
1765 40 unneback 
`define MODULE cnt_bin_clear
1766 
module `BASE`MODULE (
1767 
`undef MODULE
1768 
 clear, q, rst, clk);
1769 
 
1770 22 unneback 
   parameter length = 4;
1771 
   input clear;
1772 
   output [length:1] q;
1773 
   input rst;
1774 
   input clk;
1775 
 
1776 
   parameter clear_value = 0;
1777 
   parameter set_value = 1;
1778 
   parameter wrap_value = 0;
1779 
   parameter level1_value = 15;
1780 
 
1781 
   reg  [length:1] qi;
1782 
   wire [length:1] q_next;
1783 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1784 
 
1785 
   always @ (posedge clk or posedge rst)
1786 
     if (rst)
1787 
       qi <= {length{1'b0}};
1788 
     else
1789 
       qi <= q_next;
1790 
 
1791 
   assign q = qi;
1792 
 
1793 
endmodule
1794 40 unneback 
`endif
1795 
`ifdef CNT_BIN_CE
1796 22 unneback 
//////////////////////////////////////////////////////////////////////
1797 
////                                                              ////
1798 
////  Versatile counter                                           ////
1799 
////                                                              ////
1800 
////  Description                                                 ////
1801 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1802 
////  counter                                                     ////
1803 
////                                                              ////
1804 
////  To Do:                                                      ////
1805 
////   - add LFSR with more taps                                  ////
1806 
////                                                              ////
1807 
////  Author(s):                                                  ////
1808 
////      - Michael Unneback, unneback@opencores.org              ////
1809 
////        ORSoC AB                                              ////
1810 
////                                                              ////
1811 
//////////////////////////////////////////////////////////////////////
1812 
////                                                              ////
1813 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1814 
////                                                              ////
1815 
//// This source file may be used and distributed without         ////
1816 
//// restriction provided that this copyright statement is not    ////
1817 
//// removed from the file and that any derivative work contains  ////
1818 
//// the original copyright notice and the associated disclaimer. ////
1819 
////                                                              ////
1820 
//// This source file is free software; you can redistribute it   ////
1821 
//// and/or modify it under the terms of the GNU Lesser General   ////
1822 
//// Public License as published by the Free Software Foundation; ////
1823 
//// either version 2.1 of the License, or (at your option) any   ////
1824 
//// later version.                                               ////
1825 
////                                                              ////
1826 
//// This source is distributed in the hope that it will be       ////
1827 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1828 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1829 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1830 
//// details.                                                     ////
1831 
////                                                              ////
1832 
//// You should have received a copy of the GNU Lesser General    ////
1833 
//// Public License along with this source; if not, download it   ////
1834 
//// from http://www.opencores.org/lgpl.shtml                     ////
1835 
////                                                              ////
1836 
//////////////////////////////////////////////////////////////////////
1837 
 
1838 
// binary counter
1839 6 unneback 
 
1840 40 unneback 
`define MODULE cnt_bin_ce
1841 
module `BASE`MODULE (
1842 
`undef MODULE
1843 
 cke, q, rst, clk);
1844 
 
1845 6 unneback 
   parameter length = 4;
1846 
   input cke;
1847 
   output [length:1] q;
1848 
   input rst;
1849 
   input clk;
1850 
 
1851 
   parameter clear_value = 0;
1852 
   parameter set_value = 1;
1853 
   parameter wrap_value = 0;
1854 
   parameter level1_value = 15;
1855 
 
1856 
   reg  [length:1] qi;
1857 
   wire [length:1] q_next;
1858 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1859 
 
1860 
   always @ (posedge clk or posedge rst)
1861 
     if (rst)
1862 
       qi <= {length{1'b0}};
1863 
     else
1864 
     if (cke)
1865 
       qi <= q_next;
1866 
 
1867 
   assign q = qi;
1868 
 
1869 
endmodule
1870 40 unneback 
`endif
1871 
`ifdef CNT_BIN_CE_CLEAR
1872 6 unneback 
//////////////////////////////////////////////////////////////////////
1873 
////                                                              ////
1874 
////  Versatile counter                                           ////
1875 
////                                                              ////
1876 
////  Description                                                 ////
1877 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1878 
////  counter                                                     ////
1879 
////                                                              ////
1880 
////  To Do:                                                      ////
1881 
////   - add LFSR with more taps                                  ////
1882 
////                                                              ////
1883 
////  Author(s):                                                  ////
1884 
////      - Michael Unneback, unneback@opencores.org              ////
1885 
////        ORSoC AB                                              ////
1886 
////                                                              ////
1887 
//////////////////////////////////////////////////////////////////////
1888 
////                                                              ////
1889 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1890 
////                                                              ////
1891 
//// This source file may be used and distributed without         ////
1892 
//// restriction provided that this copyright statement is not    ////
1893 
//// removed from the file and that any derivative work contains  ////
1894 
//// the original copyright notice and the associated disclaimer. ////
1895 
////                                                              ////
1896 
//// This source file is free software; you can redistribute it   ////
1897 
//// and/or modify it under the terms of the GNU Lesser General   ////
1898 
//// Public License as published by the Free Software Foundation; ////
1899 
//// either version 2.1 of the License, or (at your option) any   ////
1900 
//// later version.                                               ////
1901 
////                                                              ////
1902 
//// This source is distributed in the hope that it will be       ////
1903 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1904 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1905 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1906 
//// details.                                                     ////
1907 
////                                                              ////
1908 
//// You should have received a copy of the GNU Lesser General    ////
1909 
//// Public License along with this source; if not, download it   ////
1910 
//// from http://www.opencores.org/lgpl.shtml                     ////
1911 
////                                                              ////
1912 
//////////////////////////////////////////////////////////////////////
1913 
 
1914 
// binary counter
1915 
 
1916 40 unneback 
`define MODULE cnt_bin_ce_clear
1917 
module `BASE`MODULE (
1918 
`undef MODULE
1919 
 clear, cke, q, rst, clk);
1920 
 
1921 6 unneback 
   parameter length = 4;
1922 
   input clear;
1923 
   input cke;
1924 
   output [length:1] q;
1925 
   input rst;
1926 
   input clk;
1927 
 
1928 
   parameter clear_value = 0;
1929 
   parameter set_value = 1;
1930 
   parameter wrap_value = 0;
1931 
   parameter level1_value = 15;
1932 
 
1933 
   reg  [length:1] qi;
1934 
   wire [length:1] q_next;
1935 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1936 
 
1937 
   always @ (posedge clk or posedge rst)
1938 
     if (rst)
1939 
       qi <= {length{1'b0}};
1940 
     else
1941 
     if (cke)
1942 
       qi <= q_next;
1943 
 
1944 
   assign q = qi;
1945 
 
1946 
endmodule
1947 40 unneback 
`endif
1948 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1949 6 unneback 
//////////////////////////////////////////////////////////////////////
1950 
////                                                              ////
1951 
////  Versatile counter                                           ////
1952 
////                                                              ////
1953 
////  Description                                                 ////
1954 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1955 
////  counter                                                     ////
1956 
////                                                              ////
1957 
////  To Do:                                                      ////
1958 
////   - add LFSR with more taps                                  ////
1959 
////                                                              ////
1960 
////  Author(s):                                                  ////
1961 
////      - Michael Unneback, unneback@opencores.org              ////
1962 
////        ORSoC AB                                              ////
1963 
////                                                              ////
1964 
//////////////////////////////////////////////////////////////////////
1965 
////                                                              ////
1966 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1967 
////                                                              ////
1968 
//// This source file may be used and distributed without         ////
1969 
//// restriction provided that this copyright statement is not    ////
1970 
//// removed from the file and that any derivative work contains  ////
1971 
//// the original copyright notice and the associated disclaimer. ////
1972 
////                                                              ////
1973 
//// This source file is free software; you can redistribute it   ////
1974 
//// and/or modify it under the terms of the GNU Lesser General   ////
1975 
//// Public License as published by the Free Software Foundation; ////
1976 
//// either version 2.1 of the License, or (at your option) any   ////
1977 
//// later version.                                               ////
1978 
////                                                              ////
1979 
//// This source is distributed in the hope that it will be       ////
1980 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1981 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1982 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1983 
//// details.                                                     ////
1984 
////                                                              ////
1985 
//// You should have received a copy of the GNU Lesser General    ////
1986 
//// Public License along with this source; if not, download it   ////
1987 
//// from http://www.opencores.org/lgpl.shtml                     ////
1988 
////                                                              ////
1989 
//////////////////////////////////////////////////////////////////////
1990 
 
1991 
// binary counter
1992 29 unneback 
 
1993 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1994 
module `BASE`MODULE (
1995 
`undef MODULE
1996 
 clear, cke, q, level1, level2, rst, clk);
1997 
 
1998 29 unneback 
   parameter length = 4;
1999 
   input clear;
2000 
   input cke;
2001 
   output [length:1] q;
2002 
   output reg level1;
2003 
   output reg level2;
2004 
   input rst;
2005 
   input clk;
2006 
 
2007 
   parameter clear_value = 0;
2008 
   parameter set_value = 1;
2009 30 unneback 
   parameter wrap_value = 15;
2010 
   parameter level1_value = 8;
2011 
   parameter level2_value = 15;
2012 29 unneback 
 
2013 
   wire rew;
2014 30 unneback 
   assign rew = 1'b0;
2015 29 unneback 
   reg  [length:1] qi;
2016 
   wire [length:1] q_next;
2017 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2018 
 
2019 
   always @ (posedge clk or posedge rst)
2020 
     if (rst)
2021 
       qi <= {length{1'b0}};
2022 
     else
2023 
     if (cke)
2024 
       qi <= q_next;
2025 
 
2026 
   assign q = qi;
2027 
 
2028 
 
2029 
    always @ (posedge clk or posedge rst)
2030 
    if (rst)
2031 
        level1 <= 1'b0;
2032 
    else
2033 
    if (cke)
2034 
    if (clear)
2035 
        level1 <= 1'b0;
2036 
    else if (q_next == level1_value)
2037 
        level1 <= 1'b1;
2038 
    else if (qi == level1_value & rew)
2039 
        level1 <= 1'b0;
2040 
 
2041 
    always @ (posedge clk or posedge rst)
2042 
    if (rst)
2043 
        level2 <= 1'b0;
2044 
    else
2045 
    if (cke)
2046 
    if (clear)
2047 
        level2 <= 1'b0;
2048 
    else if (q_next == level2_value)
2049 
        level2 <= 1'b1;
2050 
    else if (qi == level2_value & rew)
2051 
        level2 <= 1'b0;
2052 
endmodule
2053 40 unneback 
`endif
2054 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2055 29 unneback 
//////////////////////////////////////////////////////////////////////
2056 
////                                                              ////
2057 
////  Versatile counter                                           ////
2058 
////                                                              ////
2059 
////  Description                                                 ////
2060 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2061 
////  counter                                                     ////
2062 
////                                                              ////
2063 
////  To Do:                                                      ////
2064 
////   - add LFSR with more taps                                  ////
2065 
////                                                              ////
2066 
////  Author(s):                                                  ////
2067 
////      - Michael Unneback, unneback@opencores.org              ////
2068 
////        ORSoC AB                                              ////
2069 
////                                                              ////
2070 
//////////////////////////////////////////////////////////////////////
2071 
////                                                              ////
2072 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2073 
////                                                              ////
2074 
//// This source file may be used and distributed without         ////
2075 
//// restriction provided that this copyright statement is not    ////
2076 
//// removed from the file and that any derivative work contains  ////
2077 
//// the original copyright notice and the associated disclaimer. ////
2078 
////                                                              ////
2079 
//// This source file is free software; you can redistribute it   ////
2080 
//// and/or modify it under the terms of the GNU Lesser General   ////
2081 
//// Public License as published by the Free Software Foundation; ////
2082 
//// either version 2.1 of the License, or (at your option) any   ////
2083 
//// later version.                                               ////
2084 
////                                                              ////
2085 
//// This source is distributed in the hope that it will be       ////
2086 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2087 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2088 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2089 
//// details.                                                     ////
2090 
////                                                              ////
2091 
//// You should have received a copy of the GNU Lesser General    ////
2092 
//// Public License along with this source; if not, download it   ////
2093 
//// from http://www.opencores.org/lgpl.shtml                     ////
2094 
////                                                              ////
2095 
//////////////////////////////////////////////////////////////////////
2096 
 
2097 
// binary counter
2098 6 unneback 
 
2099 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
2100 
module `BASE`MODULE (
2101 
`undef MODULE
2102 
 clear, set, cke, rew, q, rst, clk);
2103 
 
2104 6 unneback 
   parameter length = 4;
2105 
   input clear;
2106 
   input set;
2107 
   input cke;
2108 
   input rew;
2109 
   output [length:1] q;
2110 
   input rst;
2111 
   input clk;
2112 
 
2113 
   parameter clear_value = 0;
2114 
   parameter set_value = 1;
2115 
   parameter wrap_value = 0;
2116 
   parameter level1_value = 15;
2117 
 
2118 
   reg  [length:1] qi;
2119 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2120 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2121 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2122 
   assign q_next = rew ? q_next_rew : q_next_fw;
2123 
 
2124 
   always @ (posedge clk or posedge rst)
2125 
     if (rst)
2126 
       qi <= {length{1'b0}};
2127 
     else
2128 
     if (cke)
2129 
       qi <= q_next;
2130 
 
2131 
   assign q = qi;
2132 
 
2133 
endmodule
2134 40 unneback 
`endif
2135 
`ifdef CNT_BIN_CE_REW_L1
2136 6 unneback 
//////////////////////////////////////////////////////////////////////
2137 
////                                                              ////
2138 
////  Versatile counter                                           ////
2139 
////                                                              ////
2140 
////  Description                                                 ////
2141 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2142 
////  counter                                                     ////
2143 
////                                                              ////
2144 
////  To Do:                                                      ////
2145 
////   - add LFSR with more taps                                  ////
2146 
////                                                              ////
2147 
////  Author(s):                                                  ////
2148 
////      - Michael Unneback, unneback@opencores.org              ////
2149 
////        ORSoC AB                                              ////
2150 
////                                                              ////
2151 
//////////////////////////////////////////////////////////////////////
2152 
////                                                              ////
2153 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2154 
////                                                              ////
2155 
//// This source file may be used and distributed without         ////
2156 
//// restriction provided that this copyright statement is not    ////
2157 
//// removed from the file and that any derivative work contains  ////
2158 
//// the original copyright notice and the associated disclaimer. ////
2159 
////                                                              ////
2160 
//// This source file is free software; you can redistribute it   ////
2161 
//// and/or modify it under the terms of the GNU Lesser General   ////
2162 
//// Public License as published by the Free Software Foundation; ////
2163 
//// either version 2.1 of the License, or (at your option) any   ////
2164 
//// later version.                                               ////
2165 
////                                                              ////
2166 
//// This source is distributed in the hope that it will be       ////
2167 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2168 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2169 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2170 
//// details.                                                     ////
2171 
////                                                              ////
2172 
//// You should have received a copy of the GNU Lesser General    ////
2173 
//// Public License along with this source; if not, download it   ////
2174 
//// from http://www.opencores.org/lgpl.shtml                     ////
2175 
////                                                              ////
2176 
//////////////////////////////////////////////////////////////////////
2177 
 
2178 
// binary counter
2179 
 
2180 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
2181 
module `BASE`MODULE (
2182 
`undef MODULE
2183 
 cke, rew, level1, rst, clk);
2184 
 
2185 6 unneback 
   parameter length = 4;
2186 
   input cke;
2187 
   input rew;
2188 
   output reg level1;
2189 
   input rst;
2190 
   input clk;
2191 
 
2192 
   parameter clear_value = 0;
2193 
   parameter set_value = 1;
2194 
   parameter wrap_value = 1;
2195 
   parameter level1_value = 15;
2196 
 
2197 29 unneback 
   wire clear;
2198 30 unneback 
   assign clear = 1'b0;
2199 6 unneback 
   reg  [length:1] qi;
2200 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2201 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2202 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2203 
   assign q_next = rew ? q_next_rew : q_next_fw;
2204 
 
2205 
   always @ (posedge clk or posedge rst)
2206 
     if (rst)
2207 
       qi <= {length{1'b0}};
2208 
     else
2209 
     if (cke)
2210 
       qi <= q_next;
2211 
 
2212 
 
2213 
 
2214 
    always @ (posedge clk or posedge rst)
2215 
    if (rst)
2216 
        level1 <= 1'b0;
2217 
    else
2218 
    if (cke)
2219 29 unneback 
    if (clear)
2220 
        level1 <= 1'b0;
2221 
    else if (q_next == level1_value)
2222 6 unneback 
        level1 <= 1'b1;
2223 
    else if (qi == level1_value & rew)
2224 
        level1 <= 1'b0;
2225 
endmodule
2226 40 unneback 
`endif
2227 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2228 6 unneback 
//////////////////////////////////////////////////////////////////////
2229 
////                                                              ////
2230 
////  Versatile counter                                           ////
2231 
////                                                              ////
2232 
////  Description                                                 ////
2233 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2234 
////  counter                                                     ////
2235 
////                                                              ////
2236 
////  To Do:                                                      ////
2237 
////   - add LFSR with more taps                                  ////
2238 
////                                                              ////
2239 
////  Author(s):                                                  ////
2240 
////      - Michael Unneback, unneback@opencores.org              ////
2241 
////        ORSoC AB                                              ////
2242 
////                                                              ////
2243 
//////////////////////////////////////////////////////////////////////
2244 
////                                                              ////
2245 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2246 
////                                                              ////
2247 
//// This source file may be used and distributed without         ////
2248 
//// restriction provided that this copyright statement is not    ////
2249 
//// removed from the file and that any derivative work contains  ////
2250 
//// the original copyright notice and the associated disclaimer. ////
2251 
////                                                              ////
2252 
//// This source file is free software; you can redistribute it   ////
2253 
//// and/or modify it under the terms of the GNU Lesser General   ////
2254 
//// Public License as published by the Free Software Foundation; ////
2255 
//// either version 2.1 of the License, or (at your option) any   ////
2256 
//// later version.                                               ////
2257 
////                                                              ////
2258 
//// This source is distributed in the hope that it will be       ////
2259 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2260 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2261 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2262 
//// details.                                                     ////
2263 
////                                                              ////
2264 
//// You should have received a copy of the GNU Lesser General    ////
2265 
//// Public License along with this source; if not, download it   ////
2266 
//// from http://www.opencores.org/lgpl.shtml                     ////
2267 
////                                                              ////
2268 
//////////////////////////////////////////////////////////////////////
2269 
 
2270 25 unneback 
// binary counter
2271 
 
2272 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2273 
module `BASE`MODULE (
2274 
`undef MODULE
2275 
 cke, rew, zq, level1, rst, clk);
2276 
 
2277 25 unneback 
   parameter length = 4;
2278 
   input cke;
2279 
   input rew;
2280 
   output reg zq;
2281 
   output reg level1;
2282 
   input rst;
2283 
   input clk;
2284 
 
2285 
   parameter clear_value = 0;
2286 
   parameter set_value = 1;
2287 
   parameter wrap_value = 1;
2288 
   parameter level1_value = 15;
2289 
 
2290 29 unneback 
   wire clear;
2291 30 unneback 
   assign clear = 1'b0;
2292 25 unneback 
   reg  [length:1] qi;
2293 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2294 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2295 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2296 
   assign q_next = rew ? q_next_rew : q_next_fw;
2297 
 
2298 
   always @ (posedge clk or posedge rst)
2299 
     if (rst)
2300 
       qi <= {length{1'b0}};
2301 
     else
2302 
     if (cke)
2303 
       qi <= q_next;
2304 
 
2305 
 
2306 
 
2307 
   always @ (posedge clk or posedge rst)
2308 
     if (rst)
2309 
       zq <= 1'b1;
2310 
     else
2311 
     if (cke)
2312 
       zq <= q_next == {length{1'b0}};
2313 
 
2314 
    always @ (posedge clk or posedge rst)
2315 
    if (rst)
2316 
        level1 <= 1'b0;
2317 
    else
2318 
    if (cke)
2319 29 unneback 
    if (clear)
2320 
        level1 <= 1'b0;
2321 
    else if (q_next == level1_value)
2322 25 unneback 
        level1 <= 1'b1;
2323 
    else if (qi == level1_value & rew)
2324 
        level1 <= 1'b0;
2325 
endmodule
2326 40 unneback 
`endif
2327 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2328 25 unneback 
//////////////////////////////////////////////////////////////////////
2329 
////                                                              ////
2330 
////  Versatile counter                                           ////
2331 
////                                                              ////
2332 
////  Description                                                 ////
2333 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2334 
////  counter                                                     ////
2335 
////                                                              ////
2336 
////  To Do:                                                      ////
2337 
////   - add LFSR with more taps                                  ////
2338 
////                                                              ////
2339 
////  Author(s):                                                  ////
2340 
////      - Michael Unneback, unneback@opencores.org              ////
2341 
////        ORSoC AB                                              ////
2342 
////                                                              ////
2343 
//////////////////////////////////////////////////////////////////////
2344 
////                                                              ////
2345 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2346 
////                                                              ////
2347 
//// This source file may be used and distributed without         ////
2348 
//// restriction provided that this copyright statement is not    ////
2349 
//// removed from the file and that any derivative work contains  ////
2350 
//// the original copyright notice and the associated disclaimer. ////
2351 
////                                                              ////
2352 
//// This source file is free software; you can redistribute it   ////
2353 
//// and/or modify it under the terms of the GNU Lesser General   ////
2354 
//// Public License as published by the Free Software Foundation; ////
2355 
//// either version 2.1 of the License, or (at your option) any   ////
2356 
//// later version.                                               ////
2357 
////                                                              ////
2358 
//// This source is distributed in the hope that it will be       ////
2359 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2360 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2361 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2362 
//// details.                                                     ////
2363 
////                                                              ////
2364 
//// You should have received a copy of the GNU Lesser General    ////
2365 
//// Public License along with this source; if not, download it   ////
2366 
//// from http://www.opencores.org/lgpl.shtml                     ////
2367 
////                                                              ////
2368 
//////////////////////////////////////////////////////////////////////
2369 
 
2370 
// binary counter
2371 
 
2372 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2373 
module `BASE`MODULE (
2374 
`undef MODULE
2375 
 cke, rew, q, zq, level1, rst, clk);
2376 
 
2377 25 unneback 
   parameter length = 4;
2378 
   input cke;
2379 
   input rew;
2380 
   output [length:1] q;
2381 
   output reg zq;
2382 
   output reg level1;
2383 
   input rst;
2384 
   input clk;
2385 
 
2386 
   parameter clear_value = 0;
2387 
   parameter set_value = 1;
2388 
   parameter wrap_value = 1;
2389 
   parameter level1_value = 15;
2390 
 
2391 29 unneback 
   wire clear;
2392 30 unneback 
   assign clear = 1'b0;
2393 25 unneback 
   reg  [length:1] qi;
2394 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2395 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2396 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2397 
   assign q_next = rew ? q_next_rew : q_next_fw;
2398 
 
2399 
   always @ (posedge clk or posedge rst)
2400 
     if (rst)
2401 
       qi <= {length{1'b0}};
2402 
     else
2403 
     if (cke)
2404 
       qi <= q_next;
2405 
 
2406 
   assign q = qi;
2407 
 
2408 
 
2409 
   always @ (posedge clk or posedge rst)
2410 
     if (rst)
2411 
       zq <= 1'b1;
2412 
     else
2413 
     if (cke)
2414 
       zq <= q_next == {length{1'b0}};
2415 
 
2416 
    always @ (posedge clk or posedge rst)
2417 
    if (rst)
2418 
        level1 <= 1'b0;
2419 
    else
2420 
    if (cke)
2421 29 unneback 
    if (clear)
2422 
        level1 <= 1'b0;
2423 
    else if (q_next == level1_value)
2424 25 unneback 
        level1 <= 1'b1;
2425 
    else if (qi == level1_value & rew)
2426 
        level1 <= 1'b0;
2427 
endmodule
2428 40 unneback 
`endif
2429 
`ifdef CNT_LFSR_ZQ
2430 25 unneback 
//////////////////////////////////////////////////////////////////////
2431 
////                                                              ////
2432 
////  Versatile counter                                           ////
2433 
////                                                              ////
2434 
////  Description                                                 ////
2435 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2436 
////  counter                                                     ////
2437 
////                                                              ////
2438 
////  To Do:                                                      ////
2439 
////   - add LFSR with more taps                                  ////
2440 
////                                                              ////
2441 
////  Author(s):                                                  ////
2442 
////      - Michael Unneback, unneback@opencores.org              ////
2443 
////        ORSoC AB                                              ////
2444 
////                                                              ////
2445 
//////////////////////////////////////////////////////////////////////
2446 
////                                                              ////
2447 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2448 
////                                                              ////
2449 
//// This source file may be used and distributed without         ////
2450 
//// restriction provided that this copyright statement is not    ////
2451 
//// removed from the file and that any derivative work contains  ////
2452 
//// the original copyright notice and the associated disclaimer. ////
2453 
////                                                              ////
2454 
//// This source file is free software; you can redistribute it   ////
2455 
//// and/or modify it under the terms of the GNU Lesser General   ////
2456 
//// Public License as published by the Free Software Foundation; ////
2457 
//// either version 2.1 of the License, or (at your option) any   ////
2458 
//// later version.                                               ////
2459 
////                                                              ////
2460 
//// This source is distributed in the hope that it will be       ////
2461 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2462 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2463 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2464 
//// details.                                                     ////
2465 
////                                                              ////
2466 
//// You should have received a copy of the GNU Lesser General    ////
2467 
//// Public License along with this source; if not, download it   ////
2468 
//// from http://www.opencores.org/lgpl.shtml                     ////
2469 
////                                                              ////
2470 
//////////////////////////////////////////////////////////////////////
2471 
 
2472 6 unneback 
// LFSR counter
2473 
 
2474 40 unneback 
`define MODULE cnt_lfsr_zq
2475 
module `BASE`MODULE (
2476 
`undef MODULE
2477 
 zq, rst, clk);
2478 
 
2479 6 unneback 
   parameter length = 4;
2480 
   output reg zq;
2481 
   input rst;
2482 
   input clk;
2483 
 
2484 
   parameter clear_value = 0;
2485 
   parameter set_value = 1;
2486 
   parameter wrap_value = 8;
2487 
   parameter level1_value = 15;
2488 
 
2489 
   reg  [length:1] qi;
2490 
   reg lfsr_fb;
2491 
   wire [length:1] q_next;
2492 
   reg [32:1] polynom;
2493 
   integer i;
2494 
 
2495 
   always @ (qi)
2496 
   begin
2497 
        case (length)
2498 
         2: polynom = 32'b11;                               // 0x3
2499 
         3: polynom = 32'b110;                              // 0x6
2500 
         4: polynom = 32'b1100;                             // 0xC
2501 
         5: polynom = 32'b10100;                            // 0x14
2502 
         6: polynom = 32'b110000;                           // 0x30
2503 
         7: polynom = 32'b1100000;                          // 0x60
2504 
         8: polynom = 32'b10111000;                         // 0xb8
2505 
         9: polynom = 32'b100010000;                        // 0x110
2506 
        10: polynom = 32'b1001000000;                       // 0x240
2507 
        11: polynom = 32'b10100000000;                      // 0x500
2508 
        12: polynom = 32'b100000101001;                     // 0x829
2509 
        13: polynom = 32'b1000000001100;                    // 0x100C
2510 
        14: polynom = 32'b10000000010101;                   // 0x2015
2511 
        15: polynom = 32'b110000000000000;                  // 0x6000
2512 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2513 
        17: polynom = 32'b10010000000000000;                // 0x12000
2514 
        18: polynom = 32'b100000010000000000;               // 0x20400
2515 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2516 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2517 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2518 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2519 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2520 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2521 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2522 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2523 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2524 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2525 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2526 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2527 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2528 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2529 
        default: polynom = 32'b0;
2530 
        endcase
2531 
        lfsr_fb = qi[length];
2532 
        for (i=length-1; i>=1; i=i-1) begin
2533 
            if (polynom[i])
2534 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2535 
        end
2536 
    end
2537 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2538 
 
2539 
   always @ (posedge clk or posedge rst)
2540 
     if (rst)
2541 
       qi <= {length{1'b0}};
2542 
     else
2543 
       qi <= q_next;
2544 
 
2545 
 
2546 
 
2547 
   always @ (posedge clk or posedge rst)
2548 
     if (rst)
2549 
       zq <= 1'b1;
2550 
     else
2551 
       zq <= q_next == {length{1'b0}};
2552 
endmodule
2553 40 unneback 
`endif
2554 75 unneback 
`ifdef CNT_LFSR_CE
2555 
//////////////////////////////////////////////////////////////////////
2556 
////                                                              ////
2557 
////  Versatile counter                                           ////
2558 
////                                                              ////
2559 
////  Description                                                 ////
2560 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2561 
////  counter                                                     ////
2562 
////                                                              ////
2563 
////  To Do:                                                      ////
2564 
////   - add LFSR with more taps                                  ////
2565 
////                                                              ////
2566 
////  Author(s):                                                  ////
2567 
////      - Michael Unneback, unneback@opencores.org              ////
2568 
////        ORSoC AB                                              ////
2569 
////                                                              ////
2570 
//////////////////////////////////////////////////////////////////////
2571 
////                                                              ////
2572 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2573 
////                                                              ////
2574 
//// This source file may be used and distributed without         ////
2575 
//// restriction provided that this copyright statement is not    ////
2576 
//// removed from the file and that any derivative work contains  ////
2577 
//// the original copyright notice and the associated disclaimer. ////
2578 
////                                                              ////
2579 
//// This source file is free software; you can redistribute it   ////
2580 
//// and/or modify it under the terms of the GNU Lesser General   ////
2581 
//// Public License as published by the Free Software Foundation; ////
2582 
//// either version 2.1 of the License, or (at your option) any   ////
2583 
//// later version.                                               ////
2584 
////                                                              ////
2585 
//// This source is distributed in the hope that it will be       ////
2586 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2587 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2588 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2589 
//// details.                                                     ////
2590 
////                                                              ////
2591 
//// You should have received a copy of the GNU Lesser General    ////
2592 
//// Public License along with this source; if not, download it   ////
2593 
//// from http://www.opencores.org/lgpl.shtml                     ////
2594 
////                                                              ////
2595 
//////////////////////////////////////////////////////////////////////
2596 
 
2597 
// LFSR counter
2598 
 
2599 
`define MODULE cnt_lfsr_ce
2600 
module `BASE`MODULE (
2601 
`undef MODULE
2602 
 cke, zq, rst, clk);
2603 
 
2604 
   parameter length = 4;
2605 
   input cke;
2606 
   output reg zq;
2607 
   input rst;
2608 
   input clk;
2609 
 
2610 
   parameter clear_value = 0;
2611 
   parameter set_value = 1;
2612 
   parameter wrap_value = 0;
2613 
   parameter level1_value = 15;
2614 
 
2615 
   reg  [length:1] qi;
2616 
   reg lfsr_fb;
2617 
   wire [length:1] q_next;
2618 
   reg [32:1] polynom;
2619 
   integer i;
2620 
 
2621 
   always @ (qi)
2622 
   begin
2623 
        case (length)
2624 
         2: polynom = 32'b11;                               // 0x3
2625 
         3: polynom = 32'b110;                              // 0x6
2626 
         4: polynom = 32'b1100;                             // 0xC
2627 
         5: polynom = 32'b10100;                            // 0x14
2628 
         6: polynom = 32'b110000;                           // 0x30
2629 
         7: polynom = 32'b1100000;                          // 0x60
2630 
         8: polynom = 32'b10111000;                         // 0xb8
2631 
         9: polynom = 32'b100010000;                        // 0x110
2632 
        10: polynom = 32'b1001000000;                       // 0x240
2633 
        11: polynom = 32'b10100000000;                      // 0x500
2634 
        12: polynom = 32'b100000101001;                     // 0x829
2635 
        13: polynom = 32'b1000000001100;                    // 0x100C
2636 
        14: polynom = 32'b10000000010101;                   // 0x2015
2637 
        15: polynom = 32'b110000000000000;                  // 0x6000
2638 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2639 
        17: polynom = 32'b10010000000000000;                // 0x12000
2640 
        18: polynom = 32'b100000010000000000;               // 0x20400
2641 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2642 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2643 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2644 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2645 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2646 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2647 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2648 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2649 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2650 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2651 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2652 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2653 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2654 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2655 
        default: polynom = 32'b0;
2656 
        endcase
2657 
        lfsr_fb = qi[length];
2658 
        for (i=length-1; i>=1; i=i-1) begin
2659 
            if (polynom[i])
2660 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2661 
        end
2662 
    end
2663 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2664 
 
2665 
   always @ (posedge clk or posedge rst)
2666 
     if (rst)
2667 
       qi <= {length{1'b0}};
2668 
     else
2669 
     if (cke)
2670 
       qi <= q_next;
2671 
 
2672 
 
2673 
 
2674 
   always @ (posedge clk or posedge rst)
2675 
     if (rst)
2676 
       zq <= 1'b1;
2677 
     else
2678 
     if (cke)
2679 
       zq <= q_next == {length{1'b0}};
2680 
endmodule
2681 
`endif
2682 40 unneback 
`ifdef CNT_LFSR_CE_ZQ
2683 6 unneback 
//////////////////////////////////////////////////////////////////////
2684 
////                                                              ////
2685 
////  Versatile counter                                           ////
2686 
////                                                              ////
2687 
////  Description                                                 ////
2688 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2689 
////  counter                                                     ////
2690 
////                                                              ////
2691 
////  To Do:                                                      ////
2692 
////   - add LFSR with more taps                                  ////
2693 
////                                                              ////
2694 
////  Author(s):                                                  ////
2695 
////      - Michael Unneback, unneback@opencores.org              ////
2696 
////        ORSoC AB                                              ////
2697 
////                                                              ////
2698 
//////////////////////////////////////////////////////////////////////
2699 
////                                                              ////
2700 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2701 
////                                                              ////
2702 
//// This source file may be used and distributed without         ////
2703 
//// restriction provided that this copyright statement is not    ////
2704 
//// removed from the file and that any derivative work contains  ////
2705 
//// the original copyright notice and the associated disclaimer. ////
2706 
////                                                              ////
2707 
//// This source file is free software; you can redistribute it   ////
2708 
//// and/or modify it under the terms of the GNU Lesser General   ////
2709 
//// Public License as published by the Free Software Foundation; ////
2710 
//// either version 2.1 of the License, or (at your option) any   ////
2711 
//// later version.                                               ////
2712 
////                                                              ////
2713 
//// This source is distributed in the hope that it will be       ////
2714 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2715 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2716 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2717 
//// details.                                                     ////
2718 
////                                                              ////
2719 
//// You should have received a copy of the GNU Lesser General    ////
2720 
//// Public License along with this source; if not, download it   ////
2721 
//// from http://www.opencores.org/lgpl.shtml                     ////
2722 
////                                                              ////
2723 
//////////////////////////////////////////////////////////////////////
2724 
 
2725 
// LFSR counter
2726 
 
2727 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2728 
module `BASE`MODULE (
2729 
`undef MODULE
2730 
 cke, zq, rst, clk);
2731 
 
2732 6 unneback 
   parameter length = 4;
2733 
   input cke;
2734 
   output reg zq;
2735 
   input rst;
2736 
   input clk;
2737 
 
2738 
   parameter clear_value = 0;
2739 
   parameter set_value = 1;
2740 
   parameter wrap_value = 8;
2741 
   parameter level1_value = 15;
2742 
 
2743 
   reg  [length:1] qi;
2744 
   reg lfsr_fb;
2745 
   wire [length:1] q_next;
2746 
   reg [32:1] polynom;
2747 
   integer i;
2748 
 
2749 
   always @ (qi)
2750 
   begin
2751 
        case (length)
2752 
         2: polynom = 32'b11;                               // 0x3
2753 
         3: polynom = 32'b110;                              // 0x6
2754 
         4: polynom = 32'b1100;                             // 0xC
2755 
         5: polynom = 32'b10100;                            // 0x14
2756 
         6: polynom = 32'b110000;                           // 0x30
2757 
         7: polynom = 32'b1100000;                          // 0x60
2758 
         8: polynom = 32'b10111000;                         // 0xb8
2759 
         9: polynom = 32'b100010000;                        // 0x110
2760 
        10: polynom = 32'b1001000000;                       // 0x240
2761 
        11: polynom = 32'b10100000000;                      // 0x500
2762 
        12: polynom = 32'b100000101001;                     // 0x829
2763 
        13: polynom = 32'b1000000001100;                    // 0x100C
2764 
        14: polynom = 32'b10000000010101;                   // 0x2015
2765 
        15: polynom = 32'b110000000000000;                  // 0x6000
2766 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2767 
        17: polynom = 32'b10010000000000000;                // 0x12000
2768 
        18: polynom = 32'b100000010000000000;               // 0x20400
2769 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2770 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2771 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2772 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2773 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2774 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2775 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2776 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2777 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2778 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2779 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2780 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2781 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2782 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2783 
        default: polynom = 32'b0;
2784 
        endcase
2785 
        lfsr_fb = qi[length];
2786 
        for (i=length-1; i>=1; i=i-1) begin
2787 
            if (polynom[i])
2788 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2789 
        end
2790 
    end
2791 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2792 
 
2793 
   always @ (posedge clk or posedge rst)
2794 
     if (rst)
2795 
       qi <= {length{1'b0}};
2796 
     else
2797 
     if (cke)
2798 
       qi <= q_next;
2799 
 
2800 
 
2801 
 
2802 
   always @ (posedge clk or posedge rst)
2803 
     if (rst)
2804 
       zq <= 1'b1;
2805 
     else
2806 
     if (cke)
2807 
       zq <= q_next == {length{1'b0}};
2808 
endmodule
2809 40 unneback 
`endif
2810 
`ifdef CNT_LFSR_CE_Q
2811 6 unneback 
//////////////////////////////////////////////////////////////////////
2812 
////                                                              ////
2813 
////  Versatile counter                                           ////
2814 
////                                                              ////
2815 
////  Description                                                 ////
2816 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2817 
////  counter                                                     ////
2818