OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 124

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
14
    // ACTEL FPGA should not use logic to handle rw collision
15
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16
`else
17
    `define SYN_NO_RW_CHECK
18
`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
23
`define SYNC_RST
24
`define PLL
25
 
26
`define MULTS
27
`define MULTS18X18
28
`define MULT
29
`define SHIFT_UNIT_32
30
`define LOGIC_UNIT
31
 
32
`define CNT_SHREG_WRAP
33
`define CNT_SHREG_CE_WRAP
34 105 unneback
`define CNT_SHREG_CLEAR
35 40 unneback
`define CNT_SHREG_CE_CLEAR
36
`define CNT_SHREG_CE_CLEAR_WRAP
37
 
38
`define MUX_ANDOR
39
`define MUX2_ANDOR
40
`define MUX3_ANDOR
41
`define MUX4_ANDOR
42
`define MUX5_ANDOR
43
`define MUX6_ANDOR
44 43 unneback
`define PARITY
45 40 unneback
 
46
`define ROM_INIT
47
`define RAM
48
`define RAM_BE
49
`define DPRAM_1R1W
50
`define DPRAM_2R1W
51 100 unneback
`define DPRAM_1R2W
52 40 unneback
`define DPRAM_2R2W
53 75 unneback
`define DPRAM_BE_2R2W
54 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
55
`define FIFO_2R2W_SYNC_SIMPLEX
56
`define FIFO_CMP_ASYNC
57
`define FIFO_1R1W_ASYNC
58
`define FIFO_2R2W_ASYNC
59
`define FIFO_2R2W_ASYNC_SIMPLEX
60 48 unneback
`define REG_FILE
61 40 unneback
 
62
`define DFF
63
`define DFF_ARRAY
64
`define DFF_CE
65
`define DFF_CE_CLEAR
66
`define DF_CE_SET
67
`define SPR
68
`define SRP
69
`define DFF_SR
70
`define LATCH
71
`define SHREG
72
`define SHREG_CE
73
`define DELAY
74
`define DELAY_EMPTYFLAG
75 94 unneback
`define PULSE2TOGGLE
76
`define TOGGLE2PULSE
77
`define SYNCHRONIZER
78
`define CDC
79 40 unneback
 
80 75 unneback
`define WB3AVALON_BRIDGE
81 40 unneback
`define WB3WB3_BRIDGE
82
`define WB3_ARBITER_TYPE1
83 83 unneback
`define WB_ADR_INC
84 101 unneback
`define WB_RAM
85 103 unneback
`define WB_SHADOW_RAM
86 48 unneback
`define WB_B4_ROM
87 40 unneback
`define WB_BOOT_ROM
88
`define WB_DPRAM
89 101 unneback
`define WB_CACHE
90 103 unneback
`define WB_AVALON_BRIDGE
91
`define WB_AVALON_MEM_CACHE
92 40 unneback
 
93 44 unneback
`define IO_DFF_OE
94
`define O_DFF
95
 
96 40 unneback
`endif
97
 
98
`ifdef PLL
99
`ifndef SYNC_RST
100
`define SYNC_RST
101
`endif
102
`endif
103
 
104
`ifdef SYNC_RST
105
`ifndef GBUF
106
`define GBUF
107
`endif
108
`endif
109
 
110 108 unneback
`ifdef WB_DPRAM
111 92 unneback
`ifndef WB_ADR_INC
112
`define WB_ADR_INC
113 40 unneback
`endif
114 92 unneback
`ifndef DPRAM_BE_2R2W
115
`define DPRAM_BE_2R2W
116 40 unneback
`endif
117
`endif
118
 
119
`ifdef WB3_ARBITER_TYPE1
120 42 unneback
`ifndef SPR
121
`define SPR
122
`endif
123 40 unneback
`ifndef MUX_ANDOR
124
`define MUX_ANDOR
125
`endif
126
`endif
127
 
128 76 unneback
`ifdef WB3AVALON_BRIDGE
129
`ifndef WB3WB3_BRIDGE
130
`define WB3WB3_BRIDGE
131
`endif
132
`endif
133
 
134 40 unneback
`ifdef WB3WB3_BRIDGE
135
`ifndef CNT_SHREG_CE_CLEAR
136
`define CNT_SHREG_CE_CLEAR
137
`endif
138
`ifndef DFF
139
`define DFF
140
`endif
141
`ifndef DFF_CE
142
`define DFF_CE
143
`endif
144
`ifndef CNT_SHREG_CE_CLEAR
145
`define CNT_SHREG_CE_CLEAR
146
`endif
147
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
148
`define FIFO_2R2W_ASYNC_SIMPLEX
149
`endif
150
`endif
151
 
152 103 unneback
 
153
`ifdef WB_AVALON_MEM_CACHE
154
`ifndef WB_SHADOW_RAM
155
`define WB_SHADOW_RAM
156
`endif
157
`ifndef WB_CACHE
158
`define WB_CACHE
159
`endif
160
`ifndef WB_AVALON_BRIDGE
161
`define WB_AVALON_BRIDGE
162
`endif
163
`endif
164
 
165 101 unneback
`ifdef WB_CACHE
166 100 unneback
`ifndef RAM
167
`define RAM
168
`endif
169
`ifndef WB_ADR_INC
170
`define WB_ADR_INC
171
`endif
172
`ifndef DPRAM_1R1W
173
`define DPRAM_1R1W
174
`endif
175
`ifndef DPRAM_1R2W
176
`define DPRAM_1R2W
177
`endif
178
`ifndef DPRAM_BE_2R2W
179
`define DPRAM_BE_2R2W
180
`endif
181
`ifndef CDC
182
`define CDC
183
`endif
184
`endif
185 103 unneback
 
186
`ifdef WB_SHADOW_RAM
187 115 unneback
`ifndef WB_RAM
188
`define WB_RAM
189 103 unneback
`endif
190
`endif
191
 
192
`ifdef WB_RAM
193
`ifndef WB_ADR_INC
194
`define WB_ADR_INC
195
`endif
196 114 unneback
`ifndef RAM_BE
197
`define RAM_BE
198 103 unneback
`endif
199 114 unneback
`endif
200
 
201 40 unneback
`ifdef MULTS18X18
202
`ifndef MULTS
203
`define MULTS
204
`endif
205
`endif
206
 
207
`ifdef SHIFT_UNIT_32
208
`ifndef MULTS
209
`define MULTS
210
`endif
211
`endif
212
 
213
`ifdef MUX2_ANDOR
214
`ifndef MUX_ANDOR
215
`define MUX_ANDOR
216
`endif
217
`endif
218
 
219
`ifdef MUX3_ANDOR
220
`ifndef MUX_ANDOR
221
`define MUX_ANDOR
222
`endif
223
`endif
224
 
225
`ifdef MUX4_ANDOR
226
`ifndef MUX_ANDOR
227
`define MUX_ANDOR
228
`endif
229
`endif
230
 
231
`ifdef MUX5_ANDOR
232
`ifndef MUX_ANDOR
233
`define MUX_ANDOR
234
`endif
235
`endif
236
 
237
`ifdef MUX6_ANDOR
238
`ifndef MUX_ANDOR
239
`define MUX_ANDOR
240
`endif
241
`endif
242
 
243
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
244
`ifndef CNT_BIN_CE
245
`define CNT_BIN_CE
246
`endif
247
`ifndef DPRAM_1R1W
248
`define DPRAM_1R1W
249
`endif
250
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
251
`define CNT_BIN_CE_REW_Q_ZQ_L1
252
`endif
253
`endif
254
 
255
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
256
`ifndef CNT_LFSR_CE
257
`define CNT_LFSR_CE
258
`endif
259
`ifndef DPRAM_2R2W
260
`define DPRAM_2R2W
261
`endif
262
`ifndef CNT_BIN_CE_REW_ZQ_L1
263
`define CNT_BIN_CE_REW_ZQ_L1
264
`endif
265
`endif
266
 
267
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
268
`ifndef CNT_GRAY_CE_BIN
269
`define CNT_GRAY_CE_BIN
270
`endif
271
`ifndef DPRAM_2R2W
272
`define DPRAM_2R2W
273
`endif
274
`ifndef FIFO_CMP_ASYNC
275
`define FIFO_CMP_ASYNC
276
`endif
277
`endif
278
 
279
`ifdef FIFO_2R2W_ASYNC
280
`ifndef FIFO_1R1W_ASYNC
281
`define FIFO_1R1W_ASYNC
282
`endif
283
`endif
284
 
285
`ifdef FIFO_1R1W_ASYNC
286
`ifndef CNT_GRAY_CE_BIN
287
`define CNT_GRAY_CE_BIN
288
`endif
289
`ifndef DPRAM_1R1W
290
`define DPRAM_1R1W
291
`endif
292
`ifndef FIFO_CMP_ASYNC
293
`define FIFO_CMP_ASYNC
294
`endif
295
`endif
296
 
297
`ifdef FIFO_CMP_ASYNC
298
`ifndef DFF_SR
299
`define DFF_SR
300
`endif
301
`ifndef DFF
302
`define DFF
303
`endif
304
`endif
305 48 unneback
 
306
`ifdef REG_FILE
307
`ifndef DPRAM_1R1W
308
`define DPRAM_1R1W
309
`endif
310
`endif
311 97 unneback
 
312 98 unneback
`ifdef CDC
313
`ifndef PULSE2TOGGLE
314
`define PULSE2TOGGLE
315
`endif
316
`ifndef TOGGLE2PULSE
317
`define TOGGLE2PULSE
318
`endif
319
`ifndef SYNCHRONIZER
320
`define SYNCHRONIZER
321
`endif
322
`endif
323
 
324 97 unneback
// size to width
325 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
326 62 unneback
//////////////////////////////////////////////////////////////////////
327 6 unneback
////                                                              ////
328
////  Versatile library, clock and reset                          ////
329
////                                                              ////
330
////  Description                                                 ////
331
////  Logic related to clock and reset                            ////
332
////                                                              ////
333
////                                                              ////
334
////  To Do:                                                      ////
335
////   - add more different registers                             ////
336
////                                                              ////
337
////  Author(s):                                                  ////
338
////      - Michael Unneback, unneback@opencores.org              ////
339
////        ORSoC AB                                              ////
340
////                                                              ////
341
//////////////////////////////////////////////////////////////////////
342
////                                                              ////
343
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
344
////                                                              ////
345
//// This source file may be used and distributed without         ////
346
//// restriction provided that this copyright statement is not    ////
347
//// removed from the file and that any derivative work contains  ////
348
//// the original copyright notice and the associated disclaimer. ////
349
////                                                              ////
350
//// This source file is free software; you can redistribute it   ////
351
//// and/or modify it under the terms of the GNU Lesser General   ////
352
//// Public License as published by the Free Software Foundation; ////
353
//// either version 2.1 of the License, or (at your option) any   ////
354
//// later version.                                               ////
355
////                                                              ////
356
//// This source is distributed in the hope that it will be       ////
357
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
358
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
359
//// PURPOSE.  See the GNU Lesser General Public License for more ////
360
//// details.                                                     ////
361
////                                                              ////
362
//// You should have received a copy of the GNU Lesser General    ////
363
//// Public License along with this source; if not, download it   ////
364
//// from http://www.opencores.org/lgpl.shtml                     ////
365
////                                                              ////
366
//////////////////////////////////////////////////////////////////////
367
 
368 48 unneback
`ifdef ACTEL
369
`ifdef GBUF
370
`timescale 1 ns/100 ps
371 6 unneback
// Global buffer
372
// usage:
373
// use to enable global buffers for high fan out signals such as clock and reset
374
// Version: 8.4 8.4.0.33
375
module gbuf(GL,CLK);
376
output GL;
377
input  CLK;
378
 
379
    wire GND;
380
 
381
    GND GND_1_net(.Y(GND));
382
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
383
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
384
 
385
endmodule
386
`timescale 1 ns/1 ns
387 40 unneback
`define MODULE gbuf
388
module `BASE`MODULE ( i, o);
389
`undef MODULE
390 6 unneback
input i;
391
output o;
392
`ifdef SIM_GBUF
393
assign o=i;
394
`else
395
gbuf gbuf_i0 ( .CLK(i), .GL(o));
396
`endif
397
endmodule
398 40 unneback
`endif
399 33 unneback
 
400 6 unneback
`else
401 33 unneback
 
402 40 unneback
`ifdef ALTERA
403
`ifdef GBUF
404 21 unneback
//altera
405 40 unneback
`define MODULE gbuf
406
module `BASE`MODULE ( i, o);
407
`undef MODULE
408 33 unneback
input i;
409
output o;
410
assign o = i;
411
endmodule
412 40 unneback
`endif
413 33 unneback
 
414 6 unneback
`else
415
 
416 40 unneback
`ifdef GBUF
417 6 unneback
`timescale 1 ns/100 ps
418 40 unneback
`define MODULE
419
module `BASE`MODULE ( i, o);
420
`undef MODULE
421 6 unneback
input i;
422
output o;
423
assign o = i;
424
endmodule
425 40 unneback
`endif
426 6 unneback
`endif // ALTERA
427
`endif //ACTEL
428
 
429 40 unneback
`ifdef SYNC_RST
430 6 unneback
// sync reset
431 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
432 6 unneback
// output active high global reset sync with two DFFs 
433
`timescale 1 ns/100 ps
434 40 unneback
`define MODULE sync_rst
435
module `BASE`MODULE ( rst_n_i, rst_o, clk);
436
`undef MODULE
437 6 unneback
input rst_n_i, clk;
438
output rst_o;
439 18 unneback
reg [1:0] tmp;
440 6 unneback
always @ (posedge clk or negedge rst_n_i)
441
if (!rst_n_i)
442 17 unneback
        tmp <= 2'b11;
443 6 unneback
else
444 33 unneback
        tmp <= {1'b0,tmp[1]};
445 40 unneback
`define MODULE gbuf
446
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
447
`undef MODULE
448 6 unneback
endmodule
449 40 unneback
`endif
450 6 unneback
 
451 40 unneback
`ifdef PLL
452 6 unneback
// vl_pll
453
`ifdef ACTEL
454 32 unneback
///////////////////////////////////////////////////////////////////////////////
455 17 unneback
`timescale 1 ps/1 ps
456 40 unneback
`define MODULE pll
457
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
458
`undef MODULE
459 6 unneback
parameter index = 0;
460
parameter number_of_clk = 1;
461 17 unneback
parameter period_time_0 = 20000;
462
parameter period_time_1 = 20000;
463
parameter period_time_2 = 20000;
464
parameter lock_delay = 2000000;
465 6 unneback
input clk_i, rst_n_i;
466
output lock;
467
output reg [0:number_of_clk-1] clk_o;
468
output [0:number_of_clk-1] rst_o;
469
 
470
`ifdef SIM_PLL
471
 
472
always
473
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
474
 
475
generate if (number_of_clk > 1)
476
always
477
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
478
endgenerate
479
 
480
generate if (number_of_clk > 2)
481
always
482
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
483
endgenerate
484
 
485
genvar i;
486
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
487
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
488
end
489
endgenerate
490
 
491
assign #lock_delay lock = rst_n_i;
492
 
493
endmodule
494
`else
495
generate if (number_of_clk==1 & index==0) begin
496
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
497
end
498
endgenerate // index==0
499
generate if (number_of_clk==1 & index==1) begin
500
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
501
end
502
endgenerate // index==1
503
generate if (number_of_clk==1 & index==2) begin
504
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
505
end
506
endgenerate // index==2
507
generate if (number_of_clk==1 & index==3) begin
508
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
509
end
510
endgenerate // index==0
511
 
512
generate if (number_of_clk==2 & index==0) begin
513
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
514
end
515
endgenerate // index==0
516
generate if (number_of_clk==2 & index==1) begin
517
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
518
end
519
endgenerate // index==1
520
generate if (number_of_clk==2 & index==2) begin
521
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
522
end
523
endgenerate // index==2
524
generate if (number_of_clk==2 & index==3) begin
525
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
526
end
527
endgenerate // index==0
528
 
529
generate if (number_of_clk==3 & index==0) begin
530
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
531
end
532
endgenerate // index==0
533
generate if (number_of_clk==3 & index==1) begin
534
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
535
end
536
endgenerate // index==1
537
generate if (number_of_clk==3 & index==2) begin
538
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
539
end
540
endgenerate // index==2
541
generate if (number_of_clk==3 & index==3) begin
542
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
543
end
544
endgenerate // index==0
545
 
546
genvar i;
547
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
548 40 unneback
`define MODULE sync_rst
549
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
550
`undef MODULE
551 6 unneback
end
552
endgenerate
553
endmodule
554
`endif
555 32 unneback
///////////////////////////////////////////////////////////////////////////////
556 6 unneback
 
557
`else
558
 
559 32 unneback
///////////////////////////////////////////////////////////////////////////////
560 6 unneback
`ifdef ALTERA
561
 
562 32 unneback
`timescale 1 ps/1 ps
563 40 unneback
`define MODULE pll
564
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
565
`undef MODULE
566 32 unneback
parameter index = 0;
567
parameter number_of_clk = 1;
568
parameter period_time_0 = 20000;
569
parameter period_time_1 = 20000;
570
parameter period_time_2 = 20000;
571
parameter period_time_3 = 20000;
572
parameter period_time_4 = 20000;
573
parameter lock_delay = 2000000;
574
input clk_i, rst_n_i;
575
output lock;
576
output reg [0:number_of_clk-1] clk_o;
577
output [0:number_of_clk-1] rst_o;
578
 
579
`ifdef SIM_PLL
580
 
581
always
582
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
583
 
584
generate if (number_of_clk > 1)
585
always
586
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
587
endgenerate
588
 
589
generate if (number_of_clk > 2)
590
always
591
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
592
endgenerate
593
 
594 33 unneback
generate if (number_of_clk > 3)
595 32 unneback
always
596
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
597
endgenerate
598
 
599 33 unneback
generate if (number_of_clk > 4)
600 32 unneback
always
601
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
602
endgenerate
603
 
604
genvar i;
605
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
606
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
607
end
608
endgenerate
609
 
610 33 unneback
//assign #lock_delay lock = rst_n_i;
611
assign lock = rst_n_i;
612 32 unneback
 
613
endmodule
614 6 unneback
`else
615
 
616 33 unneback
`ifdef VL_PLL0
617
`ifdef VL_PLL0_CLK1
618
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
619
`endif
620
`ifdef VL_PLL0_CLK2
621
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
622
`endif
623
`ifdef VL_PLL0_CLK3
624
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
625
`endif
626
`ifdef VL_PLL0_CLK4
627
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
628
`endif
629
`ifdef VL_PLL0_CLK5
630
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
631
`endif
632
`endif
633 32 unneback
 
634 33 unneback
`ifdef VL_PLL1
635
`ifdef VL_PLL1_CLK1
636
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
637
`endif
638
`ifdef VL_PLL1_CLK2
639
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
640
`endif
641
`ifdef VL_PLL1_CLK3
642
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
643
`endif
644
`ifdef VL_PLL1_CLK4
645
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
646
`endif
647
`ifdef VL_PLL1_CLK5
648
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
649
`endif
650
`endif
651 32 unneback
 
652 33 unneback
`ifdef VL_PLL2
653
`ifdef VL_PLL2_CLK1
654
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
655
`endif
656
`ifdef VL_PLL2_CLK2
657
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
658
`endif
659
`ifdef VL_PLL2_CLK3
660
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
661
`endif
662
`ifdef VL_PLL2_CLK4
663
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
664
`endif
665
`ifdef VL_PLL2_CLK5
666
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
667
`endif
668
`endif
669 32 unneback
 
670 33 unneback
`ifdef VL_PLL3
671
`ifdef VL_PLL3_CLK1
672
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
673
`endif
674
`ifdef VL_PLL3_CLK2
675
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
676
`endif
677
`ifdef VL_PLL3_CLK3
678
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
679
`endif
680
`ifdef VL_PLL3_CLK4
681
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
682
`endif
683
`ifdef VL_PLL3_CLK5
684
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
685
`endif
686
`endif
687 32 unneback
 
688
genvar i;
689
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
690 40 unneback
`define MODULE sync_rst
691
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
692
`undef MODULE
693 32 unneback
end
694
endgenerate
695
endmodule
696
`endif
697
///////////////////////////////////////////////////////////////////////////////
698
 
699
`else
700
 
701 6 unneback
// generic PLL
702 17 unneback
`timescale 1 ps/1 ps
703 40 unneback
`define MODULE pll
704
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
705
`undef MODULE
706 6 unneback
parameter index = 0;
707
parameter number_of_clk = 1;
708 17 unneback
parameter period_time_0 = 20000;
709
parameter period_time_1 = 20000;
710
parameter period_time_2 = 20000;
711 6 unneback
parameter lock_delay = 2000;
712
input clk_i, rst_n_i;
713
output lock;
714
output reg [0:number_of_clk-1] clk_o;
715
output [0:number_of_clk-1] rst_o;
716
 
717
always
718
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
719
 
720
generate if (number_of_clk > 1)
721
always
722
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
723
endgenerate
724
 
725
generate if (number_of_clk > 2)
726
always
727
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
728
endgenerate
729
 
730
genvar i;
731
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
732 40 unneback
`define MODULE sync_rst
733
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
734
`undef MODULE
735 6 unneback
end
736
endgenerate
737
 
738
assign #lock_delay lock = rst_n_i;
739
 
740
endmodule
741
 
742
`endif //altera
743 17 unneback
`endif //actel
744 40 unneback
`undef MODULE
745
`endif//////////////////////////////////////////////////////////////////////
746 6 unneback
////                                                              ////
747
////  Versatile library, registers                                ////
748
////                                                              ////
749
////  Description                                                 ////
750
////  Different type of registers                                 ////
751
////                                                              ////
752
////                                                              ////
753
////  To Do:                                                      ////
754
////   - add more different registers                             ////
755
////                                                              ////
756
////  Author(s):                                                  ////
757
////      - Michael Unneback, unneback@opencores.org              ////
758
////        ORSoC AB                                              ////
759
////                                                              ////
760
//////////////////////////////////////////////////////////////////////
761
////                                                              ////
762
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
763
////                                                              ////
764
//// This source file may be used and distributed without         ////
765
//// restriction provided that this copyright statement is not    ////
766
//// removed from the file and that any derivative work contains  ////
767
//// the original copyright notice and the associated disclaimer. ////
768
////                                                              ////
769
//// This source file is free software; you can redistribute it   ////
770
//// and/or modify it under the terms of the GNU Lesser General   ////
771
//// Public License as published by the Free Software Foundation; ////
772
//// either version 2.1 of the License, or (at your option) any   ////
773
//// later version.                                               ////
774
////                                                              ////
775
//// This source is distributed in the hope that it will be       ////
776
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
777
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
778
//// PURPOSE.  See the GNU Lesser General Public License for more ////
779
//// details.                                                     ////
780
////                                                              ////
781
//// You should have received a copy of the GNU Lesser General    ////
782
//// Public License along with this source; if not, download it   ////
783
//// from http://www.opencores.org/lgpl.shtml                     ////
784
////                                                              ////
785
//////////////////////////////////////////////////////////////////////
786
 
787 40 unneback
`ifdef DFF
788
`define MODULE dff
789
module `BASE`MODULE ( d, q, clk, rst);
790
`undef MODULE
791 6 unneback
        parameter width = 1;
792
        parameter reset_value = 0;
793
 
794
        input [width-1:0] d;
795
        input clk, rst;
796
        output reg [width-1:0] q;
797
 
798
        always @ (posedge clk or posedge rst)
799
        if (rst)
800
                q <= reset_value;
801
        else
802
                q <= d;
803
 
804
endmodule
805 40 unneback
`endif
806 6 unneback
 
807 40 unneback
`ifdef DFF_ARRAY
808
`define MODULE dff_array
809
module `BASE`MODULE ( d, q, clk, rst);
810
`undef MODULE
811 6 unneback
 
812
        parameter width = 1;
813
        parameter depth = 2;
814
        parameter reset_value = 1'b0;
815
 
816
        input [width-1:0] d;
817
        input clk, rst;
818
        output [width-1:0] q;
819
        reg  [0:depth-1] q_tmp [width-1:0];
820
        integer i;
821
        always @ (posedge clk or posedge rst)
822
        if (rst) begin
823
            for (i=0;i<depth;i=i+1)
824
                q_tmp[i] <= {width{reset_value}};
825
        end else begin
826
            q_tmp[0] <= d;
827
            for (i=1;i<depth;i=i+1)
828
                q_tmp[i] <= q_tmp[i-1];
829
        end
830
 
831
    assign q = q_tmp[depth-1];
832
 
833
endmodule
834 40 unneback
`endif
835 6 unneback
 
836 40 unneback
`ifdef DFF_CE
837
`define MODULE dff_ce
838
module `BASE`MODULE ( d, ce, q, clk, rst);
839
`undef MODULE
840 6 unneback
 
841
        parameter width = 1;
842
        parameter reset_value = 0;
843
 
844
        input [width-1:0] d;
845
        input ce, clk, rst;
846
        output reg [width-1:0] q;
847
 
848
        always @ (posedge clk or posedge rst)
849
        if (rst)
850
                q <= reset_value;
851
        else
852
                if (ce)
853
                        q <= d;
854
 
855
endmodule
856 40 unneback
`endif
857 6 unneback
 
858 40 unneback
`ifdef DFF_CE_CLEAR
859
`define MODULE dff_ce_clear
860
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
861
`undef MODULE
862 8 unneback
 
863
        parameter width = 1;
864
        parameter reset_value = 0;
865
 
866
        input [width-1:0] d;
867 10 unneback
        input ce, clear, clk, rst;
868 8 unneback
        output reg [width-1:0] q;
869
 
870
        always @ (posedge clk or posedge rst)
871
        if (rst)
872
            q <= reset_value;
873
        else
874
            if (ce)
875
                if (clear)
876
                    q <= {width{1'b0}};
877
                else
878
                    q <= d;
879
 
880
endmodule
881 40 unneback
`endif
882 8 unneback
 
883 40 unneback
`ifdef DF_CE_SET
884
`define MODULE dff_ce_set
885
module `BASE`MODULE ( d, ce, set, q, clk, rst);
886
`undef MODULE
887 24 unneback
 
888
        parameter width = 1;
889
        parameter reset_value = 0;
890
 
891
        input [width-1:0] d;
892
        input ce, set, clk, rst;
893
        output reg [width-1:0] q;
894
 
895
        always @ (posedge clk or posedge rst)
896
        if (rst)
897
            q <= reset_value;
898
        else
899
            if (ce)
900
                if (set)
901
                    q <= {width{1'b1}};
902
                else
903
                    q <= d;
904
 
905
endmodule
906 40 unneback
`endif
907 24 unneback
 
908 40 unneback
`ifdef SPR
909
`define MODULE spr
910
module `BASE`MODULE ( sp, r, q, clk, rst);
911
`undef MODULE
912
 
913 64 unneback
        //parameter width = 1;
914
        parameter reset_value = 1'b0;
915 29 unneback
 
916
        input sp, r;
917
        output reg q;
918
        input clk, rst;
919
 
920
        always @ (posedge clk or posedge rst)
921
        if (rst)
922
            q <= reset_value;
923
        else
924
            if (sp)
925
                q <= 1'b1;
926
            else if (r)
927
                q <= 1'b0;
928
 
929
endmodule
930 40 unneback
`endif
931 29 unneback
 
932 40 unneback
`ifdef SRP
933
`define MODULE srp
934
module `BASE`MODULE ( s, rp, q, clk, rst);
935
`undef MODULE
936
 
937 29 unneback
        parameter width = 1;
938
        parameter reset_value = 0;
939
 
940
        input s, rp;
941
        output reg q;
942
        input clk, rst;
943
 
944
        always @ (posedge clk or posedge rst)
945
        if (rst)
946
            q <= reset_value;
947
        else
948
            if (rp)
949
                q <= 1'b0;
950
            else if (s)
951
                q <= 1'b1;
952
 
953
endmodule
954 40 unneback
`endif
955 29 unneback
 
956 40 unneback
`ifdef ALTERA
957 29 unneback
 
958 40 unneback
`ifdef DFF_SR
959 6 unneback
// megafunction wizard: %LPM_FF%
960
// GENERATION: STANDARD
961
// VERSION: WM1.0
962
// MODULE: lpm_ff 
963
 
964
// ============================================================
965
// File Name: dff_sr.v
966
// Megafunction Name(s):
967
//                      lpm_ff
968
//
969
// Simulation Library Files(s):
970
//                      lpm
971
// ============================================================
972
// ************************************************************
973
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
974
//
975
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
976
// ************************************************************
977
 
978
 
979
//Copyright (C) 1991-2010 Altera Corporation
980
//Your use of Altera Corporation's design tools, logic functions 
981
//and other software and tools, and its AMPP partner logic 
982
//functions, and any output files from any of the foregoing 
983
//(including device programming or simulation files), and any 
984
//associated documentation or information are expressly subject 
985
//to the terms and conditions of the Altera Program License 
986
//Subscription Agreement, Altera MegaCore Function License 
987
//Agreement, or other applicable license agreement, including, 
988
//without limitation, that your use is for the sole purpose of 
989
//programming logic devices manufactured by Altera and sold by 
990
//Altera or its authorized distributors.  Please refer to the 
991
//applicable agreement for further details.
992
 
993
 
994
// synopsys translate_off
995
`timescale 1 ps / 1 ps
996
// synopsys translate_on
997 40 unneback
`define MODULE dff_sr
998
module `BASE`MODULE (
999
`undef MODULE
1000
 
1001 6 unneback
        aclr,
1002
        aset,
1003
        clock,
1004
        data,
1005
        q);
1006
 
1007
        input     aclr;
1008
        input     aset;
1009
        input     clock;
1010
        input     data;
1011
        output    q;
1012
 
1013
        wire [0:0] sub_wire0;
1014
        wire [0:0] sub_wire1 = sub_wire0[0:0];
1015
        wire  q = sub_wire1;
1016
        wire  sub_wire2 = data;
1017
        wire  sub_wire3 = sub_wire2;
1018
 
1019
        lpm_ff  lpm_ff_component (
1020
                                .aclr (aclr),
1021
                                .clock (clock),
1022
                                .data (sub_wire3),
1023
                                .aset (aset),
1024
                                .q (sub_wire0)
1025
                                // synopsys translate_off
1026
                                ,
1027
                                .aload (),
1028
                                .enable (),
1029
                                .sclr (),
1030
                                .sload (),
1031
                                .sset ()
1032
                                // synopsys translate_on
1033
                                );
1034
        defparam
1035
                lpm_ff_component.lpm_fftype = "DFF",
1036
                lpm_ff_component.lpm_type = "LPM_FF",
1037
                lpm_ff_component.lpm_width = 1;
1038
 
1039
 
1040
endmodule
1041
 
1042
// ============================================================
1043
// CNX file retrieval info
1044
// ============================================================
1045
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1046
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1047
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1048
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1049
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1050
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1051
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1052
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1053
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1054
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1055
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1056
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1057
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1058
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1059
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1060
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1061
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1062
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1063
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1064
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1065
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1066
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1067
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1068
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1069
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1070
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1071
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1072
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1073
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1074
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1075
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1076
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1077
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1078
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1079
// Retrieval info: LIB_FILE: lpm
1080 40 unneback
`endif
1081 6 unneback
 
1082
`else
1083
 
1084 40 unneback
`ifdef DFF_SR
1085
`define MODULE dff_sr
1086
module `BASE`MODULE ( aclr, aset, clock, data, q);
1087
`undef MODULE
1088 6 unneback
 
1089
    input         aclr;
1090
    input         aset;
1091
    input         clock;
1092
    input         data;
1093
    output reg    q;
1094
 
1095
   always @ (posedge clock or posedge aclr or posedge aset)
1096
     if (aclr)
1097
       q <= 1'b0;
1098
     else if (aset)
1099
       q <= 1'b1;
1100
     else
1101
       q <= data;
1102
 
1103
endmodule
1104 40 unneback
`endif
1105 6 unneback
 
1106
`endif
1107
 
1108
// LATCH
1109
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1110
`ifdef ALTERA
1111 40 unneback
 
1112
`ifdef LATCH
1113
`define MODULE latch
1114
module `BASE`MODULE ( d, le, q, clk);
1115
`undef MODULE
1116 6 unneback
input d, le;
1117
output q;
1118
input clk;
1119
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1120
endmodule
1121 40 unneback
`endif
1122
 
1123 6 unneback
`else
1124 40 unneback
 
1125
`ifdef LATCH
1126
`define MODULE latch
1127
module `BASE`MODULE ( d, le, q, clk);
1128
`undef MODULE
1129 6 unneback
input d, le;
1130 48 unneback
input clk;
1131
always @ (le or d)
1132 60 unneback
if (le)
1133 48 unneback
    d <= q;
1134 6 unneback
endmodule
1135 15 unneback
`endif
1136
 
1137 40 unneback
`endif
1138
 
1139
`ifdef SHREG
1140
`define MODULE shreg
1141
module `BASE`MODULE ( d, q, clk, rst);
1142
`undef MODULE
1143
 
1144 17 unneback
parameter depth = 10;
1145
input d;
1146
output q;
1147
input clk, rst;
1148
 
1149
reg [1:depth] dffs;
1150
 
1151
always @ (posedge clk or posedge rst)
1152
if (rst)
1153
    dffs <= {depth{1'b0}};
1154
else
1155
    dffs <= {d,dffs[1:depth-1]};
1156
assign q = dffs[depth];
1157
endmodule
1158 40 unneback
`endif
1159 17 unneback
 
1160 40 unneback
`ifdef SHREG_CE
1161
`define MODULE shreg_ce
1162
module `BASE`MODULE ( d, ce, q, clk, rst);
1163
`undef MODULE
1164 17 unneback
parameter depth = 10;
1165
input d, ce;
1166
output q;
1167
input clk, rst;
1168
 
1169
reg [1:depth] dffs;
1170
 
1171
always @ (posedge clk or posedge rst)
1172
if (rst)
1173
    dffs <= {depth{1'b0}};
1174
else
1175
    if (ce)
1176
        dffs <= {d,dffs[1:depth-1]};
1177
assign q = dffs[depth];
1178
endmodule
1179 40 unneback
`endif
1180 17 unneback
 
1181 40 unneback
`ifdef DELAY
1182
`define MODULE delay
1183
module `BASE`MODULE ( d, q, clk, rst);
1184
`undef MODULE
1185 15 unneback
parameter depth = 10;
1186
input d;
1187
output q;
1188
input clk, rst;
1189
 
1190
reg [1:depth] dffs;
1191
 
1192
always @ (posedge clk or posedge rst)
1193
if (rst)
1194
    dffs <= {depth{1'b0}};
1195
else
1196
    dffs <= {d,dffs[1:depth-1]};
1197
assign q = dffs[depth];
1198 17 unneback
endmodule
1199 40 unneback
`endif
1200 17 unneback
 
1201 40 unneback
`ifdef DELAY_EMPTYFLAG
1202
`define MODULE delay_emptyflag
1203 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1204 40 unneback
`undef MODULE
1205 17 unneback
parameter depth = 10;
1206
input d;
1207
output q, emptyflag;
1208
input clk, rst;
1209
 
1210
reg [1:depth] dffs;
1211
 
1212
always @ (posedge clk or posedge rst)
1213
if (rst)
1214
    dffs <= {depth{1'b0}};
1215
else
1216
    dffs <= {d,dffs[1:depth-1]};
1217
assign q = dffs[depth];
1218
assign emptyflag = !(|dffs);
1219
endmodule
1220 40 unneback
`endif
1221 75 unneback
 
1222 94 unneback
`ifdef PULSE2TOGGLE
1223 98 unneback
`define MODULE pulse2toggle
1224
module `BASE`MODULE ( pl, q, clk, rst);
1225 75 unneback
`undef MODULE
1226 94 unneback
input pl;
1227 98 unneback
output reg q;
1228 94 unneback
input clk, rst;
1229
always @ (posedge clk or posedge rst)
1230 75 unneback
if (rst)
1231 94 unneback
    q <= 1'b0;
1232 75 unneback
else
1233 94 unneback
    q <= pl ^ q;
1234
endmodule
1235
`endif
1236 75 unneback
 
1237 94 unneback
`ifdef TOGGLE2PULSE
1238 98 unneback
`define MODULE toggle2pulse
1239 94 unneback
module `BASE`MODULE (d, pl, clk, rst);
1240 97 unneback
`undef MODULE
1241 94 unneback
input d;
1242
output pl;
1243
input clk, rst;
1244
reg dff;
1245
always @ (posedge clk or posedge rst)
1246
if (rst)
1247
    dff <= 1'b0;
1248 75 unneback
else
1249 94 unneback
    dff <= d;
1250 98 unneback
assign pl = d ^ dff;
1251 94 unneback
endmodule
1252
`endif
1253 75 unneback
 
1254 94 unneback
`ifdef SYNCHRONIZER
1255
`define MODULE synchronizer
1256
module `BASE`MODULE (d, q, clk, rst);
1257
`undef MODULE
1258
input d;
1259
output reg q;
1260 116 unneback
input clk, rst;
1261 94 unneback
reg dff;
1262
always @ (posedge clk or posedge rst)
1263
if (rst)
1264 100 unneback
    {q,dff} <= 2'b00;
1265 75 unneback
else
1266 100 unneback
    {q,dff} <= {dff,d};
1267 94 unneback
endmodule
1268
`endif
1269 75 unneback
 
1270 94 unneback
`ifdef CDC
1271
`define MODULE cdc
1272 97 unneback
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1273 94 unneback
`undef MODULE
1274
input start_pl;
1275
output take_it_pl;
1276
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1277
output got_it_pl;
1278
input clk_src, rst_src;
1279
input clk_dst, rst_dst;
1280
wire take_it_tg, take_it_tg_sync;
1281
wire got_it_tg, got_it_tg_sync;
1282
// src -> dst
1283
`define MODULE pulse2toggle
1284
`BASE`MODULE p2t0 (
1285
`undef MODULE
1286
    .pl(start_pl),
1287
    .q(take_it_tg),
1288
    .clk(clk_src),
1289
    .rst(rst_src));
1290 75 unneback
 
1291 94 unneback
`define MODULE synchronizer
1292
`BASE`MODULE sync0 (
1293
`undef MODULE
1294
    .d(take_it_tg),
1295
    .q(take_it_tg_sync),
1296
    .clk(clk_dst),
1297
    .rst(rst_dst));
1298
 
1299
`define MODULE toggle2pulse
1300
`BASE`MODULE t2p0 (
1301
`undef MODULE
1302 100 unneback
    .d(take_it_tg_sync),
1303 94 unneback
    .pl(take_it_pl),
1304
    .clk(clk_dst),
1305
    .rst(rst_dst));
1306
 
1307
// dst -> src
1308
`define MODULE pulse2toggle
1309 98 unneback
`BASE`MODULE p2t1 (
1310 94 unneback
`undef MODULE
1311
    .pl(take_it_grant_pl),
1312
    .q(got_it_tg),
1313
    .clk(clk_dst),
1314
    .rst(rst_dst));
1315
 
1316
`define MODULE synchronizer
1317
`BASE`MODULE sync1 (
1318
`undef MODULE
1319
    .d(got_it_tg),
1320
    .q(got_it_tg_sync),
1321
    .clk(clk_src),
1322
    .rst(rst_src));
1323
 
1324
`define MODULE toggle2pulse
1325
`BASE`MODULE t2p1 (
1326
`undef MODULE
1327 100 unneback
    .d(got_it_tg_sync),
1328 94 unneback
    .pl(got_it_pl),
1329
    .clk(clk_src),
1330
    .rst(rst_src));
1331
 
1332 75 unneback
endmodule
1333
`endif
1334 17 unneback
//////////////////////////////////////////////////////////////////////
1335 6 unneback
////                                                              ////
1336 18 unneback
////  Logic functions                                             ////
1337
////                                                              ////
1338
////  Description                                                 ////
1339
////  Logic functions such as multiplexers                        ////
1340
////                                                              ////
1341
////                                                              ////
1342
////  To Do:                                                      ////
1343
////   -                                                          ////
1344
////                                                              ////
1345
////  Author(s):                                                  ////
1346
////      - Michael Unneback, unneback@opencores.org              ////
1347
////        ORSoC AB                                              ////
1348
////                                                              ////
1349
//////////////////////////////////////////////////////////////////////
1350
////                                                              ////
1351
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1352
////                                                              ////
1353
//// This source file may be used and distributed without         ////
1354
//// restriction provided that this copyright statement is not    ////
1355
//// removed from the file and that any derivative work contains  ////
1356
//// the original copyright notice and the associated disclaimer. ////
1357
////                                                              ////
1358
//// This source file is free software; you can redistribute it   ////
1359
//// and/or modify it under the terms of the GNU Lesser General   ////
1360
//// Public License as published by the Free Software Foundation; ////
1361
//// either version 2.1 of the License, or (at your option) any   ////
1362
//// later version.                                               ////
1363
////                                                              ////
1364
//// This source is distributed in the hope that it will be       ////
1365
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1366
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1367
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1368
//// details.                                                     ////
1369
////                                                              ////
1370
//// You should have received a copy of the GNU Lesser General    ////
1371
//// Public License along with this source; if not, download it   ////
1372
//// from http://www.opencores.org/lgpl.shtml                     ////
1373
////                                                              ////
1374
//////////////////////////////////////////////////////////////////////
1375 40 unneback
`ifdef MUX_ANDOR
1376
`define MODULE mux_andor
1377
module `BASE`MODULE ( a, sel, dout);
1378
`undef MODULE
1379 36 unneback
 
1380
parameter width = 32;
1381
parameter nr_of_ports = 4;
1382
 
1383
input [nr_of_ports*width-1:0] a;
1384
input [nr_of_ports-1:0] sel;
1385
output reg [width-1:0] dout;
1386
 
1387 38 unneback
integer i,j;
1388
 
1389 36 unneback
always @ (a, sel)
1390
begin
1391
    dout = a[width-1:0] & {width{sel[0]}};
1392 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1393
        for (j=0;j<width;j=j+1)
1394
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1395 36 unneback
end
1396
 
1397
endmodule
1398 40 unneback
`endif
1399 36 unneback
 
1400 40 unneback
`ifdef MUX2_ANDOR
1401
`define MODULE mux2_andor
1402
module `BASE`MODULE ( a1, a0, sel, dout);
1403
`undef MODULE
1404 18 unneback
 
1405 34 unneback
parameter width = 32;
1406 35 unneback
localparam nr_of_ports = 2;
1407 34 unneback
input [width-1:0] a1, a0;
1408
input [nr_of_ports-1:0] sel;
1409
output [width-1:0] dout;
1410
 
1411 40 unneback
`define MODULE mux_andor
1412
`BASE`MODULE
1413 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1414 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1415 40 unneback
`undef MODULE
1416
 
1417 34 unneback
endmodule
1418 40 unneback
`endif
1419 34 unneback
 
1420 40 unneback
`ifdef MUX3_ANDOR
1421
`define MODULE mux3_andor
1422
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1423
`undef MODULE
1424 34 unneback
 
1425
parameter width = 32;
1426 35 unneback
localparam nr_of_ports = 3;
1427 34 unneback
input [width-1:0] a2, a1, a0;
1428
input [nr_of_ports-1:0] sel;
1429
output [width-1:0] dout;
1430
 
1431 40 unneback
`define MODULE mux_andor
1432
`BASE`MODULE
1433 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1434 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1435 40 unneback
`undef MODULE
1436 34 unneback
endmodule
1437 40 unneback
`endif
1438 34 unneback
 
1439 40 unneback
`ifdef MUX4_ANDOR
1440
`define MODULE mux4_andor
1441
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1442
`undef MODULE
1443 18 unneback
 
1444
parameter width = 32;
1445 35 unneback
localparam nr_of_ports = 4;
1446 18 unneback
input [width-1:0] a3, a2, a1, a0;
1447
input [nr_of_ports-1:0] sel;
1448 22 unneback
output [width-1:0] dout;
1449 18 unneback
 
1450 40 unneback
`define MODULE mux_andor
1451
`BASE`MODULE
1452 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1453 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1454 40 unneback
`undef MODULE
1455 18 unneback
 
1456
endmodule
1457 40 unneback
`endif
1458 18 unneback
 
1459 40 unneback
`ifdef MUX5_ANDOR
1460
`define MODULE mux5_andor
1461
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1462
`undef MODULE
1463 18 unneback
 
1464
parameter width = 32;
1465 35 unneback
localparam nr_of_ports = 5;
1466 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1467
input [nr_of_ports-1:0] sel;
1468 22 unneback
output [width-1:0] dout;
1469 18 unneback
 
1470 40 unneback
`define MODULE mux_andor
1471
`BASE`MODULE
1472 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1473 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1474 40 unneback
`undef MODULE
1475 18 unneback
 
1476
endmodule
1477 40 unneback
`endif
1478 18 unneback
 
1479 40 unneback
`ifdef MUX6_ANDOR
1480
`define MODULE mux6_andor
1481
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1482
`undef MODULE
1483 18 unneback
 
1484
parameter width = 32;
1485 35 unneback
localparam nr_of_ports = 6;
1486 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1487
input [nr_of_ports-1:0] sel;
1488 22 unneback
output [width-1:0] dout;
1489 18 unneback
 
1490 40 unneback
`define MODULE mux_andor
1491
`BASE`MODULE
1492 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1493 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1494 40 unneback
`undef MODULE
1495 18 unneback
 
1496
endmodule
1497 40 unneback
`endif
1498 43 unneback
 
1499
`ifdef PARITY
1500
 
1501
`define MODULE parity_generate
1502
module `BASE`MODULE (data, parity);
1503
`undef MODULE
1504
parameter word_size = 32;
1505
parameter chunk_size = 8;
1506
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1507
input [word_size-1:0] data;
1508
output reg [word_size/chunk_size-1:0] parity;
1509
integer i,j;
1510
always @ (data)
1511
for (i=0;i<word_size/chunk_size;i=i+1) begin
1512
    parity[i] = parity_type;
1513
    for (j=0;j<chunk_size;j=j+1) begin
1514 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1515 43 unneback
    end
1516
end
1517
endmodule
1518
 
1519
`define MODULE parity_check
1520
module `BASE`MODULE( data, parity, parity_error);
1521
`undef MODULE
1522
parameter word_size = 32;
1523
parameter chunk_size = 8;
1524
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1525
input [word_size-1:0] data;
1526
input [word_size/chunk_size-1:0] parity;
1527
output parity_error;
1528 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1529 43 unneback
integer i,j;
1530
always @ (data or parity)
1531
for (i=0;i<word_size/chunk_size;i=i+1) begin
1532
    error_flag[i] = parity[i] ^ parity_type;
1533
    for (j=0;j<chunk_size;j=j+1) begin
1534 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1535 43 unneback
    end
1536
end
1537
assign parity_error = |error_flag;
1538
endmodule
1539
 
1540 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1541
////                                                              ////
1542
////  IO functions                                                ////
1543
////                                                              ////
1544
////  Description                                                 ////
1545
////  IO functions such as IOB flip-flops                         ////
1546
////                                                              ////
1547
////                                                              ////
1548
////  To Do:                                                      ////
1549
////   -                                                          ////
1550
////                                                              ////
1551
////  Author(s):                                                  ////
1552
////      - Michael Unneback, unneback@opencores.org              ////
1553
////        ORSoC AB                                              ////
1554
////                                                              ////
1555 18 unneback
//////////////////////////////////////////////////////////////////////
1556
////                                                              ////
1557 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1558
////                                                              ////
1559
//// This source file may be used and distributed without         ////
1560
//// restriction provided that this copyright statement is not    ////
1561
//// removed from the file and that any derivative work contains  ////
1562
//// the original copyright notice and the associated disclaimer. ////
1563
////                                                              ////
1564
//// This source file is free software; you can redistribute it   ////
1565
//// and/or modify it under the terms of the GNU Lesser General   ////
1566
//// Public License as published by the Free Software Foundation; ////
1567
//// either version 2.1 of the License, or (at your option) any   ////
1568
//// later version.                                               ////
1569
////                                                              ////
1570
//// This source is distributed in the hope that it will be       ////
1571
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1572
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1573
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1574
//// details.                                                     ////
1575
////                                                              ////
1576
//// You should have received a copy of the GNU Lesser General    ////
1577
//// Public License along with this source; if not, download it   ////
1578
//// from http://www.opencores.org/lgpl.shtml                     ////
1579
////                                                              ////
1580
//////////////////////////////////////////////////////////////////////
1581 45 unneback
`timescale 1ns/1ns
1582 44 unneback
`ifdef O_DFF
1583
`define MODULE o_dff
1584
module `BASE`MODULE (d_i, o_pad, clk, rst);
1585
`undef MODULE
1586
parameter width = 1;
1587 45 unneback
parameter reset_value = {width{1'b0}};
1588
input  [width-1:0]  d_i;
1589 44 unneback
output [width-1:0] o_pad;
1590
input clk, rst;
1591
wire [width-1:0] d_i_int `SYN_KEEP;
1592 45 unneback
reg  [width-1:0] o_pad_int;
1593 44 unneback
assign d_i_int = d_i;
1594
genvar i;
1595 45 unneback
generate
1596 44 unneback
for (i=0;i<width;i=i+1) begin
1597
    always @ (posedge clk or posedge rst)
1598
    if (rst)
1599 45 unneback
        o_pad_int[i] <= reset_value[i];
1600 44 unneback
    else
1601 45 unneback
        o_pad_int[i] <= d_i_int[i];
1602
    assign #1 o_pad[i] = o_pad_int[i];
1603 44 unneback
end
1604
endgenerate
1605
endmodule
1606
`endif
1607
 
1608 45 unneback
`timescale 1ns/1ns
1609 44 unneback
`ifdef IO_DFF_OE
1610
`define MODULE io_dff_oe
1611
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1612
`undef MODULE
1613
parameter width = 1;
1614
input  [width-1:0] d_o;
1615
output reg [width-1:0] d_i;
1616
input oe;
1617
inout [width-1:0] io_pad;
1618
input clk, rst;
1619
wire [width-1:0] oe_d `SYN_KEEP;
1620
reg [width-1:0] oe_q;
1621
reg [width-1:0] d_o_q;
1622
assign oe_d = {width{oe}};
1623
genvar i;
1624
generate
1625
for (i=0;i<width;i=i+1) begin
1626
    always @ (posedge clk or posedge rst)
1627
    if (rst)
1628
        oe_q[i] <= 1'b0;
1629
    else
1630
        oe_q[i] <= oe_d[i];
1631
    always @ (posedge clk or posedge rst)
1632
    if (rst)
1633
        d_o_q[i] <= 1'b0;
1634
    else
1635
        d_o_q[i] <= d_o[i];
1636
    always @ (posedge clk or posedge rst)
1637
    if (rst)
1638
        d_i[i] <= 1'b0;
1639
    else
1640
        d_i[i] <= io_pad[i];
1641 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1642 44 unneback
end
1643
endgenerate
1644
endmodule
1645
`endif
1646
`ifdef CNT_BIN
1647
//////////////////////////////////////////////////////////////////////
1648
////                                                              ////
1649 6 unneback
////  Versatile counter                                           ////
1650
////                                                              ////
1651
////  Description                                                 ////
1652
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1653
////  counter                                                     ////
1654
////                                                              ////
1655
////  To Do:                                                      ////
1656
////   - add LFSR with more taps                                  ////
1657
////                                                              ////
1658
////  Author(s):                                                  ////
1659
////      - Michael Unneback, unneback@opencores.org              ////
1660
////        ORSoC AB                                              ////
1661
////                                                              ////
1662
//////////////////////////////////////////////////////////////////////
1663
////                                                              ////
1664
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1665
////                                                              ////
1666
//// This source file may be used and distributed without         ////
1667
//// restriction provided that this copyright statement is not    ////
1668
//// removed from the file and that any derivative work contains  ////
1669
//// the original copyright notice and the associated disclaimer. ////
1670
////                                                              ////
1671
//// This source file is free software; you can redistribute it   ////
1672
//// and/or modify it under the terms of the GNU Lesser General   ////
1673
//// Public License as published by the Free Software Foundation; ////
1674
//// either version 2.1 of the License, or (at your option) any   ////
1675
//// later version.                                               ////
1676
////                                                              ////
1677
//// This source is distributed in the hope that it will be       ////
1678
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1679
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1680
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1681
//// details.                                                     ////
1682
////                                                              ////
1683
//// You should have received a copy of the GNU Lesser General    ////
1684
//// Public License along with this source; if not, download it   ////
1685
//// from http://www.opencores.org/lgpl.shtml                     ////
1686
////                                                              ////
1687
//////////////////////////////////////////////////////////////////////
1688
 
1689
// binary counter
1690 22 unneback
 
1691 40 unneback
`define MODULE cnt_bin
1692
module `BASE`MODULE (
1693
`undef MODULE
1694
 q, rst, clk);
1695
 
1696 22 unneback
   parameter length = 4;
1697
   output [length:1] q;
1698
   input rst;
1699
   input clk;
1700
 
1701
   parameter clear_value = 0;
1702
   parameter set_value = 1;
1703
   parameter wrap_value = 0;
1704
   parameter level1_value = 15;
1705
 
1706
   reg  [length:1] qi;
1707
   wire [length:1] q_next;
1708
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1709
 
1710
   always @ (posedge clk or posedge rst)
1711
     if (rst)
1712
       qi <= {length{1'b0}};
1713
     else
1714
       qi <= q_next;
1715
 
1716
   assign q = qi;
1717
 
1718
endmodule
1719 40 unneback
`endif
1720
`ifdef CNT_BIN_CLEAR
1721 22 unneback
//////////////////////////////////////////////////////////////////////
1722
////                                                              ////
1723
////  Versatile counter                                           ////
1724
////                                                              ////
1725
////  Description                                                 ////
1726
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1727
////  counter                                                     ////
1728
////                                                              ////
1729
////  To Do:                                                      ////
1730
////   - add LFSR with more taps                                  ////
1731
////                                                              ////
1732
////  Author(s):                                                  ////
1733
////      - Michael Unneback, unneback@opencores.org              ////
1734
////        ORSoC AB                                              ////
1735
////                                                              ////
1736
//////////////////////////////////////////////////////////////////////
1737
////                                                              ////
1738
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1739
////                                                              ////
1740
//// This source file may be used and distributed without         ////
1741
//// restriction provided that this copyright statement is not    ////
1742
//// removed from the file and that any derivative work contains  ////
1743
//// the original copyright notice and the associated disclaimer. ////
1744
////                                                              ////
1745
//// This source file is free software; you can redistribute it   ////
1746
//// and/or modify it under the terms of the GNU Lesser General   ////
1747
//// Public License as published by the Free Software Foundation; ////
1748
//// either version 2.1 of the License, or (at your option) any   ////
1749
//// later version.                                               ////
1750
////                                                              ////
1751
//// This source is distributed in the hope that it will be       ////
1752
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1753
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1754
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1755
//// details.                                                     ////
1756
////                                                              ////
1757
//// You should have received a copy of the GNU Lesser General    ////
1758
//// Public License along with this source; if not, download it   ////
1759
//// from http://www.opencores.org/lgpl.shtml                     ////
1760
////                                                              ////
1761
//////////////////////////////////////////////////////////////////////
1762
 
1763
// binary counter
1764
 
1765 40 unneback
`define MODULE cnt_bin_clear
1766
module `BASE`MODULE (
1767
`undef MODULE
1768
 clear, q, rst, clk);
1769
 
1770 22 unneback
   parameter length = 4;
1771
   input clear;
1772
   output [length:1] q;
1773
   input rst;
1774
   input clk;
1775
 
1776
   parameter clear_value = 0;
1777
   parameter set_value = 1;
1778
   parameter wrap_value = 0;
1779
   parameter level1_value = 15;
1780
 
1781
   reg  [length:1] qi;
1782
   wire [length:1] q_next;
1783
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1784
 
1785
   always @ (posedge clk or posedge rst)
1786
     if (rst)
1787
       qi <= {length{1'b0}};
1788
     else
1789
       qi <= q_next;
1790
 
1791
   assign q = qi;
1792
 
1793
endmodule
1794 40 unneback
`endif
1795
`ifdef CNT_BIN_CE
1796 22 unneback
//////////////////////////////////////////////////////////////////////
1797
////                                                              ////
1798
////  Versatile counter                                           ////
1799
////                                                              ////
1800
////  Description                                                 ////
1801
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1802
////  counter                                                     ////
1803
////                                                              ////
1804
////  To Do:                                                      ////
1805
////   - add LFSR with more taps                                  ////
1806
////                                                              ////
1807
////  Author(s):                                                  ////
1808
////      - Michael Unneback, unneback@opencores.org              ////
1809
////        ORSoC AB                                              ////
1810
////                                                              ////
1811
//////////////////////////////////////////////////////////////////////
1812
////                                                              ////
1813
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1814
////                                                              ////
1815
//// This source file may be used and distributed without         ////
1816
//// restriction provided that this copyright statement is not    ////
1817
//// removed from the file and that any derivative work contains  ////
1818
//// the original copyright notice and the associated disclaimer. ////
1819
////                                                              ////
1820
//// This source file is free software; you can redistribute it   ////
1821
//// and/or modify it under the terms of the GNU Lesser General   ////
1822
//// Public License as published by the Free Software Foundation; ////
1823
//// either version 2.1 of the License, or (at your option) any   ////
1824
//// later version.                                               ////
1825
////                                                              ////
1826
//// This source is distributed in the hope that it will be       ////
1827
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1828
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1829
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1830
//// details.                                                     ////
1831
////                                                              ////
1832
//// You should have received a copy of the GNU Lesser General    ////
1833
//// Public License along with this source; if not, download it   ////
1834
//// from http://www.opencores.org/lgpl.shtml                     ////
1835
////                                                              ////
1836
//////////////////////////////////////////////////////////////////////
1837
 
1838
// binary counter
1839 6 unneback
 
1840 40 unneback
`define MODULE cnt_bin_ce
1841
module `BASE`MODULE (
1842
`undef MODULE
1843
 cke, q, rst, clk);
1844
 
1845 6 unneback
   parameter length = 4;
1846
   input cke;
1847
   output [length:1] q;
1848
   input rst;
1849
   input clk;
1850
 
1851
   parameter clear_value = 0;
1852
   parameter set_value = 1;
1853
   parameter wrap_value = 0;
1854
   parameter level1_value = 15;
1855
 
1856
   reg  [length:1] qi;
1857
   wire [length:1] q_next;
1858
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1859
 
1860
   always @ (posedge clk or posedge rst)
1861
     if (rst)
1862
       qi <= {length{1'b0}};
1863
     else
1864
     if (cke)
1865
       qi <= q_next;
1866
 
1867
   assign q = qi;
1868
 
1869
endmodule
1870 40 unneback
`endif
1871
`ifdef CNT_BIN_CE_CLEAR
1872 6 unneback
//////////////////////////////////////////////////////////////////////
1873
////                                                              ////
1874
////  Versatile counter                                           ////
1875
////                                                              ////
1876
////  Description                                                 ////
1877
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1878
////  counter                                                     ////
1879
////                                                              ////
1880
////  To Do:                                                      ////
1881
////   - add LFSR with more taps                                  ////
1882
////                                                              ////
1883
////  Author(s):                                                  ////
1884
////      - Michael Unneback, unneback@opencores.org              ////
1885
////        ORSoC AB                                              ////
1886
////                                                              ////
1887
//////////////////////////////////////////////////////////////////////
1888
////                                                              ////
1889
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1890
////                                                              ////
1891
//// This source file may be used and distributed without         ////
1892
//// restriction provided that this copyright statement is not    ////
1893
//// removed from the file and that any derivative work contains  ////
1894
//// the original copyright notice and the associated disclaimer. ////
1895
////                                                              ////
1896
//// This source file is free software; you can redistribute it   ////
1897
//// and/or modify it under the terms of the GNU Lesser General   ////
1898
//// Public License as published by the Free Software Foundation; ////
1899
//// either version 2.1 of the License, or (at your option) any   ////
1900
//// later version.                                               ////
1901
////                                                              ////
1902
//// This source is distributed in the hope that it will be       ////
1903
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1904
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1905
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1906
//// details.                                                     ////
1907
////                                                              ////
1908
//// You should have received a copy of the GNU Lesser General    ////
1909
//// Public License along with this source; if not, download it   ////
1910
//// from http://www.opencores.org/lgpl.shtml                     ////
1911
////                                                              ////
1912
//////////////////////////////////////////////////////////////////////
1913
 
1914
// binary counter
1915
 
1916 40 unneback
`define MODULE cnt_bin_ce_clear
1917
module `BASE`MODULE (
1918
`undef MODULE
1919
 clear, cke, q, rst, clk);
1920
 
1921 6 unneback
   parameter length = 4;
1922
   input clear;
1923
   input cke;
1924
   output [length:1] q;
1925
   input rst;
1926
   input clk;
1927
 
1928
   parameter clear_value = 0;
1929
   parameter set_value = 1;
1930
   parameter wrap_value = 0;
1931
   parameter level1_value = 15;
1932
 
1933
   reg  [length:1] qi;
1934
   wire [length:1] q_next;
1935
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1936
 
1937
   always @ (posedge clk or posedge rst)
1938
     if (rst)
1939
       qi <= {length{1'b0}};
1940
     else
1941
     if (cke)
1942
       qi <= q_next;
1943
 
1944
   assign q = qi;
1945
 
1946
endmodule
1947 40 unneback
`endif
1948
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1949 6 unneback
//////////////////////////////////////////////////////////////////////
1950
////                                                              ////
1951
////  Versatile counter                                           ////
1952
////                                                              ////
1953
////  Description                                                 ////
1954
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1955
////  counter                                                     ////
1956
////                                                              ////
1957
////  To Do:                                                      ////
1958
////   - add LFSR with more taps                                  ////
1959
////                                                              ////
1960
////  Author(s):                                                  ////
1961
////      - Michael Unneback, unneback@opencores.org              ////
1962
////        ORSoC AB                                              ////
1963
////                                                              ////
1964
//////////////////////////////////////////////////////////////////////
1965
////                                                              ////
1966
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1967
////                                                              ////
1968
//// This source file may be used and distributed without         ////
1969
//// restriction provided that this copyright statement is not    ////
1970
//// removed from the file and that any derivative work contains  ////
1971
//// the original copyright notice and the associated disclaimer. ////
1972
////                                                              ////
1973
//// This source file is free software; you can redistribute it   ////
1974
//// and/or modify it under the terms of the GNU Lesser General   ////
1975
//// Public License as published by the Free Software Foundation; ////
1976
//// either version 2.1 of the License, or (at your option) any   ////
1977
//// later version.                                               ////
1978
////                                                              ////
1979
//// This source is distributed in the hope that it will be       ////
1980
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1981
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1982
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1983
//// details.                                                     ////
1984
////                                                              ////
1985
//// You should have received a copy of the GNU Lesser General    ////
1986
//// Public License along with this source; if not, download it   ////
1987
//// from http://www.opencores.org/lgpl.shtml                     ////
1988
////                                                              ////
1989
//////////////////////////////////////////////////////////////////////
1990
 
1991
// binary counter
1992 29 unneback
 
1993 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1994
module `BASE`MODULE (
1995
`undef MODULE
1996
 clear, cke, q, level1, level2, rst, clk);
1997
 
1998 29 unneback
   parameter length = 4;
1999
   input clear;
2000
   input cke;
2001
   output [length:1] q;
2002
   output reg level1;
2003
   output reg level2;
2004
   input rst;
2005
   input clk;
2006
 
2007
   parameter clear_value = 0;
2008
   parameter set_value = 1;
2009 30 unneback
   parameter wrap_value = 15;
2010
   parameter level1_value = 8;
2011
   parameter level2_value = 15;
2012 29 unneback
 
2013
   wire rew;
2014 30 unneback
   assign rew = 1'b0;
2015 29 unneback
   reg  [length:1] qi;
2016
   wire [length:1] q_next;
2017
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2018
 
2019
   always @ (posedge clk or posedge rst)
2020
     if (rst)
2021
       qi <= {length{1'b0}};
2022
     else
2023
     if (cke)
2024
       qi <= q_next;
2025
 
2026
   assign q = qi;
2027
 
2028
 
2029
    always @ (posedge clk or posedge rst)
2030
    if (rst)
2031
        level1 <= 1'b0;
2032
    else
2033
    if (cke)
2034
    if (clear)
2035
        level1 <= 1'b0;
2036
    else if (q_next == level1_value)
2037
        level1 <= 1'b1;
2038
    else if (qi == level1_value & rew)
2039
        level1 <= 1'b0;
2040
 
2041
    always @ (posedge clk or posedge rst)
2042
    if (rst)
2043
        level2 <= 1'b0;
2044
    else
2045
    if (cke)
2046
    if (clear)
2047
        level2 <= 1'b0;
2048
    else if (q_next == level2_value)
2049
        level2 <= 1'b1;
2050
    else if (qi == level2_value & rew)
2051
        level2 <= 1'b0;
2052
endmodule
2053 40 unneback
`endif
2054
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2055 29 unneback
//////////////////////////////////////////////////////////////////////
2056
////                                                              ////
2057
////  Versatile counter                                           ////
2058
////                                                              ////
2059
////  Description                                                 ////
2060
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2061
////  counter                                                     ////
2062
////                                                              ////
2063
////  To Do:                                                      ////
2064
////   - add LFSR with more taps                                  ////
2065
////                                                              ////
2066
////  Author(s):                                                  ////
2067
////      - Michael Unneback, unneback@opencores.org              ////
2068
////        ORSoC AB                                              ////
2069
////                                                              ////
2070
//////////////////////////////////////////////////////////////////////
2071
////                                                              ////
2072
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2073
////                                                              ////
2074
//// This source file may be used and distributed without         ////
2075
//// restriction provided that this copyright statement is not    ////
2076
//// removed from the file and that any derivative work contains  ////
2077
//// the original copyright notice and the associated disclaimer. ////
2078
////                                                              ////
2079
//// This source file is free software; you can redistribute it   ////
2080
//// and/or modify it under the terms of the GNU Lesser General   ////
2081
//// Public License as published by the Free Software Foundation; ////
2082
//// either version 2.1 of the License, or (at your option) any   ////
2083
//// later version.                                               ////
2084
////                                                              ////
2085
//// This source is distributed in the hope that it will be       ////
2086
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2087
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2088
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2089
//// details.                                                     ////
2090
////                                                              ////
2091
//// You should have received a copy of the GNU Lesser General    ////
2092
//// Public License along with this source; if not, download it   ////
2093
//// from http://www.opencores.org/lgpl.shtml                     ////
2094
////                                                              ////
2095
//////////////////////////////////////////////////////////////////////
2096
 
2097
// binary counter
2098 6 unneback
 
2099 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2100
module `BASE`MODULE (
2101
`undef MODULE
2102
 clear, set, cke, rew, q, rst, clk);
2103
 
2104 6 unneback
   parameter length = 4;
2105
   input clear;
2106
   input set;
2107
   input cke;
2108
   input rew;
2109
   output [length:1] q;
2110
   input rst;
2111
   input clk;
2112
 
2113
   parameter clear_value = 0;
2114
   parameter set_value = 1;
2115
   parameter wrap_value = 0;
2116
   parameter level1_value = 15;
2117
 
2118
   reg  [length:1] qi;
2119
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2120
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2121
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2122
   assign q_next = rew ? q_next_rew : q_next_fw;
2123
 
2124
   always @ (posedge clk or posedge rst)
2125
     if (rst)
2126
       qi <= {length{1'b0}};
2127
     else
2128
     if (cke)
2129
       qi <= q_next;
2130
 
2131
   assign q = qi;
2132
 
2133
endmodule
2134 40 unneback
`endif
2135
`ifdef CNT_BIN_CE_REW_L1
2136 6 unneback
//////////////////////////////////////////////////////////////////////
2137
////                                                              ////
2138
////  Versatile counter                                           ////
2139
////                                                              ////
2140
////  Description                                                 ////
2141
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2142
////  counter                                                     ////
2143
////                                                              ////
2144
////  To Do:                                                      ////
2145
////   - add LFSR with more taps                                  ////
2146
////                                                              ////
2147
////  Author(s):                                                  ////
2148
////      - Michael Unneback, unneback@opencores.org              ////
2149
////        ORSoC AB                                              ////
2150
////                                                              ////
2151
//////////////////////////////////////////////////////////////////////
2152
////                                                              ////
2153
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2154
////                                                              ////
2155
//// This source file may be used and distributed without         ////
2156
//// restriction provided that this copyright statement is not    ////
2157
//// removed from the file and that any derivative work contains  ////
2158
//// the original copyright notice and the associated disclaimer. ////
2159
////                                                              ////
2160
//// This source file is free software; you can redistribute it   ////
2161
//// and/or modify it under the terms of the GNU Lesser General   ////
2162
//// Public License as published by the Free Software Foundation; ////
2163
//// either version 2.1 of the License, or (at your option) any   ////
2164
//// later version.                                               ////
2165
////                                                              ////
2166
//// This source is distributed in the hope that it will be       ////
2167
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2168
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2169
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2170
//// details.                                                     ////
2171
////                                                              ////
2172
//// You should have received a copy of the GNU Lesser General    ////
2173
//// Public License along with this source; if not, download it   ////
2174
//// from http://www.opencores.org/lgpl.shtml                     ////
2175
////                                                              ////
2176
//////////////////////////////////////////////////////////////////////
2177
 
2178
// binary counter
2179
 
2180 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2181
module `BASE`MODULE (
2182
`undef MODULE
2183
 cke, rew, level1, rst, clk);
2184
 
2185 6 unneback
   parameter length = 4;
2186
   input cke;
2187
   input rew;
2188
   output reg level1;
2189
   input rst;
2190
   input clk;
2191
 
2192
   parameter clear_value = 0;
2193
   parameter set_value = 1;
2194
   parameter wrap_value = 1;
2195
   parameter level1_value = 15;
2196
 
2197 29 unneback
   wire clear;
2198 30 unneback
   assign clear = 1'b0;
2199 6 unneback
   reg  [length:1] qi;
2200
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2201
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2202
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2203
   assign q_next = rew ? q_next_rew : q_next_fw;
2204
 
2205
   always @ (posedge clk or posedge rst)
2206
     if (rst)
2207
       qi <= {length{1'b0}};
2208
     else
2209
     if (cke)
2210
       qi <= q_next;
2211
 
2212
 
2213
 
2214
    always @ (posedge clk or posedge rst)
2215
    if (rst)
2216
        level1 <= 1'b0;
2217
    else
2218
    if (cke)
2219 29 unneback
    if (clear)
2220
        level1 <= 1'b0;
2221
    else if (q_next == level1_value)
2222 6 unneback
        level1 <= 1'b1;
2223
    else if (qi == level1_value & rew)
2224
        level1 <= 1'b0;
2225
endmodule
2226 40 unneback
`endif
2227
`ifdef CNT_BIN_CE_REW_ZQ_L1
2228 6 unneback
//////////////////////////////////////////////////////////////////////
2229
////                                                              ////
2230
////  Versatile counter                                           ////
2231
////                                                              ////
2232
////  Description                                                 ////
2233
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2234
////  counter                                                     ////
2235
////                                                              ////
2236
////  To Do:                                                      ////
2237
////   - add LFSR with more taps                                  ////
2238
////                                                              ////
2239
////  Author(s):                                                  ////
2240
////      - Michael Unneback, unneback@opencores.org              ////
2241
////        ORSoC AB                                              ////
2242
////                                                              ////
2243
//////////////////////////////////////////////////////////////////////
2244
////                                                              ////
2245
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2246
////                                                              ////
2247
//// This source file may be used and distributed without         ////
2248
//// restriction provided that this copyright statement is not    ////
2249
//// removed from the file and that any derivative work contains  ////
2250
//// the original copyright notice and the associated disclaimer. ////
2251
////                                                              ////
2252
//// This source file is free software; you can redistribute it   ////
2253
//// and/or modify it under the terms of the GNU Lesser General   ////
2254
//// Public License as published by the Free Software Foundation; ////
2255
//// either version 2.1 of the License, or (at your option) any   ////
2256
//// later version.                                               ////
2257
////                                                              ////
2258
//// This source is distributed in the hope that it will be       ////
2259
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2260
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2261
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2262
//// details.                                                     ////
2263
////                                                              ////
2264
//// You should have received a copy of the GNU Lesser General    ////
2265
//// Public License along with this source; if not, download it   ////
2266
//// from http://www.opencores.org/lgpl.shtml                     ////
2267
////                                                              ////
2268
//////////////////////////////////////////////////////////////////////
2269
 
2270 25 unneback
// binary counter
2271
 
2272 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2273
module `BASE`MODULE (
2274
`undef MODULE
2275
 cke, rew, zq, level1, rst, clk);
2276
 
2277 25 unneback
   parameter length = 4;
2278
   input cke;
2279
   input rew;
2280
   output reg zq;
2281
   output reg level1;
2282
   input rst;
2283
   input clk;
2284
 
2285
   parameter clear_value = 0;
2286
   parameter set_value = 1;
2287
   parameter wrap_value = 1;
2288
   parameter level1_value = 15;
2289
 
2290 29 unneback
   wire clear;
2291 30 unneback
   assign clear = 1'b0;
2292 25 unneback
   reg  [length:1] qi;
2293
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2294
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2295
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2296
   assign q_next = rew ? q_next_rew : q_next_fw;
2297
 
2298
   always @ (posedge clk or posedge rst)
2299
     if (rst)
2300
       qi <= {length{1'b0}};
2301
     else
2302
     if (cke)
2303
       qi <= q_next;
2304
 
2305
 
2306
 
2307
   always @ (posedge clk or posedge rst)
2308
     if (rst)
2309
       zq <= 1'b1;
2310
     else
2311
     if (cke)
2312
       zq <= q_next == {length{1'b0}};
2313
 
2314
    always @ (posedge clk or posedge rst)
2315
    if (rst)
2316
        level1 <= 1'b0;
2317
    else
2318
    if (cke)
2319 29 unneback
    if (clear)
2320
        level1 <= 1'b0;
2321
    else if (q_next == level1_value)
2322 25 unneback
        level1 <= 1'b1;
2323
    else if (qi == level1_value & rew)
2324
        level1 <= 1'b0;
2325
endmodule
2326 40 unneback
`endif
2327
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2328 25 unneback
//////////////////////////////////////////////////////////////////////
2329
////                                                              ////
2330
////  Versatile counter                                           ////
2331
////                                                              ////
2332
////  Description                                                 ////
2333
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2334
////  counter                                                     ////
2335
////                                                              ////
2336
////  To Do:                                                      ////
2337
////   - add LFSR with more taps                                  ////
2338
////                                                              ////
2339
////  Author(s):                                                  ////
2340
////      - Michael Unneback, unneback@opencores.org              ////
2341
////        ORSoC AB                                              ////
2342
////                                                              ////
2343
//////////////////////////////////////////////////////////////////////
2344
////                                                              ////
2345
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2346
////                                                              ////
2347
//// This source file may be used and distributed without         ////
2348
//// restriction provided that this copyright statement is not    ////
2349
//// removed from the file and that any derivative work contains  ////
2350
//// the original copyright notice and the associated disclaimer. ////
2351
////                                                              ////
2352
//// This source file is free software; you can redistribute it   ////
2353
//// and/or modify it under the terms of the GNU Lesser General   ////
2354
//// Public License as published by the Free Software Foundation; ////
2355
//// either version 2.1 of the License, or (at your option) any   ////
2356
//// later version.                                               ////
2357
////                                                              ////
2358
//// This source is distributed in the hope that it will be       ////
2359
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2360
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2361
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2362
//// details.                                                     ////
2363
////                                                              ////
2364
//// You should have received a copy of the GNU Lesser General    ////
2365
//// Public License along with this source; if not, download it   ////
2366
//// from http://www.opencores.org/lgpl.shtml                     ////
2367
////                                                              ////
2368
//////////////////////////////////////////////////////////////////////
2369
 
2370
// binary counter
2371
 
2372 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2373
module `BASE`MODULE (
2374
`undef MODULE
2375
 cke, rew, q, zq, level1, rst, clk);
2376
 
2377 25 unneback
   parameter length = 4;
2378
   input cke;
2379
   input rew;
2380
   output [length:1] q;
2381
   output reg zq;
2382
   output reg level1;
2383
   input rst;
2384
   input clk;
2385
 
2386
   parameter clear_value = 0;
2387
   parameter set_value = 1;
2388
   parameter wrap_value = 1;
2389
   parameter level1_value = 15;
2390
 
2391 29 unneback
   wire clear;
2392 30 unneback
   assign clear = 1'b0;
2393 25 unneback
   reg  [length:1] qi;
2394
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2395
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2396
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2397
   assign q_next = rew ? q_next_rew : q_next_fw;
2398
 
2399
   always @ (posedge clk or posedge rst)
2400
     if (rst)
2401
       qi <= {length{1'b0}};
2402
     else
2403
     if (cke)
2404
       qi <= q_next;
2405
 
2406
   assign q = qi;
2407
 
2408
 
2409
   always @ (posedge clk or posedge rst)
2410
     if (rst)
2411
       zq <= 1'b1;
2412
     else
2413
     if (cke)
2414
       zq <= q_next == {length{1'b0}};
2415
 
2416
    always @ (posedge clk or posedge rst)
2417
    if (rst)
2418
        level1 <= 1'b0;
2419
    else
2420
    if (cke)
2421 29 unneback
    if (clear)
2422
        level1 <= 1'b0;
2423
    else if (q_next == level1_value)
2424 25 unneback
        level1 <= 1'b1;
2425
    else if (qi == level1_value & rew)
2426
        level1 <= 1'b0;
2427
endmodule
2428 40 unneback
`endif
2429
`ifdef CNT_LFSR_ZQ
2430 25 unneback
//////////////////////////////////////////////////////////////////////
2431
////                                                              ////
2432
////  Versatile counter                                           ////
2433
////                                                              ////
2434
////  Description                                                 ////
2435
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2436
////  counter                                                     ////
2437
////                                                              ////
2438
////  To Do:                                                      ////
2439
////   - add LFSR with more taps                                  ////
2440
////                                                              ////
2441
////  Author(s):                                                  ////
2442
////      - Michael Unneback, unneback@opencores.org              ////
2443
////        ORSoC AB                                              ////
2444
////                                                              ////
2445
//////////////////////////////////////////////////////////////////////
2446
////                                                              ////
2447
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2448
////                                                              ////
2449
//// This source file may be used and distributed without         ////
2450
//// restriction provided that this copyright statement is not    ////
2451
//// removed from the file and that any derivative work contains  ////
2452
//// the original copyright notice and the associated disclaimer. ////
2453
////                                                              ////
2454
//// This source file is free software; you can redistribute it   ////
2455
//// and/or modify it under the terms of the GNU Lesser General   ////
2456
//// Public License as published by the Free Software Foundation; ////
2457
//// either version 2.1 of the License, or (at your option) any   ////
2458
//// later version.                                               ////
2459
////                                                              ////
2460
//// This source is distributed in the hope that it will be       ////
2461
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2462
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2463
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2464
//// details.                                                     ////
2465
////                                                              ////
2466
//// You should have received a copy of the GNU Lesser General    ////
2467
//// Public License along with this source; if not, download it   ////
2468
//// from http://www.opencores.org/lgpl.shtml                     ////
2469
////                                                              ////
2470
//////////////////////////////////////////////////////////////////////
2471
 
2472 6 unneback
// LFSR counter
2473
 
2474 40 unneback
`define MODULE cnt_lfsr_zq
2475
module `BASE`MODULE (
2476
`undef MODULE
2477
 zq, rst, clk);
2478
 
2479 6 unneback
   parameter length = 4;
2480
   output reg zq;
2481
   input rst;
2482
   input clk;
2483
 
2484
   parameter clear_value = 0;
2485
   parameter set_value = 1;
2486
   parameter wrap_value = 8;
2487
   parameter level1_value = 15;
2488
 
2489
   reg  [length:1] qi;
2490
   reg lfsr_fb;
2491
   wire [length:1] q_next;
2492
   reg [32:1] polynom;
2493
   integer i;
2494
 
2495
   always @ (qi)
2496
   begin
2497
        case (length)
2498
         2: polynom = 32'b11;                               // 0x3
2499
         3: polynom = 32'b110;                              // 0x6
2500
         4: polynom = 32'b1100;                             // 0xC
2501
         5: polynom = 32'b10100;                            // 0x14
2502
         6: polynom = 32'b110000;                           // 0x30
2503
         7: polynom = 32'b1100000;                          // 0x60
2504
         8: polynom = 32'b10111000;                         // 0xb8
2505
         9: polynom = 32'b100010000;                        // 0x110
2506
        10: polynom = 32'b1001000000;                       // 0x240
2507
        11: polynom = 32'b10100000000;                      // 0x500
2508
        12: polynom = 32'b100000101001;                     // 0x829
2509
        13: polynom = 32'b1000000001100;                    // 0x100C
2510
        14: polynom = 32'b10000000010101;                   // 0x2015
2511
        15: polynom = 32'b110000000000000;                  // 0x6000
2512
        16: polynom = 32'b1101000000001000;                 // 0xD008
2513
        17: polynom = 32'b10010000000000000;                // 0x12000
2514
        18: polynom = 32'b100000010000000000;               // 0x20400
2515
        19: polynom = 32'b1000000000000100011;              // 0x40023
2516 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2517 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2518
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2519
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2520
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2521
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2522
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2523
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2524
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2525
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2526
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2527
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2528
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2529
        default: polynom = 32'b0;
2530
        endcase
2531
        lfsr_fb = qi[length];
2532
        for (i=length-1; i>=1; i=i-1) begin
2533
            if (polynom[i])
2534
                lfsr_fb = lfsr_fb  ~^ qi[i];
2535
        end
2536
    end
2537
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2538
 
2539
   always @ (posedge clk or posedge rst)
2540
     if (rst)
2541
       qi <= {length{1'b0}};
2542
     else
2543
       qi <= q_next;
2544
 
2545
 
2546
 
2547
   always @ (posedge clk or posedge rst)
2548
     if (rst)
2549
       zq <= 1'b1;
2550
     else
2551
       zq <= q_next == {length{1'b0}};
2552
endmodule
2553 40 unneback
`endif
2554 75 unneback
`ifdef CNT_LFSR_CE
2555
//////////////////////////////////////////////////////////////////////
2556
////                                                              ////
2557
////  Versatile counter                                           ////
2558
////                                                              ////
2559
////  Description                                                 ////
2560
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2561
////  counter                                                     ////
2562
////                                                              ////
2563
////  To Do:                                                      ////
2564
////   - add LFSR with more taps                                  ////
2565
////                                                              ////
2566
////  Author(s):                                                  ////
2567
////      - Michael Unneback, unneback@opencores.org              ////
2568
////        ORSoC AB                                              ////
2569
////                                                              ////
2570
//////////////////////////////////////////////////////////////////////
2571
////                                                              ////
2572
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2573
////                                                              ////
2574
//// This source file may be used and distributed without         ////
2575
//// restriction provided that this copyright statement is not    ////
2576
//// removed from the file and that any derivative work contains  ////
2577
//// the original copyright notice and the associated disclaimer. ////
2578
////                                                              ////
2579
//// This source file is free software; you can redistribute it   ////
2580
//// and/or modify it under the terms of the GNU Lesser General   ////
2581
//// Public License as published by the Free Software Foundation; ////
2582
//// either version 2.1 of the License, or (at your option) any   ////
2583
//// later version.                                               ////
2584
////                                                              ////
2585
//// This source is distributed in the hope that it will be       ////
2586
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2587
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2588
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2589
//// details.                                                     ////
2590
////                                                              ////
2591
//// You should have received a copy of the GNU Lesser General    ////
2592
//// Public License along with this source; if not, download it   ////
2593
//// from http://www.opencores.org/lgpl.shtml                     ////
2594
////                                                              ////
2595
//////////////////////////////////////////////////////////////////////
2596
 
2597
// LFSR counter
2598
 
2599
`define MODULE cnt_lfsr_ce
2600
module `BASE`MODULE (
2601
`undef MODULE
2602
 cke, zq, rst, clk);
2603
 
2604
   parameter length = 4;
2605
   input cke;
2606
   output reg zq;
2607
   input rst;
2608
   input clk;
2609
 
2610
   parameter clear_value = 0;
2611
   parameter set_value = 1;
2612
   parameter wrap_value = 0;
2613
   parameter level1_value = 15;
2614
 
2615
   reg  [length:1] qi;
2616
   reg lfsr_fb;
2617
   wire [length:1] q_next;
2618
   reg [32:1] polynom;
2619
   integer i;
2620
 
2621
   always @ (qi)
2622
   begin
2623
        case (length)
2624
         2: polynom = 32'b11;                               // 0x3
2625
         3: polynom = 32'b110;                              // 0x6
2626
         4: polynom = 32'b1100;                             // 0xC
2627
         5: polynom = 32'b10100;                            // 0x14
2628
         6: polynom = 32'b110000;                           // 0x30
2629
         7: polynom = 32'b1100000;                          // 0x60
2630
         8: polynom = 32'b10111000;                         // 0xb8
2631
         9: polynom = 32'b100010000;                        // 0x110
2632
        10: polynom = 32'b1001000000;                       // 0x240
2633
        11: polynom = 32'b10100000000;                      // 0x500
2634
        12: polynom = 32'b100000101001;                     // 0x829
2635
        13: polynom = 32'b1000000001100;                    // 0x100C
2636
        14: polynom = 32'b10000000010101;                   // 0x2015
2637
        15: polynom = 32'b110000000000000;                  // 0x6000
2638
        16: polynom = 32'b1101000000001000;                 // 0xD008
2639
        17: polynom = 32'b10010000000000000;                // 0x12000
2640
        18: polynom = 32'b100000010000000000;               // 0x20400
2641
        19: polynom = 32'b1000000000000100011;              // 0x40023
2642
        20: polynom = 32'b10010000000000000000;             // 0x90000
2643
        21: polynom = 32'b101000000000000000000;            // 0x140000
2644
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2645
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2646
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2647
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2648
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2649
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2650
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2651
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2652
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2653
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2654
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2655
        default: polynom = 32'b0;
2656
        endcase
2657
        lfsr_fb = qi[length];
2658
        for (i=length-1; i>=1; i=i-1) begin
2659
            if (polynom[i])
2660
                lfsr_fb = lfsr_fb  ~^ qi[i];
2661
        end
2662
    end
2663
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2664
 
2665
   always @ (posedge clk or posedge rst)
2666
     if (rst)
2667
       qi <= {length{1'b0}};
2668
     else
2669
     if (cke)
2670
       qi <= q_next;
2671
 
2672
 
2673
 
2674
   always @ (posedge clk or posedge rst)
2675
     if (rst)
2676
       zq <= 1'b1;
2677
     else
2678
     if (cke)
2679
       zq <= q_next == {length{1'b0}};
2680
endmodule
2681
`endif
2682 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2683 6 unneback
//////////////////////////////////////////////////////////////////////
2684
////                                                              ////
2685
////  Versatile counter                                           ////
2686
////                                                              ////
2687
////  Description                                                 ////
2688
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2689
////  counter                                                     ////
2690
////                                                              ////
2691
////  To Do:                                                      ////
2692
////   - add LFSR with more taps                                  ////
2693
////                                                              ////
2694
////  Author(s):                                                  ////
2695
////      - Michael Unneback, unneback@opencores.org              ////
2696
////        ORSoC AB                                              ////
2697
////                                                              ////
2698
//////////////////////////////////////////////////////////////////////
2699
////                                                              ////
2700
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2701
////                                                              ////
2702
//// This source file may be used and distributed without         ////
2703
//// restriction provided that this copyright statement is not    ////
2704
//// removed from the file and that any derivative work contains  ////
2705
//// the original copyright notice and the associated disclaimer. ////
2706
////                                                              ////
2707
//// This source file is free software; you can redistribute it   ////
2708
//// and/or modify it under the terms of the GNU Lesser General   ////
2709
//// Public License as published by the Free Software Foundation; ////
2710
//// either version 2.1 of the License, or (at your option) any   ////
2711
//// later version.                                               ////
2712
////                                                              ////
2713
//// This source is distributed in the hope that it will be       ////
2714
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2715
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2716
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2717
//// details.                                                     ////
2718
////                                                              ////
2719
//// You should have received a copy of the GNU Lesser General    ////
2720
//// Public License along with this source; if not, download it   ////
2721
//// from http://www.opencores.org/lgpl.shtml                     ////
2722
////                                                              ////
2723
//////////////////////////////////////////////////////////////////////
2724
 
2725
// LFSR counter
2726
 
2727 40 unneback
`define MODULE cnt_lfsr_ce_zq
2728
module `BASE`MODULE (
2729
`undef MODULE
2730
 cke, zq, rst, clk);
2731
 
2732 6 unneback
   parameter length = 4;
2733
   input cke;
2734
   output reg zq;
2735
   input rst;
2736
   input clk;
2737
 
2738
   parameter clear_value = 0;
2739
   parameter set_value = 1;
2740
   parameter wrap_value = 8;
2741
   parameter level1_value = 15;
2742
 
2743
   reg  [length:1] qi;
2744
   reg lfsr_fb;
2745
   wire [length:1] q_next;
2746
   reg [32:1] polynom;
2747
   integer i;
2748
 
2749
   always @ (qi)
2750
   begin
2751
        case (length)
2752
         2: polynom = 32'b11;                               // 0x3
2753
         3: polynom = 32'b110;                              // 0x6
2754
         4: polynom = 32'b1100;                             // 0xC
2755
         5: polynom = 32'b10100;                            // 0x14
2756
         6: polynom = 32'b110000;                           // 0x30
2757
         7: polynom = 32'b1100000;                          // 0x60
2758
         8: polynom = 32'b10111000;                         // 0xb8
2759
         9: polynom = 32'b100010000;                        // 0x110
2760
        10: polynom = 32'b1001000000;                       // 0x240
2761
        11: polynom = 32'b10100000000;                      // 0x500
2762
        12: polynom = 32'b100000101001;                     // 0x829
2763
        13: polynom = 32'b1000000001100;                    // 0x100C
2764
        14: polynom = 32'b10000000010101;                   // 0x2015
2765
        15: polynom = 32'b110000000000000;                  // 0x6000
2766
        16: polynom = 32'b1101000000001000;                 // 0xD008
2767
        17: polynom = 32'b10010000000000000;                // 0x12000
2768
        18: polynom = 32'b100000010000000000;               // 0x20400
2769
        19: polynom = 32'b1000000000000100011;              // 0x40023
2770 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2771 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2772
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2773
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2774
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2775
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2776
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2777
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2778
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2779
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2780
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2781
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2782
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2783
        default: polynom = 32'b0;
2784
        endcase
2785
        lfsr_fb = qi[length];
2786
        for (i=length-1; i>=1; i=i-1) begin
2787
            if (polynom[i])
2788
                lfsr_fb = lfsr_fb  ~^ qi[i];
2789
        end
2790
    end
2791
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2792
 
2793
   always @ (posedge clk or posedge rst)
2794
     if (rst)
2795
       qi <= {length{1'b0}};
2796
     else
2797
     if (cke)
2798
       qi <= q_next;
2799
 
2800
 
2801
 
2802
   always @ (posedge clk or posedge rst)
2803
     if (rst)
2804
       zq <= 1'b1;
2805
     else
2806
     if (cke)
2807
       zq <= q_next == {length{1'b0}};
2808
endmodule
2809 40 unneback
`endif
2810
`ifdef CNT_LFSR_CE_Q
2811 6 unneback
//////////////////////////////////////////////////////////////////////
2812
////                                                              ////
2813
////  Versatile counter                                           ////
2814
////                                                              ////
2815
////  Description                                                 ////
2816
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2817
////  counter                                                     ////
2818
////                                                              ////
2819
////  To Do:                                                      ////
2820
////   - add LFSR with more taps                                  ////
2821
////                                                              ////
2822
////  Author(s):                                                  ////
2823
////      - Michael Unneback, unneback@opencores.org              ////
2824
////        ORSoC AB                                              ////
2825
////                                                              ////
2826
//////////////////////////////////////////////////////////////////////
2827
////                                                              ////
2828
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2829
////                                                              ////
2830
//// This source file may be used and distributed without         ////
2831
//// restriction provided that this copyright statement is not    ////
2832
//// removed from the file and that any derivative work contains  ////
2833
//// the original copyright notice and the associated disclaimer. ////
2834
////                                                              ////
2835
//// This source file is free software; you can redistribute it   ////
2836
//// and/or modify it under the terms of the GNU Lesser General   ////
2837
//// Public License as published by the Free Software Foundation; ////
2838
//// either version 2.1 of the License, or (at your option) any   ////
2839
//// later version.                                               ////
2840
////                                                              ////
2841
//// This source is distributed in the hope that it will be       ////
2842
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2843
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2844
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2845
//// details.                                                     ////
2846
////                                                              ////
2847
//// You should have received a copy of the GNU Lesser General    ////
2848
//// Public License along with this source; if not, download it   ////
2849
//// from http://www.opencores.org/lgpl.shtml                     ////
2850
////                                                              ////
2851
//////////////////////////////////////////////////////////////////////
2852 22 unneback
 
2853
// LFSR counter
2854 27 unneback
 
2855 40 unneback
`define MODULE cnt_lfsr_ce_q
2856
module `BASE`MODULE (
2857
`undef MODULE
2858
 cke, q, rst, clk);
2859
 
2860 27 unneback
   parameter length = 4;
2861
   input cke;
2862
   output [length:1] q;
2863
   input rst;
2864
   input clk;
2865
 
2866
   parameter clear_value = 0;
2867
   parameter set_value = 1;
2868
   parameter wrap_value = 8;
2869
   parameter level1_value = 15;
2870
 
2871
   reg  [length:1] qi;
2872
   reg lfsr_fb;
2873
   wire [length:1] q_next;
2874
   reg [32:1] polynom;
2875
   integer i;
2876
 
2877
   always @ (qi)
2878
   begin
2879
        case (length)
2880
         2: polynom = 32'b11;                               // 0x3
2881
         3: polynom = 32'b110;                              // 0x6
2882
         4: polynom = 32'b1100;                             // 0xC
2883
         5: polynom = 32'b10100;                            // 0x14
2884
         6: polynom = 32'b110000;                           // 0x30
2885
         7: polynom = 32'b1100000;                          // 0x60
2886
         8: polynom = 32'b10111000;                         // 0xb8
2887
         9: polynom = 32'b100010000;                        // 0x110
2888
        10: polynom = 32'b1001000000;                       // 0x240
2889
        11: polynom = 32'b10100000000;                      // 0x500
2890
        12: polynom = 32'b100000101001;                     // 0x829
2891
        13: polynom = 32'b1000000001100;                    // 0x100C
2892
        14: polynom = 32'b10000000010101;                   // 0x2015
2893
        15: polynom = 32'b110000000000000;                  // 0x6000
2894
        16: polynom = 32'b1101000000001000;                 // 0xD008
2895
        17: polynom = 32'b10010000000000000;                // 0x12000
2896
        18: polynom = 32'b100000010000000000;               // 0x20400
2897
        19: polynom = 32'b1000000000000100011;              // 0x40023
2898 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2899 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2900
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2901
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2902
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2903
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2904
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2905
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2906
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2907
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2908
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2909
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2910
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2911
        default: polynom = 32'b0;
2912
        endcase
2913
        lfsr_fb = qi[length];
2914
        for (i=length-1; i>=1; i=i-1) begin
2915
            if (polynom[i])
2916
                lfsr_fb = lfsr_fb  ~^ qi[i];
2917
        end
2918
    end
2919
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2920
 
2921
   always @ (posedge clk or posedge rst)
2922
     if (rst)
2923
       qi <= {length{1'b0}};
2924
     else
2925
     if (cke)
2926
       qi <= q_next;
2927
 
2928
   assign q = qi;
2929
 
2930
endmodule
2931 40 unneback
`endif
2932
`ifdef CNT_LFSR_CE_CLEAR_Q
2933 27 unneback
//////////////////////////////////////////////////////////////////////
2934
////                                                              ////
2935
////  Versatile counter                                           ////
2936
////                                                              ////
2937
////  Description                                                 ////
2938
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2939
////  counter                                                     ////
2940
////                                                              ////
2941
////  To Do:                                                      ////
2942
////   - add LFSR with more taps                                  ////
2943
////                                                              ////
2944
////  Author(s):                                                  ////
2945
////      - Michael Unneback, unneback@opencores.org              ////
2946
////        ORSoC AB                                              ////
2947
////                                                              ////
2948
//////////////////////////////////////////////////////////////////////
2949
////                                                              ////
2950
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2951
////                                                              ////
2952
//// This source file may be used and distributed without         ////
2953
//// restriction provided that this copyright statement is not    ////
2954
//// removed from the file and that any derivative work contains  ////
2955
//// the original copyright notice and the associated disclaimer. ////
2956
////                                                              ////
2957
//// This source file is free software; you can redistribute it   ////
2958
//// and/or modify it under the terms of the GNU Lesser General   ////
2959
//// Public License as published by the Free Software Foundation; ////
2960
//// either version 2.1 of the License, or (at your option) any   ////
2961
//// later version.                                               ////
2962
////                                                              ////
2963
//// This source is distributed in the hope that it will be       ////
2964
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2965
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2966
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2967
//// details.                                                     ////
2968
////                                                              ////
2969
//// You should have received a copy of the GNU Lesser General    ////
2970
//// Public License along with this source; if not, download it   ////
2971
//// from http://www.opencores.org/lgpl.shtml                     ////
2972
////                                                              ////
2973
//////////////////////////////////////////////////////////////////////
2974
 
2975
// LFSR counter
2976
 
2977 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2978
module `BASE`MODULE (
2979
`undef MODULE
2980
 clear, cke, q, rst, clk);
2981
 
2982 27 unneback
   parameter length = 4;
2983
   input clear;
2984
   input cke;
2985
   output [length:1] q;
2986
   input rst;
2987
   input clk;
2988
 
2989
   parameter clear_value = 0;
2990
   parameter set_value = 1;
2991
   parameter wrap_value = 8;
2992
   parameter level1_value = 15;
2993
 
2994
   reg  [length:1] qi;
2995
   reg lfsr_fb;
2996
   wire [length:1] q_next;
2997
   reg [32:1] polynom;
2998
   integer i;
2999
 
3000
   always @ (qi)
3001
   begin
3002
        case (length)
3003
         2: polynom = 32'b11;                               // 0x3
3004
         3: polynom = 32'b110;                              // 0x6
3005
         4: polynom = 32'b1100;                             // 0xC
3006
         5: polynom = 32'b10100;                            // 0x14
3007
         6: polynom = 32'b110000;                           // 0x30
3008
         7: polynom = 32'b1100000;                          // 0x60
3009
         8: polynom = 32'b10111000;                         // 0xb8
3010
         9: polynom = 32'b100010000;                        // 0x110
3011
        10: polynom = 32'b1001000000;                       // 0x240
3012
        11: polynom = 32'b10100000000;                      // 0x500
3013
        12: polynom = 32'b100000101001;                     // 0x829
3014
        13: polynom = 32'b1000000001100;                    // 0x100C
3015
        14: polynom = 32'b10000000010101;                   // 0x2015
3016
        15: polynom = 32'b110000000000000;                  // 0x6000
3017
        16: polynom = 32'b1101000000001000;                 // 0xD008
3018
        17: polynom = 32'b10010000000000000;                // 0x12000
3019
        18: polynom = 32'b100000010000000000;               // 0x20400
3020
        19: polynom = 32'b1000000000000100011;              // 0x40023
3021 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3022 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3023
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3024
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3025
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3026
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3027
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3028
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3029
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3030
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3031
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3032
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3033
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3034
        default: polynom = 32'b0;
3035
        endcase
3036
        lfsr_fb = qi[length];
3037
        for (i=length-1; i>=1; i=i-1) begin
3038
            if (polynom[i])
3039
                lfsr_fb = lfsr_fb  ~^ qi[i];
3040
        end
3041
    end
3042
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3043
 
3044
   always @ (posedge clk or posedge rst)
3045
     if (rst)
3046
       qi <= {length{1'b0}};
3047
     else
3048
     if (cke)
3049
       qi <= q_next;
3050
 
3051
   assign q = qi;
3052
 
3053
endmodule
3054 40 unneback
`endif
3055
`ifdef CNT_LFSR_CE_Q_ZQ
3056 27 unneback
//////////////////////////////////////////////////////////////////////
3057
////                                                              ////
3058
////  Versatile counter                                           ////
3059
////                                                              ////
3060
////  Description                                                 ////
3061
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3062
////  counter                                                     ////
3063
////                                                              ////
3064
////  To Do:                                                      ////
3065
////   - add LFSR with more taps                                  ////
3066
////                                                              ////
3067
////  Author(s):                                                  ////
3068
////      - Michael Unneback, unneback@opencores.org              ////
3069
////        ORSoC AB                                              ////
3070
////                                                              ////
3071
//////////////////////////////////////////////////////////////////////
3072
////                                                              ////
3073
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3074
////                                                              ////
3075
//// This source file may be used and distributed without         ////
3076
//// restriction provided that this copyright statement is not    ////
3077
//// removed from the file and that any derivative work contains  ////
3078
//// the original copyright notice and the associated disclaimer. ////
3079
////                                                              ////
3080
//// This source file is free software; you can redistribute it   ////
3081
//// and/or modify it under the terms of the GNU Lesser General   ////
3082
//// Public License as published by the Free Software Foundation; ////
3083
//// either version 2.1 of the License, or (at your option) any   ////
3084
//// later version.                                               ////
3085
////                                                              ////
3086
//// This source is distributed in the hope that it will be       ////
3087
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3088
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3089
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3090
//// details.                                                     ////
3091
////                                                              ////
3092
//// You should have received a copy of the GNU Lesser General    ////
3093
//// Public License along with this source; if not, download it   ////
3094
//// from http://www.opencores.org/lgpl.shtml                     ////
3095
////                                                              ////
3096
//////////////////////////////////////////////////////////////////////
3097
 
3098
// LFSR counter
3099 22 unneback
 
3100 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
3101
module `BASE`MODULE (
3102
`undef MODULE
3103
 cke, q, zq, rst, clk);
3104
 
3105 22 unneback
   parameter length = 4;
3106
   input cke;
3107
   output [length:1] q;
3108
   output reg zq;
3109
   input rst;
3110
   input clk;
3111
 
3112
   parameter clear_value = 0;
3113
   parameter set_value = 1;
3114
   parameter wrap_value = 8;
3115
   parameter level1_value = 15;
3116
 
3117
   reg  [length:1] qi;
3118
   reg lfsr_fb;
3119
   wire [length:1] q_next;
3120
   reg [32:1] polynom;
3121
   integer i;
3122
 
3123
   always @ (qi)
3124
   begin
3125
        case (length)
3126
         2: polynom = 32'b11;                               // 0x3
3127
         3: polynom = 32'b110;                              // 0x6
3128
         4: polynom = 32'b1100;                             // 0xC
3129
         5: polynom = 32'b10100;                            // 0x14
3130
         6: polynom = 32'b110000;                           // 0x30
3131
         7: polynom = 32'b1100000;                          // 0x60
3132
         8: polynom = 32'b10111000;                         // 0xb8
3133
         9: polynom = 32'b100010000;                        // 0x110
3134
        10: polynom = 32'b1001000000;                       // 0x240
3135
        11: polynom = 32'b10100000000;                      // 0x500
3136
        12: polynom = 32'b100000101001;                     // 0x829
3137
        13: polynom = 32'b1000000001100;                    // 0x100C
3138
        14: polynom = 32'b10000000010101;                   // 0x2015
3139
        15: polynom = 32'b110000000000000;                  // 0x6000
3140
        16: polynom = 32'b1101000000001000;                 // 0xD008
3141
        17: polynom = 32'b10010000000000000;                // 0x12000
3142
        18: polynom = 32'b100000010000000000;               // 0x20400
3143
        19: polynom = 32'b1000000000000100011;              // 0x40023
3144 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3145 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3146
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3147
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3148
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3149
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3150
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3151
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3152
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3153
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3154
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3155
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3156
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3157
        default: polynom = 32'b0;
3158
        endcase
3159
        lfsr_fb = qi[length];
3160
        for (i=length-1; i>=1; i=i-1) begin
3161
            if (polynom[i])
3162
                lfsr_fb = lfsr_fb  ~^ qi[i];
3163
        end
3164
    end
3165
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3166
 
3167
   always @ (posedge clk or posedge rst)
3168
     if (rst)
3169
       qi <= {length{1'b0}};
3170
     else
3171
     if (cke)
3172
       qi <= q_next;
3173
 
3174
   assign q = qi;
3175
 
3176
 
3177
   always @ (posedge clk or posedge rst)
3178
     if (rst)
3179
       zq <= 1'b1;
3180
     else
3181
     if (cke)
3182
       zq <= q_next == {length{1'b0}};
3183
endmodule
3184 40 unneback
`endif
3185
`ifdef CNT_LFSR_CE_REW_L1
3186 22 unneback
//////////////////////////////////////////////////////////////////////
3187
////                                                              ////
3188
////  Versatile counter                                           ////
3189
////                                                              ////
3190
////  Description                                                 ////
3191
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3192
////  counter                                                     ////
3193
////                                                              ////
3194
////  To Do:                                                      ////
3195
////   - add LFSR with more taps                                  ////
3196
////                                                              ////
3197
////  Author(s):                                                  ////
3198
////      - Michael Unneback, unneback@opencores.org              ////
3199
////        ORSoC AB                                              ////
3200
////                                                              ////
3201
//////////////////////////////////////////////////////////////////////
3202
////                                                              ////
3203
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3204
////                                                              ////
3205
//// This source file may be used and distributed without         ////
3206
//// restriction provided that this copyright statement is not    ////
3207
//// removed from the file and that any derivative work contains  ////
3208
//// the original copyright notice and the associated disclaimer. ////
3209
////                                                              ////
3210
//// This source file is free software; you can redistribute it   ////
3211
//// and/or modify it under the terms of the GNU Lesser General   ////
3212
//// Public License as published by the Free Software Foundation; ////
3213
//// either version 2.1 of the License, or (at your option) any   ////
3214
//// later version.                                               ////
3215
////                                                              ////
3216
//// This source is distributed in the hope that it will be       ////
3217
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3218
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3219
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3220
//// details.                                                     ////
3221
////                                                              ////
3222
//// You should have received a copy of the GNU Lesser General    ////
3223
//// Public License along with this source; if not, download it   ////
3224
//// from http://www.opencores.org/lgpl.shtml                     ////
3225
////                                                              ////
3226
//////////////////////////////////////////////////////////////////////
3227 6 unneback
 
3228
// LFSR counter
3229
 
3230 40 unneback
`define MODULE cnt_lfsr_ce_rew_l1
3231
module `BASE`MODULE (
3232
`undef MODULE
3233
 cke, rew, level1, rst, clk);
3234
 
3235 6 unneback
   parameter length = 4;
3236
   input cke;
3237
   input rew;
3238
   output reg level1;
3239
   input rst;
3240
   input clk;
3241
 
3242
   parameter clear_value = 0;
3243
   parameter set_value = 1;
3244
   parameter wrap_value = 8;
3245
   parameter level1_value = 15;
3246
 
3247 29 unneback
   wire clear;
3248 30 unneback
   assign clear = 1'b0;
3249 6 unneback
   reg  [length:1] qi;
3250
   reg lfsr_fb, lfsr_fb_rew;
3251
   wire  [length:1] q_next, q_next_fw, q_next_rew;
3252
   reg [32:1] polynom_rew;
3253
   integer j;
3254
   reg [32:1] polynom;
3255
   integer i;
3256
 
3257
   always @ (qi)
3258
   begin
3259
        case (length)
3260
         2: polynom = 32'b11;                               // 0x3
3261
         3: polynom = 32'b110;                              // 0x6
3262
         4: polynom = 32'b1100;                             // 0xC
3263
         5: polynom = 32'b10100;                            // 0x14
3264
         6: polynom = 32'b110000;                           // 0x30
3265
         7: polynom = 32'b1100000;                          // 0x60
3266
         8: polynom = 32'b10111000;                         // 0xb8
3267
         9: polynom = 32'b100010000;                        // 0x110
3268
        10: polynom = 32'b1001000000;                       // 0x240
3269
        11: polynom = 32'b10100000000;                      // 0x500
3270
        12: polynom = 32'b100000101001;                     // 0x829
3271
        13: polynom = 32'b1000000001100;                    // 0x100C
3272
        14: polynom = 32'b10000000010101;                   // 0x2015
3273
        15: polynom = 32'b110000000000000;                  // 0x6000
3274
        16: polynom = 32'b1101000000001000;                 // 0xD008
3275
        17: polynom = 32'b10010000000000000;                // 0x12000
3276
        18: polynom = 32'b100000010000000000;               // 0x20400
3277
        19: polynom = 32'b1000000000000100011;              // 0x40023
3278 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3279 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3280
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3281
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3282
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3283
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3284
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3285
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3286
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3287
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3288
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3289
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3290
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3291
        default: polynom = 32'b0;
3292
        endcase
3293
        lfsr_fb = qi[length];
3294
        for (i=length-1; i>=1; i=i-1) begin
3295
            if (polynom[i])
3296
                lfsr_fb = lfsr_fb  ~^ qi[i];
3297
        end
3298
    end
3299
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3300
   always @ (qi)
3301
   begin
3302
        case (length)
3303
         2: polynom_rew = 32'b11;
3304
         3: polynom_rew = 32'b110;
3305
         4: polynom_rew = 32'b1100;
3306
         5: polynom_rew = 32'b10100;
3307
         6: polynom_rew = 32'b110000;
3308
         7: polynom_rew = 32'b1100000;
3309
         8: polynom_rew = 32'b10111000;
3310
         9: polynom_rew = 32'b100010000;
3311
        10: polynom_rew = 32'b1001000000;
3312
        11: polynom_rew = 32'b10100000000;
3313
        12: polynom_rew = 32'b100000101001;
3314
        13: polynom_rew = 32'b1000000001100;
3315
        14: polynom_rew = 32'b10000000010101;
3316
        15: polynom_rew = 32'b110000000000000;
3317
        16: polynom_rew = 32'b1101000000001000;
3318
        17: polynom_rew = 32'b10010000000000000;
3319
        18: polynom_rew = 32'b100000010000000000;
3320
        19: polynom_rew = 32'b1000000000000100011;
3321
        20: polynom_rew = 32'b10000010000000000000;
3322
        21: polynom_rew = 32'b101000000000000000000;
3323
        22: polynom_rew = 32'b1100000000000000000000;
3324
        23: polynom_rew = 32'b10000100000000000000000;
3325
        24: polynom_rew = 32'b111000010000000000000000;
3326
        25: polynom_rew = 32'b1001000000000000000000000;
3327
        26: polynom_rew = 32'b10000000000000000000100011;
3328
        27: polynom_rew = 32'b100000000000000000000010011;
3329
        28: polynom_rew = 32'b1100100000000000000000000000;
3330
        29: polynom_rew = 32'b10100000000000000000000000000;
3331
        30: polynom_rew = 32'b100000000000000000000000101001;
3332
        31: polynom_rew = 32'b1001000000000000000000000000000;
3333
        32: polynom_rew = 32'b10000000001000000000000000000011;
3334
        default: polynom_rew = 32'b0;
3335
        endcase
3336
        // rotate left
3337
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3338
        lfsr_fb_rew = qi[length];
3339
        for (i=length-1; i>=1; i=i-1) begin
3340
            if (polynom_rew[i])
3341
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3342
        end
3343
    end
3344
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3345
   assign q_next = rew ? q_next_rew : q_next_fw;
3346
 
3347
   always @ (posedge clk or posedge rst)
3348
     if (rst)
3349
       qi <= {length{1'b0}};
3350
     else
3351
     if (cke)
3352
       qi <= q_next;
3353
 
3354
 
3355
 
3356
    always @ (posedge clk or posedge rst)
3357
    if (rst)
3358
        level1 <= 1'b0;
3359
    else
3360
    if (cke)
3361 29 unneback
    if (clear)
3362
        level1 <= 1'b0;
3363
    else if (q_next == level1_value)
3364 6 unneback
        level1 <= 1'b1;
3365
    else if (qi == level1_value & rew)
3366
        level1 <= 1'b0;
3367
endmodule
3368 40 unneback
`endif
3369
`ifdef CNT_GRAY
3370 6 unneback
//////////////////////////////////////////////////////////////////////
3371
////                                                              ////
3372
////  Versatile counter                                           ////
3373
////                                                              ////
3374
////  Description                                                 ////
3375
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3376
////  counter                                                     ////
3377
////                                                              ////
3378
////  To Do:                                                      ////
3379
////   - add LFSR with more taps                                  ////
3380
////                                                              ////
3381
////  Author(s):                                                  ////
3382
////      - Michael Unneback, unneback@opencores.org              ////
3383
////        ORSoC AB                                              ////
3384
////                                                              ////
3385
//////////////////////////////////////////////////////////////////////
3386
////                                                              ////
3387
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3388
////                                                              ////
3389
//// This source file may be used and distributed without         ////
3390
//// restriction provided that this copyright statement is not    ////
3391
//// removed from the file and that any derivative work contains  ////
3392
//// the original copyright notice and the associated disclaimer. ////
3393
////                                                              ////
3394
//// This source file is free software; you can redistribute it   ////
3395
//// and/or modify it under the terms of the GNU Lesser General   ////
3396
//// Public License as published by the Free Software Foundation; ////
3397
//// either version 2.1 of the License, or (at your option) any   ////
3398
//// later version.                                               ////
3399
////                                                              ////
3400
//// This source is distributed in the hope that it will be       ////
3401
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3402
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3403
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3404
//// details.                                                     ////
3405
////                                                              ////
3406
//// You should have received a copy of the GNU Lesser General    ////
3407
//// Public License along with this source; if not, download it   ////
3408
//// from http://www.opencores.org/lgpl.shtml                     ////
3409
////                                                              ////
3410
//////////////////////////////////////////////////////////////////////
3411
 
3412
// GRAY counter
3413
 
3414 40 unneback
`define MODULE cnt_gray
3415
module `BASE`MODULE (
3416
`undef MODULE
3417
 q, rst, clk);
3418
 
3419 6 unneback
   parameter length = 4;
3420
   output reg [length:1] q;
3421
   input rst;
3422
   input clk;
3423
 
3424
   parameter clear_value = 0;
3425
   parameter set_value = 1;
3426
   parameter wrap_value = 8;
3427
   parameter level1_value = 15;
3428
 
3429
   reg  [length:1] qi;
3430
   wire [length:1] q_next;
3431
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3432
 
3433
   always @ (posedge clk or posedge rst)
3434
     if (rst)
3435
       qi <= {length{1'b0}};
3436
     else
3437
       qi <= q_next;
3438
 
3439
   always @ (posedge clk or posedge rst)
3440
     if (rst)
3441
       q <= {length{1'b0}};
3442
     else
3443
         q <= (q_next>>1) ^ q_next;
3444
 
3445
endmodule
3446 40 unneback
`endif
3447
`ifdef CNT_GRAY_CE
3448 6 unneback
//////////////////////////////////////////////////////////////////////
3449
////                                                              ////
3450
////  Versatile counter                                           ////
3451
////                                                              ////
3452
////  Description                                                 ////
3453
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3454
////  counter                                                     ////
3455
////                                                              ////
3456
////  To Do:                                                      ////
3457
////   - add LFSR with more taps                                  ////
3458
////                                                              ////
3459
////  Author(s):                                                  ////
3460
////      - Michael Unneback, unneback@opencores.org              ////
3461
////        ORSoC AB                                              ////
3462
////                                                              ////
3463
//////////////////////////////////////////////////////////////////////
3464
////                                                              ////
3465
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3466
////                                                              ////
3467
//// This source file may be used and distributed without         ////
3468
//// restriction provided that this copyright statement is not    ////
3469
//// removed from the file and that any derivative work contains  ////
3470
//// the original copyright notice and the associated disclaimer. ////
3471
////                                                              ////
3472
//// This source file is free software; you can redistribute it   ////
3473
//// and/or modify it under the terms of the GNU Lesser General   ////
3474
//// Public License as published by the Free Software Foundation; ////
3475
//// either version 2.1 of the License, or (at your option) any   ////
3476
//// later version.                                               ////
3477
////                                                              ////
3478
//// This source is distributed in the hope that it will be       ////
3479
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3480
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3481
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3482
//// details.                                                     ////
3483
////                                                              ////
3484
//// You should have received a copy of the GNU Lesser General    ////
3485
//// Public License along with this source; if not, download it   ////
3486
//// from http://www.opencores.org/lgpl.shtml                     ////
3487
////                                                              ////
3488
//////////////////////////////////////////////////////////////////////
3489
 
3490
// GRAY counter
3491
 
3492 40 unneback
`define MODULE cnt_gray_ce
3493
module `BASE`MODULE (
3494
`undef MODULE
3495
 cke, q, rst, clk);
3496
 
3497 6 unneback
   parameter length = 4;
3498
   input cke;
3499
   output reg [length:1] q;
3500
   input rst;
3501
   input clk;
3502
 
3503
   parameter clear_value = 0;
3504
   parameter set_value = 1;
3505
   parameter wrap_value = 8;
3506
   parameter level1_value = 15;
3507
 
3508
   reg  [length:1] qi;
3509
   wire [length:1] q_next;
3510
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3511
 
3512
   always @ (posedge clk or posedge rst)
3513
     if (rst)
3514
       qi <= {length{1'b0}};
3515
     else
3516
     if (cke)
3517
       qi <= q_next;
3518
 
3519
   always @ (posedge clk or posedge rst)
3520
     if (rst)
3521
       q <= {length{1'b0}};
3522
     else
3523
       if (cke)
3524
         q <= (q_next>>1) ^ q_next;
3525
 
3526
endmodule
3527 40 unneback
`endif
3528
`ifdef CNT_GRAY_CE_BIN
3529 6 unneback
//////////////////////////////////////////////////////////////////////
3530
////                                                              ////
3531
////  Versatile counter                                           ////
3532
////                                                              ////
3533
////  Description                                                 ////
3534
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3535
////  counter                                                     ////
3536
////                                                              ////
3537
////  To Do:                                                      ////
3538
////   - add LFSR with more taps                                  ////
3539
////                                                              ////
3540
////  Author(s):                                                  ////
3541
////      - Michael Unneback, unneback@opencores.org              ////
3542
////        ORSoC AB                                              ////
3543
////                                                              ////
3544
//////////////////////////////////////////////////////////////////////
3545
////                                                              ////
3546
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3547
////                                                              ////
3548
//// This source file may be used and distributed without         ////
3549
//// restriction provided that this copyright statement is not    ////
3550
//// removed from the file and that any derivative work contains  ////
3551
//// the original copyright notice and the associated disclaimer. ////
3552
////                                                              ////
3553
//// This source file is free software; you can redistribute it   ////
3554
//// and/or modify it under the terms of the GNU Lesser General   ////
3555
//// Public License as published by the Free Software Foundation; ////
3556
//// either version 2.1 of the License, or (at your option) any   ////
3557
//// later version.                                               ////
3558
////                                                              ////
3559
//// This source is distributed in the hope that it will be       ////
3560
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3561
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3562
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3563
//// details.                                                     ////
3564
////                                                              ////
3565
//// You should have received a copy of the GNU Lesser General    ////
3566
//// Public License along with this source; if not, download it   ////
3567
//// from http://www.opencores.org/lgpl.shtml                     ////
3568
////                                                              ////
3569
//////////////////////////////////////////////////////////////////////
3570
 
3571
// GRAY counter
3572
 
3573 40 unneback
`define MODULE cnt_gray_ce_bin
3574
module `BASE`MODULE (
3575
`undef MODULE
3576
 cke, q, q_bin, rst, clk);
3577
 
3578 6 unneback
   parameter length = 4;
3579
   input cke;
3580
   output reg [length:1] q;
3581
   output [length:1] q_bin;
3582
   input rst;
3583
   input clk;
3584
 
3585
   parameter clear_value = 0;
3586
   parameter set_value = 1;
3587
   parameter wrap_value = 8;
3588
   parameter level1_value = 15;
3589
 
3590
   reg  [length:1] qi;
3591
   wire [length:1] q_next;
3592
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3593
 
3594
   always @ (posedge clk or posedge rst)
3595
     if (rst)
3596
       qi <= {length{1'b0}};
3597
     else
3598
     if (cke)
3599
       qi <= q_next;
3600
 
3601
   always @ (posedge clk or posedge rst)
3602
     if (rst)
3603
       q <= {length{1'b0}};
3604
     else
3605
       if (cke)
3606
         q <= (q_next>>1) ^ q_next;
3607
 
3608
   assign q_bin = qi;
3609
 
3610
endmodule
3611 40 unneback
`endif
3612 6 unneback
//////////////////////////////////////////////////////////////////////
3613
////                                                              ////
3614
////  Versatile library, counters                                 ////
3615
////                                                              ////
3616
////  Description                                                 ////
3617
////  counters                                                    ////
3618
////                                                              ////
3619
////                                                              ////
3620
////  To Do:                                                      ////
3621
////   - add more counters                                        ////
3622
////                                                              ////
3623
////  Author(s):                                                  ////
3624
////      - Michael Unneback, unneback@opencores.org              ////
3625
////        ORSoC AB                                              ////
3626
////                                                              ////
3627
//////////////////////////////////////////////////////////////////////
3628
////                                                              ////
3629
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3630
////                                                              ////
3631
//// This source file may be used and distributed without         ////
3632
//// restriction provided that this copyright statement is not    ////
3633
//// removed from the file and that any derivative work contains  ////
3634
//// the original copyright notice and the associated disclaimer. ////
3635
////                                                              ////
3636
//// This source file is free software; you can redistribute it   ////
3637
//// and/or modify it under the terms of the GNU Lesser General   ////
3638
//// Public License as published by the Free Software Foundation; ////
3639
//// either version 2.1 of the License, or (at your option) any   ////
3640
//// later version.                                               ////
3641
////                                                              ////
3642
//// This source is distributed in the hope that it will be       ////
3643
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3644
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3645
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3646
//// details.                                                     ////
3647
////                                                              ////
3648
//// You should have received a copy of the GNU Lesser General    ////
3649
//// Public License along with this source; if not, download it   ////
3650
//// from http://www.opencores.org/lgpl.shtml                     ////
3651
////                                                              ////
3652
//////////////////////////////////////////////////////////////////////
3653
 
3654 40 unneback
`ifdef CNT_SHREG_WRAP
3655
`define MODULE cnt_shreg_wrap
3656
module `BASE`MODULE ( q, rst, clk);
3657
`undef MODULE
3658 6 unneback
 
3659
   parameter length = 4;
3660
   output reg [0:length-1] q;
3661
   input rst;
3662
   input clk;
3663
 
3664
    always @ (posedge clk or posedge rst)
3665
    if (rst)
3666
        q <= {1'b1,{length-1{1'b0}}};
3667
    else
3668
        q <= {q[length-1],q[0:length-2]};
3669
 
3670
endmodule
3671 40 unneback
`endif
3672 6 unneback
 
3673 40 unneback
`ifdef CNT_SHREG_CE_WRAP
3674
`define MODULE cnt_shreg_ce_wrap
3675
module `BASE`MODULE ( cke, q, rst, clk);
3676
`undef MODULE
3677 6 unneback
 
3678
   parameter length = 4;
3679
   input cke;
3680
   output reg [0:length-1] q;
3681
   input rst;
3682
   input clk;
3683
 
3684
    always @ (posedge clk or posedge rst)
3685
    if (rst)
3686
        q <= {1'b1,{length-1{1'b0}}};
3687
    else
3688
        if (cke)
3689
            q <= {q[length-1],q[0:length-2]};
3690
 
3691
endmodule
3692 40 unneback
`endif
3693 6 unneback
 
3694 105 unneback
`ifdef CNT_SHREG_CLEAR
3695
`define MODULE cnt_shreg_clear
3696
module `BASE`MODULE ( clear, q, rst, clk);
3697
`undef MODULE
3698
 
3699
   parameter length = 4;
3700
   input clear;
3701
   output reg [0:length-1] q;
3702
   input rst;
3703
   input clk;
3704
 
3705
    always @ (posedge clk or posedge rst)
3706
    if (rst)
3707
        q <= {1'b1,{length-1{1'b0}}};
3708
    else
3709
        if (clear)
3710
            q <= {1'b1,{length-1{1'b0}}};
3711
        else
3712
            q <= q >> 1;
3713
 
3714
endmodule
3715
`endif
3716
 
3717 40 unneback
`ifdef CNT_SHREG_CE_CLEAR
3718
`define MODULE cnt_shreg_ce_clear
3719
module `BASE`MODULE ( cke, clear, q, rst, clk);
3720
`undef MODULE
3721 6 unneback
 
3722
   parameter length = 4;
3723
   input cke, clear;
3724
   output reg [0:length-1] q;
3725
   input rst;
3726
   input clk;
3727
 
3728
    always @ (posedge clk or posedge rst)
3729
    if (rst)
3730
        q <= {1'b1,{length-1{1'b0}}};
3731
    else
3732
        if (cke)
3733
            if (clear)
3734
                q <= {1'b1,{length-1{1'b0}}};
3735
            else
3736
                q <= q >> 1;
3737
 
3738
endmodule
3739 40 unneback
`endif
3740 6 unneback
 
3741 40 unneback
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3742
`define MODULE cnt_shreg_ce_clear_wrap
3743
module `BASE`MODULE ( cke, clear, q, rst, clk);
3744
`undef MODULE
3745 6 unneback
 
3746
   parameter length = 4;
3747
   input cke, clear;
3748
   output reg [0:length-1] q;
3749
   input rst;
3750
   input clk;
3751
 
3752
    always @ (posedge clk or posedge rst)
3753
    if (rst)
3754
        q <= {1'b1,{length-1{1'b0}}};
3755
    else
3756
        if (cke)
3757
            if (clear)
3758
                q <= {1'b1,{length-1{1'b0}}};
3759
            else
3760
            q <= {q[length-1],q[0:length-2]};
3761
 
3762
endmodule
3763 40 unneback
`endif
3764 6 unneback
//////////////////////////////////////////////////////////////////////
3765
////                                                              ////
3766
////  Versatile library, memories                                 ////
3767
////                                                              ////
3768
////  Description                                                 ////
3769
////  memories                                                    ////
3770
////                                                              ////
3771
////                                                              ////
3772
////  To Do:                                                      ////
3773
////   - add more memory types                                    ////
3774
////                                                              ////
3775
////  Author(s):                                                  ////
3776
////      - Michael Unneback, unneback@opencores.org              ////
3777
////        ORSoC AB                                              ////
3778
////                                                              ////
3779
//////////////////////////////////////////////////////////////////////
3780
////                                                              ////
3781
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3782
////                                                              ////
3783
//// This source file may be used and distributed without         ////
3784
//// restriction provided that this copyright statement is not    ////
3785
//// removed from the file and that any derivative work contains  ////
3786
//// the original copyright notice and the associated disclaimer. ////
3787
////                                                              ////
3788
//// This source file is free software; you can redistribute it   ////
3789
//// and/or modify it under the terms of the GNU Lesser General   ////
3790
//// Public License as published by the Free Software Foundation; ////
3791
//// either version 2.1 of the License, or (at your option) any   ////
3792
//// later version.                                               ////
3793
////                                                              ////
3794
//// This source is distributed in the hope that it will be       ////
3795
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3796
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3797
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3798
//// details.                                                     ////
3799
////                                                              ////
3800
//// You should have received a copy of the GNU Lesser General    ////
3801
//// Public License along with this source; if not, download it   ////
3802
//// from http://www.opencores.org/lgpl.shtml                     ////
3803
////                                                              ////
3804
//////////////////////////////////////////////////////////////////////
3805
 
3806 40 unneback
`ifdef ROM_INIT
3807 6 unneback
/// ROM
3808 40 unneback
`define MODULE rom_init
3809
module `BASE`MODULE ( adr, q, clk);
3810
`undef MODULE
3811 6 unneback
 
3812 7 unneback
   parameter data_width = 32;
3813
   parameter addr_width = 8;
3814 75 unneback
   parameter mem_size = 1<<addr_width;
3815 7 unneback
   input [(addr_width-1):0]       adr;
3816
   output reg [(data_width-1):0] q;
3817
   input                         clk;
3818 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
3819 7 unneback
   parameter memory_file = "vl_rom.vmem";
3820
   initial
3821
     begin
3822
        $readmemh(memory_file, rom);
3823
     end
3824
 
3825
   always @ (posedge clk)
3826
     q <= rom[adr];
3827 6 unneback
 
3828 7 unneback
endmodule
3829 40 unneback
`endif
3830 7 unneback
 
3831 40 unneback
`ifdef RAM
3832
`define MODULE ram
3833 6 unneback
// Single port RAM
3834 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
3835
`undef MODULE
3836 6 unneback
 
3837
   parameter data_width = 32;
3838
   parameter addr_width = 8;
3839 75 unneback
   parameter mem_size = 1<<addr_width;
3840 100 unneback
   parameter debug = 0;
3841 6 unneback
   input [(data_width-1):0]      d;
3842
   input [(addr_width-1):0]       adr;
3843
   input                         we;
3844 7 unneback
   output reg [(data_width-1):0] q;
3845 6 unneback
   input                         clk;
3846 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
3847 100 unneback
 
3848
    parameter memory_init = 0;
3849
    parameter memory_file = "vl_ram.vmem";
3850
    generate
3851
    if (memory_init == 1) begin : init_mem
3852
        initial
3853
            $readmemh(memory_file, ram);
3854
   end else if (memory_init == 2) begin : init_zero
3855
        integer k;
3856
        initial
3857
            for (k = 0; k < mem_size; k = k + 1)
3858
                ram[k] = 0;
3859 7 unneback
   end
3860
   endgenerate
3861
 
3862 100 unneback
    generate
3863
    if (debug==1) begin : debug_we
3864
        always @ (posedge clk)
3865
        if (we)
3866
            $display ("Value %h written at address %h : time %t", d, adr, $time);
3867
 
3868
    end
3869
    endgenerate
3870
 
3871 6 unneback
   always @ (posedge clk)
3872
   begin
3873
   if (we)
3874
     ram[adr] <= d;
3875
   q <= ram[adr];
3876
   end
3877
 
3878
endmodule
3879 40 unneback
`endif
3880 6 unneback
 
3881 40 unneback
`ifdef RAM_BE
3882
`define MODULE ram_be
3883 91 unneback
module `BASE`MODULE ( d, adr, be, we, q, clk);
3884 40 unneback
`undef MODULE
3885
 
3886 7 unneback
   parameter data_width = 32;
3887 72 unneback
   parameter addr_width = 6;
3888 75 unneback
   parameter mem_size = 1<<addr_width;
3889 7 unneback
   input [(data_width-1):0]      d;
3890
   input [(addr_width-1):0]       adr;
3891 73 unneback
   input [(data_width/8)-1:0]    be;
3892 7 unneback
   input                         we;
3893
   output reg [(data_width-1):0] q;
3894
   input                         clk;
3895
 
3896 85 unneback
 
3897 65 unneback
`ifdef SYSTEMVERILOG
3898 95 unneback
    // use a multi-dimensional packed array
3899
    //t o model individual bytes within the word
3900
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
3901 65 unneback
`else
3902 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
3903
    wire [data_width/8-1:0] cke;
3904 65 unneback
`endif
3905
 
3906 100 unneback
    parameter memory_init = 0;
3907
    parameter memory_file = "vl_ram.vmem";
3908
    generate
3909
    if (memory_init == 1) begin : init_mem
3910
        initial
3911
            $readmemh(memory_file, ram);
3912
    end else if (memory_init == 2) begin : init_zero
3913
        integer k;
3914
        initial
3915
            for (k = 0; k < mem_size; k = k + 1)
3916
                ram[k] = 0;
3917
    end
3918 7 unneback
   endgenerate
3919
 
3920 60 unneback
`ifdef SYSTEMVERILOG
3921
 
3922
always_ff@(posedge clk)
3923
begin
3924 95 unneback
    if(we) begin
3925 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
3926
        if(be[2]) ram[adr][2] <= d[23:16];
3927
        if(be[1]) ram[adr][1] <= d[15:8];
3928
        if(be[0]) ram[adr][0] <= d[7:0];
3929 60 unneback
    end
3930 90 unneback
        q <= ram[adr];
3931 60 unneback
end
3932
 
3933
`else
3934
 
3935 85 unneback
assign cke = {data_width/8{we}} & be;
3936 7 unneback
   genvar i;
3937 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
3938 7 unneback
      always @ (posedge clk)
3939 85 unneback
      if (cke[i])
3940 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3941
   end
3942
   endgenerate
3943
 
3944
   always @ (posedge clk)
3945
      q <= ram[adr];
3946
 
3947 60 unneback
`endif
3948
 
3949 93 unneback
`ifdef verilator
3950 85 unneback
   // Function to access RAM (for use by Verilator).
3951
   function [31:0] get_mem;
3952
      // verilator public
3953 90 unneback
      input [addr_width-1:0]             addr;
3954 85 unneback
      get_mem = ram[addr];
3955
   endfunction // get_mem
3956
 
3957
   // Function to write RAM (for use by Verilator).
3958
   function set_mem;
3959
      // verilator public
3960 90 unneback
      input [addr_width-1:0]             addr;
3961
      input [data_width-1:0]             data;
3962 85 unneback
      ram[addr] = data;
3963
   endfunction // set_mem
3964 93 unneback
`endif
3965 85 unneback
 
3966 7 unneback
endmodule
3967 40 unneback
`endif
3968 7 unneback
 
3969 40 unneback
`ifdef DPRAM_1R1W
3970
`define MODULE dpram_1r1w
3971
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3972
`undef MODULE
3973 6 unneback
   parameter data_width = 32;
3974
   parameter addr_width = 8;
3975 75 unneback
   parameter mem_size = 1<<addr_width;
3976 6 unneback
   input [(data_width-1):0]      d_a;
3977
   input [(addr_width-1):0]       adr_a;
3978
   input [(addr_width-1):0]       adr_b;
3979
   input                         we_a;
3980 118 unneback
   output reg [(data_width-1):0]          q_b;
3981 6 unneback
   input                         clk_a, clk_b;
3982 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
3983 7 unneback
 
3984 100 unneback
    parameter memory_init = 0;
3985
    parameter memory_file = "vl_ram.vmem";
3986
    parameter debug = 0;
3987
 
3988
    generate
3989
    if (memory_init == 1) begin : init_mem
3990
        initial
3991
            $readmemh(memory_file, ram);
3992
    end else if (memory_init == 2) begin : init_zero
3993
        integer k;
3994
        initial
3995
            for (k = 0; k < mem_size; k = k + 1)
3996
                ram[k] = 0;
3997
    end
3998 7 unneback
   endgenerate
3999
 
4000 100 unneback
    generate
4001
    if (debug==1) begin : debug_we
4002
        always @ (posedge clk_a)
4003
        if (we_a)
4004
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4005
 
4006
    end
4007
    endgenerate
4008
 
4009 6 unneback
   always @ (posedge clk_a)
4010
   if (we_a)
4011
     ram[adr_a] <= d_a;
4012 118 unneback
 
4013 6 unneback
   always @ (posedge clk_b)
4014 118 unneback
      q_b = ram[adr_b];
4015 40 unneback
 
4016 6 unneback
endmodule
4017 40 unneback
`endif
4018 6 unneback
 
4019 40 unneback
`ifdef DPRAM_2R1W
4020
`define MODULE dpram_2r1w
4021
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
4022
`undef MODULE
4023
 
4024 6 unneback
   parameter data_width = 32;
4025
   parameter addr_width = 8;
4026 75 unneback
   parameter mem_size = 1<<addr_width;
4027 6 unneback
   input [(data_width-1):0]      d_a;
4028
   input [(addr_width-1):0]       adr_a;
4029
   input [(addr_width-1):0]       adr_b;
4030
   input                         we_a;
4031
   output [(data_width-1):0]      q_b;
4032
   output reg [(data_width-1):0] q_a;
4033
   input                         clk_a, clk_b;
4034
   reg [(data_width-1):0]         q_b;
4035 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4036 7 unneback
 
4037 100 unneback
    parameter memory_init = 0;
4038
    parameter memory_file = "vl_ram.vmem";
4039
    parameter debug = 0;
4040
 
4041
    generate
4042
    if (memory_init == 1) begin : init_mem
4043
        initial
4044
            $readmemh(memory_file, ram);
4045
    end else if (memory_init == 2) begin : init_zero
4046
        integer k;
4047
        initial
4048
            for (k = 0; k < mem_size; k = k + 1)
4049
                ram[k] = 0;
4050
    end
4051 7 unneback
   endgenerate
4052
 
4053 100 unneback
    generate
4054
    if (debug==1) begin : debug_we
4055
        always @ (posedge clk_a)
4056
        if (we_a)
4057
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4058
 
4059
    end
4060
    endgenerate
4061
 
4062 6 unneback
   always @ (posedge clk_a)
4063
     begin
4064
        q_a <= ram[adr_a];
4065
        if (we_a)
4066
             ram[adr_a] <= d_a;
4067
     end
4068
   always @ (posedge clk_b)
4069
          q_b <= ram[adr_b];
4070
endmodule
4071 40 unneback
`endif
4072 6 unneback
 
4073 100 unneback
`ifdef DPRAM_1R2W
4074
`define MODULE dpram_1r2w
4075
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
4076
`undef MODULE
4077
 
4078
   parameter data_width = 32;
4079
   parameter addr_width = 8;
4080
   parameter mem_size = 1<<addr_width;
4081
   input [(data_width-1):0]      d_a;
4082
   input [(addr_width-1):0]       adr_a;
4083
   input [(addr_width-1):0]       adr_b;
4084
   input                         we_a;
4085
   input [(data_width-1):0]       d_b;
4086
   output reg [(data_width-1):0] q_a;
4087
   input                         we_b;
4088
   input                         clk_a, clk_b;
4089
   reg [(data_width-1):0]         q_b;
4090 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4091 100 unneback
 
4092
    parameter memory_init = 0;
4093
    parameter memory_file = "vl_ram.vmem";
4094
    parameter debug = 0;
4095
 
4096
    generate
4097
    if (memory_init == 1) begin : init_mem
4098
        initial
4099
            $readmemh(memory_file, ram);
4100
    end else if (memory_init == 2) begin : init_zero
4101
        integer k;
4102
        initial
4103
            for (k = 0; k < mem_size; k = k + 1)
4104
                ram[k] = 0;
4105
    end
4106
   endgenerate
4107
 
4108
    generate
4109
    if (debug==1) begin : debug_we
4110
        always @ (posedge clk_a)
4111
        if (we_a)
4112
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4113
        always @ (posedge clk_b)
4114
        if (we_b)
4115
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4116
    end
4117
    endgenerate
4118
 
4119
   always @ (posedge clk_a)
4120
     begin
4121
        q_a <= ram[adr_a];
4122
        if (we_a)
4123
             ram[adr_a] <= d_a;
4124
     end
4125
   always @ (posedge clk_b)
4126
     begin
4127
        if (we_b)
4128
          ram[adr_b] <= d_b;
4129
     end
4130
endmodule
4131
`endif
4132
 
4133 40 unneback
`ifdef DPRAM_2R2W
4134
`define MODULE dpram_2r2w
4135
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
4136
`undef MODULE
4137
 
4138 6 unneback
   parameter data_width = 32;
4139
   parameter addr_width = 8;
4140 75 unneback
   parameter mem_size = 1<<addr_width;
4141 6 unneback
   input [(data_width-1):0]      d_a;
4142
   input [(addr_width-1):0]       adr_a;
4143
   input [(addr_width-1):0]       adr_b;
4144
   input                         we_a;
4145
   output [(data_width-1):0]      q_b;
4146
   input [(data_width-1):0]       d_b;
4147
   output reg [(data_width-1):0] q_a;
4148
   input                         we_b;
4149
   input                         clk_a, clk_b;
4150
   reg [(data_width-1):0]         q_b;
4151 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4152 7 unneback
 
4153 100 unneback
    parameter memory_init = 0;
4154
    parameter memory_file = "vl_ram.vmem";
4155
    parameter debug = 0;
4156
 
4157
    generate
4158
    if (memory_init) begin : init_mem
4159
        initial
4160
            $readmemh(memory_file, ram);
4161
    end else if (memory_init == 2) begin : init_zero
4162
        integer k;
4163
        initial
4164
            for (k = 0; k < mem_size; k = k + 1)
4165
                ram[k] = 0;
4166
    end
4167 7 unneback
   endgenerate
4168
 
4169 100 unneback
    generate
4170
    if (debug==1) begin : debug_we
4171
        always @ (posedge clk_a)
4172
        if (we_a)
4173
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4174
        always @ (posedge clk_b)
4175
        if (we_b)
4176
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4177
    end
4178
    endgenerate
4179
 
4180 6 unneback
   always @ (posedge clk_a)
4181
     begin
4182
        q_a <= ram[adr_a];
4183
        if (we_a)
4184
             ram[adr_a] <= d_a;
4185
     end
4186
   always @ (posedge clk_b)
4187
     begin
4188
        q_b <= ram[adr_b];
4189
        if (we_b)
4190
          ram[adr_b] <= d_b;
4191
     end
4192
endmodule
4193 40 unneback
`endif
4194 6 unneback
 
4195 83 unneback
 
4196 75 unneback
`ifdef DPRAM_BE_2R2W
4197
`define MODULE dpram_be_2r2w
4198 92 unneback
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
4199 75 unneback
`undef MODULE
4200
 
4201
   parameter a_data_width = 32;
4202
   parameter a_addr_width = 8;
4203 95 unneback
   parameter b_data_width = 64; //a_data_width;
4204 124 unneback
   //localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
4205
   localparam b_addr_width =
4206
        (a_data_width==b_data_width) ? aw_m :
4207
        (a_data_width==b_data_width*2) ? aw_m+1 :
4208
        (a_data_width==b_data_width*4) ? aw_m+2 :
4209
        (a_data_width==b_data_width*8) ? aw_m+3 :
4210
        (a_data_width==b_data_width*16) ? aw_m+4 :
4211
        (a_data_width==b_data_width*32) ? aw_m+5 :
4212
        (a_data_width==b_data_width/2) ? aw_m-1 :
4213
        (a_data_width==b_data_width/4) ? aw_m-2 :
4214
        (a_data_width==b_data_width/8) ? aw_m-3 :
4215
        (a_data_width==b_data_width/16) ? aw_m-4 :
4216
        (a_data_width==b_data_width/32) ? aw_m-5 : 0;
4217
 
4218 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
4219
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
4220 91 unneback
 
4221 100 unneback
   parameter memory_init = 0;
4222 95 unneback
   parameter memory_file = "vl_ram.vmem";
4223 100 unneback
   parameter debug = 0;
4224 95 unneback
 
4225 75 unneback
   input [(a_data_width-1):0]      d_a;
4226 91 unneback
   input [(a_addr_width-1):0]       adr_a;
4227
   input [(a_data_width/8-1):0]    be_a;
4228
   input                           we_a;
4229 75 unneback
   output reg [(a_data_width-1):0] q_a;
4230 91 unneback
   input [(b_data_width-1):0]       d_b;
4231
   input [(b_addr_width-1):0]       adr_b;
4232 92 unneback
   input [(b_data_width/8-1):0]    be_b;
4233
   input                           we_b;
4234
   output reg [(b_data_width-1):0]          q_b;
4235 91 unneback
   input                           clk_a, clk_b;
4236 75 unneback
 
4237 100 unneback
    generate
4238
    if (debug==1) begin : debug_we
4239
        always @ (posedge clk_a)
4240
        if (we_a)
4241
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4242
        always @ (posedge clk_b)
4243
        if (we_b)
4244
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4245
    end
4246
    endgenerate
4247
 
4248
 
4249 91 unneback
`ifdef SYSTEMVERILOG
4250
// use a multi-dimensional packed array
4251
//to model individual bytes within the word
4252
 
4253 75 unneback
generate
4254 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
4255 75 unneback
 
4256 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4257 95 unneback
 
4258
    initial
4259 100 unneback
        if (memory_init==1)
4260 95 unneback
            $readmemh(memory_file, ram);
4261 100 unneback
 
4262
    integer k;
4263
    initial
4264
        if (memory_init==2)
4265
            for (k = 0; k < mem_size; k = k + 1)
4266
                ram[k] = 0;
4267 91 unneback
 
4268
    always_ff@(posedge clk_a)
4269
    begin
4270
        if(we_a) begin
4271 100 unneback
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
4272
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
4273
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
4274
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
4275 91 unneback
        end
4276
    end
4277
 
4278 92 unneback
    always@(posedge clk_a)
4279
        q_a = ram[adr_a];
4280 91 unneback
 
4281
    always_ff@(posedge clk_b)
4282 92 unneback
    begin
4283
        if(we_b) begin
4284 100 unneback
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
4285
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
4286
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
4287
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
4288 92 unneback
        end
4289
    end
4290 91 unneback
 
4291 92 unneback
    always@(posedge clk_b)
4292
        q_b = ram[adr_b];
4293 91 unneback
 
4294 75 unneback
end
4295
endgenerate
4296
 
4297 95 unneback
generate
4298
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
4299
 
4300 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4301 95 unneback
 
4302
    initial
4303 100 unneback
        if (memory_init==1)
4304 95 unneback
            $readmemh(memory_file, ram);
4305 100 unneback
 
4306
    integer k;
4307
    initial
4308
        if (memory_init==2)
4309
            for (k = 0; k < mem_size; k = k + 1)
4310
                ram[k] = 0;
4311 95 unneback
 
4312
    always_ff@(posedge clk_a)
4313
    begin
4314
        if(we_a) begin
4315
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
4316
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
4317
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
4318
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
4319
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
4320
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
4321
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
4322
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
4323
        end
4324
    end
4325
 
4326
    always@(posedge clk_a)
4327
        q_a = ram[adr_a];
4328
 
4329
    always_ff@(posedge clk_b)
4330
    begin
4331
        if(we_b) begin
4332
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
4333
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
4334
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
4335
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
4336
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
4337
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
4338
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
4339
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
4340
        end
4341
    end
4342
 
4343
    always@(posedge clk_b)
4344
        q_b = ram[adr_b];
4345
 
4346
end
4347
endgenerate
4348
 
4349
generate
4350
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
4351
logic [31:0] temp;
4352
`define MODULE dpram_be_2r2w
4353 111 unneback
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
4354 95 unneback
`undef MODULE
4355
dpram6464 (
4356
    .d_a(d_a),
4357
    .q_a(q_a),
4358
    .adr_a(adr_a),
4359
    .be_a(be_a),
4360
    .we_a(we_a),
4361
    .clk_a(clk_a),
4362
    .d_b({d_b,d_b}),
4363
    .q_b(temp),
4364
    .adr_b(adr_b),
4365
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
4366
    .we_b(we_b),
4367
    .clk_b(clk_b)
4368
);
4369
 
4370 100 unneback
always @ (adr_b[0] or temp)
4371 95 unneback
    if (adr_b[0])
4372
        q_b = temp[31:16];
4373
    else
4374
        q_b = temp[15:0];
4375
 
4376
end
4377
endgenerate
4378
 
4379
generate
4380
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
4381
logic [63:0] temp;
4382
`define MODULE dpram_be_2r2w
4383 111 unneback
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
4384 95 unneback
`undef MODULE
4385
dpram6464 (
4386
    .d_a({d_a,d_a}),
4387
    .q_a(temp),
4388
    .adr_a(adr_a[a_addr_width-1:1]),
4389
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
4390
    .we_a(we_a),
4391
    .clk_a(clk_a),
4392
    .d_b(d_b),
4393
    .q_b(q_b),
4394
    .adr_b(adr_b),
4395
    .be_b(be_b),
4396
    .we_b(we_b),
4397
    .clk_b(clk_b)
4398
);
4399
 
4400 100 unneback
always @ (adr_a[0] or temp)
4401 95 unneback
    if (adr_a[0])
4402
        q_a = temp[63:32];
4403
    else
4404
        q_a = temp[31:0];
4405
 
4406
end
4407
endgenerate
4408
 
4409 91 unneback
`else
4410 92 unneback
    // This modules requires SystemVerilog
4411 98 unneback
    // at this point anyway
4412 91 unneback
`endif
4413 75 unneback
endmodule
4414
`endif
4415
 
4416 91 unneback
`ifdef CAM
4417 6 unneback
// Content addresable memory, CAM
4418 91 unneback
`endif
4419 6 unneback
 
4420 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
4421 6 unneback
// FIFO
4422 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
4423
module `BASE`MODULE (
4424
`undef MODULE
4425 25 unneback
    d, wr, fifo_full,
4426
    q, rd, fifo_empty,
4427
    fill_level,
4428
    clk, rst
4429
    );
4430
 
4431
parameter data_width = 18;
4432
parameter addr_width = 4;
4433 6 unneback
 
4434 25 unneback
// write side
4435
input  [data_width-1:0] d;
4436
input                   wr;
4437
output                  fifo_full;
4438
// read side
4439
output [data_width-1:0] q;
4440
input                   rd;
4441
output                  fifo_empty;
4442
// common
4443
output [addr_width:0]   fill_level;
4444
input rst, clk;
4445
 
4446
wire [addr_width:1] wadr, radr;
4447
 
4448 40 unneback
`define MODULE cnt_bin_ce
4449
`BASE`MODULE
4450 25 unneback
    # ( .length(addr_width))
4451
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
4452 40 unneback
`BASE`MODULE
4453 25 unneback
    # (.length(addr_width))
4454
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
4455 40 unneback
`undef MODULE
4456 25 unneback
 
4457 40 unneback
`define MODULE dpram_1r1w
4458
`BASE`MODULE
4459 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
4460
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
4461 40 unneback
`undef MODULE
4462 25 unneback
 
4463 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
4464
`BASE`MODULE
4465 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
4466 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
4467 40 unneback
`undef MODULE
4468 25 unneback
endmodule
4469 40 unneback
`endif
4470 25 unneback
 
4471 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
4472 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
4473
// RAM is supposed to be larger than the two FIFOs
4474
// LFSR counters used adr pointers
4475 40 unneback
`define MODULE fifo_2r2w_sync_simplex
4476
module `BASE`MODULE (
4477
`undef MODULE
4478 27 unneback
    // a side
4479
    a_d, a_wr, a_fifo_full,
4480
    a_q, a_rd, a_fifo_empty,
4481
    a_fill_level,
4482
    // b side
4483
    b_d, b_wr, b_fifo_full,
4484
    b_q, b_rd, b_fifo_empty,
4485
    b_fill_level,
4486
    // common
4487
    clk, rst
4488
    );
4489
parameter data_width = 8;
4490
parameter addr_width = 5;
4491
parameter fifo_full_level = (1<<addr_width)-1;
4492
 
4493
// a side
4494
input  [data_width-1:0] a_d;
4495
input                   a_wr;
4496
output                  a_fifo_full;
4497
output [data_width-1:0] a_q;
4498
input                   a_rd;
4499
output                  a_fifo_empty;
4500
output [addr_width-1:0] a_fill_level;
4501
 
4502
// b side
4503
input  [data_width-1:0] b_d;
4504
input                   b_wr;
4505
output                  b_fifo_full;
4506
output [data_width-1:0] b_q;
4507
input                   b_rd;
4508
output                  b_fifo_empty;
4509
output [addr_width-1:0] b_fill_level;
4510
 
4511
input                   clk;
4512
input                   rst;
4513
 
4514
// adr_gen
4515
wire [addr_width:1] a_wadr, a_radr;
4516
wire [addr_width:1] b_wadr, b_radr;
4517
// dpram
4518
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4519
 
4520 40 unneback
`define MODULE cnt_lfsr_ce
4521
`BASE`MODULE
4522 27 unneback
    # ( .length(addr_width))
4523
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
4524
 
4525 40 unneback
`BASE`MODULE
4526 27 unneback
    # (.length(addr_width))
4527
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
4528
 
4529 40 unneback
`BASE`MODULE
4530 27 unneback
    # ( .length(addr_width))
4531
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
4532
 
4533 40 unneback
`BASE`MODULE
4534 27 unneback
    # (.length(addr_width))
4535
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
4536 40 unneback
`undef MODULE
4537 27 unneback
 
4538
// mux read or write adr to DPRAM
4539
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
4540
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
4541
 
4542 40 unneback
`define MODULE dpram_2r2w
4543
`BASE`MODULE
4544 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
4545
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4546
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4547 40 unneback
`undef MODULE
4548
 
4549
`define MODULE cnt_bin_ce_rew_zq_l1
4550
`BASE`MODULE
4551 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
4552 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
4553
 
4554 40 unneback
`BASE`MODULE
4555 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
4556 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
4557 40 unneback
`undef MODULE
4558 27 unneback
 
4559
endmodule
4560 40 unneback
`endif
4561 27 unneback
 
4562 40 unneback
`ifdef FIFO_CMP_ASYNC
4563
`define MODULE fifo_cmp_async
4564
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
4565
`undef MODULE
4566 6 unneback
 
4567 11 unneback
   parameter addr_width = 4;
4568
   parameter N = addr_width-1;
4569 6 unneback
 
4570
   parameter Q1 = 2'b00;
4571
   parameter Q2 = 2'b01;
4572
   parameter Q3 = 2'b11;
4573
   parameter Q4 = 2'b10;
4574
 
4575
   parameter going_empty = 1'b0;
4576
   parameter going_full  = 1'b1;
4577
 
4578
   input [N:0]  wptr, rptr;
4579 14 unneback
   output       fifo_empty;
4580 6 unneback
   output       fifo_full;
4581
   input        wclk, rclk, rst;
4582
 
4583
`ifndef GENERATE_DIRECTION_AS_LATCH
4584
   wire direction;
4585
`endif
4586
`ifdef GENERATE_DIRECTION_AS_LATCH
4587
   reg direction;
4588
`endif
4589
   reg  direction_set, direction_clr;
4590
 
4591
   wire async_empty, async_full;
4592
   wire fifo_full2;
4593 14 unneback
   wire fifo_empty2;
4594 6 unneback
 
4595
   // direction_set
4596
   always @ (wptr[N:N-1] or rptr[N:N-1])
4597
     case ({wptr[N:N-1],rptr[N:N-1]})
4598
       {Q1,Q2} : direction_set <= 1'b1;
4599
       {Q2,Q3} : direction_set <= 1'b1;
4600
       {Q3,Q4} : direction_set <= 1'b1;
4601
       {Q4,Q1} : direction_set <= 1'b1;
4602
       default : direction_set <= 1'b0;
4603
     endcase
4604
 
4605
   // direction_clear
4606
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
4607
     if (rst)
4608
       direction_clr <= 1'b1;
4609
     else
4610
       case ({wptr[N:N-1],rptr[N:N-1]})
4611
         {Q2,Q1} : direction_clr <= 1'b1;
4612
         {Q3,Q2} : direction_clr <= 1'b1;
4613
         {Q4,Q3} : direction_clr <= 1'b1;
4614
         {Q1,Q4} : direction_clr <= 1'b1;
4615
         default : direction_clr <= 1'b0;
4616
       endcase
4617
 
4618 40 unneback
`define MODULE dff_sr
4619 6 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
4620 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
4621 6 unneback
`endif
4622
 
4623
`ifdef GENERATE_DIRECTION_AS_LATCH
4624
   always @ (posedge direction_set or posedge direction_clr)
4625
     if (direction_clr)
4626
       direction <= going_empty;
4627
     else
4628
       direction <= going_full;
4629
`endif
4630
 
4631
   assign async_empty = (wptr == rptr) && (direction==going_empty);
4632
   assign async_full  = (wptr == rptr) && (direction==going_full);
4633
 
4634 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
4635
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
4636
`undef MODULE
4637 6 unneback
 
4638
/*
4639
   always @ (posedge wclk or posedge rst or posedge async_full)
4640
     if (rst)
4641
       {fifo_full, fifo_full2} <= 2'b00;
4642
     else if (async_full)
4643
       {fifo_full, fifo_full2} <= 2'b11;
4644
     else
4645
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
4646
*/
4647 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
4648 6 unneback
     if (async_empty)
4649
       {fifo_empty, fifo_empty2} <= 2'b11;
4650
     else
4651 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
4652 40 unneback
`define MODULE dff
4653
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
4654
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
4655
`undef MODULE
4656 27 unneback
endmodule // async_compb
4657 40 unneback
`endif
4658 6 unneback
 
4659 40 unneback
`ifdef FIFO_1R1W_ASYNC
4660
`define MODULE fifo_1r1w_async
4661
module `BASE`MODULE (
4662
`undef MODULE
4663 6 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
4664
    q, rd, fifo_empty, rd_clk, rd_rst
4665
    );
4666
 
4667
parameter data_width = 18;
4668
parameter addr_width = 4;
4669
 
4670
// write side
4671
input  [data_width-1:0] d;
4672
input                   wr;
4673
output                  fifo_full;
4674
input                   wr_clk;
4675
input                   wr_rst;
4676
// read side
4677
output [data_width-1:0] q;
4678
input                   rd;
4679
output                  fifo_empty;
4680
input                   rd_clk;
4681
input                   rd_rst;
4682
 
4683
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
4684 23 unneback
 
4685 40 unneback
`define MODULE cnt_gray_ce_bin
4686
`BASE`MODULE
4687 6 unneback
    # ( .length(addr_width))
4688
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
4689
 
4690 40 unneback
`BASE`MODULE
4691 6 unneback
    # (.length(addr_width))
4692 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
4693 40 unneback
`undef MODULE
4694 6 unneback
 
4695 40 unneback
`define MODULE dpram_1r1w
4696
`BASE`MODULE
4697 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
4698
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
4699 40 unneback
`undef MODULE
4700 6 unneback
 
4701 40 unneback
`define MODULE fifo_cmp_async
4702
`BASE`MODULE
4703 6 unneback
    # (.addr_width(addr_width))
4704
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
4705 40 unneback
`undef MODULE
4706 6 unneback
 
4707
endmodule
4708 40 unneback
`endif
4709 6 unneback
 
4710 40 unneback
`ifdef FIFO_2R2W_ASYNC
4711
`define MODULE fifo_2r2w_async
4712
module `BASE`MODULE (
4713
`undef MODULE
4714 6 unneback
    // a side
4715
    a_d, a_wr, a_fifo_full,
4716
    a_q, a_rd, a_fifo_empty,
4717
    a_clk, a_rst,
4718
    // b side
4719
    b_d, b_wr, b_fifo_full,
4720
    b_q, b_rd, b_fifo_empty,
4721
    b_clk, b_rst
4722
    );
4723
 
4724
parameter data_width = 18;
4725
parameter addr_width = 4;
4726
 
4727
// a side
4728
input  [data_width-1:0] a_d;
4729
input                   a_wr;
4730
output                  a_fifo_full;
4731
output [data_width-1:0] a_q;
4732
input                   a_rd;
4733
output                  a_fifo_empty;
4734
input                   a_clk;
4735
input                   a_rst;
4736
 
4737
// b side
4738
input  [data_width-1:0] b_d;
4739
input                   b_wr;
4740
output                  b_fifo_full;
4741
output [data_width-1:0] b_q;
4742
input                   b_rd;
4743
output                  b_fifo_empty;
4744
input                   b_clk;
4745
input                   b_rst;
4746
 
4747 40 unneback
`define MODULE fifo_1r1w_async
4748
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4749 6 unneback
vl_fifo_1r1w_async_a (
4750
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4751
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4752
    );
4753
 
4754 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4755 6 unneback
vl_fifo_1r1w_async_b (
4756
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4757
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4758
    );
4759 40 unneback
`undef MODULE
4760
 
4761 6 unneback
endmodule
4762 40 unneback
`endif
4763 6 unneback
 
4764 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4765
`define MODULE fifo_2r2w_async_simplex
4766
module `BASE`MODULE (
4767
`undef MODULE
4768 6 unneback
    // a side
4769
    a_d, a_wr, a_fifo_full,
4770
    a_q, a_rd, a_fifo_empty,
4771
    a_clk, a_rst,
4772
    // b side
4773
    b_d, b_wr, b_fifo_full,
4774
    b_q, b_rd, b_fifo_empty,
4775
    b_clk, b_rst
4776
    );
4777
 
4778
parameter data_width = 18;
4779
parameter addr_width = 4;
4780
 
4781
// a side
4782
input  [data_width-1:0] a_d;
4783
input                   a_wr;
4784
output                  a_fifo_full;
4785
output [data_width-1:0] a_q;
4786
input                   a_rd;
4787
output                  a_fifo_empty;
4788
input                   a_clk;
4789
input                   a_rst;
4790
 
4791
// b side
4792
input  [data_width-1:0] b_d;
4793
input                   b_wr;
4794
output                  b_fifo_full;
4795
output [data_width-1:0] b_q;
4796
input                   b_rd;
4797
output                  b_fifo_empty;
4798
input                   b_clk;
4799
input                   b_rst;
4800
 
4801
// adr_gen
4802
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4803
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4804
// dpram
4805
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4806
 
4807 40 unneback
`define MODULE cnt_gray_ce_bin
4808
`BASE`MODULE
4809 6 unneback
    # ( .length(addr_width))
4810
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4811
 
4812 40 unneback
`BASE`MODULE
4813 6 unneback
    # (.length(addr_width))
4814
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4815
 
4816 40 unneback
`BASE`MODULE
4817 6 unneback
    # ( .length(addr_width))
4818
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4819
 
4820 40 unneback
`BASE`MODULE
4821 6 unneback
    # (.length(addr_width))
4822
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4823 40 unneback
`undef MODULE
4824 6 unneback
 
4825
// mux read or write adr to DPRAM
4826
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4827
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4828
 
4829 40 unneback
`define MODULE dpram_2r2w
4830
`BASE`MODULE
4831 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
4832
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4833
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4834 40 unneback
`undef MODULE
4835 6 unneback
 
4836 40 unneback
`define MODULE fifo_cmp_async
4837
`BASE`MODULE
4838 6 unneback
    # (.addr_width(addr_width))
4839
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4840
 
4841 40 unneback
`BASE`MODULE
4842 6 unneback
    # (.addr_width(addr_width))
4843
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4844 40 unneback
`undef MODULE
4845 6 unneback
 
4846
endmodule
4847 40 unneback
`endif
4848 48 unneback
 
4849
`ifdef REG_FILE
4850
`define MODULE reg_file
4851
module `BASE`MODULE (
4852
`undef MODULE
4853
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4854
);
4855
parameter data_width = 32;
4856
parameter addr_width = 5;
4857
input [addr_width-1:0] a1, a2, a3;
4858
input [data_width-1:0] wd3;
4859
input we3;
4860
output [data_width-1:0] rd1, rd2;
4861
input clk;
4862
 
4863
`ifdef ACTEL
4864
reg [data_width-1:0] wd3_reg;
4865
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4866
reg we3_reg;
4867 98 unneback
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
4868
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
4869 48 unneback
always @ (posedge clk or posedge rst)
4870
if (rst)
4871
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4872
else
4873
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4874
 
4875
    always @ (negedge clk)
4876
    if (we3_reg)
4877
        ram1[a3_reg] <= wd3;
4878
    always @ (posedge clk)
4879
        a1_reg <= a1;
4880
    assign rd1 = ram1[a1_reg];
4881
 
4882
    always @ (negedge clk)
4883
    if (we3_reg)
4884
        ram2[a3_reg] <= wd3;
4885
    always @ (posedge clk)
4886
        a2_reg <= a2;
4887
    assign rd2 = ram2[a2_reg];
4888
 
4889
`else
4890
 
4891
`define MODULE dpram_1r1w
4892
`BASE`MODULE
4893
    # ( .data_width(data_width), .addr_width(addr_width))
4894
    ram1 (
4895
        .d_a(wd3),
4896
        .adr_a(a3),
4897
        .we_a(we3),
4898
        .clk_a(clk),
4899
        .q_b(rd1),
4900
        .adr_b(a1),
4901
        .clk_b(clk) );
4902
 
4903
`BASE`MODULE
4904
    # ( .data_width(data_width), .addr_width(addr_width))
4905
    ram2 (
4906
        .d_a(wd3),
4907
        .adr_a(a3),
4908
        .we_a(we3),
4909
        .clk_a(clk),
4910
        .q_b(rd2),
4911
        .adr_b(a2),
4912
        .clk_b(clk) );
4913
`undef MODULE
4914
 
4915
`endif
4916
 
4917
endmodule
4918
`endif
4919 12 unneback
//////////////////////////////////////////////////////////////////////
4920
////                                                              ////
4921
////  Versatile library, wishbone stuff                           ////
4922
////                                                              ////
4923
////  Description                                                 ////
4924
////  Wishbone compliant modules                                  ////
4925
////                                                              ////
4926
////                                                              ////
4927
////  To Do:                                                      ////
4928
////   -                                                          ////
4929
////                                                              ////
4930
////  Author(s):                                                  ////
4931
////      - Michael Unneback, unneback@opencores.org              ////
4932
////        ORSoC AB                                              ////
4933
////                                                              ////
4934
//////////////////////////////////////////////////////////////////////
4935
////                                                              ////
4936
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4937
////                                                              ////
4938
//// This source file may be used and distributed without         ////
4939
//// restriction provided that this copyright statement is not    ////
4940
//// removed from the file and that any derivative work contains  ////
4941
//// the original copyright notice and the associated disclaimer. ////
4942
////                                                              ////
4943
//// This source file is free software; you can redistribute it   ////
4944
//// and/or modify it under the terms of the GNU Lesser General   ////
4945
//// Public License as published by the Free Software Foundation; ////
4946
//// either version 2.1 of the License, or (at your option) any   ////
4947
//// later version.                                               ////
4948
////                                                              ////
4949
//// This source is distributed in the hope that it will be       ////
4950
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4951
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4952
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4953
//// details.                                                     ////
4954
////                                                              ////
4955
//// You should have received a copy of the GNU Lesser General    ////
4956
//// Public License along with this source; if not, download it   ////
4957
//// from http://www.opencores.org/lgpl.shtml                     ////
4958
////                                                              ////
4959
//////////////////////////////////////////////////////////////////////
4960
 
4961 75 unneback
`ifdef WB_ADR_INC
4962
`timescale 1ns/1ns
4963
`define MODULE wb_adr_inc
4964 85 unneback
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
4965 75 unneback
`undef MODULE
4966 83 unneback
parameter adr_width = 10;
4967
parameter max_burst_width = 4;
4968 85 unneback
input cyc_i, stb_i, we_i;
4969 83 unneback
input [2:0] cti_i;
4970
input [1:0] bte_i;
4971
input [adr_width-1:0] adr_i;
4972
output [adr_width-1:0] adr_o;
4973
output ack_o;
4974
input clk, rst;
4975 75 unneback
 
4976 83 unneback
reg [adr_width-1:0] adr;
4977 90 unneback
wire [max_burst_width-1:0] to_adr;
4978 91 unneback
reg [max_burst_width-1:0] last_adr;
4979 92 unneback
reg last_cycle;
4980
localparam idle_or_eoc = 1'b0;
4981
localparam cyc_or_ws   = 1'b1;
4982 90 unneback
 
4983 91 unneback
always @ (posedge clk or posedge rst)
4984
if (rst)
4985
    last_adr <= {max_burst_width{1'b0}};
4986
else
4987
    if (stb_i)
4988 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
4989 91 unneback
 
4990 83 unneback
generate
4991
if (max_burst_width==0) begin : inst_0
4992 97 unneback
 
4993
        reg ack_o;
4994
        assign adr_o = adr_i;
4995
        always @ (posedge clk or posedge rst)
4996
        if (rst)
4997
            ack_o <= 1'b0;
4998
        else
4999
            ack_o <= cyc_i & stb_i & !ack_o;
5000
 
5001 83 unneback
end else begin
5002
 
5003
    always @ (posedge clk or posedge rst)
5004
    if (rst)
5005 92 unneback
        last_cycle <= idle_or_eoc;
5006 83 unneback
    else
5007 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
5008
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
5009
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
5010
                      cyc_or_ws; // cyc
5011
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
5012 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
5013 91 unneback
                                        (!stb_i) ? last_adr :
5014 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
5015 85 unneback
                                        adr[max_burst_width-1:0];
5016 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
5017 97 unneback
 
5018 83 unneback
end
5019
endgenerate
5020
 
5021
generate
5022
if (max_burst_width==2) begin : inst_2
5023
    always @ (posedge clk or posedge rst)
5024
    if (rst)
5025
        adr <= 2'h0;
5026
    else
5027
        if (cyc_i & stb_i)
5028
            adr[1:0] <= to_adr[1:0] + 2'd1;
5029 75 unneback
        else
5030 83 unneback
            adr <= to_adr[1:0];
5031
end
5032
endgenerate
5033
 
5034
generate
5035
if (max_burst_width==3) begin : inst_3
5036
    always @ (posedge clk or posedge rst)
5037
    if (rst)
5038
        adr <= 3'h0;
5039
    else
5040
        if (cyc_i & stb_i)
5041
            case (bte_i)
5042
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
5043
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
5044 75 unneback
            endcase
5045 83 unneback
        else
5046
            adr <= to_adr[2:0];
5047
end
5048
endgenerate
5049
 
5050
generate
5051
if (max_burst_width==4) begin : inst_4
5052
    always @ (posedge clk or posedge rst)
5053
    if (rst)
5054
        adr <= 4'h0;
5055
    else
5056 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
5057 83 unneback
            case (bte_i)
5058
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
5059
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
5060
            default: adr[3:0] <= to_adr + 4'd1;
5061
            endcase
5062
        else
5063
            adr <= to_adr[3:0];
5064
end
5065
endgenerate
5066
 
5067
generate
5068
if (adr_width > max_burst_width) begin : pass_through
5069
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
5070
end
5071
endgenerate
5072
 
5073
endmodule
5074 75 unneback
`endif
5075
 
5076 105 unneback
`ifdef WB_B4_EOC
5077
`define MODULE wb_b4_eoc
5078
module `BASE`MODULE ( cyc_i, stb_i, stall_o, ack_o, busy, eoc, clk, rst);
5079
`undef MODULE
5080
input cyc_i, stb_i, ack_o;
5081
output busy, eoc;
5082
input clk, rst;
5083
 
5084
`define MODULE cnt_bin_ce_rew_zq_l1
5085
`BASE`MODULE # ( .length(4), level1_value(1))
5086
cnt0 (
5087
    .cke(), .rew(), .zq(), .level1(), .rst(), clk);
5088
`undef MODULE
5089
 
5090
endmodule
5091
`endif
5092
 
5093 40 unneback
`ifdef WB3WB3_BRIDGE
5094 12 unneback
// async wb3 - wb3 bridge
5095
`timescale 1ns/1ns
5096 40 unneback
`define MODULE wb3wb3_bridge
5097
module `BASE`MODULE (
5098
`undef MODULE
5099 12 unneback
        // wishbone slave side
5100
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5101
        // wishbone master side
5102
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
5103
 
5104 95 unneback
parameter style = "FIFO"; // valid: simple, FIFO
5105
parameter addr_width = 4;
5106
 
5107 12 unneback
input [31:0] wbs_dat_i;
5108
input [31:2] wbs_adr_i;
5109
input [3:0]  wbs_sel_i;
5110
input [1:0]  wbs_bte_i;
5111
input [2:0]  wbs_cti_i;
5112
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
5113
output [31:0] wbs_dat_o;
5114 14 unneback
output wbs_ack_o;
5115 12 unneback
input wbs_clk, wbs_rst;
5116
 
5117
output [31:0] wbm_dat_o;
5118
output reg [31:2] wbm_adr_o;
5119
output [3:0]  wbm_sel_o;
5120
output reg [1:0]  wbm_bte_o;
5121
output reg [2:0]  wbm_cti_o;
5122 14 unneback
output reg wbm_we_o;
5123
output wbm_cyc_o;
5124 12 unneback
output wbm_stb_o;
5125
input [31:0]  wbm_dat_i;
5126
input wbm_ack_i;
5127
input wbm_clk, wbm_rst;
5128
 
5129
// bte
5130
parameter linear       = 2'b00;
5131
parameter wrap4        = 2'b01;
5132
parameter wrap8        = 2'b10;
5133
parameter wrap16       = 2'b11;
5134
// cti
5135
parameter classic      = 3'b000;
5136
parameter incburst     = 3'b010;
5137
parameter endofburst   = 3'b111;
5138
 
5139 95 unneback
localparam wbs_adr  = 1'b0;
5140
localparam wbs_data = 1'b1;
5141 12 unneback
 
5142 95 unneback
localparam wbm_adr0      = 2'b00;
5143
localparam wbm_adr1      = 2'b01;
5144
localparam wbm_data      = 2'b10;
5145
localparam wbm_data_wait = 2'b11;
5146 12 unneback
 
5147
reg [1:0] wbs_bte_reg;
5148
reg wbs;
5149
wire wbs_eoc_alert, wbm_eoc_alert;
5150
reg wbs_eoc, wbm_eoc;
5151
reg [1:0] wbm;
5152
 
5153 14 unneback
wire [1:16] wbs_count, wbm_count;
5154 12 unneback
 
5155
wire [35:0] a_d, a_q, b_d, b_q;
5156
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
5157
reg a_rd_reg;
5158
wire b_rd_adr, b_rd_data;
5159 14 unneback
wire b_rd_data_reg;
5160
wire [35:0] temp;
5161 12 unneback
 
5162
`define WE 5
5163
`define BTE 4:3
5164
`define CTI 2:0
5165
 
5166
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
5167
always @ (posedge wbs_clk or posedge wbs_rst)
5168
if (wbs_rst)
5169
        wbs_eoc <= 1'b0;
5170
else
5171
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
5172 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
5173 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
5174
                wbs_eoc <= 1'b1;
5175
 
5176 40 unneback
`define MODULE cnt_shreg_ce_clear
5177
`BASE`MODULE # ( .length(16))
5178
`undef MODULE
5179 12 unneback
    cnt0 (
5180
        .cke(wbs_ack_o),
5181
        .clear(wbs_eoc),
5182
        .q(wbs_count),
5183
        .rst(wbs_rst),
5184
        .clk(wbs_clk));
5185
 
5186
always @ (posedge wbs_clk or posedge wbs_rst)
5187
if (wbs_rst)
5188
        wbs <= wbs_adr;
5189
else
5190 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
5191 12 unneback
                wbs <= wbs_data;
5192
        else if (wbs_eoc & wbs_ack_o)
5193
                wbs <= wbs_adr;
5194
 
5195
// wbs FIFO
5196 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
5197
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
5198 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
5199
              1'b0;
5200
assign a_rd = !a_fifo_empty;
5201
always @ (posedge wbs_clk or posedge wbs_rst)
5202
if (wbs_rst)
5203
        a_rd_reg <= 1'b0;
5204
else
5205
        a_rd_reg <= a_rd;
5206
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
5207
 
5208
assign wbs_dat_o = a_q[35:4];
5209
 
5210
always @ (posedge wbs_clk or posedge wbs_rst)
5211
if (wbs_rst)
5212 13 unneback
        wbs_bte_reg <= 2'b00;
5213 12 unneback
else
5214 13 unneback
        wbs_bte_reg <= wbs_bte_i;
5215 12 unneback
 
5216
// wbm FIFO
5217
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
5218
always @ (posedge wbm_clk or posedge wbm_rst)
5219
if (wbm_rst)
5220
        wbm_eoc <= 1'b0;
5221
else
5222
        if (wbm==wbm_adr0 & !b_fifo_empty)
5223
                wbm_eoc <= b_q[`BTE] == linear;
5224
        else if (wbm_eoc_alert & wbm_ack_i)
5225
                wbm_eoc <= 1'b1;
5226
 
5227
always @ (posedge wbm_clk or posedge wbm_rst)
5228
if (wbm_rst)
5229
        wbm <= wbm_adr0;
5230
else
5231 33 unneback
/*
5232 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
5233
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
5234
        (wbm==wbm_adr1 & !wbm_we_o) |
5235
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
5236
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
5237 33 unneback
*/
5238
    case (wbm)
5239
    wbm_adr0:
5240
        if (!b_fifo_empty)
5241
            wbm <= wbm_adr1;
5242
    wbm_adr1:
5243
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
5244
            wbm <= wbm_data;
5245
    wbm_data:
5246
        if (wbm_ack_i & wbm_eoc)
5247
            wbm <= wbm_adr0;
5248
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
5249
            wbm <= wbm_data_wait;
5250
    wbm_data_wait:
5251
        if (!b_fifo_empty)
5252
            wbm <= wbm_data;
5253
    endcase
5254 12 unneback
 
5255
assign b_d = {wbm_dat_i,4'b1111};
5256
assign b_wr = !wbm_we_o & wbm_ack_i;
5257
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
5258
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
5259
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
5260 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
5261 12 unneback
                   1'b0;
5262
assign b_rd = b_rd_adr | b_rd_data;
5263
 
5264 40 unneback
`define MODULE dff
5265
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
5266
`undef MODULE
5267
`define MODULE dff_ce
5268
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
5269
`undef MODULE
5270 12 unneback
 
5271
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
5272
 
5273 40 unneback
`define MODULE cnt_shreg_ce_clear
5274 42 unneback
`BASE`MODULE # ( .length(16))
5275 40 unneback
`undef MODULE
5276 12 unneback
    cnt1 (
5277
        .cke(wbm_ack_i),
5278
        .clear(wbm_eoc),
5279
        .q(wbm_count),
5280
        .rst(wbm_rst),
5281
        .clk(wbm_clk));
5282
 
5283 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
5284
assign wbm_stb_o = (wbm==wbm_data);
5285 12 unneback
 
5286
always @ (posedge wbm_clk or posedge wbm_rst)
5287
if (wbm_rst)
5288
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
5289
else begin
5290
        if (wbm==wbm_adr0 & !b_fifo_empty)
5291
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
5292
        else if (wbm_eoc_alert & wbm_ack_i)
5293
                wbm_cti_o <= endofburst;
5294
end
5295
 
5296
//async_fifo_dw_simplex_top
5297 40 unneback
`define MODULE fifo_2r2w_async_simplex
5298
`BASE`MODULE
5299
`undef MODULE
5300 12 unneback
# ( .data_width(36), .addr_width(addr_width))
5301
fifo (
5302
    // a side
5303
    .a_d(a_d),
5304
    .a_wr(a_wr),
5305
    .a_fifo_full(a_fifo_full),
5306
    .a_q(a_q),
5307
    .a_rd(a_rd),
5308
    .a_fifo_empty(a_fifo_empty),
5309
    .a_clk(wbs_clk),
5310
    .a_rst(wbs_rst),
5311
    // b side
5312
    .b_d(b_d),
5313
    .b_wr(b_wr),
5314
    .b_fifo_full(b_fifo_full),
5315
    .b_q(b_q),
5316
    .b_rd(b_rd),
5317
    .b_fifo_empty(b_fifo_empty),
5318
    .b_clk(wbm_clk),
5319
    .b_rst(wbm_rst)
5320
    );
5321
 
5322
endmodule
5323 40 unneback
`undef WE
5324
`undef BTE
5325
`undef CTI
5326
`endif
5327 17 unneback
 
5328 75 unneback
`ifdef WB3AVALON_BRIDGE
5329
`define MODULE wb3avalon_bridge
5330
module `BASE`MODULE (
5331
`undef MODULE
5332
        // wishbone slave side
5333
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5334 77 unneback
        // avalon master side
5335 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
5336
 
5337 85 unneback
parameter linewrapburst = 1'b0;
5338
 
5339 75 unneback
input [31:0] wbs_dat_i;
5340
input [31:2] wbs_adr_i;
5341
input [3:0]  wbs_sel_i;
5342
input [1:0]  wbs_bte_i;
5343
input [2:0]  wbs_cti_i;
5344 83 unneback
input wbs_we_i;
5345
input wbs_cyc_i;
5346
input wbs_stb_i;
5347 75 unneback
output [31:0] wbs_dat_o;
5348
output wbs_ack_o;
5349
input wbs_clk, wbs_rst;
5350
 
5351
input [31:0] readdata;
5352
output [31:0] writedata;
5353
output [31:2] address;
5354
output [3:0]  be;
5355
output write;
5356 81 unneback
output read;
5357 75 unneback
output beginbursttransfer;
5358
output [3:0] burstcount;
5359
input readdatavalid;
5360
input waitrequest;
5361
input clk;
5362
input rst;
5363
 
5364
wire [1:0] wbm_bte_o;
5365
wire [2:0] wbm_cti_o;
5366
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
5367
reg last_cyc;
5368 79 unneback
reg [3:0] counter;
5369 82 unneback
reg read_busy;
5370 75 unneback
 
5371
always @ (posedge clk or posedge rst)
5372
if (rst)
5373
    last_cyc <= 1'b0;
5374
else
5375
    last_cyc <= wbm_cyc_o;
5376
 
5377 79 unneback
always @ (posedge clk or posedge rst)
5378
if (rst)
5379 82 unneback
    read_busy <= 1'b0;
5380 79 unneback
else
5381 82 unneback
    if (read & !waitrequest)
5382
        read_busy <= 1'b1;
5383
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
5384
        read_busy <= 1'b0;
5385
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
5386 81 unneback
 
5387 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
5388
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
5389
                    (wbm_bte_o==2'b10) ? 4'd8 :
5390 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
5391
                    4'd1;
5392 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
5393 75 unneback
 
5394 79 unneback
always @ (posedge clk or posedge rst)
5395
if (rst) begin
5396
    counter <= 4'd0;
5397
end else
5398 80 unneback
    if (wbm_we_o) begin
5399
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
5400 85 unneback
            counter <= burstcount -4'd1;
5401 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
5402
            counter <= burstcount;
5403
        end else if (!waitrequest & wbm_stb_o) begin
5404
            counter <= counter - 4'd1;
5405
        end
5406 82 unneback
    end
5407 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
5408 79 unneback
 
5409 75 unneback
`define MODULE wb3wb3_bridge
5410 77 unneback
`BASE`MODULE wbwb3inst (
5411 75 unneback
`undef MODULE
5412
    // wishbone slave side
5413
    .wbs_dat_i(wbs_dat_i),
5414
    .wbs_adr_i(wbs_adr_i),
5415
    .wbs_sel_i(wbs_sel_i),
5416
    .wbs_bte_i(wbs_bte_i),
5417
    .wbs_cti_i(wbs_cti_i),
5418
    .wbs_we_i(wbs_we_i),
5419
    .wbs_cyc_i(wbs_cyc_i),
5420
    .wbs_stb_i(wbs_stb_i),
5421
    .wbs_dat_o(wbs_dat_o),
5422
    .wbs_ack_o(wbs_ack_o),
5423
    .wbs_clk(wbs_clk),
5424
    .wbs_rst(wbs_rst),
5425
    // wishbone master side
5426
    .wbm_dat_o(writedata),
5427 78 unneback
    .wbm_adr_o(address),
5428 75 unneback
    .wbm_sel_o(be),
5429
    .wbm_bte_o(wbm_bte_o),
5430
    .wbm_cti_o(wbm_cti_o),
5431
    .wbm_we_o(wbm_we_o),
5432
    .wbm_cyc_o(wbm_cyc_o),
5433
    .wbm_stb_o(wbm_stb_o),
5434
    .wbm_dat_i(readdata),
5435
    .wbm_ack_i(wbm_ack_i),
5436
    .wbm_clk(clk),
5437
    .wbm_rst(rst));
5438
 
5439
 
5440
endmodule
5441
`endif
5442
 
5443 105 unneback
`ifdef WB_ARBITER
5444
`define MODULE wb_arbiter
5445 42 unneback
module `BASE`MODULE (
5446 40 unneback
`undef MODULE
5447 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5448 105 unneback
    wbm_dat_i, wbm_stall_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
5449 39 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5450 105 unneback
    wbs_dat_o, wbs_stall_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
5451 39 unneback
    wb_clk, wb_rst
5452
);
5453
 
5454
parameter nr_of_ports = 3;
5455
parameter adr_size = 26;
5456
parameter adr_lo   = 2;
5457
parameter dat_size = 32;
5458
parameter sel_size = dat_size/8;
5459
 
5460
localparam aw = (adr_size - adr_lo) * nr_of_ports;
5461
localparam dw = dat_size * nr_of_ports;
5462
localparam sw = sel_size * nr_of_ports;
5463
localparam cw = 3 * nr_of_ports;
5464
localparam bw = 2 * nr_of_ports;
5465
 
5466
input  [dw-1:0] wbm_dat_o;
5467
input  [aw-1:0] wbm_adr_o;
5468
input  [sw-1:0] wbm_sel_o;
5469
input  [cw-1:0] wbm_cti_o;
5470
input  [bw-1:0] wbm_bte_o;
5471
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
5472
output [dw-1:0] wbm_dat_i;
5473 105 unneback
output [nr_of_ports-1:0] wbm_stall_o, wbm_ack_i, wbm_err_i, wbm_rty_i;
5474 39 unneback
 
5475
output [dat_size-1:0] wbs_dat_i;
5476
output [adr_size-1:adr_lo] wbs_adr_i;
5477
output [sel_size-1:0] wbs_sel_i;
5478
output [2:0] wbs_cti_i;
5479
output [1:0] wbs_bte_i;
5480
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
5481
input  [dat_size-1:0] wbs_dat_o;
5482 105 unneback
input  wbs_stall_o, wbs_ack_o, wbs_err_o, wbs_rty_o;
5483 39 unneback
 
5484
input wb_clk, wb_rst;
5485
 
5486 44 unneback
reg  [nr_of_ports-1:0] select;
5487 39 unneback
wire [nr_of_ports-1:0] state;
5488
wire [nr_of_ports-1:0] eoc; // end-of-cycle
5489
wire [nr_of_ports-1:0] sel;
5490
wire idle;
5491
 
5492
genvar i;
5493
 
5494
assign idle = !(|state);
5495
 
5496
generate
5497
if (nr_of_ports == 2) begin
5498
 
5499
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
5500
 
5501
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5502
 
5503 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5504
 
5505
    always @ (idle or wbm_cyc_o)
5506
    if (idle)
5507
        casex (wbm_cyc_o)
5508
        2'b1x : select = 2'b10;
5509
        2'b01 : select = 2'b01;
5510
        default : select = {nr_of_ports{1'b0}};
5511
        endcase
5512
    else
5513
        select = {nr_of_ports{1'b0}};
5514
 
5515 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5516
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5517
 
5518
end
5519
endgenerate
5520
 
5521
generate
5522
if (nr_of_ports == 3) begin
5523
 
5524
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5525
 
5526
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5527
 
5528 44 unneback
    always @ (idle or wbm_cyc_o)
5529
    if (idle)
5530
        casex (wbm_cyc_o)
5531
        3'b1xx : select = 3'b100;
5532
        3'b01x : select = 3'b010;
5533
        3'b001 : select = 3'b001;
5534
        default : select = {nr_of_ports{1'b0}};
5535
        endcase
5536
    else
5537
        select = {nr_of_ports{1'b0}};
5538
 
5539
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5540 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5541
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5542
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5543
 
5544
end
5545
endgenerate
5546
 
5547
generate
5548 44 unneback
if (nr_of_ports == 4) begin
5549
 
5550
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5551
 
5552
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5553
 
5554
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5555
 
5556
    always @ (idle or wbm_cyc_o)
5557
    if (idle)
5558
        casex (wbm_cyc_o)
5559
        4'b1xxx : select = 4'b1000;
5560
        4'b01xx : select = 4'b0100;
5561
        4'b001x : select = 4'b0010;
5562
        4'b0001 : select = 4'b0001;
5563
        default : select = {nr_of_ports{1'b0}};
5564
        endcase
5565
    else
5566
        select = {nr_of_ports{1'b0}};
5567
 
5568
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5569
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5570
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5571
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5572
 
5573
end
5574
endgenerate
5575
 
5576
generate
5577
if (nr_of_ports == 5) begin
5578
 
5579
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5580
 
5581
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5582
 
5583
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5584
 
5585
    always @ (idle or wbm_cyc_o)
5586
    if (idle)
5587
        casex (wbm_cyc_o)
5588
        5'b1xxxx : select = 5'b10000;
5589
        5'b01xxx : select = 5'b01000;
5590
        5'b001xx : select = 5'b00100;
5591
        5'b0001x : select = 5'b00010;
5592
        5'b00001 : select = 5'b00001;
5593
        default : select = {nr_of_ports{1'b0}};
5594
        endcase
5595
    else
5596
        select = {nr_of_ports{1'b0}};
5597
 
5598
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5599
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5600
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5601
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5602
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5603
 
5604
end
5605
endgenerate
5606
 
5607
generate
5608 67 unneback
if (nr_of_ports == 6) begin
5609
 
5610
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5611
 
5612
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5613
 
5614
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5615
 
5616
    always @ (idle or wbm_cyc_o)
5617
    if (idle)
5618
        casex (wbm_cyc_o)
5619
        6'b1xxxxx : select = 6'b100000;
5620
        6'b01xxxx : select = 6'b010000;
5621
        6'b001xxx : select = 6'b001000;
5622
        6'b0001xx : select = 6'b000100;
5623
        6'b00001x : select = 6'b000010;
5624
        6'b000001 : select = 6'b000001;
5625
        default : select = {nr_of_ports{1'b0}};
5626
        endcase
5627
    else
5628
        select = {nr_of_ports{1'b0}};
5629
 
5630
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5631
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5632
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5633
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5634
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5635
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5636
 
5637
end
5638
endgenerate
5639
 
5640
generate
5641
if (nr_of_ports == 7) begin
5642
 
5643
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5644
 
5645
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5646
 
5647
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5648
 
5649
    always @ (idle or wbm_cyc_o)
5650
    if (idle)
5651
        casex (wbm_cyc_o)
5652
        7'b1xxxxxx : select = 7'b1000000;
5653
        7'b01xxxxx : select = 7'b0100000;
5654
        7'b001xxxx : select = 7'b0010000;
5655
        7'b0001xxx : select = 7'b0001000;
5656
        7'b00001xx : select = 7'b0000100;
5657
        7'b000001x : select = 7'b0000010;
5658
        7'b0000001 : select = 7'b0000001;
5659
        default : select = {nr_of_ports{1'b0}};
5660
        endcase
5661
    else
5662
        select = {nr_of_ports{1'b0}};
5663
 
5664
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5665
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5666
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5667
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5668
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5669
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5670
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5671
 
5672
end
5673
endgenerate
5674
 
5675
generate
5676
if (nr_of_ports == 8) begin
5677
 
5678
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5679
 
5680
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5681
 
5682
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5683
 
5684
    always @ (idle or wbm_cyc_o)
5685
    if (idle)
5686
        casex (wbm_cyc_o)
5687
        8'b1xxxxxxx : select = 8'b10000000;
5688
        8'b01xxxxxx : select = 8'b01000000;
5689
        8'b001xxxxx : select = 8'b00100000;
5690
        8'b0001xxxx : select = 8'b00010000;
5691
        8'b00001xxx : select = 8'b00001000;
5692
        8'b000001xx : select = 8'b00000100;
5693
        8'b0000001x : select = 8'b00000010;
5694
        8'b00000001 : select = 8'b00000001;
5695
        default : select = {nr_of_ports{1'b0}};
5696
        endcase
5697
    else
5698
        select = {nr_of_ports{1'b0}};
5699
 
5700
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
5701
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5702
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5703
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5704
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5705
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5706
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5707
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5708
 
5709
end
5710
endgenerate
5711
 
5712
generate
5713 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
5714 42 unneback
`define MODULE spr
5715
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
5716
`undef MODULE
5717 39 unneback
end
5718
endgenerate
5719
 
5720
    assign sel = select | state;
5721
 
5722 40 unneback
`define MODULE mux_andor
5723
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
5724
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
5725
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
5726
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
5727
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
5728
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
5729
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
5730
`undef MODULE
5731 39 unneback
    assign wbs_cyc_i = |sel;
5732
 
5733
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
5734
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
5735
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
5736
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
5737
 
5738
endmodule
5739 40 unneback
`endif
5740 39 unneback
 
5741 101 unneback
`ifdef WB_RAM
5742 49 unneback
// WB RAM with byte enable
5743 101 unneback
`define MODULE wb_ram
5744 59 unneback
module `BASE`MODULE (
5745
`undef MODULE
5746 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5747 101 unneback
    wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
5748 59 unneback
 
5749 101 unneback
parameter adr_width = 16;
5750
parameter mem_size = 1<<adr_width;
5751
parameter dat_width = 32;
5752
parameter max_burst_width = 4; // only used for B3
5753
parameter mode = "B3"; // valid options: B3, B4
5754 60 unneback
parameter memory_init = 1;
5755
parameter memory_file = "vl_ram.vmem";
5756 59 unneback
 
5757 101 unneback
input [dat_width-1:0] wbs_dat_i;
5758
input [adr_width-1:0] wbs_adr_i;
5759
input [2:0] wbs_cti_i;
5760
input [1:0] wbs_bte_i;
5761
input [dat_width/8-1:0] wbs_sel_i;
5762 70 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5763 101 unneback
output [dat_width-1:0] wbs_dat_o;
5764 70 unneback
output wbs_ack_o;
5765 101 unneback
output wbs_stall_o;
5766 71 unneback
input wb_clk, wb_rst;
5767 59 unneback
 
5768 101 unneback
wire [adr_width-1:0] adr;
5769
wire we;
5770 59 unneback
 
5771 101 unneback
generate
5772
if (mode=="B3") begin : B3_inst
5773 83 unneback
`define MODULE wb_adr_inc
5774 101 unneback
`BASE`MODULE # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
5775 83 unneback
    .cyc_i(wbs_cyc_i),
5776
    .stb_i(wbs_stb_i),
5777
    .cti_i(wbs_cti_i),
5778
    .bte_i(wbs_bte_i),
5779
    .adr_i(wbs_adr_i),
5780 85 unneback
    .we_i(wbs_we_i),
5781 83 unneback
    .ack_o(wbs_ack_o),
5782
    .adr_o(adr),
5783
    .clk(wb_clk),
5784
    .rst(wb_rst));
5785
`undef MODULE
5786 101 unneback
assign we = wbs_we_i & wbs_ack_o;
5787
end else if (mode=="B4") begin : B4_inst
5788
reg wbs_ack_o_reg;
5789
always @ (posedge wb_clk or posedge wb_rst)
5790
    if (wb_rst)
5791
        wbs_ack_o_reg <= 1'b0;
5792
    else
5793
        wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
5794
assign wbs_ack_o = wbs_ack_o_reg;
5795
assign wbs_stall_o = 1'b0;
5796
assign adr = wbs_adr_i;
5797
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
5798
end
5799
endgenerate
5800 60 unneback
 
5801 100 unneback
`define MODULE ram_be
5802
`BASE`MODULE # (
5803
    .data_width(dat_width),
5804
    .addr_width(adr_width),
5805
    .mem_size(mem_size),
5806
    .memory_init(memory_init),
5807
    .memory_file(memory_file))
5808
ram0(
5809
`undef MODULE
5810 101 unneback
    .d(wbs_dat_i),
5811
    .adr(adr),
5812
    .be(wbs_sel_i),
5813
    .we(we),
5814
    .q(wbs_dat_o),
5815 100 unneback
    .clk(wb_clk)
5816
);
5817 49 unneback
 
5818
endmodule
5819
`endif
5820
 
5821 103 unneback
`ifdef WB_SHADOW_RAM
5822
// A wishbone compliant RAM module that can be placed in front of other memory controllers
5823
`define MODULE wb_shadow_ram
5824
module `BASE`MODULE (
5825
`undef MODULE
5826
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5827
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
5828
    wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5829
    wbm_dat_i, wbm_ack_i, wbm_stall_i,
5830
    wb_clk, wb_rst);
5831
 
5832
parameter dat_width = 32;
5833
parameter mode = "B4";
5834
parameter max_burst_width = 4; // only used for B3
5835
 
5836
parameter shadow_mem_adr_width = 10;
5837
parameter shadow_mem_size = 1024;
5838
parameter shadow_mem_init = 2;
5839
parameter shadow_mem_file = "vl_ram.v";
5840
 
5841
parameter main_mem_adr_width = 24;
5842
 
5843
input [dat_width-1:0] wbs_dat_i;
5844
input [main_mem_adr_width-1:0] wbs_adr_i;
5845
input [2:0] wbs_cti_i;
5846
input [1:0] wbs_bte_i;
5847
input [dat_width/8-1:0] wbs_sel_i;
5848
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5849
output [dat_width-1:0] wbs_dat_o;
5850
output wbs_ack_o;
5851
output wbs_stall_o;
5852
 
5853
output [dat_width-1:0] wbm_dat_o;
5854
output [main_mem_adr_width-1:0] wbm_adr_o;
5855
output [2:0] wbm_cti_o;
5856
output [1:0] wbm_bte_o;
5857
output [dat_width/8-1:0] wbm_sel_o;
5858
output wbm_we_o, wbm_stb_o, wbm_cyc_o;
5859
input [dat_width-1:0] wbm_dat_i;
5860
input wbm_ack_i, wbm_stall_i;
5861
 
5862
input wb_clk, wb_rst;
5863
 
5864
generate
5865
if (shadow_mem_size>0) begin : shadow_ram_inst
5866
 
5867
wire cyc;
5868
wire [dat_width-1:0] dat;
5869
wire stall, ack;
5870
 
5871
assign cyc = wbs_cyc_i & (wbs_adr_i<=shadow_mem_size);
5872
`define MODULE wb_ram
5873
`BASE`MODULE # (
5874
    .dat_width(dat_width),
5875
    .adr_width(shadow_mem_adr_width),
5876
    .mem_size(shadow_mem_size),
5877
    .memory_init(shadow_mem_init),
5878 117 unneback
    .memory_file(shadow_mem_file),
5879 103 unneback
    .mode(mode))
5880
shadow_mem0 (
5881
    .wbs_dat_i(wbs_dat_i),
5882
    .wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),
5883
    .wbs_sel_i(wbs_sel_i),
5884
    .wbs_we_i (wbs_we_i),
5885
    .wbs_bte_i(wbs_bte_i),
5886
    .wbs_cti_i(wbs_cti_i),
5887
    .wbs_stb_i(wbs_stb_i),
5888
    .wbs_cyc_i(cyc),
5889
    .wbs_dat_o(dat),
5890
    .wbs_stall_o(stall),
5891
    .wbs_ack_o(ack),
5892
    .wb_clk(wb_clk),
5893
    .wb_rst(wb_rst));
5894
`undef MODULE
5895
 
5896
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o} =
5897
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i};
5898
assign wbm_cyc_o = wbs_cyc_i & (wbs_adr_i>shadow_mem_size);
5899
 
5900
assign wbs_dat_o = (dat & {dat_width{cyc}}) | (wbm_dat_i & {dat_width{wbm_cyc_o}});
5901
assign wbs_ack_o = (ack & cyc) | (wbm_ack_i & wbm_cyc_o);
5902
assign wbs_stall_o = (stall & cyc) | (wbm_stall_i & wbm_cyc_o);
5903
 
5904
end else begin : no_shadow_ram_inst
5905
 
5906
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o} =
5907
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i};
5908
assign {wbs_dat_o, wbs_ack_o, wbs_stall_o} = {wbm_dat_i, wbm_ack_i, wbm_stall_i};
5909
 
5910
end
5911
endgenerate
5912
 
5913
endmodule
5914
`endif
5915
 
5916 48 unneback
`ifdef WB_B4_ROM
5917
// WB ROM
5918
`define MODULE wb_b4_rom
5919
module `BASE`MODULE (
5920
`undef MODULE
5921
    wb_adr_i, wb_stb_i, wb_cyc_i,
5922
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
5923
 
5924
    parameter dat_width = 32;
5925
    parameter dat_default = 32'h15000000;
5926
    parameter adr_width = 32;
5927
 
5928
/*
5929
`ifndef ROM
5930
`define ROM "rom.v"
5931
`endif
5932
*/
5933
    input [adr_width-1:2]   wb_adr_i;
5934
    input                   wb_stb_i;
5935
    input                   wb_cyc_i;
5936
    output [dat_width-1:0]  wb_dat_o;
5937
    reg [dat_width-1:0]     wb_dat_o;
5938
    output                  wb_ack_o;
5939
    reg                     wb_ack_o;
5940
    output                  stall_o;
5941
    input                   wb_clk;
5942
    input                   wb_rst;
5943
 
5944
always @ (posedge wb_clk or posedge wb_rst)
5945
    if (wb_rst)
5946
        wb_dat_o <= {dat_width{1'b0}};
5947
    else
5948
         case (wb_adr_i[adr_width-1:2])
5949
`ifdef ROM
5950
`include `ROM
5951
`endif
5952
           default:
5953
             wb_dat_o <= dat_default;
5954
 
5955
         endcase // case (wb_adr_i)
5956
 
5957
 
5958
always @ (posedge wb_clk or posedge wb_rst)
5959
    if (wb_rst)
5960
        wb_ack_o <= 1'b0;
5961
    else
5962
        wb_ack_o <= wb_stb_i & wb_cyc_i;
5963
 
5964
assign stall_o = 1'b0;
5965
 
5966
endmodule
5967
`endif
5968
 
5969
 
5970 40 unneback
`ifdef WB_BOOT_ROM
5971 17 unneback
// WB ROM
5972 40 unneback
`define MODULE wb_boot_rom
5973
module `BASE`MODULE (
5974
`undef MODULE
5975 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
5976 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
5977 17 unneback
 
5978 18 unneback
    parameter adr_hi = 31;
5979
    parameter adr_lo = 28;
5980
    parameter adr_sel = 4'hf;
5981
    parameter addr_width = 5;
5982 33 unneback
/*
5983 17 unneback
`ifndef BOOT_ROM
5984
`define BOOT_ROM "boot_rom.v"
5985
`endif
5986 33 unneback
*/
5987 18 unneback
    input [adr_hi:2]    wb_adr_i;
5988
    input               wb_stb_i;
5989
    input               wb_cyc_i;
5990
    output [31:0]        wb_dat_o;
5991
    output              wb_ack_o;
5992
    output              hit_o;
5993
    input               wb_clk;
5994
    input               wb_rst;
5995
 
5996
    wire hit;
5997
    reg [31:0] wb_dat;
5998
    reg wb_ack;
5999
 
6000
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
6001 17 unneback
 
6002
always @ (posedge wb_clk or posedge wb_rst)
6003
    if (wb_rst)
6004 18 unneback
        wb_dat <= 32'h15000000;
6005 17 unneback
    else
6006 18 unneback
         case (wb_adr_i[addr_width-1:2])
6007 33 unneback
`ifdef BOOT_ROM
6008 17 unneback
`include `BOOT_ROM
6009 33 unneback
`endif
6010 17 unneback
           /*
6011
            // Zero r0 and jump to 0x00000100
6012 18 unneback
 
6013
            1 : wb_dat <= 32'hA8200000;
6014
            2 : wb_dat <= 32'hA8C00100;
6015
            3 : wb_dat <= 32'h44003000;
6016
            4 : wb_dat <= 32'h15000000;
6017 17 unneback
            */
6018
           default:
6019 18 unneback
             wb_dat <= 32'h00000000;
6020 17 unneback
 
6021
         endcase // case (wb_adr_i)
6022
 
6023
 
6024
always @ (posedge wb_clk or posedge wb_rst)
6025
    if (wb_rst)
6026 18 unneback
        wb_ack <= 1'b0;
6027 17 unneback
    else
6028 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
6029 17 unneback
 
6030 18 unneback
assign hit_o = hit;
6031
assign wb_dat_o = wb_dat & {32{wb_ack}};
6032
assign wb_ack_o = wb_ack;
6033
 
6034 17 unneback
endmodule
6035 40 unneback
`endif
6036 32 unneback
 
6037 106 unneback
`ifdef WB_DPRAM
6038
`define MODULE wb_dpram
6039 40 unneback
module `BASE`MODULE (
6040
`undef MODULE
6041 32 unneback
        // wishbone slave side a
6042 106 unneback
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, wbsa_stall_o,
6043 32 unneback
        wbsa_clk, wbsa_rst,
6044 92 unneback
        // wishbone slave side b
6045 106 unneback
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, wbsb_stall_o,
6046 32 unneback
        wbsb_clk, wbsb_rst);
6047
 
6048 92 unneback
parameter data_width_a = 32;
6049
parameter data_width_b = data_width_a;
6050
parameter addr_width_a = 8;
6051
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
6052 101 unneback
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
6053 92 unneback
parameter max_burst_width_a = 4;
6054
parameter max_burst_width_b = max_burst_width_a;
6055 101 unneback
parameter mode = "B3";
6056 109 unneback
parameter memory_init = 0;
6057
parameter memory_file = "vl_ram.v";
6058 92 unneback
input [data_width_a-1:0] wbsa_dat_i;
6059
input [addr_width_a-1:0] wbsa_adr_i;
6060
input [data_width_a/8-1:0] wbsa_sel_i;
6061
input [2:0] wbsa_cti_i;
6062
input [1:0] wbsa_bte_i;
6063 32 unneback
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
6064 92 unneback
output [data_width_a-1:0] wbsa_dat_o;
6065 109 unneback
output wbsa_ack_o;
6066 106 unneback
output wbsa_stall_o;
6067 32 unneback
input wbsa_clk, wbsa_rst;
6068
 
6069 92 unneback
input [data_width_b-1:0] wbsb_dat_i;
6070
input [addr_width_b-1:0] wbsb_adr_i;
6071
input [data_width_b/8-1:0] wbsb_sel_i;
6072
input [2:0] wbsb_cti_i;
6073
input [1:0] wbsb_bte_i;
6074 32 unneback
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
6075 92 unneback
output [data_width_b-1:0] wbsb_dat_o;
6076 109 unneback
output wbsb_ack_o;
6077 106 unneback
output wbsb_stall_o;
6078 32 unneback
input wbsb_clk, wbsb_rst;
6079
 
6080 92 unneback
wire [addr_width_a-1:0] adr_a;
6081
wire [addr_width_b-1:0] adr_b;
6082 101 unneback
wire we_a, we_b;
6083
generate
6084
if (mode=="B3") begin : b3_inst
6085 92 unneback
`define MODULE wb_adr_inc
6086
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
6087
    .cyc_i(wbsa_cyc_i),
6088
    .stb_i(wbsa_stb_i),
6089
    .cti_i(wbsa_cti_i),
6090
    .bte_i(wbsa_bte_i),
6091
    .adr_i(wbsa_adr_i),
6092
    .we_i(wbsa_we_i),
6093
    .ack_o(wbsa_ack_o),
6094
    .adr_o(adr_a),
6095
    .clk(wbsa_clk),
6096
    .rst(wbsa_rst));
6097 101 unneback
assign we_a = wbsa_we_i & wbsa_ack_o;
6098 92 unneback
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
6099
    .cyc_i(wbsb_cyc_i),
6100
    .stb_i(wbsb_stb_i),
6101
    .cti_i(wbsb_cti_i),
6102
    .bte_i(wbsb_bte_i),
6103
    .adr_i(wbsb_adr_i),
6104
    .we_i(wbsb_we_i),
6105
    .ack_o(wbsb_ack_o),
6106
    .adr_o(adr_b),
6107
    .clk(wbsb_clk),
6108
    .rst(wbsb_rst));
6109 40 unneback
`undef MODULE
6110 101 unneback
assign we_b = wbsb_we_i & wbsb_ack_o;
6111
end else if (mode=="B4") begin : b4_inst
6112 109 unneback
`define MODULE dff
6113
`BASE`MODULE dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
6114 101 unneback
assign wbsa_stall_o = 1'b0;
6115
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
6116 109 unneback
`BASE`MODULE dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
6117
`undef MODULE
6118 101 unneback
assign wbsb_stall_o = 1'b0;
6119
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
6120
end
6121
endgenerate
6122 92 unneback
 
6123
`define MODULE dpram_be_2r2w
6124 109 unneback
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
6125 110 unneback
                 .b_data_width(data_width_b),
6126 109 unneback
                 .memory_init(memory_init), .memory_file(memory_file))
6127 92 unneback
`undef MODULE
6128
ram_i (
6129 32 unneback
    .d_a(wbsa_dat_i),
6130 92 unneback
    .q_a(wbsa_dat_o),
6131
    .adr_a(adr_a),
6132
    .be_a(wbsa_sel_i),
6133 101 unneback
    .we_a(we_a),
6134 32 unneback
    .clk_a(wbsa_clk),
6135
    .d_b(wbsb_dat_i),
6136 92 unneback
    .q_b(wbsb_dat_o),
6137
    .adr_b(adr_b),
6138
    .be_b(wbsb_sel_i),
6139 101 unneback
    .we_b(we_b),
6140 32 unneback
    .clk_b(wbsb_clk) );
6141
 
6142
endmodule
6143 40 unneback
`endif
6144 94 unneback
 
6145 101 unneback
`ifdef WB_CACHE
6146
`define MODULE wb_cache
6147 97 unneback
module `BASE`MODULE (
6148 103 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
6149 98 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
6150 97 unneback
);
6151
`undef MODULE
6152
 
6153
parameter dw_s = 32;
6154
parameter aw_s = 24;
6155
parameter dw_m = dw_s;
6156 124 unneback
//localparam aw_m = dw_s * aw_s / dw_m;
6157
localparam aw_m =
6158
        (dw_s==dw_m) ? aw_m :
6159
        (dw_s==dw_m*2) ? aw_m+1 :
6160
        (dw_s==dw_m*4) ? aw_m+2 :
6161
        (dw_s==dw_m*8) ? aw_m+3 :
6162
        (dw_s==dw_m*16) ? aw_m+4 :
6163
        (dw_s==dw_m*32) ? aw_m+5 :
6164
        (dw_s==dw_m/2) ? aw_m-1 :
6165
        (dw_s==adw_m/4) ? aw_m-2 :
6166
        (dw_s==dw_m/8) ? aw_m-3 :
6167
        (dw_s==dw_m/16) ? aw_m-4 :
6168
        (dw_s==dw_m/32) ? aw_m-5 : 0;
6169
 
6170 100 unneback
parameter wbs_max_burst_width = 4;
6171 103 unneback
parameter wbs_mode = "B3";
6172 97 unneback
 
6173
parameter async = 1; // wbs_clk != wbm_clk
6174
 
6175
parameter nr_of_ways = 1;
6176
parameter aw_offset = 4; // 4 => 16 words per cache line
6177
parameter aw_slot = 10;
6178 100 unneback
 
6179
parameter valid_mem = 0;
6180
parameter debug = 0;
6181
 
6182
localparam aw_b_offset = aw_offset * dw_s / dw_m;
6183 98 unneback
localparam aw_tag = aw_s - aw_slot - aw_offset;
6184 97 unneback
parameter wbm_burst_size = 4; // valid options 4,8,16
6185 98 unneback
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
6186 97 unneback
`define SIZE2WIDTH wbm_burst_size
6187
localparam wbm_burst_width `SIZE2WIDTH_EXPR
6188
`undef SIZE2WIDTH
6189
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
6190
`define SIZE2WIDTH nr_of_wbm_burst
6191
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
6192
`undef SIZE2WIDTH
6193 100 unneback
 
6194 97 unneback
input [dw_s-1:0] wbs_dat_i;
6195
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
6196 98 unneback
input [dw_s/8-1:0] wbs_sel_i;
6197 97 unneback
input [2:0] wbs_cti_i;
6198
input [1:0] wbs_bte_i;
6199 98 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
6200 97 unneback
output [dw_s-1:0] wbs_dat_o;
6201
output wbs_ack_o;
6202 103 unneback
output wbs_stall_o;
6203 97 unneback
input wbs_clk, wbs_rst;
6204
 
6205
output [dw_m-1:0] wbm_dat_o;
6206
output [aw_m-1:0] wbm_adr_o;
6207
output [dw_m/8-1:0] wbm_sel_o;
6208
output [2:0] wbm_cti_o;
6209
output [1:0] wbm_bte_o;
6210 98 unneback
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
6211 97 unneback
input [dw_m-1:0] wbm_dat_i;
6212
input wbm_ack_i;
6213
input wbm_stall_i;
6214
input wbm_clk, wbm_rst;
6215
 
6216 100 unneback
wire valid, dirty, hit;
6217 97 unneback
wire [aw_tag-1:0] tag;
6218
wire tag_mem_we;
6219
wire [aw_tag-1:0] wbs_adr_tag;
6220
wire [aw_slot-1:0] wbs_adr_slot;
6221 98 unneback
wire [aw_offset-1:0] wbs_adr_word;
6222
wire [aw_s-1:0] wbs_adr;
6223 97 unneback
 
6224
reg [1:0] state;
6225
localparam idle = 2'h0;
6226
localparam rdwr = 2'h1;
6227
localparam push = 2'h2;
6228
localparam pull = 2'h3;
6229
wire eoc;
6230 103 unneback
wire we;
6231 97 unneback
 
6232
// cdc
6233
wire done, mem_alert, mem_done;
6234
 
6235 98 unneback
// wbm side
6236
reg [aw_m-1:0] wbm_radr;
6237
reg [aw_m-1:0] wbm_wadr;
6238 100 unneback
wire [aw_slot-1:0] wbm_adr;
6239 98 unneback
wire wbm_radr_cke, wbm_wadr_cke;
6240
 
6241 100 unneback
reg [2:0] phase;
6242
// phase = {we,stb,cyc}
6243
localparam wbm_wait     = 3'b000;
6244
localparam wbm_wr       = 3'b111;
6245
localparam wbm_wr_drain = 3'b101;
6246
localparam wbm_rd       = 3'b011;
6247
localparam wbm_rd_drain = 3'b001;
6248 98 unneback
 
6249 97 unneback
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
6250
 
6251 100 unneback
generate
6252
if (valid_mem==0) begin : no_valid_mem
6253
assign valid = 1'b1;
6254
end else begin : valid_mem_inst
6255
`define MODULE dpram_1r1w
6256 97 unneback
`BASE`MODULE
6257 100 unneback
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6258
    valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6259
                .q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6260 97 unneback
`undef MODULE
6261 100 unneback
end
6262
endgenerate
6263 97 unneback
 
6264 100 unneback
`define MODULE dpram_1r1w
6265
`BASE`MODULE
6266
    # ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6267
    tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6268
              .q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6269
assign hit = wbs_adr_tag == tag;
6270
`undef MODULE
6271
 
6272
`define MODULE dpram_1r2w
6273
`BASE`MODULE
6274
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6275
    dirty_mem (
6276
        .d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
6277
        .d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
6278
`undef MODULE
6279
 
6280 103 unneback
generate
6281
if (wbs_mode=="B3") begin : inst_b3
6282 97 unneback
`define MODULE wb_adr_inc
6283 100 unneback
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
6284
    .cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
6285
    .stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
6286 97 unneback
    .cti_i(wbs_cti_i),
6287
    .bte_i(wbs_bte_i),
6288
    .adr_i(wbs_adr_i),
6289
    .we_i (wbs_we_i),
6290
    .ack_o(wbs_ack_o),
6291
    .adr_o(wbs_adr),
6292 100 unneback
    .clk(wbs_clk),
6293
    .rst(wbs_rst));
6294 97 unneback
`undef MODULE
6295 103 unneback
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
6296
assign we = wbs_cyc_i &  wbs_we_i & wbs_ack_o;
6297
end else if (wbs_mode=="B4") begin : inst_b4
6298
end
6299 97 unneback
 
6300 103 unneback
endgenerate
6301
 
6302 97 unneback
`define MODULE dpram_be_2r2w
6303
`BASE`MODULE
6304 100 unneback
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
6305 103 unneback
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
6306 100 unneback
                .d_b(wbm_dat_i), .adr_b(wbm_adr_o[aw_slot+aw_offset-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
6307 97 unneback
`undef MODULE
6308
 
6309
always @ (posedge wbs_clk or posedge wbs_rst)
6310
if (wbs_rst)
6311 98 unneback
    state <= idle;
6312 97 unneback
else
6313
    case (state)
6314
    idle:
6315
        if (wbs_cyc_i)
6316
            state <= rdwr;
6317
    rdwr:
6318 100 unneback
        casex ({valid, hit, dirty, eoc})
6319
        4'b0xxx: state <= pull;
6320
        4'b11x1: state <= idle;
6321
        4'b101x: state <= push;
6322
        4'b100x: state <= pull;
6323
        endcase
6324 97 unneback
    push:
6325
        if (done)
6326
            state <= rdwr;
6327
    pull:
6328
        if (done)
6329
            state <= rdwr;
6330
    default: state <= idle;
6331
    endcase
6332
 
6333
// cdc
6334
generate
6335
if (async==1) begin : cdc0
6336
`define MODULE cdc
6337 100 unneback
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
6338 97 unneback
`undef MODULE
6339
end
6340
else begin : nocdc
6341 100 unneback
    assign mem_alert = state==rdwr & (!valid | !hit);
6342 97 unneback
    assign done = mem_done;
6343
end
6344
endgenerate
6345
 
6346
// FSM generating a number of burts 4 cycles
6347
// actual number depends on data width ratio
6348
// nr_of_wbm_burst
6349 101 unneback
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0]       cnt_rw, cnt_ack;
6350 97 unneback
 
6351
always @ (posedge wbm_clk or posedge wbm_rst)
6352
if (wbm_rst)
6353 100 unneback
    cnt_rw <= {wbm_burst_width{1'b0}};
6354 97 unneback
else
6355 100 unneback
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
6356
        cnt_rw <= cnt_rw + 1;
6357 97 unneback
 
6358 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6359
if (wbm_rst)
6360 100 unneback
    cnt_ack <= {wbm_burst_width{1'b0}};
6361 98 unneback
else
6362 100 unneback
    if (wbm_ack_i)
6363
        cnt_ack <= cnt_ack + 1;
6364 97 unneback
 
6365 100 unneback
generate
6366 101 unneback
if (nr_of_wbm_burst==1) begin : one_burst
6367 100 unneback
 
6368 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6369
if (wbm_rst)
6370
    phase <= wbm_wait;
6371
else
6372
    case (phase)
6373
    wbm_wait:
6374
        if (mem_alert)
6375 100 unneback
            if (state==push)
6376
                phase <= wbm_wr;
6377
            else
6378
                phase <= wbm_rd;
6379 98 unneback
    wbm_wr:
6380 100 unneback
        if (&cnt_rw)
6381
            phase <= wbm_wr_drain;
6382
    wbm_wr_drain:
6383
        if (&cnt_ack)
6384 98 unneback
            phase <= wbm_rd;
6385
    wbm_rd:
6386 100 unneback
        if (&cnt_rw)
6387
            phase <= wbm_rd_drain;
6388
    wbm_rd_drain:
6389
        if (&cnt_ack)
6390
            phase <= wbm_wait;
6391 98 unneback
    default: phase <= wbm_wait;
6392
    endcase
6393
 
6394 100 unneback
end else begin : multiple_burst
6395
 
6396 101 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6397
if (wbm_rst)
6398
    phase <= wbm_wait;
6399
else
6400
    case (phase)
6401
    wbm_wait:
6402
        if (mem_alert)
6403
            if (state==push)
6404
                phase <= wbm_wr;
6405
            else
6406
                phase <= wbm_rd;
6407
    wbm_wr:
6408
        if (&cnt_rw[wbm_burst_width-1:0])
6409
            phase <= wbm_wr_drain;
6410
    wbm_wr_drain:
6411
        if (&cnt_ack)
6412
            phase <= wbm_rd;
6413
        else if (&cnt_ack[wbm_burst_width-1:0])
6414
            phase <= wbm_wr;
6415
    wbm_rd:
6416
        if (&cnt_rw[wbm_burst_width-1:0])
6417
            phase <= wbm_rd_drain;
6418
    wbm_rd_drain:
6419
        if (&cnt_ack)
6420
            phase <= wbm_wait;
6421
        else if (&cnt_ack[wbm_burst_width-1:0])
6422
            phase <= wbm_rd;
6423
    default: phase <= wbm_wait;
6424
    endcase
6425 100 unneback
 
6426 101 unneback
 
6427 100 unneback
end
6428
endgenerate
6429
 
6430 101 unneback
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
6431 100 unneback
 
6432
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
6433
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
6434
assign wbm_sel_o = {dw_m/8{1'b1}};
6435
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
6436 98 unneback
assign wbm_bte_o = bte;
6437 100 unneback
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
6438 98 unneback
 
6439 97 unneback
endmodule
6440
`endif
6441 103 unneback
 
6442
`ifdef WB_AVALON_BRIDGE
6443
// Wishbone to avalon bridge supporting one type of burst transfer only
6444
// intended use is together with cache above
6445
// WB B4 -> pipelined avalon
6446
`define MODULE wb_avalon_bridge
6447
module `BASE`MODULE (
6448
`undef MODULE
6449
        // wishbone slave side
6450
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
6451
        // avalon master side
6452
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
6453
        // common
6454
        clk, rst);
6455
 
6456
parameter adr_width = 30;
6457
parameter dat_width = 32;
6458
parameter burst_size = 4;
6459
 
6460
input [dat_width-1:0] wbs_dat_i;
6461
input [adr_width-1:0] wbs_adr_i;
6462
input [dat_width/8-1:0]  wbs_sel_i;
6463
input [1:0]  wbs_bte_i;
6464
input [2:0]  wbs_cti_i;
6465
input wbs_we_i;
6466
input wbs_cyc_i;
6467
input wbs_stb_i;
6468
output [dat_width:0] wbs_dat_o;
6469
output wbs_ack_o;
6470
output wbs_stall_o;
6471
 
6472
input [dat_width-1:0] readdata;
6473
input readdatavalid;
6474
output [dat_width-1:0] writedata;
6475
output [adr_width-1:0] address;
6476
output [dat_width/8-1:0]  be;
6477
output write;
6478
output read;
6479
output beginbursttransfer;
6480
output [3:0] burstcount;
6481
input waitrequest;
6482
input clk, rst;
6483
 
6484
reg last_cyc_idle_or_eoc;
6485
 
6486
reg [3:0] cnt;
6487
always @ (posedge clk or posedge rst)
6488
if (rst)
6489
    cnt <= 4'h0;
6490
else
6491
    if (beginbursttransfer & waitrequest)
6492
        cnt <= burst_size - 1;
6493
    else if (beginbursttransfer & !waitrequest)
6494
        cnt <= burst_size - 2;
6495
    else if (wbs_ack_o)
6496
        cnt <= cnt - 1;
6497
 
6498
reg wr_ack;
6499
always @ (posedge clk or posedge rst)
6500
if (rst)
6501
    wr_ack <= 1'b0;
6502
else
6503
    wr_ack <=  (wbs_we_i & wbs_cyc_i & wbs_stb_i & !wbs_stall_o);
6504
 
6505
// to avalon
6506
assign writedata = wbs_dat_i;
6507
assign address = wbs_adr_i;
6508
assign be = wbs_sel_i;
6509
assign write = cnt==(burst_size-1) & wbs_cyc_i &  wbs_we_i;
6510
assign read  = cnt==(burst_size-1) & wbs_cyc_i & !wbs_we_i;
6511
assign beginbursttransfer = cnt==4'h0 & wbs_cyc_i;
6512
assign burstcount = burst_size;
6513
 
6514
// to wishbone
6515
assign wbs_dat_o = readdata;
6516
assign wbs_ack_o = wr_ack | readdatavalid;
6517
assign wbs_stall_o = waitrequest;
6518
 
6519
endmodule
6520
`endif
6521
 
6522
`ifdef WB_AVALON_MEM_CACHE
6523
`define MODULE wb_avalon_mem_cache
6524
module `BASE`MODULE (
6525
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
6526
    readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst
6527
);
6528
`undef MODULE
6529
 
6530
// wishbone
6531
parameter wb_dat_width = 32;
6532
parameter wb_adr_width = 22;
6533
parameter wb_max_burst_width = 4;
6534
parameter wb_mode = "B4";
6535
// avalon
6536
parameter avalon_dat_width = 32;
6537 121 unneback
//localparam avalon_adr_width = wb_dat_width * wb_adr_width / avalon_dat_width;
6538 122 unneback
localparam avalon_adr_width =
6539
        (wb_dat_width==avalon_dat_width) ? wb_adr_width :
6540
        (wb_dat_width==avalon_dat_width*2) ? wb_adr_width+1 :
6541
        (wb_dat_width==avalon_dat_width*4) ? wb_adr_width+2 :
6542
        (wb_dat_width==avalon_dat_width*8) ? wb_adr_width+3 :
6543
        (wb_dat_width==avalon_dat_width*16) ? wb_adr_width+4 :
6544
        (wb_dat_width==avalon_dat_width*32) ? wb_adr_width+5 :
6545
        (wb_dat_width==avalon_dat_width/2) ? wb_adr_width-1 :
6546
        (wb_dat_width==avalon_dat_width/4) ? wb_adr_width-2 :
6547
        (wb_dat_width==avalon_dat_width/8) ? wb_adr_width-3 :
6548
        (wb_dat_width==avalon_dat_width/16) ? wb_adr_width-4 :
6549 123 unneback
        (wb_dat_width==avalon_dat_width/32) ? wb_adr_width-5 : 0;
6550 103 unneback
parameter avalon_burst_size = 4;
6551
// cache
6552
parameter async = 1;
6553
parameter nr_of_ways = 1;
6554
parameter aw_offset = 4;
6555
parameter aw_slot = 10;
6556
parameter valid_mem = 1;
6557
// shadow RAM
6558
parameter shadow_ram = 0;
6559
parameter shadow_ram_adr_width = 10;
6560
parameter shadow_ram_size = 1024;
6561
parameter shadow_ram_init = 2; // 0: no init, 1: from file, 2: with zero
6562
parameter shadow_ram_file = "vl_ram.v";
6563
 
6564
input [wb_dat_width-1:0] wbs_dat_i;
6565
input [wb_adr_width-1:0] wbs_adr_i; // dont include a1,a0
6566
input [wb_dat_width/8-1:0] wbs_sel_i;
6567
input [2:0] wbs_cti_i;
6568
input [1:0] wbs_bte_i;
6569
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
6570
output [wb_dat_width-1:0] wbs_dat_o;
6571
output wbs_ack_o;
6572
output wbs_stall_o;
6573
input wbs_clk, wbs_rst;
6574
 
6575
input [avalon_dat_width-1:0] readdata;
6576
input readdatavalid;
6577
output [avalon_dat_width-1:0] writedata;
6578
output [avalon_adr_width-1:0] address;
6579
output [avalon_dat_width/8-1:0]  be;
6580
output write;
6581
output read;
6582
output beginbursttransfer;
6583
output [3:0] burstcount;
6584
input waitrequest;
6585
input clk, rst;
6586
 
6587
`define DAT_WIDTH wb_dat_width
6588
`define ADR_WIDTH wb_adr_width
6589
`define WB wb1
6590
`include "wb_wires.v"
6591
`define WB wb2
6592
`include "wb_wires.v"
6593
`undef DAT_WIDTH
6594
`undef ADR_WIDTH
6595
 
6596
`define MODULE wb_shadow_ram
6597
`BASE`MODULE # ( .dat_width(wb_dat_width), .mode(wb_mode), .max_burst_width(wb_max_burst_width),
6598 120 unneback
                 .shadow_mem_adr_width(shadow_ram_adr_width), .shadow_mem_size(shadow_ram_size), .shadow_mem_init(shadow_ram_init), .shadow_mem_file(shadow_ram_file),
6599 103 unneback
                 .main_mem_adr_width(wb_adr_width))
6600
shadow_ram0 (
6601
    .wbs_dat_i(wbs_dat_i), .wbs_adr_i(wbs_adr_i), .wbs_cti_i(wbs_cti_i), .wbs_bte_i(wbs_bte_i), .wbs_sel_i(wbs_sel_i), .wbs_we_i(wbs_we_i), .wbs_stb_i(wbs_stb_i), .wbs_cyc_i(wbs_cyc_i),
6602
    .wbs_dat_o(wbs_dat_o), .wbs_ack_o(wbs_ack_o), .wbs_stall_o(wbs_stall_o),
6603
    .wbm_dat_o(wb1_dat_o), .wbm_adr_o(wb1_adr_o), .wbm_cti_o(wb1_cti_o), .wbm_bte_o(wb1_bte_o), .wbm_sel_o(wb1_sel_o), .wbm_we_o(wb1_we_o), .wbm_stb_o(wb1_stb_o), .wbm_cyc_o(wb1_cyc_o),
6604
    .wbm_dat_i(wb1_dat_i), .wbm_ack_i(wb1_ack_i), .wbm_stall_i(wb1_stall_i),
6605
    .wb_clk(wbs_clk), .wb_rst(wbs_rst));
6606
`undef MODULE
6607
 
6608
`define MODULE wb_cache
6609
`BASE`MODULE
6610
# ( .dw_s(wb_dat_width), .aw_s(wb_adr_width), .dw_m(avalon_dat_width), .wbs_mode(wb_mode), .wbs_max_burst_width(wb_max_burst_width), .async(async), .nr_of_ways(nr_of_ways), .aw_offset(aw_offset), .aw_slot(aw_slot), .valid_mem(valid_mem))
6611
cache0 (
6612
    .wbs_dat_i(wb1_dat_o), .wbs_adr_i(wb1_adr_o), .wbs_sel_i(wb1_sel_o), .wbs_cti_i(wb1_cti_o), .wbs_bte_i(wb1_bte_o), .wbs_we_i(wb1_we_o), .wbs_stb_i(wb1_stb_o), .wbs_cyc_i(wb1_cyc_o),
6613
    .wbs_dat_o(wb1_dat_i), .wbs_ack_o(wb1_ack_i), .wbs_stall_o(wb1_stall_i), .wbs_clk(wbs_clk), .wbs_rst(wbs_rst),
6614
    .wbm_dat_o(wb2_dat_o), .wbm_adr_o(wb2_adr_o), .wbm_sel_o(wb2_sel_o), .wbm_cti_o(wb2_cti_o), .wbm_bte_o(wb2_bte_o), .wbm_we_o(wb2_we_o), .wbm_stb_o(wb2_stb_o), .wbm_cyc_o(wb2_cyc_o),
6615
    .wbm_dat_i(wb2_dat_i), .wbm_ack_i(wb2_ack_i), .wbm_stall_i(wb2_stall_i), .wbm_clk(clk), .wbm_rst(rst));
6616
`undef MODULE
6617
 
6618
`define MODULE wb_avalon_bridge
6619
`BASE`MODULE # ( .adr_width(avalon_adr_width), .dat_width(avalon_dat_width), .burst_size(avalon_burst_size))
6620
bridge0 (
6621
        // wishbone slave side
6622
        .wbs_dat_i(wb2_dat_o), .wbs_adr_i(wb2_adr_o), .wbs_sel_i(wb2_sel_o), .wbs_bte_i(wb2_bte_o), .wbs_cti_i(wb2_cti_o), .wbs_we_i(wb2_we_o), .wbs_cyc_i(wb2_cyc_o), .wbs_stb_i(wb2_stb_o),
6623
        .wbs_dat_o(wb2_dat_i), .wbs_ack_o(wb2_ack_i), .wbs_stall_o(wb2_stall_i),
6624
        // avalon master side
6625
        .readdata(readdata), .readdatavalid(readdatavalid), .address(address), .read(read), .be(be), .write(write), .burstcount(burstcount), .writedata(writedata), .waitrequest(waitrequest), .beginbursttransfer(beginbursttransfer),
6626
        // common
6627
        .clk(clk), .rst(rst));
6628
`undef MODULE
6629
 
6630
endmodule
6631
`endif
6632 105 unneback
 
6633
`ifdef WB_SDR_SDRAM
6634
`define MODULE wb_sdr_sdram
6635
module `BASE`MODULE (
6636
`undef MODULE
6637
    // wisbone i/f
6638
    dat_i, adr_i, sel_i, we_i, cyc_i, stb_i, dat_o, ack_o, stall_o
6639
    // SDR SDRAM
6640
    ba, a, cmd, cke, cs_n, dqm, dq_i, dq_o, dq_oe,
6641
    // system
6642
    clk, rst);
6643
 
6644
    // external data bus size
6645
    parameter dat_size = 16;
6646
    // memory geometry parameters
6647
    parameter ba_size  = `SDR_BA_SIZE;
6648
    parameter row_size = `SDR_ROW_SIZE;
6649
    parameter col_size = `SDR_COL_SIZE;
6650
    parameter cl = 2;
6651
    // memory timing parameters
6652
    parameter tRFC = 9;
6653
    parameter tRP  = 2;
6654
    parameter tRCD = 2;
6655
    parameter tMRD = 2;
6656
 
6657
    // LMR
6658
    // [12:10] reserved
6659
    // [9]     WB, write burst; 0 - programmed burst length, 1 - single location
6660
    // [8:7]   OP Mode, 2'b00
6661
    // [6:4]   CAS Latency; 3'b010 - 2, 3'b011 - 3
6662
    // [3]     BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
6663
    // [2:0]   Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
6664
    localparam init_wb = 1'b1;
6665
    localparam init_cl = (cl==2) ? 3'b010 : 3'b011;
6666
    localparam init_bt = 1'b0;
6667
    localparam init_bl = 3'b000;
6668
 
6669
    input [dat_size:0] dat_i;
6670
    input [ba_size+col_size+row_size-1:0] adr_i;
6671
    input [dat_size/8-1:0] sel_i;
6672
    input we_i, cyc_i, stb_i;
6673
    output [dat_size-1:0] dat_o;
6674
    output ack_o;
6675
    output reg stall_o;
6676
 
6677
    output [ba_size-1:0]    ba;
6678
    output reg [12:0]   a;
6679
    output reg [2:0]    cmd; // {ras,cas,we}
6680
    output cke, cs_n;
6681
    output reg [dat_size/8-1:0]    dqm;
6682
    output [dat_size-1:0]       dq_o;
6683
    output reg          dq_oe;
6684
    input  [dat_size-1:0]       dq_i;
6685
 
6686
    input clk, rst;
6687
 
6688
    wire [ba_size-1:0]   bank;
6689
    wire [row_size-1:0] row;
6690
    wire [col_size-1:0] col;
6691
    wire [0:31]  shreg;
6692
    wire                ref_cnt_zero;
6693
    reg                 refresh_req;
6694
 
6695
    wire ack_rd, rd_ack_emptyflag;
6696
    wire ack_wr;
6697
 
6698
    // to keep track of open rows per bank
6699
    reg [row_size-1:0]   open_row[0:3];
6700
    reg [0:3]            open_ba;
6701
    reg                 current_bank_closed, current_row_open;
6702
 
6703
    parameter rfr_length = 10;
6704
    parameter rfr_wrap_value = 1010;
6705
 
6706
    parameter [2:0] cmd_nop = 3'b111,
6707
                    cmd_act = 3'b011,
6708
                    cmd_rd  = 3'b101,
6709
                    cmd_wr  = 3'b100,
6710
                    cmd_pch = 3'b010,
6711
                    cmd_rfr = 3'b001,
6712
                    cmd_lmr = 3'b000;
6713
 
6714
// ctrl FSM
6715
`define FSM_INIT 3'b000
6716
`define FSM_IDLE 3'b001
6717
`define FSM_RFR  3'b010
6718
`define FSM_ADR  3'b011
6719
`define FSM_PCH  3'b100
6720
`define FSM_ACT  3'b101
6721
`define FSM_RW   3'b111
6722
 
6723
    assign cke = 1'b1;
6724
    assign cs_n = 1'b0;
6725
 
6726
    reg [2:0] state, next;
6727
 
6728
    function [12:0] a10_fix;
6729
        input [col_size-1:0] a;
6730
        integer i;
6731
    begin
6732
        for (i=0;i<13;i=i+1) begin
6733
            if (i<10)
6734
              if (i<col_size)
6735
                a10_fix[i] = a[i];
6736
              else
6737
                a10_fix[i] = 1'b0;
6738
            else if (i==10)
6739
              a10_fix[i] = 1'b0;
6740
            else
6741
              if (i<col_size)
6742
                a10_fix[i] = a[i-1];
6743
              else
6744
                a10_fix[i] = 1'b0;
6745
        end
6746
    end
6747
    endfunction
6748
 
6749
    assign {bank,row,col} = adr_i;
6750
 
6751
    always @ (posedge clk or posedge rst)
6752
    if (rst)
6753
       state <= `FSM_INIT;
6754
    else
6755
       state <= next;
6756
 
6757
    always @*
6758
    begin
6759
        next = state;
6760
        case (state)
6761
        `FSM_INIT:
6762
            if (shreg[3+tRP+tRFC+tRFC+tMRD]) next = `FSM_IDLE;
6763
        `FSM_IDLE:
6764
            if (refresh_req) next = `FSM_RFR;
6765
            else if (cyc_i & stb_i & rd_ack_emptyflag) next = `FSM_ADR;
6766
        `FSM_RFR:
6767
            if (shreg[tRP+tRFC-2]) next = `FSM_IDLE; // take away two cycles because no cmd will be issued in idle and adr
6768
        `FSM_ADR:
6769
            if (current_bank_closed) next = `FSM_ACT;
6770
            else if (current_row_open) next = `FSM_RW;
6771
            else next = `FSM_PCH;
6772
        `FSM_PCH:
6773
            if (shreg[tRP]) next = `FSM_ACT;
6774
        `FSM_ACT:
6775
            if (shreg[tRCD]) next = `FSM_RW;
6776
        `FSM_RW:
6777
            if (!stb_i) next = `FSM_IDLE;
6778
        endcase
6779
    end
6780
 
6781
    // counter
6782
`define MODULE cnt_shreg_ce_clear
6783
    `VLBASE`MODULE # ( .length(32))
6784
`undef MODULE
6785
        cnt0 (
6786
            .clear(state!=next),
6787
            .q(shreg),
6788
            .rst(rst),
6789
            .clk(clk));
6790
 
6791
    // ba, a, cmd
6792
    // outputs dependent on state vector
6793
    always @ (*)
6794
        begin
6795
            {a,cmd} = {13'd0,cmd_nop};
6796
            dqm = 2'b11;
6797
            dq_oe = 1'b0;
6798
            stall_o = 1'b1;
6799
            case (state)
6800
            `FSM_INIT:
6801
                if (shreg[3]) begin
6802
                    {a,cmd} = {13'b0010000000000, cmd_pch};
6803
                end else if (shreg[3+tRP] | shreg[3+tRP+tRFC])
6804
                    {a,cmd} = {13'd0, cmd_rfr};
6805
                else if (shreg[3+tRP+tRFC+tRFC])
6806
                    {a,cmd} = {3'b000,init_wb,2'b00,init_cl,init_bt,init_bl,cmd_lmr};
6807
            `FSM_RFR:
6808
                if (shreg[0])
6809
                    {a,cmd} = {13'b0010000000000, cmd_pch};
6810
                else if (shreg[tRP])
6811
                    {a,cmd} = {13'd0, cmd_rfr};
6812
            `FSM_PCH:
6813
                if (shreg[0])
6814
                    {a,cmd} = {13'd0,cmd_pch};
6815
            `FSM_ACT:
6816
                if (shreg[0])
6817
                    {a[row_size-1:0],cmd} = {row,cmd_act};
6818
            `FSM_RW:
6819
                begin
6820
                    if (we_i)
6821
                        cmd = cmd_wr;
6822
                    else
6823
                        cmd = cmd_rd;
6824
                    if (we_i)
6825
                        dqm = ~sel_i;
6826
                    else
6827
                        dqm = 2'b00;
6828
                    if (we_i)
6829
                        dq_oe = 1'b1;
6830
                    a = a10_fix(col);
6831
                    stall_o = 1'b1;
6832
                end
6833
            endcase
6834
        end
6835
 
6836
    assign ba = bank;
6837
 
6838
    // precharge individual bank A10=0
6839
    // precharge all bank A10=1
6840
    genvar i;
6841
    generate
6842
    for (i=0;i<2<<ba_size-1;i=i+1) begin
6843
 
6844
        always @ (posedge clk or posedge rst)
6845
        if (rst)
6846
            {open_ba[i],open_row[i]} <= {1'b0,{row_size{1'b0}}};
6847
        else
6848
            if (cmd==cmd_pch & (a[10] | bank==i))
6849
                open_ba[i] <= 1'b0;
6850
            else if (cmd==cmd_act & bank==i)
6851
                {open_ba[i],open_row[i]} <= {1'b1,row};
6852
 
6853
    end
6854
    endgenerate
6855
 
6856
    // bank and row open ?
6857
    always @ (posedge clk or posedge rst)
6858
    if (rst)
6859
       {current_bank_closed, current_row_open} <= {1'b1, 1'b0};
6860
    else
6861
       {current_bank_closed, current_row_open} <= {!(open_ba[bank]), open_row[bank]==row};
6862
 
6863
    // refresh counter
6864
`define MODULE cnt_lfsr_zq
6865
    `VLBASE`MODULE # ( .length(rfr_length), .wrap_value (rfr_wrap_value)) ref_counter0( .zq(ref_cnt_zero), .rst(rst), .clk(clk));
6866
`undef MODULE
6867
 
6868
    always @ (posedge clk or posedge rst)
6869
    if (rst)
6870
        refresh_req <= 1'b0;
6871
    else
6872
        if (ref_cnt_zero)
6873
            refresh_req <= 1'b1;
6874
        else if (state==`FSM_RFR)
6875
            refresh_req <= 1'b0;
6876
 
6877
    assign dat_o = dq_i;
6878
 
6879
    assign ack_wr = (state==`FSM_RW & count0 & we_i);
6880
`define MODULE delay_emptyflag
6881
    `VLBASE`MODULE # ( .depth(cl+2)) delay0 ( .d(state==`FSM_RW & stb_i & !we_i), .q(ack_rd), .emptyflag(rd_ack_emptyflag), .clk(clk), .rst(rst));
6882
`undef MODULE
6883
    assign ack_o = ack_rd | ack_wr;
6884
 
6885
    assign dq_o = dat_i;
6886
 
6887
endmodule
6888
`endif
6889 18 unneback
//////////////////////////////////////////////////////////////////////
6890
////                                                              ////
6891
////  Arithmetic functions                                        ////
6892
////                                                              ////
6893
////  Description                                                 ////
6894
////  Arithmetic functions for ALU and DSP                        ////
6895
////                                                              ////
6896
////                                                              ////
6897
////  To Do:                                                      ////
6898
////   -                                                          ////
6899
////                                                              ////
6900
////  Author(s):                                                  ////
6901
////      - Michael Unneback, unneback@opencores.org              ////
6902
////        ORSoC AB                                              ////
6903
////                                                              ////
6904
//////////////////////////////////////////////////////////////////////
6905
////                                                              ////
6906
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
6907
////                                                              ////
6908
//// This source file may be used and distributed without         ////
6909
//// restriction provided that this copyright statement is not    ////
6910
//// removed from the file and that any derivative work contains  ////
6911
//// the original copyright notice and the associated disclaimer. ////
6912
////                                                              ////
6913
//// This source file is free software; you can redistribute it   ////
6914
//// and/or modify it under the terms of the GNU Lesser General   ////
6915
//// Public License as published by the Free Software Foundation; ////
6916
//// either version 2.1 of the License, or (at your option) any   ////
6917
//// later version.                                               ////
6918
////                                                              ////
6919
//// This source is distributed in the hope that it will be       ////
6920
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
6921
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
6922
//// PURPOSE.  See the GNU Lesser General Public License for more ////
6923
//// details.                                                     ////
6924
////                                                              ////
6925
//// You should have received a copy of the GNU Lesser General    ////
6926
//// Public License along with this source; if not, download it   ////
6927
//// from http://www.opencores.org/lgpl.shtml                     ////
6928
////                                                              ////
6929
//////////////////////////////////////////////////////////////////////
6930
 
6931 40 unneback
`ifdef MULTS
6932 18 unneback
// signed multiplication
6933 40 unneback
`define MODULE mults
6934
module `BASE`MODULE (a,b,p);
6935
`undef MODULE
6936 18 unneback
parameter operand_a_width = 18;
6937
parameter operand_b_width = 18;
6938
parameter result_hi = 35;
6939
parameter result_lo = 0;
6940
input [operand_a_width-1:0] a;
6941
input [operand_b_width-1:0] b;
6942
output [result_hi:result_lo] p;
6943
wire signed [operand_a_width-1:0] ai;
6944
wire signed [operand_b_width-1:0] bi;
6945
wire signed [operand_a_width+operand_b_width-1:0] result;
6946
 
6947
    assign ai = a;
6948
    assign bi = b;
6949
    assign result = ai * bi;
6950
    assign p = result[result_hi:result_lo];
6951
 
6952
endmodule
6953 40 unneback
`endif
6954
`ifdef MULTS18X18
6955
`define MODULE mults18x18
6956
module `BASE`MODULE (a,b,p);
6957
`undef MODULE
6958 18 unneback
input [17:0] a,b;
6959
output [35:0] p;
6960
vl_mult
6961
    # (.operand_a_width(18), .operand_b_width(18))
6962
    mult0 (.a(a), .b(b), .p(p));
6963
endmodule
6964 40 unneback
`endif
6965 18 unneback
 
6966 40 unneback
`ifdef MULT
6967
`define MODULE mult
6968 18 unneback
// unsigned multiplication
6969 40 unneback
module `BASE`MODULE (a,b,p);
6970
`undef MODULE
6971 18 unneback
parameter operand_a_width = 18;
6972
parameter operand_b_width = 18;
6973
parameter result_hi = 35;
6974
parameter result_lo = 0;
6975
input [operand_a_width-1:0] a;
6976
input [operand_b_width-1:0] b;
6977
output [result_hi:result_hi] p;
6978
 
6979
wire [operand_a_width+operand_b_width-1:0] result;
6980
 
6981
    assign result = a * b;
6982
    assign p = result[result_hi:result_lo];
6983
 
6984
endmodule
6985 40 unneback
`endif
6986 18 unneback
 
6987 40 unneback
`ifdef SHIFT_UNIT_32
6988
`define MODULE shift_unit_32
6989 18 unneback
// shift unit
6990
// supporting the following shift functions
6991
//   SLL
6992
//   SRL
6993
//   SRA
6994
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
6995 40 unneback
module `BASE`MODULE( din, s, dout, opcode);
6996
`undef MODULE
6997 18 unneback
input [31:0] din; // data in operand
6998
input [4:0] s; // shift operand
6999
input [1:0] opcode;
7000
output [31:0] dout;
7001
 
7002
parameter opcode_sll = 2'b00;
7003
//parameter opcode_srl = 2'b01;
7004
parameter opcode_sra = 2'b10;
7005
//parameter opcode_ror = 2'b11;
7006
 
7007
wire sll, sra;
7008
assign sll = opcode == opcode_sll;
7009
assign sra = opcode == opcode_sra;
7010
 
7011
wire [15:1] s1;
7012
wire [3:0] sign;
7013
wire [7:0] tmp [0:3];
7014
 
7015
// first stage is multiplier based
7016
// shift operand as fractional 8.7
7017
assign s1[15] = sll & s[2:0]==3'd7;
7018
assign s1[14] = sll & s[2:0]==3'd6;
7019
assign s1[13] = sll & s[2:0]==3'd5;
7020
assign s1[12] = sll & s[2:0]==3'd4;
7021
assign s1[11] = sll & s[2:0]==3'd3;
7022
assign s1[10] = sll & s[2:0]==3'd2;
7023
assign s1[ 9] = sll & s[2:0]==3'd1;
7024
assign s1[ 8] = s[2:0]==3'd0;
7025
assign s1[ 7] = !sll & s[2:0]==3'd1;
7026
assign s1[ 6] = !sll & s[2:0]==3'd2;
7027
assign s1[ 5] = !sll & s[2:0]==3'd3;
7028
assign s1[ 4] = !sll & s[2:0]==3'd4;
7029
assign s1[ 3] = !sll & s[2:0]==3'd5;
7030
assign s1[ 2] = !sll & s[2:0]==3'd6;
7031
assign s1[ 1] = !sll & s[2:0]==3'd7;
7032
 
7033
assign sign[3] = din[31] & sra;
7034
assign sign[2] = sign[3] & (&din[31:24]);
7035
assign sign[1] = sign[2] & (&din[23:16]);
7036
assign sign[0] = sign[1] & (&din[15:8]);
7037 40 unneback
`define MODULE mults
7038
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
7039
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
7040
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
7041
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
7042
`undef MODULE
7043 18 unneback
// second stage is multiplexer based
7044
// shift on byte level
7045
 
7046
// mux byte 3
7047
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
7048
                     (sll & s[4:3]==2'b01) ? tmp[2] :
7049
                     (sll & s[4:3]==2'b10) ? tmp[1] :
7050
                     (sll & s[4:3]==2'b11) ? tmp[0] :
7051
                     {8{sign[3]}};
7052
 
7053
// mux byte 2
7054
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
7055
                     (sll & s[4:3]==2'b01) ? tmp[1] :
7056
                     (sll & s[4:3]==2'b10) ? tmp[0] :
7057
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
7058
                     (s[4:3]==2'b01) ? tmp[3] :
7059
                     {8{sign[3]}};
7060
 
7061
// mux byte 1
7062
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
7063
                     (sll & s[4:3]==2'b01) ? tmp[0] :
7064
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
7065
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
7066
                     (s[4:3]==2'b01) ? tmp[2] :
7067
                     (s[4:3]==2'b10) ? tmp[3] :
7068
                     {8{sign[3]}};
7069
 
7070
// mux byte 0
7071
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
7072
                     (sll) ?  {8{1'b0}}:
7073
                     (s[4:3]==2'b01) ? tmp[1] :
7074
                     (s[4:3]==2'b10) ? tmp[2] :
7075
                     tmp[3];
7076
 
7077
endmodule
7078 40 unneback
`endif
7079 18 unneback
 
7080 40 unneback
`ifdef LOGIC_UNIT
7081 18 unneback
// logic unit
7082
// supporting the following logic functions
7083
//    a and b
7084
//    a or  b
7085
//    a xor b
7086
//    not b
7087 40 unneback
`define MODULE logic_unit
7088
module `BASE`MODULE( a, b, result, opcode);
7089
`undef MODULE
7090 18 unneback
parameter width = 32;
7091
parameter opcode_and = 2'b00;
7092
parameter opcode_or  = 2'b01;
7093
parameter opcode_xor = 2'b10;
7094
input [width-1:0] a,b;
7095
output [width-1:0] result;
7096
input [1:0] opcode;
7097
 
7098
assign result = (opcode==opcode_and) ? a & b :
7099
                (opcode==opcode_or)  ? a | b :
7100
                (opcode==opcode_xor) ? a ^ b :
7101
                b;
7102
 
7103
endmodule
7104 48 unneback
`endif
7105 18 unneback
 
7106 48 unneback
`ifdef ARITH_UNIT
7107
`define MODULE arith_unit
7108
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
7109
`undef MODULE
7110 18 unneback
parameter width = 32;
7111
parameter opcode_add = 1'b0;
7112
parameter opcode_sub = 1'b1;
7113
input [width-1:0] a,b;
7114
input c_in, add_sub, sign;
7115
output [width-1:0] result;
7116
output c_out, z, ovfl;
7117
 
7118
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
7119
assign z = (result=={width{1'b0}});
7120
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
7121
               (~a[width-1] & ~b[width-1] &  result[width-1]);
7122
endmodule
7123 40 unneback
`endif
7124 48 unneback
 
7125
`ifdef COUNT_UNIT
7126
`define MODULE count_unit
7127
module `BASE`MODULE (din, dout, opcode);
7128
`undef MODULE
7129
parameter width = 32;
7130
input [width-1:0] din;
7131
output [width-1:0] dout;
7132
input opcode;
7133
 
7134
integer i;
7135 58 unneback
wire [width/32+4:0] ff1, fl1;
7136 48 unneback
 
7137 57 unneback
/*
7138 48 unneback
always @(din) begin
7139
    ff1 = 0; i = 0;
7140
    while (din[i] == 0 && i < width) begin // complex condition
7141
        ff1 = ff1 + 1;
7142
        i = i + 1;
7143
    end
7144
end
7145
 
7146
always @(din) begin
7147
    fl1 = width; i = width-1;
7148
    while (din[i] == 0 && i >= width) begin // complex condition
7149
        fl1 = fl1 - 1;
7150
        i = i - 1;
7151
    end
7152
end
7153 57 unneback
*/
7154 48 unneback
 
7155
generate
7156
if (width==32) begin
7157 57 unneback
 
7158
    assign ff1 = din[0] ? 6'd1 :
7159
                 din[1] ? 6'd2 :
7160
                 din[2] ? 6'd3 :
7161
                 din[3] ? 6'd4 :
7162
                 din[4] ? 6'd5 :
7163
                 din[5] ? 6'd6 :
7164
                 din[6] ? 6'd7 :
7165
                 din[7] ? 6'd8 :
7166
                 din[8] ? 6'd9 :
7167
                 din[9] ? 6'd10 :
7168
                 din[10] ? 6'd11 :
7169
                 din[11] ? 6'd12 :
7170
                 din[12] ? 6'd13 :
7171
                 din[13] ? 6'd14 :
7172
                 din[14] ? 6'd15 :
7173
                 din[15] ? 6'd16 :
7174
                 din[16] ? 6'd17 :
7175
                 din[17] ? 6'd18 :
7176
                 din[18] ? 6'd19 :
7177
                 din[19] ? 6'd20 :
7178
                 din[20] ? 6'd21 :
7179
                 din[21] ? 6'd22 :
7180
                 din[22] ? 6'd23 :
7181
                 din[23] ? 6'd24 :
7182
                 din[24] ? 6'd25 :
7183
                 din[25] ? 6'd26 :
7184
                 din[26] ? 6'd27 :
7185
                 din[27] ? 6'd28 :
7186
                 din[28] ? 6'd29 :
7187
                 din[29] ? 6'd30 :
7188
                 din[30] ? 6'd31 :
7189
                 din[31] ? 6'd32 :
7190
                 6'd0;
7191
 
7192
    assign fl1 = din[31] ? 6'd32 :
7193
                 din[30] ? 6'd31 :
7194
                 din[29] ? 6'd30 :
7195
                 din[28] ? 6'd29 :
7196
                 din[27] ? 6'd28 :
7197
                 din[26] ? 6'd27 :
7198
                 din[25] ? 6'd26 :
7199
                 din[24] ? 6'd25 :
7200
                 din[23] ? 6'd24 :
7201
                 din[22] ? 6'd23 :
7202
                 din[21] ? 6'd22 :
7203
                 din[20] ? 6'd21 :
7204
                 din[19] ? 6'd20 :
7205
                 din[18] ? 6'd19 :
7206
                 din[17] ? 6'd18 :
7207
                 din[16] ? 6'd17 :
7208
                 din[15] ? 6'd16 :
7209
                 din[14] ? 6'd15 :
7210
                 din[13] ? 6'd14 :
7211
                 din[12] ? 6'd13 :
7212
                 din[11] ? 6'd12 :
7213
                 din[10] ? 6'd11 :
7214
                 din[9] ? 6'd10 :
7215
                 din[8] ? 6'd9 :
7216
                 din[7] ? 6'd8 :
7217
                 din[6] ? 6'd7 :
7218
                 din[5] ? 6'd6 :
7219
                 din[4] ? 6'd5 :
7220
                 din[3] ? 6'd4 :
7221
                 din[2] ? 6'd3 :
7222
                 din[1] ? 6'd2 :
7223
                 din[0] ? 6'd1 :
7224
                 6'd0;
7225
 
7226
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
7227 48 unneback
end
7228
endgenerate
7229 57 unneback
 
7230 48 unneback
generate
7231
if (width==64) begin
7232 57 unneback
    assign ff1 = 7'd0;
7233
    assign fl1 = 7'd0;
7234
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
7235 48 unneback
end
7236
endgenerate
7237
 
7238
endmodule
7239
`endif
7240
 
7241
`ifdef EXT_UNIT
7242
`define MODULE ext_unit
7243
module `BASE`MODULE ( a, b, F, result, opcode);
7244
`undef MODULE
7245
parameter width = 32;
7246
input [width-1:0] a, b;
7247
input F;
7248
output reg [width-1:0] result;
7249
input [2:0] opcode;
7250
 
7251
generate
7252
if (width==32) begin
7253
always @ (a or b or F or opcode)
7254
begin
7255
    case (opcode)
7256
    3'b000: result = {{24{1'b0}},a[7:0]};
7257
    3'b001: result = {{24{a[7]}},a[7:0]};
7258
    3'b010: result = {{16{1'b0}},a[7:0]};
7259
    3'b011: result = {{16{a[15]}},a[15:0]};
7260
    3'b110: result = (F) ? a : b;
7261
    default: result = {b[15:0],16'h0000};
7262
    endcase
7263
end
7264
end
7265
endgenerate
7266
 
7267
generate
7268
if (width==64) begin
7269
always @ (a or b or F or opcode)
7270
begin
7271
    case (opcode)
7272
    3'b000: result = {{56{1'b0}},a[7:0]};
7273
    3'b001: result = {{56{a[7]}},a[7:0]};
7274
    3'b010: result = {{48{1'b0}},a[7:0]};
7275
    3'b011: result = {{48{a[15]}},a[15:0]};
7276 57 unneback
    3'b110: result = (F) ? a : b;
7277 48 unneback
    default: result = {32'h00000000,b[15:0],16'h0000};
7278
    endcase
7279
end
7280
end
7281
endgenerate
7282
endmodule
7283
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.