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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 137

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
14
    // ACTEL FPGA should not use logic to handle rw collision
15
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16
`else
17
    `define SYN_NO_RW_CHECK
18
`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
23
`define SYNC_RST
24
`define PLL
25
 
26
`define MULTS
27
`define MULTS18X18
28
`define MULT
29
`define SHIFT_UNIT_32
30
`define LOGIC_UNIT
31
 
32
`define CNT_SHREG_WRAP
33
`define CNT_SHREG_CE_WRAP
34 105 unneback
`define CNT_SHREG_CLEAR
35 40 unneback
`define CNT_SHREG_CE_CLEAR
36
`define CNT_SHREG_CE_CLEAR_WRAP
37
 
38
`define MUX_ANDOR
39
`define MUX2_ANDOR
40
`define MUX3_ANDOR
41
`define MUX4_ANDOR
42
`define MUX5_ANDOR
43
`define MUX6_ANDOR
44 43 unneback
`define PARITY
45 40 unneback
 
46
`define ROM_INIT
47
`define RAM
48
`define RAM_BE
49
`define DPRAM_1R1W
50
`define DPRAM_2R1W
51 100 unneback
`define DPRAM_1R2W
52 40 unneback
`define DPRAM_2R2W
53 75 unneback
`define DPRAM_BE_2R2W
54 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
55
`define FIFO_2R2W_SYNC_SIMPLEX
56
`define FIFO_CMP_ASYNC
57
`define FIFO_1R1W_ASYNC
58
`define FIFO_2R2W_ASYNC
59
`define FIFO_2R2W_ASYNC_SIMPLEX
60 48 unneback
`define REG_FILE
61 40 unneback
 
62
`define DFF
63
`define DFF_ARRAY
64
`define DFF_CE
65
`define DFF_CE_CLEAR
66
`define DF_CE_SET
67
`define SPR
68
`define SRP
69
`define DFF_SR
70
`define LATCH
71
`define SHREG
72
`define SHREG_CE
73
`define DELAY
74
`define DELAY_EMPTYFLAG
75 94 unneback
`define PULSE2TOGGLE
76
`define TOGGLE2PULSE
77
`define SYNCHRONIZER
78
`define CDC
79 40 unneback
 
80 75 unneback
`define WB3AVALON_BRIDGE
81 40 unneback
`define WB3WB3_BRIDGE
82
`define WB3_ARBITER_TYPE1
83 83 unneback
`define WB_ADR_INC
84 101 unneback
`define WB_RAM
85 103 unneback
`define WB_SHADOW_RAM
86 48 unneback
`define WB_B4_ROM
87 40 unneback
`define WB_BOOT_ROM
88
`define WB_DPRAM
89 101 unneback
`define WB_CACHE
90 103 unneback
`define WB_AVALON_BRIDGE
91
`define WB_AVALON_MEM_CACHE
92 136 unneback
`define WB_SDR_SDRAM_CTRL
93 40 unneback
 
94 44 unneback
`define IO_DFF_OE
95
`define O_DFF
96 136 unneback
`define O_DDR
97
`define O_CLK
98 44 unneback
 
99 40 unneback
`endif
100
 
101 136 unneback
///////////////////////////////////////
102
// dependencies
103
///////////////////////////////////////
104
 
105 40 unneback
`ifdef PLL
106
`ifndef SYNC_RST
107
`define SYNC_RST
108
`endif
109
`endif
110
 
111
`ifdef SYNC_RST
112
`ifndef GBUF
113
`define GBUF
114
`endif
115
`endif
116
 
117 136 unneback
`ifdef WB_SDR_SDRAM_CTRL
118
`ifndef WB_SHADOW_RAM
119
`define WB_SHADOW_RAM
120
`endif
121
`ifndef WB_CACHE
122
`define WB_CACHE
123
`endif
124
`ifndef WB_SDR_SDRAM
125
`define WB_SDR_SDRAM
126
`endif
127
`ifndef IO_DFF_OE
128
`define IO_DFF_OE
129
`endif
130
`ifndef O_DFF
131
`define O_DFF
132
`endif
133
`ifndef O_CLK
134
`define O_CLK
135
`endif
136
`endif
137
 
138
`ifdef WB_SDR_SDRAM
139
`ifndef CNT_SHREG_CLEAR
140
`define CNT_SHREG_CLEAR
141
`endif
142
`ifndef CNT_LFSR_ZQ
143
`define CNT_LFSR_ZQ
144
`endif
145
`ifndef DELAY_EMPTYFLAG
146
`define DELAY_EMPTYFLAG
147
`endif
148
`endif
149
 
150 108 unneback
`ifdef WB_DPRAM
151 92 unneback
`ifndef WB_ADR_INC
152
`define WB_ADR_INC
153 40 unneback
`endif
154 92 unneback
`ifndef DPRAM_BE_2R2W
155
`define DPRAM_BE_2R2W
156 40 unneback
`endif
157
`endif
158
 
159
`ifdef WB3_ARBITER_TYPE1
160 42 unneback
`ifndef SPR
161
`define SPR
162
`endif
163 40 unneback
`ifndef MUX_ANDOR
164
`define MUX_ANDOR
165
`endif
166
`endif
167
 
168 76 unneback
`ifdef WB3AVALON_BRIDGE
169
`ifndef WB3WB3_BRIDGE
170
`define WB3WB3_BRIDGE
171
`endif
172
`endif
173
 
174 40 unneback
`ifdef WB3WB3_BRIDGE
175
`ifndef CNT_SHREG_CE_CLEAR
176
`define CNT_SHREG_CE_CLEAR
177
`endif
178
`ifndef DFF
179
`define DFF
180
`endif
181
`ifndef DFF_CE
182
`define DFF_CE
183
`endif
184
`ifndef CNT_SHREG_CE_CLEAR
185
`define CNT_SHREG_CE_CLEAR
186
`endif
187
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
188
`define FIFO_2R2W_ASYNC_SIMPLEX
189
`endif
190
`endif
191
 
192 103 unneback
 
193
`ifdef WB_AVALON_MEM_CACHE
194
`ifndef WB_SHADOW_RAM
195
`define WB_SHADOW_RAM
196
`endif
197
`ifndef WB_CACHE
198
`define WB_CACHE
199
`endif
200
`ifndef WB_AVALON_BRIDGE
201
`define WB_AVALON_BRIDGE
202
`endif
203
`endif
204
 
205 101 unneback
`ifdef WB_CACHE
206 100 unneback
`ifndef RAM
207
`define RAM
208
`endif
209
`ifndef WB_ADR_INC
210
`define WB_ADR_INC
211
`endif
212
`ifndef DPRAM_1R1W
213
`define DPRAM_1R1W
214
`endif
215
`ifndef DPRAM_1R2W
216
`define DPRAM_1R2W
217
`endif
218
`ifndef DPRAM_BE_2R2W
219
`define DPRAM_BE_2R2W
220
`endif
221
`ifndef CDC
222
`define CDC
223
`endif
224 136 unneback
`ifndef O_DFF
225
`define O_DFF
226 100 unneback
`endif
227 136 unneback
`ifndef O_CLK
228
`define O_CLK
229
`endif
230
`endif
231 103 unneback
 
232
`ifdef WB_SHADOW_RAM
233 115 unneback
`ifndef WB_RAM
234
`define WB_RAM
235 103 unneback
`endif
236
`endif
237
 
238
`ifdef WB_RAM
239
`ifndef WB_ADR_INC
240
`define WB_ADR_INC
241
`endif
242 114 unneback
`ifndef RAM_BE
243
`define RAM_BE
244 103 unneback
`endif
245 114 unneback
`endif
246
 
247 40 unneback
`ifdef MULTS18X18
248
`ifndef MULTS
249
`define MULTS
250
`endif
251
`endif
252
 
253
`ifdef SHIFT_UNIT_32
254
`ifndef MULTS
255
`define MULTS
256
`endif
257
`endif
258
 
259
`ifdef MUX2_ANDOR
260
`ifndef MUX_ANDOR
261
`define MUX_ANDOR
262
`endif
263
`endif
264
 
265
`ifdef MUX3_ANDOR
266
`ifndef MUX_ANDOR
267
`define MUX_ANDOR
268
`endif
269
`endif
270
 
271
`ifdef MUX4_ANDOR
272
`ifndef MUX_ANDOR
273
`define MUX_ANDOR
274
`endif
275
`endif
276
 
277
`ifdef MUX5_ANDOR
278
`ifndef MUX_ANDOR
279
`define MUX_ANDOR
280
`endif
281
`endif
282
 
283
`ifdef MUX6_ANDOR
284
`ifndef MUX_ANDOR
285
`define MUX_ANDOR
286
`endif
287
`endif
288
 
289
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
290
`ifndef CNT_BIN_CE
291
`define CNT_BIN_CE
292
`endif
293
`ifndef DPRAM_1R1W
294
`define DPRAM_1R1W
295
`endif
296
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
297
`define CNT_BIN_CE_REW_Q_ZQ_L1
298
`endif
299
`endif
300
 
301
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
302
`ifndef CNT_LFSR_CE
303
`define CNT_LFSR_CE
304
`endif
305
`ifndef DPRAM_2R2W
306
`define DPRAM_2R2W
307
`endif
308
`ifndef CNT_BIN_CE_REW_ZQ_L1
309
`define CNT_BIN_CE_REW_ZQ_L1
310
`endif
311
`endif
312
 
313
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
314
`ifndef CNT_GRAY_CE_BIN
315
`define CNT_GRAY_CE_BIN
316
`endif
317
`ifndef DPRAM_2R2W
318
`define DPRAM_2R2W
319
`endif
320
`ifndef FIFO_CMP_ASYNC
321
`define FIFO_CMP_ASYNC
322
`endif
323
`endif
324
 
325
`ifdef FIFO_2R2W_ASYNC
326
`ifndef FIFO_1R1W_ASYNC
327
`define FIFO_1R1W_ASYNC
328
`endif
329
`endif
330
 
331
`ifdef FIFO_1R1W_ASYNC
332
`ifndef CNT_GRAY_CE_BIN
333
`define CNT_GRAY_CE_BIN
334
`endif
335
`ifndef DPRAM_1R1W
336
`define DPRAM_1R1W
337
`endif
338
`ifndef FIFO_CMP_ASYNC
339
`define FIFO_CMP_ASYNC
340
`endif
341
`endif
342
 
343
`ifdef FIFO_CMP_ASYNC
344
`ifndef DFF_SR
345
`define DFF_SR
346
`endif
347
`ifndef DFF
348
`define DFF
349
`endif
350
`endif
351 48 unneback
 
352
`ifdef REG_FILE
353
`ifndef DPRAM_1R1W
354
`define DPRAM_1R1W
355
`endif
356
`endif
357 97 unneback
 
358 98 unneback
`ifdef CDC
359
`ifndef PULSE2TOGGLE
360
`define PULSE2TOGGLE
361
`endif
362
`ifndef TOGGLE2PULSE
363
`define TOGGLE2PULSE
364
`endif
365
`ifndef SYNCHRONIZER
366
`define SYNCHRONIZER
367
`endif
368
`endif
369
 
370 136 unneback
`ifdef O_CLK
371
`ifndef O_DDR
372
`define O_DDR
373
`endif
374
`endif
375
 
376 97 unneback
// size to width
377 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
378 62 unneback
//////////////////////////////////////////////////////////////////////
379 6 unneback
////                                                              ////
380
////  Versatile library, clock and reset                          ////
381
////                                                              ////
382
////  Description                                                 ////
383
////  Logic related to clock and reset                            ////
384
////                                                              ////
385
////                                                              ////
386
////  To Do:                                                      ////
387
////   - add more different registers                             ////
388
////                                                              ////
389
////  Author(s):                                                  ////
390
////      - Michael Unneback, unneback@opencores.org              ////
391
////        ORSoC AB                                              ////
392
////                                                              ////
393
//////////////////////////////////////////////////////////////////////
394
////                                                              ////
395
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
396
////                                                              ////
397
//// This source file may be used and distributed without         ////
398
//// restriction provided that this copyright statement is not    ////
399
//// removed from the file and that any derivative work contains  ////
400
//// the original copyright notice and the associated disclaimer. ////
401
////                                                              ////
402
//// This source file is free software; you can redistribute it   ////
403
//// and/or modify it under the terms of the GNU Lesser General   ////
404
//// Public License as published by the Free Software Foundation; ////
405
//// either version 2.1 of the License, or (at your option) any   ////
406
//// later version.                                               ////
407
////                                                              ////
408
//// This source is distributed in the hope that it will be       ////
409
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
410
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
411
//// PURPOSE.  See the GNU Lesser General Public License for more ////
412
//// details.                                                     ////
413
////                                                              ////
414
//// You should have received a copy of the GNU Lesser General    ////
415
//// Public License along with this source; if not, download it   ////
416
//// from http://www.opencores.org/lgpl.shtml                     ////
417
////                                                              ////
418
//////////////////////////////////////////////////////////////////////
419
 
420 48 unneback
`ifdef ACTEL
421
`ifdef GBUF
422
`timescale 1 ns/100 ps
423 6 unneback
// Global buffer
424
// usage:
425
// use to enable global buffers for high fan out signals such as clock and reset
426
// Version: 8.4 8.4.0.33
427
module gbuf(GL,CLK);
428
output GL;
429
input  CLK;
430
 
431
    wire GND;
432
 
433
    GND GND_1_net(.Y(GND));
434
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
435
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
436
 
437
endmodule
438
`timescale 1 ns/1 ns
439 40 unneback
`define MODULE gbuf
440
module `BASE`MODULE ( i, o);
441
`undef MODULE
442 6 unneback
input i;
443
output o;
444
`ifdef SIM_GBUF
445
assign o=i;
446
`else
447
gbuf gbuf_i0 ( .CLK(i), .GL(o));
448
`endif
449
endmodule
450 40 unneback
`endif
451 33 unneback
 
452 6 unneback
`else
453 33 unneback
 
454 40 unneback
`ifdef ALTERA
455
`ifdef GBUF
456 21 unneback
//altera
457 40 unneback
`define MODULE gbuf
458
module `BASE`MODULE ( i, o);
459
`undef MODULE
460 33 unneback
input i;
461
output o;
462
assign o = i;
463
endmodule
464 40 unneback
`endif
465 33 unneback
 
466 6 unneback
`else
467
 
468 40 unneback
`ifdef GBUF
469 6 unneback
`timescale 1 ns/100 ps
470 40 unneback
`define MODULE
471
module `BASE`MODULE ( i, o);
472
`undef MODULE
473 6 unneback
input i;
474
output o;
475
assign o = i;
476
endmodule
477 40 unneback
`endif
478 6 unneback
`endif // ALTERA
479
`endif //ACTEL
480
 
481 40 unneback
`ifdef SYNC_RST
482 6 unneback
// sync reset
483 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
484 6 unneback
// output active high global reset sync with two DFFs 
485
`timescale 1 ns/100 ps
486 40 unneback
`define MODULE sync_rst
487
module `BASE`MODULE ( rst_n_i, rst_o, clk);
488
`undef MODULE
489 6 unneback
input rst_n_i, clk;
490
output rst_o;
491 18 unneback
reg [1:0] tmp;
492 6 unneback
always @ (posedge clk or negedge rst_n_i)
493
if (!rst_n_i)
494 17 unneback
        tmp <= 2'b11;
495 6 unneback
else
496 33 unneback
        tmp <= {1'b0,tmp[1]};
497 40 unneback
`define MODULE gbuf
498
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
499
`undef MODULE
500 6 unneback
endmodule
501 40 unneback
`endif
502 6 unneback
 
503 40 unneback
`ifdef PLL
504 6 unneback
// vl_pll
505
`ifdef ACTEL
506 32 unneback
///////////////////////////////////////////////////////////////////////////////
507 17 unneback
`timescale 1 ps/1 ps
508 40 unneback
`define MODULE pll
509
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
510
`undef MODULE
511 6 unneback
parameter index = 0;
512
parameter number_of_clk = 1;
513 17 unneback
parameter period_time_0 = 20000;
514
parameter period_time_1 = 20000;
515
parameter period_time_2 = 20000;
516
parameter lock_delay = 2000000;
517 6 unneback
input clk_i, rst_n_i;
518
output lock;
519
output reg [0:number_of_clk-1] clk_o;
520
output [0:number_of_clk-1] rst_o;
521
 
522
`ifdef SIM_PLL
523
 
524
always
525
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
526
 
527
generate if (number_of_clk > 1)
528
always
529
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
530
endgenerate
531
 
532
generate if (number_of_clk > 2)
533
always
534
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
535
endgenerate
536
 
537
genvar i;
538
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
539
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
540
end
541
endgenerate
542
 
543
assign #lock_delay lock = rst_n_i;
544
 
545
endmodule
546
`else
547
generate if (number_of_clk==1 & index==0) begin
548
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
549
end
550
endgenerate // index==0
551
generate if (number_of_clk==1 & index==1) begin
552
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
553
end
554
endgenerate // index==1
555
generate if (number_of_clk==1 & index==2) begin
556
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
557
end
558
endgenerate // index==2
559
generate if (number_of_clk==1 & index==3) begin
560
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
561
end
562
endgenerate // index==0
563
 
564
generate if (number_of_clk==2 & index==0) begin
565
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
566
end
567
endgenerate // index==0
568
generate if (number_of_clk==2 & index==1) begin
569
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
570
end
571
endgenerate // index==1
572
generate if (number_of_clk==2 & index==2) begin
573
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
574
end
575
endgenerate // index==2
576
generate if (number_of_clk==2 & index==3) begin
577
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
578
end
579
endgenerate // index==0
580
 
581
generate if (number_of_clk==3 & index==0) begin
582
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
583
end
584
endgenerate // index==0
585
generate if (number_of_clk==3 & index==1) begin
586
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
587
end
588
endgenerate // index==1
589
generate if (number_of_clk==3 & index==2) begin
590
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
591
end
592
endgenerate // index==2
593
generate if (number_of_clk==3 & index==3) begin
594
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
595
end
596
endgenerate // index==0
597
 
598
genvar i;
599
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
600 40 unneback
`define MODULE sync_rst
601
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
602
`undef MODULE
603 6 unneback
end
604
endgenerate
605
endmodule
606
`endif
607 32 unneback
///////////////////////////////////////////////////////////////////////////////
608 6 unneback
 
609
`else
610
 
611 32 unneback
///////////////////////////////////////////////////////////////////////////////
612 6 unneback
`ifdef ALTERA
613
 
614 32 unneback
`timescale 1 ps/1 ps
615 40 unneback
`define MODULE pll
616
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
617
`undef MODULE
618 32 unneback
parameter index = 0;
619
parameter number_of_clk = 1;
620
parameter period_time_0 = 20000;
621
parameter period_time_1 = 20000;
622
parameter period_time_2 = 20000;
623
parameter period_time_3 = 20000;
624
parameter period_time_4 = 20000;
625
parameter lock_delay = 2000000;
626
input clk_i, rst_n_i;
627
output lock;
628
output reg [0:number_of_clk-1] clk_o;
629
output [0:number_of_clk-1] rst_o;
630
 
631
`ifdef SIM_PLL
632
 
633
always
634
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
635
 
636
generate if (number_of_clk > 1)
637
always
638
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
639
endgenerate
640
 
641
generate if (number_of_clk > 2)
642
always
643
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
644
endgenerate
645
 
646 33 unneback
generate if (number_of_clk > 3)
647 32 unneback
always
648
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
649
endgenerate
650
 
651 33 unneback
generate if (number_of_clk > 4)
652 32 unneback
always
653
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
654
endgenerate
655
 
656
genvar i;
657
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
658
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
659
end
660
endgenerate
661
 
662 33 unneback
//assign #lock_delay lock = rst_n_i;
663
assign lock = rst_n_i;
664 32 unneback
 
665
endmodule
666 6 unneback
`else
667
 
668 33 unneback
`ifdef VL_PLL0
669
`ifdef VL_PLL0_CLK1
670
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
671
`endif
672
`ifdef VL_PLL0_CLK2
673
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
674
`endif
675
`ifdef VL_PLL0_CLK3
676
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
677
`endif
678
`ifdef VL_PLL0_CLK4
679
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
680
`endif
681
`ifdef VL_PLL0_CLK5
682
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
683
`endif
684
`endif
685 32 unneback
 
686 33 unneback
`ifdef VL_PLL1
687
`ifdef VL_PLL1_CLK1
688
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
689
`endif
690
`ifdef VL_PLL1_CLK2
691
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
692
`endif
693
`ifdef VL_PLL1_CLK3
694
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
695
`endif
696
`ifdef VL_PLL1_CLK4
697
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
698
`endif
699
`ifdef VL_PLL1_CLK5
700
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
701
`endif
702
`endif
703 32 unneback
 
704 33 unneback
`ifdef VL_PLL2
705
`ifdef VL_PLL2_CLK1
706
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
707
`endif
708
`ifdef VL_PLL2_CLK2
709
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
710
`endif
711
`ifdef VL_PLL2_CLK3
712
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
713
`endif
714
`ifdef VL_PLL2_CLK4
715
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
716
`endif
717
`ifdef VL_PLL2_CLK5
718
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
719
`endif
720
`endif
721 32 unneback
 
722 33 unneback
`ifdef VL_PLL3
723
`ifdef VL_PLL3_CLK1
724
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
725
`endif
726
`ifdef VL_PLL3_CLK2
727
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
728
`endif
729
`ifdef VL_PLL3_CLK3
730
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
731
`endif
732
`ifdef VL_PLL3_CLK4
733
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
734
`endif
735
`ifdef VL_PLL3_CLK5
736
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
737
`endif
738
`endif
739 32 unneback
 
740
genvar i;
741
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
742 40 unneback
`define MODULE sync_rst
743
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
744
`undef MODULE
745 32 unneback
end
746
endgenerate
747
endmodule
748
`endif
749
///////////////////////////////////////////////////////////////////////////////
750
 
751
`else
752
 
753 6 unneback
// generic PLL
754 17 unneback
`timescale 1 ps/1 ps
755 40 unneback
`define MODULE pll
756
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
757
`undef MODULE
758 6 unneback
parameter index = 0;
759
parameter number_of_clk = 1;
760 17 unneback
parameter period_time_0 = 20000;
761
parameter period_time_1 = 20000;
762
parameter period_time_2 = 20000;
763 6 unneback
parameter lock_delay = 2000;
764
input clk_i, rst_n_i;
765
output lock;
766
output reg [0:number_of_clk-1] clk_o;
767
output [0:number_of_clk-1] rst_o;
768
 
769
always
770
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
771
 
772
generate if (number_of_clk > 1)
773
always
774
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
775
endgenerate
776
 
777
generate if (number_of_clk > 2)
778
always
779
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
780
endgenerate
781
 
782
genvar i;
783
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
784 40 unneback
`define MODULE sync_rst
785
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
786
`undef MODULE
787 6 unneback
end
788
endgenerate
789
 
790
assign #lock_delay lock = rst_n_i;
791
 
792
endmodule
793
 
794
`endif //altera
795 17 unneback
`endif //actel
796 40 unneback
`undef MODULE
797
`endif//////////////////////////////////////////////////////////////////////
798 6 unneback
////                                                              ////
799
////  Versatile library, registers                                ////
800
////                                                              ////
801
////  Description                                                 ////
802
////  Different type of registers                                 ////
803
////                                                              ////
804
////                                                              ////
805
////  To Do:                                                      ////
806
////   - add more different registers                             ////
807
////                                                              ////
808
////  Author(s):                                                  ////
809
////      - Michael Unneback, unneback@opencores.org              ////
810
////        ORSoC AB                                              ////
811
////                                                              ////
812
//////////////////////////////////////////////////////////////////////
813
////                                                              ////
814
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
815
////                                                              ////
816
//// This source file may be used and distributed without         ////
817
//// restriction provided that this copyright statement is not    ////
818
//// removed from the file and that any derivative work contains  ////
819
//// the original copyright notice and the associated disclaimer. ////
820
////                                                              ////
821
//// This source file is free software; you can redistribute it   ////
822
//// and/or modify it under the terms of the GNU Lesser General   ////
823
//// Public License as published by the Free Software Foundation; ////
824
//// either version 2.1 of the License, or (at your option) any   ////
825
//// later version.                                               ////
826
////                                                              ////
827
//// This source is distributed in the hope that it will be       ////
828
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
829
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
830
//// PURPOSE.  See the GNU Lesser General Public License for more ////
831
//// details.                                                     ////
832
////                                                              ////
833
//// You should have received a copy of the GNU Lesser General    ////
834
//// Public License along with this source; if not, download it   ////
835
//// from http://www.opencores.org/lgpl.shtml                     ////
836
////                                                              ////
837
//////////////////////////////////////////////////////////////////////
838
 
839 40 unneback
`ifdef DFF
840
`define MODULE dff
841
module `BASE`MODULE ( d, q, clk, rst);
842
`undef MODULE
843 6 unneback
        parameter width = 1;
844
        parameter reset_value = 0;
845
 
846
        input [width-1:0] d;
847
        input clk, rst;
848
        output reg [width-1:0] q;
849
 
850
        always @ (posedge clk or posedge rst)
851
        if (rst)
852
                q <= reset_value;
853
        else
854
                q <= d;
855
 
856
endmodule
857 40 unneback
`endif
858 6 unneback
 
859 40 unneback
`ifdef DFF_ARRAY
860
`define MODULE dff_array
861
module `BASE`MODULE ( d, q, clk, rst);
862
`undef MODULE
863 6 unneback
 
864
        parameter width = 1;
865
        parameter depth = 2;
866
        parameter reset_value = 1'b0;
867
 
868
        input [width-1:0] d;
869
        input clk, rst;
870
        output [width-1:0] q;
871
        reg  [0:depth-1] q_tmp [width-1:0];
872
        integer i;
873
        always @ (posedge clk or posedge rst)
874
        if (rst) begin
875
            for (i=0;i<depth;i=i+1)
876
                q_tmp[i] <= {width{reset_value}};
877
        end else begin
878
            q_tmp[0] <= d;
879
            for (i=1;i<depth;i=i+1)
880
                q_tmp[i] <= q_tmp[i-1];
881
        end
882
 
883
    assign q = q_tmp[depth-1];
884
 
885
endmodule
886 40 unneback
`endif
887 6 unneback
 
888 40 unneback
`ifdef DFF_CE
889
`define MODULE dff_ce
890
module `BASE`MODULE ( d, ce, q, clk, rst);
891
`undef MODULE
892 6 unneback
 
893
        parameter width = 1;
894
        parameter reset_value = 0;
895
 
896
        input [width-1:0] d;
897
        input ce, clk, rst;
898
        output reg [width-1:0] q;
899
 
900
        always @ (posedge clk or posedge rst)
901
        if (rst)
902
                q <= reset_value;
903
        else
904
                if (ce)
905
                        q <= d;
906
 
907
endmodule
908 40 unneback
`endif
909 6 unneback
 
910 40 unneback
`ifdef DFF_CE_CLEAR
911
`define MODULE dff_ce_clear
912
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
913
`undef MODULE
914 8 unneback
 
915
        parameter width = 1;
916
        parameter reset_value = 0;
917
 
918
        input [width-1:0] d;
919 10 unneback
        input ce, clear, clk, rst;
920 8 unneback
        output reg [width-1:0] q;
921
 
922
        always @ (posedge clk or posedge rst)
923
        if (rst)
924
            q <= reset_value;
925
        else
926
            if (ce)
927
                if (clear)
928
                    q <= {width{1'b0}};
929
                else
930
                    q <= d;
931
 
932
endmodule
933 40 unneback
`endif
934 8 unneback
 
935 40 unneback
`ifdef DF_CE_SET
936
`define MODULE dff_ce_set
937
module `BASE`MODULE ( d, ce, set, q, clk, rst);
938
`undef MODULE
939 24 unneback
 
940
        parameter width = 1;
941
        parameter reset_value = 0;
942
 
943
        input [width-1:0] d;
944
        input ce, set, clk, rst;
945
        output reg [width-1:0] q;
946
 
947
        always @ (posedge clk or posedge rst)
948
        if (rst)
949
            q <= reset_value;
950
        else
951
            if (ce)
952
                if (set)
953
                    q <= {width{1'b1}};
954
                else
955
                    q <= d;
956
 
957
endmodule
958 40 unneback
`endif
959 24 unneback
 
960 40 unneback
`ifdef SPR
961
`define MODULE spr
962
module `BASE`MODULE ( sp, r, q, clk, rst);
963
`undef MODULE
964
 
965 64 unneback
        //parameter width = 1;
966
        parameter reset_value = 1'b0;
967 29 unneback
 
968
        input sp, r;
969
        output reg q;
970
        input clk, rst;
971
 
972
        always @ (posedge clk or posedge rst)
973
        if (rst)
974
            q <= reset_value;
975
        else
976
            if (sp)
977
                q <= 1'b1;
978
            else if (r)
979
                q <= 1'b0;
980
 
981
endmodule
982 40 unneback
`endif
983 29 unneback
 
984 40 unneback
`ifdef SRP
985
`define MODULE srp
986
module `BASE`MODULE ( s, rp, q, clk, rst);
987
`undef MODULE
988
 
989 29 unneback
        parameter width = 1;
990
        parameter reset_value = 0;
991
 
992
        input s, rp;
993
        output reg q;
994
        input clk, rst;
995
 
996
        always @ (posedge clk or posedge rst)
997
        if (rst)
998
            q <= reset_value;
999
        else
1000
            if (rp)
1001
                q <= 1'b0;
1002
            else if (s)
1003
                q <= 1'b1;
1004
 
1005
endmodule
1006 40 unneback
`endif
1007 29 unneback
 
1008 40 unneback
`ifdef ALTERA
1009 29 unneback
 
1010 40 unneback
`ifdef DFF_SR
1011 6 unneback
// megafunction wizard: %LPM_FF%
1012
// GENERATION: STANDARD
1013
// VERSION: WM1.0
1014
// MODULE: lpm_ff 
1015
 
1016
// ============================================================
1017
// File Name: dff_sr.v
1018
// Megafunction Name(s):
1019
//                      lpm_ff
1020
//
1021
// Simulation Library Files(s):
1022
//                      lpm
1023
// ============================================================
1024
// ************************************************************
1025
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
1026
//
1027
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
1028
// ************************************************************
1029
 
1030
 
1031
//Copyright (C) 1991-2010 Altera Corporation
1032
//Your use of Altera Corporation's design tools, logic functions 
1033
//and other software and tools, and its AMPP partner logic 
1034
//functions, and any output files from any of the foregoing 
1035
//(including device programming or simulation files), and any 
1036
//associated documentation or information are expressly subject 
1037
//to the terms and conditions of the Altera Program License 
1038
//Subscription Agreement, Altera MegaCore Function License 
1039
//Agreement, or other applicable license agreement, including, 
1040
//without limitation, that your use is for the sole purpose of 
1041
//programming logic devices manufactured by Altera and sold by 
1042
//Altera or its authorized distributors.  Please refer to the 
1043
//applicable agreement for further details.
1044
 
1045
 
1046
// synopsys translate_off
1047
`timescale 1 ps / 1 ps
1048
// synopsys translate_on
1049 40 unneback
`define MODULE dff_sr
1050
module `BASE`MODULE (
1051
`undef MODULE
1052
 
1053 6 unneback
        aclr,
1054
        aset,
1055
        clock,
1056
        data,
1057
        q);
1058
 
1059
        input     aclr;
1060
        input     aset;
1061
        input     clock;
1062
        input     data;
1063
        output    q;
1064
 
1065
        wire [0:0] sub_wire0;
1066
        wire [0:0] sub_wire1 = sub_wire0[0:0];
1067
        wire  q = sub_wire1;
1068
        wire  sub_wire2 = data;
1069
        wire  sub_wire3 = sub_wire2;
1070
 
1071
        lpm_ff  lpm_ff_component (
1072
                                .aclr (aclr),
1073
                                .clock (clock),
1074
                                .data (sub_wire3),
1075
                                .aset (aset),
1076
                                .q (sub_wire0)
1077
                                // synopsys translate_off
1078
                                ,
1079
                                .aload (),
1080
                                .enable (),
1081
                                .sclr (),
1082
                                .sload (),
1083
                                .sset ()
1084
                                // synopsys translate_on
1085
                                );
1086
        defparam
1087
                lpm_ff_component.lpm_fftype = "DFF",
1088
                lpm_ff_component.lpm_type = "LPM_FF",
1089
                lpm_ff_component.lpm_width = 1;
1090
 
1091
 
1092
endmodule
1093
 
1094
// ============================================================
1095
// CNX file retrieval info
1096
// ============================================================
1097
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1098
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1099
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1100
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1101
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1102
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1103
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1104
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1105
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1106
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1107
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1108
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1109
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1110
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1111
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1112
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1113
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1114
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1115
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1116
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1117
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1118
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1119
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1120
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1121
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1122
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1123
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1124
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1125
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1126
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1127
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1128
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1129
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1130
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1131
// Retrieval info: LIB_FILE: lpm
1132 40 unneback
`endif
1133 6 unneback
 
1134
`else
1135
 
1136 40 unneback
`ifdef DFF_SR
1137
`define MODULE dff_sr
1138
module `BASE`MODULE ( aclr, aset, clock, data, q);
1139
`undef MODULE
1140 6 unneback
 
1141
    input         aclr;
1142
    input         aset;
1143
    input         clock;
1144
    input         data;
1145
    output reg    q;
1146
 
1147
   always @ (posedge clock or posedge aclr or posedge aset)
1148
     if (aclr)
1149
       q <= 1'b0;
1150
     else if (aset)
1151
       q <= 1'b1;
1152
     else
1153
       q <= data;
1154
 
1155
endmodule
1156 40 unneback
`endif
1157 6 unneback
 
1158
`endif
1159
 
1160
// LATCH
1161
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1162
`ifdef ALTERA
1163 40 unneback
 
1164
`ifdef LATCH
1165
`define MODULE latch
1166
module `BASE`MODULE ( d, le, q, clk);
1167
`undef MODULE
1168 6 unneback
input d, le;
1169
output q;
1170
input clk;
1171
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1172
endmodule
1173 40 unneback
`endif
1174
 
1175 6 unneback
`else
1176 40 unneback
 
1177
`ifdef LATCH
1178
`define MODULE latch
1179
module `BASE`MODULE ( d, le, q, clk);
1180
`undef MODULE
1181 6 unneback
input d, le;
1182 48 unneback
input clk;
1183
always @ (le or d)
1184 60 unneback
if (le)
1185 48 unneback
    d <= q;
1186 6 unneback
endmodule
1187 15 unneback
`endif
1188
 
1189 40 unneback
`endif
1190
 
1191
`ifdef SHREG
1192
`define MODULE shreg
1193
module `BASE`MODULE ( d, q, clk, rst);
1194
`undef MODULE
1195
 
1196 17 unneback
parameter depth = 10;
1197
input d;
1198
output q;
1199
input clk, rst;
1200
 
1201
reg [1:depth] dffs;
1202
 
1203
always @ (posedge clk or posedge rst)
1204
if (rst)
1205
    dffs <= {depth{1'b0}};
1206
else
1207
    dffs <= {d,dffs[1:depth-1]};
1208
assign q = dffs[depth];
1209
endmodule
1210 40 unneback
`endif
1211 17 unneback
 
1212 40 unneback
`ifdef SHREG_CE
1213
`define MODULE shreg_ce
1214
module `BASE`MODULE ( d, ce, q, clk, rst);
1215
`undef MODULE
1216 17 unneback
parameter depth = 10;
1217
input d, ce;
1218
output q;
1219
input clk, rst;
1220
 
1221
reg [1:depth] dffs;
1222
 
1223
always @ (posedge clk or posedge rst)
1224
if (rst)
1225
    dffs <= {depth{1'b0}};
1226
else
1227
    if (ce)
1228
        dffs <= {d,dffs[1:depth-1]};
1229
assign q = dffs[depth];
1230
endmodule
1231 40 unneback
`endif
1232 17 unneback
 
1233 40 unneback
`ifdef DELAY
1234
`define MODULE delay
1235
module `BASE`MODULE ( d, q, clk, rst);
1236
`undef MODULE
1237 15 unneback
parameter depth = 10;
1238
input d;
1239
output q;
1240
input clk, rst;
1241
 
1242
reg [1:depth] dffs;
1243
 
1244
always @ (posedge clk or posedge rst)
1245
if (rst)
1246
    dffs <= {depth{1'b0}};
1247
else
1248
    dffs <= {d,dffs[1:depth-1]};
1249
assign q = dffs[depth];
1250 17 unneback
endmodule
1251 40 unneback
`endif
1252 17 unneback
 
1253 40 unneback
`ifdef DELAY_EMPTYFLAG
1254
`define MODULE delay_emptyflag
1255 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1256 40 unneback
`undef MODULE
1257 17 unneback
parameter depth = 10;
1258
input d;
1259
output q, emptyflag;
1260
input clk, rst;
1261
 
1262
reg [1:depth] dffs;
1263
 
1264
always @ (posedge clk or posedge rst)
1265
if (rst)
1266
    dffs <= {depth{1'b0}};
1267
else
1268
    dffs <= {d,dffs[1:depth-1]};
1269
assign q = dffs[depth];
1270
assign emptyflag = !(|dffs);
1271
endmodule
1272 40 unneback
`endif
1273 75 unneback
 
1274 94 unneback
`ifdef PULSE2TOGGLE
1275 98 unneback
`define MODULE pulse2toggle
1276
module `BASE`MODULE ( pl, q, clk, rst);
1277 75 unneback
`undef MODULE
1278 94 unneback
input pl;
1279 98 unneback
output reg q;
1280 94 unneback
input clk, rst;
1281
always @ (posedge clk or posedge rst)
1282 75 unneback
if (rst)
1283 94 unneback
    q <= 1'b0;
1284 75 unneback
else
1285 94 unneback
    q <= pl ^ q;
1286
endmodule
1287
`endif
1288 75 unneback
 
1289 94 unneback
`ifdef TOGGLE2PULSE
1290 98 unneback
`define MODULE toggle2pulse
1291 94 unneback
module `BASE`MODULE (d, pl, clk, rst);
1292 97 unneback
`undef MODULE
1293 94 unneback
input d;
1294
output pl;
1295
input clk, rst;
1296
reg dff;
1297
always @ (posedge clk or posedge rst)
1298
if (rst)
1299
    dff <= 1'b0;
1300 75 unneback
else
1301 94 unneback
    dff <= d;
1302 98 unneback
assign pl = d ^ dff;
1303 94 unneback
endmodule
1304
`endif
1305 75 unneback
 
1306 94 unneback
`ifdef SYNCHRONIZER
1307
`define MODULE synchronizer
1308
module `BASE`MODULE (d, q, clk, rst);
1309
`undef MODULE
1310
input d;
1311
output reg q;
1312 116 unneback
input clk, rst;
1313 94 unneback
reg dff;
1314
always @ (posedge clk or posedge rst)
1315
if (rst)
1316 100 unneback
    {q,dff} <= 2'b00;
1317 75 unneback
else
1318 100 unneback
    {q,dff} <= {dff,d};
1319 94 unneback
endmodule
1320
`endif
1321 75 unneback
 
1322 94 unneback
`ifdef CDC
1323
`define MODULE cdc
1324 97 unneback
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1325 94 unneback
`undef MODULE
1326
input start_pl;
1327
output take_it_pl;
1328
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1329
output got_it_pl;
1330
input clk_src, rst_src;
1331
input clk_dst, rst_dst;
1332
wire take_it_tg, take_it_tg_sync;
1333
wire got_it_tg, got_it_tg_sync;
1334
// src -> dst
1335
`define MODULE pulse2toggle
1336
`BASE`MODULE p2t0 (
1337
`undef MODULE
1338
    .pl(start_pl),
1339
    .q(take_it_tg),
1340
    .clk(clk_src),
1341
    .rst(rst_src));
1342 75 unneback
 
1343 94 unneback
`define MODULE synchronizer
1344
`BASE`MODULE sync0 (
1345
`undef MODULE
1346
    .d(take_it_tg),
1347
    .q(take_it_tg_sync),
1348
    .clk(clk_dst),
1349
    .rst(rst_dst));
1350
 
1351
`define MODULE toggle2pulse
1352
`BASE`MODULE t2p0 (
1353
`undef MODULE
1354 100 unneback
    .d(take_it_tg_sync),
1355 94 unneback
    .pl(take_it_pl),
1356
    .clk(clk_dst),
1357
    .rst(rst_dst));
1358
 
1359
// dst -> src
1360
`define MODULE pulse2toggle
1361 98 unneback
`BASE`MODULE p2t1 (
1362 94 unneback
`undef MODULE
1363
    .pl(take_it_grant_pl),
1364
    .q(got_it_tg),
1365
    .clk(clk_dst),
1366
    .rst(rst_dst));
1367
 
1368
`define MODULE synchronizer
1369
`BASE`MODULE sync1 (
1370
`undef MODULE
1371
    .d(got_it_tg),
1372
    .q(got_it_tg_sync),
1373
    .clk(clk_src),
1374
    .rst(rst_src));
1375
 
1376
`define MODULE toggle2pulse
1377
`BASE`MODULE t2p1 (
1378
`undef MODULE
1379 100 unneback
    .d(got_it_tg_sync),
1380 94 unneback
    .pl(got_it_pl),
1381
    .clk(clk_src),
1382
    .rst(rst_src));
1383
 
1384 75 unneback
endmodule
1385
`endif
1386 17 unneback
//////////////////////////////////////////////////////////////////////
1387 6 unneback
////                                                              ////
1388 18 unneback
////  Logic functions                                             ////
1389
////                                                              ////
1390
////  Description                                                 ////
1391
////  Logic functions such as multiplexers                        ////
1392
////                                                              ////
1393
////                                                              ////
1394
////  To Do:                                                      ////
1395
////   -                                                          ////
1396
////                                                              ////
1397
////  Author(s):                                                  ////
1398
////      - Michael Unneback, unneback@opencores.org              ////
1399
////        ORSoC AB                                              ////
1400
////                                                              ////
1401
//////////////////////////////////////////////////////////////////////
1402
////                                                              ////
1403
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1404
////                                                              ////
1405
//// This source file may be used and distributed without         ////
1406
//// restriction provided that this copyright statement is not    ////
1407
//// removed from the file and that any derivative work contains  ////
1408
//// the original copyright notice and the associated disclaimer. ////
1409
////                                                              ////
1410
//// This source file is free software; you can redistribute it   ////
1411
//// and/or modify it under the terms of the GNU Lesser General   ////
1412
//// Public License as published by the Free Software Foundation; ////
1413
//// either version 2.1 of the License, or (at your option) any   ////
1414
//// later version.                                               ////
1415
////                                                              ////
1416
//// This source is distributed in the hope that it will be       ////
1417
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1418
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1419
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1420
//// details.                                                     ////
1421
////                                                              ////
1422
//// You should have received a copy of the GNU Lesser General    ////
1423
//// Public License along with this source; if not, download it   ////
1424
//// from http://www.opencores.org/lgpl.shtml                     ////
1425
////                                                              ////
1426
//////////////////////////////////////////////////////////////////////
1427 40 unneback
`ifdef MUX_ANDOR
1428
`define MODULE mux_andor
1429
module `BASE`MODULE ( a, sel, dout);
1430
`undef MODULE
1431 36 unneback
 
1432
parameter width = 32;
1433
parameter nr_of_ports = 4;
1434
 
1435
input [nr_of_ports*width-1:0] a;
1436
input [nr_of_ports-1:0] sel;
1437
output reg [width-1:0] dout;
1438
 
1439 38 unneback
integer i,j;
1440
 
1441 36 unneback
always @ (a, sel)
1442
begin
1443
    dout = a[width-1:0] & {width{sel[0]}};
1444 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1445
        for (j=0;j<width;j=j+1)
1446
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1447 36 unneback
end
1448
 
1449
endmodule
1450 40 unneback
`endif
1451 36 unneback
 
1452 40 unneback
`ifdef MUX2_ANDOR
1453
`define MODULE mux2_andor
1454
module `BASE`MODULE ( a1, a0, sel, dout);
1455
`undef MODULE
1456 18 unneback
 
1457 34 unneback
parameter width = 32;
1458 35 unneback
localparam nr_of_ports = 2;
1459 34 unneback
input [width-1:0] a1, a0;
1460
input [nr_of_ports-1:0] sel;
1461
output [width-1:0] dout;
1462
 
1463 40 unneback
`define MODULE mux_andor
1464
`BASE`MODULE
1465 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1466 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1467 40 unneback
`undef MODULE
1468
 
1469 34 unneback
endmodule
1470 40 unneback
`endif
1471 34 unneback
 
1472 40 unneback
`ifdef MUX3_ANDOR
1473
`define MODULE mux3_andor
1474
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1475
`undef MODULE
1476 34 unneback
 
1477
parameter width = 32;
1478 35 unneback
localparam nr_of_ports = 3;
1479 34 unneback
input [width-1:0] a2, a1, a0;
1480
input [nr_of_ports-1:0] sel;
1481
output [width-1:0] dout;
1482
 
1483 40 unneback
`define MODULE mux_andor
1484
`BASE`MODULE
1485 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1486 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1487 40 unneback
`undef MODULE
1488 34 unneback
endmodule
1489 40 unneback
`endif
1490 34 unneback
 
1491 40 unneback
`ifdef MUX4_ANDOR
1492
`define MODULE mux4_andor
1493
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1494
`undef MODULE
1495 18 unneback
 
1496
parameter width = 32;
1497 35 unneback
localparam nr_of_ports = 4;
1498 18 unneback
input [width-1:0] a3, a2, a1, a0;
1499
input [nr_of_ports-1:0] sel;
1500 22 unneback
output [width-1:0] dout;
1501 18 unneback
 
1502 40 unneback
`define MODULE mux_andor
1503
`BASE`MODULE
1504 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1505 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1506 40 unneback
`undef MODULE
1507 18 unneback
 
1508
endmodule
1509 40 unneback
`endif
1510 18 unneback
 
1511 40 unneback
`ifdef MUX5_ANDOR
1512
`define MODULE mux5_andor
1513
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1514
`undef MODULE
1515 18 unneback
 
1516
parameter width = 32;
1517 35 unneback
localparam nr_of_ports = 5;
1518 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1519
input [nr_of_ports-1:0] sel;
1520 22 unneback
output [width-1:0] dout;
1521 18 unneback
 
1522 40 unneback
`define MODULE mux_andor
1523
`BASE`MODULE
1524 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1525 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1526 40 unneback
`undef MODULE
1527 18 unneback
 
1528
endmodule
1529 40 unneback
`endif
1530 18 unneback
 
1531 40 unneback
`ifdef MUX6_ANDOR
1532
`define MODULE mux6_andor
1533
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1534
`undef MODULE
1535 18 unneback
 
1536
parameter width = 32;
1537 35 unneback
localparam nr_of_ports = 6;
1538 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1539
input [nr_of_ports-1:0] sel;
1540 22 unneback
output [width-1:0] dout;
1541 18 unneback
 
1542 40 unneback
`define MODULE mux_andor
1543
`BASE`MODULE
1544 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1545 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1546 40 unneback
`undef MODULE
1547 18 unneback
 
1548
endmodule
1549 40 unneback
`endif
1550 43 unneback
 
1551
`ifdef PARITY
1552
 
1553
`define MODULE parity_generate
1554
module `BASE`MODULE (data, parity);
1555
`undef MODULE
1556
parameter word_size = 32;
1557
parameter chunk_size = 8;
1558
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1559
input [word_size-1:0] data;
1560
output reg [word_size/chunk_size-1:0] parity;
1561
integer i,j;
1562
always @ (data)
1563
for (i=0;i<word_size/chunk_size;i=i+1) begin
1564
    parity[i] = parity_type;
1565
    for (j=0;j<chunk_size;j=j+1) begin
1566 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1567 43 unneback
    end
1568
end
1569
endmodule
1570
 
1571
`define MODULE parity_check
1572
module `BASE`MODULE( data, parity, parity_error);
1573
`undef MODULE
1574
parameter word_size = 32;
1575
parameter chunk_size = 8;
1576
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1577
input [word_size-1:0] data;
1578
input [word_size/chunk_size-1:0] parity;
1579
output parity_error;
1580 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1581 43 unneback
integer i,j;
1582
always @ (data or parity)
1583
for (i=0;i<word_size/chunk_size;i=i+1) begin
1584
    error_flag[i] = parity[i] ^ parity_type;
1585
    for (j=0;j<chunk_size;j=j+1) begin
1586 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1587 43 unneback
    end
1588
end
1589
assign parity_error = |error_flag;
1590
endmodule
1591
 
1592 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1593
////                                                              ////
1594
////  IO functions                                                ////
1595
////                                                              ////
1596
////  Description                                                 ////
1597
////  IO functions such as IOB flip-flops                         ////
1598
////                                                              ////
1599
////                                                              ////
1600
////  To Do:                                                      ////
1601
////   -                                                          ////
1602
////                                                              ////
1603
////  Author(s):                                                  ////
1604
////      - Michael Unneback, unneback@opencores.org              ////
1605
////        ORSoC AB                                              ////
1606
////                                                              ////
1607 18 unneback
//////////////////////////////////////////////////////////////////////
1608
////                                                              ////
1609 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1610
////                                                              ////
1611
//// This source file may be used and distributed without         ////
1612
//// restriction provided that this copyright statement is not    ////
1613
//// removed from the file and that any derivative work contains  ////
1614
//// the original copyright notice and the associated disclaimer. ////
1615
////                                                              ////
1616
//// This source file is free software; you can redistribute it   ////
1617
//// and/or modify it under the terms of the GNU Lesser General   ////
1618
//// Public License as published by the Free Software Foundation; ////
1619
//// either version 2.1 of the License, or (at your option) any   ////
1620
//// later version.                                               ////
1621
////                                                              ////
1622
//// This source is distributed in the hope that it will be       ////
1623
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1624
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1625
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1626
//// details.                                                     ////
1627
////                                                              ////
1628
//// You should have received a copy of the GNU Lesser General    ////
1629
//// Public License along with this source; if not, download it   ////
1630
//// from http://www.opencores.org/lgpl.shtml                     ////
1631
////                                                              ////
1632
//////////////////////////////////////////////////////////////////////
1633 136 unneback
`ifdef O_DFF
1634 45 unneback
`timescale 1ns/1ns
1635 44 unneback
`define MODULE o_dff
1636
module `BASE`MODULE (d_i, o_pad, clk, rst);
1637
`undef MODULE
1638
parameter width = 1;
1639 45 unneback
parameter reset_value = {width{1'b0}};
1640
input  [width-1:0]  d_i;
1641 44 unneback
output [width-1:0] o_pad;
1642
input clk, rst;
1643
wire [width-1:0] d_i_int `SYN_KEEP;
1644 45 unneback
reg  [width-1:0] o_pad_int;
1645 44 unneback
assign d_i_int = d_i;
1646
genvar i;
1647 45 unneback
generate
1648 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
1649 44 unneback
    always @ (posedge clk or posedge rst)
1650
    if (rst)
1651 45 unneback
        o_pad_int[i] <= reset_value[i];
1652 44 unneback
    else
1653 45 unneback
        o_pad_int[i] <= d_i_int[i];
1654
    assign #1 o_pad[i] = o_pad_int[i];
1655 44 unneback
end
1656
endgenerate
1657
endmodule
1658
`endif
1659
 
1660 136 unneback
`ifdef IO_DFF_OE
1661 45 unneback
`timescale 1ns/1ns
1662 44 unneback
`define MODULE io_dff_oe
1663
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1664
`undef MODULE
1665
parameter width = 1;
1666
input  [width-1:0] d_o;
1667
output reg [width-1:0] d_i;
1668
input oe;
1669
inout [width-1:0] io_pad;
1670
input clk, rst;
1671
wire [width-1:0] oe_d `SYN_KEEP;
1672
reg [width-1:0] oe_q;
1673
reg [width-1:0] d_o_q;
1674
assign oe_d = {width{oe}};
1675
genvar i;
1676
generate
1677 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
1678 44 unneback
    always @ (posedge clk or posedge rst)
1679
    if (rst)
1680
        oe_q[i] <= 1'b0;
1681
    else
1682
        oe_q[i] <= oe_d[i];
1683
    always @ (posedge clk or posedge rst)
1684
    if (rst)
1685
        d_o_q[i] <= 1'b0;
1686
    else
1687
        d_o_q[i] <= d_o[i];
1688
    always @ (posedge clk or posedge rst)
1689
    if (rst)
1690
        d_i[i] <= 1'b0;
1691
    else
1692
        d_i[i] <= io_pad[i];
1693 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1694 44 unneback
end
1695
endgenerate
1696
endmodule
1697
`endif
1698 136 unneback
 
1699
`ifdef O_DDR
1700
`ifdef ALTERA
1701
`define MODULE o_ddr
1702
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
1703
`undef MODULE
1704
parameter width = 1;
1705
input  [width-1:0] d_h_i, d_l_i;
1706
output [width-1:0] o_pad;
1707
input clk, rst;
1708
genvar i;
1709
generate
1710
for (i=0;i<width;i=i+1) begin : ddr
1711
    ddio_out ddio_out0( .aclr(rst), .datain_h(d_h_i[i]), .datain_l(d_l_i[i]), .outclock(clk), .dataout(o_pad[i]) );
1712
end
1713
endgenerate
1714
endmodule
1715
`else
1716
`define MODULE o_ddr
1717
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
1718
`undef MODULE
1719
parameter width = 1;
1720
input  [width-1:0] d_h_i, d_l_i;
1721
output [width-1:0] o_pad;
1722
input clk, rst;
1723
reg [width-1:0] ff1;
1724
reg [width-1:0] ff2;
1725
genvar i;
1726
generate
1727
for (i=0;i<width;i=i+1) begin : ddr
1728
    always @ (posedge clk or posedge rst)
1729
    if (rst)
1730
        ff1[i] <= 1'b0;
1731
    else
1732
        ff1[i] <= d_h_i[i];
1733
    always @ (posedge clk or posedge rst)
1734
    if (rst)
1735
        ff2[i] <= 1'b0;
1736
    else
1737
        ff2[i] <= d_l_i[i];
1738
    assign o_pad = (clk) ? ff1 : ff2;
1739
end
1740
endgenerate
1741
endmodule
1742
`endif
1743
`endif
1744
 
1745
`ifdef O_CLK
1746
`define MODULE o_clk
1747
module `BASE`MODULE ( clk_o_pad, clk, rst);
1748
`undef MODULE
1749
input clk, rst;
1750
output clk_o_pad;
1751
`define MODULE o_ddr
1752
`BASE`MODULE o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
1753
`undef MODULE
1754
endmodule
1755
`endif`ifdef CNT_BIN
1756 44 unneback
//////////////////////////////////////////////////////////////////////
1757
////                                                              ////
1758 6 unneback
////  Versatile counter                                           ////
1759
////                                                              ////
1760
////  Description                                                 ////
1761
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1762
////  counter                                                     ////
1763
////                                                              ////
1764
////  To Do:                                                      ////
1765
////   - add LFSR with more taps                                  ////
1766
////                                                              ////
1767
////  Author(s):                                                  ////
1768
////      - Michael Unneback, unneback@opencores.org              ////
1769
////        ORSoC AB                                              ////
1770
////                                                              ////
1771
//////////////////////////////////////////////////////////////////////
1772
////                                                              ////
1773
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1774
////                                                              ////
1775
//// This source file may be used and distributed without         ////
1776
//// restriction provided that this copyright statement is not    ////
1777
//// removed from the file and that any derivative work contains  ////
1778
//// the original copyright notice and the associated disclaimer. ////
1779
////                                                              ////
1780
//// This source file is free software; you can redistribute it   ////
1781
//// and/or modify it under the terms of the GNU Lesser General   ////
1782
//// Public License as published by the Free Software Foundation; ////
1783
//// either version 2.1 of the License, or (at your option) any   ////
1784
//// later version.                                               ////
1785
////                                                              ////
1786
//// This source is distributed in the hope that it will be       ////
1787
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1788
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1789
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1790
//// details.                                                     ////
1791
////                                                              ////
1792
//// You should have received a copy of the GNU Lesser General    ////
1793
//// Public License along with this source; if not, download it   ////
1794
//// from http://www.opencores.org/lgpl.shtml                     ////
1795
////                                                              ////
1796
//////////////////////////////////////////////////////////////////////
1797
 
1798
// binary counter
1799 22 unneback
 
1800 40 unneback
`define MODULE cnt_bin
1801
module `BASE`MODULE (
1802
`undef MODULE
1803
 q, rst, clk);
1804
 
1805 22 unneback
   parameter length = 4;
1806
   output [length:1] q;
1807
   input rst;
1808
   input clk;
1809
 
1810
   parameter clear_value = 0;
1811
   parameter set_value = 1;
1812
   parameter wrap_value = 0;
1813
   parameter level1_value = 15;
1814
 
1815
   reg  [length:1] qi;
1816
   wire [length:1] q_next;
1817
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1818
 
1819
   always @ (posedge clk or posedge rst)
1820
     if (rst)
1821
       qi <= {length{1'b0}};
1822
     else
1823
       qi <= q_next;
1824
 
1825
   assign q = qi;
1826
 
1827
endmodule
1828 40 unneback
`endif
1829
`ifdef CNT_BIN_CLEAR
1830 22 unneback
//////////////////////////////////////////////////////////////////////
1831
////                                                              ////
1832
////  Versatile counter                                           ////
1833
////                                                              ////
1834
////  Description                                                 ////
1835
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1836
////  counter                                                     ////
1837
////                                                              ////
1838
////  To Do:                                                      ////
1839
////   - add LFSR with more taps                                  ////
1840
////                                                              ////
1841
////  Author(s):                                                  ////
1842
////      - Michael Unneback, unneback@opencores.org              ////
1843
////        ORSoC AB                                              ////
1844
////                                                              ////
1845
//////////////////////////////////////////////////////////////////////
1846
////                                                              ////
1847
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1848
////                                                              ////
1849
//// This source file may be used and distributed without         ////
1850
//// restriction provided that this copyright statement is not    ////
1851
//// removed from the file and that any derivative work contains  ////
1852
//// the original copyright notice and the associated disclaimer. ////
1853
////                                                              ////
1854
//// This source file is free software; you can redistribute it   ////
1855
//// and/or modify it under the terms of the GNU Lesser General   ////
1856
//// Public License as published by the Free Software Foundation; ////
1857
//// either version 2.1 of the License, or (at your option) any   ////
1858
//// later version.                                               ////
1859
////                                                              ////
1860
//// This source is distributed in the hope that it will be       ////
1861
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1862
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1863
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1864
//// details.                                                     ////
1865
////                                                              ////
1866
//// You should have received a copy of the GNU Lesser General    ////
1867
//// Public License along with this source; if not, download it   ////
1868
//// from http://www.opencores.org/lgpl.shtml                     ////
1869
////                                                              ////
1870
//////////////////////////////////////////////////////////////////////
1871
 
1872
// binary counter
1873
 
1874 40 unneback
`define MODULE cnt_bin_clear
1875
module `BASE`MODULE (
1876
`undef MODULE
1877
 clear, q, rst, clk);
1878
 
1879 22 unneback
   parameter length = 4;
1880
   input clear;
1881
   output [length:1] q;
1882
   input rst;
1883
   input clk;
1884
 
1885
   parameter clear_value = 0;
1886
   parameter set_value = 1;
1887
   parameter wrap_value = 0;
1888
   parameter level1_value = 15;
1889
 
1890
   reg  [length:1] qi;
1891
   wire [length:1] q_next;
1892
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1893
 
1894
   always @ (posedge clk or posedge rst)
1895
     if (rst)
1896
       qi <= {length{1'b0}};
1897
     else
1898
       qi <= q_next;
1899
 
1900
   assign q = qi;
1901
 
1902
endmodule
1903 40 unneback
`endif
1904
`ifdef CNT_BIN_CE
1905 22 unneback
//////////////////////////////////////////////////////////////////////
1906
////                                                              ////
1907
////  Versatile counter                                           ////
1908
////                                                              ////
1909
////  Description                                                 ////
1910
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1911
////  counter                                                     ////
1912
////                                                              ////
1913
////  To Do:                                                      ////
1914
////   - add LFSR with more taps                                  ////
1915
////                                                              ////
1916
////  Author(s):                                                  ////
1917
////      - Michael Unneback, unneback@opencores.org              ////
1918
////        ORSoC AB                                              ////
1919
////                                                              ////
1920
//////////////////////////////////////////////////////////////////////
1921
////                                                              ////
1922
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1923
////                                                              ////
1924
//// This source file may be used and distributed without         ////
1925
//// restriction provided that this copyright statement is not    ////
1926
//// removed from the file and that any derivative work contains  ////
1927
//// the original copyright notice and the associated disclaimer. ////
1928
////                                                              ////
1929
//// This source file is free software; you can redistribute it   ////
1930
//// and/or modify it under the terms of the GNU Lesser General   ////
1931
//// Public License as published by the Free Software Foundation; ////
1932
//// either version 2.1 of the License, or (at your option) any   ////
1933
//// later version.                                               ////
1934
////                                                              ////
1935
//// This source is distributed in the hope that it will be       ////
1936
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1937
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1938
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1939
//// details.                                                     ////
1940
////                                                              ////
1941
//// You should have received a copy of the GNU Lesser General    ////
1942
//// Public License along with this source; if not, download it   ////
1943
//// from http://www.opencores.org/lgpl.shtml                     ////
1944
////                                                              ////
1945
//////////////////////////////////////////////////////////////////////
1946
 
1947
// binary counter
1948 6 unneback
 
1949 40 unneback
`define MODULE cnt_bin_ce
1950
module `BASE`MODULE (
1951
`undef MODULE
1952
 cke, q, rst, clk);
1953
 
1954 6 unneback
   parameter length = 4;
1955
   input cke;
1956
   output [length:1] q;
1957
   input rst;
1958
   input clk;
1959
 
1960
   parameter clear_value = 0;
1961
   parameter set_value = 1;
1962
   parameter wrap_value = 0;
1963
   parameter level1_value = 15;
1964
 
1965
   reg  [length:1] qi;
1966
   wire [length:1] q_next;
1967
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1968
 
1969
   always @ (posedge clk or posedge rst)
1970
     if (rst)
1971
       qi <= {length{1'b0}};
1972
     else
1973
     if (cke)
1974
       qi <= q_next;
1975
 
1976
   assign q = qi;
1977
 
1978
endmodule
1979 40 unneback
`endif
1980
`ifdef CNT_BIN_CE_CLEAR
1981 6 unneback
//////////////////////////////////////////////////////////////////////
1982
////                                                              ////
1983
////  Versatile counter                                           ////
1984
////                                                              ////
1985
////  Description                                                 ////
1986
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1987
////  counter                                                     ////
1988
////                                                              ////
1989
////  To Do:                                                      ////
1990
////   - add LFSR with more taps                                  ////
1991
////                                                              ////
1992
////  Author(s):                                                  ////
1993
////      - Michael Unneback, unneback@opencores.org              ////
1994
////        ORSoC AB                                              ////
1995
////                                                              ////
1996
//////////////////////////////////////////////////////////////////////
1997
////                                                              ////
1998
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1999
////                                                              ////
2000
//// This source file may be used and distributed without         ////
2001
//// restriction provided that this copyright statement is not    ////
2002
//// removed from the file and that any derivative work contains  ////
2003
//// the original copyright notice and the associated disclaimer. ////
2004
////                                                              ////
2005
//// This source file is free software; you can redistribute it   ////
2006
//// and/or modify it under the terms of the GNU Lesser General   ////
2007
//// Public License as published by the Free Software Foundation; ////
2008
//// either version 2.1 of the License, or (at your option) any   ////
2009
//// later version.                                               ////
2010
////                                                              ////
2011
//// This source is distributed in the hope that it will be       ////
2012
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2013
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2014
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2015
//// details.                                                     ////
2016
////                                                              ////
2017
//// You should have received a copy of the GNU Lesser General    ////
2018
//// Public License along with this source; if not, download it   ////
2019
//// from http://www.opencores.org/lgpl.shtml                     ////
2020
////                                                              ////
2021
//////////////////////////////////////////////////////////////////////
2022
 
2023
// binary counter
2024
 
2025 40 unneback
`define MODULE cnt_bin_ce_clear
2026
module `BASE`MODULE (
2027
`undef MODULE
2028
 clear, cke, q, rst, clk);
2029
 
2030 6 unneback
   parameter length = 4;
2031
   input clear;
2032
   input cke;
2033
   output [length:1] q;
2034
   input rst;
2035
   input clk;
2036
 
2037
   parameter clear_value = 0;
2038
   parameter set_value = 1;
2039
   parameter wrap_value = 0;
2040
   parameter level1_value = 15;
2041
 
2042
   reg  [length:1] qi;
2043
   wire [length:1] q_next;
2044
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2045
 
2046
   always @ (posedge clk or posedge rst)
2047
     if (rst)
2048
       qi <= {length{1'b0}};
2049
     else
2050
     if (cke)
2051
       qi <= q_next;
2052
 
2053
   assign q = qi;
2054
 
2055
endmodule
2056 40 unneback
`endif
2057
`ifdef CNT_BIN_CE_CLEAR_L1_L2
2058 6 unneback
//////////////////////////////////////////////////////////////////////
2059
////                                                              ////
2060
////  Versatile counter                                           ////
2061
////                                                              ////
2062
////  Description                                                 ////
2063
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2064
////  counter                                                     ////
2065
////                                                              ////
2066
////  To Do:                                                      ////
2067
////   - add LFSR with more taps                                  ////
2068
////                                                              ////
2069
////  Author(s):                                                  ////
2070
////      - Michael Unneback, unneback@opencores.org              ////
2071
////        ORSoC AB                                              ////
2072
////                                                              ////
2073
//////////////////////////////////////////////////////////////////////
2074
////                                                              ////
2075
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2076
////                                                              ////
2077
//// This source file may be used and distributed without         ////
2078
//// restriction provided that this copyright statement is not    ////
2079
//// removed from the file and that any derivative work contains  ////
2080
//// the original copyright notice and the associated disclaimer. ////
2081
////                                                              ////
2082
//// This source file is free software; you can redistribute it   ////
2083
//// and/or modify it under the terms of the GNU Lesser General   ////
2084
//// Public License as published by the Free Software Foundation; ////
2085
//// either version 2.1 of the License, or (at your option) any   ////
2086
//// later version.                                               ////
2087
////                                                              ////
2088
//// This source is distributed in the hope that it will be       ////
2089
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2090
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2091
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2092
//// details.                                                     ////
2093
////                                                              ////
2094
//// You should have received a copy of the GNU Lesser General    ////
2095
//// Public License along with this source; if not, download it   ////
2096
//// from http://www.opencores.org/lgpl.shtml                     ////
2097
////                                                              ////
2098
//////////////////////////////////////////////////////////////////////
2099
 
2100
// binary counter
2101 29 unneback
 
2102 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
2103
module `BASE`MODULE (
2104
`undef MODULE
2105
 clear, cke, q, level1, level2, rst, clk);
2106
 
2107 29 unneback
   parameter length = 4;
2108
   input clear;
2109
   input cke;
2110
   output [length:1] q;
2111
   output reg level1;
2112
   output reg level2;
2113
   input rst;
2114
   input clk;
2115
 
2116
   parameter clear_value = 0;
2117
   parameter set_value = 1;
2118 30 unneback
   parameter wrap_value = 15;
2119
   parameter level1_value = 8;
2120
   parameter level2_value = 15;
2121 29 unneback
 
2122
   wire rew;
2123 30 unneback
   assign rew = 1'b0;
2124 29 unneback
   reg  [length:1] qi;
2125
   wire [length:1] q_next;
2126
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2127
 
2128
   always @ (posedge clk or posedge rst)
2129
     if (rst)
2130
       qi <= {length{1'b0}};
2131
     else
2132
     if (cke)
2133
       qi <= q_next;
2134
 
2135
   assign q = qi;
2136
 
2137
 
2138
    always @ (posedge clk or posedge rst)
2139
    if (rst)
2140
        level1 <= 1'b0;
2141
    else
2142
    if (cke)
2143
    if (clear)
2144
        level1 <= 1'b0;
2145
    else if (q_next == level1_value)
2146
        level1 <= 1'b1;
2147
    else if (qi == level1_value & rew)
2148
        level1 <= 1'b0;
2149
 
2150
    always @ (posedge clk or posedge rst)
2151
    if (rst)
2152
        level2 <= 1'b0;
2153
    else
2154
    if (cke)
2155
    if (clear)
2156
        level2 <= 1'b0;
2157
    else if (q_next == level2_value)
2158
        level2 <= 1'b1;
2159
    else if (qi == level2_value & rew)
2160
        level2 <= 1'b0;
2161
endmodule
2162 40 unneback
`endif
2163
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2164 29 unneback
//////////////////////////////////////////////////////////////////////
2165
////                                                              ////
2166
////  Versatile counter                                           ////
2167
////                                                              ////
2168
////  Description                                                 ////
2169
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2170
////  counter                                                     ////
2171
////                                                              ////
2172
////  To Do:                                                      ////
2173
////   - add LFSR with more taps                                  ////
2174
////                                                              ////
2175
////  Author(s):                                                  ////
2176
////      - Michael Unneback, unneback@opencores.org              ////
2177
////        ORSoC AB                                              ////
2178
////                                                              ////
2179
//////////////////////////////////////////////////////////////////////
2180
////                                                              ////
2181
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2182
////                                                              ////
2183
//// This source file may be used and distributed without         ////
2184
//// restriction provided that this copyright statement is not    ////
2185
//// removed from the file and that any derivative work contains  ////
2186
//// the original copyright notice and the associated disclaimer. ////
2187
////                                                              ////
2188
//// This source file is free software; you can redistribute it   ////
2189
//// and/or modify it under the terms of the GNU Lesser General   ////
2190
//// Public License as published by the Free Software Foundation; ////
2191
//// either version 2.1 of the License, or (at your option) any   ////
2192
//// later version.                                               ////
2193
////                                                              ////
2194
//// This source is distributed in the hope that it will be       ////
2195
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2196
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2197
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2198
//// details.                                                     ////
2199
////                                                              ////
2200
//// You should have received a copy of the GNU Lesser General    ////
2201
//// Public License along with this source; if not, download it   ////
2202
//// from http://www.opencores.org/lgpl.shtml                     ////
2203
////                                                              ////
2204
//////////////////////////////////////////////////////////////////////
2205
 
2206
// binary counter
2207 6 unneback
 
2208 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2209
module `BASE`MODULE (
2210
`undef MODULE
2211
 clear, set, cke, rew, q, rst, clk);
2212
 
2213 6 unneback
   parameter length = 4;
2214
   input clear;
2215
   input set;
2216
   input cke;
2217
   input rew;
2218
   output [length:1] q;
2219
   input rst;
2220
   input clk;
2221
 
2222
   parameter clear_value = 0;
2223
   parameter set_value = 1;
2224
   parameter wrap_value = 0;
2225
   parameter level1_value = 15;
2226
 
2227
   reg  [length:1] qi;
2228
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2229
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2230
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2231
   assign q_next = rew ? q_next_rew : q_next_fw;
2232
 
2233
   always @ (posedge clk or posedge rst)
2234
     if (rst)
2235
       qi <= {length{1'b0}};
2236
     else
2237
     if (cke)
2238
       qi <= q_next;
2239
 
2240
   assign q = qi;
2241
 
2242
endmodule
2243 40 unneback
`endif
2244
`ifdef CNT_BIN_CE_REW_L1
2245 6 unneback
//////////////////////////////////////////////////////////////////////
2246
////                                                              ////
2247
////  Versatile counter                                           ////
2248
////                                                              ////
2249
////  Description                                                 ////
2250
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2251
////  counter                                                     ////
2252
////                                                              ////
2253
////  To Do:                                                      ////
2254
////   - add LFSR with more taps                                  ////
2255
////                                                              ////
2256
////  Author(s):                                                  ////
2257
////      - Michael Unneback, unneback@opencores.org              ////
2258
////        ORSoC AB                                              ////
2259
////                                                              ////
2260
//////////////////////////////////////////////////////////////////////
2261
////                                                              ////
2262
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2263
////                                                              ////
2264
//// This source file may be used and distributed without         ////
2265
//// restriction provided that this copyright statement is not    ////
2266
//// removed from the file and that any derivative work contains  ////
2267
//// the original copyright notice and the associated disclaimer. ////
2268
////                                                              ////
2269
//// This source file is free software; you can redistribute it   ////
2270
//// and/or modify it under the terms of the GNU Lesser General   ////
2271
//// Public License as published by the Free Software Foundation; ////
2272
//// either version 2.1 of the License, or (at your option) any   ////
2273
//// later version.                                               ////
2274
////                                                              ////
2275
//// This source is distributed in the hope that it will be       ////
2276
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2277
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2278
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2279
//// details.                                                     ////
2280
////                                                              ////
2281
//// You should have received a copy of the GNU Lesser General    ////
2282
//// Public License along with this source; if not, download it   ////
2283
//// from http://www.opencores.org/lgpl.shtml                     ////
2284
////                                                              ////
2285
//////////////////////////////////////////////////////////////////////
2286
 
2287
// binary counter
2288
 
2289 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2290
module `BASE`MODULE (
2291
`undef MODULE
2292
 cke, rew, level1, rst, clk);
2293
 
2294 6 unneback
   parameter length = 4;
2295
   input cke;
2296
   input rew;
2297
   output reg level1;
2298
   input rst;
2299
   input clk;
2300
 
2301
   parameter clear_value = 0;
2302
   parameter set_value = 1;
2303
   parameter wrap_value = 1;
2304
   parameter level1_value = 15;
2305
 
2306 29 unneback
   wire clear;
2307 30 unneback
   assign clear = 1'b0;
2308 6 unneback
   reg  [length:1] qi;
2309
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2310
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2311
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2312
   assign q_next = rew ? q_next_rew : q_next_fw;
2313
 
2314
   always @ (posedge clk or posedge rst)
2315
     if (rst)
2316
       qi <= {length{1'b0}};
2317
     else
2318
     if (cke)
2319
       qi <= q_next;
2320
 
2321
 
2322
 
2323
    always @ (posedge clk or posedge rst)
2324
    if (rst)
2325
        level1 <= 1'b0;
2326
    else
2327
    if (cke)
2328 29 unneback
    if (clear)
2329
        level1 <= 1'b0;
2330
    else if (q_next == level1_value)
2331 6 unneback
        level1 <= 1'b1;
2332
    else if (qi == level1_value & rew)
2333
        level1 <= 1'b0;
2334
endmodule
2335 40 unneback
`endif
2336
`ifdef CNT_BIN_CE_REW_ZQ_L1
2337 6 unneback
//////////////////////////////////////////////////////////////////////
2338
////                                                              ////
2339
////  Versatile counter                                           ////
2340
////                                                              ////
2341
////  Description                                                 ////
2342
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2343
////  counter                                                     ////
2344
////                                                              ////
2345
////  To Do:                                                      ////
2346
////   - add LFSR with more taps                                  ////
2347
////                                                              ////
2348
////  Author(s):                                                  ////
2349
////      - Michael Unneback, unneback@opencores.org              ////
2350
////        ORSoC AB                                              ////
2351
////                                                              ////
2352
//////////////////////////////////////////////////////////////////////
2353
////                                                              ////
2354
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2355
////                                                              ////
2356
//// This source file may be used and distributed without         ////
2357
//// restriction provided that this copyright statement is not    ////
2358
//// removed from the file and that any derivative work contains  ////
2359
//// the original copyright notice and the associated disclaimer. ////
2360
////                                                              ////
2361
//// This source file is free software; you can redistribute it   ////
2362
//// and/or modify it under the terms of the GNU Lesser General   ////
2363
//// Public License as published by the Free Software Foundation; ////
2364
//// either version 2.1 of the License, or (at your option) any   ////
2365
//// later version.                                               ////
2366
////                                                              ////
2367
//// This source is distributed in the hope that it will be       ////
2368
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2369
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2370
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2371
//// details.                                                     ////
2372
////                                                              ////
2373
//// You should have received a copy of the GNU Lesser General    ////
2374
//// Public License along with this source; if not, download it   ////
2375
//// from http://www.opencores.org/lgpl.shtml                     ////
2376
////                                                              ////
2377
//////////////////////////////////////////////////////////////////////
2378
 
2379 25 unneback
// binary counter
2380
 
2381 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2382
module `BASE`MODULE (
2383
`undef MODULE
2384
 cke, rew, zq, level1, rst, clk);
2385
 
2386 25 unneback
   parameter length = 4;
2387
   input cke;
2388
   input rew;
2389
   output reg zq;
2390
   output reg level1;
2391
   input rst;
2392
   input clk;
2393
 
2394
   parameter clear_value = 0;
2395
   parameter set_value = 1;
2396
   parameter wrap_value = 1;
2397
   parameter level1_value = 15;
2398
 
2399 29 unneback
   wire clear;
2400 30 unneback
   assign clear = 1'b0;
2401 25 unneback
   reg  [length:1] qi;
2402
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2403
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2404
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2405
   assign q_next = rew ? q_next_rew : q_next_fw;
2406
 
2407
   always @ (posedge clk or posedge rst)
2408
     if (rst)
2409
       qi <= {length{1'b0}};
2410
     else
2411
     if (cke)
2412
       qi <= q_next;
2413
 
2414
 
2415
 
2416
   always @ (posedge clk or posedge rst)
2417
     if (rst)
2418
       zq <= 1'b1;
2419
     else
2420
     if (cke)
2421
       zq <= q_next == {length{1'b0}};
2422
 
2423
    always @ (posedge clk or posedge rst)
2424
    if (rst)
2425
        level1 <= 1'b0;
2426
    else
2427
    if (cke)
2428 29 unneback
    if (clear)
2429
        level1 <= 1'b0;
2430
    else if (q_next == level1_value)
2431 25 unneback
        level1 <= 1'b1;
2432
    else if (qi == level1_value & rew)
2433
        level1 <= 1'b0;
2434
endmodule
2435 40 unneback
`endif
2436
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2437 25 unneback
//////////////////////////////////////////////////////////////////////
2438
////                                                              ////
2439
////  Versatile counter                                           ////
2440
////                                                              ////
2441
////  Description                                                 ////
2442
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2443
////  counter                                                     ////
2444
////                                                              ////
2445
////  To Do:                                                      ////
2446
////   - add LFSR with more taps                                  ////
2447
////                                                              ////
2448
////  Author(s):                                                  ////
2449
////      - Michael Unneback, unneback@opencores.org              ////
2450
////        ORSoC AB                                              ////
2451
////                                                              ////
2452
//////////////////////////////////////////////////////////////////////
2453
////                                                              ////
2454
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2455
////                                                              ////
2456
//// This source file may be used and distributed without         ////
2457
//// restriction provided that this copyright statement is not    ////
2458
//// removed from the file and that any derivative work contains  ////
2459
//// the original copyright notice and the associated disclaimer. ////
2460
////                                                              ////
2461
//// This source file is free software; you can redistribute it   ////
2462
//// and/or modify it under the terms of the GNU Lesser General   ////
2463
//// Public License as published by the Free Software Foundation; ////
2464
//// either version 2.1 of the License, or (at your option) any   ////
2465
//// later version.                                               ////
2466
////                                                              ////
2467
//// This source is distributed in the hope that it will be       ////
2468
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2469
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2470
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2471
//// details.                                                     ////
2472
////                                                              ////
2473
//// You should have received a copy of the GNU Lesser General    ////
2474
//// Public License along with this source; if not, download it   ////
2475
//// from http://www.opencores.org/lgpl.shtml                     ////
2476
////                                                              ////
2477
//////////////////////////////////////////////////////////////////////
2478
 
2479
// binary counter
2480
 
2481 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2482
module `BASE`MODULE (
2483
`undef MODULE
2484
 cke, rew, q, zq, level1, rst, clk);
2485
 
2486 25 unneback
   parameter length = 4;
2487
   input cke;
2488
   input rew;
2489
   output [length:1] q;
2490
   output reg zq;
2491
   output reg level1;
2492
   input rst;
2493
   input clk;
2494
 
2495
   parameter clear_value = 0;
2496
   parameter set_value = 1;
2497
   parameter wrap_value = 1;
2498
   parameter level1_value = 15;
2499
 
2500 29 unneback
   wire clear;
2501 30 unneback
   assign clear = 1'b0;
2502 25 unneback
   reg  [length:1] qi;
2503
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2504
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2505
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2506
   assign q_next = rew ? q_next_rew : q_next_fw;
2507
 
2508
   always @ (posedge clk or posedge rst)
2509
     if (rst)
2510
       qi <= {length{1'b0}};
2511
     else
2512
     if (cke)
2513
       qi <= q_next;
2514
 
2515
   assign q = qi;
2516
 
2517
 
2518
   always @ (posedge clk or posedge rst)
2519
     if (rst)
2520
       zq <= 1'b1;
2521
     else
2522
     if (cke)
2523
       zq <= q_next == {length{1'b0}};
2524
 
2525
    always @ (posedge clk or posedge rst)
2526
    if (rst)
2527
        level1 <= 1'b0;
2528
    else
2529
    if (cke)
2530 29 unneback
    if (clear)
2531
        level1 <= 1'b0;
2532
    else if (q_next == level1_value)
2533 25 unneback
        level1 <= 1'b1;
2534
    else if (qi == level1_value & rew)
2535
        level1 <= 1'b0;
2536
endmodule
2537 40 unneback
`endif
2538
`ifdef CNT_LFSR_ZQ
2539 25 unneback
//////////////////////////////////////////////////////////////////////
2540
////                                                              ////
2541
////  Versatile counter                                           ////
2542
////                                                              ////
2543
////  Description                                                 ////
2544
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2545
////  counter                                                     ////
2546
////                                                              ////
2547
////  To Do:                                                      ////
2548
////   - add LFSR with more taps                                  ////
2549
////                                                              ////
2550
////  Author(s):                                                  ////
2551
////      - Michael Unneback, unneback@opencores.org              ////
2552
////        ORSoC AB                                              ////
2553
////                                                              ////
2554
//////////////////////////////////////////////////////////////////////
2555
////                                                              ////
2556
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2557
////                                                              ////
2558
//// This source file may be used and distributed without         ////
2559
//// restriction provided that this copyright statement is not    ////
2560
//// removed from the file and that any derivative work contains  ////
2561
//// the original copyright notice and the associated disclaimer. ////
2562
////                                                              ////
2563
//// This source file is free software; you can redistribute it   ////
2564
//// and/or modify it under the terms of the GNU Lesser General   ////
2565
//// Public License as published by the Free Software Foundation; ////
2566
//// either version 2.1 of the License, or (at your option) any   ////
2567
//// later version.                                               ////
2568
////                                                              ////
2569
//// This source is distributed in the hope that it will be       ////
2570
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2571
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2572
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2573
//// details.                                                     ////
2574
////                                                              ////
2575
//// You should have received a copy of the GNU Lesser General    ////
2576
//// Public License along with this source; if not, download it   ////
2577
//// from http://www.opencores.org/lgpl.shtml                     ////
2578
////                                                              ////
2579
//////////////////////////////////////////////////////////////////////
2580
 
2581 6 unneback
// LFSR counter
2582
 
2583 40 unneback
`define MODULE cnt_lfsr_zq
2584
module `BASE`MODULE (
2585
`undef MODULE
2586
 zq, rst, clk);
2587
 
2588 6 unneback
   parameter length = 4;
2589
   output reg zq;
2590
   input rst;
2591
   input clk;
2592
 
2593
   parameter clear_value = 0;
2594
   parameter set_value = 1;
2595
   parameter wrap_value = 8;
2596
   parameter level1_value = 15;
2597
 
2598
   reg  [length:1] qi;
2599
   reg lfsr_fb;
2600
   wire [length:1] q_next;
2601
   reg [32:1] polynom;
2602
   integer i;
2603
 
2604
   always @ (qi)
2605
   begin
2606
        case (length)
2607
         2: polynom = 32'b11;                               // 0x3
2608
         3: polynom = 32'b110;                              // 0x6
2609
         4: polynom = 32'b1100;                             // 0xC
2610
         5: polynom = 32'b10100;                            // 0x14
2611
         6: polynom = 32'b110000;                           // 0x30
2612
         7: polynom = 32'b1100000;                          // 0x60
2613
         8: polynom = 32'b10111000;                         // 0xb8
2614
         9: polynom = 32'b100010000;                        // 0x110
2615
        10: polynom = 32'b1001000000;                       // 0x240
2616
        11: polynom = 32'b10100000000;                      // 0x500
2617
        12: polynom = 32'b100000101001;                     // 0x829
2618
        13: polynom = 32'b1000000001100;                    // 0x100C
2619
        14: polynom = 32'b10000000010101;                   // 0x2015
2620
        15: polynom = 32'b110000000000000;                  // 0x6000
2621
        16: polynom = 32'b1101000000001000;                 // 0xD008
2622
        17: polynom = 32'b10010000000000000;                // 0x12000
2623
        18: polynom = 32'b100000010000000000;               // 0x20400
2624
        19: polynom = 32'b1000000000000100011;              // 0x40023
2625 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2626 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2627
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2628
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2629
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2630
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2631
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2632
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2633
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2634
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2635
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2636
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2637
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2638
        default: polynom = 32'b0;
2639
        endcase
2640
        lfsr_fb = qi[length];
2641
        for (i=length-1; i>=1; i=i-1) begin
2642
            if (polynom[i])
2643
                lfsr_fb = lfsr_fb  ~^ qi[i];
2644
        end
2645
    end
2646
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2647
 
2648
   always @ (posedge clk or posedge rst)
2649
     if (rst)
2650
       qi <= {length{1'b0}};
2651
     else
2652
       qi <= q_next;
2653
 
2654
 
2655
 
2656
   always @ (posedge clk or posedge rst)
2657
     if (rst)
2658
       zq <= 1'b1;
2659
     else
2660
       zq <= q_next == {length{1'b0}};
2661
endmodule
2662 40 unneback
`endif
2663 75 unneback
`ifdef CNT_LFSR_CE
2664
//////////////////////////////////////////////////////////////////////
2665
////                                                              ////
2666
////  Versatile counter                                           ////
2667
////                                                              ////
2668
////  Description                                                 ////
2669
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2670
////  counter                                                     ////
2671
////                                                              ////
2672
////  To Do:                                                      ////
2673
////   - add LFSR with more taps                                  ////
2674
////                                                              ////
2675
////  Author(s):                                                  ////
2676
////      - Michael Unneback, unneback@opencores.org              ////
2677
////        ORSoC AB                                              ////
2678
////                                                              ////
2679
//////////////////////////////////////////////////////////////////////
2680
////                                                              ////
2681
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2682
////                                                              ////
2683
//// This source file may be used and distributed without         ////
2684
//// restriction provided that this copyright statement is not    ////
2685
//// removed from the file and that any derivative work contains  ////
2686
//// the original copyright notice and the associated disclaimer. ////
2687
////                                                              ////
2688
//// This source file is free software; you can redistribute it   ////
2689
//// and/or modify it under the terms of the GNU Lesser General   ////
2690
//// Public License as published by the Free Software Foundation; ////
2691
//// either version 2.1 of the License, or (at your option) any   ////
2692
//// later version.                                               ////
2693
////                                                              ////
2694
//// This source is distributed in the hope that it will be       ////
2695
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2696
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2697
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2698
//// details.                                                     ////
2699
////                                                              ////
2700
//// You should have received a copy of the GNU Lesser General    ////
2701
//// Public License along with this source; if not, download it   ////
2702
//// from http://www.opencores.org/lgpl.shtml                     ////
2703
////                                                              ////
2704
//////////////////////////////////////////////////////////////////////
2705
 
2706
// LFSR counter
2707
 
2708
`define MODULE cnt_lfsr_ce
2709
module `BASE`MODULE (
2710
`undef MODULE
2711
 cke, zq, rst, clk);
2712
 
2713
   parameter length = 4;
2714
   input cke;
2715
   output reg zq;
2716
   input rst;
2717
   input clk;
2718
 
2719
   parameter clear_value = 0;
2720
   parameter set_value = 1;
2721
   parameter wrap_value = 0;
2722
   parameter level1_value = 15;
2723
 
2724
   reg  [length:1] qi;
2725
   reg lfsr_fb;
2726
   wire [length:1] q_next;
2727
   reg [32:1] polynom;
2728
   integer i;
2729
 
2730
   always @ (qi)
2731
   begin
2732
        case (length)
2733
         2: polynom = 32'b11;                               // 0x3
2734
         3: polynom = 32'b110;                              // 0x6
2735
         4: polynom = 32'b1100;                             // 0xC
2736
         5: polynom = 32'b10100;                            // 0x14
2737
         6: polynom = 32'b110000;                           // 0x30
2738
         7: polynom = 32'b1100000;                          // 0x60
2739
         8: polynom = 32'b10111000;                         // 0xb8
2740
         9: polynom = 32'b100010000;                        // 0x110
2741
        10: polynom = 32'b1001000000;                       // 0x240
2742
        11: polynom = 32'b10100000000;                      // 0x500
2743
        12: polynom = 32'b100000101001;                     // 0x829
2744
        13: polynom = 32'b1000000001100;                    // 0x100C
2745
        14: polynom = 32'b10000000010101;                   // 0x2015
2746
        15: polynom = 32'b110000000000000;                  // 0x6000
2747
        16: polynom = 32'b1101000000001000;                 // 0xD008
2748
        17: polynom = 32'b10010000000000000;                // 0x12000
2749
        18: polynom = 32'b100000010000000000;               // 0x20400
2750
        19: polynom = 32'b1000000000000100011;              // 0x40023
2751
        20: polynom = 32'b10010000000000000000;             // 0x90000
2752
        21: polynom = 32'b101000000000000000000;            // 0x140000
2753
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2754
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2755
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2756
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2757
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2758
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2759
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2760
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2761
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2762
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2763
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2764
        default: polynom = 32'b0;
2765
        endcase
2766
        lfsr_fb = qi[length];
2767
        for (i=length-1; i>=1; i=i-1) begin
2768
            if (polynom[i])
2769
                lfsr_fb = lfsr_fb  ~^ qi[i];
2770
        end
2771
    end
2772
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2773
 
2774
   always @ (posedge clk or posedge rst)
2775
     if (rst)
2776
       qi <= {length{1'b0}};
2777
     else
2778
     if (cke)
2779
       qi <= q_next;
2780
 
2781
 
2782
 
2783
   always @ (posedge clk or posedge rst)
2784
     if (rst)
2785
       zq <= 1'b1;
2786
     else
2787
     if (cke)
2788
       zq <= q_next == {length{1'b0}};
2789
endmodule
2790
`endif
2791 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2792 6 unneback
//////////////////////////////////////////////////////////////////////
2793
////                                                              ////
2794
////  Versatile counter                                           ////
2795
////                                                              ////
2796
////  Description                                                 ////
2797
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2798
////  counter                                                     ////
2799
////                                                              ////
2800
////  To Do:                                                      ////
2801
////   - add LFSR with more taps                                  ////
2802
////                                                              ////
2803
////  Author(s):                                                  ////
2804
////      - Michael Unneback, unneback@opencores.org              ////
2805
////        ORSoC AB                                              ////
2806
////                                                              ////
2807
//////////////////////////////////////////////////////////////////////
2808
////                                                              ////
2809
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2810
////                                                              ////
2811
//// This source file may be used and distributed without         ////
2812
//// restriction provided that this copyright statement is not    ////
2813
//// removed from the file and that any derivative work contains  ////
2814
//// the original copyright notice and the associated disclaimer. ////
2815
////                                                              ////
2816
//// This source file is free software; you can redistribute it   ////
2817
//// and/or modify it under the terms of the GNU Lesser General   ////
2818
//// Public License as published by the Free Software Foundation; ////
2819
//// either version 2.1 of the License, or (at your option) any   ////
2820
//// later version.                                               ////
2821
////                                                              ////
2822
//// This source is distributed in the hope that it will be       ////
2823
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2824
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2825
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2826
//// details.                                                     ////
2827
////                                                              ////
2828
//// You should have received a copy of the GNU Lesser General    ////
2829
//// Public License along with this source; if not, download it   ////
2830
//// from http://www.opencores.org/lgpl.shtml                     ////
2831
////                                                              ////
2832
//////////////////////////////////////////////////////////////////////
2833
 
2834
// LFSR counter
2835
 
2836 40 unneback
`define MODULE cnt_lfsr_ce_zq
2837
module `BASE`MODULE (
2838
`undef MODULE
2839
 cke, zq, rst, clk);
2840
 
2841 6 unneback
   parameter length = 4;
2842
   input cke;
2843
   output reg zq;
2844
   input rst;
2845
   input clk;
2846
 
2847
   parameter clear_value = 0;
2848
   parameter set_value = 1;
2849
   parameter wrap_value = 8;
2850
   parameter level1_value = 15;
2851
 
2852
   reg  [length:1] qi;
2853
   reg lfsr_fb;
2854
   wire [length:1] q_next;
2855
   reg [32:1] polynom;
2856
   integer i;
2857
 
2858
   always @ (qi)
2859
   begin
2860
        case (length)
2861
         2: polynom = 32'b11;                               // 0x3
2862
         3: polynom = 32'b110;                              // 0x6
2863
         4: polynom = 32'b1100;                             // 0xC
2864
         5: polynom = 32'b10100;                            // 0x14
2865
         6: polynom = 32'b110000;                           // 0x30
2866
         7: polynom = 32'b1100000;                          // 0x60
2867
         8: polynom = 32'b10111000;                         // 0xb8
2868
         9: polynom = 32'b100010000;                        // 0x110
2869
        10: polynom = 32'b1001000000;                       // 0x240
2870
        11: polynom = 32'b10100000000;                      // 0x500
2871
        12: polynom = 32'b100000101001;                     // 0x829
2872
        13: polynom = 32'b1000000001100;                    // 0x100C
2873
        14: polynom = 32'b10000000010101;                   // 0x2015
2874
        15: polynom = 32'b110000000000000;                  // 0x6000
2875
        16: polynom = 32'b1101000000001000;                 // 0xD008
2876
        17: polynom = 32'b10010000000000000;                // 0x12000
2877
        18: polynom = 32'b100000010000000000;               // 0x20400
2878
        19: polynom = 32'b1000000000000100011;              // 0x40023
2879 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2880 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2881
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2882
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2883
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2884
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2885
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2886
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2887
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2888
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2889
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2890
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2891
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2892
        default: polynom = 32'b0;
2893
        endcase
2894
        lfsr_fb = qi[length];
2895
        for (i=length-1; i>=1; i=i-1) begin
2896
            if (polynom[i])
2897
                lfsr_fb = lfsr_fb  ~^ qi[i];
2898
        end
2899
    end
2900
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2901
 
2902
   always @ (posedge clk or posedge rst)
2903
     if (rst)
2904
       qi <= {length{1'b0}};
2905
     else
2906
     if (cke)
2907
       qi <= q_next;
2908
 
2909
 
2910
 
2911
   always @ (posedge clk or posedge rst)
2912
     if (rst)
2913
       zq <= 1'b1;
2914
     else
2915
     if (cke)
2916
       zq <= q_next == {length{1'b0}};
2917
endmodule
2918 40 unneback
`endif
2919
`ifdef CNT_LFSR_CE_Q
2920 6 unneback
//////////////////////////////////////////////////////////////////////
2921
////                                                              ////
2922
////  Versatile counter                                           ////
2923
////                                                              ////
2924
////  Description                                                 ////
2925
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2926
////  counter                                                     ////
2927
////                                                              ////
2928
////  To Do:                                                      ////
2929
////   - add LFSR with more taps                                  ////
2930
////                                                              ////
2931
////  Author(s):                                                  ////
2932
////      - Michael Unneback, unneback@opencores.org              ////
2933
////        ORSoC AB                                              ////
2934
////                                                              ////
2935
//////////////////////////////////////////////////////////////////////
2936
////                                                              ////
2937
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2938
////                                                              ////
2939
//// This source file may be used and distributed without         ////
2940
//// restriction provided that this copyright statement is not    ////
2941
//// removed from the file and that any derivative work contains  ////
2942
//// the original copyright notice and the associated disclaimer. ////
2943
////                                                              ////
2944
//// This source file is free software; you can redistribute it   ////
2945
//// and/or modify it under the terms of the GNU Lesser General   ////
2946
//// Public License as published by the Free Software Foundation; ////
2947
//// either version 2.1 of the License, or (at your option) any   ////
2948
//// later version.                                               ////
2949
////                                                              ////
2950
//// This source is distributed in the hope that it will be       ////
2951
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2952
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2953
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2954
//// details.                                                     ////
2955
////                                                              ////
2956
//// You should have received a copy of the GNU Lesser General    ////
2957
//// Public License along with this source; if not, download it   ////
2958
//// from http://www.opencores.org/lgpl.shtml                     ////
2959
////                                                              ////
2960
//////////////////////////////////////////////////////////////////////
2961 22 unneback
 
2962
// LFSR counter
2963 27 unneback
 
2964 40 unneback
`define MODULE cnt_lfsr_ce_q
2965
module `BASE`MODULE (
2966
`undef MODULE
2967
 cke, q, rst, clk);
2968
 
2969 27 unneback
   parameter length = 4;
2970
   input cke;
2971
   output [length:1] q;
2972
   input rst;
2973
   input clk;
2974
 
2975
   parameter clear_value = 0;
2976
   parameter set_value = 1;
2977
   parameter wrap_value = 8;
2978
   parameter level1_value = 15;
2979
 
2980
   reg  [length:1] qi;
2981
   reg lfsr_fb;
2982
   wire [length:1] q_next;
2983
   reg [32:1] polynom;
2984
   integer i;
2985
 
2986
   always @ (qi)
2987
   begin
2988
        case (length)
2989
         2: polynom = 32'b11;                               // 0x3
2990
         3: polynom = 32'b110;                              // 0x6
2991
         4: polynom = 32'b1100;                             // 0xC
2992
         5: polynom = 32'b10100;                            // 0x14
2993
         6: polynom = 32'b110000;                           // 0x30
2994
         7: polynom = 32'b1100000;                          // 0x60
2995
         8: polynom = 32'b10111000;                         // 0xb8
2996
         9: polynom = 32'b100010000;                        // 0x110
2997
        10: polynom = 32'b1001000000;                       // 0x240
2998
        11: polynom = 32'b10100000000;                      // 0x500
2999
        12: polynom = 32'b100000101001;                     // 0x829
3000
        13: polynom = 32'b1000000001100;                    // 0x100C
3001
        14: polynom = 32'b10000000010101;                   // 0x2015
3002
        15: polynom = 32'b110000000000000;                  // 0x6000
3003
        16: polynom = 32'b1101000000001000;                 // 0xD008
3004
        17: polynom = 32'b10010000000000000;                // 0x12000
3005
        18: polynom = 32'b100000010000000000;               // 0x20400
3006
        19: polynom = 32'b1000000000000100011;              // 0x40023
3007 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3008 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3009
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3010
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3011
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3012
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3013
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3014
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3015
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3016
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3017
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3018
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3019
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3020
        default: polynom = 32'b0;
3021
        endcase
3022
        lfsr_fb = qi[length];
3023
        for (i=length-1; i>=1; i=i-1) begin
3024
            if (polynom[i])
3025
                lfsr_fb = lfsr_fb  ~^ qi[i];
3026
        end
3027
    end
3028
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3029
 
3030
   always @ (posedge clk or posedge rst)
3031
     if (rst)
3032
       qi <= {length{1'b0}};
3033
     else
3034
     if (cke)
3035
       qi <= q_next;
3036
 
3037
   assign q = qi;
3038
 
3039
endmodule
3040 40 unneback
`endif
3041
`ifdef CNT_LFSR_CE_CLEAR_Q
3042 27 unneback
//////////////////////////////////////////////////////////////////////
3043
////                                                              ////
3044
////  Versatile counter                                           ////
3045
////                                                              ////
3046
////  Description                                                 ////
3047
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3048
////  counter                                                     ////
3049
////                                                              ////
3050
////  To Do:                                                      ////
3051
////   - add LFSR with more taps                                  ////
3052
////                                                              ////
3053
////  Author(s):                                                  ////
3054
////      - Michael Unneback, unneback@opencores.org              ////
3055
////        ORSoC AB                                              ////
3056
////                                                              ////
3057
//////////////////////////////////////////////////////////////////////
3058
////                                                              ////
3059
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3060
////                                                              ////
3061
//// This source file may be used and distributed without         ////
3062
//// restriction provided that this copyright statement is not    ////
3063
//// removed from the file and that any derivative work contains  ////
3064
//// the original copyright notice and the associated disclaimer. ////
3065
////                                                              ////
3066
//// This source file is free software; you can redistribute it   ////
3067
//// and/or modify it under the terms of the GNU Lesser General   ////
3068
//// Public License as published by the Free Software Foundation; ////
3069
//// either version 2.1 of the License, or (at your option) any   ////
3070
//// later version.                                               ////
3071
////                                                              ////
3072
//// This source is distributed in the hope that it will be       ////
3073
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3074
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3075
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3076
//// details.                                                     ////
3077
////                                                              ////
3078
//// You should have received a copy of the GNU Lesser General    ////
3079
//// Public License along with this source; if not, download it   ////
3080
//// from http://www.opencores.org/lgpl.shtml                     ////
3081
////                                                              ////
3082
//////////////////////////////////////////////////////////////////////
3083
 
3084
// LFSR counter
3085
 
3086 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
3087
module `BASE`MODULE (
3088
`undef MODULE
3089
 clear, cke, q, rst, clk);
3090
 
3091 27 unneback
   parameter length = 4;
3092
   input clear;
3093
   input cke;
3094
   output [length:1] q;
3095
   input rst;
3096
   input clk;
3097
 
3098
   parameter clear_value = 0;
3099
   parameter set_value = 1;
3100
   parameter wrap_value = 8;
3101
   parameter level1_value = 15;
3102
 
3103
   reg  [length:1] qi;
3104
   reg lfsr_fb;
3105
   wire [length:1] q_next;
3106
   reg [32:1] polynom;
3107
   integer i;
3108
 
3109
   always @ (qi)
3110
   begin
3111
        case (length)
3112
         2: polynom = 32'b11;                               // 0x3
3113
         3: polynom = 32'b110;                              // 0x6
3114
         4: polynom = 32'b1100;                             // 0xC
3115
         5: polynom = 32'b10100;                            // 0x14
3116
         6: polynom = 32'b110000;                           // 0x30
3117
         7: polynom = 32'b1100000;                          // 0x60
3118
         8: polynom = 32'b10111000;                         // 0xb8
3119
         9: polynom = 32'b100010000;                        // 0x110
3120
        10: polynom = 32'b1001000000;                       // 0x240
3121
        11: polynom = 32'b10100000000;                      // 0x500
3122
        12: polynom = 32'b100000101001;                     // 0x829
3123
        13: polynom = 32'b1000000001100;                    // 0x100C
3124
        14: polynom = 32'b10000000010101;                   // 0x2015
3125
        15: polynom = 32'b110000000000000;                  // 0x6000
3126
        16: polynom = 32'b1101000000001000;                 // 0xD008
3127
        17: polynom = 32'b10010000000000000;                // 0x12000
3128
        18: polynom = 32'b100000010000000000;               // 0x20400
3129
        19: polynom = 32'b1000000000000100011;              // 0x40023
3130 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3131 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3132
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3133
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3134
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3135
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3136
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3137
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3138
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3139
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3140
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3141
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3142
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3143
        default: polynom = 32'b0;
3144
        endcase
3145
        lfsr_fb = qi[length];
3146
        for (i=length-1; i>=1; i=i-1) begin
3147
            if (polynom[i])
3148
                lfsr_fb = lfsr_fb  ~^ qi[i];
3149
        end
3150
    end
3151
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3152
 
3153
   always @ (posedge clk or posedge rst)
3154
     if (rst)
3155
       qi <= {length{1'b0}};
3156
     else
3157
     if (cke)
3158
       qi <= q_next;
3159
 
3160
   assign q = qi;
3161
 
3162
endmodule
3163 40 unneback
`endif
3164
`ifdef CNT_LFSR_CE_Q_ZQ
3165 27 unneback
//////////////////////////////////////////////////////////////////////
3166
////                                                              ////
3167
////  Versatile counter                                           ////
3168
////                                                              ////
3169
////  Description                                                 ////
3170
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3171
////  counter                                                     ////
3172
////                                                              ////
3173
////  To Do:                                                      ////
3174
////   - add LFSR with more taps                                  ////
3175
////                                                              ////
3176
////  Author(s):                                                  ////
3177
////      - Michael Unneback, unneback@opencores.org              ////
3178
////        ORSoC AB                                              ////
3179
////                                                              ////
3180
//////////////////////////////////////////////////////////////////////
3181
////                                                              ////
3182
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3183
////                                                              ////
3184
//// This source file may be used and distributed without         ////
3185
//// restriction provided that this copyright statement is not    ////
3186
//// removed from the file and that any derivative work contains  ////
3187
//// the original copyright notice and the associated disclaimer. ////
3188
////                                                              ////
3189
//// This source file is free software; you can redistribute it   ////
3190
//// and/or modify it under the terms of the GNU Lesser General   ////
3191
//// Public License as published by the Free Software Foundation; ////
3192
//// either version 2.1 of the License, or (at your option) any   ////
3193
//// later version.                                               ////
3194
////                                                              ////
3195
//// This source is distributed in the hope that it will be       ////
3196
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3197
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3198
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3199
//// details.                                                     ////
3200
////                                                              ////
3201
//// You should have received a copy of the GNU Lesser General    ////
3202
//// Public License along with this source; if not, download it   ////
3203
//// from http://www.opencores.org/lgpl.shtml                     ////
3204
////                                                              ////
3205
//////////////////////////////////////////////////////////////////////
3206
 
3207
// LFSR counter
3208 22 unneback
 
3209 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
3210
module `BASE`MODULE (
3211
`undef MODULE
3212
 cke, q, zq, rst, clk);
3213
 
3214 22 unneback
   parameter length = 4;
3215
   input cke;
3216
   output [length:1] q;
3217
   output reg zq;
3218
   input rst;
3219
   input clk;
3220
 
3221
   parameter clear_value = 0;
3222
   parameter set_value = 1;
3223
   parameter wrap_value = 8;
3224
   parameter level1_value = 15;
3225
 
3226
   reg  [length:1] qi;
3227
   reg lfsr_fb;
3228
   wire [length:1] q_next;
3229
   reg [32:1] polynom;
3230
   integer i;
3231
 
3232
   always @ (qi)
3233
   begin
3234
        case (length)
3235
         2: polynom = 32'b11;                               // 0x3
3236
         3: polynom = 32'b110;                              // 0x6
3237
         4: polynom = 32'b1100;                             // 0xC
3238
         5: polynom = 32'b10100;                            // 0x14
3239
         6: polynom = 32'b110000;                           // 0x30
3240
         7: polynom = 32'b1100000;                          // 0x60
3241
         8: polynom = 32'b10111000;                         // 0xb8
3242
         9: polynom = 32'b100010000;                        // 0x110
3243
        10: polynom = 32'b1001000000;                       // 0x240
3244
        11: polynom = 32'b10100000000;                      // 0x500
3245
        12: polynom = 32'b100000101001;                     // 0x829
3246
        13: polynom = 32'b1000000001100;                    // 0x100C
3247
        14: polynom = 32'b10000000010101;                   // 0x2015
3248
        15: polynom = 32'b110000000000000;                  // 0x6000
3249
        16: polynom = 32'b1101000000001000;                 // 0xD008
3250
        17: polynom = 32'b10010000000000000;                // 0x12000
3251
        18: polynom = 32'b100000010000000000;               // 0x20400
3252
        19: polynom = 32'b1000000000000100011;              // 0x40023
3253 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3254 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3255
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3256
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3257
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3258
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3259
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3260
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3261
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3262
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3263
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3264
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3265
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3266
        default: polynom = 32'b0;
3267
        endcase
3268
        lfsr_fb = qi[length];
3269
        for (i=length-1; i>=1; i=i-1) begin
3270
            if (polynom[i])
3271
                lfsr_fb = lfsr_fb  ~^ qi[i];
3272
        end
3273
    end
3274
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3275
 
3276
   always @ (posedge clk or posedge rst)
3277
     if (rst)
3278
       qi <= {length{1'b0}};
3279
     else
3280
     if (cke)
3281
       qi <= q_next;
3282
 
3283
   assign q = qi;
3284
 
3285
 
3286
   always @ (posedge clk or posedge rst)
3287
     if (rst)
3288
       zq <= 1'b1;
3289
     else
3290
     if (cke)
3291
       zq <= q_next == {length{1'b0}};
3292
endmodule
3293 40 unneback
`endif
3294
`ifdef CNT_LFSR_CE_REW_L1
3295 22 unneback
//////////////////////////////////////////////////////////////////////
3296
////                                                              ////
3297
////  Versatile counter                                           ////
3298
////                                                              ////
3299
////  Description                                                 ////
3300
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3301
////  counter                                                     ////
3302
////                                                              ////
3303
////  To Do:                                                      ////
3304
////   - add LFSR with more taps                                  ////
3305
////                                                              ////
3306
////  Author(s):                                                  ////
3307
////      - Michael Unneback, unneback@opencores.org              ////
3308
////        ORSoC AB                                              ////
3309
////                                                              ////
3310
//////////////////////////////////////////////////////////////////////
3311
////                                                              ////
3312
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3313
////                                                              ////
3314
//// This source file may be used and distributed without         ////
3315
//// restriction provided that this copyright statement is not    ////
3316
//// removed from the file and that any derivative work contains  ////
3317
//// the original copyright notice and the associated disclaimer. ////
3318
////                                                              ////
3319
//// This source file is free software; you can redistribute it   ////
3320
//// and/or modify it under the terms of the GNU Lesser General   ////
3321
//// Public License as published by the Free Software Foundation; ////
3322
//// either version 2.1 of the License, or (at your option) any   ////
3323
//// later version.                                               ////
3324
////                                                              ////
3325
//// This source is distributed in the hope that it will be       ////
3326
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3327
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3328
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3329
//// details.                                                     ////
3330
////                                                              ////
3331
//// You should have received a copy of the GNU Lesser General    ////
3332
//// Public License along with this source; if not, download it   ////
3333
//// from http://www.opencores.org/lgpl.shtml                     ////
3334
////                                                              ////
3335
//////////////////////////////////////////////////////////////////////
3336 6 unneback
 
3337
// LFSR counter
3338
 
3339 40 unneback
`define MODULE cnt_lfsr_ce_rew_l1
3340
module `BASE`MODULE (
3341
`undef MODULE
3342
 cke, rew, level1, rst, clk);
3343
 
3344 6 unneback
   parameter length = 4;
3345
   input cke;
3346
   input rew;
3347
   output reg level1;
3348
   input rst;
3349
   input clk;
3350
 
3351
   parameter clear_value = 0;
3352
   parameter set_value = 1;
3353
   parameter wrap_value = 8;
3354
   parameter level1_value = 15;
3355
 
3356 29 unneback
   wire clear;
3357 30 unneback
   assign clear = 1'b0;
3358 6 unneback
   reg  [length:1] qi;
3359
   reg lfsr_fb, lfsr_fb_rew;
3360
   wire  [length:1] q_next, q_next_fw, q_next_rew;
3361
   reg [32:1] polynom_rew;
3362
   integer j;
3363
   reg [32:1] polynom;
3364
   integer i;
3365
 
3366
   always @ (qi)
3367
   begin
3368
        case (length)
3369
         2: polynom = 32'b11;                               // 0x3
3370
         3: polynom = 32'b110;                              // 0x6
3371
         4: polynom = 32'b1100;                             // 0xC
3372
         5: polynom = 32'b10100;                            // 0x14
3373
         6: polynom = 32'b110000;                           // 0x30
3374
         7: polynom = 32'b1100000;                          // 0x60
3375
         8: polynom = 32'b10111000;                         // 0xb8
3376
         9: polynom = 32'b100010000;                        // 0x110
3377
        10: polynom = 32'b1001000000;                       // 0x240
3378
        11: polynom = 32'b10100000000;                      // 0x500
3379
        12: polynom = 32'b100000101001;                     // 0x829
3380
        13: polynom = 32'b1000000001100;                    // 0x100C
3381
        14: polynom = 32'b10000000010101;                   // 0x2015
3382
        15: polynom = 32'b110000000000000;                  // 0x6000
3383
        16: polynom = 32'b1101000000001000;                 // 0xD008
3384
        17: polynom = 32'b10010000000000000;                // 0x12000
3385
        18: polynom = 32'b100000010000000000;               // 0x20400
3386
        19: polynom = 32'b1000000000000100011;              // 0x40023
3387 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3388 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3389
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3390
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3391
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3392
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3393
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3394
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3395
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3396
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3397
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3398
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3399
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3400
        default: polynom = 32'b0;
3401
        endcase
3402
        lfsr_fb = qi[length];
3403
        for (i=length-1; i>=1; i=i-1) begin
3404
            if (polynom[i])
3405
                lfsr_fb = lfsr_fb  ~^ qi[i];
3406
        end
3407
    end
3408
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3409
   always @ (qi)
3410
   begin
3411
        case (length)
3412
         2: polynom_rew = 32'b11;
3413
         3: polynom_rew = 32'b110;
3414
         4: polynom_rew = 32'b1100;
3415
         5: polynom_rew = 32'b10100;
3416
         6: polynom_rew = 32'b110000;
3417
         7: polynom_rew = 32'b1100000;
3418
         8: polynom_rew = 32'b10111000;
3419
         9: polynom_rew = 32'b100010000;
3420
        10: polynom_rew = 32'b1001000000;
3421
        11: polynom_rew = 32'b10100000000;
3422
        12: polynom_rew = 32'b100000101001;
3423
        13: polynom_rew = 32'b1000000001100;
3424
        14: polynom_rew = 32'b10000000010101;
3425
        15: polynom_rew = 32'b110000000000000;
3426
        16: polynom_rew = 32'b1101000000001000;
3427
        17: polynom_rew = 32'b10010000000000000;
3428
        18: polynom_rew = 32'b100000010000000000;
3429
        19: polynom_rew = 32'b1000000000000100011;
3430
        20: polynom_rew = 32'b10000010000000000000;
3431
        21: polynom_rew = 32'b101000000000000000000;
3432
        22: polynom_rew = 32'b1100000000000000000000;
3433
        23: polynom_rew = 32'b10000100000000000000000;
3434
        24: polynom_rew = 32'b111000010000000000000000;
3435
        25: polynom_rew = 32'b1001000000000000000000000;
3436
        26: polynom_rew = 32'b10000000000000000000100011;
3437
        27: polynom_rew = 32'b100000000000000000000010011;
3438
        28: polynom_rew = 32'b1100100000000000000000000000;
3439
        29: polynom_rew = 32'b10100000000000000000000000000;
3440
        30: polynom_rew = 32'b100000000000000000000000101001;
3441
        31: polynom_rew = 32'b1001000000000000000000000000000;
3442
        32: polynom_rew = 32'b10000000001000000000000000000011;
3443
        default: polynom_rew = 32'b0;
3444
        endcase
3445
        // rotate left
3446
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3447
        lfsr_fb_rew = qi[length];
3448
        for (i=length-1; i>=1; i=i-1) begin
3449
            if (polynom_rew[i])
3450
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3451
        end
3452
    end
3453
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3454
   assign q_next = rew ? q_next_rew : q_next_fw;
3455
 
3456
   always @ (posedge clk or posedge rst)
3457
     if (rst)
3458
       qi <= {length{1'b0}};
3459
     else
3460
     if (cke)
3461
       qi <= q_next;
3462
 
3463
 
3464
 
3465
    always @ (posedge clk or posedge rst)
3466
    if (rst)
3467
        level1 <= 1'b0;
3468
    else
3469
    if (cke)
3470 29 unneback
    if (clear)
3471
        level1 <= 1'b0;
3472
    else if (q_next == level1_value)
3473 6 unneback
        level1 <= 1'b1;
3474
    else if (qi == level1_value & rew)
3475
        level1 <= 1'b0;
3476
endmodule
3477 40 unneback
`endif
3478
`ifdef CNT_GRAY
3479 6 unneback
//////////////////////////////////////////////////////////////////////
3480
////                                                              ////
3481
////  Versatile counter                                           ////
3482
////                                                              ////
3483
////  Description                                                 ////
3484
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3485
////  counter                                                     ////
3486
////                                                              ////
3487
////  To Do:                                                      ////
3488
////   - add LFSR with more taps                                  ////
3489
////                                                              ////
3490
////  Author(s):                                                  ////
3491
////      - Michael Unneback, unneback@opencores.org              ////
3492
////        ORSoC AB                                              ////
3493
////                                                              ////
3494
//////////////////////////////////////////////////////////////////////
3495
////                                                              ////
3496
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3497
////                                                              ////
3498
//// This source file may be used and distributed without         ////
3499
//// restriction provided that this copyright statement is not    ////
3500
//// removed from the file and that any derivative work contains  ////
3501
//// the original copyright notice and the associated disclaimer. ////
3502
////                                                              ////
3503
//// This source file is free software; you can redistribute it   ////
3504
//// and/or modify it under the terms of the GNU Lesser General   ////
3505
//// Public License as published by the Free Software Foundation; ////
3506
//// either version 2.1 of the License, or (at your option) any   ////
3507
//// later version.                                               ////
3508
////                                                              ////
3509
//// This source is distributed in the hope that it will be       ////
3510
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3511
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3512
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3513
//// details.                                                     ////
3514
////                                                              ////
3515
//// You should have received a copy of the GNU Lesser General    ////
3516
//// Public License along with this source; if not, download it   ////
3517
//// from http://www.opencores.org/lgpl.shtml                     ////
3518
////                                                              ////
3519
//////////////////////////////////////////////////////////////////////
3520
 
3521
// GRAY counter
3522
 
3523 40 unneback
`define MODULE cnt_gray
3524
module `BASE`MODULE (
3525
`undef MODULE
3526
 q, rst, clk);
3527
 
3528 6 unneback
   parameter length = 4;
3529
   output reg [length:1] q;
3530
   input rst;
3531
   input clk;
3532
 
3533
   parameter clear_value = 0;
3534
   parameter set_value = 1;
3535
   parameter wrap_value = 8;
3536
   parameter level1_value = 15;
3537
 
3538
   reg  [length:1] qi;
3539
   wire [length:1] q_next;
3540
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3541
 
3542
   always @ (posedge clk or posedge rst)
3543
     if (rst)
3544
       qi <= {length{1'b0}};
3545
     else
3546
       qi <= q_next;
3547
 
3548
   always @ (posedge clk or posedge rst)
3549
     if (rst)
3550
       q <= {length{1'b0}};
3551
     else
3552
         q <= (q_next>>1) ^ q_next;
3553
 
3554
endmodule
3555 40 unneback
`endif
3556
`ifdef CNT_GRAY_CE
3557 6 unneback
//////////////////////////////////////////////////////////////////////
3558
////                                                              ////
3559
////  Versatile counter                                           ////
3560
////                                                              ////
3561
////  Description                                                 ////
3562
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3563
////  counter                                                     ////
3564
////                                                              ////
3565
////  To Do:                                                      ////
3566
////   - add LFSR with more taps                                  ////
3567
////                                                              ////
3568
////  Author(s):                                                  ////
3569
////      - Michael Unneback, unneback@opencores.org              ////
3570
////        ORSoC AB                                              ////
3571
////                                                              ////
3572
//////////////////////////////////////////////////////////////////////
3573
////                                                              ////
3574
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3575
////                                                              ////
3576
//// This source file may be used and distributed without         ////
3577
//// restriction provided that this copyright statement is not    ////
3578
//// removed from the file and that any derivative work contains  ////
3579
//// the original copyright notice and the associated disclaimer. ////
3580
////                                                              ////
3581
//// This source file is free software; you can redistribute it   ////
3582
//// and/or modify it under the terms of the GNU Lesser General   ////
3583
//// Public License as published by the Free Software Foundation; ////
3584
//// either version 2.1 of the License, or (at your option) any   ////
3585
//// later version.                                               ////
3586
////                                                              ////
3587
//// This source is distributed in the hope that it will be       ////
3588
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3589
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3590
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3591
//// details.                                                     ////
3592
////                                                              ////
3593
//// You should have received a copy of the GNU Lesser General    ////
3594
//// Public License along with this source; if not, download it   ////
3595
//// from http://www.opencores.org/lgpl.shtml                     ////
3596
////                                                              ////
3597
//////////////////////////////////////////////////////////////////////
3598
 
3599
// GRAY counter
3600
 
3601 40 unneback
`define MODULE cnt_gray_ce
3602
module `BASE`MODULE (
3603
`undef MODULE
3604
 cke, q, rst, clk);
3605
 
3606 6 unneback
   parameter length = 4;
3607
   input cke;
3608
   output reg [length:1] q;
3609
   input rst;
3610
   input clk;
3611
 
3612
   parameter clear_value = 0;
3613
   parameter set_value = 1;
3614
   parameter wrap_value = 8;
3615
   parameter level1_value = 15;
3616
 
3617
   reg  [length:1] qi;
3618
   wire [length:1] q_next;
3619
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3620
 
3621
   always @ (posedge clk or posedge rst)
3622
     if (rst)
3623
       qi <= {length{1'b0}};
3624
     else
3625
     if (cke)
3626
       qi <= q_next;
3627
 
3628
   always @ (posedge clk or posedge rst)
3629
     if (rst)
3630
       q <= {length{1'b0}};
3631
     else
3632
       if (cke)
3633
         q <= (q_next>>1) ^ q_next;
3634
 
3635
endmodule
3636 40 unneback
`endif
3637
`ifdef CNT_GRAY_CE_BIN
3638 6 unneback
//////////////////////////////////////////////////////////////////////
3639
////                                                              ////
3640
////  Versatile counter                                           ////
3641
////                                                              ////
3642
////  Description                                                 ////
3643
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3644
////  counter                                                     ////
3645
////                                                              ////
3646
////  To Do:                                                      ////
3647
////   - add LFSR with more taps                                  ////
3648
////                                                              ////
3649
////  Author(s):                                                  ////
3650
////      - Michael Unneback, unneback@opencores.org              ////
3651
////        ORSoC AB                                              ////
3652
////                                                              ////
3653
//////////////////////////////////////////////////////////////////////
3654
////                                                              ////
3655
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3656
////                                                              ////
3657
//// This source file may be used and distributed without         ////
3658
//// restriction provided that this copyright statement is not    ////
3659
//// removed from the file and that any derivative work contains  ////
3660
//// the original copyright notice and the associated disclaimer. ////
3661
////                                                              ////
3662
//// This source file is free software; you can redistribute it   ////
3663
//// and/or modify it under the terms of the GNU Lesser General   ////
3664
//// Public License as published by the Free Software Foundation; ////
3665
//// either version 2.1 of the License, or (at your option) any   ////
3666
//// later version.                                               ////
3667
////                                                              ////
3668
//// This source is distributed in the hope that it will be       ////
3669
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3670
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3671
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3672
//// details.                                                     ////
3673
////                                                              ////
3674
//// You should have received a copy of the GNU Lesser General    ////
3675
//// Public License along with this source; if not, download it   ////
3676
//// from http://www.opencores.org/lgpl.shtml                     ////
3677
////                                                              ////
3678
//////////////////////////////////////////////////////////////////////
3679
 
3680
// GRAY counter
3681
 
3682 40 unneback
`define MODULE cnt_gray_ce_bin
3683
module `BASE`MODULE (
3684
`undef MODULE
3685
 cke, q, q_bin, rst, clk);
3686
 
3687 6 unneback
   parameter length = 4;
3688
   input cke;
3689
   output reg [length:1] q;
3690
   output [length:1] q_bin;
3691
   input rst;
3692
   input clk;
3693
 
3694
   parameter clear_value = 0;
3695
   parameter set_value = 1;
3696
   parameter wrap_value = 8;
3697
   parameter level1_value = 15;
3698
 
3699
   reg  [length:1] qi;
3700
   wire [length:1] q_next;
3701
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3702
 
3703
   always @ (posedge clk or posedge rst)
3704
     if (rst)
3705
       qi <= {length{1'b0}};
3706
     else
3707
     if (cke)
3708
       qi <= q_next;
3709
 
3710
   always @ (posedge clk or posedge rst)
3711
     if (rst)
3712
       q <= {length{1'b0}};
3713
     else
3714
       if (cke)
3715
         q <= (q_next>>1) ^ q_next;
3716
 
3717
   assign q_bin = qi;
3718
 
3719
endmodule
3720 40 unneback
`endif
3721 6 unneback
//////////////////////////////////////////////////////////////////////
3722
////                                                              ////
3723
////  Versatile library, counters                                 ////
3724
////                                                              ////
3725
////  Description                                                 ////
3726
////  counters                                                    ////
3727
////                                                              ////
3728
////                                                              ////
3729
////  To Do:                                                      ////
3730
////   - add more counters                                        ////
3731
////                                                              ////
3732
////  Author(s):                                                  ////
3733
////      - Michael Unneback, unneback@opencores.org              ////
3734
////        ORSoC AB                                              ////
3735
////                                                              ////
3736
//////////////////////////////////////////////////////////////////////
3737
////                                                              ////
3738
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3739
////                                                              ////
3740
//// This source file may be used and distributed without         ////
3741
//// restriction provided that this copyright statement is not    ////
3742
//// removed from the file and that any derivative work contains  ////
3743
//// the original copyright notice and the associated disclaimer. ////
3744
////                                                              ////
3745
//// This source file is free software; you can redistribute it   ////
3746
//// and/or modify it under the terms of the GNU Lesser General   ////
3747
//// Public License as published by the Free Software Foundation; ////
3748
//// either version 2.1 of the License, or (at your option) any   ////
3749
//// later version.                                               ////
3750
////                                                              ////
3751
//// This source is distributed in the hope that it will be       ////
3752
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3753
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3754
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3755
//// details.                                                     ////
3756
////                                                              ////
3757
//// You should have received a copy of the GNU Lesser General    ////
3758
//// Public License along with this source; if not, download it   ////
3759
//// from http://www.opencores.org/lgpl.shtml                     ////
3760
////                                                              ////
3761
//////////////////////////////////////////////////////////////////////
3762
 
3763 40 unneback
`ifdef CNT_SHREG_WRAP
3764
`define MODULE cnt_shreg_wrap
3765
module `BASE`MODULE ( q, rst, clk);
3766
`undef MODULE
3767 6 unneback
 
3768
   parameter length = 4;
3769
   output reg [0:length-1] q;
3770
   input rst;
3771
   input clk;
3772
 
3773
    always @ (posedge clk or posedge rst)
3774
    if (rst)
3775
        q <= {1'b1,{length-1{1'b0}}};
3776
    else
3777
        q <= {q[length-1],q[0:length-2]};
3778
 
3779
endmodule
3780 40 unneback
`endif
3781 6 unneback
 
3782 40 unneback
`ifdef CNT_SHREG_CE_WRAP
3783
`define MODULE cnt_shreg_ce_wrap
3784
module `BASE`MODULE ( cke, q, rst, clk);
3785
`undef MODULE
3786 6 unneback
 
3787
   parameter length = 4;
3788
   input cke;
3789
   output reg [0:length-1] q;
3790
   input rst;
3791
   input clk;
3792
 
3793
    always @ (posedge clk or posedge rst)
3794
    if (rst)
3795
        q <= {1'b1,{length-1{1'b0}}};
3796
    else
3797
        if (cke)
3798
            q <= {q[length-1],q[0:length-2]};
3799
 
3800
endmodule
3801 40 unneback
`endif
3802 6 unneback
 
3803 105 unneback
`ifdef CNT_SHREG_CLEAR
3804
`define MODULE cnt_shreg_clear
3805
module `BASE`MODULE ( clear, q, rst, clk);
3806
`undef MODULE
3807
 
3808
   parameter length = 4;
3809
   input clear;
3810
   output reg [0:length-1] q;
3811
   input rst;
3812
   input clk;
3813
 
3814
    always @ (posedge clk or posedge rst)
3815
    if (rst)
3816
        q <= {1'b1,{length-1{1'b0}}};
3817
    else
3818
        if (clear)
3819
            q <= {1'b1,{length-1{1'b0}}};
3820
        else
3821
            q <= q >> 1;
3822
 
3823
endmodule
3824
`endif
3825
 
3826 40 unneback
`ifdef CNT_SHREG_CE_CLEAR
3827
`define MODULE cnt_shreg_ce_clear
3828
module `BASE`MODULE ( cke, clear, q, rst, clk);
3829
`undef MODULE
3830 6 unneback
 
3831
   parameter length = 4;
3832
   input cke, clear;
3833
   output reg [0:length-1] q;
3834
   input rst;
3835
   input clk;
3836
 
3837
    always @ (posedge clk or posedge rst)
3838
    if (rst)
3839
        q <= {1'b1,{length-1{1'b0}}};
3840
    else
3841
        if (cke)
3842
            if (clear)
3843
                q <= {1'b1,{length-1{1'b0}}};
3844
            else
3845
                q <= q >> 1;
3846
 
3847
endmodule
3848 40 unneback
`endif
3849 6 unneback
 
3850 40 unneback
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3851
`define MODULE cnt_shreg_ce_clear_wrap
3852
module `BASE`MODULE ( cke, clear, q, rst, clk);
3853
`undef MODULE
3854 6 unneback
 
3855
   parameter length = 4;
3856
   input cke, clear;
3857
   output reg [0:length-1] q;
3858
   input rst;
3859
   input clk;
3860
 
3861
    always @ (posedge clk or posedge rst)
3862
    if (rst)
3863
        q <= {1'b1,{length-1{1'b0}}};
3864
    else
3865
        if (cke)
3866
            if (clear)
3867
                q <= {1'b1,{length-1{1'b0}}};
3868
            else
3869
            q <= {q[length-1],q[0:length-2]};
3870
 
3871
endmodule
3872 40 unneback
`endif
3873 6 unneback
//////////////////////////////////////////////////////////////////////
3874
////                                                              ////
3875
////  Versatile library, memories                                 ////
3876
////                                                              ////
3877
////  Description                                                 ////
3878
////  memories                                                    ////
3879
////                                                              ////
3880
////                                                              ////
3881
////  To Do:                                                      ////
3882
////   - add more memory types                                    ////
3883
////                                                              ////
3884
////  Author(s):                                                  ////
3885
////      - Michael Unneback, unneback@opencores.org              ////
3886
////        ORSoC AB                                              ////
3887
////                                                              ////
3888
//////////////////////////////////////////////////////////////////////
3889
////                                                              ////
3890
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3891
////                                                              ////
3892
//// This source file may be used and distributed without         ////
3893
//// restriction provided that this copyright statement is not    ////
3894
//// removed from the file and that any derivative work contains  ////
3895
//// the original copyright notice and the associated disclaimer. ////
3896
////                                                              ////
3897
//// This source file is free software; you can redistribute it   ////
3898
//// and/or modify it under the terms of the GNU Lesser General   ////
3899
//// Public License as published by the Free Software Foundation; ////
3900
//// either version 2.1 of the License, or (at your option) any   ////
3901
//// later version.                                               ////
3902
////                                                              ////
3903
//// This source is distributed in the hope that it will be       ////
3904
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3905
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3906
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3907
//// details.                                                     ////
3908
////                                                              ////
3909
//// You should have received a copy of the GNU Lesser General    ////
3910
//// Public License along with this source; if not, download it   ////
3911
//// from http://www.opencores.org/lgpl.shtml                     ////
3912
////                                                              ////
3913
//////////////////////////////////////////////////////////////////////
3914
 
3915 40 unneback
`ifdef ROM_INIT
3916 6 unneback
/// ROM
3917 40 unneback
`define MODULE rom_init
3918
module `BASE`MODULE ( adr, q, clk);
3919
`undef MODULE
3920 6 unneback
 
3921 7 unneback
   parameter data_width = 32;
3922
   parameter addr_width = 8;
3923 75 unneback
   parameter mem_size = 1<<addr_width;
3924 7 unneback
   input [(addr_width-1):0]       adr;
3925
   output reg [(data_width-1):0] q;
3926
   input                         clk;
3927 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
3928 7 unneback
   parameter memory_file = "vl_rom.vmem";
3929
   initial
3930
     begin
3931
        $readmemh(memory_file, rom);
3932
     end
3933
 
3934
   always @ (posedge clk)
3935
     q <= rom[adr];
3936 6 unneback
 
3937 7 unneback
endmodule
3938 40 unneback
`endif
3939 7 unneback
 
3940 40 unneback
`ifdef RAM
3941
`define MODULE ram
3942 6 unneback
// Single port RAM
3943 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
3944
`undef MODULE
3945 6 unneback
 
3946
   parameter data_width = 32;
3947
   parameter addr_width = 8;
3948 75 unneback
   parameter mem_size = 1<<addr_width;
3949 100 unneback
   parameter debug = 0;
3950 6 unneback
   input [(data_width-1):0]      d;
3951
   input [(addr_width-1):0]       adr;
3952
   input                         we;
3953 7 unneback
   output reg [(data_width-1):0] q;
3954 6 unneback
   input                         clk;
3955 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
3956 100 unneback
 
3957
    parameter memory_init = 0;
3958
    parameter memory_file = "vl_ram.vmem";
3959
    generate
3960
    if (memory_init == 1) begin : init_mem
3961
        initial
3962
            $readmemh(memory_file, ram);
3963
   end else if (memory_init == 2) begin : init_zero
3964
        integer k;
3965
        initial
3966
            for (k = 0; k < mem_size; k = k + 1)
3967
                ram[k] = 0;
3968 7 unneback
   end
3969
   endgenerate
3970
 
3971 100 unneback
    generate
3972
    if (debug==1) begin : debug_we
3973
        always @ (posedge clk)
3974
        if (we)
3975
            $display ("Value %h written at address %h : time %t", d, adr, $time);
3976
 
3977
    end
3978
    endgenerate
3979
 
3980 6 unneback
   always @ (posedge clk)
3981
   begin
3982
   if (we)
3983
     ram[adr] <= d;
3984
   q <= ram[adr];
3985
   end
3986
 
3987
endmodule
3988 40 unneback
`endif
3989 6 unneback
 
3990 40 unneback
`ifdef RAM_BE
3991
`define MODULE ram_be
3992 91 unneback
module `BASE`MODULE ( d, adr, be, we, q, clk);
3993 40 unneback
`undef MODULE
3994
 
3995 7 unneback
   parameter data_width = 32;
3996 72 unneback
   parameter addr_width = 6;
3997 75 unneback
   parameter mem_size = 1<<addr_width;
3998 7 unneback
   input [(data_width-1):0]      d;
3999
   input [(addr_width-1):0]       adr;
4000 73 unneback
   input [(data_width/8)-1:0]    be;
4001 7 unneback
   input                         we;
4002
   output reg [(data_width-1):0] q;
4003
   input                         clk;
4004
 
4005 85 unneback
 
4006 65 unneback
`ifdef SYSTEMVERILOG
4007 95 unneback
    // use a multi-dimensional packed array
4008
    //t o model individual bytes within the word
4009
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
4010 65 unneback
`else
4011 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
4012
    wire [data_width/8-1:0] cke;
4013 65 unneback
`endif
4014
 
4015 100 unneback
    parameter memory_init = 0;
4016
    parameter memory_file = "vl_ram.vmem";
4017
    generate
4018
    if (memory_init == 1) begin : init_mem
4019
        initial
4020
            $readmemh(memory_file, ram);
4021
    end else if (memory_init == 2) begin : init_zero
4022
        integer k;
4023
        initial
4024
            for (k = 0; k < mem_size; k = k + 1)
4025
                ram[k] = 0;
4026
    end
4027 7 unneback
   endgenerate
4028
 
4029 60 unneback
`ifdef SYSTEMVERILOG
4030
 
4031
always_ff@(posedge clk)
4032
begin
4033 95 unneback
    if(we) begin
4034 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
4035
        if(be[2]) ram[adr][2] <= d[23:16];
4036
        if(be[1]) ram[adr][1] <= d[15:8];
4037
        if(be[0]) ram[adr][0] <= d[7:0];
4038 60 unneback
    end
4039 90 unneback
        q <= ram[adr];
4040 60 unneback
end
4041
 
4042
`else
4043
 
4044 85 unneback
assign cke = {data_width/8{we}} & be;
4045 7 unneback
   genvar i;
4046 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
4047 7 unneback
      always @ (posedge clk)
4048 85 unneback
      if (cke[i])
4049 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
4050
   end
4051
   endgenerate
4052
 
4053
   always @ (posedge clk)
4054
      q <= ram[adr];
4055
 
4056 60 unneback
`endif
4057
 
4058 93 unneback
`ifdef verilator
4059 85 unneback
   // Function to access RAM (for use by Verilator).
4060
   function [31:0] get_mem;
4061
      // verilator public
4062 90 unneback
      input [addr_width-1:0]             addr;
4063 85 unneback
      get_mem = ram[addr];
4064
   endfunction // get_mem
4065
 
4066
   // Function to write RAM (for use by Verilator).
4067
   function set_mem;
4068
      // verilator public
4069 90 unneback
      input [addr_width-1:0]             addr;
4070
      input [data_width-1:0]             data;
4071 85 unneback
      ram[addr] = data;
4072
   endfunction // set_mem
4073 93 unneback
`endif
4074 85 unneback
 
4075 7 unneback
endmodule
4076 40 unneback
`endif
4077 7 unneback
 
4078 40 unneback
`ifdef DPRAM_1R1W
4079
`define MODULE dpram_1r1w
4080
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
4081
`undef MODULE
4082 6 unneback
   parameter data_width = 32;
4083
   parameter addr_width = 8;
4084 75 unneback
   parameter mem_size = 1<<addr_width;
4085 6 unneback
   input [(data_width-1):0]      d_a;
4086
   input [(addr_width-1):0]       adr_a;
4087
   input [(addr_width-1):0]       adr_b;
4088
   input                         we_a;
4089 118 unneback
   output reg [(data_width-1):0]          q_b;
4090 6 unneback
   input                         clk_a, clk_b;
4091 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4092 7 unneback
 
4093 100 unneback
    parameter memory_init = 0;
4094
    parameter memory_file = "vl_ram.vmem";
4095
    parameter debug = 0;
4096
 
4097
    generate
4098
    if (memory_init == 1) begin : init_mem
4099
        initial
4100
            $readmemh(memory_file, ram);
4101
    end else if (memory_init == 2) begin : init_zero
4102
        integer k;
4103
        initial
4104
            for (k = 0; k < mem_size; k = k + 1)
4105
                ram[k] = 0;
4106
    end
4107 7 unneback
   endgenerate
4108
 
4109 100 unneback
    generate
4110
    if (debug==1) begin : debug_we
4111
        always @ (posedge clk_a)
4112
        if (we_a)
4113
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4114
 
4115
    end
4116
    endgenerate
4117
 
4118 6 unneback
   always @ (posedge clk_a)
4119
   if (we_a)
4120
     ram[adr_a] <= d_a;
4121 118 unneback
 
4122 6 unneback
   always @ (posedge clk_b)
4123 118 unneback
      q_b = ram[adr_b];
4124 40 unneback
 
4125 6 unneback
endmodule
4126 40 unneback
`endif
4127 6 unneback
 
4128 40 unneback
`ifdef DPRAM_2R1W
4129
`define MODULE dpram_2r1w
4130
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
4131
`undef MODULE
4132
 
4133 6 unneback
   parameter data_width = 32;
4134
   parameter addr_width = 8;
4135 75 unneback
   parameter mem_size = 1<<addr_width;
4136 6 unneback
   input [(data_width-1):0]      d_a;
4137
   input [(addr_width-1):0]       adr_a;
4138
   input [(addr_width-1):0]       adr_b;
4139
   input                         we_a;
4140
   output [(data_width-1):0]      q_b;
4141
   output reg [(data_width-1):0] q_a;
4142
   input                         clk_a, clk_b;
4143
   reg [(data_width-1):0]         q_b;
4144 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4145 7 unneback
 
4146 100 unneback
    parameter memory_init = 0;
4147
    parameter memory_file = "vl_ram.vmem";
4148
    parameter debug = 0;
4149
 
4150
    generate
4151
    if (memory_init == 1) begin : init_mem
4152
        initial
4153
            $readmemh(memory_file, ram);
4154
    end else if (memory_init == 2) begin : init_zero
4155
        integer k;
4156
        initial
4157
            for (k = 0; k < mem_size; k = k + 1)
4158
                ram[k] = 0;
4159
    end
4160 7 unneback
   endgenerate
4161
 
4162 100 unneback
    generate
4163
    if (debug==1) begin : debug_we
4164
        always @ (posedge clk_a)
4165
        if (we_a)
4166
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4167
 
4168
    end
4169
    endgenerate
4170
 
4171 6 unneback
   always @ (posedge clk_a)
4172
     begin
4173
        q_a <= ram[adr_a];
4174
        if (we_a)
4175
             ram[adr_a] <= d_a;
4176
     end
4177
   always @ (posedge clk_b)
4178
          q_b <= ram[adr_b];
4179
endmodule
4180 40 unneback
`endif
4181 6 unneback
 
4182 100 unneback
`ifdef DPRAM_1R2W
4183
`define MODULE dpram_1r2w
4184
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
4185
`undef MODULE
4186
 
4187
   parameter data_width = 32;
4188
   parameter addr_width = 8;
4189
   parameter mem_size = 1<<addr_width;
4190
   input [(data_width-1):0]      d_a;
4191
   input [(addr_width-1):0]       adr_a;
4192
   input [(addr_width-1):0]       adr_b;
4193
   input                         we_a;
4194
   input [(data_width-1):0]       d_b;
4195
   output reg [(data_width-1):0] q_a;
4196
   input                         we_b;
4197
   input                         clk_a, clk_b;
4198
   reg [(data_width-1):0]         q_b;
4199 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4200 100 unneback
 
4201
    parameter memory_init = 0;
4202
    parameter memory_file = "vl_ram.vmem";
4203
    parameter debug = 0;
4204
 
4205
    generate
4206
    if (memory_init == 1) begin : init_mem
4207
        initial
4208
            $readmemh(memory_file, ram);
4209
    end else if (memory_init == 2) begin : init_zero
4210
        integer k;
4211
        initial
4212
            for (k = 0; k < mem_size; k = k + 1)
4213
                ram[k] = 0;
4214
    end
4215
   endgenerate
4216
 
4217
    generate
4218
    if (debug==1) begin : debug_we
4219
        always @ (posedge clk_a)
4220
        if (we_a)
4221
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4222
        always @ (posedge clk_b)
4223
        if (we_b)
4224
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4225
    end
4226
    endgenerate
4227
 
4228
   always @ (posedge clk_a)
4229
     begin
4230
        q_a <= ram[adr_a];
4231
        if (we_a)
4232
             ram[adr_a] <= d_a;
4233
     end
4234
   always @ (posedge clk_b)
4235
     begin
4236
        if (we_b)
4237
          ram[adr_b] <= d_b;
4238
     end
4239
endmodule
4240
`endif
4241
 
4242 40 unneback
`ifdef DPRAM_2R2W
4243
`define MODULE dpram_2r2w
4244
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
4245
`undef MODULE
4246
 
4247 6 unneback
   parameter data_width = 32;
4248
   parameter addr_width = 8;
4249 75 unneback
   parameter mem_size = 1<<addr_width;
4250 6 unneback
   input [(data_width-1):0]      d_a;
4251
   input [(addr_width-1):0]       adr_a;
4252
   input [(addr_width-1):0]       adr_b;
4253
   input                         we_a;
4254
   output [(data_width-1):0]      q_b;
4255
   input [(data_width-1):0]       d_b;
4256
   output reg [(data_width-1):0] q_a;
4257
   input                         we_b;
4258
   input                         clk_a, clk_b;
4259
   reg [(data_width-1):0]         q_b;
4260 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4261 7 unneback
 
4262 100 unneback
    parameter memory_init = 0;
4263
    parameter memory_file = "vl_ram.vmem";
4264
    parameter debug = 0;
4265
 
4266
    generate
4267
    if (memory_init) begin : init_mem
4268
        initial
4269
            $readmemh(memory_file, ram);
4270
    end else if (memory_init == 2) begin : init_zero
4271
        integer k;
4272
        initial
4273
            for (k = 0; k < mem_size; k = k + 1)
4274
                ram[k] = 0;
4275
    end
4276 7 unneback
   endgenerate
4277
 
4278 100 unneback
    generate
4279
    if (debug==1) begin : debug_we
4280
        always @ (posedge clk_a)
4281
        if (we_a)
4282
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4283
        always @ (posedge clk_b)
4284
        if (we_b)
4285
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4286
    end
4287
    endgenerate
4288
 
4289 6 unneback
   always @ (posedge clk_a)
4290
     begin
4291
        q_a <= ram[adr_a];
4292
        if (we_a)
4293
             ram[adr_a] <= d_a;
4294
     end
4295
   always @ (posedge clk_b)
4296
     begin
4297
        q_b <= ram[adr_b];
4298
        if (we_b)
4299
          ram[adr_b] <= d_b;
4300
     end
4301
endmodule
4302 40 unneback
`endif
4303 6 unneback
 
4304 83 unneback
 
4305 75 unneback
`ifdef DPRAM_BE_2R2W
4306
`define MODULE dpram_be_2r2w
4307 92 unneback
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
4308 75 unneback
`undef MODULE
4309
 
4310
   parameter a_data_width = 32;
4311
   parameter a_addr_width = 8;
4312 95 unneback
   parameter b_data_width = 64; //a_data_width;
4313 124 unneback
   //localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
4314
   localparam b_addr_width =
4315 125 unneback
        (a_data_width==b_data_width) ? a_addr_width :
4316
        (a_data_width==b_data_width*2) ? a_addr_width+1 :
4317
        (a_data_width==b_data_width*4) ? a_addr_width+2 :
4318
        (a_data_width==b_data_width*8) ? a_addr_width+3 :
4319
        (a_data_width==b_data_width*16) ? a_addr_width+4 :
4320
        (a_data_width==b_data_width*32) ? a_addr_width+5 :
4321
        (a_data_width==b_data_width/2) ? a_addr_width-1 :
4322
        (a_data_width==b_data_width/4) ? a_addr_width-2 :
4323
        (a_data_width==b_data_width/8) ? a_addr_width-3 :
4324
        (a_data_width==b_data_width/16) ? a_addr_width-4 :
4325
        (a_data_width==b_data_width/32) ? a_addr_width-5 : 0;
4326 124 unneback
 
4327 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
4328
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
4329 91 unneback
 
4330 100 unneback
   parameter memory_init = 0;
4331 95 unneback
   parameter memory_file = "vl_ram.vmem";
4332 100 unneback
   parameter debug = 0;
4333 95 unneback
 
4334 75 unneback
   input [(a_data_width-1):0]      d_a;
4335 91 unneback
   input [(a_addr_width-1):0]       adr_a;
4336
   input [(a_data_width/8-1):0]    be_a;
4337
   input                           we_a;
4338 75 unneback
   output reg [(a_data_width-1):0] q_a;
4339 91 unneback
   input [(b_data_width-1):0]       d_b;
4340
   input [(b_addr_width-1):0]       adr_b;
4341 92 unneback
   input [(b_data_width/8-1):0]    be_b;
4342
   input                           we_b;
4343
   output reg [(b_data_width-1):0]          q_b;
4344 91 unneback
   input                           clk_a, clk_b;
4345 75 unneback
 
4346 100 unneback
    generate
4347
    if (debug==1) begin : debug_we
4348
        always @ (posedge clk_a)
4349
        if (we_a)
4350
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4351
        always @ (posedge clk_b)
4352
        if (we_b)
4353
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4354
    end
4355
    endgenerate
4356
 
4357
 
4358 91 unneback
`ifdef SYSTEMVERILOG
4359
// use a multi-dimensional packed array
4360
//to model individual bytes within the word
4361
 
4362 75 unneback
generate
4363 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
4364 75 unneback
 
4365 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4366 95 unneback
 
4367
    initial
4368 100 unneback
        if (memory_init==1)
4369 95 unneback
            $readmemh(memory_file, ram);
4370 100 unneback
 
4371
    integer k;
4372
    initial
4373
        if (memory_init==2)
4374
            for (k = 0; k < mem_size; k = k + 1)
4375
                ram[k] = 0;
4376 91 unneback
 
4377
    always_ff@(posedge clk_a)
4378
    begin
4379
        if(we_a) begin
4380 100 unneback
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
4381
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
4382
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
4383
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
4384 91 unneback
        end
4385
    end
4386
 
4387 92 unneback
    always@(posedge clk_a)
4388
        q_a = ram[adr_a];
4389 91 unneback
 
4390
    always_ff@(posedge clk_b)
4391 92 unneback
    begin
4392
        if(we_b) begin
4393 100 unneback
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
4394
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
4395
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
4396
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
4397 92 unneback
        end
4398
    end
4399 91 unneback
 
4400 92 unneback
    always@(posedge clk_b)
4401
        q_b = ram[adr_b];
4402 91 unneback
 
4403 75 unneback
end
4404
endgenerate
4405
 
4406 95 unneback
generate
4407
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
4408
 
4409 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4410 95 unneback
 
4411
    initial
4412 100 unneback
        if (memory_init==1)
4413 95 unneback
            $readmemh(memory_file, ram);
4414 100 unneback
 
4415
    integer k;
4416
    initial
4417
        if (memory_init==2)
4418
            for (k = 0; k < mem_size; k = k + 1)
4419
                ram[k] = 0;
4420 95 unneback
 
4421
    always_ff@(posedge clk_a)
4422
    begin
4423
        if(we_a) begin
4424
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
4425
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
4426
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
4427
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
4428
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
4429
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
4430
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
4431
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
4432
        end
4433
    end
4434
 
4435
    always@(posedge clk_a)
4436
        q_a = ram[adr_a];
4437
 
4438
    always_ff@(posedge clk_b)
4439
    begin
4440
        if(we_b) begin
4441
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
4442
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
4443
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
4444
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
4445
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
4446
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
4447
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
4448
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
4449
        end
4450
    end
4451
 
4452
    always@(posedge clk_b)
4453
        q_b = ram[adr_b];
4454
 
4455
end
4456
endgenerate
4457
 
4458
generate
4459
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
4460
logic [31:0] temp;
4461
`define MODULE dpram_be_2r2w
4462 128 unneback
`BASE`MODULE # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
4463 95 unneback
`undef MODULE
4464 128 unneback
dpram3232 (
4465 95 unneback
    .d_a(d_a),
4466
    .q_a(q_a),
4467
    .adr_a(adr_a),
4468
    .be_a(be_a),
4469
    .we_a(we_a),
4470
    .clk_a(clk_a),
4471
    .d_b({d_b,d_b}),
4472
    .q_b(temp),
4473 128 unneback
    .adr_b(adr_b[b_addr_width-1:1]),
4474 137 unneback
    .be_b({be_b,be_b} & {{2{!adr_b[0]}},{2{adr_b[0]}}}),
4475 95 unneback
    .we_b(we_b),
4476
    .clk_b(clk_b)
4477
);
4478
 
4479 100 unneback
always @ (adr_b[0] or temp)
4480 95 unneback
    if (adr_b[0])
4481
        q_b = temp[31:16];
4482
    else
4483
        q_b = temp[15:0];
4484
 
4485
end
4486
endgenerate
4487
 
4488
generate
4489
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
4490
logic [63:0] temp;
4491
`define MODULE dpram_be_2r2w
4492 128 unneback
`BASE`MODULE # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
4493 95 unneback
`undef MODULE
4494
dpram6464 (
4495
    .d_a({d_a,d_a}),
4496
    .q_a(temp),
4497
    .adr_a(adr_a[a_addr_width-1:1]),
4498
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
4499
    .we_a(we_a),
4500
    .clk_a(clk_a),
4501
    .d_b(d_b),
4502
    .q_b(q_b),
4503
    .adr_b(adr_b),
4504
    .be_b(be_b),
4505
    .we_b(we_b),
4506
    .clk_b(clk_b)
4507
);
4508
 
4509 100 unneback
always @ (adr_a[0] or temp)
4510 95 unneback
    if (adr_a[0])
4511
        q_a = temp[63:32];
4512
    else
4513
        q_a = temp[31:0];
4514
 
4515
end
4516
endgenerate
4517
 
4518 91 unneback
`else
4519 92 unneback
    // This modules requires SystemVerilog
4520 98 unneback
    // at this point anyway
4521 91 unneback
`endif
4522 75 unneback
endmodule
4523
`endif
4524
 
4525 91 unneback
`ifdef CAM
4526 6 unneback
// Content addresable memory, CAM
4527 91 unneback
`endif
4528 6 unneback
 
4529 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
4530 6 unneback
// FIFO
4531 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
4532
module `BASE`MODULE (
4533
`undef MODULE
4534 25 unneback
    d, wr, fifo_full,
4535
    q, rd, fifo_empty,
4536
    fill_level,
4537
    clk, rst
4538
    );
4539
 
4540
parameter data_width = 18;
4541
parameter addr_width = 4;
4542 6 unneback
 
4543 25 unneback
// write side
4544
input  [data_width-1:0] d;
4545
input                   wr;
4546
output                  fifo_full;
4547
// read side
4548
output [data_width-1:0] q;
4549
input                   rd;
4550
output                  fifo_empty;
4551
// common
4552
output [addr_width:0]   fill_level;
4553
input rst, clk;
4554
 
4555
wire [addr_width:1] wadr, radr;
4556
 
4557 40 unneback
`define MODULE cnt_bin_ce
4558
`BASE`MODULE
4559 25 unneback
    # ( .length(addr_width))
4560
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
4561 40 unneback
`BASE`MODULE
4562 25 unneback
    # (.length(addr_width))
4563
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
4564 40 unneback
`undef MODULE
4565 25 unneback
 
4566 40 unneback
`define MODULE dpram_1r1w
4567
`BASE`MODULE
4568 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
4569
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
4570 40 unneback
`undef MODULE
4571 25 unneback
 
4572 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
4573
`BASE`MODULE
4574 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
4575 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
4576 40 unneback
`undef MODULE
4577 25 unneback
endmodule
4578 40 unneback
`endif
4579 25 unneback
 
4580 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
4581 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
4582
// RAM is supposed to be larger than the two FIFOs
4583
// LFSR counters used adr pointers
4584 40 unneback
`define MODULE fifo_2r2w_sync_simplex
4585
module `BASE`MODULE (
4586
`undef MODULE
4587 27 unneback
    // a side
4588
    a_d, a_wr, a_fifo_full,
4589
    a_q, a_rd, a_fifo_empty,
4590
    a_fill_level,
4591
    // b side
4592
    b_d, b_wr, b_fifo_full,
4593
    b_q, b_rd, b_fifo_empty,
4594
    b_fill_level,
4595
    // common
4596
    clk, rst
4597
    );
4598
parameter data_width = 8;
4599
parameter addr_width = 5;
4600
parameter fifo_full_level = (1<<addr_width)-1;
4601
 
4602
// a side
4603
input  [data_width-1:0] a_d;
4604
input                   a_wr;
4605
output                  a_fifo_full;
4606
output [data_width-1:0] a_q;
4607
input                   a_rd;
4608
output                  a_fifo_empty;
4609
output [addr_width-1:0] a_fill_level;
4610
 
4611
// b side
4612
input  [data_width-1:0] b_d;
4613
input                   b_wr;
4614
output                  b_fifo_full;
4615
output [data_width-1:0] b_q;
4616
input                   b_rd;
4617
output                  b_fifo_empty;
4618
output [addr_width-1:0] b_fill_level;
4619
 
4620
input                   clk;
4621
input                   rst;
4622
 
4623
// adr_gen
4624
wire [addr_width:1] a_wadr, a_radr;
4625
wire [addr_width:1] b_wadr, b_radr;
4626
// dpram
4627
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4628
 
4629 40 unneback
`define MODULE cnt_lfsr_ce
4630
`BASE`MODULE
4631 27 unneback
    # ( .length(addr_width))
4632
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
4633
 
4634 40 unneback
`BASE`MODULE
4635 27 unneback
    # (.length(addr_width))
4636
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
4637
 
4638 40 unneback
`BASE`MODULE
4639 27 unneback
    # ( .length(addr_width))
4640
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
4641
 
4642 40 unneback
`BASE`MODULE
4643 27 unneback
    # (.length(addr_width))
4644
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
4645 40 unneback
`undef MODULE
4646 27 unneback
 
4647
// mux read or write adr to DPRAM
4648
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
4649
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
4650
 
4651 40 unneback
`define MODULE dpram_2r2w
4652
`BASE`MODULE
4653 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
4654
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4655
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4656 40 unneback
`undef MODULE
4657
 
4658
`define MODULE cnt_bin_ce_rew_zq_l1
4659
`BASE`MODULE
4660 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
4661 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
4662
 
4663 40 unneback
`BASE`MODULE
4664 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
4665 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
4666 40 unneback
`undef MODULE
4667 27 unneback
 
4668
endmodule
4669 40 unneback
`endif
4670 27 unneback
 
4671 40 unneback
`ifdef FIFO_CMP_ASYNC
4672
`define MODULE fifo_cmp_async
4673
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
4674
`undef MODULE
4675 6 unneback
 
4676 11 unneback
   parameter addr_width = 4;
4677
   parameter N = addr_width-1;
4678 6 unneback
 
4679
   parameter Q1 = 2'b00;
4680
   parameter Q2 = 2'b01;
4681
   parameter Q3 = 2'b11;
4682
   parameter Q4 = 2'b10;
4683
 
4684
   parameter going_empty = 1'b0;
4685
   parameter going_full  = 1'b1;
4686
 
4687
   input [N:0]  wptr, rptr;
4688 14 unneback
   output       fifo_empty;
4689 6 unneback
   output       fifo_full;
4690
   input        wclk, rclk, rst;
4691
 
4692
`ifndef GENERATE_DIRECTION_AS_LATCH
4693
   wire direction;
4694
`endif
4695
`ifdef GENERATE_DIRECTION_AS_LATCH
4696
   reg direction;
4697
`endif
4698
   reg  direction_set, direction_clr;
4699
 
4700
   wire async_empty, async_full;
4701
   wire fifo_full2;
4702 14 unneback
   wire fifo_empty2;
4703 6 unneback
 
4704
   // direction_set
4705
   always @ (wptr[N:N-1] or rptr[N:N-1])
4706
     case ({wptr[N:N-1],rptr[N:N-1]})
4707
       {Q1,Q2} : direction_set <= 1'b1;
4708
       {Q2,Q3} : direction_set <= 1'b1;
4709
       {Q3,Q4} : direction_set <= 1'b1;
4710
       {Q4,Q1} : direction_set <= 1'b1;
4711
       default : direction_set <= 1'b0;
4712
     endcase
4713
 
4714
   // direction_clear
4715
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
4716
     if (rst)
4717
       direction_clr <= 1'b1;
4718
     else
4719
       case ({wptr[N:N-1],rptr[N:N-1]})
4720
         {Q2,Q1} : direction_clr <= 1'b1;
4721
         {Q3,Q2} : direction_clr <= 1'b1;
4722
         {Q4,Q3} : direction_clr <= 1'b1;
4723
         {Q1,Q4} : direction_clr <= 1'b1;
4724
         default : direction_clr <= 1'b0;
4725
       endcase
4726
 
4727 40 unneback
`define MODULE dff_sr
4728 6 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
4729 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
4730 6 unneback
`endif
4731
 
4732
`ifdef GENERATE_DIRECTION_AS_LATCH
4733
   always @ (posedge direction_set or posedge direction_clr)
4734
     if (direction_clr)
4735
       direction <= going_empty;
4736
     else
4737
       direction <= going_full;
4738
`endif
4739
 
4740
   assign async_empty = (wptr == rptr) && (direction==going_empty);
4741
   assign async_full  = (wptr == rptr) && (direction==going_full);
4742
 
4743 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
4744
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
4745
`undef MODULE
4746 6 unneback
 
4747
/*
4748
   always @ (posedge wclk or posedge rst or posedge async_full)
4749
     if (rst)
4750
       {fifo_full, fifo_full2} <= 2'b00;
4751
     else if (async_full)
4752
       {fifo_full, fifo_full2} <= 2'b11;
4753
     else
4754
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
4755
*/
4756 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
4757 6 unneback
     if (async_empty)
4758
       {fifo_empty, fifo_empty2} <= 2'b11;
4759
     else
4760 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
4761 40 unneback
`define MODULE dff
4762
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
4763
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
4764
`undef MODULE
4765 27 unneback
endmodule // async_compb
4766 40 unneback
`endif
4767 6 unneback
 
4768 40 unneback
`ifdef FIFO_1R1W_ASYNC
4769
`define MODULE fifo_1r1w_async
4770
module `BASE`MODULE (
4771
`undef MODULE
4772 6 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
4773
    q, rd, fifo_empty, rd_clk, rd_rst
4774
    );
4775
 
4776
parameter data_width = 18;
4777
parameter addr_width = 4;
4778
 
4779
// write side
4780
input  [data_width-1:0] d;
4781
input                   wr;
4782
output                  fifo_full;
4783
input                   wr_clk;
4784
input                   wr_rst;
4785
// read side
4786
output [data_width-1:0] q;
4787
input                   rd;
4788
output                  fifo_empty;
4789
input                   rd_clk;
4790
input                   rd_rst;
4791
 
4792
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
4793 23 unneback
 
4794 40 unneback
`define MODULE cnt_gray_ce_bin
4795
`BASE`MODULE
4796 6 unneback
    # ( .length(addr_width))
4797
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
4798
 
4799 40 unneback
`BASE`MODULE
4800 6 unneback
    # (.length(addr_width))
4801 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
4802 40 unneback
`undef MODULE
4803 6 unneback
 
4804 40 unneback
`define MODULE dpram_1r1w
4805
`BASE`MODULE
4806 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
4807
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
4808 40 unneback
`undef MODULE
4809 6 unneback
 
4810 40 unneback
`define MODULE fifo_cmp_async
4811
`BASE`MODULE
4812 6 unneback
    # (.addr_width(addr_width))
4813
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
4814 40 unneback
`undef MODULE
4815 6 unneback
 
4816
endmodule
4817 40 unneback
`endif
4818 6 unneback
 
4819 40 unneback
`ifdef FIFO_2R2W_ASYNC
4820
`define MODULE fifo_2r2w_async
4821
module `BASE`MODULE (
4822
`undef MODULE
4823 6 unneback
    // a side
4824
    a_d, a_wr, a_fifo_full,
4825
    a_q, a_rd, a_fifo_empty,
4826
    a_clk, a_rst,
4827
    // b side
4828
    b_d, b_wr, b_fifo_full,
4829
    b_q, b_rd, b_fifo_empty,
4830
    b_clk, b_rst
4831
    );
4832
 
4833
parameter data_width = 18;
4834
parameter addr_width = 4;
4835
 
4836
// a side
4837
input  [data_width-1:0] a_d;
4838
input                   a_wr;
4839
output                  a_fifo_full;
4840
output [data_width-1:0] a_q;
4841
input                   a_rd;
4842
output                  a_fifo_empty;
4843
input                   a_clk;
4844
input                   a_rst;
4845
 
4846
// b side
4847
input  [data_width-1:0] b_d;
4848
input                   b_wr;
4849
output                  b_fifo_full;
4850
output [data_width-1:0] b_q;
4851
input                   b_rd;
4852
output                  b_fifo_empty;
4853
input                   b_clk;
4854
input                   b_rst;
4855
 
4856 40 unneback
`define MODULE fifo_1r1w_async
4857
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4858 6 unneback
vl_fifo_1r1w_async_a (
4859
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4860
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4861
    );
4862
 
4863 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4864 6 unneback
vl_fifo_1r1w_async_b (
4865
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4866
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4867
    );
4868 40 unneback
`undef MODULE
4869
 
4870 6 unneback
endmodule
4871 40 unneback
`endif
4872 6 unneback
 
4873 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4874
`define MODULE fifo_2r2w_async_simplex
4875
module `BASE`MODULE (
4876
`undef MODULE
4877 6 unneback
    // a side
4878
    a_d, a_wr, a_fifo_full,
4879
    a_q, a_rd, a_fifo_empty,
4880
    a_clk, a_rst,
4881
    // b side
4882
    b_d, b_wr, b_fifo_full,
4883
    b_q, b_rd, b_fifo_empty,
4884
    b_clk, b_rst
4885
    );
4886
 
4887
parameter data_width = 18;
4888
parameter addr_width = 4;
4889
 
4890
// a side
4891
input  [data_width-1:0] a_d;
4892
input                   a_wr;
4893
output                  a_fifo_full;
4894
output [data_width-1:0] a_q;
4895
input                   a_rd;
4896
output                  a_fifo_empty;
4897
input                   a_clk;
4898
input                   a_rst;
4899
 
4900
// b side
4901
input  [data_width-1:0] b_d;
4902
input                   b_wr;
4903
output                  b_fifo_full;
4904
output [data_width-1:0] b_q;
4905
input                   b_rd;
4906
output                  b_fifo_empty;
4907
input                   b_clk;
4908
input                   b_rst;
4909
 
4910
// adr_gen
4911
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4912
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4913
// dpram
4914
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4915
 
4916 40 unneback
`define MODULE cnt_gray_ce_bin
4917
`BASE`MODULE
4918 6 unneback
    # ( .length(addr_width))
4919
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4920
 
4921 40 unneback
`BASE`MODULE
4922 6 unneback
    # (.length(addr_width))
4923
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4924
 
4925 40 unneback
`BASE`MODULE
4926 6 unneback
    # ( .length(addr_width))
4927
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4928
 
4929 40 unneback
`BASE`MODULE
4930 6 unneback
    # (.length(addr_width))
4931
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4932 40 unneback
`undef MODULE
4933 6 unneback
 
4934
// mux read or write adr to DPRAM
4935
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4936
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4937
 
4938 40 unneback
`define MODULE dpram_2r2w
4939
`BASE`MODULE
4940 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
4941
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4942
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4943 40 unneback
`undef MODULE
4944 6 unneback
 
4945 40 unneback
`define MODULE fifo_cmp_async
4946
`BASE`MODULE
4947 6 unneback
    # (.addr_width(addr_width))
4948
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4949
 
4950 40 unneback
`BASE`MODULE
4951 6 unneback
    # (.addr_width(addr_width))
4952
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4953 40 unneback
`undef MODULE
4954 6 unneback
 
4955
endmodule
4956 40 unneback
`endif
4957 48 unneback
 
4958
`ifdef REG_FILE
4959
`define MODULE reg_file
4960
module `BASE`MODULE (
4961
`undef MODULE
4962
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4963
);
4964
parameter data_width = 32;
4965
parameter addr_width = 5;
4966
input [addr_width-1:0] a1, a2, a3;
4967
input [data_width-1:0] wd3;
4968
input we3;
4969
output [data_width-1:0] rd1, rd2;
4970
input clk;
4971
 
4972
`ifdef ACTEL
4973
reg [data_width-1:0] wd3_reg;
4974
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4975
reg we3_reg;
4976 98 unneback
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
4977
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
4978 48 unneback
always @ (posedge clk or posedge rst)
4979
if (rst)
4980
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4981
else
4982
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4983
 
4984
    always @ (negedge clk)
4985
    if (we3_reg)
4986
        ram1[a3_reg] <= wd3;
4987
    always @ (posedge clk)
4988
        a1_reg <= a1;
4989
    assign rd1 = ram1[a1_reg];
4990
 
4991
    always @ (negedge clk)
4992
    if (we3_reg)
4993
        ram2[a3_reg] <= wd3;
4994
    always @ (posedge clk)
4995
        a2_reg <= a2;
4996
    assign rd2 = ram2[a2_reg];
4997
 
4998
`else
4999
 
5000
`define MODULE dpram_1r1w
5001
`BASE`MODULE
5002
    # ( .data_width(data_width), .addr_width(addr_width))
5003
    ram1 (
5004
        .d_a(wd3),
5005
        .adr_a(a3),
5006
        .we_a(we3),
5007
        .clk_a(clk),
5008
        .q_b(rd1),
5009
        .adr_b(a1),
5010
        .clk_b(clk) );
5011
 
5012
`BASE`MODULE
5013
    # ( .data_width(data_width), .addr_width(addr_width))
5014
    ram2 (
5015
        .d_a(wd3),
5016
        .adr_a(a3),
5017
        .we_a(we3),
5018
        .clk_a(clk),
5019
        .q_b(rd2),
5020
        .adr_b(a2),
5021
        .clk_b(clk) );
5022
`undef MODULE
5023
 
5024
`endif
5025
 
5026
endmodule
5027
`endif
5028 12 unneback
//////////////////////////////////////////////////////////////////////
5029
////                                                              ////
5030
////  Versatile library, wishbone stuff                           ////
5031
////                                                              ////
5032
////  Description                                                 ////
5033
////  Wishbone compliant modules                                  ////
5034
////                                                              ////
5035
////                                                              ////
5036
////  To Do:                                                      ////
5037
////   -                                                          ////
5038
////                                                              ////
5039
////  Author(s):                                                  ////
5040
////      - Michael Unneback, unneback@opencores.org              ////
5041
////        ORSoC AB                                              ////
5042
////                                                              ////
5043
//////////////////////////////////////////////////////////////////////
5044
////                                                              ////
5045
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
5046
////                                                              ////
5047
//// This source file may be used and distributed without         ////
5048
//// restriction provided that this copyright statement is not    ////
5049
//// removed from the file and that any derivative work contains  ////
5050
//// the original copyright notice and the associated disclaimer. ////
5051
////                                                              ////
5052
//// This source file is free software; you can redistribute it   ////
5053
//// and/or modify it under the terms of the GNU Lesser General   ////
5054
//// Public License as published by the Free Software Foundation; ////
5055
//// either version 2.1 of the License, or (at your option) any   ////
5056
//// later version.                                               ////
5057
////                                                              ////
5058
//// This source is distributed in the hope that it will be       ////
5059
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
5060
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
5061
//// PURPOSE.  See the GNU Lesser General Public License for more ////
5062
//// details.                                                     ////
5063
////                                                              ////
5064
//// You should have received a copy of the GNU Lesser General    ////
5065
//// Public License along with this source; if not, download it   ////
5066
//// from http://www.opencores.org/lgpl.shtml                     ////
5067
////                                                              ////
5068
//////////////////////////////////////////////////////////////////////
5069
 
5070 75 unneback
`ifdef WB_ADR_INC
5071
`timescale 1ns/1ns
5072
`define MODULE wb_adr_inc
5073 85 unneback
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
5074 75 unneback
`undef MODULE
5075 83 unneback
parameter adr_width = 10;
5076
parameter max_burst_width = 4;
5077 85 unneback
input cyc_i, stb_i, we_i;
5078 83 unneback
input [2:0] cti_i;
5079
input [1:0] bte_i;
5080
input [adr_width-1:0] adr_i;
5081
output [adr_width-1:0] adr_o;
5082
output ack_o;
5083
input clk, rst;
5084 75 unneback
 
5085 83 unneback
reg [adr_width-1:0] adr;
5086 90 unneback
wire [max_burst_width-1:0] to_adr;
5087 91 unneback
reg [max_burst_width-1:0] last_adr;
5088 92 unneback
reg last_cycle;
5089
localparam idle_or_eoc = 1'b0;
5090
localparam cyc_or_ws   = 1'b1;
5091 90 unneback
 
5092 91 unneback
always @ (posedge clk or posedge rst)
5093
if (rst)
5094
    last_adr <= {max_burst_width{1'b0}};
5095
else
5096
    if (stb_i)
5097 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
5098 91 unneback
 
5099 83 unneback
generate
5100
if (max_burst_width==0) begin : inst_0
5101 97 unneback
 
5102
        reg ack_o;
5103
        assign adr_o = adr_i;
5104
        always @ (posedge clk or posedge rst)
5105
        if (rst)
5106
            ack_o <= 1'b0;
5107
        else
5108
            ack_o <= cyc_i & stb_i & !ack_o;
5109
 
5110 83 unneback
end else begin
5111
 
5112
    always @ (posedge clk or posedge rst)
5113
    if (rst)
5114 92 unneback
        last_cycle <= idle_or_eoc;
5115 83 unneback
    else
5116 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
5117
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
5118
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
5119
                      cyc_or_ws; // cyc
5120
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
5121 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
5122 91 unneback
                                        (!stb_i) ? last_adr :
5123 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
5124 85 unneback
                                        adr[max_burst_width-1:0];
5125 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
5126 97 unneback
 
5127 83 unneback
end
5128
endgenerate
5129
 
5130
generate
5131
if (max_burst_width==2) begin : inst_2
5132
    always @ (posedge clk or posedge rst)
5133
    if (rst)
5134
        adr <= 2'h0;
5135
    else
5136
        if (cyc_i & stb_i)
5137
            adr[1:0] <= to_adr[1:0] + 2'd1;
5138 75 unneback
        else
5139 83 unneback
            adr <= to_adr[1:0];
5140
end
5141
endgenerate
5142
 
5143
generate
5144
if (max_burst_width==3) begin : inst_3
5145
    always @ (posedge clk or posedge rst)
5146
    if (rst)
5147
        adr <= 3'h0;
5148
    else
5149
        if (cyc_i & stb_i)
5150
            case (bte_i)
5151
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
5152
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
5153 75 unneback
            endcase
5154 83 unneback
        else
5155
            adr <= to_adr[2:0];
5156
end
5157
endgenerate
5158
 
5159
generate
5160
if (max_burst_width==4) begin : inst_4
5161
    always @ (posedge clk or posedge rst)
5162
    if (rst)
5163
        adr <= 4'h0;
5164
    else
5165 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
5166 83 unneback
            case (bte_i)
5167
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
5168
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
5169
            default: adr[3:0] <= to_adr + 4'd1;
5170
            endcase
5171
        else
5172
            adr <= to_adr[3:0];
5173
end
5174
endgenerate
5175
 
5176
generate
5177
if (adr_width > max_burst_width) begin : pass_through
5178
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
5179
end
5180
endgenerate
5181
 
5182
endmodule
5183 75 unneback
`endif
5184
 
5185 105 unneback
`ifdef WB_B4_EOC
5186
`define MODULE wb_b4_eoc
5187
module `BASE`MODULE ( cyc_i, stb_i, stall_o, ack_o, busy, eoc, clk, rst);
5188
`undef MODULE
5189
input cyc_i, stb_i, ack_o;
5190
output busy, eoc;
5191
input clk, rst;
5192
 
5193
`define MODULE cnt_bin_ce_rew_zq_l1
5194
`BASE`MODULE # ( .length(4), level1_value(1))
5195
cnt0 (
5196
    .cke(), .rew(), .zq(), .level1(), .rst(), clk);
5197
`undef MODULE
5198
 
5199
endmodule
5200
`endif
5201
 
5202 40 unneback
`ifdef WB3WB3_BRIDGE
5203 12 unneback
// async wb3 - wb3 bridge
5204
`timescale 1ns/1ns
5205 40 unneback
`define MODULE wb3wb3_bridge
5206
module `BASE`MODULE (
5207
`undef MODULE
5208 12 unneback
        // wishbone slave side
5209
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5210
        // wishbone master side
5211
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
5212
 
5213 95 unneback
parameter style = "FIFO"; // valid: simple, FIFO
5214
parameter addr_width = 4;
5215
 
5216 12 unneback
input [31:0] wbs_dat_i;
5217
input [31:2] wbs_adr_i;
5218
input [3:0]  wbs_sel_i;
5219
input [1:0]  wbs_bte_i;
5220
input [2:0]  wbs_cti_i;
5221
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
5222
output [31:0] wbs_dat_o;
5223 14 unneback
output wbs_ack_o;
5224 12 unneback
input wbs_clk, wbs_rst;
5225
 
5226
output [31:0] wbm_dat_o;
5227
output reg [31:2] wbm_adr_o;
5228
output [3:0]  wbm_sel_o;
5229
output reg [1:0]  wbm_bte_o;
5230
output reg [2:0]  wbm_cti_o;
5231 14 unneback
output reg wbm_we_o;
5232
output wbm_cyc_o;
5233 12 unneback
output wbm_stb_o;
5234
input [31:0]  wbm_dat_i;
5235
input wbm_ack_i;
5236
input wbm_clk, wbm_rst;
5237
 
5238
// bte
5239
parameter linear       = 2'b00;
5240
parameter wrap4        = 2'b01;
5241
parameter wrap8        = 2'b10;
5242
parameter wrap16       = 2'b11;
5243
// cti
5244
parameter classic      = 3'b000;
5245
parameter incburst     = 3'b010;
5246
parameter endofburst   = 3'b111;
5247
 
5248 95 unneback
localparam wbs_adr  = 1'b0;
5249
localparam wbs_data = 1'b1;
5250 12 unneback
 
5251 95 unneback
localparam wbm_adr0      = 2'b00;
5252
localparam wbm_adr1      = 2'b01;
5253
localparam wbm_data      = 2'b10;
5254
localparam wbm_data_wait = 2'b11;
5255 12 unneback
 
5256
reg [1:0] wbs_bte_reg;
5257
reg wbs;
5258
wire wbs_eoc_alert, wbm_eoc_alert;
5259
reg wbs_eoc, wbm_eoc;
5260
reg [1:0] wbm;
5261
 
5262 14 unneback
wire [1:16] wbs_count, wbm_count;
5263 12 unneback
 
5264
wire [35:0] a_d, a_q, b_d, b_q;
5265
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
5266
reg a_rd_reg;
5267
wire b_rd_adr, b_rd_data;
5268 14 unneback
wire b_rd_data_reg;
5269
wire [35:0] temp;
5270 12 unneback
 
5271
`define WE 5
5272
`define BTE 4:3
5273
`define CTI 2:0
5274
 
5275
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
5276
always @ (posedge wbs_clk or posedge wbs_rst)
5277
if (wbs_rst)
5278
        wbs_eoc <= 1'b0;
5279
else
5280
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
5281 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
5282 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
5283
                wbs_eoc <= 1'b1;
5284
 
5285 40 unneback
`define MODULE cnt_shreg_ce_clear
5286
`BASE`MODULE # ( .length(16))
5287
`undef MODULE
5288 12 unneback
    cnt0 (
5289
        .cke(wbs_ack_o),
5290
        .clear(wbs_eoc),
5291
        .q(wbs_count),
5292
        .rst(wbs_rst),
5293
        .clk(wbs_clk));
5294
 
5295
always @ (posedge wbs_clk or posedge wbs_rst)
5296
if (wbs_rst)
5297
        wbs <= wbs_adr;
5298
else
5299 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
5300 12 unneback
                wbs <= wbs_data;
5301
        else if (wbs_eoc & wbs_ack_o)
5302
                wbs <= wbs_adr;
5303
 
5304
// wbs FIFO
5305 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
5306
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
5307 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
5308
              1'b0;
5309
assign a_rd = !a_fifo_empty;
5310
always @ (posedge wbs_clk or posedge wbs_rst)
5311
if (wbs_rst)
5312
        a_rd_reg <= 1'b0;
5313
else
5314
        a_rd_reg <= a_rd;
5315
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
5316
 
5317
assign wbs_dat_o = a_q[35:4];
5318
 
5319
always @ (posedge wbs_clk or posedge wbs_rst)
5320
if (wbs_rst)
5321 13 unneback
        wbs_bte_reg <= 2'b00;
5322 12 unneback
else
5323 13 unneback
        wbs_bte_reg <= wbs_bte_i;
5324 12 unneback
 
5325
// wbm FIFO
5326
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
5327
always @ (posedge wbm_clk or posedge wbm_rst)
5328
if (wbm_rst)
5329
        wbm_eoc <= 1'b0;
5330
else
5331
        if (wbm==wbm_adr0 & !b_fifo_empty)
5332
                wbm_eoc <= b_q[`BTE] == linear;
5333
        else if (wbm_eoc_alert & wbm_ack_i)
5334
                wbm_eoc <= 1'b1;
5335
 
5336
always @ (posedge wbm_clk or posedge wbm_rst)
5337
if (wbm_rst)
5338
        wbm <= wbm_adr0;
5339
else
5340 33 unneback
/*
5341 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
5342
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
5343
        (wbm==wbm_adr1 & !wbm_we_o) |
5344
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
5345
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
5346 33 unneback
*/
5347
    case (wbm)
5348
    wbm_adr0:
5349
        if (!b_fifo_empty)
5350
            wbm <= wbm_adr1;
5351
    wbm_adr1:
5352
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
5353
            wbm <= wbm_data;
5354
    wbm_data:
5355
        if (wbm_ack_i & wbm_eoc)
5356
            wbm <= wbm_adr0;
5357
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
5358
            wbm <= wbm_data_wait;
5359
    wbm_data_wait:
5360
        if (!b_fifo_empty)
5361
            wbm <= wbm_data;
5362
    endcase
5363 12 unneback
 
5364
assign b_d = {wbm_dat_i,4'b1111};
5365
assign b_wr = !wbm_we_o & wbm_ack_i;
5366
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
5367
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
5368
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
5369 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
5370 12 unneback
                   1'b0;
5371
assign b_rd = b_rd_adr | b_rd_data;
5372
 
5373 40 unneback
`define MODULE dff
5374
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
5375
`undef MODULE
5376
`define MODULE dff_ce
5377
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
5378
`undef MODULE
5379 12 unneback
 
5380
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
5381
 
5382 40 unneback
`define MODULE cnt_shreg_ce_clear
5383 42 unneback
`BASE`MODULE # ( .length(16))
5384 40 unneback
`undef MODULE
5385 12 unneback
    cnt1 (
5386
        .cke(wbm_ack_i),
5387
        .clear(wbm_eoc),
5388
        .q(wbm_count),
5389
        .rst(wbm_rst),
5390
        .clk(wbm_clk));
5391
 
5392 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
5393
assign wbm_stb_o = (wbm==wbm_data);
5394 12 unneback
 
5395
always @ (posedge wbm_clk or posedge wbm_rst)
5396
if (wbm_rst)
5397
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
5398
else begin
5399
        if (wbm==wbm_adr0 & !b_fifo_empty)
5400
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
5401
        else if (wbm_eoc_alert & wbm_ack_i)
5402
                wbm_cti_o <= endofburst;
5403
end
5404
 
5405
//async_fifo_dw_simplex_top
5406 40 unneback
`define MODULE fifo_2r2w_async_simplex
5407
`BASE`MODULE
5408
`undef MODULE
5409 12 unneback
# ( .data_width(36), .addr_width(addr_width))
5410
fifo (
5411
    // a side
5412
    .a_d(a_d),
5413
    .a_wr(a_wr),
5414
    .a_fifo_full(a_fifo_full),
5415
    .a_q(a_q),
5416
    .a_rd(a_rd),
5417
    .a_fifo_empty(a_fifo_empty),
5418
    .a_clk(wbs_clk),
5419
    .a_rst(wbs_rst),
5420
    // b side
5421
    .b_d(b_d),
5422
    .b_wr(b_wr),
5423
    .b_fifo_full(b_fifo_full),
5424
    .b_q(b_q),
5425
    .b_rd(b_rd),
5426
    .b_fifo_empty(b_fifo_empty),
5427
    .b_clk(wbm_clk),
5428
    .b_rst(wbm_rst)
5429
    );
5430
 
5431
endmodule
5432 40 unneback
`undef WE
5433
`undef BTE
5434
`undef CTI
5435
`endif
5436 17 unneback
 
5437 75 unneback
`ifdef WB3AVALON_BRIDGE
5438
`define MODULE wb3avalon_bridge
5439
module `BASE`MODULE (
5440
`undef MODULE
5441
        // wishbone slave side
5442
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5443 77 unneback
        // avalon master side
5444 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
5445
 
5446 85 unneback
parameter linewrapburst = 1'b0;
5447
 
5448 75 unneback
input [31:0] wbs_dat_i;
5449
input [31:2] wbs_adr_i;
5450
input [3:0]  wbs_sel_i;
5451
input [1:0]  wbs_bte_i;
5452
input [2:0]  wbs_cti_i;
5453 83 unneback
input wbs_we_i;
5454
input wbs_cyc_i;
5455
input wbs_stb_i;
5456 75 unneback
output [31:0] wbs_dat_o;
5457
output wbs_ack_o;
5458
input wbs_clk, wbs_rst;
5459
 
5460
input [31:0] readdata;
5461
output [31:0] writedata;
5462
output [31:2] address;
5463
output [3:0]  be;
5464
output write;
5465 81 unneback
output read;
5466 75 unneback
output beginbursttransfer;
5467
output [3:0] burstcount;
5468
input readdatavalid;
5469
input waitrequest;
5470
input clk;
5471
input rst;
5472
 
5473
wire [1:0] wbm_bte_o;
5474
wire [2:0] wbm_cti_o;
5475
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
5476
reg last_cyc;
5477 79 unneback
reg [3:0] counter;
5478 82 unneback
reg read_busy;
5479 75 unneback
 
5480
always @ (posedge clk or posedge rst)
5481
if (rst)
5482
    last_cyc <= 1'b0;
5483
else
5484
    last_cyc <= wbm_cyc_o;
5485
 
5486 79 unneback
always @ (posedge clk or posedge rst)
5487
if (rst)
5488 82 unneback
    read_busy <= 1'b0;
5489 79 unneback
else
5490 82 unneback
    if (read & !waitrequest)
5491
        read_busy <= 1'b1;
5492
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
5493
        read_busy <= 1'b0;
5494
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
5495 81 unneback
 
5496 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
5497
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
5498
                    (wbm_bte_o==2'b10) ? 4'd8 :
5499 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
5500
                    4'd1;
5501 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
5502 75 unneback
 
5503 79 unneback
always @ (posedge clk or posedge rst)
5504
if (rst) begin
5505
    counter <= 4'd0;
5506
end else
5507 80 unneback
    if (wbm_we_o) begin
5508
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
5509 85 unneback
            counter <= burstcount -4'd1;
5510 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
5511
            counter <= burstcount;
5512
        end else if (!waitrequest & wbm_stb_o) begin
5513
            counter <= counter - 4'd1;
5514
        end
5515 82 unneback
    end
5516 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
5517 79 unneback
 
5518 75 unneback
`define MODULE wb3wb3_bridge
5519 77 unneback
`BASE`MODULE wbwb3inst (
5520 75 unneback
`undef MODULE
5521
    // wishbone slave side
5522
    .wbs_dat_i(wbs_dat_i),
5523
    .wbs_adr_i(wbs_adr_i),
5524
    .wbs_sel_i(wbs_sel_i),
5525
    .wbs_bte_i(wbs_bte_i),
5526
    .wbs_cti_i(wbs_cti_i),
5527
    .wbs_we_i(wbs_we_i),
5528
    .wbs_cyc_i(wbs_cyc_i),
5529
    .wbs_stb_i(wbs_stb_i),
5530
    .wbs_dat_o(wbs_dat_o),
5531
    .wbs_ack_o(wbs_ack_o),
5532
    .wbs_clk(wbs_clk),
5533
    .wbs_rst(wbs_rst),
5534
    // wishbone master side
5535
    .wbm_dat_o(writedata),
5536 78 unneback
    .wbm_adr_o(address),
5537 75 unneback
    .wbm_sel_o(be),
5538
    .wbm_bte_o(wbm_bte_o),
5539
    .wbm_cti_o(wbm_cti_o),
5540
    .wbm_we_o(wbm_we_o),
5541
    .wbm_cyc_o(wbm_cyc_o),
5542
    .wbm_stb_o(wbm_stb_o),
5543
    .wbm_dat_i(readdata),
5544
    .wbm_ack_i(wbm_ack_i),
5545
    .wbm_clk(clk),
5546
    .wbm_rst(rst));
5547
 
5548
 
5549
endmodule
5550
`endif
5551
 
5552 105 unneback
`ifdef WB_ARBITER
5553
`define MODULE wb_arbiter
5554 42 unneback
module `BASE`MODULE (
5555 40 unneback
`undef MODULE
5556 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5557 105 unneback
    wbm_dat_i, wbm_stall_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
5558 39 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5559 105 unneback
    wbs_dat_o, wbs_stall_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
5560 39 unneback
    wb_clk, wb_rst
5561
);
5562
 
5563
parameter nr_of_ports = 3;
5564
parameter adr_size = 26;
5565
parameter adr_lo   = 2;
5566
parameter dat_size = 32;
5567
parameter sel_size = dat_size/8;
5568
 
5569
localparam aw = (adr_size - adr_lo) * nr_of_ports;
5570
localparam dw = dat_size * nr_of_ports;
5571
localparam sw = sel_size * nr_of_ports;
5572
localparam cw = 3 * nr_of_ports;
5573
localparam bw = 2 * nr_of_ports;
5574
 
5575
input  [dw-1:0] wbm_dat_o;
5576
input  [aw-1:0] wbm_adr_o;
5577
input  [sw-1:0] wbm_sel_o;
5578
input  [cw-1:0] wbm_cti_o;
5579
input  [bw-1:0] wbm_bte_o;
5580
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
5581
output [dw-1:0] wbm_dat_i;
5582 105 unneback
output [nr_of_ports-1:0] wbm_stall_o, wbm_ack_i, wbm_err_i, wbm_rty_i;
5583 39 unneback
 
5584
output [dat_size-1:0] wbs_dat_i;
5585
output [adr_size-1:adr_lo] wbs_adr_i;
5586
output [sel_size-1:0] wbs_sel_i;
5587
output [2:0] wbs_cti_i;
5588
output [1:0] wbs_bte_i;
5589
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
5590
input  [dat_size-1:0] wbs_dat_o;
5591 105 unneback
input  wbs_stall_o, wbs_ack_o, wbs_err_o, wbs_rty_o;
5592 39 unneback
 
5593
input wb_clk, wb_rst;
5594
 
5595 44 unneback
reg  [nr_of_ports-1:0] select;
5596 39 unneback
wire [nr_of_ports-1:0] state;
5597
wire [nr_of_ports-1:0] eoc; // end-of-cycle
5598
wire [nr_of_ports-1:0] sel;
5599
wire idle;
5600
 
5601
genvar i;
5602
 
5603
assign idle = !(|state);
5604
 
5605
generate
5606
if (nr_of_ports == 2) begin
5607
 
5608
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
5609
 
5610
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5611
 
5612 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5613
 
5614
    always @ (idle or wbm_cyc_o)
5615
    if (idle)
5616
        casex (wbm_cyc_o)
5617
        2'b1x : select = 2'b10;
5618
        2'b01 : select = 2'b01;
5619
        default : select = {nr_of_ports{1'b0}};
5620
        endcase
5621
    else
5622
        select = {nr_of_ports{1'b0}};
5623
 
5624 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5625
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5626
 
5627
end
5628
endgenerate
5629
 
5630
generate
5631
if (nr_of_ports == 3) begin
5632
 
5633
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5634
 
5635
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5636
 
5637 44 unneback
    always @ (idle or wbm_cyc_o)
5638
    if (idle)
5639
        casex (wbm_cyc_o)
5640
        3'b1xx : select = 3'b100;
5641
        3'b01x : select = 3'b010;
5642
        3'b001 : select = 3'b001;
5643
        default : select = {nr_of_ports{1'b0}};
5644
        endcase
5645
    else
5646
        select = {nr_of_ports{1'b0}};
5647
 
5648
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5649 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5650
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5651
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5652
 
5653
end
5654
endgenerate
5655
 
5656
generate
5657 44 unneback
if (nr_of_ports == 4) begin
5658
 
5659
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5660
 
5661
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5662
 
5663
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5664
 
5665
    always @ (idle or wbm_cyc_o)
5666
    if (idle)
5667
        casex (wbm_cyc_o)
5668
        4'b1xxx : select = 4'b1000;
5669
        4'b01xx : select = 4'b0100;
5670
        4'b001x : select = 4'b0010;
5671
        4'b0001 : select = 4'b0001;
5672
        default : select = {nr_of_ports{1'b0}};
5673
        endcase
5674
    else
5675
        select = {nr_of_ports{1'b0}};
5676
 
5677
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5678
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5679
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5680
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5681
 
5682
end
5683
endgenerate
5684
 
5685
generate
5686
if (nr_of_ports == 5) begin
5687
 
5688
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5689
 
5690
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5691
 
5692
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5693
 
5694
    always @ (idle or wbm_cyc_o)
5695
    if (idle)
5696
        casex (wbm_cyc_o)
5697
        5'b1xxxx : select = 5'b10000;
5698
        5'b01xxx : select = 5'b01000;
5699
        5'b001xx : select = 5'b00100;
5700
        5'b0001x : select = 5'b00010;
5701
        5'b00001 : select = 5'b00001;
5702
        default : select = {nr_of_ports{1'b0}};
5703
        endcase
5704
    else
5705
        select = {nr_of_ports{1'b0}};
5706
 
5707
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5708
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5709
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5710
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5711
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5712
 
5713
end
5714
endgenerate
5715
 
5716
generate
5717 67 unneback
if (nr_of_ports == 6) begin
5718
 
5719
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5720
 
5721
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5722
 
5723
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5724
 
5725
    always @ (idle or wbm_cyc_o)
5726
    if (idle)
5727
        casex (wbm_cyc_o)
5728
        6'b1xxxxx : select = 6'b100000;
5729
        6'b01xxxx : select = 6'b010000;
5730
        6'b001xxx : select = 6'b001000;
5731
        6'b0001xx : select = 6'b000100;
5732
        6'b00001x : select = 6'b000010;
5733
        6'b000001 : select = 6'b000001;
5734
        default : select = {nr_of_ports{1'b0}};
5735
        endcase
5736
    else
5737
        select = {nr_of_ports{1'b0}};
5738
 
5739
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5740
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5741
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5742
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5743
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5744
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5745
 
5746
end
5747
endgenerate
5748
 
5749
generate
5750
if (nr_of_ports == 7) begin
5751
 
5752
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5753
 
5754
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5755
 
5756
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5757
 
5758
    always @ (idle or wbm_cyc_o)
5759
    if (idle)
5760
        casex (wbm_cyc_o)
5761
        7'b1xxxxxx : select = 7'b1000000;
5762
        7'b01xxxxx : select = 7'b0100000;
5763
        7'b001xxxx : select = 7'b0010000;
5764
        7'b0001xxx : select = 7'b0001000;
5765
        7'b00001xx : select = 7'b0000100;
5766
        7'b000001x : select = 7'b0000010;
5767
        7'b0000001 : select = 7'b0000001;
5768
        default : select = {nr_of_ports{1'b0}};
5769
        endcase
5770
    else
5771
        select = {nr_of_ports{1'b0}};
5772
 
5773
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5774
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5775
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5776
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5777
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5778
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5779
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5780
 
5781
end
5782
endgenerate
5783
 
5784
generate
5785
if (nr_of_ports == 8) begin
5786
 
5787
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5788
 
5789
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5790
 
5791
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5792
 
5793
    always @ (idle or wbm_cyc_o)
5794
    if (idle)
5795
        casex (wbm_cyc_o)
5796
        8'b1xxxxxxx : select = 8'b10000000;
5797
        8'b01xxxxxx : select = 8'b01000000;
5798
        8'b001xxxxx : select = 8'b00100000;
5799
        8'b0001xxxx : select = 8'b00010000;
5800
        8'b00001xxx : select = 8'b00001000;
5801
        8'b000001xx : select = 8'b00000100;
5802
        8'b0000001x : select = 8'b00000010;
5803
        8'b00000001 : select = 8'b00000001;
5804
        default : select = {nr_of_ports{1'b0}};
5805
        endcase
5806
    else
5807
        select = {nr_of_ports{1'b0}};
5808
 
5809
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
5810
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5811
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5812
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5813
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5814
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5815
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5816
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5817
 
5818
end
5819
endgenerate
5820
 
5821
generate
5822 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
5823 42 unneback
`define MODULE spr
5824
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
5825
`undef MODULE
5826 39 unneback
end
5827
endgenerate
5828
 
5829
    assign sel = select | state;
5830
 
5831 40 unneback
`define MODULE mux_andor
5832
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
5833
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
5834
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
5835
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
5836
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
5837
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
5838
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
5839
`undef MODULE
5840 39 unneback
    assign wbs_cyc_i = |sel;
5841
 
5842
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
5843
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
5844
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
5845
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
5846
 
5847
endmodule
5848 40 unneback
`endif
5849 39 unneback
 
5850 101 unneback
`ifdef WB_RAM
5851 49 unneback
// WB RAM with byte enable
5852 101 unneback
`define MODULE wb_ram
5853 59 unneback
module `BASE`MODULE (
5854
`undef MODULE
5855 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5856 101 unneback
    wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
5857 59 unneback
 
5858 101 unneback
parameter adr_width = 16;
5859
parameter mem_size = 1<<adr_width;
5860
parameter dat_width = 32;
5861
parameter max_burst_width = 4; // only used for B3
5862
parameter mode = "B3"; // valid options: B3, B4
5863 60 unneback
parameter memory_init = 1;
5864
parameter memory_file = "vl_ram.vmem";
5865 59 unneback
 
5866 101 unneback
input [dat_width-1:0] wbs_dat_i;
5867
input [adr_width-1:0] wbs_adr_i;
5868
input [2:0] wbs_cti_i;
5869
input [1:0] wbs_bte_i;
5870
input [dat_width/8-1:0] wbs_sel_i;
5871 70 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5872 101 unneback
output [dat_width-1:0] wbs_dat_o;
5873 70 unneback
output wbs_ack_o;
5874 101 unneback
output wbs_stall_o;
5875 71 unneback
input wb_clk, wb_rst;
5876 59 unneback
 
5877 101 unneback
wire [adr_width-1:0] adr;
5878
wire we;
5879 59 unneback
 
5880 101 unneback
generate
5881
if (mode=="B3") begin : B3_inst
5882 83 unneback
`define MODULE wb_adr_inc
5883 101 unneback
`BASE`MODULE # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
5884 83 unneback
    .cyc_i(wbs_cyc_i),
5885
    .stb_i(wbs_stb_i),
5886
    .cti_i(wbs_cti_i),
5887
    .bte_i(wbs_bte_i),
5888
    .adr_i(wbs_adr_i),
5889 85 unneback
    .we_i(wbs_we_i),
5890 83 unneback
    .ack_o(wbs_ack_o),
5891
    .adr_o(adr),
5892
    .clk(wb_clk),
5893
    .rst(wb_rst));
5894
`undef MODULE
5895 101 unneback
assign we = wbs_we_i & wbs_ack_o;
5896
end else if (mode=="B4") begin : B4_inst
5897
reg wbs_ack_o_reg;
5898
always @ (posedge wb_clk or posedge wb_rst)
5899
    if (wb_rst)
5900
        wbs_ack_o_reg <= 1'b0;
5901
    else
5902
        wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
5903
assign wbs_ack_o = wbs_ack_o_reg;
5904
assign wbs_stall_o = 1'b0;
5905
assign adr = wbs_adr_i;
5906
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
5907
end
5908
endgenerate
5909 60 unneback
 
5910 100 unneback
`define MODULE ram_be
5911
`BASE`MODULE # (
5912
    .data_width(dat_width),
5913
    .addr_width(adr_width),
5914
    .mem_size(mem_size),
5915
    .memory_init(memory_init),
5916
    .memory_file(memory_file))
5917
ram0(
5918
`undef MODULE
5919 101 unneback
    .d(wbs_dat_i),
5920
    .adr(adr),
5921
    .be(wbs_sel_i),
5922
    .we(we),
5923
    .q(wbs_dat_o),
5924 100 unneback
    .clk(wb_clk)
5925
);
5926 49 unneback
 
5927
endmodule
5928
`endif
5929
 
5930 103 unneback
`ifdef WB_SHADOW_RAM
5931
// A wishbone compliant RAM module that can be placed in front of other memory controllers
5932
`define MODULE wb_shadow_ram
5933
module `BASE`MODULE (
5934
`undef MODULE
5935
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5936
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
5937
    wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5938
    wbm_dat_i, wbm_ack_i, wbm_stall_i,
5939
    wb_clk, wb_rst);
5940
 
5941
parameter dat_width = 32;
5942
parameter mode = "B4";
5943
parameter max_burst_width = 4; // only used for B3
5944
 
5945
parameter shadow_mem_adr_width = 10;
5946
parameter shadow_mem_size = 1024;
5947
parameter shadow_mem_init = 2;
5948
parameter shadow_mem_file = "vl_ram.v";
5949
 
5950
parameter main_mem_adr_width = 24;
5951
 
5952
input [dat_width-1:0] wbs_dat_i;
5953
input [main_mem_adr_width-1:0] wbs_adr_i;
5954
input [2:0] wbs_cti_i;
5955
input [1:0] wbs_bte_i;
5956
input [dat_width/8-1:0] wbs_sel_i;
5957
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5958
output [dat_width-1:0] wbs_dat_o;
5959
output wbs_ack_o;
5960
output wbs_stall_o;
5961
 
5962
output [dat_width-1:0] wbm_dat_o;
5963
output [main_mem_adr_width-1:0] wbm_adr_o;
5964
output [2:0] wbm_cti_o;
5965
output [1:0] wbm_bte_o;
5966
output [dat_width/8-1:0] wbm_sel_o;
5967
output wbm_we_o, wbm_stb_o, wbm_cyc_o;
5968
input [dat_width-1:0] wbm_dat_i;
5969
input wbm_ack_i, wbm_stall_i;
5970
 
5971
input wb_clk, wb_rst;
5972
 
5973
generate
5974
if (shadow_mem_size>0) begin : shadow_ram_inst
5975
 
5976
wire cyc;
5977
wire [dat_width-1:0] dat;
5978
wire stall, ack;
5979
 
5980
assign cyc = wbs_cyc_i & (wbs_adr_i<=shadow_mem_size);
5981
`define MODULE wb_ram
5982
`BASE`MODULE # (
5983
    .dat_width(dat_width),
5984
    .adr_width(shadow_mem_adr_width),
5985
    .mem_size(shadow_mem_size),
5986
    .memory_init(shadow_mem_init),
5987 117 unneback
    .memory_file(shadow_mem_file),
5988 103 unneback
    .mode(mode))
5989
shadow_mem0 (
5990
    .wbs_dat_i(wbs_dat_i),
5991
    .wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),
5992
    .wbs_sel_i(wbs_sel_i),
5993
    .wbs_we_i (wbs_we_i),
5994
    .wbs_bte_i(wbs_bte_i),
5995
    .wbs_cti_i(wbs_cti_i),
5996
    .wbs_stb_i(wbs_stb_i),
5997
    .wbs_cyc_i(cyc),
5998
    .wbs_dat_o(dat),
5999
    .wbs_stall_o(stall),
6000
    .wbs_ack_o(ack),
6001
    .wb_clk(wb_clk),
6002
    .wb_rst(wb_rst));
6003
`undef MODULE
6004
 
6005
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o} =
6006
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i};
6007
assign wbm_cyc_o = wbs_cyc_i & (wbs_adr_i>shadow_mem_size);
6008
 
6009
assign wbs_dat_o = (dat & {dat_width{cyc}}) | (wbm_dat_i & {dat_width{wbm_cyc_o}});
6010
assign wbs_ack_o = (ack & cyc) | (wbm_ack_i & wbm_cyc_o);
6011
assign wbs_stall_o = (stall & cyc) | (wbm_stall_i & wbm_cyc_o);
6012
 
6013
end else begin : no_shadow_ram_inst
6014
 
6015
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o} =
6016
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i};
6017
assign {wbs_dat_o, wbs_ack_o, wbs_stall_o} = {wbm_dat_i, wbm_ack_i, wbm_stall_i};
6018
 
6019
end
6020
endgenerate
6021
 
6022
endmodule
6023
`endif
6024
 
6025 48 unneback
`ifdef WB_B4_ROM
6026
// WB ROM
6027
`define MODULE wb_b4_rom
6028
module `BASE`MODULE (
6029
`undef MODULE
6030
    wb_adr_i, wb_stb_i, wb_cyc_i,
6031
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
6032
 
6033
    parameter dat_width = 32;
6034
    parameter dat_default = 32'h15000000;
6035
    parameter adr_width = 32;
6036
 
6037
/*
6038
`ifndef ROM
6039
`define ROM "rom.v"
6040
`endif
6041
*/
6042
    input [adr_width-1:2]   wb_adr_i;
6043
    input                   wb_stb_i;
6044
    input                   wb_cyc_i;
6045
    output [dat_width-1:0]  wb_dat_o;
6046
    reg [dat_width-1:0]     wb_dat_o;
6047
    output                  wb_ack_o;
6048
    reg                     wb_ack_o;
6049
    output                  stall_o;
6050
    input                   wb_clk;
6051
    input                   wb_rst;
6052
 
6053
always @ (posedge wb_clk or posedge wb_rst)
6054
    if (wb_rst)
6055
        wb_dat_o <= {dat_width{1'b0}};
6056
    else
6057
         case (wb_adr_i[adr_width-1:2])
6058
`ifdef ROM
6059
`include `ROM
6060
`endif
6061
           default:
6062
             wb_dat_o <= dat_default;
6063
 
6064
         endcase // case (wb_adr_i)
6065
 
6066
 
6067
always @ (posedge wb_clk or posedge wb_rst)
6068
    if (wb_rst)
6069
        wb_ack_o <= 1'b0;
6070
    else
6071
        wb_ack_o <= wb_stb_i & wb_cyc_i;
6072
 
6073
assign stall_o = 1'b0;
6074
 
6075
endmodule
6076
`endif
6077
 
6078
 
6079 40 unneback
`ifdef WB_BOOT_ROM
6080 17 unneback
// WB ROM
6081 40 unneback
`define MODULE wb_boot_rom
6082
module `BASE`MODULE (
6083
`undef MODULE
6084 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
6085 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
6086 17 unneback
 
6087 18 unneback
    parameter adr_hi = 31;
6088
    parameter adr_lo = 28;
6089
    parameter adr_sel = 4'hf;
6090
    parameter addr_width = 5;
6091 33 unneback
/*
6092 17 unneback
`ifndef BOOT_ROM
6093
`define BOOT_ROM "boot_rom.v"
6094
`endif
6095 33 unneback
*/
6096 18 unneback
    input [adr_hi:2]    wb_adr_i;
6097
    input               wb_stb_i;
6098
    input               wb_cyc_i;
6099
    output [31:0]        wb_dat_o;
6100
    output              wb_ack_o;
6101
    output              hit_o;
6102
    input               wb_clk;
6103
    input               wb_rst;
6104
 
6105
    wire hit;
6106
    reg [31:0] wb_dat;
6107
    reg wb_ack;
6108
 
6109
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
6110 17 unneback
 
6111
always @ (posedge wb_clk or posedge wb_rst)
6112
    if (wb_rst)
6113 18 unneback
        wb_dat <= 32'h15000000;
6114 17 unneback
    else
6115 18 unneback
         case (wb_adr_i[addr_width-1:2])
6116 33 unneback
`ifdef BOOT_ROM
6117 17 unneback
`include `BOOT_ROM
6118 33 unneback
`endif
6119 17 unneback
           /*
6120
            // Zero r0 and jump to 0x00000100
6121 18 unneback
 
6122
            1 : wb_dat <= 32'hA8200000;
6123
            2 : wb_dat <= 32'hA8C00100;
6124
            3 : wb_dat <= 32'h44003000;
6125
            4 : wb_dat <= 32'h15000000;
6126 17 unneback
            */
6127
           default:
6128 18 unneback
             wb_dat <= 32'h00000000;
6129 17 unneback
 
6130
         endcase // case (wb_adr_i)
6131
 
6132
 
6133
always @ (posedge wb_clk or posedge wb_rst)
6134
    if (wb_rst)
6135 18 unneback
        wb_ack <= 1'b0;
6136 17 unneback
    else
6137 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
6138 17 unneback
 
6139 18 unneback
assign hit_o = hit;
6140
assign wb_dat_o = wb_dat & {32{wb_ack}};
6141
assign wb_ack_o = wb_ack;
6142
 
6143 17 unneback
endmodule
6144 40 unneback
`endif
6145 32 unneback
 
6146 106 unneback
`ifdef WB_DPRAM
6147
`define MODULE wb_dpram
6148 40 unneback
module `BASE`MODULE (
6149
`undef MODULE
6150 32 unneback
        // wishbone slave side a
6151 106 unneback
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, wbsa_stall_o,
6152 32 unneback
        wbsa_clk, wbsa_rst,
6153 92 unneback
        // wishbone slave side b
6154 106 unneback
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, wbsb_stall_o,
6155 32 unneback
        wbsb_clk, wbsb_rst);
6156
 
6157 92 unneback
parameter data_width_a = 32;
6158
parameter data_width_b = data_width_a;
6159
parameter addr_width_a = 8;
6160
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
6161 101 unneback
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
6162 92 unneback
parameter max_burst_width_a = 4;
6163
parameter max_burst_width_b = max_burst_width_a;
6164 101 unneback
parameter mode = "B3";
6165 109 unneback
parameter memory_init = 0;
6166
parameter memory_file = "vl_ram.v";
6167 92 unneback
input [data_width_a-1:0] wbsa_dat_i;
6168
input [addr_width_a-1:0] wbsa_adr_i;
6169
input [data_width_a/8-1:0] wbsa_sel_i;
6170
input [2:0] wbsa_cti_i;
6171
input [1:0] wbsa_bte_i;
6172 32 unneback
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
6173 92 unneback
output [data_width_a-1:0] wbsa_dat_o;
6174 109 unneback
output wbsa_ack_o;
6175 106 unneback
output wbsa_stall_o;
6176 32 unneback
input wbsa_clk, wbsa_rst;
6177
 
6178 92 unneback
input [data_width_b-1:0] wbsb_dat_i;
6179
input [addr_width_b-1:0] wbsb_adr_i;
6180
input [data_width_b/8-1:0] wbsb_sel_i;
6181
input [2:0] wbsb_cti_i;
6182
input [1:0] wbsb_bte_i;
6183 32 unneback
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
6184 92 unneback
output [data_width_b-1:0] wbsb_dat_o;
6185 109 unneback
output wbsb_ack_o;
6186 106 unneback
output wbsb_stall_o;
6187 32 unneback
input wbsb_clk, wbsb_rst;
6188
 
6189 92 unneback
wire [addr_width_a-1:0] adr_a;
6190
wire [addr_width_b-1:0] adr_b;
6191 101 unneback
wire we_a, we_b;
6192
generate
6193
if (mode=="B3") begin : b3_inst
6194 92 unneback
`define MODULE wb_adr_inc
6195
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
6196
    .cyc_i(wbsa_cyc_i),
6197
    .stb_i(wbsa_stb_i),
6198
    .cti_i(wbsa_cti_i),
6199
    .bte_i(wbsa_bte_i),
6200
    .adr_i(wbsa_adr_i),
6201
    .we_i(wbsa_we_i),
6202
    .ack_o(wbsa_ack_o),
6203
    .adr_o(adr_a),
6204
    .clk(wbsa_clk),
6205
    .rst(wbsa_rst));
6206 101 unneback
assign we_a = wbsa_we_i & wbsa_ack_o;
6207 92 unneback
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
6208
    .cyc_i(wbsb_cyc_i),
6209
    .stb_i(wbsb_stb_i),
6210
    .cti_i(wbsb_cti_i),
6211
    .bte_i(wbsb_bte_i),
6212
    .adr_i(wbsb_adr_i),
6213
    .we_i(wbsb_we_i),
6214
    .ack_o(wbsb_ack_o),
6215
    .adr_o(adr_b),
6216
    .clk(wbsb_clk),
6217
    .rst(wbsb_rst));
6218 40 unneback
`undef MODULE
6219 101 unneback
assign we_b = wbsb_we_i & wbsb_ack_o;
6220
end else if (mode=="B4") begin : b4_inst
6221 109 unneback
`define MODULE dff
6222
`BASE`MODULE dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
6223 101 unneback
assign wbsa_stall_o = 1'b0;
6224
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
6225 109 unneback
`BASE`MODULE dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
6226
`undef MODULE
6227 101 unneback
assign wbsb_stall_o = 1'b0;
6228
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
6229
end
6230
endgenerate
6231 92 unneback
 
6232
`define MODULE dpram_be_2r2w
6233 109 unneback
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
6234 110 unneback
                 .b_data_width(data_width_b),
6235 109 unneback
                 .memory_init(memory_init), .memory_file(memory_file))
6236 92 unneback
`undef MODULE
6237
ram_i (
6238 32 unneback
    .d_a(wbsa_dat_i),
6239 92 unneback
    .q_a(wbsa_dat_o),
6240
    .adr_a(adr_a),
6241
    .be_a(wbsa_sel_i),
6242 101 unneback
    .we_a(we_a),
6243 32 unneback
    .clk_a(wbsa_clk),
6244
    .d_b(wbsb_dat_i),
6245 92 unneback
    .q_b(wbsb_dat_o),
6246
    .adr_b(adr_b),
6247
    .be_b(wbsb_sel_i),
6248 101 unneback
    .we_b(we_b),
6249 32 unneback
    .clk_b(wbsb_clk) );
6250
 
6251
endmodule
6252 40 unneback
`endif
6253 94 unneback
 
6254 101 unneback
`ifdef WB_CACHE
6255
`define MODULE wb_cache
6256 97 unneback
module `BASE`MODULE (
6257 103 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
6258 98 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
6259 97 unneback
);
6260
`undef MODULE
6261
 
6262
parameter dw_s = 32;
6263
parameter aw_s = 24;
6264
parameter dw_m = dw_s;
6265 124 unneback
//localparam aw_m = dw_s * aw_s / dw_m;
6266
localparam aw_m =
6267 126 unneback
        (dw_s==dw_m) ? aw_s :
6268
        (dw_s==dw_m*2) ? aw_s+1 :
6269
        (dw_s==dw_m*4) ? aw_s+2 :
6270
        (dw_s==dw_m*8) ? aw_s+3 :
6271
        (dw_s==dw_m*16) ? aw_s+4 :
6272
        (dw_s==dw_m*32) ? aw_s+5 :
6273
        (dw_s==dw_m/2) ? aw_s-1 :
6274 127 unneback
        (dw_s==dw_m/4) ? aw_s-2 :
6275 126 unneback
        (dw_s==dw_m/8) ? aw_s-3 :
6276
        (dw_s==dw_m/16) ? aw_s-4 :
6277
        (dw_s==dw_m/32) ? aw_s-5 : 0;
6278 124 unneback
 
6279 100 unneback
parameter wbs_max_burst_width = 4;
6280 103 unneback
parameter wbs_mode = "B3";
6281 97 unneback
 
6282
parameter async = 1; // wbs_clk != wbm_clk
6283
 
6284
parameter nr_of_ways = 1;
6285
parameter aw_offset = 4; // 4 => 16 words per cache line
6286
parameter aw_slot = 10;
6287 100 unneback
 
6288
parameter valid_mem = 0;
6289
parameter debug = 0;
6290
 
6291
localparam aw_b_offset = aw_offset * dw_s / dw_m;
6292 98 unneback
localparam aw_tag = aw_s - aw_slot - aw_offset;
6293 97 unneback
parameter wbm_burst_size = 4; // valid options 4,8,16
6294 98 unneback
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
6295 97 unneback
`define SIZE2WIDTH wbm_burst_size
6296
localparam wbm_burst_width `SIZE2WIDTH_EXPR
6297
`undef SIZE2WIDTH
6298
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
6299
`define SIZE2WIDTH nr_of_wbm_burst
6300
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
6301
`undef SIZE2WIDTH
6302 100 unneback
 
6303 97 unneback
input [dw_s-1:0] wbs_dat_i;
6304
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
6305 98 unneback
input [dw_s/8-1:0] wbs_sel_i;
6306 97 unneback
input [2:0] wbs_cti_i;
6307
input [1:0] wbs_bte_i;
6308 98 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
6309 97 unneback
output [dw_s-1:0] wbs_dat_o;
6310
output wbs_ack_o;
6311 103 unneback
output wbs_stall_o;
6312 97 unneback
input wbs_clk, wbs_rst;
6313
 
6314
output [dw_m-1:0] wbm_dat_o;
6315
output [aw_m-1:0] wbm_adr_o;
6316
output [dw_m/8-1:0] wbm_sel_o;
6317
output [2:0] wbm_cti_o;
6318
output [1:0] wbm_bte_o;
6319 98 unneback
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
6320 97 unneback
input [dw_m-1:0] wbm_dat_i;
6321
input wbm_ack_i;
6322
input wbm_stall_i;
6323
input wbm_clk, wbm_rst;
6324
 
6325 100 unneback
wire valid, dirty, hit;
6326 97 unneback
wire [aw_tag-1:0] tag;
6327
wire tag_mem_we;
6328
wire [aw_tag-1:0] wbs_adr_tag;
6329
wire [aw_slot-1:0] wbs_adr_slot;
6330 98 unneback
wire [aw_offset-1:0] wbs_adr_word;
6331
wire [aw_s-1:0] wbs_adr;
6332 97 unneback
 
6333
reg [1:0] state;
6334
localparam idle = 2'h0;
6335
localparam rdwr = 2'h1;
6336
localparam push = 2'h2;
6337
localparam pull = 2'h3;
6338
wire eoc;
6339 103 unneback
wire we;
6340 97 unneback
 
6341
// cdc
6342
wire done, mem_alert, mem_done;
6343
 
6344 98 unneback
// wbm side
6345
reg [aw_m-1:0] wbm_radr;
6346
reg [aw_m-1:0] wbm_wadr;
6347 137 unneback
//wire [aw_slot-1:0] wbm_adr;
6348
wire [aw_m-1:0] wbm_adr;
6349 98 unneback
wire wbm_radr_cke, wbm_wadr_cke;
6350
 
6351 100 unneback
reg [2:0] phase;
6352
// phase = {we,stb,cyc}
6353
localparam wbm_wait     = 3'b000;
6354
localparam wbm_wr       = 3'b111;
6355
localparam wbm_wr_drain = 3'b101;
6356
localparam wbm_rd       = 3'b011;
6357
localparam wbm_rd_drain = 3'b001;
6358 98 unneback
 
6359 97 unneback
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
6360
 
6361 100 unneback
generate
6362
if (valid_mem==0) begin : no_valid_mem
6363
assign valid = 1'b1;
6364
end else begin : valid_mem_inst
6365
`define MODULE dpram_1r1w
6366 97 unneback
`BASE`MODULE
6367 100 unneback
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6368
    valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6369
                .q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6370 97 unneback
`undef MODULE
6371 100 unneback
end
6372
endgenerate
6373 97 unneback
 
6374 100 unneback
`define MODULE dpram_1r1w
6375
`BASE`MODULE
6376
    # ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6377
    tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6378
              .q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6379
assign hit = wbs_adr_tag == tag;
6380
`undef MODULE
6381
 
6382
`define MODULE dpram_1r2w
6383
`BASE`MODULE
6384
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6385
    dirty_mem (
6386
        .d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
6387
        .d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
6388
`undef MODULE
6389
 
6390 103 unneback
generate
6391
if (wbs_mode=="B3") begin : inst_b3
6392 97 unneback
`define MODULE wb_adr_inc
6393 100 unneback
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
6394
    .cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
6395
    .stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
6396 97 unneback
    .cti_i(wbs_cti_i),
6397
    .bte_i(wbs_bte_i),
6398
    .adr_i(wbs_adr_i),
6399
    .we_i (wbs_we_i),
6400
    .ack_o(wbs_ack_o),
6401
    .adr_o(wbs_adr),
6402 100 unneback
    .clk(wbs_clk),
6403
    .rst(wbs_rst));
6404 97 unneback
`undef MODULE
6405 103 unneback
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
6406
assign we = wbs_cyc_i &  wbs_we_i & wbs_ack_o;
6407
end else if (wbs_mode=="B4") begin : inst_b4
6408
end
6409 97 unneback
 
6410 103 unneback
endgenerate
6411 131 unneback
localparam cache_mem_b_aw =
6412
    (dw_s==dw_m) ? aw_slot+aw_offset :
6413 133 unneback
    (dw_s==dw_m/2) ? aw_slot+aw_offset-1 :
6414
    (dw_s==dw_m/4) ? aw_slot+aw_offset-2 :
6415
    (dw_s==dw_m/8) ? aw_slot+aw_offset-3 :
6416
    (dw_s==dw_m/16) ? aw_slot+aw_offset-4 :
6417
    (dw_s==dw_m*2) ? aw_slot+aw_offset+1 :
6418
    (dw_s==dw_m*4) ? aw_slot+aw_offset+2 :
6419
    (dw_s==dw_m*8) ? aw_slot+aw_offset+3 :
6420
    (dw_s==dw_m*16) ? aw_slot+aw_offset+4 : 0;
6421 103 unneback
 
6422 97 unneback
`define MODULE dpram_be_2r2w
6423
`BASE`MODULE
6424 100 unneback
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
6425 103 unneback
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
6426 136 unneback
                .d_b(wbm_dat_i), .adr_b(wbm_adr[cache_mem_b_aw-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbm_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
6427 97 unneback
`undef MODULE
6428
 
6429
always @ (posedge wbs_clk or posedge wbs_rst)
6430
if (wbs_rst)
6431 98 unneback
    state <= idle;
6432 97 unneback
else
6433
    case (state)
6434
    idle:
6435
        if (wbs_cyc_i)
6436
            state <= rdwr;
6437
    rdwr:
6438 100 unneback
        casex ({valid, hit, dirty, eoc})
6439
        4'b0xxx: state <= pull;
6440
        4'b11x1: state <= idle;
6441
        4'b101x: state <= push;
6442
        4'b100x: state <= pull;
6443
        endcase
6444 97 unneback
    push:
6445
        if (done)
6446
            state <= rdwr;
6447
    pull:
6448
        if (done)
6449
            state <= rdwr;
6450
    default: state <= idle;
6451
    endcase
6452
 
6453
// cdc
6454
generate
6455
if (async==1) begin : cdc0
6456
`define MODULE cdc
6457 100 unneback
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
6458 97 unneback
`undef MODULE
6459
end
6460
else begin : nocdc
6461 100 unneback
    assign mem_alert = state==rdwr & (!valid | !hit);
6462 97 unneback
    assign done = mem_done;
6463
end
6464
endgenerate
6465
 
6466 136 unneback
// FSM generating a number of bursts 4 cycles
6467 97 unneback
// actual number depends on data width ratio
6468
// nr_of_wbm_burst
6469 101 unneback
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0]       cnt_rw, cnt_ack;
6470 97 unneback
 
6471
always @ (posedge wbm_clk or posedge wbm_rst)
6472
if (wbm_rst)
6473 100 unneback
    cnt_rw <= {wbm_burst_width{1'b0}};
6474 97 unneback
else
6475 100 unneback
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
6476
        cnt_rw <= cnt_rw + 1;
6477 97 unneback
 
6478 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6479
if (wbm_rst)
6480 100 unneback
    cnt_ack <= {wbm_burst_width{1'b0}};
6481 98 unneback
else
6482 100 unneback
    if (wbm_ack_i)
6483
        cnt_ack <= cnt_ack + 1;
6484 97 unneback
 
6485 100 unneback
generate
6486 101 unneback
if (nr_of_wbm_burst==1) begin : one_burst
6487 100 unneback
 
6488 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6489
if (wbm_rst)
6490
    phase <= wbm_wait;
6491
else
6492
    case (phase)
6493
    wbm_wait:
6494
        if (mem_alert)
6495 100 unneback
            if (state==push)
6496
                phase <= wbm_wr;
6497
            else
6498
                phase <= wbm_rd;
6499 98 unneback
    wbm_wr:
6500 100 unneback
        if (&cnt_rw)
6501
            phase <= wbm_wr_drain;
6502
    wbm_wr_drain:
6503
        if (&cnt_ack)
6504 98 unneback
            phase <= wbm_rd;
6505
    wbm_rd:
6506 100 unneback
        if (&cnt_rw)
6507
            phase <= wbm_rd_drain;
6508
    wbm_rd_drain:
6509
        if (&cnt_ack)
6510
            phase <= wbm_wait;
6511 98 unneback
    default: phase <= wbm_wait;
6512
    endcase
6513
 
6514 100 unneback
end else begin : multiple_burst
6515
 
6516 101 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6517
if (wbm_rst)
6518
    phase <= wbm_wait;
6519
else
6520
    case (phase)
6521
    wbm_wait:
6522
        if (mem_alert)
6523
            if (state==push)
6524
                phase <= wbm_wr;
6525
            else
6526
                phase <= wbm_rd;
6527
    wbm_wr:
6528
        if (&cnt_rw[wbm_burst_width-1:0])
6529
            phase <= wbm_wr_drain;
6530
    wbm_wr_drain:
6531
        if (&cnt_ack)
6532
            phase <= wbm_rd;
6533
        else if (&cnt_ack[wbm_burst_width-1:0])
6534
            phase <= wbm_wr;
6535
    wbm_rd:
6536
        if (&cnt_rw[wbm_burst_width-1:0])
6537
            phase <= wbm_rd_drain;
6538
    wbm_rd_drain:
6539
        if (&cnt_ack)
6540
            phase <= wbm_wait;
6541
        else if (&cnt_ack[wbm_burst_width-1:0])
6542
            phase <= wbm_rd;
6543
    default: phase <= wbm_wait;
6544
    endcase
6545 100 unneback
 
6546 101 unneback
 
6547 100 unneback
end
6548
endgenerate
6549
 
6550 101 unneback
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
6551 100 unneback
 
6552
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
6553 137 unneback
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_ack};
6554 100 unneback
assign wbm_sel_o = {dw_m/8{1'b1}};
6555
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
6556 98 unneback
assign wbm_bte_o = bte;
6557 100 unneback
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
6558 98 unneback
 
6559 97 unneback
endmodule
6560
`endif
6561 103 unneback
 
6562
`ifdef WB_AVALON_BRIDGE
6563
// Wishbone to avalon bridge supporting one type of burst transfer only
6564
// intended use is together with cache above
6565
// WB B4 -> pipelined avalon
6566
`define MODULE wb_avalon_bridge
6567
module `BASE`MODULE (
6568
`undef MODULE
6569
        // wishbone slave side
6570
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
6571
        // avalon master side
6572
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
6573 136 unneback
        init_done,
6574 103 unneback
        // common
6575
        clk, rst);
6576
 
6577
parameter adr_width = 30;
6578
parameter dat_width = 32;
6579
parameter burst_size = 4;
6580
 
6581
input [dat_width-1:0] wbs_dat_i;
6582
input [adr_width-1:0] wbs_adr_i;
6583
input [dat_width/8-1:0]  wbs_sel_i;
6584
input [1:0]  wbs_bte_i;
6585
input [2:0]  wbs_cti_i;
6586
input wbs_we_i;
6587
input wbs_cyc_i;
6588
input wbs_stb_i;
6589 130 unneback
output [dat_width-1:0] wbs_dat_o;
6590 103 unneback
output wbs_ack_o;
6591
output wbs_stall_o;
6592
 
6593
input [dat_width-1:0] readdata;
6594
input readdatavalid;
6595
output [dat_width-1:0] writedata;
6596
output [adr_width-1:0] address;
6597
output [dat_width/8-1:0]  be;
6598
output write;
6599
output read;
6600
output beginbursttransfer;
6601
output [3:0] burstcount;
6602
input waitrequest;
6603 136 unneback
input init_done;
6604 103 unneback
input clk, rst;
6605
 
6606 136 unneback
// cnt1 - initiated read or writes
6607
// cnt2 - # of read or writes in pipeline
6608
reg [3:0] cnt1;
6609
reg [3:0] cnt2;
6610 103 unneback
 
6611 136 unneback
reg next_state, state;
6612
localparam s0 = 1'b0;
6613
localparam s1 = 1'b1;
6614
 
6615
wire eoc;
6616
 
6617
always @ *
6618
begin
6619
    case (state)
6620
    s0: if (init_done & wbs_cyc_i) next_state <= s1;
6621
    s1:
6622
    default: next_state <= state;
6623
    end
6624
end
6625
 
6626 103 unneback
always @ (posedge clk or posedge rst)
6627
if (rst)
6628 136 unneback
    state <= s0;
6629 103 unneback
else
6630 136 unneback
    state <= next_state;
6631 103 unneback
 
6632 136 unneback
assign eoc = state==s1 & !(read | write) & (& !waitrequest & cnt2=;
6633
always @ (posedge clk or posedge rst)
6634
if (rst)
6635
    cnt1 <= 4'h0;
6636
else
6637
    if (read & !waitrequest & init_done)
6638
        cnt1 <= burst_size - 1;
6639
    else if (write & !waitrequest & init_done)
6640
        cnt1 <= cnt1 + 4'h1;
6641
    else if (next_state==idle)
6642
        cnt1 <= 4'h0;
6643
 
6644
always @ (posedge clk or posedge rst)
6645
if (rst)
6646
    cnt2 <= 4'h0;
6647
else
6648
    if (read & !waitrequest & init_done)
6649
        cnt2 <= burst_size - 1;
6650
    else if (write & !waitrequest & init_done & )
6651
        cnt2 <= cnt1 + 4'h1;
6652
    else if (next_state==idle)
6653
        cnt2 <= 4'h0;
6654
 
6655 103 unneback
reg wr_ack;
6656
always @ (posedge clk or posedge rst)
6657
if (rst)
6658
    wr_ack <= 1'b0;
6659
else
6660
    wr_ack <=  (wbs_we_i & wbs_cyc_i & wbs_stb_i & !wbs_stall_o);
6661
 
6662
// to avalon
6663
assign writedata = wbs_dat_i;
6664
assign address = wbs_adr_i;
6665
assign be = wbs_sel_i;
6666 136 unneback
assign write = cnt!=4'h0 & wbs_cyc_i &  wbs_we_i;
6667
assign read  = cnt!=4'h0 & wbs_cyc_i & !wbs_we_i;
6668
assign beginbursttransfer = state==s0 & next_state==s1;
6669 103 unneback
assign burstcount = burst_size;
6670
 
6671
// to wishbone
6672
assign wbs_dat_o = readdata;
6673
assign wbs_ack_o = wr_ack | readdatavalid;
6674
assign wbs_stall_o = waitrequest;
6675
 
6676
endmodule
6677
`endif
6678
 
6679
`ifdef WB_AVALON_MEM_CACHE
6680
`define MODULE wb_avalon_mem_cache
6681
module `BASE`MODULE (
6682
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
6683
    readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst
6684
);
6685
`undef MODULE
6686
 
6687
// wishbone
6688
parameter wb_dat_width = 32;
6689
parameter wb_adr_width = 22;
6690
parameter wb_max_burst_width = 4;
6691
parameter wb_mode = "B4";
6692
// avalon
6693
parameter avalon_dat_width = 32;
6694 121 unneback
//localparam avalon_adr_width = wb_dat_width * wb_adr_width / avalon_dat_width;
6695 122 unneback
localparam avalon_adr_width =
6696
        (wb_dat_width==avalon_dat_width) ? wb_adr_width :
6697
        (wb_dat_width==avalon_dat_width*2) ? wb_adr_width+1 :
6698
        (wb_dat_width==avalon_dat_width*4) ? wb_adr_width+2 :
6699
        (wb_dat_width==avalon_dat_width*8) ? wb_adr_width+3 :
6700
        (wb_dat_width==avalon_dat_width*16) ? wb_adr_width+4 :
6701
        (wb_dat_width==avalon_dat_width*32) ? wb_adr_width+5 :
6702
        (wb_dat_width==avalon_dat_width/2) ? wb_adr_width-1 :
6703
        (wb_dat_width==avalon_dat_width/4) ? wb_adr_width-2 :
6704
        (wb_dat_width==avalon_dat_width/8) ? wb_adr_width-3 :
6705
        (wb_dat_width==avalon_dat_width/16) ? wb_adr_width-4 :
6706 123 unneback
        (wb_dat_width==avalon_dat_width/32) ? wb_adr_width-5 : 0;
6707 103 unneback
parameter avalon_burst_size = 4;
6708
// cache
6709
parameter async = 1;
6710
parameter nr_of_ways = 1;
6711
parameter aw_offset = 4;
6712
parameter aw_slot = 10;
6713
parameter valid_mem = 1;
6714
// shadow RAM
6715
parameter shadow_ram = 0;
6716
parameter shadow_ram_adr_width = 10;
6717
parameter shadow_ram_size = 1024;
6718
parameter shadow_ram_init = 2; // 0: no init, 1: from file, 2: with zero
6719
parameter shadow_ram_file = "vl_ram.v";
6720
 
6721
input [wb_dat_width-1:0] wbs_dat_i;
6722
input [wb_adr_width-1:0] wbs_adr_i; // dont include a1,a0
6723
input [wb_dat_width/8-1:0] wbs_sel_i;
6724
input [2:0] wbs_cti_i;
6725
input [1:0] wbs_bte_i;
6726
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
6727
output [wb_dat_width-1:0] wbs_dat_o;
6728
output wbs_ack_o;
6729
output wbs_stall_o;
6730
input wbs_clk, wbs_rst;
6731
 
6732
input [avalon_dat_width-1:0] readdata;
6733
input readdatavalid;
6734
output [avalon_dat_width-1:0] writedata;
6735
output [avalon_adr_width-1:0] address;
6736
output [avalon_dat_width/8-1:0]  be;
6737
output write;
6738
output read;
6739
output beginbursttransfer;
6740
output [3:0] burstcount;
6741
input waitrequest;
6742
input clk, rst;
6743
 
6744
`define DAT_WIDTH wb_dat_width
6745
`define ADR_WIDTH wb_adr_width
6746
`define WB wb1
6747
`include "wb_wires.v"
6748 129 unneback
`undef DAT_WIDTH
6749
`undef ADR_WIDTH
6750
`define DAT_WIDTH avalon_dat_width
6751
`define ADR_WIDTH avalon_adr_width
6752 103 unneback
`define WB wb2
6753
`include "wb_wires.v"
6754
`undef DAT_WIDTH
6755
`undef ADR_WIDTH
6756
 
6757
`define MODULE wb_shadow_ram
6758
`BASE`MODULE # ( .dat_width(wb_dat_width), .mode(wb_mode), .max_burst_width(wb_max_burst_width),
6759 120 unneback
                 .shadow_mem_adr_width(shadow_ram_adr_width), .shadow_mem_size(shadow_ram_size), .shadow_mem_init(shadow_ram_init), .shadow_mem_file(shadow_ram_file),
6760 103 unneback
                 .main_mem_adr_width(wb_adr_width))
6761
shadow_ram0 (
6762
    .wbs_dat_i(wbs_dat_i), .wbs_adr_i(wbs_adr_i), .wbs_cti_i(wbs_cti_i), .wbs_bte_i(wbs_bte_i), .wbs_sel_i(wbs_sel_i), .wbs_we_i(wbs_we_i), .wbs_stb_i(wbs_stb_i), .wbs_cyc_i(wbs_cyc_i),
6763
    .wbs_dat_o(wbs_dat_o), .wbs_ack_o(wbs_ack_o), .wbs_stall_o(wbs_stall_o),
6764
    .wbm_dat_o(wb1_dat_o), .wbm_adr_o(wb1_adr_o), .wbm_cti_o(wb1_cti_o), .wbm_bte_o(wb1_bte_o), .wbm_sel_o(wb1_sel_o), .wbm_we_o(wb1_we_o), .wbm_stb_o(wb1_stb_o), .wbm_cyc_o(wb1_cyc_o),
6765
    .wbm_dat_i(wb1_dat_i), .wbm_ack_i(wb1_ack_i), .wbm_stall_i(wb1_stall_i),
6766
    .wb_clk(wbs_clk), .wb_rst(wbs_rst));
6767
`undef MODULE
6768
 
6769
`define MODULE wb_cache
6770
`BASE`MODULE
6771
# ( .dw_s(wb_dat_width), .aw_s(wb_adr_width), .dw_m(avalon_dat_width), .wbs_mode(wb_mode), .wbs_max_burst_width(wb_max_burst_width), .async(async), .nr_of_ways(nr_of_ways), .aw_offset(aw_offset), .aw_slot(aw_slot), .valid_mem(valid_mem))
6772
cache0 (
6773
    .wbs_dat_i(wb1_dat_o), .wbs_adr_i(wb1_adr_o), .wbs_sel_i(wb1_sel_o), .wbs_cti_i(wb1_cti_o), .wbs_bte_i(wb1_bte_o), .wbs_we_i(wb1_we_o), .wbs_stb_i(wb1_stb_o), .wbs_cyc_i(wb1_cyc_o),
6774
    .wbs_dat_o(wb1_dat_i), .wbs_ack_o(wb1_ack_i), .wbs_stall_o(wb1_stall_i), .wbs_clk(wbs_clk), .wbs_rst(wbs_rst),
6775
    .wbm_dat_o(wb2_dat_o), .wbm_adr_o(wb2_adr_o), .wbm_sel_o(wb2_sel_o), .wbm_cti_o(wb2_cti_o), .wbm_bte_o(wb2_bte_o), .wbm_we_o(wb2_we_o), .wbm_stb_o(wb2_stb_o), .wbm_cyc_o(wb2_cyc_o),
6776
    .wbm_dat_i(wb2_dat_i), .wbm_ack_i(wb2_ack_i), .wbm_stall_i(wb2_stall_i), .wbm_clk(clk), .wbm_rst(rst));
6777
`undef MODULE
6778
 
6779
`define MODULE wb_avalon_bridge
6780
`BASE`MODULE # ( .adr_width(avalon_adr_width), .dat_width(avalon_dat_width), .burst_size(avalon_burst_size))
6781
bridge0 (
6782
        // wishbone slave side
6783
        .wbs_dat_i(wb2_dat_o), .wbs_adr_i(wb2_adr_o), .wbs_sel_i(wb2_sel_o), .wbs_bte_i(wb2_bte_o), .wbs_cti_i(wb2_cti_o), .wbs_we_i(wb2_we_o), .wbs_cyc_i(wb2_cyc_o), .wbs_stb_i(wb2_stb_o),
6784
        .wbs_dat_o(wb2_dat_i), .wbs_ack_o(wb2_ack_i), .wbs_stall_o(wb2_stall_i),
6785
        // avalon master side
6786
        .readdata(readdata), .readdatavalid(readdatavalid), .address(address), .read(read), .be(be), .write(write), .burstcount(burstcount), .writedata(writedata), .waitrequest(waitrequest), .beginbursttransfer(beginbursttransfer),
6787
        // common
6788
        .clk(clk), .rst(rst));
6789
`undef MODULE
6790
 
6791
endmodule
6792
`endif
6793 105 unneback
 
6794
`ifdef WB_SDR_SDRAM
6795
`define MODULE wb_sdr_sdram
6796
module `BASE`MODULE (
6797
`undef MODULE
6798
    // wisbone i/f
6799 136 unneback
    dat_i, adr_i, sel_i, we_i, cyc_i, stb_i, dat_o, ack_o, stall_o,
6800 105 unneback
    // SDR SDRAM
6801
    ba, a, cmd, cke, cs_n, dqm, dq_i, dq_o, dq_oe,
6802
    // system
6803
    clk, rst);
6804
 
6805
    // external data bus size
6806
    parameter dat_size = 16;
6807
    // memory geometry parameters
6808 136 unneback
    parameter ba_size  = 2;
6809
    parameter row_size = 13;
6810
    parameter col_size = 9;
6811 105 unneback
    parameter cl = 2;
6812
    // memory timing parameters
6813
    parameter tRFC = 9;
6814
    parameter tRP  = 2;
6815
    parameter tRCD = 2;
6816
    parameter tMRD = 2;
6817
 
6818
    // LMR
6819
    // [12:10] reserved
6820
    // [9]     WB, write burst; 0 - programmed burst length, 1 - single location
6821
    // [8:7]   OP Mode, 2'b00
6822
    // [6:4]   CAS Latency; 3'b010 - 2, 3'b011 - 3
6823
    // [3]     BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
6824
    // [2:0]   Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
6825
    localparam init_wb = 1'b1;
6826
    localparam init_cl = (cl==2) ? 3'b010 : 3'b011;
6827
    localparam init_bt = 1'b0;
6828
    localparam init_bl = 3'b000;
6829
 
6830 136 unneback
    input [dat_size-1:0] dat_i;
6831 105 unneback
    input [ba_size+col_size+row_size-1:0] adr_i;
6832
    input [dat_size/8-1:0] sel_i;
6833
    input we_i, cyc_i, stb_i;
6834
    output [dat_size-1:0] dat_o;
6835
    output ack_o;
6836
    output reg stall_o;
6837
 
6838
    output [ba_size-1:0]    ba;
6839
    output reg [12:0]   a;
6840
    output reg [2:0]    cmd; // {ras,cas,we}
6841
    output cke, cs_n;
6842
    output reg [dat_size/8-1:0]    dqm;
6843
    output [dat_size-1:0]       dq_o;
6844
    output reg          dq_oe;
6845
    input  [dat_size-1:0]       dq_i;
6846
 
6847
    input clk, rst;
6848
 
6849
    wire [ba_size-1:0]   bank;
6850
    wire [row_size-1:0] row;
6851
    wire [col_size-1:0] col;
6852
    wire [0:31]  shreg;
6853
    wire                ref_cnt_zero;
6854
    reg                 refresh_req;
6855
 
6856
    wire ack_rd, rd_ack_emptyflag;
6857
    wire ack_wr;
6858
 
6859
    // to keep track of open rows per bank
6860
    reg [row_size-1:0]   open_row[0:3];
6861
    reg [0:3]            open_ba;
6862
    reg                 current_bank_closed, current_row_open;
6863
 
6864
    parameter rfr_length = 10;
6865
    parameter rfr_wrap_value = 1010;
6866
 
6867
    parameter [2:0] cmd_nop = 3'b111,
6868
                    cmd_act = 3'b011,
6869
                    cmd_rd  = 3'b101,
6870
                    cmd_wr  = 3'b100,
6871
                    cmd_pch = 3'b010,
6872
                    cmd_rfr = 3'b001,
6873
                    cmd_lmr = 3'b000;
6874
 
6875
// ctrl FSM
6876
`define FSM_INIT 3'b000
6877
`define FSM_IDLE 3'b001
6878
`define FSM_RFR  3'b010
6879
`define FSM_ADR  3'b011
6880
`define FSM_PCH  3'b100
6881
`define FSM_ACT  3'b101
6882
`define FSM_RW   3'b111
6883
 
6884
    assign cke = 1'b1;
6885
    assign cs_n = 1'b0;
6886
 
6887
    reg [2:0] state, next;
6888
 
6889
    function [12:0] a10_fix;
6890
        input [col_size-1:0] a;
6891
        integer i;
6892
    begin
6893
        for (i=0;i<13;i=i+1) begin
6894
            if (i<10)
6895
              if (i<col_size)
6896
                a10_fix[i] = a[i];
6897
              else
6898
                a10_fix[i] = 1'b0;
6899
            else if (i==10)
6900
              a10_fix[i] = 1'b0;
6901
            else
6902
              if (i<col_size)
6903
                a10_fix[i] = a[i-1];
6904
              else
6905
                a10_fix[i] = 1'b0;
6906
        end
6907
    end
6908
    endfunction
6909
 
6910
    assign {bank,row,col} = adr_i;
6911
 
6912
    always @ (posedge clk or posedge rst)
6913
    if (rst)
6914
       state <= `FSM_INIT;
6915
    else
6916
       state <= next;
6917
 
6918
    always @*
6919
    begin
6920
        next = state;
6921
        case (state)
6922
        `FSM_INIT:
6923
            if (shreg[3+tRP+tRFC+tRFC+tMRD]) next = `FSM_IDLE;
6924
        `FSM_IDLE:
6925
            if (refresh_req) next = `FSM_RFR;
6926
            else if (cyc_i & stb_i & rd_ack_emptyflag) next = `FSM_ADR;
6927
        `FSM_RFR:
6928
            if (shreg[tRP+tRFC-2]) next = `FSM_IDLE; // take away two cycles because no cmd will be issued in idle and adr
6929
        `FSM_ADR:
6930
            if (current_bank_closed) next = `FSM_ACT;
6931
            else if (current_row_open) next = `FSM_RW;
6932
            else next = `FSM_PCH;
6933
        `FSM_PCH:
6934
            if (shreg[tRP]) next = `FSM_ACT;
6935
        `FSM_ACT:
6936
            if (shreg[tRCD]) next = `FSM_RW;
6937
        `FSM_RW:
6938
            if (!stb_i) next = `FSM_IDLE;
6939
        endcase
6940
    end
6941
 
6942
    // counter
6943 136 unneback
`define MODULE cnt_shreg_clear
6944
    `BASE`MODULE # ( .length(32))
6945 105 unneback
`undef MODULE
6946
        cnt0 (
6947
            .clear(state!=next),
6948
            .q(shreg),
6949
            .rst(rst),
6950
            .clk(clk));
6951
 
6952
    // ba, a, cmd
6953
    // outputs dependent on state vector
6954
    always @ (*)
6955
        begin
6956
            {a,cmd} = {13'd0,cmd_nop};
6957
            dqm = 2'b11;
6958
            dq_oe = 1'b0;
6959
            stall_o = 1'b1;
6960
            case (state)
6961
            `FSM_INIT:
6962
                if (shreg[3]) begin
6963
                    {a,cmd} = {13'b0010000000000, cmd_pch};
6964
                end else if (shreg[3+tRP] | shreg[3+tRP+tRFC])
6965
                    {a,cmd} = {13'd0, cmd_rfr};
6966
                else if (shreg[3+tRP+tRFC+tRFC])
6967
                    {a,cmd} = {3'b000,init_wb,2'b00,init_cl,init_bt,init_bl,cmd_lmr};
6968
            `FSM_RFR:
6969
                if (shreg[0])
6970
                    {a,cmd} = {13'b0010000000000, cmd_pch};
6971
                else if (shreg[tRP])
6972
                    {a,cmd} = {13'd0, cmd_rfr};
6973
            `FSM_PCH:
6974
                if (shreg[0])
6975
                    {a,cmd} = {13'd0,cmd_pch};
6976
            `FSM_ACT:
6977
                if (shreg[0])
6978
                    {a[row_size-1:0],cmd} = {row,cmd_act};
6979
            `FSM_RW:
6980
                begin
6981
                    if (we_i)
6982
                        cmd = cmd_wr;
6983
                    else
6984
                        cmd = cmd_rd;
6985
                    if (we_i)
6986
                        dqm = ~sel_i;
6987
                    else
6988
                        dqm = 2'b00;
6989
                    if (we_i)
6990
                        dq_oe = 1'b1;
6991
                    a = a10_fix(col);
6992 136 unneback
                    stall_o = 1'b0;
6993 105 unneback
                end
6994
            endcase
6995
        end
6996
 
6997
    assign ba = bank;
6998
 
6999
    // precharge individual bank A10=0
7000
    // precharge all bank A10=1
7001
    genvar i;
7002
    generate
7003 136 unneback
    for (i=0;i<2<<ba_size-1;i=i+1) begin : open_ba_logic
7004 105 unneback
 
7005
        always @ (posedge clk or posedge rst)
7006
        if (rst)
7007
            {open_ba[i],open_row[i]} <= {1'b0,{row_size{1'b0}}};
7008
        else
7009
            if (cmd==cmd_pch & (a[10] | bank==i))
7010
                open_ba[i] <= 1'b0;
7011
            else if (cmd==cmd_act & bank==i)
7012
                {open_ba[i],open_row[i]} <= {1'b1,row};
7013
 
7014
    end
7015
    endgenerate
7016
 
7017
    // bank and row open ?
7018
    always @ (posedge clk or posedge rst)
7019
    if (rst)
7020
       {current_bank_closed, current_row_open} <= {1'b1, 1'b0};
7021
    else
7022
       {current_bank_closed, current_row_open} <= {!(open_ba[bank]), open_row[bank]==row};
7023
 
7024
    // refresh counter
7025
`define MODULE cnt_lfsr_zq
7026 136 unneback
    `BASE`MODULE # ( .length(rfr_length), .wrap_value (rfr_wrap_value)) ref_counter0( .zq(ref_cnt_zero), .rst(rst), .clk(clk));
7027 105 unneback
`undef MODULE
7028
 
7029
    always @ (posedge clk or posedge rst)
7030
    if (rst)
7031
        refresh_req <= 1'b0;
7032
    else
7033
        if (ref_cnt_zero)
7034
            refresh_req <= 1'b1;
7035
        else if (state==`FSM_RFR)
7036
            refresh_req <= 1'b0;
7037
 
7038
    assign dat_o = dq_i;
7039
 
7040 136 unneback
    assign ack_wr = (state==`FSM_RW & we_i);
7041 105 unneback
`define MODULE delay_emptyflag
7042 136 unneback
    `BASE`MODULE # ( .depth(cl+2)) delay0 ( .d(state==`FSM_RW & stb_i & !we_i), .q(ack_rd), .emptyflag(rd_ack_emptyflag), .clk(clk), .rst(rst));
7043 105 unneback
`undef MODULE
7044
    assign ack_o = ack_rd | ack_wr;
7045
 
7046
    assign dq_o = dat_i;
7047
 
7048
endmodule
7049
`endif
7050 136 unneback
 
7051
`ifdef WB_SDR_SDRAM_CTRL
7052
`define MODULE wb_sdr_sdram_ctrl
7053
module `BASE`MODULE (
7054
    // WB i/f
7055
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
7056
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
7057
    // SDR SDRAM
7058
    mem_ba, mem_a, mem_cmd, mem_cke, mem_cs_n, mem_dqm, mem_dq_i, mem_dq_o, mem_dq_oe,
7059
    // system
7060
    wb_clk, wb_rst, mem_clk, mem_rst);
7061
`undef MODULE
7062
 
7063
    // WB slave
7064
    parameter wbs_dat_width = 32;
7065
    parameter wbs_adr_width = 24;
7066
    parameter wbs_mode = "B3";
7067
    parameter wbs_max_burst_width = 4;
7068
 
7069
    // Shadow RAM
7070
    parameter shadow_mem_adr_width = 10;
7071
    parameter shadow_mem_size = 1024;
7072
    parameter shadow_mem_init = 2;
7073
    parameter shadow_mem_file = "vl_ram.v";
7074
 
7075
    // Cache
7076
    parameter cache_async = 1; // wbs_clk != wbm_clk
7077
    parameter cache_nr_of_ways = 1;
7078
    parameter cache_aw_offset = 4; // 4 => 16 words per cache line
7079
    parameter cache_aw_slot = 10;
7080
    parameter cache_valid_mem = 0;
7081
    parameter cache_debug = 0;
7082
 
7083
    // SDRAM parameters
7084
    parameter mem_dat_size = 16;
7085
    parameter mem_ba_size  = 2;
7086
    parameter mem_row_size = 13;
7087
    parameter mem_col_size = 9;
7088
    parameter mem_cl = 2;
7089
    parameter mem_tRFC = 9;
7090
    parameter mem_tRP  = 2;
7091
    parameter mem_tRCD = 2;
7092
    parameter mem_tMRD = 2;
7093
    parameter mem_rfr_length = 10;
7094
    parameter mem_rfr_wrap_value = 1010;
7095
 
7096
    input [wbs_dat_width-1:0] wbs_dat_i;
7097
    input [wbs_adr_width-1:0] wbs_adr_i;
7098
    input [2:0] wbs_cti_i;
7099
    input [1:0] wbs_bte_i;
7100
    input [wbs_dat_width/8-1:0] wbs_sel_i;
7101
    input wbs_we_i, wbs_stb_i, wbs_cyc_i;
7102
    output [wbs_dat_width-1:0] wbs_dat_o;
7103
    output wbs_ack_o;
7104
    output wbs_stall_o;
7105
 
7106
    output [mem_ba_size-1:0]    mem_ba;
7107
    output reg [12:0]           mem_a;
7108
    output reg [2:0]            mem_cmd; // {ras,cas,we}
7109
    output                      mem_cke, mem_cs_n;
7110
    output reg [mem_dat_size/8-1:0] mem_dqm;
7111
    output [mem_dat_size-1:0]       mem_dq_o;
7112
    output reg                  mem_dq_oe;
7113
    input  [mem_dat_size-1:0]       mem_dq_i;
7114
 
7115
    input wb_clk, wb_rst, mem_clk, mem_rst;
7116
 
7117
    // wbm1
7118
    wire [wbs_dat_width-1:0] wbm1_dat_o;
7119
    wire [wbs_adr_width-1:0] wbm1_adr_o;
7120
    wire [2:0] wbm1_cti_o;
7121
    wire [1:0] wbm1_bte_o;
7122
    wire [wbs_dat_width/8-1:0] wbm1_sel_o;
7123
    wire wbm1_we_o, wbm1_stb_o, wbm1_cyc_o;
7124
    wire [wbs_dat_width-1:0] wbm1_dat_i;
7125
    wire wbm1_ack_i, wbm1_stall_i;
7126
    // wbm2
7127
    wire [mem_dat_size-1:0] wbm2_dat_o;
7128
    wire [mem_ba_size+mem_row_size+mem_col_size-1:0] wbm2_adr_o;
7129
    wire [2:0] wbm2_cti_o;
7130
    wire [1:0] wbm2_bte_o;
7131
    wire [mem_dat_size/8-1:0] wbm2_sel_o;
7132
    wire wbm2_we_o, wbm2_stb_o, wbm2_cyc_o;
7133
    wire [mem_dat_size-1:0] wbm2_dat_i;
7134
    wire wbm2_ack_i, wbm2_stall_i;
7135
 
7136
`define MODULE wb_shadow_ram
7137
`BASE`MODULE # (
7138
    .shadow_mem_adr_width(shadow_mem_adr_width), .shadow_mem_size(shadow_mem_size), .shadow_mem_init(shadow_mem_init), .shadow_mem_file(shadow_mem_file), .main_mem_adr_width(wbs_adr_width), .dat_width(wbs_dat_width), .mode(wbs_mode), .max_burst_width(wbs_max_burst_width) )
7139
shadow_ram0 (
7140
    .wbs_dat_i(wbs_dat_i),
7141
    .wbs_adr_i(wbs_adr_i),
7142
    .wbs_cti_i(wbs_cti_i),
7143
    .wbs_bte_i(wbs_bte_i),
7144
    .wbs_sel_i(wbs_sel_i),
7145
    .wbs_we_i (wbs_we_i),
7146
    .wbs_stb_i(wbs_stb_i),
7147
    .wbs_cyc_i(wbs_cyc_i),
7148
    .wbs_dat_o(wbs_dat_o),
7149
    .wbs_ack_o(wbs_ack_o),
7150
    .wbs_stall_o(wbs_stall_o),
7151
    .wbm_dat_o(wbm1_dat_o),
7152
    .wbm_adr_o(wbm1_adr_o),
7153
    .wbm_cti_o(wbm1_cti_o),
7154
    .wbm_bte_o(wbm1_bte_o),
7155
    .wbm_sel_o(wbm1_sel_o),
7156
    .wbm_we_o(wbm1_we_o),
7157
    .wbm_stb_o(wbm1_stb_o),
7158
    .wbm_cyc_o(wbm1_cyc_o),
7159
    .wbm_dat_i(wbm1_dat_i),
7160
    .wbm_ack_i(wbm1_ack_i),
7161
    .wbm_stall_i(wbm1_stall_i),
7162
    .wb_clk(wb_clk),
7163
    .wb_rst(wb_rst) );
7164
`undef MODULE
7165
 
7166
`define MODULE wb_cache
7167
`BASE`MODULE # (
7168
    .dw_s(wbs_dat_width), .aw_s(wbs_adr_width), .dw_m(mem_dat_size), .wbs_max_burst_width(cache_aw_offset), .wbs_mode(wbs_mode), .async(cache_async), .nr_of_ways(cache_nr_of_ways), .aw_offset(cache_aw_offset), .aw_slot(cache_aw_slot), .valid_mem(cache_valid_mem) )
7169
cache0 (
7170
    .wbs_dat_i(wbm1_dat_o),
7171
    .wbs_adr_i(wbm1_adr_o),
7172
    .wbs_sel_i(wbm1_sel_o),
7173
    .wbs_cti_i(wbm1_cti_o),
7174
    .wbs_bte_i(wbm1_bte_o),
7175
    .wbs_we_i (wbm1_we_o),
7176
    .wbs_stb_i(wbm1_stb_o),
7177
    .wbs_cyc_i(wbm1_cyc_o),
7178
    .wbs_dat_o(wbm1_dat_i),
7179
    .wbs_ack_o(wbm1_ack_i),
7180
    .wbs_stall_o(wbm1_stall_i),
7181
    .wbs_clk(wb_clk),
7182
    .wbs_rst(wb_rst),
7183
    .wbm_dat_o(wbm2_dat_o),
7184
    .wbm_adr_o(wbm2_adr_o),
7185
    .wbm_sel_o(wbm2_sel_o),
7186
    .wbm_cti_o(wbm2_cti_o),
7187
    .wbm_bte_o(wbm2_bte_o),
7188
    .wbm_we_o (wbm2_we_o),
7189
    .wbm_stb_o(wbm2_stb_o),
7190
    .wbm_cyc_o(wbm2_cyc_o),
7191
    .wbm_dat_i(wbm2_dat_i),
7192
    .wbm_ack_i(wbm2_ack_i),
7193
    .wbm_stall_i(wbm2_stall_i),
7194
    .wbm_clk(mem_clk),
7195
    .wbm_rst(mem_rst) );
7196
`undef MODULE
7197
 
7198
`define MODULE wb_sdr_sdram
7199
`BASE`MODULE # (
7200
    .dat_size(mem_dat_size), .ba_size(mem_ba_size), .row_size(mem_row_size), .col_size(mem_col_size), .cl(mem_cl), .tRFC(mem_tRFC), .tRP(mem_tRP), .tRCD(mem_tRCD), .tMRD(mem_tMRD), .rfr_length(mem_rfr_length), .rfr_wrap_value(mem_rfr_wrap_value) )
7201
ctrl0(
7202
    // wisbone i/f
7203
    .dat_i(wbm2_dat_o),
7204
    .adr_i(wbm2_adr_o),
7205
    .sel_i(wbm2_sel_o),
7206
    .we_i (wbm2_we_o),
7207
    .cyc_i(wbm2_cyc_o),
7208
    .stb_i(wbm2_stb_o),
7209
    .dat_o(wbm2_dat_i),
7210
    .ack_o(wbm2_ack_i),
7211
    .stall_o(wbm2_stall_i),
7212
    // SDR SDRAM
7213
    .ba(mem_ba),
7214
    .a(mem_a),
7215
    .cmd(mem_cmd),
7216
    .cke(mem_cke),
7217
    .cs_n(mem_cs_n),
7218
    .dqm(mem_dqm),
7219
    .dq_i(mem_dq_i),
7220
    .dq_o(mem_dq_o),
7221
    .dq_oe(mem_dq_oe),
7222
    // system
7223
    .clk(mem_clk),
7224
    .rst(mem_rst) );
7225
`undef MODULE
7226
 
7227
endmodule
7228
`endif
7229 18 unneback
//////////////////////////////////////////////////////////////////////
7230
////                                                              ////
7231
////  Arithmetic functions                                        ////
7232
////                                                              ////
7233
////  Description                                                 ////
7234
////  Arithmetic functions for ALU and DSP                        ////
7235
////                                                              ////
7236
////                                                              ////
7237
////  To Do:                                                      ////
7238
////   -                                                          ////
7239
////                                                              ////
7240
////  Author(s):                                                  ////
7241
////      - Michael Unneback, unneback@opencores.org              ////
7242
////        ORSoC AB                                              ////
7243
////                                                              ////
7244
//////////////////////////////////////////////////////////////////////
7245
////                                                              ////
7246
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
7247
////                                                              ////
7248
//// This source file may be used and distributed without         ////
7249
//// restriction provided that this copyright statement is not    ////
7250
//// removed from the file and that any derivative work contains  ////
7251
//// the original copyright notice and the associated disclaimer. ////
7252
////                                                              ////
7253
//// This source file is free software; you can redistribute it   ////
7254
//// and/or modify it under the terms of the GNU Lesser General   ////
7255
//// Public License as published by the Free Software Foundation; ////
7256
//// either version 2.1 of the License, or (at your option) any   ////
7257
//// later version.                                               ////
7258
////                                                              ////
7259
//// This source is distributed in the hope that it will be       ////
7260
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
7261
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
7262
//// PURPOSE.  See the GNU Lesser General Public License for more ////
7263
//// details.                                                     ////
7264
////                                                              ////
7265
//// You should have received a copy of the GNU Lesser General    ////
7266
//// Public License along with this source; if not, download it   ////
7267
//// from http://www.opencores.org/lgpl.shtml                     ////
7268
////                                                              ////
7269
//////////////////////////////////////////////////////////////////////
7270
 
7271 40 unneback
`ifdef MULTS
7272 18 unneback
// signed multiplication
7273 40 unneback
`define MODULE mults
7274
module `BASE`MODULE (a,b,p);
7275
`undef MODULE
7276 18 unneback
parameter operand_a_width = 18;
7277
parameter operand_b_width = 18;
7278
parameter result_hi = 35;
7279
parameter result_lo = 0;
7280
input [operand_a_width-1:0] a;
7281
input [operand_b_width-1:0] b;
7282
output [result_hi:result_lo] p;
7283
wire signed [operand_a_width-1:0] ai;
7284
wire signed [operand_b_width-1:0] bi;
7285
wire signed [operand_a_width+operand_b_width-1:0] result;
7286
 
7287
    assign ai = a;
7288
    assign bi = b;
7289
    assign result = ai * bi;
7290
    assign p = result[result_hi:result_lo];
7291
 
7292
endmodule
7293 40 unneback
`endif
7294
`ifdef MULTS18X18
7295
`define MODULE mults18x18
7296
module `BASE`MODULE (a,b,p);
7297
`undef MODULE
7298 18 unneback
input [17:0] a,b;
7299
output [35:0] p;
7300
vl_mult
7301
    # (.operand_a_width(18), .operand_b_width(18))
7302
    mult0 (.a(a), .b(b), .p(p));
7303
endmodule
7304 40 unneback
`endif
7305 18 unneback
 
7306 40 unneback
`ifdef MULT
7307
`define MODULE mult
7308 18 unneback
// unsigned multiplication
7309 40 unneback
module `BASE`MODULE (a,b,p);
7310
`undef MODULE
7311 18 unneback
parameter operand_a_width = 18;
7312
parameter operand_b_width = 18;
7313
parameter result_hi = 35;
7314
parameter result_lo = 0;
7315
input [operand_a_width-1:0] a;
7316
input [operand_b_width-1:0] b;
7317
output [result_hi:result_hi] p;
7318
 
7319
wire [operand_a_width+operand_b_width-1:0] result;
7320
 
7321
    assign result = a * b;
7322
    assign p = result[result_hi:result_lo];
7323
 
7324
endmodule
7325 40 unneback
`endif
7326 18 unneback
 
7327 40 unneback
`ifdef SHIFT_UNIT_32
7328
`define MODULE shift_unit_32
7329 18 unneback
// shift unit
7330
// supporting the following shift functions
7331
//   SLL
7332
//   SRL
7333
//   SRA
7334
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
7335 40 unneback
module `BASE`MODULE( din, s, dout, opcode);
7336
`undef MODULE
7337 18 unneback
input [31:0] din; // data in operand
7338
input [4:0] s; // shift operand
7339
input [1:0] opcode;
7340
output [31:0] dout;
7341
 
7342
parameter opcode_sll = 2'b00;
7343
//parameter opcode_srl = 2'b01;
7344
parameter opcode_sra = 2'b10;
7345
//parameter opcode_ror = 2'b11;
7346
 
7347
wire sll, sra;
7348
assign sll = opcode == opcode_sll;
7349
assign sra = opcode == opcode_sra;
7350
 
7351
wire [15:1] s1;
7352
wire [3:0] sign;
7353
wire [7:0] tmp [0:3];
7354
 
7355
// first stage is multiplier based
7356
// shift operand as fractional 8.7
7357
assign s1[15] = sll & s[2:0]==3'd7;
7358
assign s1[14] = sll & s[2:0]==3'd6;
7359
assign s1[13] = sll & s[2:0]==3'd5;
7360
assign s1[12] = sll & s[2:0]==3'd4;
7361
assign s1[11] = sll & s[2:0]==3'd3;
7362
assign s1[10] = sll & s[2:0]==3'd2;
7363
assign s1[ 9] = sll & s[2:0]==3'd1;
7364
assign s1[ 8] = s[2:0]==3'd0;
7365
assign s1[ 7] = !sll & s[2:0]==3'd1;
7366
assign s1[ 6] = !sll & s[2:0]==3'd2;
7367
assign s1[ 5] = !sll & s[2:0]==3'd3;
7368
assign s1[ 4] = !sll & s[2:0]==3'd4;
7369
assign s1[ 3] = !sll & s[2:0]==3'd5;
7370
assign s1[ 2] = !sll & s[2:0]==3'd6;
7371
assign s1[ 1] = !sll & s[2:0]==3'd7;
7372
 
7373
assign sign[3] = din[31] & sra;
7374
assign sign[2] = sign[3] & (&din[31:24]);
7375
assign sign[1] = sign[2] & (&din[23:16]);
7376
assign sign[0] = sign[1] & (&din[15:8]);
7377 40 unneback
`define MODULE mults
7378
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
7379
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
7380
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
7381
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
7382
`undef MODULE
7383 18 unneback
// second stage is multiplexer based
7384
// shift on byte level
7385
 
7386
// mux byte 3
7387
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
7388
                     (sll & s[4:3]==2'b01) ? tmp[2] :
7389
                     (sll & s[4:3]==2'b10) ? tmp[1] :
7390
                     (sll & s[4:3]==2'b11) ? tmp[0] :
7391
                     {8{sign[3]}};
7392
 
7393
// mux byte 2
7394
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
7395
                     (sll & s[4:3]==2'b01) ? tmp[1] :
7396
                     (sll & s[4:3]==2'b10) ? tmp[0] :
7397
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
7398
                     (s[4:3]==2'b01) ? tmp[3] :
7399
                     {8{sign[3]}};
7400
 
7401
// mux byte 1
7402
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
7403
                     (sll & s[4:3]==2'b01) ? tmp[0] :
7404
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
7405
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
7406
                     (s[4:3]==2'b01) ? tmp[2] :
7407
                     (s[4:3]==2'b10) ? tmp[3] :
7408
                     {8{sign[3]}};
7409
 
7410
// mux byte 0
7411
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
7412
                     (sll) ?  {8{1'b0}}:
7413
                     (s[4:3]==2'b01) ? tmp[1] :
7414
                     (s[4:3]==2'b10) ? tmp[2] :
7415
                     tmp[3];
7416
 
7417
endmodule
7418 40 unneback
`endif
7419 18 unneback
 
7420 40 unneback
`ifdef LOGIC_UNIT
7421 18 unneback
// logic unit
7422
// supporting the following logic functions
7423
//    a and b
7424
//    a or  b
7425
//    a xor b
7426
//    not b
7427 40 unneback
`define MODULE logic_unit
7428
module `BASE`MODULE( a, b, result, opcode);
7429
`undef MODULE
7430 18 unneback
parameter width = 32;
7431
parameter opcode_and = 2'b00;
7432
parameter opcode_or  = 2'b01;
7433
parameter opcode_xor = 2'b10;
7434
input [width-1:0] a,b;
7435
output [width-1:0] result;
7436
input [1:0] opcode;
7437
 
7438
assign result = (opcode==opcode_and) ? a & b :
7439
                (opcode==opcode_or)  ? a | b :
7440
                (opcode==opcode_xor) ? a ^ b :
7441
                b;
7442
 
7443
endmodule
7444 48 unneback
`endif
7445 18 unneback
 
7446 48 unneback
`ifdef ARITH_UNIT
7447
`define MODULE arith_unit
7448
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
7449
`undef MODULE
7450 18 unneback
parameter width = 32;
7451
parameter opcode_add = 1'b0;
7452
parameter opcode_sub = 1'b1;
7453
input [width-1:0] a,b;
7454
input c_in, add_sub, sign;
7455
output [width-1:0] result;
7456
output c_out, z, ovfl;
7457
 
7458
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
7459
assign z = (result=={width{1'b0}});
7460
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
7461
               (~a[width-1] & ~b[width-1] &  result[width-1]);
7462
endmodule
7463 40 unneback
`endif
7464 48 unneback
 
7465
`ifdef COUNT_UNIT
7466
`define MODULE count_unit
7467
module `BASE`MODULE (din, dout, opcode);
7468
`undef MODULE
7469
parameter width = 32;
7470
input [width-1:0] din;
7471
output [width-1:0] dout;
7472
input opcode;
7473
 
7474
integer i;
7475 58 unneback
wire [width/32+4:0] ff1, fl1;
7476 48 unneback
 
7477 57 unneback
/*
7478 48 unneback
always @(din) begin
7479
    ff1 = 0; i = 0;
7480
    while (din[i] == 0 && i < width) begin // complex condition
7481
        ff1 = ff1 + 1;
7482
        i = i + 1;
7483
    end
7484
end
7485
 
7486
always @(din) begin
7487
    fl1 = width; i = width-1;
7488
    while (din[i] == 0 && i >= width) begin // complex condition
7489
        fl1 = fl1 - 1;
7490
        i = i - 1;
7491
    end
7492
end
7493 57 unneback
*/
7494 48 unneback
 
7495
generate
7496
if (width==32) begin
7497 57 unneback
 
7498
    assign ff1 = din[0] ? 6'd1 :
7499
                 din[1] ? 6'd2 :
7500
                 din[2] ? 6'd3 :
7501
                 din[3] ? 6'd4 :
7502
                 din[4] ? 6'd5 :
7503
                 din[5] ? 6'd6 :
7504
                 din[6] ? 6'd7 :
7505
                 din[7] ? 6'd8 :
7506
                 din[8] ? 6'd9 :
7507
                 din[9] ? 6'd10 :
7508
                 din[10] ? 6'd11 :
7509
                 din[11] ? 6'd12 :
7510
                 din[12] ? 6'd13 :
7511
                 din[13] ? 6'd14 :
7512
                 din[14] ? 6'd15 :
7513
                 din[15] ? 6'd16 :
7514
                 din[16] ? 6'd17 :
7515
                 din[17] ? 6'd18 :
7516
                 din[18] ? 6'd19 :
7517
                 din[19] ? 6'd20 :
7518
                 din[20] ? 6'd21 :
7519
                 din[21] ? 6'd22 :
7520
                 din[22] ? 6'd23 :
7521
                 din[23] ? 6'd24 :
7522
                 din[24] ? 6'd25 :
7523
                 din[25] ? 6'd26 :
7524
                 din[26] ? 6'd27 :
7525
                 din[27] ? 6'd28 :
7526
                 din[28] ? 6'd29 :
7527
                 din[29] ? 6'd30 :
7528
                 din[30] ? 6'd31 :
7529
                 din[31] ? 6'd32 :
7530
                 6'd0;
7531
 
7532
    assign fl1 = din[31] ? 6'd32 :
7533
                 din[30] ? 6'd31 :
7534
                 din[29] ? 6'd30 :
7535
                 din[28] ? 6'd29 :
7536
                 din[27] ? 6'd28 :
7537
                 din[26] ? 6'd27 :
7538
                 din[25] ? 6'd26 :
7539
                 din[24] ? 6'd25 :
7540
                 din[23] ? 6'd24 :
7541
                 din[22] ? 6'd23 :
7542
                 din[21] ? 6'd22 :
7543
                 din[20] ? 6'd21 :
7544
                 din[19] ? 6'd20 :
7545
                 din[18] ? 6'd19 :
7546
                 din[17] ? 6'd18 :
7547
                 din[16] ? 6'd17 :
7548
                 din[15] ? 6'd16 :
7549
                 din[14] ? 6'd15 :
7550
                 din[13] ? 6'd14 :
7551
                 din[12] ? 6'd13 :
7552
                 din[11] ? 6'd12 :
7553
                 din[10] ? 6'd11 :
7554
                 din[9] ? 6'd10 :
7555
                 din[8] ? 6'd9 :
7556
                 din[7] ? 6'd8 :
7557
                 din[6] ? 6'd7 :
7558
                 din[5] ? 6'd6 :
7559
                 din[4] ? 6'd5 :
7560
                 din[3] ? 6'd4 :
7561
                 din[2] ? 6'd3 :
7562
                 din[1] ? 6'd2 :
7563
                 din[0] ? 6'd1 :
7564
                 6'd0;
7565
 
7566
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
7567 48 unneback
end
7568
endgenerate
7569 57 unneback
 
7570 48 unneback
generate
7571
if (width==64) begin
7572 57 unneback
    assign ff1 = 7'd0;
7573
    assign fl1 = 7'd0;
7574
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
7575 48 unneback
end
7576
endgenerate
7577
 
7578
endmodule
7579
`endif
7580
 
7581
`ifdef EXT_UNIT
7582
`define MODULE ext_unit
7583
module `BASE`MODULE ( a, b, F, result, opcode);
7584
`undef MODULE
7585
parameter width = 32;
7586
input [width-1:0] a, b;
7587
input F;
7588
output reg [width-1:0] result;
7589
input [2:0] opcode;
7590
 
7591
generate
7592
if (width==32) begin
7593
always @ (a or b or F or opcode)
7594
begin
7595
    case (opcode)
7596
    3'b000: result = {{24{1'b0}},a[7:0]};
7597
    3'b001: result = {{24{a[7]}},a[7:0]};
7598
    3'b010: result = {{16{1'b0}},a[7:0]};
7599
    3'b011: result = {{16{a[15]}},a[15:0]};
7600
    3'b110: result = (F) ? a : b;
7601
    default: result = {b[15:0],16'h0000};
7602
    endcase
7603
end
7604
end
7605
endgenerate
7606
 
7607
generate
7608
if (width==64) begin
7609
always @ (a or b or F or opcode)
7610
begin
7611
    case (opcode)
7612
    3'b000: result = {{56{1'b0}},a[7:0]};
7613
    3'b001: result = {{56{a[7]}},a[7:0]};
7614
    3'b010: result = {{48{1'b0}},a[7:0]};
7615
    3'b011: result = {{48{a[15]}},a[15:0]};
7616 57 unneback
    3'b110: result = (F) ? a : b;
7617 48 unneback
    default: result = {32'h00000000,b[15:0],16'h0000};
7618
    endcase
7619
end
7620
end
7621
endgenerate
7622
endmodule
7623
`endif

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