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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 137

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
14
    // ACTEL FPGA should not use logic to handle rw collision
15
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16
`else
17
    `define SYN_NO_RW_CHECK
18
`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
23
`define SYNC_RST
24
`define PLL
25
 
26
`define MULTS
27
`define MULTS18X18
28
`define MULT
29
`define SHIFT_UNIT_32
30
`define LOGIC_UNIT
31
 
32
`define CNT_SHREG_WRAP
33
`define CNT_SHREG_CE_WRAP
34 105 unneback
`define CNT_SHREG_CLEAR
35 40 unneback
`define CNT_SHREG_CE_CLEAR
36
`define CNT_SHREG_CE_CLEAR_WRAP
37
 
38
`define MUX_ANDOR
39
`define MUX2_ANDOR
40
`define MUX3_ANDOR
41
`define MUX4_ANDOR
42
`define MUX5_ANDOR
43
`define MUX6_ANDOR
44 43 unneback
`define PARITY
45 40 unneback
 
46
`define ROM_INIT
47
`define RAM
48
`define RAM_BE
49
`define DPRAM_1R1W
50
`define DPRAM_2R1W
51 100 unneback
`define DPRAM_1R2W
52 40 unneback
`define DPRAM_2R2W
53 75 unneback
`define DPRAM_BE_2R2W
54 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
55
`define FIFO_2R2W_SYNC_SIMPLEX
56
`define FIFO_CMP_ASYNC
57
`define FIFO_1R1W_ASYNC
58
`define FIFO_2R2W_ASYNC
59
`define FIFO_2R2W_ASYNC_SIMPLEX
60 48 unneback
`define REG_FILE
61 40 unneback
 
62
`define DFF
63
`define DFF_ARRAY
64
`define DFF_CE
65
`define DFF_CE_CLEAR
66
`define DF_CE_SET
67
`define SPR
68
`define SRP
69
`define DFF_SR
70
`define LATCH
71
`define SHREG
72
`define SHREG_CE
73
`define DELAY
74
`define DELAY_EMPTYFLAG
75 94 unneback
`define PULSE2TOGGLE
76
`define TOGGLE2PULSE
77
`define SYNCHRONIZER
78
`define CDC
79 40 unneback
 
80 75 unneback
`define WB3AVALON_BRIDGE
81 40 unneback
`define WB3WB3_BRIDGE
82
`define WB3_ARBITER_TYPE1
83 83 unneback
`define WB_ADR_INC
84 101 unneback
`define WB_RAM
85 103 unneback
`define WB_SHADOW_RAM
86 48 unneback
`define WB_B4_ROM
87 40 unneback
`define WB_BOOT_ROM
88
`define WB_DPRAM
89 101 unneback
`define WB_CACHE
90 103 unneback
`define WB_AVALON_BRIDGE
91
`define WB_AVALON_MEM_CACHE
92 136 unneback
`define WB_SDR_SDRAM_CTRL
93 40 unneback
 
94 44 unneback
`define IO_DFF_OE
95
`define O_DFF
96 136 unneback
`define O_DDR
97
`define O_CLK
98 44 unneback
 
99 40 unneback
`endif
100
 
101 136 unneback
///////////////////////////////////////
102
// dependencies
103
///////////////////////////////////////
104
 
105 40 unneback
`ifdef PLL
106
`ifndef SYNC_RST
107
`define SYNC_RST
108
`endif
109
`endif
110
 
111
`ifdef SYNC_RST
112
`ifndef GBUF
113
`define GBUF
114
`endif
115
`endif
116
 
117 136 unneback
`ifdef WB_SDR_SDRAM_CTRL
118
`ifndef WB_SHADOW_RAM
119
`define WB_SHADOW_RAM
120
`endif
121
`ifndef WB_CACHE
122
`define WB_CACHE
123
`endif
124
`ifndef WB_SDR_SDRAM
125
`define WB_SDR_SDRAM
126
`endif
127
`ifndef IO_DFF_OE
128
`define IO_DFF_OE
129
`endif
130
`ifndef O_DFF
131
`define O_DFF
132
`endif
133
`ifndef O_CLK
134
`define O_CLK
135
`endif
136
`endif
137
 
138
`ifdef WB_SDR_SDRAM
139
`ifndef CNT_SHREG_CLEAR
140
`define CNT_SHREG_CLEAR
141
`endif
142
`ifndef CNT_LFSR_ZQ
143
`define CNT_LFSR_ZQ
144
`endif
145
`ifndef DELAY_EMPTYFLAG
146
`define DELAY_EMPTYFLAG
147
`endif
148
`endif
149
 
150 108 unneback
`ifdef WB_DPRAM
151 92 unneback
`ifndef WB_ADR_INC
152
`define WB_ADR_INC
153 40 unneback
`endif
154 92 unneback
`ifndef DPRAM_BE_2R2W
155
`define DPRAM_BE_2R2W
156 40 unneback
`endif
157
`endif
158
 
159
`ifdef WB3_ARBITER_TYPE1
160 42 unneback
`ifndef SPR
161
`define SPR
162
`endif
163 40 unneback
`ifndef MUX_ANDOR
164
`define MUX_ANDOR
165
`endif
166
`endif
167
 
168 76 unneback
`ifdef WB3AVALON_BRIDGE
169
`ifndef WB3WB3_BRIDGE
170
`define WB3WB3_BRIDGE
171
`endif
172
`endif
173
 
174 40 unneback
`ifdef WB3WB3_BRIDGE
175
`ifndef CNT_SHREG_CE_CLEAR
176
`define CNT_SHREG_CE_CLEAR
177
`endif
178
`ifndef DFF
179
`define DFF
180
`endif
181
`ifndef DFF_CE
182
`define DFF_CE
183
`endif
184
`ifndef CNT_SHREG_CE_CLEAR
185
`define CNT_SHREG_CE_CLEAR
186
`endif
187
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
188
`define FIFO_2R2W_ASYNC_SIMPLEX
189
`endif
190
`endif
191
 
192 103 unneback
 
193
`ifdef WB_AVALON_MEM_CACHE
194
`ifndef WB_SHADOW_RAM
195
`define WB_SHADOW_RAM
196
`endif
197
`ifndef WB_CACHE
198
`define WB_CACHE
199
`endif
200
`ifndef WB_AVALON_BRIDGE
201
`define WB_AVALON_BRIDGE
202
`endif
203
`endif
204
 
205 101 unneback
`ifdef WB_CACHE
206 100 unneback
`ifndef RAM
207
`define RAM
208
`endif
209
`ifndef WB_ADR_INC
210
`define WB_ADR_INC
211
`endif
212
`ifndef DPRAM_1R1W
213
`define DPRAM_1R1W
214
`endif
215
`ifndef DPRAM_1R2W
216
`define DPRAM_1R2W
217
`endif
218
`ifndef DPRAM_BE_2R2W
219
`define DPRAM_BE_2R2W
220
`endif
221
`ifndef CDC
222
`define CDC
223
`endif
224 136 unneback
`ifndef O_DFF
225
`define O_DFF
226 100 unneback
`endif
227 136 unneback
`ifndef O_CLK
228
`define O_CLK
229
`endif
230
`endif
231 103 unneback
 
232
`ifdef WB_SHADOW_RAM
233 115 unneback
`ifndef WB_RAM
234
`define WB_RAM
235 103 unneback
`endif
236
`endif
237
 
238
`ifdef WB_RAM
239
`ifndef WB_ADR_INC
240
`define WB_ADR_INC
241
`endif
242 114 unneback
`ifndef RAM_BE
243
`define RAM_BE
244 103 unneback
`endif
245 114 unneback
`endif
246
 
247 40 unneback
`ifdef MULTS18X18
248
`ifndef MULTS
249
`define MULTS
250
`endif
251
`endif
252
 
253
`ifdef SHIFT_UNIT_32
254
`ifndef MULTS
255
`define MULTS
256
`endif
257
`endif
258
 
259
`ifdef MUX2_ANDOR
260
`ifndef MUX_ANDOR
261
`define MUX_ANDOR
262
`endif
263
`endif
264
 
265
`ifdef MUX3_ANDOR
266
`ifndef MUX_ANDOR
267
`define MUX_ANDOR
268
`endif
269
`endif
270
 
271
`ifdef MUX4_ANDOR
272
`ifndef MUX_ANDOR
273
`define MUX_ANDOR
274
`endif
275
`endif
276
 
277
`ifdef MUX5_ANDOR
278
`ifndef MUX_ANDOR
279
`define MUX_ANDOR
280
`endif
281
`endif
282
 
283
`ifdef MUX6_ANDOR
284
`ifndef MUX_ANDOR
285
`define MUX_ANDOR
286
`endif
287
`endif
288
 
289
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
290
`ifndef CNT_BIN_CE
291
`define CNT_BIN_CE
292
`endif
293
`ifndef DPRAM_1R1W
294
`define DPRAM_1R1W
295
`endif
296
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
297
`define CNT_BIN_CE_REW_Q_ZQ_L1
298
`endif
299
`endif
300
 
301
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
302
`ifndef CNT_LFSR_CE
303
`define CNT_LFSR_CE
304
`endif
305
`ifndef DPRAM_2R2W
306
`define DPRAM_2R2W
307
`endif
308
`ifndef CNT_BIN_CE_REW_ZQ_L1
309
`define CNT_BIN_CE_REW_ZQ_L1
310
`endif
311
`endif
312
 
313
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
314
`ifndef CNT_GRAY_CE_BIN
315
`define CNT_GRAY_CE_BIN
316
`endif
317
`ifndef DPRAM_2R2W
318
`define DPRAM_2R2W
319
`endif
320
`ifndef FIFO_CMP_ASYNC
321
`define FIFO_CMP_ASYNC
322
`endif
323
`endif
324
 
325
`ifdef FIFO_2R2W_ASYNC
326
`ifndef FIFO_1R1W_ASYNC
327
`define FIFO_1R1W_ASYNC
328
`endif
329
`endif
330
 
331
`ifdef FIFO_1R1W_ASYNC
332
`ifndef CNT_GRAY_CE_BIN
333
`define CNT_GRAY_CE_BIN
334
`endif
335
`ifndef DPRAM_1R1W
336
`define DPRAM_1R1W
337
`endif
338
`ifndef FIFO_CMP_ASYNC
339
`define FIFO_CMP_ASYNC
340
`endif
341
`endif
342
 
343
`ifdef FIFO_CMP_ASYNC
344
`ifndef DFF_SR
345
`define DFF_SR
346
`endif
347
`ifndef DFF
348
`define DFF
349
`endif
350
`endif
351 48 unneback
 
352
`ifdef REG_FILE
353
`ifndef DPRAM_1R1W
354
`define DPRAM_1R1W
355
`endif
356
`endif
357 97 unneback
 
358 98 unneback
`ifdef CDC
359
`ifndef PULSE2TOGGLE
360
`define PULSE2TOGGLE
361
`endif
362
`ifndef TOGGLE2PULSE
363
`define TOGGLE2PULSE
364
`endif
365
`ifndef SYNCHRONIZER
366
`define SYNCHRONIZER
367
`endif
368
`endif
369
 
370 136 unneback
`ifdef O_CLK
371
`ifndef O_DDR
372
`define O_DDR
373
`endif
374
`endif
375
 
376 97 unneback
// size to width
377 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
378 62 unneback
//////////////////////////////////////////////////////////////////////
379 6 unneback
////                                                              ////
380
////  Versatile library, clock and reset                          ////
381
////                                                              ////
382
////  Description                                                 ////
383
////  Logic related to clock and reset                            ////
384
////                                                              ////
385
////                                                              ////
386
////  To Do:                                                      ////
387
////   - add more different registers                             ////
388
////                                                              ////
389
////  Author(s):                                                  ////
390
////      - Michael Unneback, unneback@opencores.org              ////
391
////        ORSoC AB                                              ////
392
////                                                              ////
393
//////////////////////////////////////////////////////////////////////
394
////                                                              ////
395
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
396
////                                                              ////
397
//// This source file may be used and distributed without         ////
398
//// restriction provided that this copyright statement is not    ////
399
//// removed from the file and that any derivative work contains  ////
400
//// the original copyright notice and the associated disclaimer. ////
401
////                                                              ////
402
//// This source file is free software; you can redistribute it   ////
403
//// and/or modify it under the terms of the GNU Lesser General   ////
404
//// Public License as published by the Free Software Foundation; ////
405
//// either version 2.1 of the License, or (at your option) any   ////
406
//// later version.                                               ////
407
////                                                              ////
408
//// This source is distributed in the hope that it will be       ////
409
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
410
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
411
//// PURPOSE.  See the GNU Lesser General Public License for more ////
412
//// details.                                                     ////
413
////                                                              ////
414
//// You should have received a copy of the GNU Lesser General    ////
415
//// Public License along with this source; if not, download it   ////
416
//// from http://www.opencores.org/lgpl.shtml                     ////
417
////                                                              ////
418
//////////////////////////////////////////////////////////////////////
419
 
420 48 unneback
`ifdef ACTEL
421
`ifdef GBUF
422
`timescale 1 ns/100 ps
423 6 unneback
// Global buffer
424
// usage:
425
// use to enable global buffers for high fan out signals such as clock and reset
426
// Version: 8.4 8.4.0.33
427
module gbuf(GL,CLK);
428
output GL;
429
input  CLK;
430
 
431
    wire GND;
432
 
433
    GND GND_1_net(.Y(GND));
434
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
435
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
436
 
437
endmodule
438
`timescale 1 ns/1 ns
439 40 unneback
`define MODULE gbuf
440
module `BASE`MODULE ( i, o);
441
`undef MODULE
442 6 unneback
input i;
443
output o;
444
`ifdef SIM_GBUF
445
assign o=i;
446
`else
447
gbuf gbuf_i0 ( .CLK(i), .GL(o));
448
`endif
449
endmodule
450 40 unneback
`endif
451 33 unneback
 
452 6 unneback
`else
453 33 unneback
 
454 40 unneback
`ifdef ALTERA
455
`ifdef GBUF
456 21 unneback
//altera
457 40 unneback
`define MODULE gbuf
458
module `BASE`MODULE ( i, o);
459
`undef MODULE
460 33 unneback
input i;
461
output o;
462
assign o = i;
463
endmodule
464 40 unneback
`endif
465 33 unneback
 
466 6 unneback
`else
467
 
468 40 unneback
`ifdef GBUF
469 6 unneback
`timescale 1 ns/100 ps
470 40 unneback
`define MODULE
471
module `BASE`MODULE ( i, o);
472
`undef MODULE
473 6 unneback
input i;
474
output o;
475
assign o = i;
476
endmodule
477 40 unneback
`endif
478 6 unneback
`endif // ALTERA
479
`endif //ACTEL
480
 
481 40 unneback
`ifdef SYNC_RST
482 6 unneback
// sync reset
483 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
484 6 unneback
// output active high global reset sync with two DFFs 
485
`timescale 1 ns/100 ps
486 40 unneback
`define MODULE sync_rst
487
module `BASE`MODULE ( rst_n_i, rst_o, clk);
488
`undef MODULE
489 6 unneback
input rst_n_i, clk;
490
output rst_o;
491 18 unneback
reg [1:0] tmp;
492 6 unneback
always @ (posedge clk or negedge rst_n_i)
493
if (!rst_n_i)
494 17 unneback
        tmp <= 2'b11;
495 6 unneback
else
496 33 unneback
        tmp <= {1'b0,tmp[1]};
497 40 unneback
`define MODULE gbuf
498
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
499
`undef MODULE
500 6 unneback
endmodule
501 40 unneback
`endif
502 6 unneback
 
503 40 unneback
`ifdef PLL
504 6 unneback
// vl_pll
505
`ifdef ACTEL
506 32 unneback
///////////////////////////////////////////////////////////////////////////////
507 17 unneback
`timescale 1 ps/1 ps
508 40 unneback
`define MODULE pll
509
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
510
`undef MODULE
511 6 unneback
parameter index = 0;
512
parameter number_of_clk = 1;
513 17 unneback
parameter period_time_0 = 20000;
514
parameter period_time_1 = 20000;
515
parameter period_time_2 = 20000;
516
parameter lock_delay = 2000000;
517 6 unneback
input clk_i, rst_n_i;
518
output lock;
519
output reg [0:number_of_clk-1] clk_o;
520
output [0:number_of_clk-1] rst_o;
521
 
522
`ifdef SIM_PLL
523
 
524
always
525
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
526
 
527
generate if (number_of_clk > 1)
528
always
529
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
530
endgenerate
531
 
532
generate if (number_of_clk > 2)
533
always
534
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
535
endgenerate
536
 
537
genvar i;
538
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
539
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
540
end
541
endgenerate
542
 
543
assign #lock_delay lock = rst_n_i;
544
 
545
endmodule
546
`else
547
generate if (number_of_clk==1 & index==0) begin
548
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
549
end
550
endgenerate // index==0
551
generate if (number_of_clk==1 & index==1) begin
552
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
553
end
554
endgenerate // index==1
555
generate if (number_of_clk==1 & index==2) begin
556
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
557
end
558
endgenerate // index==2
559
generate if (number_of_clk==1 & index==3) begin
560
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
561
end
562
endgenerate // index==0
563
 
564
generate if (number_of_clk==2 & index==0) begin
565
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
566
end
567
endgenerate // index==0
568
generate if (number_of_clk==2 & index==1) begin
569
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
570
end
571
endgenerate // index==1
572
generate if (number_of_clk==2 & index==2) begin
573
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
574
end
575
endgenerate // index==2
576
generate if (number_of_clk==2 & index==3) begin
577
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
578
end
579
endgenerate // index==0
580
 
581
generate if (number_of_clk==3 & index==0) begin
582
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
583
end
584
endgenerate // index==0
585
generate if (number_of_clk==3 & index==1) begin
586
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
587
end
588
endgenerate // index==1
589
generate if (number_of_clk==3 & index==2) begin
590
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
591
end
592
endgenerate // index==2
593
generate if (number_of_clk==3 & index==3) begin
594
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
595
end
596
endgenerate // index==0
597
 
598
genvar i;
599
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
600 40 unneback
`define MODULE sync_rst
601
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
602
`undef MODULE
603 6 unneback
end
604
endgenerate
605
endmodule
606
`endif
607 32 unneback
///////////////////////////////////////////////////////////////////////////////
608 6 unneback
 
609
`else
610
 
611 32 unneback
///////////////////////////////////////////////////////////////////////////////
612 6 unneback
`ifdef ALTERA
613
 
614 32 unneback
`timescale 1 ps/1 ps
615 40 unneback
`define MODULE pll
616
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
617
`undef MODULE
618 32 unneback
parameter index = 0;
619
parameter number_of_clk = 1;
620
parameter period_time_0 = 20000;
621
parameter period_time_1 = 20000;
622
parameter period_time_2 = 20000;
623
parameter period_time_3 = 20000;
624
parameter period_time_4 = 20000;
625
parameter lock_delay = 2000000;
626
input clk_i, rst_n_i;
627
output lock;
628
output reg [0:number_of_clk-1] clk_o;
629
output [0:number_of_clk-1] rst_o;
630
 
631
`ifdef SIM_PLL
632
 
633
always
634
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
635
 
636
generate if (number_of_clk > 1)
637
always
638
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
639
endgenerate
640
 
641
generate if (number_of_clk > 2)
642
always
643
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
644
endgenerate
645
 
646 33 unneback
generate if (number_of_clk > 3)
647 32 unneback
always
648
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
649
endgenerate
650
 
651 33 unneback
generate if (number_of_clk > 4)
652 32 unneback
always
653
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
654
endgenerate
655
 
656
genvar i;
657
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
658
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
659
end
660
endgenerate
661
 
662 33 unneback
//assign #lock_delay lock = rst_n_i;
663
assign lock = rst_n_i;
664 32 unneback
 
665
endmodule
666 6 unneback
`else
667
 
668 33 unneback
`ifdef VL_PLL0
669
`ifdef VL_PLL0_CLK1
670
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
671
`endif
672
`ifdef VL_PLL0_CLK2
673
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
674
`endif
675
`ifdef VL_PLL0_CLK3
676
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
677
`endif
678
`ifdef VL_PLL0_CLK4
679
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
680
`endif
681
`ifdef VL_PLL0_CLK5
682
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
683
`endif
684
`endif
685 32 unneback
 
686 33 unneback
`ifdef VL_PLL1
687
`ifdef VL_PLL1_CLK1
688
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
689
`endif
690
`ifdef VL_PLL1_CLK2
691
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
692
`endif
693
`ifdef VL_PLL1_CLK3
694
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
695
`endif
696
`ifdef VL_PLL1_CLK4
697
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
698
`endif
699
`ifdef VL_PLL1_CLK5
700
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
701
`endif
702
`endif
703 32 unneback
 
704 33 unneback
`ifdef VL_PLL2
705
`ifdef VL_PLL2_CLK1
706
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
707
`endif
708
`ifdef VL_PLL2_CLK2
709
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
710
`endif
711
`ifdef VL_PLL2_CLK3
712
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
713
`endif
714
`ifdef VL_PLL2_CLK4
715
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
716
`endif
717
`ifdef VL_PLL2_CLK5
718
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
719
`endif
720
`endif
721 32 unneback
 
722 33 unneback
`ifdef VL_PLL3
723
`ifdef VL_PLL3_CLK1
724
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
725
`endif
726
`ifdef VL_PLL3_CLK2
727
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
728
`endif
729
`ifdef VL_PLL3_CLK3
730
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
731
`endif
732
`ifdef VL_PLL3_CLK4
733
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
734
`endif
735
`ifdef VL_PLL3_CLK5
736
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
737
`endif
738
`endif
739 32 unneback
 
740
genvar i;
741
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
742 40 unneback
`define MODULE sync_rst
743
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
744
`undef MODULE
745 32 unneback
end
746
endgenerate
747
endmodule
748
`endif
749
///////////////////////////////////////////////////////////////////////////////
750
 
751
`else
752
 
753 6 unneback
// generic PLL
754 17 unneback
`timescale 1 ps/1 ps
755 40 unneback
`define MODULE pll
756
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
757
`undef MODULE
758 6 unneback
parameter index = 0;
759
parameter number_of_clk = 1;
760 17 unneback
parameter period_time_0 = 20000;
761
parameter period_time_1 = 20000;
762
parameter period_time_2 = 20000;
763 6 unneback
parameter lock_delay = 2000;
764
input clk_i, rst_n_i;
765
output lock;
766
output reg [0:number_of_clk-1] clk_o;
767
output [0:number_of_clk-1] rst_o;
768
 
769
always
770
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
771
 
772
generate if (number_of_clk > 1)
773
always
774
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
775
endgenerate
776
 
777
generate if (number_of_clk > 2)
778
always
779
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
780
endgenerate
781
 
782
genvar i;
783
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
784 40 unneback
`define MODULE sync_rst
785
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
786
`undef MODULE
787 6 unneback
end
788
endgenerate
789
 
790
assign #lock_delay lock = rst_n_i;
791
 
792
endmodule
793
 
794
`endif //altera
795 17 unneback
`endif //actel
796 40 unneback
`undef MODULE
797
`endif//////////////////////////////////////////////////////////////////////
798 6 unneback
////                                                              ////
799
////  Versatile library, registers                                ////
800
////                                                              ////
801
////  Description                                                 ////
802
////  Different type of registers                                 ////
803
////                                                              ////
804
////                                                              ////
805
////  To Do:                                                      ////
806
////   - add more different registers                             ////
807
////                                                              ////
808
////  Author(s):                                                  ////
809
////      - Michael Unneback, unneback@opencores.org              ////
810
////        ORSoC AB                                              ////
811
////                                                              ////
812
//////////////////////////////////////////////////////////////////////
813
////                                                              ////
814
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
815
////                                                              ////
816
//// This source file may be used and distributed without         ////
817
//// restriction provided that this copyright statement is not    ////
818
//// removed from the file and that any derivative work contains  ////
819
//// the original copyright notice and the associated disclaimer. ////
820
////                                                              ////
821
//// This source file is free software; you can redistribute it   ////
822
//// and/or modify it under the terms of the GNU Lesser General   ////
823
//// Public License as published by the Free Software Foundation; ////
824
//// either version 2.1 of the License, or (at your option) any   ////
825
//// later version.                                               ////
826
////                                                              ////
827
//// This source is distributed in the hope that it will be       ////
828
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
829
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
830
//// PURPOSE.  See the GNU Lesser General Public License for more ////
831
//// details.                                                     ////
832
////                                                              ////
833
//// You should have received a copy of the GNU Lesser General    ////
834
//// Public License along with this source; if not, download it   ////
835
//// from http://www.opencores.org/lgpl.shtml                     ////
836
////                                                              ////
837
//////////////////////////////////////////////////////////////////////
838
 
839 40 unneback
`ifdef DFF
840
`define MODULE dff
841
module `BASE`MODULE ( d, q, clk, rst);
842
`undef MODULE
843 6 unneback
        parameter width = 1;
844
        parameter reset_value = 0;
845
 
846
        input [width-1:0] d;
847
        input clk, rst;
848
        output reg [width-1:0] q;
849
 
850
        always @ (posedge clk or posedge rst)
851
        if (rst)
852
                q <= reset_value;
853
        else
854
                q <= d;
855
 
856
endmodule
857 40 unneback
`endif
858 6 unneback
 
859 40 unneback
`ifdef DFF_ARRAY
860
`define MODULE dff_array
861
module `BASE`MODULE ( d, q, clk, rst);
862
`undef MODULE
863 6 unneback
 
864
        parameter width = 1;
865
        parameter depth = 2;
866
        parameter reset_value = 1'b0;
867
 
868
        input [width-1:0] d;
869
        input clk, rst;
870
        output [width-1:0] q;
871
        reg  [0:depth-1] q_tmp [width-1:0];
872
        integer i;
873
        always @ (posedge clk or posedge rst)
874
        if (rst) begin
875
            for (i=0;i<depth;i=i+1)
876
                q_tmp[i] <= {width{reset_value}};
877
        end else begin
878
            q_tmp[0] <= d;
879
            for (i=1;i<depth;i=i+1)
880
                q_tmp[i] <= q_tmp[i-1];
881
        end
882
 
883
    assign q = q_tmp[depth-1];
884
 
885
endmodule
886 40 unneback
`endif
887 6 unneback
 
888 40 unneback
`ifdef DFF_CE
889
`define MODULE dff_ce
890
module `BASE`MODULE ( d, ce, q, clk, rst);
891
`undef MODULE
892 6 unneback
 
893
        parameter width = 1;
894
        parameter reset_value = 0;
895
 
896
        input [width-1:0] d;
897
        input ce, clk, rst;
898
        output reg [width-1:0] q;
899
 
900
        always @ (posedge clk or posedge rst)
901
        if (rst)
902
                q <= reset_value;
903
        else
904
                if (ce)
905
                        q <= d;
906
 
907
endmodule
908 40 unneback
`endif
909 6 unneback
 
910 40 unneback
`ifdef DFF_CE_CLEAR
911
`define MODULE dff_ce_clear
912
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
913
`undef MODULE
914 8 unneback
 
915
        parameter width = 1;
916
        parameter reset_value = 0;
917
 
918
        input [width-1:0] d;
919 10 unneback
        input ce, clear, clk, rst;
920 8 unneback
        output reg [width-1:0] q;
921
 
922
        always @ (posedge clk or posedge rst)
923
        if (rst)
924
            q <= reset_value;
925
        else
926
            if (ce)
927
                if (clear)
928
                    q <= {width{1'b0}};
929
                else
930
                    q <= d;
931
 
932
endmodule
933 40 unneback
`endif
934 8 unneback
 
935 40 unneback
`ifdef DF_CE_SET
936
`define MODULE dff_ce_set
937
module `BASE`MODULE ( d, ce, set, q, clk, rst);
938
`undef MODULE
939 24 unneback
 
940
        parameter width = 1;
941
        parameter reset_value = 0;
942
 
943
        input [width-1:0] d;
944
        input ce, set, clk, rst;
945
        output reg [width-1:0] q;
946
 
947
        always @ (posedge clk or posedge rst)
948
        if (rst)
949
            q <= reset_value;
950
        else
951
            if (ce)
952
                if (set)
953
                    q <= {width{1'b1}};
954
                else
955
                    q <= d;
956
 
957
endmodule
958 40 unneback
`endif
959 24 unneback
 
960 40 unneback
`ifdef SPR
961
`define MODULE spr
962
module `BASE`MODULE ( sp, r, q, clk, rst);
963
`undef MODULE
964
 
965 64 unneback
        //parameter width = 1;
966
        parameter reset_value = 1'b0;
967 29 unneback
 
968
        input sp, r;
969
        output reg q;
970
        input clk, rst;
971
 
972
        always @ (posedge clk or posedge rst)
973
        if (rst)
974
            q <= reset_value;
975
        else
976
            if (sp)
977
                q <= 1'b1;
978
            else if (r)
979
                q <= 1'b0;
980
 
981
endmodule
982 40 unneback
`endif
983 29 unneback
 
984 40 unneback
`ifdef SRP
985
`define MODULE srp
986
module `BASE`MODULE ( s, rp, q, clk, rst);
987
`undef MODULE
988
 
989 29 unneback
        parameter width = 1;
990
        parameter reset_value = 0;
991
 
992
        input s, rp;
993
        output reg q;
994
        input clk, rst;
995
 
996
        always @ (posedge clk or posedge rst)
997
        if (rst)
998
            q <= reset_value;
999
        else
1000
            if (rp)
1001
                q <= 1'b0;
1002
            else if (s)
1003
                q <= 1'b1;
1004
 
1005
endmodule
1006 40 unneback
`endif
1007 29 unneback
 
1008 40 unneback
`ifdef ALTERA
1009 29 unneback
 
1010 40 unneback
`ifdef DFF_SR
1011 6 unneback
// megafunction wizard: %LPM_FF%
1012
// GENERATION: STANDARD
1013
// VERSION: WM1.0
1014
// MODULE: lpm_ff 
1015
 
1016
// ============================================================
1017
// File Name: dff_sr.v
1018
// Megafunction Name(s):
1019
//                      lpm_ff
1020
//
1021
// Simulation Library Files(s):
1022
//                      lpm
1023
// ============================================================
1024
// ************************************************************
1025
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
1026
//
1027
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
1028
// ************************************************************
1029
 
1030
 
1031
//Copyright (C) 1991-2010 Altera Corporation
1032
//Your use of Altera Corporation's design tools, logic functions 
1033
//and other software and tools, and its AMPP partner logic 
1034
//functions, and any output files from any of the foregoing 
1035
//(including device programming or simulation files), and any 
1036
//associated documentation or information are expressly subject 
1037
//to the terms and conditions of the Altera Program License 
1038
//Subscription Agreement, Altera MegaCore Function License 
1039
//Agreement, or other applicable license agreement, including, 
1040
//without limitation, that your use is for the sole purpose of 
1041
//programming logic devices manufactured by Altera and sold by 
1042
//Altera or its authorized distributors.  Please refer to the 
1043
//applicable agreement for further details.
1044
 
1045
 
1046
// synopsys translate_off
1047
`timescale 1 ps / 1 ps
1048
// synopsys translate_on
1049 40 unneback
`define MODULE dff_sr
1050
module `BASE`MODULE (
1051
`undef MODULE
1052
 
1053 6 unneback
        aclr,
1054
        aset,
1055
        clock,
1056
        data,
1057
        q);
1058
 
1059
        input     aclr;
1060
        input     aset;
1061
        input     clock;
1062
        input     data;
1063
        output    q;
1064
 
1065
        wire [0:0] sub_wire0;
1066
        wire [0:0] sub_wire1 = sub_wire0[0:0];
1067
        wire  q = sub_wire1;
1068
        wire  sub_wire2 = data;
1069
        wire  sub_wire3 = sub_wire2;
1070
 
1071
        lpm_ff  lpm_ff_component (
1072
                                .aclr (aclr),
1073
                                .clock (clock),
1074
                                .data (sub_wire3),
1075
                                .aset (aset),
1076
                                .q (sub_wire0)
1077
                                // synopsys translate_off
1078
                                ,
1079
                                .aload (),
1080
                                .enable (),
1081
                                .sclr (),
1082
                                .sload (),
1083
                                .sset ()
1084
                                // synopsys translate_on
1085
                                );
1086
        defparam
1087
                lpm_ff_component.lpm_fftype = "DFF",
1088
                lpm_ff_component.lpm_type = "LPM_FF",
1089
                lpm_ff_component.lpm_width = 1;
1090
 
1091
 
1092
endmodule
1093
 
1094
// ============================================================
1095
// CNX file retrieval info
1096
// ============================================================
1097
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1098
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1099
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1100
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1101
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1102
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1103
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1104
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1105
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1106
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1107
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1108
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1109
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1110
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1111
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1112
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1113
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1114
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1115
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1116
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1117
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1118
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1119
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1120
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1121
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1122
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1123
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1124
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1125
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1126
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1127
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1128
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1129
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1130
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1131
// Retrieval info: LIB_FILE: lpm
1132 40 unneback
`endif
1133 6 unneback
 
1134
`else
1135
 
1136 40 unneback
`ifdef DFF_SR
1137
`define MODULE dff_sr
1138
module `BASE`MODULE ( aclr, aset, clock, data, q);
1139
`undef MODULE
1140 6 unneback
 
1141
    input         aclr;
1142
    input         aset;
1143
    input         clock;
1144
    input         data;
1145
    output reg    q;
1146
 
1147
   always @ (posedge clock or posedge aclr or posedge aset)
1148
     if (aclr)
1149
       q <= 1'b0;
1150
     else if (aset)
1151
       q <= 1'b1;
1152
     else
1153
       q <= data;
1154
 
1155
endmodule
1156 40 unneback
`endif
1157 6 unneback
 
1158
`endif
1159
 
1160
// LATCH
1161
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1162
`ifdef ALTERA
1163 40 unneback
 
1164
`ifdef LATCH
1165
`define MODULE latch
1166
module `BASE`MODULE ( d, le, q, clk);
1167
`undef MODULE
1168 6 unneback
input d, le;
1169
output q;
1170
input clk;
1171
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1172
endmodule
1173 40 unneback
`endif
1174
 
1175 6 unneback
`else
1176 40 unneback
 
1177
`ifdef LATCH
1178
`define MODULE latch
1179
module `BASE`MODULE ( d, le, q, clk);
1180
`undef MODULE
1181 6 unneback
input d, le;
1182 48 unneback
input clk;
1183
always @ (le or d)
1184 60 unneback
if (le)
1185 48 unneback
    d <= q;
1186 6 unneback
endmodule
1187 15 unneback
`endif
1188
 
1189 40 unneback
`endif
1190
 
1191
`ifdef SHREG
1192
`define MODULE shreg
1193
module `BASE`MODULE ( d, q, clk, rst);
1194
`undef MODULE
1195
 
1196 17 unneback
parameter depth = 10;
1197
input d;
1198
output q;
1199
input clk, rst;
1200
 
1201
reg [1:depth] dffs;
1202
 
1203
always @ (posedge clk or posedge rst)
1204
if (rst)
1205
    dffs <= {depth{1'b0}};
1206
else
1207
    dffs <= {d,dffs[1:depth-1]};
1208
assign q = dffs[depth];
1209
endmodule
1210 40 unneback
`endif
1211 17 unneback
 
1212 40 unneback
`ifdef SHREG_CE
1213
`define MODULE shreg_ce
1214
module `BASE`MODULE ( d, ce, q, clk, rst);
1215
`undef MODULE
1216 17 unneback
parameter depth = 10;
1217
input d, ce;
1218
output q;
1219
input clk, rst;
1220
 
1221
reg [1:depth] dffs;
1222
 
1223
always @ (posedge clk or posedge rst)
1224
if (rst)
1225
    dffs <= {depth{1'b0}};
1226
else
1227
    if (ce)
1228
        dffs <= {d,dffs[1:depth-1]};
1229
assign q = dffs[depth];
1230
endmodule
1231 40 unneback
`endif
1232 17 unneback
 
1233 40 unneback
`ifdef DELAY
1234
`define MODULE delay
1235
module `BASE`MODULE ( d, q, clk, rst);
1236
`undef MODULE
1237 15 unneback
parameter depth = 10;
1238
input d;
1239
output q;
1240
input clk, rst;
1241
 
1242
reg [1:depth] dffs;
1243
 
1244
always @ (posedge clk or posedge rst)
1245
if (rst)
1246
    dffs <= {depth{1'b0}};
1247
else
1248
    dffs <= {d,dffs[1:depth-1]};
1249
assign q = dffs[depth];
1250 17 unneback
endmodule
1251 40 unneback
`endif
1252 17 unneback
 
1253 40 unneback
`ifdef DELAY_EMPTYFLAG
1254
`define MODULE delay_emptyflag
1255 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1256 40 unneback
`undef MODULE
1257 17 unneback
parameter depth = 10;
1258
input d;
1259
output q, emptyflag;
1260
input clk, rst;
1261
 
1262
reg [1:depth] dffs;
1263
 
1264
always @ (posedge clk or posedge rst)
1265
if (rst)
1266
    dffs <= {depth{1'b0}};
1267
else
1268
    dffs <= {d,dffs[1:depth-1]};
1269
assign q = dffs[depth];
1270
assign emptyflag = !(|dffs);
1271
endmodule
1272 40 unneback
`endif
1273 75 unneback
 
1274 94 unneback
`ifdef PULSE2TOGGLE
1275 98 unneback
`define MODULE pulse2toggle
1276
module `BASE`MODULE ( pl, q, clk, rst);
1277 75 unneback
`undef MODULE
1278 94 unneback
input pl;
1279 98 unneback
output reg q;
1280 94 unneback
input clk, rst;
1281
always @ (posedge clk or posedge rst)
1282 75 unneback
if (rst)
1283 94 unneback
    q <= 1'b0;
1284 75 unneback
else
1285 94 unneback
    q <= pl ^ q;
1286
endmodule
1287
`endif
1288 75 unneback
 
1289 94 unneback
`ifdef TOGGLE2PULSE
1290 98 unneback
`define MODULE toggle2pulse
1291 94 unneback
module `BASE`MODULE (d, pl, clk, rst);
1292 97 unneback
`undef MODULE
1293 94 unneback
input d;
1294
output pl;
1295
input clk, rst;
1296
reg dff;
1297
always @ (posedge clk or posedge rst)
1298
if (rst)
1299
    dff <= 1'b0;
1300 75 unneback
else
1301 94 unneback
    dff <= d;
1302 98 unneback
assign pl = d ^ dff;
1303 94 unneback
endmodule
1304
`endif
1305 75 unneback
 
1306 94 unneback
`ifdef SYNCHRONIZER
1307
`define MODULE synchronizer
1308
module `BASE`MODULE (d, q, clk, rst);
1309
`undef MODULE
1310
input d;
1311
output reg q;
1312 116 unneback
input clk, rst;
1313 94 unneback
reg dff;
1314
always @ (posedge clk or posedge rst)
1315
if (rst)
1316 100 unneback
    {q,dff} <= 2'b00;
1317 75 unneback
else
1318 100 unneback
    {q,dff} <= {dff,d};
1319 94 unneback
endmodule
1320
`endif
1321 75 unneback
 
1322 94 unneback
`ifdef CDC
1323
`define MODULE cdc
1324 97 unneback
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1325 94 unneback
`undef MODULE
1326
input start_pl;
1327
output take_it_pl;
1328
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1329
output got_it_pl;
1330
input clk_src, rst_src;
1331
input clk_dst, rst_dst;
1332
wire take_it_tg, take_it_tg_sync;
1333
wire got_it_tg, got_it_tg_sync;
1334
// src -> dst
1335
`define MODULE pulse2toggle
1336
`BASE`MODULE p2t0 (
1337
`undef MODULE
1338
    .pl(start_pl),
1339
    .q(take_it_tg),
1340
    .clk(clk_src),
1341
    .rst(rst_src));
1342 75 unneback
 
1343 94 unneback
`define MODULE synchronizer
1344
`BASE`MODULE sync0 (
1345
`undef MODULE
1346
    .d(take_it_tg),
1347
    .q(take_it_tg_sync),
1348
    .clk(clk_dst),
1349
    .rst(rst_dst));
1350
 
1351
`define MODULE toggle2pulse
1352
`BASE`MODULE t2p0 (
1353
`undef MODULE
1354 100 unneback
    .d(take_it_tg_sync),
1355 94 unneback
    .pl(take_it_pl),
1356
    .clk(clk_dst),
1357
    .rst(rst_dst));
1358
 
1359
// dst -> src
1360
`define MODULE pulse2toggle
1361 98 unneback
`BASE`MODULE p2t1 (
1362 94 unneback
`undef MODULE
1363
    .pl(take_it_grant_pl),
1364
    .q(got_it_tg),
1365
    .clk(clk_dst),
1366
    .rst(rst_dst));
1367
 
1368
`define MODULE synchronizer
1369
`BASE`MODULE sync1 (
1370
`undef MODULE
1371
    .d(got_it_tg),
1372
    .q(got_it_tg_sync),
1373
    .clk(clk_src),
1374
    .rst(rst_src));
1375
 
1376
`define MODULE toggle2pulse
1377
`BASE`MODULE t2p1 (
1378
`undef MODULE
1379 100 unneback
    .d(got_it_tg_sync),
1380 94 unneback
    .pl(got_it_pl),
1381
    .clk(clk_src),
1382
    .rst(rst_src));
1383
 
1384 75 unneback
endmodule
1385
`endif
1386 17 unneback
//////////////////////////////////////////////////////////////////////
1387 6 unneback
////                                                              ////
1388 18 unneback
////  Logic functions                                             ////
1389
////                                                              ////
1390
////  Description                                                 ////
1391
////  Logic functions such as multiplexers                        ////
1392
////                                                              ////
1393
////                                                              ////
1394
////  To Do:                                                      ////
1395
////   -                                                          ////
1396
////                                                              ////
1397
////  Author(s):                                                  ////
1398
////      - Michael Unneback, unneback@opencores.org              ////
1399
////        ORSoC AB                                              ////
1400
////                                                              ////
1401
//////////////////////////////////////////////////////////////////////
1402
////                                                              ////
1403
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1404
////                                                              ////
1405
//// This source file may be used and distributed without         ////
1406
//// restriction provided that this copyright statement is not    ////
1407
//// removed from the file and that any derivative work contains  ////
1408
//// the original copyright notice and the associated disclaimer. ////
1409
////                                                              ////
1410
//// This source file is free software; you can redistribute it   ////
1411
//// and/or modify it under the terms of the GNU Lesser General   ////
1412
//// Public License as published by the Free Software Foundation; ////
1413
//// either version 2.1 of the License, or (at your option) any   ////
1414
//// later version.                                               ////
1415
////                                                              ////
1416
//// This source is distributed in the hope that it will be       ////
1417
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1418
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1419
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1420
//// details.                                                     ////
1421
////                                                              ////
1422
//// You should have received a copy of the GNU Lesser General    ////
1423
//// Public License along with this source; if not, download it   ////
1424
//// from http://www.opencores.org/lgpl.shtml                     ////
1425
////                                                              ////
1426
//////////////////////////////////////////////////////////////////////
1427 40 unneback
`ifdef MUX_ANDOR
1428
`define MODULE mux_andor
1429
module `BASE`MODULE ( a, sel, dout);
1430
`undef MODULE
1431 36 unneback
 
1432
parameter width = 32;
1433
parameter nr_of_ports = 4;
1434
 
1435
input [nr_of_ports*width-1:0] a;
1436
input [nr_of_ports-1:0] sel;
1437
output reg [width-1:0] dout;
1438
 
1439 38 unneback
integer i,j;
1440
 
1441 36 unneback
always @ (a, sel)
1442
begin
1443
    dout = a[width-1:0] & {width{sel[0]}};
1444 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1445
        for (j=0;j<width;j=j+1)
1446
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1447 36 unneback
end
1448
 
1449
endmodule
1450 40 unneback
`endif
1451 36 unneback
 
1452 40 unneback
`ifdef MUX2_ANDOR
1453
`define MODULE mux2_andor
1454
module `BASE`MODULE ( a1, a0, sel, dout);
1455
`undef MODULE
1456 18 unneback
 
1457 34 unneback
parameter width = 32;
1458 35 unneback
localparam nr_of_ports = 2;
1459 34 unneback
input [width-1:0] a1, a0;
1460
input [nr_of_ports-1:0] sel;
1461
output [width-1:0] dout;
1462
 
1463 40 unneback
`define MODULE mux_andor
1464
`BASE`MODULE
1465 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1466 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1467 40 unneback
`undef MODULE
1468
 
1469 34 unneback
endmodule
1470 40 unneback
`endif
1471 34 unneback
 
1472 40 unneback
`ifdef MUX3_ANDOR
1473
`define MODULE mux3_andor
1474
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1475
`undef MODULE
1476 34 unneback
 
1477
parameter width = 32;
1478 35 unneback
localparam nr_of_ports = 3;
1479 34 unneback
input [width-1:0] a2, a1, a0;
1480
input [nr_of_ports-1:0] sel;
1481
output [width-1:0] dout;
1482
 
1483 40 unneback
`define MODULE mux_andor
1484
`BASE`MODULE
1485 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1486 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1487 40 unneback
`undef MODULE
1488 34 unneback
endmodule
1489 40 unneback
`endif
1490 34 unneback
 
1491 40 unneback
`ifdef MUX4_ANDOR
1492
`define MODULE mux4_andor
1493
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1494
`undef MODULE
1495 18 unneback
 
1496
parameter width = 32;
1497 35 unneback
localparam nr_of_ports = 4;
1498 18 unneback
input [width-1:0] a3, a2, a1, a0;
1499
input [nr_of_ports-1:0] sel;
1500 22 unneback
output [width-1:0] dout;
1501 18 unneback
 
1502 40 unneback
`define MODULE mux_andor
1503
`BASE`MODULE
1504 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1505 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1506 40 unneback
`undef MODULE
1507 18 unneback
 
1508
endmodule
1509 40 unneback
`endif
1510 18 unneback
 
1511 40 unneback
`ifdef MUX5_ANDOR
1512
`define MODULE mux5_andor
1513
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1514
`undef MODULE
1515 18 unneback
 
1516
parameter width = 32;
1517 35 unneback
localparam nr_of_ports = 5;
1518 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1519
input [nr_of_ports-1:0] sel;
1520 22 unneback
output [width-1:0] dout;
1521 18 unneback
 
1522 40 unneback
`define MODULE mux_andor
1523
`BASE`MODULE
1524 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1525 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1526 40 unneback
`undef MODULE
1527 18 unneback
 
1528
endmodule
1529 40 unneback
`endif
1530 18 unneback
 
1531 40 unneback
`ifdef MUX6_ANDOR
1532
`define MODULE mux6_andor
1533
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1534
`undef MODULE
1535 18 unneback
 
1536
parameter width = 32;
1537 35 unneback
localparam nr_of_ports = 6;
1538 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1539
input [nr_of_ports-1:0] sel;
1540 22 unneback
output [width-1:0] dout;
1541 18 unneback
 
1542 40 unneback
`define MODULE mux_andor
1543
`BASE`MODULE
1544 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1545 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1546 40 unneback
`undef MODULE
1547 18 unneback
 
1548
endmodule
1549 40 unneback
`endif
1550 43 unneback
 
1551
`ifdef PARITY
1552
 
1553
`define MODULE parity_generate
1554
module `BASE`MODULE (data, parity);
1555
`undef MODULE
1556
parameter word_size = 32;
1557
parameter chunk_size = 8;
1558
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1559
input [word_size-1:0] data;
1560
output reg [word_size/chunk_size-1:0] parity;
1561
integer i,j;
1562
always @ (data)
1563
for (i=0;i<word_size/chunk_size;i=i+1) begin
1564
    parity[i] = parity_type;
1565
    for (j=0;j<chunk_size;j=j+1) begin
1566 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1567 43 unneback
    end
1568
end
1569
endmodule
1570
 
1571
`define MODULE parity_check
1572
module `BASE`MODULE( data, parity, parity_error);
1573
`undef MODULE
1574
parameter word_size = 32;
1575
parameter chunk_size = 8;
1576
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1577
input [word_size-1:0] data;
1578
input [word_size/chunk_size-1:0] parity;
1579
output parity_error;
1580 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1581 43 unneback
integer i,j;
1582
always @ (data or parity)
1583
for (i=0;i<word_size/chunk_size;i=i+1) begin
1584
    error_flag[i] = parity[i] ^ parity_type;
1585
    for (j=0;j<chunk_size;j=j+1) begin
1586 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1587 43 unneback
    end
1588
end
1589
assign parity_error = |error_flag;
1590
endmodule
1591
 
1592 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1593
////                                                              ////
1594
////  IO functions                                                ////
1595
////                                                              ////
1596
////  Description                                                 ////
1597
////  IO functions such as IOB flip-flops                         ////
1598
////                                                              ////
1599
////                                                              ////
1600
////  To Do:                                                      ////
1601
////   -                                                          ////
1602
////                                                              ////
1603
////  Author(s):                                                  ////
1604
////      - Michael Unneback, unneback@opencores.org              ////
1605
////        ORSoC AB                                              ////
1606
////                                                              ////
1607 18 unneback
//////////////////////////////////////////////////////////////////////
1608
////                                                              ////
1609 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1610
////                                                              ////
1611
//// This source file may be used and distributed without         ////
1612
//// restriction provided that this copyright statement is not    ////
1613
//// removed from the file and that any derivative work contains  ////
1614
//// the original copyright notice and the associated disclaimer. ////
1615
////                                                              ////
1616
//// This source file is free software; you can redistribute it   ////
1617
//// and/or modify it under the terms of the GNU Lesser General   ////
1618
//// Public License as published by the Free Software Foundation; ////
1619
//// either version 2.1 of the License, or (at your option) any   ////
1620
//// later version.                                               ////
1621
////                                                              ////
1622
//// This source is distributed in the hope that it will be       ////
1623
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1624
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1625
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1626
//// details.                                                     ////
1627
////                                                              ////
1628
//// You should have received a copy of the GNU Lesser General    ////
1629
//// Public License along with this source; if not, download it   ////
1630
//// from http://www.opencores.org/lgpl.shtml                     ////
1631
////                                                              ////
1632
//////////////////////////////////////////////////////////////////////
1633 136 unneback
`ifdef O_DFF
1634 45 unneback
`timescale 1ns/1ns
1635 44 unneback
`define MODULE o_dff
1636
module `BASE`MODULE (d_i, o_pad, clk, rst);
1637
`undef MODULE
1638
parameter width = 1;
1639 45 unneback
parameter reset_value = {width{1'b0}};
1640
input  [width-1:0]  d_i;
1641 44 unneback
output [width-1:0] o_pad;
1642
input clk, rst;
1643
wire [width-1:0] d_i_int `SYN_KEEP;
1644 45 unneback
reg  [width-1:0] o_pad_int;
1645 44 unneback
assign d_i_int = d_i;
1646
genvar i;
1647 45 unneback
generate
1648 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
1649 44 unneback
    always @ (posedge clk or posedge rst)
1650
    if (rst)
1651 45 unneback
        o_pad_int[i] <= reset_value[i];
1652 44 unneback
    else
1653 45 unneback
        o_pad_int[i] <= d_i_int[i];
1654
    assign #1 o_pad[i] = o_pad_int[i];
1655 44 unneback
end
1656
endgenerate
1657
endmodule
1658
`endif
1659
 
1660 136 unneback
`ifdef IO_DFF_OE
1661 45 unneback
`timescale 1ns/1ns
1662 44 unneback
`define MODULE io_dff_oe
1663
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1664
`undef MODULE
1665
parameter width = 1;
1666
input  [width-1:0] d_o;
1667
output reg [width-1:0] d_i;
1668
input oe;
1669
inout [width-1:0] io_pad;
1670
input clk, rst;
1671
wire [width-1:0] oe_d `SYN_KEEP;
1672
reg [width-1:0] oe_q;
1673
reg [width-1:0] d_o_q;
1674
assign oe_d = {width{oe}};
1675
genvar i;
1676
generate
1677 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
1678 44 unneback
    always @ (posedge clk or posedge rst)
1679
    if (rst)
1680
        oe_q[i] <= 1'b0;
1681
    else
1682
        oe_q[i] <= oe_d[i];
1683
    always @ (posedge clk or posedge rst)
1684
    if (rst)
1685
        d_o_q[i] <= 1'b0;
1686
    else
1687
        d_o_q[i] <= d_o[i];
1688
    always @ (posedge clk or posedge rst)
1689
    if (rst)
1690
        d_i[i] <= 1'b0;
1691
    else
1692
        d_i[i] <= io_pad[i];
1693 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1694 44 unneback
end
1695
endgenerate
1696
endmodule
1697
`endif
1698 136 unneback
 
1699
`ifdef O_DDR
1700
`ifdef ALTERA
1701
`define MODULE o_ddr
1702
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
1703
`undef MODULE
1704
parameter width = 1;
1705
input  [width-1:0] d_h_i, d_l_i;
1706
output [width-1:0] o_pad;
1707
input clk, rst;
1708
genvar i;
1709
generate
1710
for (i=0;i<width;i=i+1) begin : ddr
1711
    ddio_out ddio_out0( .aclr(rst), .datain_h(d_h_i[i]), .datain_l(d_l_i[i]), .outclock(clk), .dataout(o_pad[i]) );
1712
end
1713
endgenerate
1714
endmodule
1715
`else
1716
`define MODULE o_ddr
1717
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
1718
`undef MODULE
1719
parameter width = 1;
1720
input  [width-1:0] d_h_i, d_l_i;
1721
output [width-1:0] o_pad;
1722
input clk, rst;
1723
reg [width-1:0] ff1;
1724
reg [width-1:0] ff2;
1725
genvar i;
1726
generate
1727
for (i=0;i<width;i=i+1) begin : ddr
1728
    always @ (posedge clk or posedge rst)
1729
    if (rst)
1730
        ff1[i] <= 1'b0;
1731
    else
1732
        ff1[i] <= d_h_i[i];
1733
    always @ (posedge clk or posedge rst)
1734
    if (rst)
1735
        ff2[i] <= 1'b0;
1736
    else
1737
        ff2[i] <= d_l_i[i];
1738
    assign o_pad = (clk) ? ff1 : ff2;
1739
end
1740
endgenerate
1741
endmodule
1742
`endif
1743
`endif
1744
 
1745
`ifdef O_CLK
1746
`define MODULE o_clk
1747
module `BASE`MODULE ( clk_o_pad, clk, rst);
1748
`undef MODULE
1749
input clk, rst;
1750
output clk_o_pad;
1751
`define MODULE o_ddr
1752
`BASE`MODULE o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
1753
`undef MODULE
1754
endmodule
1755
`endif`ifdef CNT_BIN
1756 44 unneback
//////////////////////////////////////////////////////////////////////
1757
////                                                              ////
1758 6 unneback
////  Versatile counter                                           ////
1759
////                                                              ////
1760
////  Description                                                 ////
1761
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1762
////  counter                                                     ////
1763
////                                                              ////
1764
////  To Do:                                                      ////
1765
////   - add LFSR with more taps                                  ////
1766
////                                                              ////
1767
////  Author(s):                                                  ////
1768
////      - Michael Unneback, unneback@opencores.org              ////
1769
////        ORSoC AB                                              ////
1770
////                                                              ////
1771
//////////////////////////////////////////////////////////////////////
1772
////                                                              ////
1773
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1774
////                                                              ////
1775
//// This source file may be used and distributed without         ////
1776
//// restriction provided that this copyright statement is not    ////
1777
//// removed from the file and that any derivative work contains  ////
1778
//// the original copyright notice and the associated disclaimer. ////
1779
////                                                              ////
1780
//// This source file is free software; you can redistribute it   ////
1781
//// and/or modify it under the terms of the GNU Lesser General   ////
1782
//// Public License as published by the Free Software Foundation; ////
1783
//// either version 2.1 of the License, or (at your option) any   ////
1784
//// later version.                                               ////
1785
////                                                              ////
1786
//// This source is distributed in the hope that it will be       ////
1787
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1788
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1789
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1790
//// details.                                                     ////
1791
////                                                              ////
1792
//// You should have received a copy of the GNU Lesser General    ////
1793
//// Public License along with this source; if not, download it   ////
1794
//// from http://www.opencores.org/lgpl.shtml                     ////
1795
////                                                              ////
1796
//////////////////////////////////////////////////////////////////////
1797
 
1798
// binary counter
1799 22 unneback
 
1800 40 unneback
`define MODULE cnt_bin
1801
module `BASE`MODULE (
1802
`undef MODULE
1803
 q, rst, clk);
1804
 
1805 22 unneback
   parameter length = 4;
1806
   output [length:1] q;
1807
   input rst;
1808
   input clk;
1809
 
1810
   parameter clear_value = 0;
1811
   parameter set_value = 1;
1812
   parameter wrap_value = 0;
1813
   parameter level1_value = 15;
1814
 
1815
   reg  [length:1] qi;
1816
   wire [length:1] q_next;
1817
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1818
 
1819
   always @ (posedge clk or posedge rst)
1820
     if (rst)
1821
       qi <= {length{1'b0}};
1822
     else
1823
       qi <= q_next;
1824
 
1825
   assign q = qi;
1826
 
1827
endmodule
1828 40 unneback
`endif
1829
`ifdef CNT_BIN_CLEAR
1830 22 unneback
//////////////////////////////////////////////////////////////////////
1831
////                                                              ////
1832
////  Versatile counter                                           ////
1833
////                                                              ////
1834
////  Description                                                 ////
1835
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1836
////  counter                                                     ////
1837
////                                                              ////
1838
////  To Do:                                                      ////
1839
////   - add LFSR with more taps                                  ////
1840
////                                                              ////
1841
////  Author(s):                                                  ////
1842
////      - Michael Unneback, unneback@opencores.org              ////
1843
////        ORSoC AB                                              ////
1844
////                                                              ////
1845
//////////////////////////////////////////////////////////////////////
1846
////                                                              ////
1847
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1848
////                                                              ////
1849
//// This source file may be used and distributed without         ////
1850
//// restriction provided that this copyright statement is not    ////
1851
//// removed from the file and that any derivative work contains  ////
1852
//// the original copyright notice and the associated disclaimer. ////
1853
////                                                              ////
1854
//// This source file is free software; you can redistribute it   ////
1855
//// and/or modify it under the terms of the GNU Lesser General   ////
1856
//// Public License as published by the Free Software Foundation; ////
1857
//// either version 2.1 of the License, or (at your option) any   ////
1858
//// later version.                                               ////
1859
////                                                              ////
1860
//// This source is distributed in the hope that it will be       ////
1861
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1862
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1863
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1864
//// details.                                                     ////
1865
////                                                              ////
1866
//// You should have received a copy of the GNU Lesser General    ////
1867
//// Public License along with this source; if not, download it   ////
1868
//// from http://www.opencores.org/lgpl.shtml                     ////
1869
////                                                              ////
1870
//////////////////////////////////////////////////////////////////////
1871
 
1872
// binary counter
1873
 
1874 40 unneback
`define MODULE cnt_bin_clear
1875
module `BASE`MODULE (
1876
`undef MODULE
1877
 clear, q, rst, clk);
1878
 
1879 22 unneback
   parameter length = 4;
1880
   input clear;
1881
   output [length:1] q;
1882
   input rst;
1883
   input clk;
1884
 
1885
   parameter clear_value = 0;
1886
   parameter set_value = 1;
1887
   parameter wrap_value = 0;
1888
   parameter level1_value = 15;
1889
 
1890
   reg  [length:1] qi;
1891
   wire [length:1] q_next;
1892
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1893
 
1894
   always @ (posedge clk or posedge rst)
1895
     if (rst)
1896
       qi <= {length{1'b0}};
1897
     else
1898
       qi <= q_next;
1899
 
1900
   assign q = qi;
1901
 
1902
endmodule
1903 40 unneback
`endif
1904
`ifdef CNT_BIN_CE
1905 22 unneback
//////////////////////////////////////////////////////////////////////
1906
////                                                              ////
1907
////  Versatile counter                                           ////
1908
////                                                              ////
1909
////  Description                                                 ////
1910
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1911
////  counter                                                     ////
1912
////                                                              ////
1913
////  To Do:                                                      ////
1914
////   - add LFSR with more taps                                  ////
1915
////                                                              ////
1916
////  Author(s):                                                  ////
1917
////      - Michael Unneback, unneback@opencores.org              ////
1918
////        ORSoC AB                                              ////
1919
////                                                              ////
1920
//////////////////////////////////////////////////////////////////////
1921
////                                                              ////
1922
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1923
////                                                              ////
1924
//// This source file may be used and distributed without         ////
1925
//// restriction provided that this copyright statement is not    ////
1926
//// removed from the file and that any derivative work contains  ////
1927
//// the original copyright notice and the associated disclaimer. ////
1928
////                                                              ////
1929
//// This source file is free software; you can redistribute it   ////
1930
//// and/or modify it under the terms of the GNU Lesser General   ////
1931
//// Public License as published by the Free Software Foundation; ////
1932
//// either version 2.1 of the License, or (at your option) any   ////
1933
//// later version.                                               ////
1934
////                                                              ////
1935
//// This source is distributed in the hope that it will be       ////
1936
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1937
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1938
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1939
//// details.                                                     ////
1940
////                                                              ////
1941
//// You should have received a copy of the GNU Lesser General    ////
1942
//// Public License along with this source; if not, download it   ////
1943
//// from http://www.opencores.org/lgpl.shtml                     ////
1944
////                                                              ////
1945
//////////////////////////////////////////////////////////////////////
1946
 
1947
// binary counter
1948 6 unneback
 
1949 40 unneback
`define MODULE cnt_bin_ce
1950
module `BASE`MODULE (
1951
`undef MODULE
1952
 cke, q, rst, clk);
1953
 
1954 6 unneback
   parameter length = 4;
1955
   input cke;
1956
   output [length:1] q;
1957
   input rst;
1958
   input clk;
1959
 
1960
   parameter clear_value = 0;
1961
   parameter set_value = 1;
1962
   parameter wrap_value = 0;
1963
   parameter level1_value = 15;
1964
 
1965
   reg  [length:1] qi;
1966
   wire [length:1] q_next;
1967
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1968
 
1969
   always @ (posedge clk or posedge rst)
1970
     if (rst)
1971
       qi <= {length{1'b0}};
1972
     else
1973
     if (cke)
1974
       qi <= q_next;
1975
 
1976
   assign q = qi;
1977
 
1978
endmodule
1979 40 unneback
`endif
1980
`ifdef CNT_BIN_CE_CLEAR
1981 6 unneback
//////////////////////////////////////////////////////////////////////
1982
////                                                              ////
1983
////  Versatile counter                                           ////
1984
////                                                              ////
1985
////  Description                                                 ////
1986
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1987
////  counter                                                     ////
1988
////                                                              ////
1989
////  To Do:                                                      ////
1990
////   - add LFSR with more taps                                  ////
1991
////                                                              ////
1992
////  Author(s):                                                  ////
1993
////      - Michael Unneback, unneback@opencores.org              ////
1994
////        ORSoC AB                                              ////
1995
////                                                              ////
1996
//////////////////////////////////////////////////////////////////////
1997
////                                                              ////
1998
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1999
////                                                              ////
2000
//// This source file may be used and distributed without         ////
2001
//// restriction provided that this copyright statement is not    ////
2002
//// removed from the file and that any derivative work contains  ////
2003
//// the original copyright notice and the associated disclaimer. ////
2004
////                                                              ////
2005
//// This source file is free software; you can redistribute it   ////
2006
//// and/or modify it under the terms of the GNU Lesser General   ////
2007
//// Public License as published by the Free Software Foundation; ////
2008
//// either version 2.1 of the License, or (at your option) any   ////
2009
//// later version.                                               ////
2010
////                                                              ////
2011
//// This source is distributed in the hope that it will be       ////
2012
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2013
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2014
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2015
//// details.                                                     ////
2016
////                                                              ////
2017
//// You should have received a copy of the GNU Lesser General    ////
2018
//// Public License along with this source; if not, download it   ////
2019
//// from http://www.opencores.org/lgpl.shtml                     ////
2020
////                                                              ////
2021
//////////////////////////////////////////////////////////////////////
2022
 
2023
// binary counter
2024
 
2025 40 unneback
`define MODULE cnt_bin_ce_clear
2026
module `BASE`MODULE (
2027
`undef MODULE
2028
 clear, cke, q, rst, clk);
2029
 
2030 6 unneback
   parameter length = 4;
2031
   input clear;
2032
   input cke;
2033
   output [length:1] q;
2034
   input rst;
2035
   input clk;
2036
 
2037
   parameter clear_value = 0;
2038
   parameter set_value = 1;
2039
   parameter wrap_value = 0;
2040
   parameter level1_value = 15;
2041
 
2042
   reg  [length:1] qi;
2043
   wire [length:1] q_next;
2044
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2045
 
2046
   always @ (posedge clk or posedge rst)
2047
     if (rst)
2048
       qi <= {length{1'b0}};
2049
     else
2050
     if (cke)
2051
       qi <= q_next;
2052
 
2053
   assign q = qi;
2054
 
2055
endmodule
2056 40 unneback
`endif
2057
`ifdef CNT_BIN_CE_CLEAR_L1_L2
2058 6 unneback
//////////////////////////////////////////////////////////////////////
2059
////                                                              ////
2060
////  Versatile counter                                           ////
2061
////                                                              ////
2062
////  Description                                                 ////
2063
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2064
////  counter                                                     ////
2065
////                                                              ////
2066
////  To Do:                                                      ////
2067
////   - add LFSR with more taps                                  ////
2068
////                                                              ////
2069
////  Author(s):                                                  ////
2070
////      - Michael Unneback, unneback@opencores.org              ////
2071
////        ORSoC AB                                              ////
2072
////                                                              ////
2073
//////////////////////////////////////////////////////////////////////
2074
////                                                              ////
2075
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2076
////                                                              ////
2077
//// This source file may be used and distributed without         ////
2078
//// restriction provided that this copyright statement is not    ////
2079
//// removed from the file and that any derivative work contains  ////
2080
//// the original copyright notice and the associated disclaimer. ////
2081
////                                                              ////
2082
//// This source file is free software; you can redistribute it   ////
2083
//// and/or modify it under the terms of the GNU Lesser General   ////
2084
//// Public License as published by the Free Software Foundation; ////
2085
//// either version 2.1 of the License, or (at your option) any   ////
2086
//// later version.                                               ////
2087
////                                                              ////
2088
//// This source is distributed in the hope that it will be       ////
2089
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2090
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2091
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2092
//// details.                                                     ////
2093
////                                                              ////
2094
//// You should have received a copy of the GNU Lesser General    ////
2095
//// Public License along with this source; if not, download it   ////
2096
//// from http://www.opencores.org/lgpl.shtml                     ////
2097
////                                                              ////
2098
//////////////////////////////////////////////////////////////////////
2099
 
2100
// binary counter
2101 29 unneback
 
2102 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
2103
module `BASE`MODULE (
2104
`undef MODULE
2105
 clear, cke, q, level1, level2, rst, clk);
2106
 
2107 29 unneback
   parameter length = 4;
2108
   input clear;
2109
   input cke;
2110
   output [length:1] q;
2111
   output reg level1;
2112
   output reg level2;
2113
   input rst;
2114
   input clk;
2115
 
2116
   parameter clear_value = 0;
2117
   parameter set_value = 1;
2118 30 unneback
   parameter wrap_value = 15;
2119
   parameter level1_value = 8;
2120
   parameter level2_value = 15;
2121 29 unneback
 
2122
   wire rew;
2123 30 unneback
   assign rew = 1'b0;
2124 29 unneback
   reg  [length:1] qi;
2125
   wire [length:1] q_next;
2126
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2127
 
2128
   always @ (posedge clk or posedge rst)
2129
     if (rst)
2130
       qi <= {length{1'b0}};
2131
     else
2132
     if (cke)
2133
       qi <= q_next;
2134
 
2135
   assign q = qi;
2136
 
2137
 
2138
    always @ (posedge clk or posedge rst)
2139
    if (rst)
2140
        level1 <= 1'b0;
2141
    else
2142
    if (cke)
2143
    if (clear)
2144
        level1 <= 1'b0;
2145
    else if (q_next == level1_value)
2146
        level1 <= 1'b1;
2147
    else if (qi == level1_value & rew)
2148
        level1 <= 1'b0;
2149
 
2150
    always @ (posedge clk or posedge rst)
2151
    if (rst)
2152
        level2 <= 1'b0;
2153
    else
2154
    if (cke)
2155
    if (clear)
2156
        level2 <= 1'b0;
2157
    else if (q_next == level2_value)
2158
        level2 <= 1'b1;
2159
    else if (qi == level2_value & rew)
2160
        level2 <= 1'b0;
2161
endmodule
2162 40 unneback
`endif
2163
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2164 29 unneback
//////////////////////////////////////////////////////////////////////
2165
////                                                              ////
2166
////  Versatile counter                                           ////
2167
////                                                              ////
2168
////  Description                                                 ////
2169
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2170
////  counter                                                     ////
2171
////                                                              ////
2172
////  To Do:                                                      ////
2173
////   - add LFSR with more taps                                  ////
2174
////                                                              ////
2175
////  Author(s):                                                  ////
2176
////      - Michael Unneback, unneback@opencores.org              ////
2177
////        ORSoC AB                                              ////
2178
////                                                              ////
2179
//////////////////////////////////////////////////////////////////////
2180
////                                                              ////
2181
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2182
////                                                              ////
2183
//// This source file may be used and distributed without         ////
2184
//// restriction provided that this copyright statement is not    ////
2185
//// removed from the file and that any derivative work contains  ////
2186
//// the original copyright notice and the associated disclaimer. ////
2187
////                                                              ////
2188
//// This source file is free software; you can redistribute it   ////
2189
//// and/or modify it under the terms of the GNU Lesser General   ////
2190
//// Public License as published by the Free Software Foundation; ////
2191
//// either version 2.1 of the License, or (at your option) any   ////
2192
//// later version.                                               ////
2193
////                                                              ////
2194
//// This source is distributed in the hope that it will be       ////
2195
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2196
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2197
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2198
//// details.                                                     ////
2199
////                                                              ////
2200
//// You should have received a copy of the GNU Lesser General    ////
2201
//// Public License along with this source; if not, download it   ////
2202
//// from http://www.opencores.org/lgpl.shtml                     ////
2203
////                                                              ////
2204
//////////////////////////////////////////////////////////////////////
2205
 
2206
// binary counter
2207 6 unneback
 
2208 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2209
module `BASE`MODULE (
2210
`undef MODULE
2211
 clear, set, cke, rew, q, rst, clk);
2212
 
2213 6 unneback
   parameter length = 4;
2214
   input clear;
2215
   input set;
2216
   input cke;
2217
   input rew;
2218
   output [length:1] q;
2219
   input rst;
2220
   input clk;
2221
 
2222
   parameter clear_value = 0;
2223
   parameter set_value = 1;
2224
   parameter wrap_value = 0;
2225
   parameter level1_value = 15;
2226
 
2227
   reg  [length:1] qi;
2228
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2229
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2230
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2231
   assign q_next = rew ? q_next_rew : q_next_fw;
2232
 
2233
   always @ (posedge clk or posedge rst)
2234
     if (rst)
2235
       qi <= {length{1'b0}};
2236
     else
2237
     if (cke)
2238
       qi <= q_next;
2239
 
2240
   assign q = qi;
2241
 
2242
endmodule
2243 40 unneback
`endif
2244
`ifdef CNT_BIN_CE_REW_L1
2245 6 unneback
//////////////////////////////////////////////////////////////////////
2246
////                                                              ////
2247
////  Versatile counter                                           ////
2248
////                                                              ////
2249
////  Description                                                 ////
2250
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2251
////  counter                                                     ////
2252
////                                                              ////
2253
////  To Do:                                                      ////
2254
////   - add LFSR with more taps                                  ////
2255
////                                                              ////
2256
////  Author(s):                                                  ////
2257
////      - Michael Unneback, unneback@opencores.org              ////
2258
////        ORSoC AB                                              ////
2259
////                                                              ////
2260
//////////////////////////////////////////////////////////////////////
2261
////                                                              ////
2262
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2263
////                                                              ////
2264
//// This source file may be used and distributed without         ////
2265
//// restriction provided that this copyright statement is not    ////
2266
//// removed from the file and that any derivative work contains  ////
2267
//// the original copyright notice and the associated disclaimer. ////
2268
////                                                              ////
2269
//// This source file is free software; you can redistribute it   ////
2270
//// and/or modify it under the terms of the GNU Lesser General   ////
2271
//// Public License as published by the Free Software Foundation; ////
2272
//// either version 2.1 of the License, or (at your option) any   ////
2273
//// later version.                                               ////
2274
////                                                              ////
2275
//// This source is distributed in the hope that it will be       ////
2276
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2277
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2278
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2279
//// details.                                                     ////
2280
////                                                              ////
2281
//// You should have received a copy of the GNU Lesser General    ////
2282
//// Public License along with this source; if not, download it   ////
2283
//// from http://www.opencores.org/lgpl.shtml                     ////
2284
////                                                              ////
2285
//////////////////////////////////////////////////////////////////////
2286
 
2287
// binary counter
2288
 
2289 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2290
module `BASE`MODULE (
2291
`undef MODULE
2292
 cke, rew, level1, rst, clk);
2293
 
2294 6 unneback
   parameter length = 4;
2295
   input cke;
2296
   input rew;
2297
   output reg level1;
2298
   input rst;
2299
   input clk;
2300
 
2301
   parameter clear_value = 0;
2302
   parameter set_value = 1;
2303
   parameter wrap_value = 1;
2304
   parameter level1_value = 15;
2305
 
2306 29 unneback
   wire clear;
2307 30 unneback
   assign clear = 1'b0;
2308 6 unneback
   reg  [length:1] qi;
2309
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2310
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2311
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2312
   assign q_next = rew ? q_next_rew : q_next_fw;
2313
 
2314
   always @ (posedge clk or posedge rst)
2315
     if (rst)
2316
       qi <= {length{1'b0}};
2317
     else
2318
     if (cke)
2319
       qi <= q_next;
2320
 
2321
 
2322
 
2323
    always @ (posedge clk or posedge rst)
2324
    if (rst)
2325
        level1 <= 1'b0;
2326
    else
2327
    if (cke)
2328 29 unneback
    if (clear)
2329
        level1 <= 1'b0;
2330
    else if (q_next == level1_value)
2331 6 unneback
        level1 <= 1'b1;
2332
    else if (qi == level1_value & rew)
2333
        level1 <= 1'b0;
2334
endmodule
2335 40 unneback
`endif
2336
`ifdef CNT_BIN_CE_REW_ZQ_L1
2337 6 unneback
//////////////////////////////////////////////////////////////////////
2338
////                                                              ////
2339
////  Versatile counter                                           ////
2340
////                                                              ////
2341
////  Description                                                 ////
2342
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2343
////  counter                                                     ////
2344
////                                                              ////
2345
////  To Do:                                                      ////
2346
////   - add LFSR with more taps                                  ////
2347
////                                                              ////
2348
////  Author(s):                                                  ////
2349
////      - Michael Unneback, unneback@opencores.org              ////
2350
////        ORSoC AB                                              ////
2351
////                                                              ////
2352
//////////////////////////////////////////////////////////////////////
2353
////                                                              ////
2354
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2355
////                                                              ////
2356
//// This source file may be used and distributed without         ////
2357
//// restriction provided that this copyright statement is not    ////
2358
//// removed from the file and that any derivative work contains  ////
2359
//// the original copyright notice and the associated disclaimer. ////
2360
////                                                              ////
2361
//// This source file is free software; you can redistribute it   ////
2362
//// and/or modify it under the terms of the GNU Lesser General   ////
2363
//// Public License as published by the Free Software Foundation; ////
2364
//// either version 2.1 of the License, or (at your option) any   ////
2365
//// later version.                                               ////
2366
////                                                              ////
2367
//// This source is distributed in the hope that it will be       ////
2368
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2369
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2370
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2371
//// details.                                                     ////
2372
////                                                              ////
2373
//// You should have received a copy of the GNU Lesser General    ////
2374
//// Public License along with this source; if not, download it   ////
2375
//// from http://www.opencores.org/lgpl.shtml                     ////
2376
////                                                              ////
2377
//////////////////////////////////////////////////////////////////////
2378
 
2379 25 unneback
// binary counter
2380
 
2381 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2382
module `BASE`MODULE (
2383
`undef MODULE
2384
 cke, rew, zq, level1, rst, clk);
2385
 
2386 25 unneback
   parameter length = 4;
2387
   input cke;
2388
   input rew;
2389
   output reg zq;
2390
   output reg level1;
2391
   input rst;
2392
   input clk;
2393
 
2394
   parameter clear_value = 0;
2395
   parameter set_value = 1;
2396
   parameter wrap_value = 1;
2397
   parameter level1_value = 15;
2398
 
2399 29 unneback
   wire clear;
2400 30 unneback
   assign clear = 1'b0;
2401 25 unneback
   reg  [length:1] qi;
2402
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2403
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2404
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2405
   assign q_next = rew ? q_next_rew : q_next_fw;
2406
 
2407
   always @ (posedge clk or posedge rst)
2408
     if (rst)
2409
       qi <= {length{1'b0}};
2410
     else
2411
     if (cke)
2412
       qi <= q_next;
2413
 
2414
 
2415
 
2416
   always @ (posedge clk or posedge rst)
2417
     if (rst)
2418
       zq <= 1'b1;
2419
     else
2420
     if (cke)
2421
       zq <= q_next == {length{1'b0}};
2422
 
2423
    always @ (posedge clk or posedge rst)
2424
    if (rst)
2425
        level1 <= 1'b0;
2426
    else
2427
    if (cke)
2428 29 unneback
    if (clear)
2429
        level1 <= 1'b0;
2430
    else if (q_next == level1_value)
2431 25 unneback
        level1 <= 1'b1;
2432
    else if (qi == level1_value & rew)
2433
        level1 <= 1'b0;
2434
endmodule
2435 40 unneback
`endif
2436
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2437 25 unneback
//////////////////////////////////////////////////////////////////////
2438
////                                                              ////
2439
////  Versatile counter                                           ////
2440
////                                                              ////
2441
////  Description                                                 ////
2442
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2443
////  counter                                                     ////
2444
////                                                              ////
2445
////  To Do:                                                      ////
2446
////   - add LFSR with more taps                                  ////
2447
////                                                              ////
2448
////  Author(s):                                                  ////
2449
////      - Michael Unneback, unneback@opencores.org              ////
2450
////        ORSoC AB                                              ////
2451
////                                                              ////
2452
//////////////////////////////////////////////////////////////////////
2453
////                                                              ////
2454
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2455
////                                                              ////
2456
//// This source file may be used and distributed without         ////
2457
//// restriction provided that this copyright statement is not    ////
2458
//// removed from the file and that any derivative work contains  ////
2459
//// the original copyright notice and the associated disclaimer. ////
2460
////                                                              ////
2461
//// This source file is free software; you can redistribute it   ////
2462
//// and/or modify it under the terms of the GNU Lesser General   ////
2463
//// Public License as published by the Free Software Foundation; ////
2464
//// either version 2.1 of the License, or (at your option) any   ////
2465
//// later version.                                               ////
2466
////                                                              ////
2467
//// This source is distributed in the hope that it will be       ////
2468
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2469
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2470
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2471
//// details.                                                     ////
2472
////                                                              ////
2473
//// You should have received a copy of the GNU Lesser General    ////
2474
//// Public License along with this source; if not, download it   ////
2475
//// from http://www.opencores.org/lgpl.shtml                     ////
2476
////                                                              ////
2477
//////////////////////////////////////////////////////////////////////
2478
 
2479
// binary counter
2480
 
2481 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2482
module `BASE`MODULE (
2483
`undef MODULE
2484
 cke, rew, q, zq, level1, rst, clk);
2485
 
2486 25 unneback
   parameter length = 4;
2487
   input cke;
2488
   input rew;
2489
   output [length:1] q;
2490
   output reg zq;
2491
   output reg level1;
2492
   input rst;
2493
   input clk;
2494
 
2495
   parameter clear_value = 0;
2496
   parameter set_value = 1;
2497
   parameter wrap_value = 1;
2498
   parameter level1_value = 15;
2499
 
2500 29 unneback
   wire clear;
2501 30 unneback
   assign clear = 1'b0;
2502 25 unneback
   reg  [length:1] qi;
2503
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2504
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2505
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2506
   assign q_next = rew ? q_next_rew : q_next_fw;
2507
 
2508
   always @ (posedge clk or posedge rst)
2509
     if (rst)
2510
       qi <= {length{1'b0}};
2511
     else
2512
     if (cke)
2513
       qi <= q_next;
2514
 
2515
   assign q = qi;
2516
 
2517
 
2518
   always @ (posedge clk or posedge rst)
2519
     if (rst)
2520
       zq <= 1'b1;
2521
     else
2522
     if (cke)
2523
       zq <= q_next == {length{1'b0}};
2524
 
2525
    always @ (posedge clk or posedge rst)
2526
    if (rst)
2527
        level1 <= 1'b0;
2528
    else
2529
    if (cke)
2530 29 unneback
    if (clear)
2531
        level1 <= 1'b0;
2532
    else if (q_next == level1_value)
2533 25 unneback
        level1 <= 1'b1;
2534
    else if (qi == level1_value & rew)
2535
        level1 <= 1'b0;
2536
endmodule
2537 40 unneback
`endif
2538
`ifdef CNT_LFSR_ZQ
2539 25 unneback
//////////////////////////////////////////////////////////////////////
2540
////                                                              ////
2541
////  Versatile counter                                           ////
2542
////                                                              ////
2543
////  Description                                                 ////
2544
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2545
////  counter                                                     ////
2546
////                                                              ////
2547
////  To Do:                                                      ////
2548
////   - add LFSR with more taps                                  ////
2549
////                                                              ////
2550
////  Author(s):                                                  ////
2551
////      - Michael Unneback, unneback@opencores.org              ////
2552
////        ORSoC AB                                              ////
2553
////                                                              ////
2554
//////////////////////////////////////////////////////////////////////
2555
////                                                              ////
2556
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2557
////                                                              ////
2558
//// This source file may be used and distributed without         ////
2559
//// restriction provided that this copyright statement is not    ////
2560
//// removed from the file and that any derivative work contains  ////
2561
//// the original copyright notice and the associated disclaimer. ////
2562
////                                                              ////
2563
//// This source file is free software; you can redistribute it   ////
2564
//// and/or modify it under the terms of the GNU Lesser General   ////
2565
//// Public License as published by the Free Software Foundation; ////
2566
//// either version 2.1 of the License, or (at your option) any   ////
2567
//// later version.                                               ////
2568
////                                                              ////
2569
//// This source is distributed in the hope that it will be       ////
2570
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2571
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2572
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2573
//// details.                                                     ////
2574
////                                                              ////
2575
//// You should have received a copy of the GNU Lesser General    ////
2576
//// Public License along with this source; if not, download it   ////
2577
//// from http://www.opencores.org/lgpl.shtml                     ////
2578
////                                                              ////
2579
//////////////////////////////////////////////////////////////////////
2580
 
2581 6 unneback
// LFSR counter
2582
 
2583 40 unneback
`define MODULE cnt_lfsr_zq
2584
module `BASE`MODULE (
2585
`undef MODULE
2586
 zq, rst, clk);
2587
 
2588 6 unneback
   parameter length = 4;
2589
   output reg zq;
2590
   input rst;
2591
   input clk;
2592
 
2593
   parameter clear_value = 0;
2594
   parameter set_value = 1;
2595
   parameter wrap_value = 8;
2596
   parameter level1_value = 15;
2597
 
2598
   reg  [length:1] qi;
2599
   reg lfsr_fb;
2600
   wire [length:1] q_next;
2601
   reg [32:1] polynom;
2602
   integer i;
2603
 
2604
   always @ (qi)
2605
   begin
2606
        case (length)
2607
         2: polynom = 32'b11;                               // 0x3
2608
         3: polynom = 32'b110;                              // 0x6
2609
         4: polynom = 32'b1100;                             // 0xC
2610
         5: polynom = 32'b10100;                            // 0x14
2611
         6: polynom = 32'b110000;                           // 0x30
2612
         7: polynom = 32'b1100000;                          // 0x60
2613
         8: polynom = 32'b10111000;                         // 0xb8
2614
         9: polynom = 32'b100010000;                        // 0x110
2615
        10: polynom = 32'b1001000000;                       // 0x240
2616
        11: polynom = 32'b10100000000;                      // 0x500
2617
        12: polynom = 32'b100000101001;                     // 0x829
2618
        13: polynom = 32'b1000000001100;                    // 0x100C
2619
        14: polynom = 32'b10000000010101;                   // 0x2015
2620
        15: polynom = 32'b110000000000000;                  // 0x6000
2621
        16: polynom = 32'b1101000000001000;                 // 0xD008
2622
        17: polynom = 32'b10010000000000000;                // 0x12000
2623
        18: polynom = 32'b100000010000000000;               // 0x20400
2624
        19: polynom = 32'b1000000000000100011;              // 0x40023
2625 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2626 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2627
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2628
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2629
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2630
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2631
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2632
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2633
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2634
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2635
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2636
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2637
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2638
        default: polynom = 32'b0;
2639
        endcase
2640
        lfsr_fb = qi[length];
2641
        for (i=length-1; i>=1; i=i-1) begin
2642
            if (polynom[i])
2643
                lfsr_fb = lfsr_fb  ~^ qi[i];
2644
        end
2645
    end
2646
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2647
 
2648
   always @ (posedge clk or posedge rst)
2649
     if (rst)
2650
       qi <= {length{1'b0}};
2651
     else
2652
       qi <= q_next;
2653
 
2654
 
2655
 
2656
   always @ (posedge clk or posedge rst)
2657
     if (rst)
2658
       zq <= 1'b1;
2659
     else
2660
       zq <= q_next == {length{1'b0}};
2661
endmodule
2662 40 unneback
`endif
2663 75 unneback
`ifdef CNT_LFSR_CE
2664
//////////////////////////////////////////////////////////////////////
2665
////                                                              ////
2666
////  Versatile counter                                           ////
2667
////                                                              ////
2668
////  Description                                                 ////
2669
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2670
////  counter                                                     ////
2671
////                                                              ////
2672
////  To Do:                                                      ////
2673
////   - add LFSR with more taps                                  ////
2674
////                                                              ////
2675
////  Author(s):                                                  ////
2676
////      - Michael Unneback, unneback@opencores.org              ////
2677
////        ORSoC AB                                              ////
2678
////                                                              ////
2679
//////////////////////////////////////////////////////////////////////
2680
////                                                              ////
2681
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2682
////                                                              ////
2683
//// This source file may be used and distributed without         ////
2684
//// restriction provided that this copyright statement is not    ////
2685
//// removed from the file and that any derivative work contains  ////
2686
//// the original copyright notice and the associated disclaimer. ////
2687
////                                                              ////
2688
//// This source file is free software; you can redistribute it   ////
2689
//// and/or modify it under the terms of the GNU Lesser General   ////
2690
//// Public License as published by the Free Software Foundation; ////
2691
//// either version 2.1 of the License, or (at your option) any   ////
2692
//// later version.                                               ////
2693
////                                                              ////
2694
//// This source is distributed in the hope that it will be       ////
2695
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2696
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2697
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2698
//// details.                                                     ////
2699
////                                                              ////
2700
//// You should have received a copy of the GNU Lesser General    ////
2701
//// Public License along with this source; if not, download it   ////
2702
//// from http://www.opencores.org/lgpl.shtml                     ////
2703
////                                                              ////
2704
//////////////////////////////////////////////////////////////////////
2705
 
2706
// LFSR counter
2707
 
2708
`define MODULE cnt_lfsr_ce
2709
module `BASE`MODULE (
2710
`undef MODULE
2711
 cke, zq, rst, clk);
2712
 
2713
   parameter length = 4;
2714
   input cke;
2715
   output reg zq;
2716
   input rst;
2717
   input clk;
2718
 
2719
   parameter clear_value = 0;
2720
   parameter set_value = 1;
2721
   parameter wrap_value = 0;
2722
   parameter level1_value = 15;
2723
 
2724
   reg  [length:1] qi;
2725
   reg lfsr_fb;
2726
   wire [length:1] q_next;
2727
   reg [32:1] polynom;
2728
   integer i;
2729
 
2730
   always @ (qi)
2731
   begin
2732
        case (length)
2733
         2: polynom = 32'b11;                               // 0x3
2734
         3: polynom = 32'b110;                              // 0x6
2735
         4: polynom = 32'b1100;                             // 0xC
2736
         5: polynom = 32'b10100;                            // 0x14
2737
         6: polynom = 32'b110000;                           // 0x30
2738
         7: polynom = 32'b1100000;                          // 0x60
2739
         8: polynom = 32'b10111000;                         // 0xb8
2740
         9: polynom = 32'b100010000;                        // 0x110
2741
        10: polynom = 32'b1001000000;                       // 0x240
2742
        11: polynom = 32'b10100000000;                      // 0x500
2743
        12: polynom = 32'b100000101001;                     // 0x829
2744
        13: polynom = 32'b1000000001100;                    // 0x100C
2745
        14: polynom = 32'b10000000010101;                   // 0x2015
2746
        15: polynom = 32'b110000000000000;                  // 0x6000
2747
        16: polynom = 32'b1101000000001000;                 // 0xD008
2748
        17: polynom = 32'b10010000000000000;                // 0x12000
2749
        18: polynom = 32'b100000010000000000;               // 0x20400
2750
        19: polynom = 32'b1000000000000100011;              // 0x40023
2751
        20: polynom = 32'b10010000000000000000;             // 0x90000
2752
        21: polynom = 32'b101000000000000000000;            // 0x140000
2753
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2754
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2755
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2756
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2757
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2758
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2759
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2760
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2761
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2762
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2763
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2764
        default: polynom = 32'b0;
2765
        endcase
2766
        lfsr_fb = qi[length];
2767
        for (i=length-1; i>=1; i=i-1) begin
2768
            if (polynom[i])
2769
                lfsr_fb = lfsr_fb  ~^ qi[i];
2770
        end
2771
    end
2772
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2773
 
2774
   always @ (posedge clk or posedge rst)
2775
     if (rst)
2776
       qi <= {length{1'b0}};
2777
     else
2778
     if (cke)
2779
       qi <= q_next;
2780
 
2781
 
2782
 
2783
   always @ (posedge clk or posedge rst)
2784
     if (rst)
2785
       zq <= 1'b1;
2786
     else
2787
     if (cke)
2788
       zq <= q_next == {length{1'b0}};
2789
endmodule
2790
`endif
2791 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2792 6 unneback
//////////////////////////////////////////////////////////////////////
2793
////                                                              ////
2794
////  Versatile counter                                           ////
2795
////                                                              ////
2796
////  Description                                                 ////
2797
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2798
////  counter                                                     ////
2799
////                                                              ////
2800
////  To Do:                                                      ////
2801
////   - add LFSR with more taps                                  ////
2802
////                                                              ////
2803
////  Author(s):                                                  ////
2804
////      - Michael Unneback, unneback@opencores.org              ////
2805
////        ORSoC AB                                              ////
2806
////                                                              ////
2807
//////////////////////////////////////////////////////////////////////
2808
////                                                              ////
2809
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2810
////                                                              ////
2811
//// This source file may be used and distributed without         ////
2812
//// restriction provided that this copyright statement is not    ////
2813
//// removed from the file and that any derivative work contains  ////
2814
//// the original copyright notice and the associated disclaimer. ////
2815
////                                                              ////
2816
//// This source file is free software; you can redistribute it   ////
2817
//// and/or modify it under the terms of the GNU Lesser General   ////
2818
//// Public License as published by the Free Software Foundation; ////
2819
//// either version 2.1 of the License, or (at your option) any   ////
2820
//// later version.                                               ////
2821
////                                                              ////
2822
//// This source is distributed in the hope that it will be       ////
2823
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2824
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2825
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2826
//// details.                                                     ////
2827
////                                                              ////
2828
//// You should have received a copy of the GNU Lesser General    ////
2829
//// Public License along with this source; if not, download it   ////
2830
//// from http://www.opencores.org/lgpl.shtml                     ////
2831
////                                                              ////
2832
//////////////////////////////////////////////////////////////////////
2833
 
2834
// LFSR counter
2835
 
2836 40 unneback
`define MODULE cnt_lfsr_ce_zq
2837
module `BASE`MODULE (
2838
`undef MODULE
2839
 cke, zq, rst, clk);
2840
 
2841 6 unneback
   parameter length = 4;
2842
   input cke;
2843
   output reg zq;
2844
   input rst;
2845
   input clk;
2846
 
2847
   parameter clear_value = 0;
2848
   parameter set_value = 1;
2849
   parameter wrap_value = 8;
2850
   parameter level1_value = 15;
2851
 
2852
   reg  [length:1] qi;
2853
   reg lfsr_fb;
2854
   wire [length:1] q_next;
2855
   reg [32:1] polynom;
2856
   integer i;
2857
 
2858
   always @ (qi)
2859
   begin
2860
        case (length)
2861
         2: polynom = 32'b11;