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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 139

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
14
    // ACTEL FPGA should not use logic to handle rw collision
15
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16
`else
17
    `define SYN_NO_RW_CHECK
18
`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
23
`define SYNC_RST
24
`define PLL
25
 
26
`define MULTS
27
`define MULTS18X18
28
`define MULT
29
`define SHIFT_UNIT_32
30
`define LOGIC_UNIT
31
 
32
`define CNT_SHREG_WRAP
33
`define CNT_SHREG_CE_WRAP
34 105 unneback
`define CNT_SHREG_CLEAR
35 40 unneback
`define CNT_SHREG_CE_CLEAR
36
`define CNT_SHREG_CE_CLEAR_WRAP
37
 
38 139 unneback
`define CNT_BIN
39
`define CNT_BIN_CE
40
`define CNT_BIN_CLEAR
41
`define CNT_BIN_CE_CLEAR
42
`define CNT_BIN_CE_CLEAR_L1_L2
43
`define CNT_BIN_CE_CLEAR_SET_REW
44
`define CNT_BIN_CE_REW_L1
45
`define CNT_BIN_CE_REW_ZQ_L1
46
`define CNT_BIN_CE_REW_Q_ZQ_L1
47
`define CNT_GRAY
48
`define CNT_GRAY_CE
49
`define CNT_GRAY_CE_BIN
50
`define CNT_LFSR_ZQ
51
`define CNT_LFSR_CE
52
`define CNT_LFSR_CE_CLEAR_Q
53
`define CNT_LFSR_CE_Q
54
`define CNT_LFSR_CE_ZQ
55
`define CNT_LFSR_CE_Q_ZQ
56
`define CNT_LFSR_CE_REW_L1
57
 
58 40 unneback
`define MUX_ANDOR
59
`define MUX2_ANDOR
60
`define MUX3_ANDOR
61
`define MUX4_ANDOR
62
`define MUX5_ANDOR
63
`define MUX6_ANDOR
64 43 unneback
`define PARITY
65 40 unneback
 
66
`define ROM_INIT
67
`define RAM
68
`define RAM_BE
69
`define DPRAM_1R1W
70
`define DPRAM_2R1W
71 100 unneback
`define DPRAM_1R2W
72 40 unneback
`define DPRAM_2R2W
73 75 unneback
`define DPRAM_BE_2R2W
74 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
75
`define FIFO_2R2W_SYNC_SIMPLEX
76
`define FIFO_CMP_ASYNC
77
`define FIFO_1R1W_ASYNC
78
`define FIFO_2R2W_ASYNC
79
`define FIFO_2R2W_ASYNC_SIMPLEX
80 48 unneback
`define REG_FILE
81 40 unneback
 
82
`define DFF
83
`define DFF_ARRAY
84
`define DFF_CE
85
`define DFF_CE_CLEAR
86
`define DF_CE_SET
87
`define SPR
88
`define SRP
89
`define DFF_SR
90
`define LATCH
91
`define SHREG
92
`define SHREG_CE
93
`define DELAY
94
`define DELAY_EMPTYFLAG
95 94 unneback
`define PULSE2TOGGLE
96
`define TOGGLE2PULSE
97
`define SYNCHRONIZER
98
`define CDC
99 40 unneback
 
100 75 unneback
`define WB3AVALON_BRIDGE
101 40 unneback
`define WB3WB3_BRIDGE
102
`define WB3_ARBITER_TYPE1
103 83 unneback
`define WB_ADR_INC
104 101 unneback
`define WB_RAM
105 103 unneback
`define WB_SHADOW_RAM
106 48 unneback
`define WB_B4_ROM
107 40 unneback
`define WB_BOOT_ROM
108
`define WB_DPRAM
109 101 unneback
`define WB_CACHE
110 103 unneback
`define WB_AVALON_BRIDGE
111
`define WB_AVALON_MEM_CACHE
112 136 unneback
`define WB_SDR_SDRAM_CTRL
113 40 unneback
 
114 44 unneback
`define IO_DFF_OE
115
`define O_DFF
116 136 unneback
`define O_DDR
117
`define O_CLK
118 44 unneback
 
119 40 unneback
`endif
120
 
121 136 unneback
///////////////////////////////////////
122
// dependencies
123
///////////////////////////////////////
124
 
125 40 unneback
`ifdef PLL
126
`ifndef SYNC_RST
127
`define SYNC_RST
128
`endif
129
`endif
130
 
131
`ifdef SYNC_RST
132
`ifndef GBUF
133
`define GBUF
134
`endif
135
`endif
136
 
137 136 unneback
`ifdef WB_SDR_SDRAM_CTRL
138
`ifndef WB_SHADOW_RAM
139
`define WB_SHADOW_RAM
140
`endif
141
`ifndef WB_CACHE
142
`define WB_CACHE
143
`endif
144
`ifndef WB_SDR_SDRAM
145
`define WB_SDR_SDRAM
146
`endif
147
`ifndef IO_DFF_OE
148
`define IO_DFF_OE
149
`endif
150
`ifndef O_DFF
151
`define O_DFF
152
`endif
153
`ifndef O_CLK
154
`define O_CLK
155
`endif
156
`endif
157
 
158
`ifdef WB_SDR_SDRAM
159
`ifndef CNT_SHREG_CLEAR
160
`define CNT_SHREG_CLEAR
161
`endif
162
`ifndef CNT_LFSR_ZQ
163
`define CNT_LFSR_ZQ
164
`endif
165
`ifndef DELAY_EMPTYFLAG
166
`define DELAY_EMPTYFLAG
167
`endif
168
`endif
169
 
170 108 unneback
`ifdef WB_DPRAM
171 92 unneback
`ifndef WB_ADR_INC
172
`define WB_ADR_INC
173 40 unneback
`endif
174 92 unneback
`ifndef DPRAM_BE_2R2W
175
`define DPRAM_BE_2R2W
176 40 unneback
`endif
177
`endif
178
 
179
`ifdef WB3_ARBITER_TYPE1
180 42 unneback
`ifndef SPR
181
`define SPR
182
`endif
183 40 unneback
`ifndef MUX_ANDOR
184
`define MUX_ANDOR
185
`endif
186
`endif
187
 
188 76 unneback
`ifdef WB3AVALON_BRIDGE
189
`ifndef WB3WB3_BRIDGE
190
`define WB3WB3_BRIDGE
191
`endif
192
`endif
193
 
194 40 unneback
`ifdef WB3WB3_BRIDGE
195
`ifndef CNT_SHREG_CE_CLEAR
196
`define CNT_SHREG_CE_CLEAR
197
`endif
198
`ifndef DFF
199
`define DFF
200
`endif
201
`ifndef DFF_CE
202
`define DFF_CE
203
`endif
204
`ifndef CNT_SHREG_CE_CLEAR
205
`define CNT_SHREG_CE_CLEAR
206
`endif
207
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
208
`define FIFO_2R2W_ASYNC_SIMPLEX
209
`endif
210
`endif
211
 
212 103 unneback
 
213
`ifdef WB_AVALON_MEM_CACHE
214
`ifndef WB_SHADOW_RAM
215
`define WB_SHADOW_RAM
216
`endif
217
`ifndef WB_CACHE
218
`define WB_CACHE
219
`endif
220
`ifndef WB_AVALON_BRIDGE
221
`define WB_AVALON_BRIDGE
222
`endif
223
`endif
224
 
225 101 unneback
`ifdef WB_CACHE
226 100 unneback
`ifndef RAM
227
`define RAM
228
`endif
229
`ifndef WB_ADR_INC
230
`define WB_ADR_INC
231
`endif
232
`ifndef DPRAM_1R1W
233
`define DPRAM_1R1W
234
`endif
235
`ifndef DPRAM_1R2W
236
`define DPRAM_1R2W
237
`endif
238
`ifndef DPRAM_BE_2R2W
239
`define DPRAM_BE_2R2W
240
`endif
241
`ifndef CDC
242
`define CDC
243
`endif
244 136 unneback
`ifndef O_DFF
245
`define O_DFF
246 100 unneback
`endif
247 136 unneback
`ifndef O_CLK
248
`define O_CLK
249
`endif
250
`endif
251 103 unneback
 
252
`ifdef WB_SHADOW_RAM
253 115 unneback
`ifndef WB_RAM
254
`define WB_RAM
255 103 unneback
`endif
256
`endif
257
 
258
`ifdef WB_RAM
259
`ifndef WB_ADR_INC
260
`define WB_ADR_INC
261
`endif
262 114 unneback
`ifndef RAM_BE
263
`define RAM_BE
264 103 unneback
`endif
265 114 unneback
`endif
266
 
267 40 unneback
`ifdef MULTS18X18
268
`ifndef MULTS
269
`define MULTS
270
`endif
271
`endif
272
 
273
`ifdef SHIFT_UNIT_32
274
`ifndef MULTS
275
`define MULTS
276
`endif
277
`endif
278
 
279
`ifdef MUX2_ANDOR
280
`ifndef MUX_ANDOR
281
`define MUX_ANDOR
282
`endif
283
`endif
284
 
285
`ifdef MUX3_ANDOR
286
`ifndef MUX_ANDOR
287
`define MUX_ANDOR
288
`endif
289
`endif
290
 
291
`ifdef MUX4_ANDOR
292
`ifndef MUX_ANDOR
293
`define MUX_ANDOR
294
`endif
295
`endif
296
 
297
`ifdef MUX5_ANDOR
298
`ifndef MUX_ANDOR
299
`define MUX_ANDOR
300
`endif
301
`endif
302
 
303
`ifdef MUX6_ANDOR
304
`ifndef MUX_ANDOR
305
`define MUX_ANDOR
306
`endif
307
`endif
308
 
309
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
310
`ifndef CNT_BIN_CE
311
`define CNT_BIN_CE
312
`endif
313
`ifndef DPRAM_1R1W
314
`define DPRAM_1R1W
315
`endif
316
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
317
`define CNT_BIN_CE_REW_Q_ZQ_L1
318
`endif
319
`endif
320
 
321
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
322
`ifndef CNT_LFSR_CE
323
`define CNT_LFSR_CE
324
`endif
325
`ifndef DPRAM_2R2W
326
`define DPRAM_2R2W
327
`endif
328
`ifndef CNT_BIN_CE_REW_ZQ_L1
329
`define CNT_BIN_CE_REW_ZQ_L1
330
`endif
331
`endif
332
 
333
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
334
`ifndef CNT_GRAY_CE_BIN
335
`define CNT_GRAY_CE_BIN
336
`endif
337
`ifndef DPRAM_2R2W
338
`define DPRAM_2R2W
339
`endif
340
`ifndef FIFO_CMP_ASYNC
341
`define FIFO_CMP_ASYNC
342
`endif
343
`endif
344
 
345
`ifdef FIFO_2R2W_ASYNC
346
`ifndef FIFO_1R1W_ASYNC
347
`define FIFO_1R1W_ASYNC
348
`endif
349
`endif
350
 
351
`ifdef FIFO_1R1W_ASYNC
352
`ifndef CNT_GRAY_CE_BIN
353
`define CNT_GRAY_CE_BIN
354
`endif
355
`ifndef DPRAM_1R1W
356
`define DPRAM_1R1W
357
`endif
358
`ifndef FIFO_CMP_ASYNC
359
`define FIFO_CMP_ASYNC
360
`endif
361
`endif
362
 
363
`ifdef FIFO_CMP_ASYNC
364
`ifndef DFF_SR
365
`define DFF_SR
366
`endif
367
`ifndef DFF
368
`define DFF
369
`endif
370
`endif
371 48 unneback
 
372
`ifdef REG_FILE
373
`ifndef DPRAM_1R1W
374
`define DPRAM_1R1W
375
`endif
376
`endif
377 97 unneback
 
378 98 unneback
`ifdef CDC
379
`ifndef PULSE2TOGGLE
380
`define PULSE2TOGGLE
381
`endif
382
`ifndef TOGGLE2PULSE
383
`define TOGGLE2PULSE
384
`endif
385
`ifndef SYNCHRONIZER
386
`define SYNCHRONIZER
387
`endif
388
`endif
389
 
390 136 unneback
`ifdef O_CLK
391
`ifndef O_DDR
392
`define O_DDR
393
`endif
394
`endif
395
 
396 97 unneback
// size to width
397 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
398 62 unneback
//////////////////////////////////////////////////////////////////////
399 6 unneback
////                                                              ////
400
////  Versatile library, clock and reset                          ////
401
////                                                              ////
402
////  Description                                                 ////
403
////  Logic related to clock and reset                            ////
404
////                                                              ////
405
////                                                              ////
406
////  To Do:                                                      ////
407
////   - add more different registers                             ////
408
////                                                              ////
409
////  Author(s):                                                  ////
410
////      - Michael Unneback, unneback@opencores.org              ////
411
////        ORSoC AB                                              ////
412
////                                                              ////
413
//////////////////////////////////////////////////////////////////////
414
////                                                              ////
415
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
416
////                                                              ////
417
//// This source file may be used and distributed without         ////
418
//// restriction provided that this copyright statement is not    ////
419
//// removed from the file and that any derivative work contains  ////
420
//// the original copyright notice and the associated disclaimer. ////
421
////                                                              ////
422
//// This source file is free software; you can redistribute it   ////
423
//// and/or modify it under the terms of the GNU Lesser General   ////
424
//// Public License as published by the Free Software Foundation; ////
425
//// either version 2.1 of the License, or (at your option) any   ////
426
//// later version.                                               ////
427
////                                                              ////
428
//// This source is distributed in the hope that it will be       ////
429
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
430
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
431
//// PURPOSE.  See the GNU Lesser General Public License for more ////
432
//// details.                                                     ////
433
////                                                              ////
434
//// You should have received a copy of the GNU Lesser General    ////
435
//// Public License along with this source; if not, download it   ////
436
//// from http://www.opencores.org/lgpl.shtml                     ////
437
////                                                              ////
438
//////////////////////////////////////////////////////////////////////
439
 
440 48 unneback
`ifdef ACTEL
441
`ifdef GBUF
442
`timescale 1 ns/100 ps
443 6 unneback
// Global buffer
444
// usage:
445
// use to enable global buffers for high fan out signals such as clock and reset
446
// Version: 8.4 8.4.0.33
447
module gbuf(GL,CLK);
448
output GL;
449
input  CLK;
450
 
451
    wire GND;
452
 
453
    GND GND_1_net(.Y(GND));
454
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
455
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
456
 
457
endmodule
458
`timescale 1 ns/1 ns
459 40 unneback
`define MODULE gbuf
460
module `BASE`MODULE ( i, o);
461
`undef MODULE
462 6 unneback
input i;
463
output o;
464
`ifdef SIM_GBUF
465
assign o=i;
466
`else
467
gbuf gbuf_i0 ( .CLK(i), .GL(o));
468
`endif
469
endmodule
470 40 unneback
`endif
471 33 unneback
 
472 6 unneback
`else
473 33 unneback
 
474 40 unneback
`ifdef ALTERA
475
`ifdef GBUF
476 21 unneback
//altera
477 40 unneback
`define MODULE gbuf
478
module `BASE`MODULE ( i, o);
479
`undef MODULE
480 33 unneback
input i;
481
output o;
482
assign o = i;
483
endmodule
484 40 unneback
`endif
485 33 unneback
 
486 6 unneback
`else
487
 
488 40 unneback
`ifdef GBUF
489 6 unneback
`timescale 1 ns/100 ps
490 40 unneback
`define MODULE
491
module `BASE`MODULE ( i, o);
492
`undef MODULE
493 6 unneback
input i;
494
output o;
495
assign o = i;
496
endmodule
497 40 unneback
`endif
498 6 unneback
`endif // ALTERA
499
`endif //ACTEL
500
 
501 40 unneback
`ifdef SYNC_RST
502 6 unneback
// sync reset
503 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
504 6 unneback
// output active high global reset sync with two DFFs 
505
`timescale 1 ns/100 ps
506 40 unneback
`define MODULE sync_rst
507
module `BASE`MODULE ( rst_n_i, rst_o, clk);
508
`undef MODULE
509 6 unneback
input rst_n_i, clk;
510
output rst_o;
511 18 unneback
reg [1:0] tmp;
512 6 unneback
always @ (posedge clk or negedge rst_n_i)
513
if (!rst_n_i)
514 17 unneback
        tmp <= 2'b11;
515 6 unneback
else
516 33 unneback
        tmp <= {1'b0,tmp[1]};
517 40 unneback
`define MODULE gbuf
518
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
519
`undef MODULE
520 6 unneback
endmodule
521 40 unneback
`endif
522 6 unneback
 
523 40 unneback
`ifdef PLL
524 6 unneback
// vl_pll
525
`ifdef ACTEL
526 32 unneback
///////////////////////////////////////////////////////////////////////////////
527 17 unneback
`timescale 1 ps/1 ps
528 40 unneback
`define MODULE pll
529
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
530
`undef MODULE
531 6 unneback
parameter index = 0;
532
parameter number_of_clk = 1;
533 17 unneback
parameter period_time_0 = 20000;
534
parameter period_time_1 = 20000;
535
parameter period_time_2 = 20000;
536
parameter lock_delay = 2000000;
537 6 unneback
input clk_i, rst_n_i;
538
output lock;
539
output reg [0:number_of_clk-1] clk_o;
540
output [0:number_of_clk-1] rst_o;
541
 
542
`ifdef SIM_PLL
543
 
544
always
545
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
546
 
547
generate if (number_of_clk > 1)
548
always
549
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
550
endgenerate
551
 
552
generate if (number_of_clk > 2)
553
always
554
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
555
endgenerate
556
 
557
genvar i;
558
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
559
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
560
end
561
endgenerate
562
 
563
assign #lock_delay lock = rst_n_i;
564
 
565
endmodule
566
`else
567
generate if (number_of_clk==1 & index==0) begin
568
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
569
end
570
endgenerate // index==0
571
generate if (number_of_clk==1 & index==1) begin
572
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
573
end
574
endgenerate // index==1
575
generate if (number_of_clk==1 & index==2) begin
576
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
577
end
578
endgenerate // index==2
579
generate if (number_of_clk==1 & index==3) begin
580
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
581
end
582
endgenerate // index==0
583
 
584
generate if (number_of_clk==2 & index==0) begin
585
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
586
end
587
endgenerate // index==0
588
generate if (number_of_clk==2 & index==1) begin
589
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
590
end
591
endgenerate // index==1
592
generate if (number_of_clk==2 & index==2) begin
593
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
594
end
595
endgenerate // index==2
596
generate if (number_of_clk==2 & index==3) begin
597
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
598
end
599
endgenerate // index==0
600
 
601
generate if (number_of_clk==3 & index==0) begin
602
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
603
end
604
endgenerate // index==0
605
generate if (number_of_clk==3 & index==1) begin
606
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
607
end
608
endgenerate // index==1
609
generate if (number_of_clk==3 & index==2) begin
610
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
611
end
612
endgenerate // index==2
613
generate if (number_of_clk==3 & index==3) begin
614
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
615
end
616
endgenerate // index==0
617
 
618
genvar i;
619
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
620 40 unneback
`define MODULE sync_rst
621
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
622
`undef MODULE
623 6 unneback
end
624
endgenerate
625
endmodule
626
`endif
627 32 unneback
///////////////////////////////////////////////////////////////////////////////
628 6 unneback
 
629
`else
630
 
631 32 unneback
///////////////////////////////////////////////////////////////////////////////
632 6 unneback
`ifdef ALTERA
633
 
634 32 unneback
`timescale 1 ps/1 ps
635 40 unneback
`define MODULE pll
636
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
637
`undef MODULE
638 32 unneback
parameter index = 0;
639
parameter number_of_clk = 1;
640
parameter period_time_0 = 20000;
641
parameter period_time_1 = 20000;
642
parameter period_time_2 = 20000;
643
parameter period_time_3 = 20000;
644
parameter period_time_4 = 20000;
645
parameter lock_delay = 2000000;
646
input clk_i, rst_n_i;
647
output lock;
648
output reg [0:number_of_clk-1] clk_o;
649
output [0:number_of_clk-1] rst_o;
650
 
651
`ifdef SIM_PLL
652
 
653
always
654
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
655
 
656
generate if (number_of_clk > 1)
657
always
658
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
659
endgenerate
660
 
661
generate if (number_of_clk > 2)
662
always
663
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
664
endgenerate
665
 
666 33 unneback
generate if (number_of_clk > 3)
667 32 unneback
always
668
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
669
endgenerate
670
 
671 33 unneback
generate if (number_of_clk > 4)
672 32 unneback
always
673
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
674
endgenerate
675
 
676
genvar i;
677
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
678
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
679
end
680
endgenerate
681
 
682 33 unneback
//assign #lock_delay lock = rst_n_i;
683
assign lock = rst_n_i;
684 32 unneback
 
685
endmodule
686 6 unneback
`else
687
 
688 33 unneback
`ifdef VL_PLL0
689
`ifdef VL_PLL0_CLK1
690
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
691
`endif
692
`ifdef VL_PLL0_CLK2
693
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
694
`endif
695
`ifdef VL_PLL0_CLK3
696
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
697
`endif
698
`ifdef VL_PLL0_CLK4
699
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
700
`endif
701
`ifdef VL_PLL0_CLK5
702
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
703
`endif
704
`endif
705 32 unneback
 
706 33 unneback
`ifdef VL_PLL1
707
`ifdef VL_PLL1_CLK1
708
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
709
`endif
710
`ifdef VL_PLL1_CLK2
711
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
712
`endif
713
`ifdef VL_PLL1_CLK3
714
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
715
`endif
716
`ifdef VL_PLL1_CLK4
717
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
718
`endif
719
`ifdef VL_PLL1_CLK5
720
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
721
`endif
722
`endif
723 32 unneback
 
724 33 unneback
`ifdef VL_PLL2
725
`ifdef VL_PLL2_CLK1
726
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
727
`endif
728
`ifdef VL_PLL2_CLK2
729
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
730
`endif
731
`ifdef VL_PLL2_CLK3
732
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
733
`endif
734
`ifdef VL_PLL2_CLK4
735
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
736
`endif
737
`ifdef VL_PLL2_CLK5
738
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
739
`endif
740
`endif
741 32 unneback
 
742 33 unneback
`ifdef VL_PLL3
743
`ifdef VL_PLL3_CLK1
744
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
745
`endif
746
`ifdef VL_PLL3_CLK2
747
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
748
`endif
749
`ifdef VL_PLL3_CLK3
750
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
751
`endif
752
`ifdef VL_PLL3_CLK4
753
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
754
`endif
755
`ifdef VL_PLL3_CLK5
756
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
757
`endif
758
`endif
759 32 unneback
 
760
genvar i;
761
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
762 40 unneback
`define MODULE sync_rst
763
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
764
`undef MODULE
765 32 unneback
end
766
endgenerate
767
endmodule
768
`endif
769
///////////////////////////////////////////////////////////////////////////////
770
 
771
`else
772
 
773 6 unneback
// generic PLL
774 17 unneback
`timescale 1 ps/1 ps
775 40 unneback
`define MODULE pll
776
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
777
`undef MODULE
778 6 unneback
parameter index = 0;
779
parameter number_of_clk = 1;
780 17 unneback
parameter period_time_0 = 20000;
781
parameter period_time_1 = 20000;
782
parameter period_time_2 = 20000;
783 6 unneback
parameter lock_delay = 2000;
784
input clk_i, rst_n_i;
785
output lock;
786
output reg [0:number_of_clk-1] clk_o;
787
output [0:number_of_clk-1] rst_o;
788
 
789
always
790
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
791
 
792
generate if (number_of_clk > 1)
793
always
794
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
795
endgenerate
796
 
797
generate if (number_of_clk > 2)
798
always
799
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
800
endgenerate
801
 
802
genvar i;
803
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
804 40 unneback
`define MODULE sync_rst
805
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
806
`undef MODULE
807 6 unneback
end
808
endgenerate
809
 
810
assign #lock_delay lock = rst_n_i;
811
 
812
endmodule
813
 
814
`endif //altera
815 17 unneback
`endif //actel
816 40 unneback
`undef MODULE
817
`endif//////////////////////////////////////////////////////////////////////
818 6 unneback
////                                                              ////
819
////  Versatile library, registers                                ////
820
////                                                              ////
821
////  Description                                                 ////
822
////  Different type of registers                                 ////
823
////                                                              ////
824
////                                                              ////
825
////  To Do:                                                      ////
826
////   - add more different registers                             ////
827
////                                                              ////
828
////  Author(s):                                                  ////
829
////      - Michael Unneback, unneback@opencores.org              ////
830
////        ORSoC AB                                              ////
831
////                                                              ////
832
//////////////////////////////////////////////////////////////////////
833
////                                                              ////
834
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
835
////                                                              ////
836
//// This source file may be used and distributed without         ////
837
//// restriction provided that this copyright statement is not    ////
838
//// removed from the file and that any derivative work contains  ////
839
//// the original copyright notice and the associated disclaimer. ////
840
////                                                              ////
841
//// This source file is free software; you can redistribute it   ////
842
//// and/or modify it under the terms of the GNU Lesser General   ////
843
//// Public License as published by the Free Software Foundation; ////
844
//// either version 2.1 of the License, or (at your option) any   ////
845
//// later version.                                               ////
846
////                                                              ////
847
//// This source is distributed in the hope that it will be       ////
848
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
849
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
850
//// PURPOSE.  See the GNU Lesser General Public License for more ////
851
//// details.                                                     ////
852
////                                                              ////
853
//// You should have received a copy of the GNU Lesser General    ////
854
//// Public License along with this source; if not, download it   ////
855
//// from http://www.opencores.org/lgpl.shtml                     ////
856
////                                                              ////
857
//////////////////////////////////////////////////////////////////////
858
 
859 40 unneback
`ifdef DFF
860
`define MODULE dff
861
module `BASE`MODULE ( d, q, clk, rst);
862
`undef MODULE
863 6 unneback
        parameter width = 1;
864 139 unneback
        parameter reset_value = {width{1'b0}};
865 6 unneback
 
866
        input [width-1:0] d;
867
        input clk, rst;
868
        output reg [width-1:0] q;
869
 
870
        always @ (posedge clk or posedge rst)
871
        if (rst)
872
                q <= reset_value;
873
        else
874
                q <= d;
875
 
876
endmodule
877 40 unneback
`endif
878 6 unneback
 
879 40 unneback
`ifdef DFF_ARRAY
880
`define MODULE dff_array
881
module `BASE`MODULE ( d, q, clk, rst);
882
`undef MODULE
883 6 unneback
 
884
        parameter width = 1;
885
        parameter depth = 2;
886
        parameter reset_value = 1'b0;
887
 
888
        input [width-1:0] d;
889
        input clk, rst;
890
        output [width-1:0] q;
891
        reg  [0:depth-1] q_tmp [width-1:0];
892
        integer i;
893
        always @ (posedge clk or posedge rst)
894
        if (rst) begin
895
            for (i=0;i<depth;i=i+1)
896
                q_tmp[i] <= {width{reset_value}};
897
        end else begin
898
            q_tmp[0] <= d;
899
            for (i=1;i<depth;i=i+1)
900
                q_tmp[i] <= q_tmp[i-1];
901
        end
902
 
903
    assign q = q_tmp[depth-1];
904
 
905
endmodule
906 40 unneback
`endif
907 6 unneback
 
908 40 unneback
`ifdef DFF_CE
909
`define MODULE dff_ce
910
module `BASE`MODULE ( d, ce, q, clk, rst);
911
`undef MODULE
912 6 unneback
 
913
        parameter width = 1;
914 139 unneback
        parameter reset_value = {width{1'b0}};
915 6 unneback
 
916
        input [width-1:0] d;
917
        input ce, clk, rst;
918
        output reg [width-1:0] q;
919
 
920
        always @ (posedge clk or posedge rst)
921
        if (rst)
922
                q <= reset_value;
923
        else
924
                if (ce)
925
                        q <= d;
926
 
927
endmodule
928 40 unneback
`endif
929 6 unneback
 
930 40 unneback
`ifdef DFF_CE_CLEAR
931
`define MODULE dff_ce_clear
932
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
933
`undef MODULE
934 8 unneback
 
935
        parameter width = 1;
936 139 unneback
        parameter reset_value = {width{1'b0}};
937 8 unneback
 
938
        input [width-1:0] d;
939 10 unneback
        input ce, clear, clk, rst;
940 8 unneback
        output reg [width-1:0] q;
941
 
942
        always @ (posedge clk or posedge rst)
943
        if (rst)
944
            q <= reset_value;
945
        else
946
            if (ce)
947
                if (clear)
948
                    q <= {width{1'b0}};
949
                else
950
                    q <= d;
951
 
952
endmodule
953 40 unneback
`endif
954 8 unneback
 
955 40 unneback
`ifdef DF_CE_SET
956
`define MODULE dff_ce_set
957
module `BASE`MODULE ( d, ce, set, q, clk, rst);
958
`undef MODULE
959 24 unneback
 
960
        parameter width = 1;
961 139 unneback
        parameter reset_value = {width{1'b0}};
962 24 unneback
 
963
        input [width-1:0] d;
964
        input ce, set, clk, rst;
965
        output reg [width-1:0] q;
966
 
967
        always @ (posedge clk or posedge rst)
968
        if (rst)
969
            q <= reset_value;
970
        else
971
            if (ce)
972
                if (set)
973
                    q <= {width{1'b1}};
974
                else
975
                    q <= d;
976
 
977
endmodule
978 40 unneback
`endif
979 24 unneback
 
980 40 unneback
`ifdef SPR
981
`define MODULE spr
982
module `BASE`MODULE ( sp, r, q, clk, rst);
983
`undef MODULE
984
 
985 64 unneback
        //parameter width = 1;
986
        parameter reset_value = 1'b0;
987 29 unneback
 
988
        input sp, r;
989
        output reg q;
990
        input clk, rst;
991
 
992
        always @ (posedge clk or posedge rst)
993
        if (rst)
994
            q <= reset_value;
995
        else
996
            if (sp)
997
                q <= 1'b1;
998
            else if (r)
999
                q <= 1'b0;
1000
 
1001
endmodule
1002 40 unneback
`endif
1003 29 unneback
 
1004 40 unneback
`ifdef SRP
1005
`define MODULE srp
1006
module `BASE`MODULE ( s, rp, q, clk, rst);
1007
`undef MODULE
1008
 
1009 29 unneback
        parameter width = 1;
1010
        parameter reset_value = 0;
1011
 
1012
        input s, rp;
1013
        output reg q;
1014
        input clk, rst;
1015
 
1016
        always @ (posedge clk or posedge rst)
1017
        if (rst)
1018
            q <= reset_value;
1019
        else
1020
            if (rp)
1021
                q <= 1'b0;
1022
            else if (s)
1023
                q <= 1'b1;
1024
 
1025
endmodule
1026 40 unneback
`endif
1027 29 unneback
 
1028 40 unneback
`ifdef ALTERA
1029 29 unneback
 
1030 40 unneback
`ifdef DFF_SR
1031 6 unneback
// megafunction wizard: %LPM_FF%
1032
// GENERATION: STANDARD
1033
// VERSION: WM1.0
1034
// MODULE: lpm_ff 
1035
 
1036
// ============================================================
1037
// File Name: dff_sr.v
1038
// Megafunction Name(s):
1039
//                      lpm_ff
1040
//
1041
// Simulation Library Files(s):
1042
//                      lpm
1043
// ============================================================
1044
// ************************************************************
1045
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
1046
//
1047
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
1048
// ************************************************************
1049
 
1050
 
1051
//Copyright (C) 1991-2010 Altera Corporation
1052
//Your use of Altera Corporation's design tools, logic functions 
1053
//and other software and tools, and its AMPP partner logic 
1054
//functions, and any output files from any of the foregoing 
1055
//(including device programming or simulation files), and any 
1056
//associated documentation or information are expressly subject 
1057
//to the terms and conditions of the Altera Program License 
1058
//Subscription Agreement, Altera MegaCore Function License 
1059
//Agreement, or other applicable license agreement, including, 
1060
//without limitation, that your use is for the sole purpose of 
1061
//programming logic devices manufactured by Altera and sold by 
1062
//Altera or its authorized distributors.  Please refer to the 
1063
//applicable agreement for further details.
1064
 
1065
 
1066
// synopsys translate_off
1067
`timescale 1 ps / 1 ps
1068
// synopsys translate_on
1069 40 unneback
`define MODULE dff_sr
1070
module `BASE`MODULE (
1071
`undef MODULE
1072
 
1073 6 unneback
        aclr,
1074
        aset,
1075
        clock,
1076
        data,
1077
        q);
1078
 
1079
        input     aclr;
1080
        input     aset;
1081
        input     clock;
1082
        input     data;
1083
        output    q;
1084
 
1085
        wire [0:0] sub_wire0;
1086
        wire [0:0] sub_wire1 = sub_wire0[0:0];
1087
        wire  q = sub_wire1;
1088
        wire  sub_wire2 = data;
1089
        wire  sub_wire3 = sub_wire2;
1090
 
1091
        lpm_ff  lpm_ff_component (
1092
                                .aclr (aclr),
1093
                                .clock (clock),
1094
                                .data (sub_wire3),
1095
                                .aset (aset),
1096
                                .q (sub_wire0)
1097
                                // synopsys translate_off
1098
                                ,
1099
                                .aload (),
1100
                                .enable (),
1101
                                .sclr (),
1102
                                .sload (),
1103
                                .sset ()
1104
                                // synopsys translate_on
1105
                                );
1106
        defparam
1107
                lpm_ff_component.lpm_fftype = "DFF",
1108
                lpm_ff_component.lpm_type = "LPM_FF",
1109
                lpm_ff_component.lpm_width = 1;
1110
 
1111
 
1112
endmodule
1113
 
1114
// ============================================================
1115
// CNX file retrieval info
1116
// ============================================================
1117
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1118
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1119
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1120
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1121
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1122
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1123
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1124
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1125
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1126
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1127
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1128
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1129
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1130
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1131
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1132
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1133
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1134
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1135
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1136
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1137
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1138
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1139
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1140
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1141
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1142
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1143
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1144
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1145
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1146
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1147
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1148
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1149
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1150
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1151
// Retrieval info: LIB_FILE: lpm
1152 40 unneback
`endif
1153 6 unneback
 
1154
`else
1155
 
1156 40 unneback
`ifdef DFF_SR
1157
`define MODULE dff_sr
1158
module `BASE`MODULE ( aclr, aset, clock, data, q);
1159
`undef MODULE
1160 6 unneback
 
1161
    input         aclr;
1162
    input         aset;
1163
    input         clock;
1164
    input         data;
1165
    output reg    q;
1166
 
1167
   always @ (posedge clock or posedge aclr or posedge aset)
1168
     if (aclr)
1169
       q <= 1'b0;
1170
     else if (aset)
1171
       q <= 1'b1;
1172
     else
1173
       q <= data;
1174
 
1175
endmodule
1176 40 unneback
`endif
1177 6 unneback
 
1178
`endif
1179
 
1180
// LATCH
1181
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1182
`ifdef ALTERA
1183 40 unneback
 
1184
`ifdef LATCH
1185
`define MODULE latch
1186
module `BASE`MODULE ( d, le, q, clk);
1187
`undef MODULE
1188 6 unneback
input d, le;
1189
output q;
1190
input clk;
1191
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1192
endmodule
1193 40 unneback
`endif
1194
 
1195 6 unneback
`else
1196 40 unneback
 
1197
`ifdef LATCH
1198
`define MODULE latch
1199
module `BASE`MODULE ( d, le, q, clk);
1200
`undef MODULE
1201 6 unneback
input d, le;
1202 48 unneback
input clk;
1203
always @ (le or d)
1204 60 unneback
if (le)
1205 48 unneback
    d <= q;
1206 6 unneback
endmodule
1207 15 unneback
`endif
1208
 
1209 40 unneback
`endif
1210
 
1211
`ifdef SHREG
1212
`define MODULE shreg
1213
module `BASE`MODULE ( d, q, clk, rst);
1214
`undef MODULE
1215
 
1216 17 unneback
parameter depth = 10;
1217
input d;
1218
output q;
1219
input clk, rst;
1220
 
1221
reg [1:depth] dffs;
1222
 
1223
always @ (posedge clk or posedge rst)
1224
if (rst)
1225
    dffs <= {depth{1'b0}};
1226
else
1227
    dffs <= {d,dffs[1:depth-1]};
1228
assign q = dffs[depth];
1229
endmodule
1230 40 unneback
`endif
1231 17 unneback
 
1232 40 unneback
`ifdef SHREG_CE
1233
`define MODULE shreg_ce
1234
module `BASE`MODULE ( d, ce, q, clk, rst);
1235
`undef MODULE
1236 17 unneback
parameter depth = 10;
1237
input d, ce;
1238
output q;
1239
input clk, rst;
1240
 
1241
reg [1:depth] dffs;
1242
 
1243
always @ (posedge clk or posedge rst)
1244
if (rst)
1245
    dffs <= {depth{1'b0}};
1246
else
1247
    if (ce)
1248
        dffs <= {d,dffs[1:depth-1]};
1249
assign q = dffs[depth];
1250
endmodule
1251 40 unneback
`endif
1252 17 unneback
 
1253 40 unneback
`ifdef DELAY
1254
`define MODULE delay
1255
module `BASE`MODULE ( d, q, clk, rst);
1256
`undef MODULE
1257 15 unneback
parameter depth = 10;
1258
input d;
1259
output q;
1260
input clk, rst;
1261
 
1262
reg [1:depth] dffs;
1263
 
1264
always @ (posedge clk or posedge rst)
1265
if (rst)
1266
    dffs <= {depth{1'b0}};
1267
else
1268
    dffs <= {d,dffs[1:depth-1]};
1269
assign q = dffs[depth];
1270 17 unneback
endmodule
1271 40 unneback
`endif
1272 17 unneback
 
1273 40 unneback
`ifdef DELAY_EMPTYFLAG
1274
`define MODULE delay_emptyflag
1275 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1276 40 unneback
`undef MODULE
1277 17 unneback
parameter depth = 10;
1278
input d;
1279
output q, emptyflag;
1280
input clk, rst;
1281
 
1282
reg [1:depth] dffs;
1283
 
1284
always @ (posedge clk or posedge rst)
1285
if (rst)
1286
    dffs <= {depth{1'b0}};
1287
else
1288
    dffs <= {d,dffs[1:depth-1]};
1289
assign q = dffs[depth];
1290
assign emptyflag = !(|dffs);
1291
endmodule
1292 40 unneback
`endif
1293 75 unneback
 
1294 94 unneback
`ifdef PULSE2TOGGLE
1295 98 unneback
`define MODULE pulse2toggle
1296
module `BASE`MODULE ( pl, q, clk, rst);
1297 75 unneback
`undef MODULE
1298 94 unneback
input pl;
1299 98 unneback
output reg q;
1300 94 unneback
input clk, rst;
1301
always @ (posedge clk or posedge rst)
1302 75 unneback
if (rst)
1303 94 unneback
    q <= 1'b0;
1304 75 unneback
else
1305 94 unneback
    q <= pl ^ q;
1306
endmodule
1307
`endif
1308 75 unneback
 
1309 94 unneback
`ifdef TOGGLE2PULSE
1310 98 unneback
`define MODULE toggle2pulse
1311 94 unneback
module `BASE`MODULE (d, pl, clk, rst);
1312 97 unneback
`undef MODULE
1313 94 unneback
input d;
1314
output pl;
1315
input clk, rst;
1316
reg dff;
1317
always @ (posedge clk or posedge rst)
1318
if (rst)
1319
    dff <= 1'b0;
1320 75 unneback
else
1321 94 unneback
    dff <= d;
1322 98 unneback
assign pl = d ^ dff;
1323 94 unneback
endmodule
1324
`endif
1325 75 unneback
 
1326 94 unneback
`ifdef SYNCHRONIZER
1327
`define MODULE synchronizer
1328
module `BASE`MODULE (d, q, clk, rst);
1329
`undef MODULE
1330
input d;
1331
output reg q;
1332 116 unneback
input clk, rst;
1333 94 unneback
reg dff;
1334
always @ (posedge clk or posedge rst)
1335
if (rst)
1336 100 unneback
    {q,dff} <= 2'b00;
1337 75 unneback
else
1338 100 unneback
    {q,dff} <= {dff,d};
1339 94 unneback
endmodule
1340
`endif
1341 75 unneback
 
1342 94 unneback
`ifdef CDC
1343
`define MODULE cdc
1344 97 unneback
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1345 94 unneback
`undef MODULE
1346
input start_pl;
1347
output take_it_pl;
1348
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1349
output got_it_pl;
1350
input clk_src, rst_src;
1351
input clk_dst, rst_dst;
1352
wire take_it_tg, take_it_tg_sync;
1353
wire got_it_tg, got_it_tg_sync;
1354
// src -> dst
1355
`define MODULE pulse2toggle
1356
`BASE`MODULE p2t0 (
1357
`undef MODULE
1358
    .pl(start_pl),
1359
    .q(take_it_tg),
1360
    .clk(clk_src),
1361
    .rst(rst_src));
1362 75 unneback
 
1363 94 unneback
`define MODULE synchronizer
1364
`BASE`MODULE sync0 (
1365
`undef MODULE
1366
    .d(take_it_tg),
1367
    .q(take_it_tg_sync),
1368
    .clk(clk_dst),
1369
    .rst(rst_dst));
1370
 
1371
`define MODULE toggle2pulse
1372
`BASE`MODULE t2p0 (
1373
`undef MODULE
1374 100 unneback
    .d(take_it_tg_sync),
1375 94 unneback
    .pl(take_it_pl),
1376
    .clk(clk_dst),
1377
    .rst(rst_dst));
1378
 
1379
// dst -> src
1380
`define MODULE pulse2toggle
1381 98 unneback
`BASE`MODULE p2t1 (
1382 94 unneback
`undef MODULE
1383
    .pl(take_it_grant_pl),
1384
    .q(got_it_tg),
1385
    .clk(clk_dst),
1386
    .rst(rst_dst));
1387
 
1388
`define MODULE synchronizer
1389
`BASE`MODULE sync1 (
1390
`undef MODULE
1391
    .d(got_it_tg),
1392
    .q(got_it_tg_sync),
1393
    .clk(clk_src),
1394
    .rst(rst_src));
1395
 
1396
`define MODULE toggle2pulse
1397
`BASE`MODULE t2p1 (
1398
`undef MODULE
1399 100 unneback
    .d(got_it_tg_sync),
1400 94 unneback
    .pl(got_it_pl),
1401
    .clk(clk_src),
1402
    .rst(rst_src));
1403
 
1404 75 unneback
endmodule
1405
`endif
1406 17 unneback
//////////////////////////////////////////////////////////////////////
1407 6 unneback
////                                                              ////
1408 18 unneback
////  Logic functions                                             ////
1409
////                                                              ////
1410
////  Description                                                 ////
1411
////  Logic functions such as multiplexers                        ////
1412
////                                                              ////
1413
////                                                              ////
1414
////  To Do:                                                      ////
1415
////   -                                                          ////
1416
////                                                              ////
1417
////  Author(s):                                                  ////
1418
////      - Michael Unneback, unneback@opencores.org              ////
1419
////        ORSoC AB                                              ////
1420
////                                                              ////
1421
//////////////////////////////////////////////////////////////////////
1422
////                                                              ////
1423
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1424
////                                                              ////
1425
//// This source file may be used and distributed without         ////
1426
//// restriction provided that this copyright statement is not    ////
1427
//// removed from the file and that any derivative work contains  ////
1428
//// the original copyright notice and the associated disclaimer. ////
1429
////                                                              ////
1430
//// This source file is free software; you can redistribute it   ////
1431
//// and/or modify it under the terms of the GNU Lesser General   ////
1432
//// Public License as published by the Free Software Foundation; ////
1433
//// either version 2.1 of the License, or (at your option) any   ////
1434
//// later version.                                               ////
1435
////                                                              ////
1436
//// This source is distributed in the hope that it will be       ////
1437
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1438
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1439
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1440
//// details.                                                     ////
1441
////                                                              ////
1442
//// You should have received a copy of the GNU Lesser General    ////
1443
//// Public License along with this source; if not, download it   ////
1444
//// from http://www.opencores.org/lgpl.shtml                     ////
1445
////                                                              ////
1446
//////////////////////////////////////////////////////////////////////
1447 40 unneback
`ifdef MUX_ANDOR
1448
`define MODULE mux_andor
1449
module `BASE`MODULE ( a, sel, dout);
1450
`undef MODULE
1451 36 unneback
 
1452
parameter width = 32;
1453
parameter nr_of_ports = 4;
1454
 
1455
input [nr_of_ports*width-1:0] a;
1456
input [nr_of_ports-1:0] sel;
1457
output reg [width-1:0] dout;
1458
 
1459 38 unneback
integer i,j;
1460
 
1461 36 unneback
always @ (a, sel)
1462
begin
1463
    dout = a[width-1:0] & {width{sel[0]}};
1464 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1465
        for (j=0;j<width;j=j+1)
1466
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1467 36 unneback
end
1468
 
1469
endmodule
1470 40 unneback
`endif
1471 36 unneback
 
1472 40 unneback
`ifdef MUX2_ANDOR
1473
`define MODULE mux2_andor
1474
module `BASE`MODULE ( a1, a0, sel, dout);
1475
`undef MODULE
1476 18 unneback
 
1477 34 unneback
parameter width = 32;
1478 35 unneback
localparam nr_of_ports = 2;
1479 34 unneback
input [width-1:0] a1, a0;
1480
input [nr_of_ports-1:0] sel;
1481
output [width-1:0] dout;
1482
 
1483 40 unneback
`define MODULE mux_andor
1484
`BASE`MODULE
1485 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1486 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1487 40 unneback
`undef MODULE
1488
 
1489 34 unneback
endmodule
1490 40 unneback
`endif
1491 34 unneback
 
1492 40 unneback
`ifdef MUX3_ANDOR
1493
`define MODULE mux3_andor
1494
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1495
`undef MODULE
1496 34 unneback
 
1497
parameter width = 32;
1498 35 unneback
localparam nr_of_ports = 3;
1499 34 unneback
input [width-1:0] a2, a1, a0;
1500
input [nr_of_ports-1:0] sel;
1501
output [width-1:0] dout;
1502
 
1503 40 unneback
`define MODULE mux_andor
1504
`BASE`MODULE
1505 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1506 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1507 40 unneback
`undef MODULE
1508 34 unneback
endmodule
1509 40 unneback
`endif
1510 34 unneback
 
1511 40 unneback
`ifdef MUX4_ANDOR
1512
`define MODULE mux4_andor
1513
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1514
`undef MODULE
1515 18 unneback
 
1516
parameter width = 32;
1517 35 unneback
localparam nr_of_ports = 4;
1518 18 unneback
input [width-1:0] a3, a2, a1, a0;
1519
input [nr_of_ports-1:0] sel;
1520 22 unneback
output [width-1:0] dout;
1521 18 unneback
 
1522 40 unneback
`define MODULE mux_andor
1523
`BASE`MODULE
1524 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1525 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1526 40 unneback
`undef MODULE
1527 18 unneback
 
1528
endmodule
1529 40 unneback
`endif
1530 18 unneback
 
1531 40 unneback
`ifdef MUX5_ANDOR
1532
`define MODULE mux5_andor
1533
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1534
`undef MODULE
1535 18 unneback
 
1536
parameter width = 32;
1537 35 unneback
localparam nr_of_ports = 5;
1538 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1539
input [nr_of_ports-1:0] sel;
1540 22 unneback
output [width-1:0] dout;
1541 18 unneback
 
1542 40 unneback
`define MODULE mux_andor
1543
`BASE`MODULE
1544 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1545 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1546 40 unneback
`undef MODULE
1547 18 unneback
 
1548
endmodule
1549 40 unneback
`endif
1550 18 unneback
 
1551 40 unneback
`ifdef MUX6_ANDOR
1552
`define MODULE mux6_andor
1553
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1554
`undef MODULE
1555 18 unneback
 
1556
parameter width = 32;
1557 35 unneback
localparam nr_of_ports = 6;
1558 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1559
input [nr_of_ports-1:0] sel;
1560 22 unneback
output [width-1:0] dout;
1561 18 unneback
 
1562 40 unneback
`define MODULE mux_andor
1563
`BASE`MODULE
1564 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1565 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1566 40 unneback
`undef MODULE
1567 18 unneback
 
1568
endmodule
1569 40 unneback
`endif
1570 43 unneback
 
1571
`ifdef PARITY
1572
 
1573
`define MODULE parity_generate
1574
module `BASE`MODULE (data, parity);
1575
`undef MODULE
1576
parameter word_size = 32;
1577
parameter chunk_size = 8;
1578
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1579
input [word_size-1:0] data;
1580
output reg [word_size/chunk_size-1:0] parity;
1581
integer i,j;
1582
always @ (data)
1583
for (i=0;i<word_size/chunk_size;i=i+1) begin
1584
    parity[i] = parity_type;
1585
    for (j=0;j<chunk_size;j=j+1) begin
1586 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1587 43 unneback
    end
1588
end
1589
endmodule
1590
 
1591
`define MODULE parity_check
1592
module `BASE`MODULE( data, parity, parity_error);
1593
`undef MODULE
1594
parameter word_size = 32;
1595
parameter chunk_size = 8;
1596
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1597
input [word_size-1:0] data;
1598
input [word_size/chunk_size-1:0] parity;
1599
output parity_error;
1600 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1601 43 unneback
integer i,j;
1602
always @ (data or parity)
1603
for (i=0;i<word_size/chunk_size;i=i+1) begin
1604
    error_flag[i] = parity[i] ^ parity_type;
1605
    for (j=0;j<chunk_size;j=j+1) begin
1606 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1607 43 unneback
    end
1608
end
1609
assign parity_error = |error_flag;
1610
endmodule
1611
 
1612 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1613
////                                                              ////
1614
////  IO functions                                                ////
1615
////                                                              ////
1616
////  Description                                                 ////
1617
////  IO functions such as IOB flip-flops                         ////
1618
////                                                              ////
1619
////                                                              ////
1620
////  To Do:                                                      ////
1621
////   -                                                          ////
1622
////                                                              ////
1623
////  Author(s):                                                  ////
1624
////      - Michael Unneback, unneback@opencores.org              ////
1625
////        ORSoC AB                                              ////
1626
////                                                              ////
1627 18 unneback
//////////////////////////////////////////////////////////////////////
1628
////                                                              ////
1629 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1630
////                                                              ////
1631
//// This source file may be used and distributed without         ////
1632
//// restriction provided that this copyright statement is not    ////
1633
//// removed from the file and that any derivative work contains  ////
1634
//// the original copyright notice and the associated disclaimer. ////
1635
////                                                              ////
1636
//// This source file is free software; you can redistribute it   ////
1637
//// and/or modify it under the terms of the GNU Lesser General   ////
1638
//// Public License as published by the Free Software Foundation; ////
1639
//// either version 2.1 of the License, or (at your option) any   ////
1640
//// later version.                                               ////
1641
////                                                              ////
1642
//// This source is distributed in the hope that it will be       ////
1643
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1644
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1645
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1646
//// details.                                                     ////
1647
////                                                              ////
1648
//// You should have received a copy of the GNU Lesser General    ////
1649
//// Public License along with this source; if not, download it   ////
1650
//// from http://www.opencores.org/lgpl.shtml                     ////
1651
////                                                              ////
1652
//////////////////////////////////////////////////////////////////////
1653 136 unneback
`ifdef O_DFF
1654 45 unneback
`timescale 1ns/1ns
1655 44 unneback
`define MODULE o_dff
1656
module `BASE`MODULE (d_i, o_pad, clk, rst);
1657
`undef MODULE
1658
parameter width = 1;
1659 45 unneback
parameter reset_value = {width{1'b0}};
1660
input  [width-1:0]  d_i;
1661 44 unneback
output [width-1:0] o_pad;
1662
input clk, rst;
1663
wire [width-1:0] d_i_int `SYN_KEEP;
1664 45 unneback
reg  [width-1:0] o_pad_int;
1665 44 unneback
assign d_i_int = d_i;
1666
genvar i;
1667 45 unneback
generate
1668 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
1669 44 unneback
    always @ (posedge clk or posedge rst)
1670
    if (rst)
1671 45 unneback
        o_pad_int[i] <= reset_value[i];
1672 44 unneback
    else
1673 45 unneback
        o_pad_int[i] <= d_i_int[i];
1674
    assign #1 o_pad[i] = o_pad_int[i];
1675 44 unneback
end
1676
endgenerate
1677
endmodule
1678
`endif
1679
 
1680 136 unneback
`ifdef IO_DFF_OE
1681 45 unneback
`timescale 1ns/1ns
1682 44 unneback
`define MODULE io_dff_oe
1683
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1684
`undef MODULE
1685
parameter width = 1;
1686
input  [width-1:0] d_o;
1687
output reg [width-1:0] d_i;
1688
input oe;
1689
inout [width-1:0] io_pad;
1690
input clk, rst;
1691
wire [width-1:0] oe_d `SYN_KEEP;
1692
reg [width-1:0] oe_q;
1693
reg [width-1:0] d_o_q;
1694
assign oe_d = {width{oe}};
1695
genvar i;
1696
generate
1697 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
1698 44 unneback
    always @ (posedge clk or posedge rst)
1699
    if (rst)
1700
        oe_q[i] <= 1'b0;
1701
    else
1702
        oe_q[i] <= oe_d[i];
1703
    always @ (posedge clk or posedge rst)
1704
    if (rst)
1705
        d_o_q[i] <= 1'b0;
1706
    else
1707
        d_o_q[i] <= d_o[i];
1708
    always @ (posedge clk or posedge rst)
1709
    if (rst)
1710
        d_i[i] <= 1'b0;
1711
    else
1712
        d_i[i] <= io_pad[i];
1713 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1714 44 unneback
end
1715
endgenerate
1716
endmodule
1717
`endif
1718 136 unneback
 
1719
`ifdef O_DDR
1720
`ifdef ALTERA
1721
`define MODULE o_ddr
1722
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
1723
`undef MODULE
1724
parameter width = 1;
1725
input  [width-1:0] d_h_i, d_l_i;
1726
output [width-1:0] o_pad;
1727
input clk, rst;
1728
genvar i;
1729
generate
1730
for (i=0;i<width;i=i+1) begin : ddr
1731
    ddio_out ddio_out0( .aclr(rst), .datain_h(d_h_i[i]), .datain_l(d_l_i[i]), .outclock(clk), .dataout(o_pad[i]) );
1732
end
1733
endgenerate
1734
endmodule
1735
`else
1736
`define MODULE o_ddr
1737
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
1738
`undef MODULE
1739
parameter width = 1;
1740
input  [width-1:0] d_h_i, d_l_i;
1741
output [width-1:0] o_pad;
1742
input clk, rst;
1743
reg [width-1:0] ff1;
1744
reg [width-1:0] ff2;
1745
genvar i;
1746
generate
1747
for (i=0;i<width;i=i+1) begin : ddr
1748
    always @ (posedge clk or posedge rst)
1749
    if (rst)
1750
        ff1[i] <= 1'b0;
1751
    else
1752
        ff1[i] <= d_h_i[i];
1753
    always @ (posedge clk or posedge rst)
1754
    if (rst)
1755
        ff2[i] <= 1'b0;
1756
    else
1757
        ff2[i] <= d_l_i[i];
1758
    assign o_pad = (clk) ? ff1 : ff2;
1759
end
1760
endgenerate
1761
endmodule
1762
`endif
1763
`endif
1764
 
1765
`ifdef O_CLK
1766
`define MODULE o_clk
1767
module `BASE`MODULE ( clk_o_pad, clk, rst);
1768
`undef MODULE
1769
input clk, rst;
1770
output clk_o_pad;
1771
`define MODULE o_ddr
1772
`BASE`MODULE o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
1773
`undef MODULE
1774
endmodule
1775
`endif`ifdef CNT_BIN
1776 44 unneback
//////////////////////////////////////////////////////////////////////
1777
////                                                              ////
1778 6 unneback
////  Versatile counter                                           ////
1779
////                                                              ////
1780
////  Description                                                 ////
1781
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1782
////  counter                                                     ////
1783
////                                                              ////
1784
////  To Do:                                                      ////
1785
////   - add LFSR with more taps                                  ////
1786
////                                                              ////
1787
////  Author(s):                                                  ////
1788
////      - Michael Unneback, unneback@opencores.org              ////
1789
////        ORSoC AB                                              ////
1790
////                                                              ////
1791
//////////////////////////////////////////////////////////////////////
1792
////                                                              ////
1793
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1794
////                                                              ////
1795
//// This source file may be used and distributed without         ////
1796
//// restriction provided that this copyright statement is not    ////
1797
//// removed from the file and that any derivative work contains  ////
1798
//// the original copyright notice and the associated disclaimer. ////
1799
////                                                              ////
1800
//// This source file is free software; you can redistribute it   ////
1801
//// and/or modify it under the terms of the GNU Lesser General   ////
1802
//// Public License as published by the Free Software Foundation; ////
1803
//// either version 2.1 of the License, or (at your option) any   ////
1804
//// later version.                                               ////
1805
////                                                              ////
1806
//// This source is distributed in the hope that it will be       ////
1807
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1808
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1809
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1810
//// details.                                                     ////
1811
////                                                              ////
1812
//// You should have received a copy of the GNU Lesser General    ////
1813
//// Public License along with this source; if not, download it   ////
1814
//// from http://www.opencores.org/lgpl.shtml                     ////
1815
////                                                              ////
1816
//////////////////////////////////////////////////////////////////////
1817
 
1818
// binary counter
1819 22 unneback
 
1820 40 unneback
`define MODULE cnt_bin
1821
module `BASE`MODULE (
1822
`undef MODULE
1823
 q, rst, clk);
1824
 
1825 22 unneback
   parameter length = 4;
1826
   output [length:1] q;
1827
   input rst;
1828
   input clk;
1829
 
1830
   parameter clear_value = 0;
1831
   parameter set_value = 1;
1832
   parameter wrap_value = 0;
1833
   parameter level1_value = 15;
1834
 
1835
   reg  [length:1] qi;
1836
   wire [length:1] q_next;
1837
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1838
 
1839
   always @ (posedge clk or posedge rst)
1840
     if (rst)
1841
       qi <= {length{1'b0}};
1842
     else
1843
       qi <= q_next;
1844
 
1845
   assign q = qi;
1846
 
1847
endmodule
1848 40 unneback
`endif
1849
`ifdef CNT_BIN_CLEAR
1850 22 unneback
//////////////////////////////////////////////////////////////////////
1851
////                                                              ////
1852
////  Versatile counter                                           ////
1853
////                                                              ////
1854
////  Description                                                 ////
1855
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1856
////  counter                                                     ////
1857
////                                                              ////
1858
////  To Do:                                                      ////
1859
////   - add LFSR with more taps                                  ////
1860
////                                                              ////
1861
////  Author(s):                                                  ////
1862
////      - Michael Unneback, unneback@opencores.org              ////
1863
////        ORSoC AB                                              ////
1864
////                                                              ////
1865
//////////////////////////////////////////////////////////////////////
1866
////                                                              ////
1867
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1868
////                                                              ////
1869
//// This source file may be used and distributed without         ////
1870
//// restriction provided that this copyright statement is not    ////
1871
//// removed from the file and that any derivative work contains  ////
1872
//// the original copyright notice and the associated disclaimer. ////
1873
////                                                              ////
1874
//// This source file is free software; you can redistribute it   ////
1875
//// and/or modify it under the terms of the GNU Lesser General   ////
1876
//// Public License as published by the Free Software Foundation; ////
1877
//// either version 2.1 of the License, or (at your option) any   ////
1878
//// later version.                                               ////
1879
////                                                              ////
1880
//// This source is distributed in the hope that it will be       ////
1881
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1882
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1883
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1884
//// details.                                                     ////
1885
////                                                              ////
1886
//// You should have received a copy of the GNU Lesser General    ////
1887
//// Public License along with this source; if not, download it   ////
1888
//// from http://www.opencores.org/lgpl.shtml                     ////
1889
////                                                              ////
1890
//////////////////////////////////////////////////////////////////////
1891
 
1892
// binary counter
1893
 
1894 40 unneback
`define MODULE cnt_bin_clear
1895
module `BASE`MODULE (
1896
`undef MODULE
1897
 clear, q, rst, clk);
1898
 
1899 22 unneback
   parameter length = 4;
1900
   input clear;
1901
   output [length:1] q;
1902
   input rst;
1903
   input clk;
1904
 
1905
   parameter clear_value = 0;
1906
   parameter set_value = 1;
1907
   parameter wrap_value = 0;
1908
   parameter level1_value = 15;
1909
 
1910
   reg  [length:1] qi;
1911
   wire [length:1] q_next;
1912
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1913
 
1914
   always @ (posedge clk or posedge rst)
1915
     if (rst)
1916
       qi <= {length{1'b0}};
1917
     else
1918
       qi <= q_next;
1919
 
1920
   assign q = qi;
1921
 
1922
endmodule
1923 40 unneback
`endif
1924
`ifdef CNT_BIN_CE
1925 22 unneback
//////////////////////////////////////////////////////////////////////
1926
////                                                              ////
1927
////  Versatile counter                                           ////
1928
////                                                              ////
1929
////  Description                                                 ////
1930
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1931
////  counter                                                     ////
1932
////                                                              ////
1933
////  To Do:                                                      ////
1934
////   - add LFSR with more taps                                  ////
1935
////                                                              ////
1936
////  Author(s):                                                  ////
1937
////      - Michael Unneback, unneback@opencores.org              ////
1938
////        ORSoC AB                                              ////
1939
////                                                              ////
1940
//////////////////////////////////////////////////////////////////////
1941
////                                                              ////
1942
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1943
////                                                              ////
1944
//// This source file may be used and distributed without         ////
1945
//// restriction provided that this copyright statement is not    ////
1946
//// removed from the file and that any derivative work contains  ////
1947
//// the original copyright notice and the associated disclaimer. ////
1948
////                                                              ////
1949
//// This source file is free software; you can redistribute it   ////
1950
//// and/or modify it under the terms of the GNU Lesser General   ////
1951
//// Public License as published by the Free Software Foundation; ////
1952
//// either version 2.1 of the License, or (at your option) any   ////
1953
//// later version.                                               ////
1954
////                                                              ////
1955
//// This source is distributed in the hope that it will be       ////
1956
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1957
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1958
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1959
//// details.                                                     ////
1960
////                                                              ////
1961
//// You should have received a copy of the GNU Lesser General    ////
1962
//// Public License along with this source; if not, download it   ////
1963
//// from http://www.opencores.org/lgpl.shtml                     ////
1964
////                                                              ////
1965
//////////////////////////////////////////////////////////////////////
1966
 
1967
// binary counter
1968 6 unneback
 
1969 40 unneback
`define MODULE cnt_bin_ce
1970
module `BASE`MODULE (
1971
`undef MODULE
1972
 cke, q, rst, clk);
1973
 
1974 6 unneback
   parameter length = 4;
1975
   input cke;
1976
   output [length:1] q;
1977
   input rst;
1978
   input clk;
1979
 
1980
   parameter clear_value = 0;
1981
   parameter set_value = 1;
1982
   parameter wrap_value = 0;
1983
   parameter level1_value = 15;
1984
 
1985
   reg  [length:1] qi;
1986
   wire [length:1] q_next;
1987
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1988
 
1989
   always @ (posedge clk or posedge rst)
1990
     if (rst)
1991
       qi <= {length{1'b0}};
1992
     else
1993
     if (cke)
1994
       qi <= q_next;
1995
 
1996
   assign q = qi;
1997
 
1998
endmodule
1999 40 unneback
`endif
2000
`ifdef CNT_BIN_CE_CLEAR
2001 6 unneback
//////////////////////////////////////////////////////////////////////
2002
////                                                              ////
2003
////  Versatile counter                                           ////
2004
////                                                              ////
2005
////  Description                                                 ////
2006
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2007
////  counter                                                     ////
2008
////                                                              ////
2009
////  To Do:                                                      ////
2010
////   - add LFSR with more taps                                  ////
2011
////                                                              ////
2012
////  Author(s):                                                  ////
2013
////      - Michael Unneback, unneback@opencores.org              ////
2014
////        ORSoC AB                                              ////
2015
////                                                              ////
2016
//////////////////////////////////////////////////////////////////////
2017
////                                                              ////
2018
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2019
////                                                              ////
2020
//// This source file may be used and distributed without         ////
2021
//// restriction provided that this copyright statement is not    ////
2022
//// removed from the file and that any derivative work contains  ////
2023
//// the original copyright notice and the associated disclaimer. ////
2024
////                                                              ////
2025
//// This source file is free software; you can redistribute it   ////
2026
//// and/or modify it under the terms of the GNU Lesser General   ////
2027
//// Public License as published by the Free Software Foundation; ////
2028
//// either version 2.1 of the License, or (at your option) any   ////
2029
//// later version.                                               ////
2030
////                                                              ////
2031
//// This source is distributed in the hope that it will be       ////
2032
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2033
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2034
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2035
//// details.                                                     ////
2036
////                                                              ////
2037
//// You should have received a copy of the GNU Lesser General    ////
2038
//// Public License along with this source; if not, download it   ////
2039
//// from http://www.opencores.org/lgpl.shtml                     ////
2040
////                                                              ////
2041
//////////////////////////////////////////////////////////////////////
2042
 
2043
// binary counter
2044
 
2045 40 unneback
`define MODULE cnt_bin_ce_clear
2046
module `BASE`MODULE (
2047
`undef MODULE
2048
 clear, cke, q, rst, clk);
2049
 
2050 6 unneback
   parameter length = 4;
2051
   input clear;
2052
   input cke;
2053
   output [length:1] q;
2054
   input rst;
2055
   input clk;
2056
 
2057
   parameter clear_value = 0;
2058
   parameter set_value = 1;
2059
   parameter wrap_value = 0;
2060
   parameter level1_value = 15;
2061
 
2062
   reg  [length:1] qi;
2063
   wire [length:1] q_next;
2064
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2065
 
2066
   always @ (posedge clk or posedge rst)
2067
     if (rst)
2068
       qi <= {length{1'b0}};
2069
     else
2070
     if (cke)
2071
       qi <= q_next;
2072
 
2073
   assign q = qi;
2074
 
2075
endmodule
2076 40 unneback
`endif
2077
`ifdef CNT_BIN_CE_CLEAR_L1_L2
2078 6 unneback
//////////////////////////////////////////////////////////////////////
2079
////                                                              ////
2080
////  Versatile counter                                           ////
2081
////                                                              ////
2082
////  Description                                                 ////
2083
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2084
////  counter                                                     ////
2085
////                                                              ////
2086
////  To Do:                                                      ////
2087
////   - add LFSR with more taps                                  ////
2088
////                                                              ////
2089
////  Author(s):                                                  ////
2090
////      - Michael Unneback, unneback@opencores.org              ////
2091
////        ORSoC AB                                              ////
2092
////                                                              ////
2093
//////////////////////////////////////////////////////////////////////
2094
////                                                              ////
2095
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2096
////                                                              ////
2097
//// This source file may be used and distributed without         ////
2098
//// restriction provided that this copyright statement is not    ////
2099
//// removed from the file and that any derivative work contains  ////
2100
//// the original copyright notice and the associated disclaimer. ////
2101
////                                                              ////
2102
//// This source file is free software; you can redistribute it   ////
2103
//// and/or modify it under the terms of the GNU Lesser General   ////
2104
//// Public License as published by the Free Software Foundation; ////
2105
//// either version 2.1 of the License, or (at your option) any   ////
2106
//// later version.                                               ////
2107
////                                                              ////
2108
//// This source is distributed in the hope that it will be       ////
2109
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2110
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2111
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2112
//// details.                                                     ////
2113
////                                                              ////
2114
//// You should have received a copy of the GNU Lesser General    ////
2115
//// Public License along with this source; if not, download it   ////
2116
//// from http://www.opencores.org/lgpl.shtml                     ////
2117
////                                                              ////
2118
//////////////////////////////////////////////////////////////////////
2119
 
2120
// binary counter
2121 29 unneback
 
2122 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
2123
module `BASE`MODULE (
2124
`undef MODULE
2125
 clear, cke, q, level1, level2, rst, clk);
2126
 
2127 29 unneback
   parameter length = 4;
2128
   input clear;
2129
   input cke;
2130
   output [length:1] q;
2131
   output reg level1;
2132
   output reg level2;
2133
   input rst;
2134
   input clk;
2135
 
2136
   parameter clear_value = 0;
2137
   parameter set_value = 1;
2138 30 unneback
   parameter wrap_value = 15;
2139
   parameter level1_value = 8;
2140
   parameter level2_value = 15;
2141 29 unneback
 
2142
   wire rew;
2143 30 unneback
   assign rew = 1'b0;
2144 29 unneback
   reg  [length:1] qi;
2145
   wire [length:1] q_next;
2146
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2147
 
2148
   always @ (posedge clk or posedge rst)
2149
     if (rst)
2150
       qi <= {length{1'b0}};
2151
     else
2152
     if (cke)
2153
       qi <= q_next;
2154
 
2155
   assign q = qi;
2156
 
2157
 
2158
    always @ (posedge clk or posedge rst)
2159
    if (rst)
2160
        level1 <= 1'b0;
2161
    else
2162
    if (cke)
2163
    if (clear)
2164
        level1 <= 1'b0;
2165
    else if (q_next == level1_value)
2166
        level1 <= 1'b1;
2167
    else if (qi == level1_value & rew)
2168
        level1 <= 1'b0;
2169
 
2170
    always @ (posedge clk or posedge rst)
2171
    if (rst)
2172
        level2 <= 1'b0;
2173
    else
2174
    if (cke)
2175
    if (clear)
2176
        level2 <= 1'b0;
2177
    else if (q_next == level2_value)
2178
        level2 <= 1'b1;
2179
    else if (qi == level2_value & rew)
2180
        level2 <= 1'b0;
2181
endmodule
2182 40 unneback
`endif
2183
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2184 29 unneback
//////////////////////////////////////////////////////////////////////
2185
////                                                              ////
2186
////  Versatile counter                                           ////
2187
////                                                              ////
2188
////  Description                                                 ////
2189
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2190
////  counter                                                     ////
2191
////                                                              ////
2192
////  To Do:                                                      ////
2193
////   - add LFSR with more taps                                  ////
2194
////                                                              ////
2195
////  Author(s):                                                  ////
2196
////      - Michael Unneback, unneback@opencores.org              ////
2197
////        ORSoC AB                                              ////
2198
////                                                              ////
2199
//////////////////////////////////////////////////////////////////////
2200
////                                                              ////
2201
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2202
////                                                              ////
2203
//// This source file may be used and distributed without         ////
2204
//// restriction provided that this copyright statement is not    ////
2205
//// removed from the file and that any derivative work contains  ////
2206
//// the original copyright notice and the associated disclaimer. ////
2207
////                                                              ////
2208
//// This source file is free software; you can redistribute it   ////
2209
//// and/or modify it under the terms of the GNU Lesser General   ////
2210
//// Public License as published by the Free Software Foundation; ////
2211
//// either version 2.1 of the License, or (at your option) any   ////
2212
//// later version.                                               ////
2213
////                                                              ////
2214
//// This source is distributed in the hope that it will be       ////
2215
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2216
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2217
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2218
//// details.                                                     ////
2219
////                                                              ////
2220
//// You should have received a copy of the GNU Lesser General    ////
2221
//// Public License along with this source; if not, download it   ////
2222
//// from http://www.opencores.org/lgpl.shtml                     ////
2223
////                                                              ////
2224
//////////////////////////////////////////////////////////////////////
2225
 
2226
// binary counter
2227 6 unneback
 
2228 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2229
module `BASE`MODULE (
2230
`undef MODULE
2231
 clear, set, cke, rew, q, rst, clk);
2232
 
2233 6 unneback
   parameter length = 4;
2234
   input clear;
2235
   input set;
2236
   input cke;
2237
   input rew;
2238
   output [length:1] q;
2239
   input rst;
2240
   input clk;
2241
 
2242
   parameter clear_value = 0;
2243
   parameter set_value = 1;
2244
   parameter wrap_value = 0;
2245
   parameter level1_value = 15;
2246
 
2247
   reg  [length:1] qi;
2248
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2249
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2250
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2251
   assign q_next = rew ? q_next_rew : q_next_fw;
2252
 
2253
   always @ (posedge clk or posedge rst)
2254
     if (rst)
2255
       qi <= {length{1'b0}};
2256
     else
2257
     if (cke)
2258
       qi <= q_next;
2259
 
2260
   assign q = qi;
2261
 
2262
endmodule
2263 40 unneback
`endif
2264
`ifdef CNT_BIN_CE_REW_L1
2265 6 unneback
//////////////////////////////////////////////////////////////////////
2266
////                                                              ////
2267
////  Versatile counter                                           ////
2268
////                                                              ////
2269
////  Description                                                 ////
2270
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2271
////  counter                                                     ////
2272
////                                                              ////
2273
////  To Do:                                                      ////
2274
////   - add LFSR with more taps                                  ////
2275
////                                                              ////
2276
////  Author(s):                                                  ////
2277
////      - Michael Unneback, unneback@opencores.org              ////
2278
////        ORSoC AB                                              ////
2279
////                                                              ////
2280
//////////////////////////////////////////////////////////////////////
2281
////                                                              ////
2282
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2283
////                                                              ////
2284
//// This source file may be used and distributed without         ////
2285
//// restriction provided that this copyright statement is not    ////
2286
//// removed from the file and that any derivative work contains  ////
2287
//// the original copyright notice and the associated disclaimer. ////
2288
////                                                              ////
2289
//// This source file is free software; you can redistribute it   ////
2290
//// and/or modify it under the terms of the GNU Lesser General   ////
2291
//// Public License as published by the Free Software Foundation; ////
2292
//// either version 2.1 of the License, or (at your option) any   ////
2293
//// later version.                                               ////
2294
////                                                              ////
2295
//// This source is distributed in the hope that it will be       ////
2296
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2297
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2298
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2299
//// details.                                                     ////
2300
////                                                              ////
2301
//// You should have received a copy of the GNU Lesser General    ////
2302
//// Public License along with this source; if not, download it   ////
2303
//// from http://www.opencores.org/lgpl.shtml                     ////
2304
////                                                              ////
2305
//////////////////////////////////////////////////////////////////////
2306
 
2307
// binary counter
2308
 
2309 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2310
module `BASE`MODULE (
2311
`undef MODULE
2312
 cke, rew, level1, rst, clk);
2313
 
2314 6 unneback
   parameter length = 4;
2315
   input cke;
2316
   input rew;
2317
   output reg level1;
2318
   input rst;
2319
   input clk;
2320
 
2321
   parameter clear_value = 0;
2322
   parameter set_value = 1;
2323
   parameter wrap_value = 1;
2324
   parameter level1_value = 15;
2325
 
2326 29 unneback
   wire clear;
2327 30 unneback
   assign clear = 1'b0;
2328 6 unneback
   reg  [length:1] qi;
2329
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2330
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2331
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2332
   assign q_next = rew ? q_next_rew : q_next_fw;
2333
 
2334
   always @ (posedge clk or posedge rst)
2335
     if (rst)
2336
       qi <= {length{1'b0}};
2337
     else
2338
     if (cke)
2339
       qi <= q_next;
2340
 
2341
 
2342
 
2343
    always @ (posedge clk or posedge rst)
2344
    if (rst)
2345
        level1 <= 1'b0;
2346
    else
2347
    if (cke)
2348 29 unneback
    if (clear)
2349
        level1 <= 1'b0;
2350
    else if (q_next == level1_value)
2351 6 unneback
        level1 <= 1'b1;
2352
    else if (qi == level1_value & rew)
2353
        level1 <= 1'b0;
2354
endmodule
2355 40 unneback
`endif
2356
`ifdef CNT_BIN_CE_REW_ZQ_L1
2357 6 unneback
//////////////////////////////////////////////////////////////////////
2358
////                                                              ////
2359
////  Versatile counter                                           ////
2360
////                                                              ////
2361
////  Description                                                 ////
2362
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2363
////  counter                                                     ////
2364
////                                                              ////
2365
////  To Do:                                                      ////
2366
////   - add LFSR with more taps                                  ////
2367
////                                                              ////
2368
////  Author(s):                                                  ////
2369
////      - Michael Unneback, unneback@opencores.org              ////
2370
////        ORSoC AB                                              ////
2371
////                                                              ////
2372
//////////////////////////////////////////////////////////////////////
2373
////                                                              ////
2374
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2375
////                                                              ////
2376
//// This source file may be used and distributed without         ////
2377
//// restriction provided that this copyright statement is not    ////
2378
//// removed from the file and that any derivative work contains  ////
2379
//// the original copyright notice and the associated disclaimer. ////
2380
////                                                              ////
2381
//// This source file is free software; you can redistribute it   ////
2382
//// and/or modify it under the terms of the GNU Lesser General   ////
2383
//// Public License as published by the Free Software Foundation; ////
2384
//// either version 2.1 of the License, or (at your option) any   ////
2385
//// later version.                                               ////
2386
////                                                              ////
2387
//// This source is distributed in the hope that it will be       ////
2388
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2389
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2390
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2391
//// details.                                                     ////
2392
////                                                              ////
2393
//// You should have received a copy of the GNU Lesser General    ////
2394
//// Public License along with this source; if not, download it   ////
2395
//// from http://www.opencores.org/lgpl.shtml                     ////
2396
////                                                              ////
2397
//////////////////////////////////////////////////////////////////////
2398
 
2399 25 unneback
// binary counter
2400
 
2401 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2402
module `BASE`MODULE (
2403
`undef MODULE
2404
 cke, rew, zq, level1, rst, clk);
2405
 
2406 25 unneback
   parameter length = 4;
2407
   input cke;
2408
   input rew;
2409
   output reg zq;
2410
   output reg level1;
2411
   input rst;
2412
   input clk;
2413
 
2414
   parameter clear_value = 0;
2415
   parameter set_value = 1;
2416
   parameter wrap_value = 1;
2417
   parameter level1_value = 15;
2418
 
2419 29 unneback
   wire clear;
2420 30 unneback
   assign clear = 1'b0;
2421 25 unneback
   reg  [length:1] qi;
2422
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2423
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2424
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2425
   assign q_next = rew ? q_next_rew : q_next_fw;
2426
 
2427
   always @ (posedge clk or posedge rst)
2428
     if (rst)
2429
       qi <= {length{1'b0}};
2430
     else
2431
     if (cke)
2432
       qi <= q_next;
2433
 
2434
 
2435
 
2436
   always @ (posedge clk or posedge rst)
2437
     if (rst)
2438
       zq <= 1'b1;
2439
     else
2440
     if (cke)
2441
       zq <= q_next == {length{1'b0}};
2442
 
2443
    always @ (posedge clk or posedge rst)
2444
    if (rst)
2445
        level1 <= 1'b0;
2446
    else
2447
    if (cke)
2448 29 unneback
    if (clear)
2449
        level1 <= 1'b0;
2450
    else if (q_next == level1_value)
2451 25 unneback
        level1 <= 1'b1;
2452
    else if (qi == level1_value & rew)
2453
        level1 <= 1'b0;
2454
endmodule
2455 40 unneback
`endif
2456
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2457 25 unneback
//////////////////////////////////////////////////////////////////////
2458
////                                                              ////
2459
////  Versatile counter                                           ////
2460
////                                                              ////
2461
////  Description                                                 ////
2462
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2463
////  counter                                                     ////
2464
////                                                              ////
2465
////  To Do:                                                      ////
2466
////   - add LFSR with more taps                                  ////
2467
////                                                              ////
2468
////  Author(s):                                                  ////
2469
////      - Michael Unneback, unneback@opencores.org              ////
2470
////        ORSoC AB                                              ////
2471
////                                                              ////
2472
//////////////////////////////////////////////////////////////////////
2473
////                                                              ////
2474
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2475
////                                                              ////
2476
//// This source file may be used and distributed without         ////
2477
//// restriction provided that this copyright statement is not    ////
2478
//// removed from the file and that any derivative work contains  ////
2479
//// the original copyright notice and the associated disclaimer. ////
2480
////                                                              ////
2481
//// This source file is free software; you can redistribute it   ////
2482
//// and/or modify it under the terms of the GNU Lesser General   ////
2483
//// Public License as published by the Free Software Foundation; ////
2484
//// either version 2.1 of the License, or (at your option) any   ////
2485
//// later version.                                               ////
2486
////                                                              ////
2487
//// This source is distributed in the hope that it will be       ////
2488
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2489
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2490
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2491
//// details.                                                     ////
2492
////                                                              ////
2493
//// You should have received a copy of the GNU Lesser General    ////
2494
//// Public License along with this source; if not, download it   ////
2495
//// from http://www.opencores.org/lgpl.shtml                     ////
2496
////                                                              ////
2497
//////////////////////////////////////////////////////////////////////
2498
 
2499
// binary counter
2500
 
2501 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2502
module `BASE`MODULE (
2503
`undef MODULE
2504
 cke, rew, q, zq, level1, rst, clk);
2505
 
2506 25 unneback
   parameter length = 4;
2507
   input cke;
2508
   input rew;
2509
   output [length:1] q;
2510
   output reg zq;
2511
   output reg level1;
2512
   input rst;
2513
   input clk;
2514
 
2515
   parameter clear_value = 0;
2516
   parameter set_value = 1;
2517
   parameter wrap_value = 1;
2518
   parameter level1_value = 15;
2519
 
2520 29 unneback
   wire clear;
2521 30 unneback
   assign clear = 1'b0;
2522 25 unneback
   reg  [length:1] qi;
2523
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2524
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2525
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2526
   assign q_next = rew ? q_next_rew : q_next_fw;
2527
 
2528
   always @ (posedge clk or posedge rst)
2529
     if (rst)
2530
       qi <= {length{1'b0}};
2531
     else
2532
     if (cke)
2533
       qi <= q_next;
2534
 
2535
   assign q = qi;
2536
 
2537
 
2538
   always @ (posedge clk or posedge rst)
2539
     if (rst)
2540
       zq <= 1'b1;
2541
     else
2542
     if (cke)
2543
       zq <= q_next == {length{1'b0}};
2544
 
2545
    always @ (posedge clk or posedge rst)
2546
    if (rst)
2547
        level1 <= 1'b0;
2548
    else
2549
    if (cke)
2550 29 unneback
    if (clear)
2551
        level1 <= 1'b0;
2552
    else if (q_next == level1_value)
2553 25 unneback
        level1 <= 1'b1;
2554
    else if (qi == level1_value & rew)
2555
        level1 <= 1'b0;
2556
endmodule
2557 40 unneback
`endif
2558
`ifdef CNT_LFSR_ZQ
2559 25 unneback
//////////////////////////////////////////////////////////////////////
2560
////                                                              ////
2561
////  Versatile counter                                           ////
2562
////                                                              ////
2563
////  Description                                                 ////
2564
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2565
////  counter                                                     ////
2566
////                                                              ////
2567
////  To Do:                                                      ////
2568
////   - add LFSR with more taps                                  ////
2569
////                                                              ////
2570
////  Author(s):                                                  ////
2571
////      - Michael Unneback, unneback@opencores.org              ////
2572
////        ORSoC AB                                              ////
2573
////                                                              ////
2574
//////////////////////////////////////////////////////////////////////
2575
////                                                              ////
2576
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2577
////                                                              ////
2578
//// This source file may be used and distributed without         ////
2579
//// restriction provided that this copyright statement is not    ////
2580
//// removed from the file and that any derivative work contains  ////
2581
//// the original copyright notice and the associated disclaimer. ////
2582
////                                                              ////
2583
//// This source file is free software; you can redistribute it   ////
2584
//// and/or modify it under the terms of the GNU Lesser General   ////
2585
//// Public License as published by the Free Software Foundation; ////
2586
//// either version 2.1 of the License, or (at your option) any   ////
2587
//// later version.                                               ////
2588
////                                                              ////
2589
//// This source is distributed in the hope that it will be       ////
2590
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2591
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2592
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2593
//// details.                                                     ////
2594
////                                                              ////
2595
//// You should have received a copy of the GNU Lesser General    ////
2596
//// Public License along with this source; if not, download it   ////
2597
//// from http://www.opencores.org/lgpl.shtml                     ////
2598
////                                                              ////
2599
//////////////////////////////////////////////////////////////////////
2600
 
2601 6 unneback
// LFSR counter
2602
 
2603 40 unneback
`define MODULE cnt_lfsr_zq
2604
module `BASE`MODULE (
2605
`undef MODULE
2606
 zq, rst, clk);
2607
 
2608 6 unneback
   parameter length = 4;
2609
   output reg zq;
2610
   input rst;
2611
   input clk;
2612
 
2613
   parameter clear_value = 0;
2614
   parameter set_value = 1;
2615
   parameter wrap_value = 8;
2616
   parameter level1_value = 15;
2617
 
2618
   reg  [length:1] qi;
2619
   reg lfsr_fb;
2620
   wire [length:1] q_next;
2621
   reg [32:1] polynom;
2622
   integer i;
2623
 
2624
   always @ (qi)
2625
   begin
2626
        case (length)
2627
         2: polynom = 32'b11;                               // 0x3
2628
         3: polynom = 32'b110;                              // 0x6
2629
         4: polynom = 32'b1100;                             // 0xC
2630
         5: polynom = 32'b10100;                            // 0x14
2631
         6: polynom = 32'b110000;                           // 0x30
2632
         7: polynom = 32'b1100000;                          // 0x60
2633
         8: polynom = 32'b10111000;                         // 0xb8
2634
         9: polynom = 32'b100010000;                        // 0x110
2635
        10: polynom = 32'b1001000000;                       // 0x240
2636
        11: polynom = 32'b10100000000;                      // 0x500
2637
        12: polynom = 32'b100000101001;                     // 0x829
2638
        13: polynom = 32'b1000000001100;                    // 0x100C
2639
        14: polynom = 32'b10000000010101;                   // 0x2015
2640
        15: polynom = 32'b110000000000000;                  // 0x6000
2641
        16: polynom = 32'b1101000000001000;                 // 0xD008
2642
        17: polynom = 32'b10010000000000000;                // 0x12000
2643
        18: polynom = 32'b100000010000000000;               // 0x20400
2644
        19: polynom = 32'b1000000000000100011;              // 0x40023
2645 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2646 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2647
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2648
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2649
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2650
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2651
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2652
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2653
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2654
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2655
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2656
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2657
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2658
        default: polynom = 32'b0;
2659
        endcase
2660
        lfsr_fb = qi[length];
2661
        for (i=length-1; i>=1; i=i-1) begin
2662
            if (polynom[i])
2663
                lfsr_fb = lfsr_fb  ~^ qi[i];
2664
        end
2665
    end
2666
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2667
 
2668
   always @ (posedge clk or posedge rst)
2669
     if (rst)
2670
       qi <= {length{1'b0}};
2671
     else
2672
       qi <= q_next;
2673
 
2674
 
2675
 
2676
   always @ (posedge clk or posedge rst)
2677
     if (rst)
2678
       zq <= 1'b1;
2679
     else
2680
       zq <= q_next == {length{1'b0}};
2681
endmodule
2682 40 unneback
`endif
2683 75 unneback
`ifdef CNT_LFSR_CE
2684
//////////////////////////////////////////////////////////////////////
2685
////                                                              ////
2686
////  Versatile counter                                           ////
2687
////                                                              ////
2688
////  Description                                                 ////
2689
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2690
////  counter                                                     ////
2691
////                                                              ////
2692
////  To Do:                                                      ////
2693
////   - add LFSR with more taps                                  ////
2694
////                                                              ////
2695
////  Author(s):                                                  ////
2696
////      - Michael Unneback, unneback@opencores.org              ////
2697
////        ORSoC AB                                              ////
2698
////                                                              ////
2699
//////////////////////////////////////////////////////////////////////
2700
////                                                              ////
2701
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2702
////                                                              ////
2703
//// This source file may be used and distributed without         ////
2704
//// restriction provided that this copyright statement is not    ////
2705
//// removed from the file and that any derivative work contains  ////
2706
//// the original copyright notice and the associated disclaimer. ////
2707
////                                                              ////
2708
//// This source file is free software; you can redistribute it   ////
2709
//// and/or modify it under the terms of the GNU Lesser General   ////
2710
//// Public License as published by the Free Software Foundation; ////
2711
//// either version 2.1 of the License, or (at your option) any   ////
2712
//// later version.                                               ////
2713
////                                                              ////
2714
//// This source is distributed in the hope that it will be       ////
2715
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2716
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2717
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2718
//// details.                                                     ////
2719
////                                                              ////
2720
//// You should have received a copy of the GNU Lesser General    ////
2721
//// Public License along with this source; if not, download it   ////
2722
//// from http://www.opencores.org/lgpl.shtml                     ////
2723
////                                                              ////
2724
//////////////////////////////////////////////////////////////////////
2725
 
2726
// LFSR counter
2727
 
2728
`define MODULE cnt_lfsr_ce
2729
module `BASE`MODULE (
2730
`undef MODULE
2731
 cke, zq, rst, clk);
2732
 
2733
   parameter length = 4;
2734
   input cke;
2735
   output reg zq;
2736
   input rst;
2737
   input clk;
2738
 
2739
   parameter clear_value = 0;
2740
   parameter set_value = 1;
2741
   parameter wrap_value = 0;
2742
   parameter level1_value = 15;
2743
 
2744
   reg  [length:1] qi;
2745
   reg lfsr_fb;
2746
   wire [length:1] q_next;
2747
   reg [32:1] polynom;
2748
   integer i;
2749
 
2750
   always @ (qi)
2751
   begin
2752
        case (length)
2753
         2: polynom = 32'b11;                               // 0x3
2754
         3: polynom = 32'b110;                              // 0x6
2755
         4: polynom = 32'b1100;                             // 0xC
2756
         5: polynom = 32'b10100;                            // 0x14
2757
         6: polynom = 32'b110000;                           // 0x30
2758
         7: polynom = 32'b1100000;                          // 0x60
2759
         8: polynom = 32'b10111000;                         // 0xb8
2760
         9: polynom = 32'b100010000;                        // 0x110
2761
        10: polynom = 32'b1001000000;                       // 0x240
2762
        11: polynom = 32'b10100000000;                      // 0x500
2763
        12: polynom = 32'b100000101001;                     // 0x829
2764
        13: polynom = 32'b1000000001100;                    // 0x100C
2765
        14: polynom = 32'b10000000010101;                   // 0x2015
2766
        15: polynom = 32'b110000000000000;                  // 0x6000
2767
        16: polynom = 32'b1101000000001000;                 // 0xD008
2768
        17: polynom = 32'b10010000000000000;                // 0x12000
2769
        18: polynom = 32'b100000010000000000;               // 0x20400
2770
        19: polynom = 32'b1000000000000100011;              // 0x40023
2771
        20: polynom = 32'b10010000000000000000;             // 0x90000
2772
        21: polynom = 32'b101000000000000000000;            // 0x140000
2773
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2774
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2775
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2776
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2777
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2778
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2779
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2780
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2781
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2782
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2783
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2784
        default: polynom = 32'b0;
2785
        endcase
2786
        lfsr_fb = qi[length];
2787
        for (i=length-1; i>=1; i=i-1) begin
2788
            if (polynom[i])
2789
                lfsr_fb = lfsr_fb  ~^ qi[i];
2790
        end
2791
    end
2792
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2793
 
2794
   always @ (posedge clk or posedge rst)
2795
     if (rst)
2796
       qi <= {length{1'b0}};
2797
     else
2798
     if (cke)
2799
       qi <= q_next;
2800
 
2801
 
2802
 
2803
   always @ (posedge clk or posedge rst)
2804
     if (rst)
2805
       zq <= 1'b1;
2806
     else
2807
     if (cke)
2808
       zq <= q_next == {length{1'b0}};
2809
endmodule
2810
`endif
2811 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2812 6 unneback
//////////////////////////////////////////////////////////////////////
2813
////                                                              ////
2814
////  Versatile counter                                           ////
2815
////                                                              ////
2816
////  Description                                                 ////
2817
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2818
////  counter                                                     ////
2819
////                                                              ////
2820
////  To Do:                                                      ////
2821
////   - add LFSR with more taps                                  ////
2822
////                                                              ////
2823
////  Author(s):                                                  ////
2824
////      - Michael Unneback, unneback@opencores.org              ////
2825
////        ORSoC AB                                              ////
2826
////                                                              ////
2827
//////////////////////////////////////////////////////////////////////
2828
////                                                              ////
2829
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2830
////                                                              ////
2831
//// This source file may be used and distributed without         ////
2832
//// restriction provided that this copyright statement is not    ////
2833
//// removed from the file and that any derivative work contains  ////
2834
//// the original copyright notice and the associated disclaimer. ////
2835
////                                                              ////
2836
//// This source file is free software; you can redistribute it   ////
2837
//// and/or modify it under the terms of the GNU Lesser General   ////
2838
//// Public License as published by the Free Software Foundation; ////
2839
//// either version 2.1 of the License, or (at your option) any   ////
2840
//// later version.                                               ////
2841
////                                                              ////
2842
//// This source is distributed in the hope that it will be       ////
2843
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2844
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2845
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2846
//// details.                                                     ////
2847
////                                                              ////
2848
//// You should have received a copy of the GNU Lesser General    ////
2849
//// Public License along with this source; if not, download it   ////
2850
//// from