OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 14

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
66
`ifdef SIM_GBUF
67
assign o=i;
68
`else
69
gbuf gbuf_i0 ( .CLK(i), .GL(o));
70
`endif
71
endmodule
72
`else
73
`ifdef ALTERA
74
altera
75
`else
76
 
77
`timescale 1 ns/100 ps
78
module vl_gbuf ( i, o);
79
input i;
80
output o;
81
assign o = i;
82
endmodule
83
`endif // ALTERA
84
`endif //ACTEL
85
 
86
// sync reset
87
// input active lo async reset, normally from external reset generetaor and/or switch
88
// output active high global reset sync with two DFFs 
89
`timescale 1 ns/100 ps
90
module vl_sync_rst ( rst_n_i, rst_o, clk);
91
input rst_n_i, clk;
92
output rst_o;
93
reg [0:1] tmp;
94
always @ (posedge clk or negedge rst_n_i)
95
if (!rst_n_i)
96
        tmp <= 2'b00;
97
else
98
        tmp <= {1'b1,tmp[0]};
99
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
100
endmodule
101
 
102
// vl_pll
103
`ifdef ACTEL
104
`timescale 1 ns/100 ps
105
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
106
parameter index = 0;
107
parameter number_of_clk = 1;
108
parameter period_time_0 = 20;
109
parameter period_time_1 = 20;
110
parameter period_time_2 = 20;
111
parameter lock_delay = 2000;
112
input clk_i, rst_n_i;
113
output lock;
114
output reg [0:number_of_clk-1] clk_o;
115
output [0:number_of_clk-1] rst_o;
116
 
117
`ifdef SIM_PLL
118
 
119
always
120
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
121
 
122
generate if (number_of_clk > 1)
123
always
124
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
125
endgenerate
126
 
127
generate if (number_of_clk > 2)
128
always
129
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
130
endgenerate
131
 
132
genvar i;
133
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
134
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
135
end
136
endgenerate
137
 
138
assign #lock_delay lock = rst_n_i;
139
 
140
endmodule
141
`else
142
generate if (number_of_clk==1 & index==0) begin
143
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==1 & index==1) begin
147
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
148
end
149
endgenerate // index==1
150
generate if (number_of_clk==1 & index==2) begin
151
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
152
end
153
endgenerate // index==2
154
generate if (number_of_clk==1 & index==3) begin
155
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
156
end
157
endgenerate // index==0
158
 
159
generate if (number_of_clk==2 & index==0) begin
160
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
161
end
162
endgenerate // index==0
163
generate if (number_of_clk==2 & index==1) begin
164
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
165
end
166
endgenerate // index==1
167
generate if (number_of_clk==2 & index==2) begin
168
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
169
end
170
endgenerate // index==2
171
generate if (number_of_clk==2 & index==3) begin
172
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
173
end
174
endgenerate // index==0
175
 
176
generate if (number_of_clk==3 & index==0) begin
177
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
178
end
179
endgenerate // index==0
180
generate if (number_of_clk==3 & index==1) begin
181
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
182
end
183
endgenerate // index==1
184
generate if (number_of_clk==3 & index==2) begin
185
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
186
end
187
endgenerate // index==2
188
generate if (number_of_clk==3 & index==3) begin
189
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
190
end
191
endgenerate // index==0
192
 
193
genvar i;
194
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
195
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
196
end
197
endgenerate
198
endmodule
199
`endif
200
 
201
`else
202
 
203
`ifdef ALTERA
204
 
205
`else
206
 
207
// generic PLL
208
`timescale 1 ns/100 ps
209
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
210
parameter index = 0;
211
parameter number_of_clk = 1;
212
parameter period_time_0 = 20;
213
parameter period_time_1 = 20;
214
parameter period_time_2 = 20;
215
parameter lock_delay = 2000;
216
input clk_i, rst_n_i;
217
output lock;
218
output reg [0:number_of_clk-1] clk_o;
219
output [0:number_of_clk-1] rst_o;
220
 
221
always
222
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
223
 
224
generate if (number_of_clk > 1)
225
always
226
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
227
endgenerate
228
 
229
generate if (number_of_clk > 2)
230
always
231
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
232
endgenerate
233
 
234
genvar i;
235
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
236
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
237
end
238
endgenerate
239
 
240
assign #lock_delay lock = rst_n_i;
241
 
242
endmodule
243
 
244
`endif //altera
245
`endif //actel//////////////////////////////////////////////////////////////////////
246
////                                                              ////
247
////  Versatile library, registers                                ////
248
////                                                              ////
249
////  Description                                                 ////
250
////  Different type of registers                                 ////
251
////                                                              ////
252
////                                                              ////
253
////  To Do:                                                      ////
254
////   - add more different registers                             ////
255
////                                                              ////
256
////  Author(s):                                                  ////
257
////      - Michael Unneback, unneback@opencores.org              ////
258
////        ORSoC AB                                              ////
259
////                                                              ////
260
//////////////////////////////////////////////////////////////////////
261
////                                                              ////
262
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
263
////                                                              ////
264
//// This source file may be used and distributed without         ////
265
//// restriction provided that this copyright statement is not    ////
266
//// removed from the file and that any derivative work contains  ////
267
//// the original copyright notice and the associated disclaimer. ////
268
////                                                              ////
269
//// This source file is free software; you can redistribute it   ////
270
//// and/or modify it under the terms of the GNU Lesser General   ////
271
//// Public License as published by the Free Software Foundation; ////
272
//// either version 2.1 of the License, or (at your option) any   ////
273
//// later version.                                               ////
274
////                                                              ////
275
//// This source is distributed in the hope that it will be       ////
276
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
277
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
278
//// PURPOSE.  See the GNU Lesser General Public License for more ////
279
//// details.                                                     ////
280
////                                                              ////
281
//// You should have received a copy of the GNU Lesser General    ////
282
//// Public License along with this source; if not, download it   ////
283
//// from http://www.opencores.org/lgpl.shtml                     ////
284
////                                                              ////
285
//////////////////////////////////////////////////////////////////////
286
 
287
module dff ( d, q, clk, rst);
288
 
289
        parameter width = 1;
290
        parameter reset_value = 0;
291
 
292
        input [width-1:0] d;
293
        input clk, rst;
294
        output reg [width-1:0] q;
295
 
296
        always @ (posedge clk or posedge rst)
297
        if (rst)
298
                q <= reset_value;
299
        else
300
                q <= d;
301
 
302
endmodule
303
 
304
module dff_array ( d, q, clk, rst);
305
 
306
        parameter width = 1;
307
        parameter depth = 2;
308
        parameter reset_value = 1'b0;
309
 
310
        input [width-1:0] d;
311
        input clk, rst;
312
        output [width-1:0] q;
313
        reg  [0:depth-1] q_tmp [width-1:0];
314
        integer i;
315
        always @ (posedge clk or posedge rst)
316
        if (rst) begin
317
            for (i=0;i<depth;i=i+1)
318
                q_tmp[i] <= {width{reset_value}};
319
        end else begin
320
            q_tmp[0] <= d;
321
            for (i=1;i<depth;i=i+1)
322
                q_tmp[i] <= q_tmp[i-1];
323
        end
324
 
325
    assign q = q_tmp[depth-1];
326
 
327
endmodule
328
 
329
module dff_ce ( d, ce, q, clk, rst);
330
 
331
        parameter width = 1;
332
        parameter reset_value = 0;
333
 
334
        input [width-1:0] d;
335
        input ce, clk, rst;
336
        output reg [width-1:0] q;
337
 
338
        always @ (posedge clk or posedge rst)
339
        if (rst)
340
                q <= reset_value;
341
        else
342
                if (ce)
343
                        q <= d;
344
 
345
endmodule
346
 
347 8 unneback
module dff_ce_clear ( d, ce, clear, q, clk, rst);
348
 
349
        parameter width = 1;
350
        parameter reset_value = 0;
351
 
352
        input [width-1:0] d;
353 10 unneback
        input ce, clear, clk, rst;
354 8 unneback
        output reg [width-1:0] q;
355
 
356
        always @ (posedge clk or posedge rst)
357
        if (rst)
358
            q <= reset_value;
359
        else
360
            if (ce)
361
                if (clear)
362
                    q <= {width{1'b0}};
363
                else
364
                    q <= d;
365
 
366
endmodule
367
 
368 6 unneback
`ifdef ALTERA
369
// megafunction wizard: %LPM_FF%
370
// GENERATION: STANDARD
371
// VERSION: WM1.0
372
// MODULE: lpm_ff 
373
 
374
// ============================================================
375
// File Name: dff_sr.v
376
// Megafunction Name(s):
377
//                      lpm_ff
378
//
379
// Simulation Library Files(s):
380
//                      lpm
381
// ============================================================
382
// ************************************************************
383
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
384
//
385
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
386
// ************************************************************
387
 
388
 
389
//Copyright (C) 1991-2010 Altera Corporation
390
//Your use of Altera Corporation's design tools, logic functions 
391
//and other software and tools, and its AMPP partner logic 
392
//functions, and any output files from any of the foregoing 
393
//(including device programming or simulation files), and any 
394
//associated documentation or information are expressly subject 
395
//to the terms and conditions of the Altera Program License 
396
//Subscription Agreement, Altera MegaCore Function License 
397
//Agreement, or other applicable license agreement, including, 
398
//without limitation, that your use is for the sole purpose of 
399
//programming logic devices manufactured by Altera and sold by 
400
//Altera or its authorized distributors.  Please refer to the 
401
//applicable agreement for further details.
402
 
403
 
404
// synopsys translate_off
405
`timescale 1 ps / 1 ps
406
// synopsys translate_on
407
module dff_sr (
408
        aclr,
409
        aset,
410
        clock,
411
        data,
412
        q);
413
 
414
        input     aclr;
415
        input     aset;
416
        input     clock;
417
        input     data;
418
        output    q;
419
 
420
        wire [0:0] sub_wire0;
421
        wire [0:0] sub_wire1 = sub_wire0[0:0];
422
        wire  q = sub_wire1;
423
        wire  sub_wire2 = data;
424
        wire  sub_wire3 = sub_wire2;
425
 
426
        lpm_ff  lpm_ff_component (
427
                                .aclr (aclr),
428
                                .clock (clock),
429
                                .data (sub_wire3),
430
                                .aset (aset),
431
                                .q (sub_wire0)
432
                                // synopsys translate_off
433
                                ,
434
                                .aload (),
435
                                .enable (),
436
                                .sclr (),
437
                                .sload (),
438
                                .sset ()
439
                                // synopsys translate_on
440
                                );
441
        defparam
442
                lpm_ff_component.lpm_fftype = "DFF",
443
                lpm_ff_component.lpm_type = "LPM_FF",
444
                lpm_ff_component.lpm_width = 1;
445
 
446
 
447
endmodule
448
 
449
// ============================================================
450
// CNX file retrieval info
451
// ============================================================
452
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
453
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
454
// Retrieval info: PRIVATE: ASET NUMERIC "1"
455
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
456
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
457
// Retrieval info: PRIVATE: DFF NUMERIC "1"
458
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
459
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
460
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
461
// Retrieval info: PRIVATE: SSET NUMERIC "0"
462
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
463
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
464
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
465
// Retrieval info: PRIVATE: nBit NUMERIC "1"
466
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
467
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
468
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
469
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
470
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
471
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
472
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
473
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
474
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
475
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
476
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
477
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
478
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
479
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
480
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
481
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
482
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
483
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
484
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
485
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
486
// Retrieval info: LIB_FILE: lpm
487
 
488
 
489
`else
490
 
491
 
492
module dff_sr ( aclr, aset, clock, data, q);
493
 
494
    input         aclr;
495
    input         aset;
496
    input         clock;
497
    input         data;
498
    output reg    q;
499
 
500
   always @ (posedge clock or posedge aclr or posedge aset)
501
     if (aclr)
502
       q <= 1'b0;
503
     else if (aset)
504
       q <= 1'b1;
505
     else
506
       q <= data;
507
 
508
endmodule
509
 
510
`endif
511
 
512
// LATCH
513
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
514
`ifdef ALTERA
515
module latch ( d, le, q, clk);
516
input d, le;
517
output q;
518
input clk;
519
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
520
endmodule
521
`else
522
module latch ( d, le, q, clk);
523
input d, le;
524
output q;
525
input clk;/*
526
   always @ (posedge direction_set or posedge direction_clr)
527
     if (direction_clr)
528
       direction <= going_empty;
529
     else
530
       direction <= going_full;*/
531
endmodule
532
`endif//////////////////////////////////////////////////////////////////////
533
////                                                              ////
534
////  Versatile counter                                           ////
535
////                                                              ////
536
////  Description                                                 ////
537
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
538
////  counter                                                     ////
539
////                                                              ////
540
////  To Do:                                                      ////
541
////   - add LFSR with more taps                                  ////
542
////                                                              ////
543
////  Author(s):                                                  ////
544
////      - Michael Unneback, unneback@opencores.org              ////
545
////        ORSoC AB                                              ////
546
////                                                              ////
547
//////////////////////////////////////////////////////////////////////
548
////                                                              ////
549
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
550
////                                                              ////
551
//// This source file may be used and distributed without         ////
552
//// restriction provided that this copyright statement is not    ////
553
//// removed from the file and that any derivative work contains  ////
554
//// the original copyright notice and the associated disclaimer. ////
555
////                                                              ////
556
//// This source file is free software; you can redistribute it   ////
557
//// and/or modify it under the terms of the GNU Lesser General   ////
558
//// Public License as published by the Free Software Foundation; ////
559
//// either version 2.1 of the License, or (at your option) any   ////
560
//// later version.                                               ////
561
////                                                              ////
562
//// This source is distributed in the hope that it will be       ////
563
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
564
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
565
//// PURPOSE.  See the GNU Lesser General Public License for more ////
566
//// details.                                                     ////
567
////                                                              ////
568
//// You should have received a copy of the GNU Lesser General    ////
569
//// Public License along with this source; if not, download it   ////
570
//// from http://www.opencores.org/lgpl.shtml                     ////
571
////                                                              ////
572
//////////////////////////////////////////////////////////////////////
573
 
574
// binary counter
575
module cnt_bin_ce ( cke, q, rst, clk);
576
 
577
   parameter length = 4;
578
   input cke;
579
   output [length:1] q;
580
   input rst;
581
   input clk;
582
 
583
   parameter clear_value = 0;
584
   parameter set_value = 1;
585
   parameter wrap_value = 0;
586
   parameter level1_value = 15;
587
 
588
   reg  [length:1] qi;
589
   wire [length:1] q_next;
590
   assign q_next = qi + {{length-1{1'b0}},1'b1};
591
 
592
   always @ (posedge clk or posedge rst)
593
     if (rst)
594
       qi <= {length{1'b0}};
595
     else
596
     if (cke)
597
       qi <= q_next;
598
 
599
   assign q = qi;
600
 
601
endmodule
602
//////////////////////////////////////////////////////////////////////
603
////                                                              ////
604
////  Versatile counter                                           ////
605
////                                                              ////
606
////  Description                                                 ////
607
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
608
////  counter                                                     ////
609
////                                                              ////
610
////  To Do:                                                      ////
611
////   - add LFSR with more taps                                  ////
612
////                                                              ////
613
////  Author(s):                                                  ////
614
////      - Michael Unneback, unneback@opencores.org              ////
615
////        ORSoC AB                                              ////
616
////                                                              ////
617
//////////////////////////////////////////////////////////////////////
618
////                                                              ////
619
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
620
////                                                              ////
621
//// This source file may be used and distributed without         ////
622
//// restriction provided that this copyright statement is not    ////
623
//// removed from the file and that any derivative work contains  ////
624
//// the original copyright notice and the associated disclaimer. ////
625
////                                                              ////
626
//// This source file is free software; you can redistribute it   ////
627
//// and/or modify it under the terms of the GNU Lesser General   ////
628
//// Public License as published by the Free Software Foundation; ////
629
//// either version 2.1 of the License, or (at your option) any   ////
630
//// later version.                                               ////
631
////                                                              ////
632
//// This source is distributed in the hope that it will be       ////
633
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
634
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
635
//// PURPOSE.  See the GNU Lesser General Public License for more ////
636
//// details.                                                     ////
637
////                                                              ////
638
//// You should have received a copy of the GNU Lesser General    ////
639
//// Public License along with this source; if not, download it   ////
640
//// from http://www.opencores.org/lgpl.shtml                     ////
641
////                                                              ////
642
//////////////////////////////////////////////////////////////////////
643
 
644
// binary counter
645
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
646
 
647
   parameter length = 4;
648
   input clear;
649
   input cke;
650
   output [length:1] q;
651
   input rst;
652
   input clk;
653
 
654
   parameter clear_value = 0;
655
   parameter set_value = 1;
656
   parameter wrap_value = 0;
657
   parameter level1_value = 15;
658
 
659
   reg  [length:1] qi;
660
   wire [length:1] q_next;
661
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
662
 
663
   always @ (posedge clk or posedge rst)
664
     if (rst)
665
       qi <= {length{1'b0}};
666
     else
667
     if (cke)
668
       qi <= q_next;
669
 
670
   assign q = qi;
671
 
672
endmodule
673
//////////////////////////////////////////////////////////////////////
674
////                                                              ////
675
////  Versatile counter                                           ////
676
////                                                              ////
677
////  Description                                                 ////
678
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
679
////  counter                                                     ////
680
////                                                              ////
681
////  To Do:                                                      ////
682
////   - add LFSR with more taps                                  ////
683
////                                                              ////
684
////  Author(s):                                                  ////
685
////      - Michael Unneback, unneback@opencores.org              ////
686
////        ORSoC AB                                              ////
687
////                                                              ////
688
//////////////////////////////////////////////////////////////////////
689
////                                                              ////
690
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
691
////                                                              ////
692
//// This source file may be used and distributed without         ////
693
//// restriction provided that this copyright statement is not    ////
694
//// removed from the file and that any derivative work contains  ////
695
//// the original copyright notice and the associated disclaimer. ////
696
////                                                              ////
697
//// This source file is free software; you can redistribute it   ////
698
//// and/or modify it under the terms of the GNU Lesser General   ////
699
//// Public License as published by the Free Software Foundation; ////
700
//// either version 2.1 of the License, or (at your option) any   ////
701
//// later version.                                               ////
702
////                                                              ////
703
//// This source is distributed in the hope that it will be       ////
704
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
705
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
706
//// PURPOSE.  See the GNU Lesser General Public License for more ////
707
//// details.                                                     ////
708
////                                                              ////
709
//// You should have received a copy of the GNU Lesser General    ////
710
//// Public License along with this source; if not, download it   ////
711
//// from http://www.opencores.org/lgpl.shtml                     ////
712
////                                                              ////
713
//////////////////////////////////////////////////////////////////////
714
 
715
// binary counter
716
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
717
 
718
   parameter length = 4;
719
   input clear;
720
   input set;
721
   input cke;
722
   input rew;
723
   output [length:1] q;
724
   input rst;
725
   input clk;
726
 
727
   parameter clear_value = 0;
728
   parameter set_value = 1;
729
   parameter wrap_value = 0;
730
   parameter level1_value = 15;
731
 
732
   reg  [length:1] qi;
733
   wire  [length:1] q_next, q_next_fw, q_next_rew;
734
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
735
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
736
   assign q_next = rew ? q_next_rew : q_next_fw;
737
 
738
   always @ (posedge clk or posedge rst)
739
     if (rst)
740
       qi <= {length{1'b0}};
741
     else
742
     if (cke)
743
       qi <= q_next;
744
 
745
   assign q = qi;
746
 
747
endmodule
748
//////////////////////////////////////////////////////////////////////
749
////                                                              ////
750
////  Versatile counter                                           ////
751
////                                                              ////
752
////  Description                                                 ////
753
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
754
////  counter                                                     ////
755
////                                                              ////
756
////  To Do:                                                      ////
757
////   - add LFSR with more taps                                  ////
758
////                                                              ////
759
////  Author(s):                                                  ////
760
////      - Michael Unneback, unneback@opencores.org              ////
761
////        ORSoC AB                                              ////
762
////                                                              ////
763
//////////////////////////////////////////////////////////////////////
764
////                                                              ////
765
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
766
////                                                              ////
767
//// This source file may be used and distributed without         ////
768
//// restriction provided that this copyright statement is not    ////
769
//// removed from the file and that any derivative work contains  ////
770
//// the original copyright notice and the associated disclaimer. ////
771
////                                                              ////
772
//// This source file is free software; you can redistribute it   ////
773
//// and/or modify it under the terms of the GNU Lesser General   ////
774
//// Public License as published by the Free Software Foundation; ////
775
//// either version 2.1 of the License, or (at your option) any   ////
776
//// later version.                                               ////
777
////                                                              ////
778
//// This source is distributed in the hope that it will be       ////
779
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
780
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
781
//// PURPOSE.  See the GNU Lesser General Public License for more ////
782
//// details.                                                     ////
783
////                                                              ////
784
//// You should have received a copy of the GNU Lesser General    ////
785
//// Public License along with this source; if not, download it   ////
786
//// from http://www.opencores.org/lgpl.shtml                     ////
787
////                                                              ////
788
//////////////////////////////////////////////////////////////////////
789
 
790
// binary counter
791
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
792
 
793
   parameter length = 4;
794
   input cke;
795
   input rew;
796
   output reg level1;
797
   input rst;
798
   input clk;
799
 
800
   parameter clear_value = 0;
801
   parameter set_value = 1;
802
   parameter wrap_value = 1;
803
   parameter level1_value = 15;
804
 
805
   reg  [length:1] qi;
806
   wire  [length:1] q_next, q_next_fw, q_next_rew;
807
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
808
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
809
   assign q_next = rew ? q_next_rew : q_next_fw;
810
 
811
   always @ (posedge clk or posedge rst)
812
     if (rst)
813
       qi <= {length{1'b0}};
814
     else
815
     if (cke)
816
       qi <= q_next;
817
 
818
 
819
 
820
    always @ (posedge clk or posedge rst)
821
    if (rst)
822
        level1 <= 1'b0;
823
    else
824
    if (cke)
825
    if (q_next == level1_value)
826
        level1 <= 1'b1;
827
    else if (qi == level1_value & rew)
828
        level1 <= 1'b0;
829
endmodule
830
//////////////////////////////////////////////////////////////////////
831
////                                                              ////
832
////  Versatile counter                                           ////
833
////                                                              ////
834
////  Description                                                 ////
835
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
836
////  counter                                                     ////
837
////                                                              ////
838
////  To Do:                                                      ////
839
////   - add LFSR with more taps                                  ////
840
////                                                              ////
841
////  Author(s):                                                  ////
842
////      - Michael Unneback, unneback@opencores.org              ////
843
////        ORSoC AB                                              ////
844
////                                                              ////
845
//////////////////////////////////////////////////////////////////////
846
////                                                              ////
847
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
848
////                                                              ////
849
//// This source file may be used and distributed without         ////
850
//// restriction provided that this copyright statement is not    ////
851
//// removed from the file and that any derivative work contains  ////
852
//// the original copyright notice and the associated disclaimer. ////
853
////                                                              ////
854
//// This source file is free software; you can redistribute it   ////
855
//// and/or modify it under the terms of the GNU Lesser General   ////
856
//// Public License as published by the Free Software Foundation; ////
857
//// either version 2.1 of the License, or (at your option) any   ////
858
//// later version.                                               ////
859
////                                                              ////
860
//// This source is distributed in the hope that it will be       ////
861
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
862
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
863
//// PURPOSE.  See the GNU Lesser General Public License for more ////
864
//// details.                                                     ////
865
////                                                              ////
866
//// You should have received a copy of the GNU Lesser General    ////
867
//// Public License along with this source; if not, download it   ////
868
//// from http://www.opencores.org/lgpl.shtml                     ////
869
////                                                              ////
870
//////////////////////////////////////////////////////////////////////
871
 
872
// LFSR counter
873
module cnt_lfsr_zq ( zq, rst, clk);
874
 
875
   parameter length = 4;
876
   output reg zq;
877
   input rst;
878
   input clk;
879
 
880
   parameter clear_value = 0;
881
   parameter set_value = 1;
882
   parameter wrap_value = 8;
883
   parameter level1_value = 15;
884
 
885
   reg  [length:1] qi;
886
   reg lfsr_fb;
887
   wire [length:1] q_next;
888
   reg [32:1] polynom;
889
   integer i;
890
 
891
   always @ (qi)
892
   begin
893
        case (length)
894
         2: polynom = 32'b11;                               // 0x3
895
         3: polynom = 32'b110;                              // 0x6
896
         4: polynom = 32'b1100;                             // 0xC
897
         5: polynom = 32'b10100;                            // 0x14
898
         6: polynom = 32'b110000;                           // 0x30
899
         7: polynom = 32'b1100000;                          // 0x60
900
         8: polynom = 32'b10111000;                         // 0xb8
901
         9: polynom = 32'b100010000;                        // 0x110
902
        10: polynom = 32'b1001000000;                       // 0x240
903
        11: polynom = 32'b10100000000;                      // 0x500
904
        12: polynom = 32'b100000101001;                     // 0x829
905
        13: polynom = 32'b1000000001100;                    // 0x100C
906
        14: polynom = 32'b10000000010101;                   // 0x2015
907
        15: polynom = 32'b110000000000000;                  // 0x6000
908
        16: polynom = 32'b1101000000001000;                 // 0xD008
909
        17: polynom = 32'b10010000000000000;                // 0x12000
910
        18: polynom = 32'b100000010000000000;               // 0x20400
911
        19: polynom = 32'b1000000000000100011;              // 0x40023
912
        20: polynom = 32'b10000010000000000000;             // 0x82000
913
        21: polynom = 32'b101000000000000000000;            // 0x140000
914
        22: polynom = 32'b1100000000000000000000;           // 0x300000
915
        23: polynom = 32'b10000100000000000000000;          // 0x420000
916
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
917
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
918
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
919
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
920
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
921
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
922
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
923
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
924
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
925
        default: polynom = 32'b0;
926
        endcase
927
        lfsr_fb = qi[length];
928
        for (i=length-1; i>=1; i=i-1) begin
929
            if (polynom[i])
930
                lfsr_fb = lfsr_fb  ~^ qi[i];
931
        end
932
    end
933
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
934
 
935
   always @ (posedge clk or posedge rst)
936
     if (rst)
937
       qi <= {length{1'b0}};
938
     else
939
       qi <= q_next;
940
 
941
 
942
 
943
   always @ (posedge clk or posedge rst)
944
     if (rst)
945
       zq <= 1'b1;
946
     else
947
       zq <= q_next == {length{1'b0}};
948
endmodule
949
//////////////////////////////////////////////////////////////////////
950
////                                                              ////
951
////  Versatile counter                                           ////
952
////                                                              ////
953
////  Description                                                 ////
954
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
955
////  counter                                                     ////
956
////                                                              ////
957
////  To Do:                                                      ////
958
////   - add LFSR with more taps                                  ////
959
////                                                              ////
960
////  Author(s):                                                  ////
961
////      - Michael Unneback, unneback@opencores.org              ////
962
////        ORSoC AB                                              ////
963
////                                                              ////
964
//////////////////////////////////////////////////////////////////////
965
////                                                              ////
966
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
967
////                                                              ////
968
//// This source file may be used and distributed without         ////
969
//// restriction provided that this copyright statement is not    ////
970
//// removed from the file and that any derivative work contains  ////
971
//// the original copyright notice and the associated disclaimer. ////
972
////                                                              ////
973
//// This source file is free software; you can redistribute it   ////
974
//// and/or modify it under the terms of the GNU Lesser General   ////
975
//// Public License as published by the Free Software Foundation; ////
976
//// either version 2.1 of the License, or (at your option) any   ////
977
//// later version.                                               ////
978
////                                                              ////
979
//// This source is distributed in the hope that it will be       ////
980
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
981
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
982
//// PURPOSE.  See the GNU Lesser General Public License for more ////
983
//// details.                                                     ////
984
////                                                              ////
985
//// You should have received a copy of the GNU Lesser General    ////
986
//// Public License along with this source; if not, download it   ////
987
//// from http://www.opencores.org/lgpl.shtml                     ////
988
////                                                              ////
989
//////////////////////////////////////////////////////////////////////
990
 
991
// LFSR counter
992
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
993
 
994
   parameter length = 4;
995
   input cke;
996
   output reg zq;
997
   input rst;
998
   input clk;
999
 
1000
   parameter clear_value = 0;
1001
   parameter set_value = 1;
1002
   parameter wrap_value = 8;
1003
   parameter level1_value = 15;
1004
 
1005
   reg  [length:1] qi;
1006
   reg lfsr_fb;
1007
   wire [length:1] q_next;
1008
   reg [32:1] polynom;
1009
   integer i;
1010
 
1011
   always @ (qi)
1012
   begin
1013
        case (length)
1014
         2: polynom = 32'b11;                               // 0x3
1015
         3: polynom = 32'b110;                              // 0x6
1016
         4: polynom = 32'b1100;                             // 0xC
1017
         5: polynom = 32'b10100;                            // 0x14
1018
         6: polynom = 32'b110000;                           // 0x30
1019
         7: polynom = 32'b1100000;                          // 0x60
1020
         8: polynom = 32'b10111000;                         // 0xb8
1021
         9: polynom = 32'b100010000;                        // 0x110
1022
        10: polynom = 32'b1001000000;                       // 0x240
1023
        11: polynom = 32'b10100000000;                      // 0x500
1024
        12: polynom = 32'b100000101001;                     // 0x829
1025
        13: polynom = 32'b1000000001100;                    // 0x100C
1026
        14: polynom = 32'b10000000010101;                   // 0x2015
1027
        15: polynom = 32'b110000000000000;                  // 0x6000
1028
        16: polynom = 32'b1101000000001000;                 // 0xD008
1029
        17: polynom = 32'b10010000000000000;                // 0x12000
1030
        18: polynom = 32'b100000010000000000;               // 0x20400
1031
        19: polynom = 32'b1000000000000100011;              // 0x40023
1032
        20: polynom = 32'b10000010000000000000;             // 0x82000
1033
        21: polynom = 32'b101000000000000000000;            // 0x140000
1034
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1035
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1036
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1037
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1038
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1039
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1040
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1041
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1042
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1043
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1044
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1045
        default: polynom = 32'b0;
1046
        endcase
1047
        lfsr_fb = qi[length];
1048
        for (i=length-1; i>=1; i=i-1) begin
1049
            if (polynom[i])
1050
                lfsr_fb = lfsr_fb  ~^ qi[i];
1051
        end
1052
    end
1053
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1054
 
1055
   always @ (posedge clk or posedge rst)
1056
     if (rst)
1057
       qi <= {length{1'b0}};
1058
     else
1059
     if (cke)
1060
       qi <= q_next;
1061
 
1062
 
1063
 
1064
   always @ (posedge clk or posedge rst)
1065
     if (rst)
1066
       zq <= 1'b1;
1067
     else
1068
     if (cke)
1069
       zq <= q_next == {length{1'b0}};
1070
endmodule
1071
//////////////////////////////////////////////////////////////////////
1072
////                                                              ////
1073
////  Versatile counter                                           ////
1074
////                                                              ////
1075
////  Description                                                 ////
1076
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1077
////  counter                                                     ////
1078
////                                                              ////
1079
////  To Do:                                                      ////
1080
////   - add LFSR with more taps                                  ////
1081
////                                                              ////
1082
////  Author(s):                                                  ////
1083
////      - Michael Unneback, unneback@opencores.org              ////
1084
////        ORSoC AB                                              ////
1085
////                                                              ////
1086
//////////////////////////////////////////////////////////////////////
1087
////                                                              ////
1088
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1089
////                                                              ////
1090
//// This source file may be used and distributed without         ////
1091
//// restriction provided that this copyright statement is not    ////
1092
//// removed from the file and that any derivative work contains  ////
1093
//// the original copyright notice and the associated disclaimer. ////
1094
////                                                              ////
1095
//// This source file is free software; you can redistribute it   ////
1096
//// and/or modify it under the terms of the GNU Lesser General   ////
1097
//// Public License as published by the Free Software Foundation; ////
1098
//// either version 2.1 of the License, or (at your option) any   ////
1099
//// later version.                                               ////
1100
////                                                              ////
1101
//// This source is distributed in the hope that it will be       ////
1102
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1103
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1104
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1105
//// details.                                                     ////
1106
////                                                              ////
1107
//// You should have received a copy of the GNU Lesser General    ////
1108
//// Public License along with this source; if not, download it   ////
1109
//// from http://www.opencores.org/lgpl.shtml                     ////
1110
////                                                              ////
1111
//////////////////////////////////////////////////////////////////////
1112
 
1113
// LFSR counter
1114
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1115
 
1116
   parameter length = 4;
1117
   input cke;
1118
   input rew;
1119
   output reg level1;
1120
   input rst;
1121
   input clk;
1122
 
1123
   parameter clear_value = 0;
1124
   parameter set_value = 1;
1125
   parameter wrap_value = 8;
1126
   parameter level1_value = 15;
1127
 
1128
   reg  [length:1] qi;
1129
   reg lfsr_fb, lfsr_fb_rew;
1130
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1131
   reg [32:1] polynom_rew;
1132
   integer j;
1133
   reg [32:1] polynom;
1134
   integer i;
1135
 
1136
   always @ (qi)
1137
   begin
1138
        case (length)
1139
         2: polynom = 32'b11;                               // 0x3
1140
         3: polynom = 32'b110;                              // 0x6
1141
         4: polynom = 32'b1100;                             // 0xC
1142
         5: polynom = 32'b10100;                            // 0x14
1143
         6: polynom = 32'b110000;                           // 0x30
1144
         7: polynom = 32'b1100000;                          // 0x60
1145
         8: polynom = 32'b10111000;                         // 0xb8
1146
         9: polynom = 32'b100010000;                        // 0x110
1147
        10: polynom = 32'b1001000000;                       // 0x240
1148
        11: polynom = 32'b10100000000;                      // 0x500
1149
        12: polynom = 32'b100000101001;                     // 0x829
1150
        13: polynom = 32'b1000000001100;                    // 0x100C
1151
        14: polynom = 32'b10000000010101;                   // 0x2015
1152
        15: polynom = 32'b110000000000000;                  // 0x6000
1153
        16: polynom = 32'b1101000000001000;                 // 0xD008
1154
        17: polynom = 32'b10010000000000000;                // 0x12000
1155
        18: polynom = 32'b100000010000000000;               // 0x20400
1156
        19: polynom = 32'b1000000000000100011;              // 0x40023
1157
        20: polynom = 32'b10000010000000000000;             // 0x82000
1158
        21: polynom = 32'b101000000000000000000;            // 0x140000
1159
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1160
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1161
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1162
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1163
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1164
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1165
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1166
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1167
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1168
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1169
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1170
        default: polynom = 32'b0;
1171
        endcase
1172
        lfsr_fb = qi[length];
1173
        for (i=length-1; i>=1; i=i-1) begin
1174
            if (polynom[i])
1175
                lfsr_fb = lfsr_fb  ~^ qi[i];
1176
        end
1177
    end
1178
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1179
   always @ (qi)
1180
   begin
1181
        case (length)
1182
         2: polynom_rew = 32'b11;
1183
         3: polynom_rew = 32'b110;
1184
         4: polynom_rew = 32'b1100;
1185
         5: polynom_rew = 32'b10100;
1186
         6: polynom_rew = 32'b110000;
1187
         7: polynom_rew = 32'b1100000;
1188
         8: polynom_rew = 32'b10111000;
1189
         9: polynom_rew = 32'b100010000;
1190
        10: polynom_rew = 32'b1001000000;
1191
        11: polynom_rew = 32'b10100000000;
1192
        12: polynom_rew = 32'b100000101001;
1193
        13: polynom_rew = 32'b1000000001100;
1194
        14: polynom_rew = 32'b10000000010101;
1195
        15: polynom_rew = 32'b110000000000000;
1196
        16: polynom_rew = 32'b1101000000001000;
1197
        17: polynom_rew = 32'b10010000000000000;
1198
        18: polynom_rew = 32'b100000010000000000;
1199
        19: polynom_rew = 32'b1000000000000100011;
1200
        20: polynom_rew = 32'b10000010000000000000;
1201
        21: polynom_rew = 32'b101000000000000000000;
1202
        22: polynom_rew = 32'b1100000000000000000000;
1203
        23: polynom_rew = 32'b10000100000000000000000;
1204
        24: polynom_rew = 32'b111000010000000000000000;
1205
        25: polynom_rew = 32'b1001000000000000000000000;
1206
        26: polynom_rew = 32'b10000000000000000000100011;
1207
        27: polynom_rew = 32'b100000000000000000000010011;
1208
        28: polynom_rew = 32'b1100100000000000000000000000;
1209
        29: polynom_rew = 32'b10100000000000000000000000000;
1210
        30: polynom_rew = 32'b100000000000000000000000101001;
1211
        31: polynom_rew = 32'b1001000000000000000000000000000;
1212
        32: polynom_rew = 32'b10000000001000000000000000000011;
1213
        default: polynom_rew = 32'b0;
1214
        endcase
1215
        // rotate left
1216
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1217
        lfsr_fb_rew = qi[length];
1218
        for (i=length-1; i>=1; i=i-1) begin
1219
            if (polynom_rew[i])
1220
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1221
        end
1222
    end
1223
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1224
   assign q_next = rew ? q_next_rew : q_next_fw;
1225
 
1226
   always @ (posedge clk or posedge rst)
1227
     if (rst)
1228
       qi <= {length{1'b0}};
1229
     else
1230
     if (cke)
1231
       qi <= q_next;
1232
 
1233
 
1234
 
1235
    always @ (posedge clk or posedge rst)
1236
    if (rst)
1237
        level1 <= 1'b0;
1238
    else
1239
    if (cke)
1240
    if (q_next == level1_value)
1241
        level1 <= 1'b1;
1242
    else if (qi == level1_value & rew)
1243
        level1 <= 1'b0;
1244
endmodule
1245
//////////////////////////////////////////////////////////////////////
1246
////                                                              ////
1247
////  Versatile counter                                           ////
1248
////                                                              ////
1249
////  Description                                                 ////
1250
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1251
////  counter                                                     ////
1252
////                                                              ////
1253
////  To Do:                                                      ////
1254
////   - add LFSR with more taps                                  ////
1255
////                                                              ////
1256
////  Author(s):                                                  ////
1257
////      - Michael Unneback, unneback@opencores.org              ////
1258
////        ORSoC AB                                              ////
1259
////                                                              ////
1260
//////////////////////////////////////////////////////////////////////
1261
////                                                              ////
1262
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1263
////                                                              ////
1264
//// This source file may be used and distributed without         ////
1265
//// restriction provided that this copyright statement is not    ////
1266
//// removed from the file and that any derivative work contains  ////
1267
//// the original copyright notice and the associated disclaimer. ////
1268
////                                                              ////
1269
//// This source file is free software; you can redistribute it   ////
1270
//// and/or modify it under the terms of the GNU Lesser General   ////
1271
//// Public License as published by the Free Software Foundation; ////
1272
//// either version 2.1 of the License, or (at your option) any   ////
1273
//// later version.                                               ////
1274
////                                                              ////
1275
//// This source is distributed in the hope that it will be       ////
1276
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1277
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1278
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1279
//// details.                                                     ////
1280
////                                                              ////
1281
//// You should have received a copy of the GNU Lesser General    ////
1282
//// Public License along with this source; if not, download it   ////
1283
//// from http://www.opencores.org/lgpl.shtml                     ////
1284
////                                                              ////
1285
//////////////////////////////////////////////////////////////////////
1286
 
1287
// GRAY counter
1288
module cnt_gray ( q, rst, clk);
1289
 
1290
   parameter length = 4;
1291
   output reg [length:1] q;
1292
   input rst;
1293
   input clk;
1294
 
1295
   parameter clear_value = 0;
1296
   parameter set_value = 1;
1297
   parameter wrap_value = 8;
1298
   parameter level1_value = 15;
1299
 
1300
   reg  [length:1] qi;
1301
   wire [length:1] q_next;
1302
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1303
 
1304
   always @ (posedge clk or posedge rst)
1305
     if (rst)
1306
       qi <= {length{1'b0}};
1307
     else
1308
       qi <= q_next;
1309
 
1310
   always @ (posedge clk or posedge rst)
1311
     if (rst)
1312
       q <= {length{1'b0}};
1313
     else
1314
         q <= (q_next>>1) ^ q_next;
1315
 
1316
endmodule
1317
//////////////////////////////////////////////////////////////////////
1318
////                                                              ////
1319
////  Versatile counter                                           ////
1320
////                                                              ////
1321
////  Description                                                 ////
1322
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1323
////  counter                                                     ////
1324
////                                                              ////
1325
////  To Do:                                                      ////
1326
////   - add LFSR with more taps                                  ////
1327
////                                                              ////
1328
////  Author(s):                                                  ////
1329
////      - Michael Unneback, unneback@opencores.org              ////
1330
////        ORSoC AB                                              ////
1331
////                                                              ////
1332
//////////////////////////////////////////////////////////////////////
1333
////                                                              ////
1334
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1335
////                                                              ////
1336
//// This source file may be used and distributed without         ////
1337
//// restriction provided that this copyright statement is not    ////
1338
//// removed from the file and that any derivative work contains  ////
1339
//// the original copyright notice and the associated disclaimer. ////
1340
////                                                              ////
1341
//// This source file is free software; you can redistribute it   ////
1342
//// and/or modify it under the terms of the GNU Lesser General   ////
1343
//// Public License as published by the Free Software Foundation; ////
1344
//// either version 2.1 of the License, or (at your option) any   ////
1345
//// later version.                                               ////
1346
////                                                              ////
1347
//// This source is distributed in the hope that it will be       ////
1348
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1349
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1350
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1351
//// details.                                                     ////
1352
////                                                              ////
1353
//// You should have received a copy of the GNU Lesser General    ////
1354
//// Public License along with this source; if not, download it   ////
1355
//// from http://www.opencores.org/lgpl.shtml                     ////
1356
////                                                              ////
1357
//////////////////////////////////////////////////////////////////////
1358
 
1359
// GRAY counter
1360
module cnt_gray_ce ( cke, q, rst, clk);
1361
 
1362
   parameter length = 4;
1363
   input cke;
1364
   output reg [length:1] q;
1365
   input rst;
1366
   input clk;
1367
 
1368
   parameter clear_value = 0;
1369
   parameter set_value = 1;
1370
   parameter wrap_value = 8;
1371
   parameter level1_value = 15;
1372
 
1373
   reg  [length:1] qi;
1374
   wire [length:1] q_next;
1375
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1376
 
1377
   always @ (posedge clk or posedge rst)
1378
     if (rst)
1379
       qi <= {length{1'b0}};
1380
     else
1381
     if (cke)
1382
       qi <= q_next;
1383
 
1384
   always @ (posedge clk or posedge rst)
1385
     if (rst)
1386
       q <= {length{1'b0}};
1387
     else
1388
       if (cke)
1389
         q <= (q_next>>1) ^ q_next;
1390
 
1391
endmodule
1392
//////////////////////////////////////////////////////////////////////
1393
////                                                              ////
1394
////  Versatile counter                                           ////
1395
////                                                              ////
1396
////  Description                                                 ////
1397
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1398
////  counter                                                     ////
1399
////                                                              ////
1400
////  To Do:                                                      ////
1401
////   - add LFSR with more taps                                  ////
1402
////                                                              ////
1403
////  Author(s):                                                  ////
1404
////      - Michael Unneback, unneback@opencores.org              ////
1405
////        ORSoC AB                                              ////
1406
////                                                              ////
1407
//////////////////////////////////////////////////////////////////////
1408
////                                                              ////
1409
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1410
////                                                              ////
1411
//// This source file may be used and distributed without         ////
1412
//// restriction provided that this copyright statement is not    ////
1413
//// removed from the file and that any derivative work contains  ////
1414
//// the original copyright notice and the associated disclaimer. ////
1415
////                                                              ////
1416
//// This source file is free software; you can redistribute it   ////
1417
//// and/or modify it under the terms of the GNU Lesser General   ////
1418
//// Public License as published by the Free Software Foundation; ////
1419
//// either version 2.1 of the License, or (at your option) any   ////
1420
//// later version.                                               ////
1421
////                                                              ////
1422
//// This source is distributed in the hope that it will be       ////
1423
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1424
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1425
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1426
//// details.                                                     ////
1427
////                                                              ////
1428
//// You should have received a copy of the GNU Lesser General    ////
1429
//// Public License along with this source; if not, download it   ////
1430
//// from http://www.opencores.org/lgpl.shtml                     ////
1431
////                                                              ////
1432
//////////////////////////////////////////////////////////////////////
1433
 
1434
// GRAY counter
1435
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1436
 
1437
   parameter length = 4;
1438
   input cke;
1439
   output reg [length:1] q;
1440
   output [length:1] q_bin;
1441
   input rst;
1442
   input clk;
1443
 
1444
   parameter clear_value = 0;
1445
   parameter set_value = 1;
1446
   parameter wrap_value = 8;
1447
   parameter level1_value = 15;
1448
 
1449
   reg  [length:1] qi;
1450
   wire [length:1] q_next;
1451
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1452
 
1453
   always @ (posedge clk or posedge rst)
1454
     if (rst)
1455
       qi <= {length{1'b0}};
1456
     else
1457
     if (cke)
1458
       qi <= q_next;
1459
 
1460
   always @ (posedge clk or posedge rst)
1461
     if (rst)
1462
       q <= {length{1'b0}};
1463
     else
1464
       if (cke)
1465
         q <= (q_next>>1) ^ q_next;
1466
 
1467
   assign q_bin = qi;
1468
 
1469
endmodule
1470
//////////////////////////////////////////////////////////////////////
1471
////                                                              ////
1472
////  Versatile library, counters                                 ////
1473
////                                                              ////
1474
////  Description                                                 ////
1475
////  counters                                                    ////
1476
////                                                              ////
1477
////                                                              ////
1478
////  To Do:                                                      ////
1479
////   - add more counters                                        ////
1480
////                                                              ////
1481
////  Author(s):                                                  ////
1482
////      - Michael Unneback, unneback@opencores.org              ////
1483
////        ORSoC AB                                              ////
1484
////                                                              ////
1485
//////////////////////////////////////////////////////////////////////
1486
////                                                              ////
1487
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1488
////                                                              ////
1489
//// This source file may be used and distributed without         ////
1490
//// restriction provided that this copyright statement is not    ////
1491
//// removed from the file and that any derivative work contains  ////
1492
//// the original copyright notice and the associated disclaimer. ////
1493
////                                                              ////
1494
//// This source file is free software; you can redistribute it   ////
1495
//// and/or modify it under the terms of the GNU Lesser General   ////
1496
//// Public License as published by the Free Software Foundation; ////
1497
//// either version 2.1 of the License, or (at your option) any   ////
1498
//// later version.                                               ////
1499
////                                                              ////
1500
//// This source is distributed in the hope that it will be       ////
1501
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1502
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1503
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1504
//// details.                                                     ////
1505
////                                                              ////
1506
//// You should have received a copy of the GNU Lesser General    ////
1507
//// Public License along with this source; if not, download it   ////
1508
//// from http://www.opencores.org/lgpl.shtml                     ////
1509
////                                                              ////
1510
//////////////////////////////////////////////////////////////////////
1511
 
1512
module cnt_shreg_wrap ( q, rst, clk);
1513
 
1514
   parameter length = 4;
1515
   output reg [0:length-1] q;
1516
   input rst;
1517
   input clk;
1518
 
1519
    always @ (posedge clk or posedge rst)
1520
    if (rst)
1521
        q <= {1'b1,{length-1{1'b0}}};
1522
    else
1523
        q <= {q[length-1],q[0:length-2]};
1524
 
1525
endmodule
1526
 
1527
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
1528
 
1529
   parameter length = 4;
1530
   input cke;
1531
   output reg [0:length-1] q;
1532
   input rst;
1533
   input clk;
1534
 
1535
    always @ (posedge clk or posedge rst)
1536
    if (rst)
1537
        q <= {1'b1,{length-1{1'b0}}};
1538
    else
1539
        if (cke)
1540
            q <= {q[length-1],q[0:length-2]};
1541
 
1542
endmodule
1543
 
1544
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1545
 
1546
   parameter length = 4;
1547
   input cke, clear;
1548
   output reg [0:length-1] q;
1549
   input rst;
1550
   input clk;
1551
 
1552
    always @ (posedge clk or posedge rst)
1553
    if (rst)
1554
        q <= {1'b1,{length-1{1'b0}}};
1555
    else
1556
        if (cke)
1557
            if (clear)
1558
                q <= {1'b1,{length-1{1'b0}}};
1559
            else
1560
                q <= q >> 1;
1561
 
1562
endmodule
1563
 
1564
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1565
 
1566
   parameter length = 4;
1567
   input cke, clear;
1568
   output reg [0:length-1] q;
1569
   input rst;
1570
   input clk;
1571
 
1572
    always @ (posedge clk or posedge rst)
1573
    if (rst)
1574
        q <= {1'b1,{length-1{1'b0}}};
1575
    else
1576
        if (cke)
1577
            if (clear)
1578
                q <= {1'b1,{length-1{1'b0}}};
1579
            else
1580
            q <= {q[length-1],q[0:length-2]};
1581
 
1582
endmodule
1583
//////////////////////////////////////////////////////////////////////
1584
////                                                              ////
1585
////  Versatile library, memories                                 ////
1586
////                                                              ////
1587
////  Description                                                 ////
1588
////  memories                                                    ////
1589
////                                                              ////
1590
////                                                              ////
1591
////  To Do:                                                      ////
1592
////   - add more memory types                                    ////
1593
////                                                              ////
1594
////  Author(s):                                                  ////
1595
////      - Michael Unneback, unneback@opencores.org              ////
1596
////        ORSoC AB                                              ////
1597
////                                                              ////
1598
//////////////////////////////////////////////////////////////////////
1599
////                                                              ////
1600
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1601
////                                                              ////
1602
//// This source file may be used and distributed without         ////
1603
//// restriction provided that this copyright statement is not    ////
1604
//// removed from the file and that any derivative work contains  ////
1605
//// the original copyright notice and the associated disclaimer. ////
1606
////                                                              ////
1607
//// This source file is free software; you can redistribute it   ////
1608
//// and/or modify it under the terms of the GNU Lesser General   ////
1609
//// Public License as published by the Free Software Foundation; ////
1610
//// either version 2.1 of the License, or (at your option) any   ////
1611
//// later version.                                               ////
1612
////                                                              ////
1613
//// This source is distributed in the hope that it will be       ////
1614
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1615
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1616
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1617
//// details.                                                     ////
1618
////                                                              ////
1619
//// You should have received a copy of the GNU Lesser General    ////
1620
//// Public License along with this source; if not, download it   ////
1621
//// from http://www.opencores.org/lgpl.shtml                     ////
1622
////                                                              ////
1623
//////////////////////////////////////////////////////////////////////
1624
 
1625
/// ROM
1626
 
1627 7 unneback
module vl_rom_init ( adr, q, clk);
1628
   parameter data_width = 32;
1629
   parameter addr_width = 8;
1630
   input [(addr_width-1):0]       adr;
1631
   output reg [(data_width-1):0] q;
1632
   input                         clk;
1633
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1634
   parameter memory_file = "vl_rom.vmem";
1635
   initial
1636
     begin
1637
        $readmemh(memory_file, rom);
1638
     end
1639
 
1640
   always @ (posedge clk)
1641
     q <= rom[adr];
1642 6 unneback
 
1643 7 unneback
endmodule
1644
 
1645 14 unneback
/*
1646 7 unneback
module vl_rom ( adr, q, clk);
1647
 
1648 6 unneback
parameter data_width = 32;
1649
parameter addr_width = 4;
1650
 
1651
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1652
    {32'h18000000},
1653
    {32'hA8200000},
1654
    {32'hA8200000},
1655
    {32'hA8200000},
1656
    {32'h44003000},
1657
    {32'h15000000},
1658
    {32'h15000000},
1659
    {32'h15000000},
1660
    {32'h15000000},
1661
    {32'h15000000},
1662
    {32'h15000000},
1663
    {32'h15000000},
1664
    {32'h15000000},
1665
    {32'h15000000},
1666
    {32'h15000000},
1667
    {32'h15000000}};
1668
 
1669 7 unneback
input [addr_width-1:0] adr;
1670 6 unneback
output reg [data_width-1:0] q;
1671
input clk;
1672
 
1673
always @ (posedge clk)
1674 7 unneback
    q <= data[adr];
1675 6 unneback
 
1676
endmodule
1677 14 unneback
*/
1678 6 unneback
// Single port RAM
1679
 
1680
module vl_ram ( d, adr, we, q, clk);
1681
   parameter data_width = 32;
1682
   parameter addr_width = 8;
1683
   input [(data_width-1):0]      d;
1684
   input [(addr_width-1):0]       adr;
1685
   input                         we;
1686 7 unneback
   output reg [(data_width-1):0] q;
1687 6 unneback
   input                         clk;
1688
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1689 7 unneback
   parameter init = 0;
1690
   parameter memory_file = "vl_ram.vmem";
1691
   generate if (init) begin : init_mem
1692
   initial
1693
     begin
1694
        $readmemh(memory_file, ram);
1695
     end
1696
   end
1697
   endgenerate
1698
 
1699 6 unneback
   always @ (posedge clk)
1700
   begin
1701
   if (we)
1702
     ram[adr] <= d;
1703
   q <= ram[adr];
1704
   end
1705
 
1706
endmodule
1707
 
1708 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1709
   parameter data_width = 32;
1710
   parameter addr_width = 8;
1711
   input [(data_width-1):0]      d;
1712
   input [(addr_width-1):0]       adr;
1713
   input [(addr_width/4)-1:0]    be;
1714
   input                         we;
1715
   output reg [(data_width-1):0] q;
1716
   input                         clk;
1717
 
1718
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1719
 
1720
   parameter init = 0;
1721
   parameter memory_file = "vl_ram.vmem";
1722
   generate if (init) begin : init_mem
1723
   initial
1724
     begin
1725
        $readmemh(memory_file, ram);
1726
     end
1727
   end
1728
   endgenerate
1729
 
1730
   genvar i;
1731
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1732
      always @ (posedge clk)
1733
      if (we & be[i])
1734
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1735
   end
1736
   endgenerate
1737
 
1738
   always @ (posedge clk)
1739
      q <= ram[adr];
1740
 
1741
endmodule
1742
 
1743
 
1744 6 unneback
// Dual port RAM
1745
 
1746
// ACTEL FPGA should not use logic to handle rw collision
1747
`ifdef ACTEL
1748
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
1749
`else
1750
        `define SYN
1751
`endif
1752
 
1753 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1754 6 unneback
   parameter data_width = 32;
1755
   parameter addr_width = 8;
1756
   input [(data_width-1):0]      d_a;
1757
   input [(addr_width-1):0]       adr_a;
1758
   input [(addr_width-1):0]       adr_b;
1759
   input                         we_a;
1760
   output [(data_width-1):0]      q_b;
1761
   input                         clk_a, clk_b;
1762
   reg [(addr_width-1):0]         adr_b_reg;
1763
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
1764 7 unneback
 
1765
   parameter init = 0;
1766
   parameter memory_file = "vl_ram.vmem";
1767
   generate if (init) begin : init_mem
1768
   initial
1769
     begin
1770
        $readmemh(memory_file, ram);
1771
     end
1772
   end
1773
   endgenerate
1774
 
1775 6 unneback
   always @ (posedge clk_a)
1776
   if (we_a)
1777
     ram[adr_a] <= d_a;
1778
   always @ (posedge clk_b)
1779
   adr_b_reg <= adr_b;
1780
   assign q_b = ram[adr_b_reg];
1781
endmodule
1782
 
1783 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1784 6 unneback
   parameter data_width = 32;
1785
   parameter addr_width = 8;
1786
   input [(data_width-1):0]      d_a;
1787
   input [(addr_width-1):0]       adr_a;
1788
   input [(addr_width-1):0]       adr_b;
1789
   input                         we_a;
1790
   output [(data_width-1):0]      q_b;
1791
   output reg [(data_width-1):0] q_a;
1792
   input                         clk_a, clk_b;
1793
   reg [(data_width-1):0]         q_b;
1794
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
1795 7 unneback
 
1796
   parameter init = 0;
1797
   parameter memory_file = "vl_ram.vmem";
1798
   generate if (init) begin : init_mem
1799
   initial
1800
     begin
1801
        $readmemh(memory_file, ram);
1802
     end
1803
   end
1804
   endgenerate
1805
 
1806 6 unneback
   always @ (posedge clk_a)
1807
     begin
1808
        q_a <= ram[adr_a];
1809
        if (we_a)
1810
             ram[adr_a] <= d_a;
1811
     end
1812
   always @ (posedge clk_b)
1813
          q_b <= ram[adr_b];
1814
endmodule
1815
 
1816 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1817 6 unneback
   parameter data_width = 32;
1818
   parameter addr_width = 8;
1819
   input [(data_width-1):0]      d_a;
1820
   input [(addr_width-1):0]       adr_a;
1821
   input [(addr_width-1):0]       adr_b;
1822
   input                         we_a;
1823
   output [(data_width-1):0]      q_b;
1824
   input [(data_width-1):0]       d_b;
1825
   output reg [(data_width-1):0] q_a;
1826
   input                         we_b;
1827
   input                         clk_a, clk_b;
1828
   reg [(data_width-1):0]         q_b;
1829
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
1830 7 unneback
 
1831
   parameter init = 0;
1832
   parameter memory_file = "vl_ram.vmem";
1833
   generate if (init) begin : init_mem
1834
   initial
1835
     begin
1836
        $readmemh(memory_file, ram);
1837
     end
1838
   end
1839
   endgenerate
1840
 
1841 6 unneback
   always @ (posedge clk_a)
1842
     begin
1843
        q_a <= ram[adr_a];
1844
        if (we_a)
1845
             ram[adr_a] <= d_a;
1846
     end
1847
   always @ (posedge clk_b)
1848
     begin
1849
        q_b <= ram[adr_b];
1850
        if (we_b)
1851
          ram[adr_b] <= d_b;
1852
     end
1853
endmodule
1854
 
1855
// Content addresable memory, CAM
1856
 
1857
// FIFO
1858
 
1859
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1860
 
1861 11 unneback
   parameter addr_width = 4;
1862
   parameter N = addr_width-1;
1863 6 unneback
 
1864
   parameter Q1 = 2'b00;
1865
   parameter Q2 = 2'b01;
1866
   parameter Q3 = 2'b11;
1867
   parameter Q4 = 2'b10;
1868
 
1869
   parameter going_empty = 1'b0;
1870
   parameter going_full  = 1'b1;
1871
 
1872
   input [N:0]  wptr, rptr;
1873 14 unneback
   output       fifo_empty;
1874 6 unneback
   output       fifo_full;
1875
   input        wclk, rclk, rst;
1876
 
1877
`ifndef GENERATE_DIRECTION_AS_LATCH
1878
   wire direction;
1879
`endif
1880
`ifdef GENERATE_DIRECTION_AS_LATCH
1881
   reg direction;
1882
`endif
1883
   reg  direction_set, direction_clr;
1884
 
1885
   wire async_empty, async_full;
1886
   wire fifo_full2;
1887 14 unneback
   wire fifo_empty2;
1888 6 unneback
 
1889
   // direction_set
1890
   always @ (wptr[N:N-1] or rptr[N:N-1])
1891
     case ({wptr[N:N-1],rptr[N:N-1]})
1892
       {Q1,Q2} : direction_set <= 1'b1;
1893
       {Q2,Q3} : direction_set <= 1'b1;
1894
       {Q3,Q4} : direction_set <= 1'b1;
1895
       {Q4,Q1} : direction_set <= 1'b1;
1896
       default : direction_set <= 1'b0;
1897
     endcase
1898
 
1899
   // direction_clear
1900
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1901
     if (rst)
1902
       direction_clr <= 1'b1;
1903
     else
1904
       case ({wptr[N:N-1],rptr[N:N-1]})
1905
         {Q2,Q1} : direction_clr <= 1'b1;
1906
         {Q3,Q2} : direction_clr <= 1'b1;
1907
         {Q4,Q3} : direction_clr <= 1'b1;
1908
         {Q1,Q4} : direction_clr <= 1'b1;
1909
         default : direction_clr <= 1'b0;
1910
       endcase
1911
 
1912
`ifndef GENERATE_DIRECTION_AS_LATCH
1913
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1914
`endif
1915
 
1916
`ifdef GENERATE_DIRECTION_AS_LATCH
1917
   always @ (posedge direction_set or posedge direction_clr)
1918
     if (direction_clr)
1919
       direction <= going_empty;
1920
     else
1921
       direction <= going_full;
1922
`endif
1923
 
1924
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1925
   assign async_full  = (wptr == rptr) && (direction==going_full);
1926
 
1927
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1928
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1929
 
1930
/*
1931
   always @ (posedge wclk or posedge rst or posedge async_full)
1932
     if (rst)
1933
       {fifo_full, fifo_full2} <= 2'b00;
1934
     else if (async_full)
1935
       {fifo_full, fifo_full2} <= 2'b11;
1936
     else
1937
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1938
*/
1939 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1940 6 unneback
     if (async_empty)
1941
       {fifo_empty, fifo_empty2} <= 2'b11;
1942
     else
1943 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1944
    dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1945
    dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1946 6 unneback
 
1947
endmodule // async_comp
1948
 
1949
module vl_fifo_1r1w_async (
1950
    d, wr, fifo_full, wr_clk, wr_rst,
1951
    q, rd, fifo_empty, rd_clk, rd_rst
1952
    );
1953
 
1954
parameter data_width = 18;
1955
parameter addr_width = 4;
1956
 
1957
// write side
1958
input  [data_width-1:0] d;
1959
input                   wr;
1960
output                  fifo_full;
1961
input                   wr_clk;
1962
input                   wr_rst;
1963
// read side
1964
output [data_width-1:0] q;
1965
input                   rd;
1966
output                  fifo_empty;
1967
input                   rd_clk;
1968
input                   rd_rst;
1969
 
1970
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1971
 
1972
vl_fifo_1r1w_async (
1973
    d, wr, fifo_full, wr_clk, wr_rst,
1974
    q, rd, fifo_empty, rd_clk, rd_rst
1975
    );
1976
 
1977 7 unneback
cnt_gray_ce_bin
1978 6 unneback
    # ( .length(addr_width))
1979
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1980
 
1981 7 unneback
cnt_gray_ce_bin
1982 6 unneback
    # (.length(addr_width))
1983
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
1984
 
1985 7 unneback
vl_dpram_1r1w
1986 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1987
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1988
 
1989
vl_fifo_cmp_async
1990
    # (.addr_width(addr_width))
1991
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1992
 
1993
endmodule
1994
 
1995 8 unneback
module vl_fifo_2r2w_async (
1996 6 unneback
    // a side
1997
    a_d, a_wr, a_fifo_full,
1998
    a_q, a_rd, a_fifo_empty,
1999
    a_clk, a_rst,
2000
    // b side
2001
    b_d, b_wr, b_fifo_full,
2002
    b_q, b_rd, b_fifo_empty,
2003
    b_clk, b_rst
2004
    );
2005
 
2006
parameter data_width = 18;
2007
parameter addr_width = 4;
2008
 
2009
// a side
2010
input  [data_width-1:0] a_d;
2011
input                   a_wr;
2012
output                  a_fifo_full;
2013
output [data_width-1:0] a_q;
2014
input                   a_rd;
2015
output                  a_fifo_empty;
2016
input                   a_clk;
2017
input                   a_rst;
2018
 
2019
// b side
2020
input  [data_width-1:0] b_d;
2021
input                   b_wr;
2022
output                  b_fifo_full;
2023
output [data_width-1:0] b_q;
2024
input                   b_rd;
2025
output                  b_fifo_empty;
2026
input                   b_clk;
2027
input                   b_rst;
2028
 
2029
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2030
vl_fifo_1r1w_async_a (
2031
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2032
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2033
    );
2034
 
2035
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2036
vl_fifo_1r1w_async_b (
2037
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2038
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2039
    );
2040
 
2041
endmodule
2042
 
2043 8 unneback
module vl_fifo_2r2w_async_simplex (
2044 6 unneback
    // a side
2045
    a_d, a_wr, a_fifo_full,
2046
    a_q, a_rd, a_fifo_empty,
2047
    a_clk, a_rst,
2048
    // b side
2049
    b_d, b_wr, b_fifo_full,
2050
    b_q, b_rd, b_fifo_empty,
2051
    b_clk, b_rst
2052
    );
2053
 
2054
parameter data_width = 18;
2055
parameter addr_width = 4;
2056
 
2057
// a side
2058
input  [data_width-1:0] a_d;
2059
input                   a_wr;
2060
output                  a_fifo_full;
2061
output [data_width-1:0] a_q;
2062
input                   a_rd;
2063
output                  a_fifo_empty;
2064
input                   a_clk;
2065
input                   a_rst;
2066
 
2067
// b side
2068
input  [data_width-1:0] b_d;
2069
input                   b_wr;
2070
output                  b_fifo_full;
2071
output [data_width-1:0] b_q;
2072
input                   b_rd;
2073
output                  b_fifo_empty;
2074
input                   b_clk;
2075
input                   b_rst;
2076
 
2077
// adr_gen
2078
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2079
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2080
// dpram
2081
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2082
 
2083 7 unneback
cnt_gray_ce_bin
2084 6 unneback
    # ( .length(addr_width))
2085
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2086
 
2087 7 unneback
cnt_gray_ce_bin
2088 6 unneback
    # (.length(addr_width))
2089
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2090
 
2091 7 unneback
cnt_gray_ce_bin
2092 6 unneback
    # ( .length(addr_width))
2093
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2094
 
2095 7 unneback
cnt_gray_ce_bin
2096 6 unneback
    # (.length(addr_width))
2097
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2098
 
2099
// mux read or write adr to DPRAM
2100
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2101
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2102
 
2103 11 unneback
vl_dpram_2r2w
2104 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2105
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2106
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2107
 
2108 11 unneback
vl_fifo_cmp_async
2109 6 unneback
    # (.addr_width(addr_width))
2110
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2111
 
2112 11 unneback
vl_fifo_cmp_async
2113 6 unneback
    # (.addr_width(addr_width))
2114
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2115
 
2116
endmodule
2117 12 unneback
//////////////////////////////////////////////////////////////////////
2118
////                                                              ////
2119
////  Versatile library, wishbone stuff                           ////
2120
////                                                              ////
2121
////  Description                                                 ////
2122
////  Wishbone compliant modules                                  ////
2123
////                                                              ////
2124
////                                                              ////
2125
////  To Do:                                                      ////
2126
////   -                                                          ////
2127
////                                                              ////
2128
////  Author(s):                                                  ////
2129
////      - Michael Unneback, unneback@opencores.org              ////
2130
////        ORSoC AB                                              ////
2131
////                                                              ////
2132
//////////////////////////////////////////////////////////////////////
2133
////                                                              ////
2134
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2135
////                                                              ////
2136
//// This source file may be used and distributed without         ////
2137
//// restriction provided that this copyright statement is not    ////
2138
//// removed from the file and that any derivative work contains  ////
2139
//// the original copyright notice and the associated disclaimer. ////
2140
////                                                              ////
2141
//// This source file is free software; you can redistribute it   ////
2142
//// and/or modify it under the terms of the GNU Lesser General   ////
2143
//// Public License as published by the Free Software Foundation; ////
2144
//// either version 2.1 of the License, or (at your option) any   ////
2145
//// later version.                                               ////
2146
////                                                              ////
2147
//// This source is distributed in the hope that it will be       ////
2148
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2149
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2150
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2151
//// details.                                                     ////
2152
////                                                              ////
2153
//// You should have received a copy of the GNU Lesser General    ////
2154
//// Public License along with this source; if not, download it   ////
2155
//// from http://www.opencores.org/lgpl.shtml                     ////
2156
////                                                              ////
2157
//////////////////////////////////////////////////////////////////////
2158
 
2159
// async wb3 - wb3 bridge
2160
`timescale 1ns/1ns
2161
module wb3wb3_bridge (
2162
        // wishbone slave side
2163
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2164
        // wishbone master side
2165
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2166
 
2167
input [31:0] wbs_dat_i;
2168
input [31:2] wbs_adr_i;
2169
input [3:0]  wbs_sel_i;
2170
input [1:0]  wbs_bte_i;
2171
input [2:0]  wbs_cti_i;
2172
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2173
output [31:0] wbs_dat_o;
2174 14 unneback
output wbs_ack_o;
2175 12 unneback
input wbs_clk, wbs_rst;
2176
 
2177
output [31:0] wbm_dat_o;
2178
output reg [31:2] wbm_adr_o;
2179
output [3:0]  wbm_sel_o;
2180
output reg [1:0]  wbm_bte_o;
2181
output reg [2:0]  wbm_cti_o;
2182 14 unneback
output reg wbm_we_o;
2183
output wbm_cyc_o;
2184 12 unneback
output wbm_stb_o;
2185
input [31:0]  wbm_dat_i;
2186
input wbm_ack_i;
2187
input wbm_clk, wbm_rst;
2188
 
2189
parameter addr_width = 4;
2190
 
2191
// bte
2192
parameter linear       = 2'b00;
2193
parameter wrap4        = 2'b01;
2194
parameter wrap8        = 2'b10;
2195
parameter wrap16       = 2'b11;
2196
// cti
2197
parameter classic      = 3'b000;
2198
parameter incburst     = 3'b010;
2199
parameter endofburst   = 3'b111;
2200
 
2201
parameter wbs_adr  = 1'b0;
2202
parameter wbs_data = 1'b1;
2203
 
2204
parameter wbm_adr0 = 2'b00;
2205
parameter wbm_adr1 = 2'b01;
2206
parameter wbm_data = 2'b10;
2207
 
2208
reg [1:0] wbs_bte_reg;
2209
reg wbs;
2210
wire wbs_eoc_alert, wbm_eoc_alert;
2211
reg wbs_eoc, wbm_eoc;
2212
reg [1:0] wbm;
2213
 
2214 14 unneback
wire [1:16] wbs_count, wbm_count;
2215 12 unneback
 
2216
wire [35:0] a_d, a_q, b_d, b_q;
2217
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2218
reg a_rd_reg;
2219
wire b_rd_adr, b_rd_data;
2220 14 unneback
wire b_rd_data_reg;
2221
wire [35:0] temp;
2222 12 unneback
 
2223
`define WE 5
2224
`define BTE 4:3
2225
`define CTI 2:0
2226
 
2227
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2228
always @ (posedge wbs_clk or posedge wbs_rst)
2229
if (wbs_rst)
2230
        wbs_eoc <= 1'b0;
2231
else
2232
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2233
                wbs_eoc <= wbs_bte_i==linear;
2234
        else if (wbs_eoc_alert & (a_rd | a_wr))
2235
                wbs_eoc <= 1'b1;
2236
 
2237
cnt_shreg_ce_clear # ( .length(16))
2238
    cnt0 (
2239
        .cke(wbs_ack_o),
2240
        .clear(wbs_eoc),
2241
        .q(wbs_count),
2242
        .rst(wbs_rst),
2243
        .clk(wbs_clk));
2244
 
2245
always @ (posedge wbs_clk or posedge wbs_rst)
2246
if (wbs_rst)
2247
        wbs <= wbs_adr;
2248
else
2249
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
2250
                wbs <= wbs_data;
2251
        else if (wbs_eoc & wbs_ack_o)
2252
                wbs <= wbs_adr;
2253
 
2254
// wbs FIFO
2255
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
2256
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
2257
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2258
              1'b0;
2259
assign a_rd = !a_fifo_empty;
2260
always @ (posedge wbs_clk or posedge wbs_rst)
2261
if (wbs_rst)
2262
        a_rd_reg <= 1'b0;
2263
else
2264
        a_rd_reg <= a_rd;
2265
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2266
 
2267
assign wbs_dat_o = a_q[35:4];
2268
 
2269
always @ (posedge wbs_clk or posedge wbs_rst)
2270
if (wbs_rst)
2271 13 unneback
        wbs_bte_reg <= 2'b00;
2272 12 unneback
else
2273 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2274 12 unneback
 
2275
// wbm FIFO
2276
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2277
always @ (posedge wbm_clk or posedge wbm_rst)
2278
if (wbm_rst)
2279
        wbm_eoc <= 1'b0;
2280
else
2281
        if (wbm==wbm_adr0 & !b_fifo_empty)
2282
                wbm_eoc <= b_q[`BTE] == linear;
2283
        else if (wbm_eoc_alert & wbm_ack_i)
2284
                wbm_eoc <= 1'b1;
2285
 
2286
always @ (posedge wbm_clk or posedge wbm_rst)
2287
if (wbm_rst)
2288
        wbm <= wbm_adr0;
2289
else
2290
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2291
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2292
        (wbm==wbm_adr1 & !wbm_we_o) |
2293
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2294
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2295
 
2296
assign b_d = {wbm_dat_i,4'b1111};
2297
assign b_wr = !wbm_we_o & wbm_ack_i;
2298
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2299
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2300
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2301
                   1'b0;
2302
assign b_rd = b_rd_adr | b_rd_data;
2303
 
2304
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2305
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2306
 
2307
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2308
 
2309
cnt_shreg_ce_clear # ( .length(16))
2310
    cnt1 (
2311
        .cke(wbm_ack_i),
2312
        .clear(wbm_eoc),
2313
        .q(wbm_count),
2314
        .rst(wbm_rst),
2315
        .clk(wbm_clk));
2316
 
2317
assign wbm_cyc_o = wbm==wbm_data;
2318
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
2319
                   (wbm==wbm_data) ? 1'b1 :
2320
                   1'b0;
2321
 
2322
always @ (posedge wbm_clk or posedge wbm_rst)
2323
if (wbm_rst)
2324
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2325
else begin
2326
        if (wbm==wbm_adr0 & !b_fifo_empty)
2327
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2328
        else if (wbm_eoc_alert & wbm_ack_i)
2329
                wbm_cti_o <= endofburst;
2330
end
2331
 
2332
//async_fifo_dw_simplex_top
2333
vl_fifo_2r2w_async_simplex
2334
# ( .data_width(36), .addr_width(addr_width))
2335
fifo (
2336
    // a side
2337
    .a_d(a_d),
2338
    .a_wr(a_wr),
2339
    .a_fifo_full(a_fifo_full),
2340
    .a_q(a_q),
2341
    .a_rd(a_rd),
2342
    .a_fifo_empty(a_fifo_empty),
2343
    .a_clk(wbs_clk),
2344
    .a_rst(wbs_rst),
2345
    // b side
2346
    .b_d(b_d),
2347
    .b_wr(b_wr),
2348
    .b_fifo_full(b_fifo_full),
2349
    .b_q(b_q),
2350
    .b_rd(b_rd),
2351
    .b_fifo_empty(b_fifo_empty),
2352
    .b_clk(wbm_clk),
2353
    .b_rst(wbm_rst)
2354
    );
2355
 
2356
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.