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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
66
`ifdef SIM_GBUF
67
assign o=i;
68
`else
69
gbuf gbuf_i0 ( .CLK(i), .GL(o));
70
`endif
71
endmodule
72
`else
73
`ifdef ALTERA
74 21 unneback
//altera
75 6 unneback
`else
76
 
77
`timescale 1 ns/100 ps
78
module vl_gbuf ( i, o);
79
input i;
80
output o;
81
assign o = i;
82
endmodule
83
`endif // ALTERA
84
`endif //ACTEL
85
 
86
// sync reset
87 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
88 6 unneback
// output active high global reset sync with two DFFs 
89
`timescale 1 ns/100 ps
90
module vl_sync_rst ( rst_n_i, rst_o, clk);
91
input rst_n_i, clk;
92
output rst_o;
93 18 unneback
reg [1:0] tmp;
94 6 unneback
always @ (posedge clk or negedge rst_n_i)
95
if (!rst_n_i)
96 17 unneback
        tmp <= 2'b11;
97 6 unneback
else
98 17 unneback
        tmp <= {1'b0,tmp[0]};
99
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
100 6 unneback
endmodule
101
 
102
// vl_pll
103
`ifdef ACTEL
104 17 unneback
`timescale 1 ps/1 ps
105 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
106
parameter index = 0;
107
parameter number_of_clk = 1;
108 17 unneback
parameter period_time_0 = 20000;
109
parameter period_time_1 = 20000;
110
parameter period_time_2 = 20000;
111
parameter lock_delay = 2000000;
112 6 unneback
input clk_i, rst_n_i;
113
output lock;
114
output reg [0:number_of_clk-1] clk_o;
115
output [0:number_of_clk-1] rst_o;
116
 
117
`ifdef SIM_PLL
118
 
119
always
120
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
121
 
122
generate if (number_of_clk > 1)
123
always
124
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
125
endgenerate
126
 
127
generate if (number_of_clk > 2)
128
always
129
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
130
endgenerate
131
 
132
genvar i;
133
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
134
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
135
end
136
endgenerate
137
 
138
assign #lock_delay lock = rst_n_i;
139
 
140
endmodule
141
`else
142
generate if (number_of_clk==1 & index==0) begin
143
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==1 & index==1) begin
147
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
148
end
149
endgenerate // index==1
150
generate if (number_of_clk==1 & index==2) begin
151
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
152
end
153
endgenerate // index==2
154
generate if (number_of_clk==1 & index==3) begin
155
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
156
end
157
endgenerate // index==0
158
 
159
generate if (number_of_clk==2 & index==0) begin
160
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
161
end
162
endgenerate // index==0
163
generate if (number_of_clk==2 & index==1) begin
164
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
165
end
166
endgenerate // index==1
167
generate if (number_of_clk==2 & index==2) begin
168
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
169
end
170
endgenerate // index==2
171
generate if (number_of_clk==2 & index==3) begin
172
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
173
end
174
endgenerate // index==0
175
 
176
generate if (number_of_clk==3 & index==0) begin
177
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
178
end
179
endgenerate // index==0
180
generate if (number_of_clk==3 & index==1) begin
181
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
182
end
183
endgenerate // index==1
184
generate if (number_of_clk==3 & index==2) begin
185
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
186
end
187
endgenerate // index==2
188
generate if (number_of_clk==3 & index==3) begin
189
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
190
end
191
endgenerate // index==0
192
 
193
genvar i;
194
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
195
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
196
end
197
endgenerate
198
endmodule
199
`endif
200
 
201
`else
202
 
203
`ifdef ALTERA
204
 
205
`else
206
 
207
// generic PLL
208 17 unneback
`timescale 1 ps/1 ps
209 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
210
parameter index = 0;
211
parameter number_of_clk = 1;
212 17 unneback
parameter period_time_0 = 20000;
213
parameter period_time_1 = 20000;
214
parameter period_time_2 = 20000;
215 6 unneback
parameter lock_delay = 2000;
216
input clk_i, rst_n_i;
217
output lock;
218
output reg [0:number_of_clk-1] clk_o;
219
output [0:number_of_clk-1] rst_o;
220
 
221
always
222
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
223
 
224
generate if (number_of_clk > 1)
225
always
226
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
227
endgenerate
228
 
229
generate if (number_of_clk > 2)
230
always
231
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
232
endgenerate
233
 
234
genvar i;
235
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
236
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
237
end
238
endgenerate
239
 
240
assign #lock_delay lock = rst_n_i;
241
 
242
endmodule
243
 
244
`endif //altera
245 17 unneback
`endif //actel
246
//////////////////////////////////////////////////////////////////////
247 6 unneback
////                                                              ////
248
////  Versatile library, registers                                ////
249
////                                                              ////
250
////  Description                                                 ////
251
////  Different type of registers                                 ////
252
////                                                              ////
253
////                                                              ////
254
////  To Do:                                                      ////
255
////   - add more different registers                             ////
256
////                                                              ////
257
////  Author(s):                                                  ////
258
////      - Michael Unneback, unneback@opencores.org              ////
259
////        ORSoC AB                                              ////
260
////                                                              ////
261
//////////////////////////////////////////////////////////////////////
262
////                                                              ////
263
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
264
////                                                              ////
265
//// This source file may be used and distributed without         ////
266
//// restriction provided that this copyright statement is not    ////
267
//// removed from the file and that any derivative work contains  ////
268
//// the original copyright notice and the associated disclaimer. ////
269
////                                                              ////
270
//// This source file is free software; you can redistribute it   ////
271
//// and/or modify it under the terms of the GNU Lesser General   ////
272
//// Public License as published by the Free Software Foundation; ////
273
//// either version 2.1 of the License, or (at your option) any   ////
274
//// later version.                                               ////
275
////                                                              ////
276
//// This source is distributed in the hope that it will be       ////
277
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
278
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
279
//// PURPOSE.  See the GNU Lesser General Public License for more ////
280
//// details.                                                     ////
281
////                                                              ////
282
//// You should have received a copy of the GNU Lesser General    ////
283
//// Public License along with this source; if not, download it   ////
284
//// from http://www.opencores.org/lgpl.shtml                     ////
285
////                                                              ////
286
//////////////////////////////////////////////////////////////////////
287
 
288 18 unneback
module vl_dff ( d, q, clk, rst);
289 6 unneback
 
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
 
293
        input [width-1:0] d;
294
        input clk, rst;
295
        output reg [width-1:0] q;
296
 
297
        always @ (posedge clk or posedge rst)
298
        if (rst)
299
                q <= reset_value;
300
        else
301
                q <= d;
302
 
303
endmodule
304
 
305 18 unneback
module vl_dff_array ( d, q, clk, rst);
306 6 unneback
 
307
        parameter width = 1;
308
        parameter depth = 2;
309
        parameter reset_value = 1'b0;
310
 
311
        input [width-1:0] d;
312
        input clk, rst;
313
        output [width-1:0] q;
314
        reg  [0:depth-1] q_tmp [width-1:0];
315
        integer i;
316
        always @ (posedge clk or posedge rst)
317
        if (rst) begin
318
            for (i=0;i<depth;i=i+1)
319
                q_tmp[i] <= {width{reset_value}};
320
        end else begin
321
            q_tmp[0] <= d;
322
            for (i=1;i<depth;i=i+1)
323
                q_tmp[i] <= q_tmp[i-1];
324
        end
325
 
326
    assign q = q_tmp[depth-1];
327
 
328
endmodule
329
 
330 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
331 6 unneback
 
332
        parameter width = 1;
333
        parameter reset_value = 0;
334
 
335
        input [width-1:0] d;
336
        input ce, clk, rst;
337
        output reg [width-1:0] q;
338
 
339
        always @ (posedge clk or posedge rst)
340
        if (rst)
341
                q <= reset_value;
342
        else
343
                if (ce)
344
                        q <= d;
345
 
346
endmodule
347
 
348 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
349 8 unneback
 
350
        parameter width = 1;
351
        parameter reset_value = 0;
352
 
353
        input [width-1:0] d;
354 10 unneback
        input ce, clear, clk, rst;
355 8 unneback
        output reg [width-1:0] q;
356
 
357
        always @ (posedge clk or posedge rst)
358
        if (rst)
359
            q <= reset_value;
360
        else
361
            if (ce)
362
                if (clear)
363
                    q <= {width{1'b0}};
364
                else
365
                    q <= d;
366
 
367
endmodule
368
 
369 6 unneback
`ifdef ALTERA
370
// megafunction wizard: %LPM_FF%
371
// GENERATION: STANDARD
372
// VERSION: WM1.0
373
// MODULE: lpm_ff 
374
 
375
// ============================================================
376
// File Name: dff_sr.v
377
// Megafunction Name(s):
378
//                      lpm_ff
379
//
380
// Simulation Library Files(s):
381
//                      lpm
382
// ============================================================
383
// ************************************************************
384
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
385
//
386
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
387
// ************************************************************
388
 
389
 
390
//Copyright (C) 1991-2010 Altera Corporation
391
//Your use of Altera Corporation's design tools, logic functions 
392
//and other software and tools, and its AMPP partner logic 
393
//functions, and any output files from any of the foregoing 
394
//(including device programming or simulation files), and any 
395
//associated documentation or information are expressly subject 
396
//to the terms and conditions of the Altera Program License 
397
//Subscription Agreement, Altera MegaCore Function License 
398
//Agreement, or other applicable license agreement, including, 
399
//without limitation, that your use is for the sole purpose of 
400
//programming logic devices manufactured by Altera and sold by 
401
//Altera or its authorized distributors.  Please refer to the 
402
//applicable agreement for further details.
403
 
404
 
405
// synopsys translate_off
406
`timescale 1 ps / 1 ps
407
// synopsys translate_on
408 18 unneback
module vl_dff_sr (
409 6 unneback
        aclr,
410
        aset,
411
        clock,
412
        data,
413
        q);
414
 
415
        input     aclr;
416
        input     aset;
417
        input     clock;
418
        input     data;
419
        output    q;
420
 
421
        wire [0:0] sub_wire0;
422
        wire [0:0] sub_wire1 = sub_wire0[0:0];
423
        wire  q = sub_wire1;
424
        wire  sub_wire2 = data;
425
        wire  sub_wire3 = sub_wire2;
426
 
427
        lpm_ff  lpm_ff_component (
428
                                .aclr (aclr),
429
                                .clock (clock),
430
                                .data (sub_wire3),
431
                                .aset (aset),
432
                                .q (sub_wire0)
433
                                // synopsys translate_off
434
                                ,
435
                                .aload (),
436
                                .enable (),
437
                                .sclr (),
438
                                .sload (),
439
                                .sset ()
440
                                // synopsys translate_on
441
                                );
442
        defparam
443
                lpm_ff_component.lpm_fftype = "DFF",
444
                lpm_ff_component.lpm_type = "LPM_FF",
445
                lpm_ff_component.lpm_width = 1;
446
 
447
 
448
endmodule
449
 
450
// ============================================================
451
// CNX file retrieval info
452
// ============================================================
453
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
454
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
455
// Retrieval info: PRIVATE: ASET NUMERIC "1"
456
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
457
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
458
// Retrieval info: PRIVATE: DFF NUMERIC "1"
459
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
460
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
461
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
462
// Retrieval info: PRIVATE: SSET NUMERIC "0"
463
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
464
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
465
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
466
// Retrieval info: PRIVATE: nBit NUMERIC "1"
467
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
468
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
469
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
470
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
471
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
472
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
473
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
474
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
475
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
476
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
477
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
478
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
479
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
480
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
481
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
482
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
483
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
484
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
485
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
486
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
487
// Retrieval info: LIB_FILE: lpm
488
 
489
 
490
`else
491
 
492
 
493 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
494 6 unneback
 
495
    input         aclr;
496
    input         aset;
497
    input         clock;
498
    input         data;
499
    output reg    q;
500
 
501
   always @ (posedge clock or posedge aclr or posedge aset)
502
     if (aclr)
503
       q <= 1'b0;
504
     else if (aset)
505
       q <= 1'b1;
506
     else
507
       q <= data;
508
 
509
endmodule
510
 
511
`endif
512
 
513
// LATCH
514
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
515
`ifdef ALTERA
516 18 unneback
module vl_latch ( d, le, q, clk);
517 6 unneback
input d, le;
518
output q;
519
input clk;
520
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
521
endmodule
522
`else
523
module latch ( d, le, q, clk);
524
input d, le;
525
output q;
526
input clk;/*
527
   always @ (posedge direction_set or posedge direction_clr)
528
     if (direction_clr)
529
       direction <= going_empty;
530
     else
531
       direction <= going_full;*/
532
endmodule
533 15 unneback
`endif
534
 
535 18 unneback
module vl_shreg ( d, q, clk, rst);
536 17 unneback
parameter depth = 10;
537
input d;
538
output q;
539
input clk, rst;
540
 
541
reg [1:depth] dffs;
542
 
543
always @ (posedge clk or posedge rst)
544
if (rst)
545
    dffs <= {depth{1'b0}};
546
else
547
    dffs <= {d,dffs[1:depth-1]};
548
assign q = dffs[depth];
549
endmodule
550
 
551 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
552 17 unneback
parameter depth = 10;
553
input d, ce;
554
output q;
555
input clk, rst;
556
 
557
reg [1:depth] dffs;
558
 
559
always @ (posedge clk or posedge rst)
560
if (rst)
561
    dffs <= {depth{1'b0}};
562
else
563
    if (ce)
564
        dffs <= {d,dffs[1:depth-1]};
565
assign q = dffs[depth];
566
endmodule
567
 
568 18 unneback
module vl_delay ( d, q, clk, rst);
569 15 unneback
parameter depth = 10;
570
input d;
571
output q;
572
input clk, rst;
573
 
574
reg [1:depth] dffs;
575
 
576
always @ (posedge clk or posedge rst)
577
if (rst)
578
    dffs <= {depth{1'b0}};
579
else
580
    dffs <= {d,dffs[1:depth-1]};
581
assign q = dffs[depth];
582 17 unneback
endmodule
583
 
584 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
585 17 unneback
parameter depth = 10;
586
input d;
587
output q, emptyflag;
588
input clk, rst;
589
 
590
reg [1:depth] dffs;
591
 
592
always @ (posedge clk or posedge rst)
593
if (rst)
594
    dffs <= {depth{1'b0}};
595
else
596
    dffs <= {d,dffs[1:depth-1]};
597
assign q = dffs[depth];
598
assign emptyflag = !(|dffs);
599
endmodule
600
//////////////////////////////////////////////////////////////////////
601 6 unneback
////                                                              ////
602 18 unneback
////  Logic functions                                             ////
603
////                                                              ////
604
////  Description                                                 ////
605
////  Logic functions such as multiplexers                        ////
606
////                                                              ////
607
////                                                              ////
608
////  To Do:                                                      ////
609
////   -                                                          ////
610
////                                                              ////
611
////  Author(s):                                                  ////
612
////      - Michael Unneback, unneback@opencores.org              ////
613
////        ORSoC AB                                              ////
614
////                                                              ////
615
//////////////////////////////////////////////////////////////////////
616
////                                                              ////
617
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
618
////                                                              ////
619
//// This source file may be used and distributed without         ////
620
//// restriction provided that this copyright statement is not    ////
621
//// removed from the file and that any derivative work contains  ////
622
//// the original copyright notice and the associated disclaimer. ////
623
////                                                              ////
624
//// This source file is free software; you can redistribute it   ////
625
//// and/or modify it under the terms of the GNU Lesser General   ////
626
//// Public License as published by the Free Software Foundation; ////
627
//// either version 2.1 of the License, or (at your option) any   ////
628
//// later version.                                               ////
629
////                                                              ////
630
//// This source is distributed in the hope that it will be       ////
631
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
632
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
633
//// PURPOSE.  See the GNU Lesser General Public License for more ////
634
//// details.                                                     ////
635
////                                                              ////
636
//// You should have received a copy of the GNU Lesser General    ////
637
//// Public License along with this source; if not, download it   ////
638
//// from http://www.opencores.org/lgpl.shtml                     ////
639
////                                                              ////
640
//////////////////////////////////////////////////////////////////////
641
 
642
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
643
 
644
parameter width = 32;
645
parameter nr_of_ports = 4;
646
input [width-1:0] a3, a2, a1, a0;
647
input [nr_of_ports-1:0] sel;
648
output reg [width-1:0] dout;
649
 
650 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
651 18 unneback
integer i;
652
 
653
// and
654
assign tmp[0] = {width{sel[0]}} & a0;
655
assign tmp[1] = {width{sel[1]}} & a1;
656
assign tmp[2] = {width{sel[2]}} & a2;
657
assign tmp[3] = {width{sel[3]}} & a3;
658
 
659
// or
660
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
661
 
662
endmodule
663
 
664
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
665
 
666
parameter width = 32;
667
parameter nr_of_ports = 5;
668
input [width-1:0] a4, a3, a2, a1, a0;
669
input [nr_of_ports-1:0] sel;
670
output reg [width-1:0] dout;
671
 
672 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
673 18 unneback
integer i;
674
 
675
// and
676
assign tmp[0] = {width{sel[0]}} & a0;
677
assign tmp[1] = {width{sel[1]}} & a1;
678
assign tmp[2] = {width{sel[2]}} & a2;
679
assign tmp[3] = {width{sel[3]}} & a3;
680
assign tmp[4] = {width{sel[4]}} & a4;
681
 
682
// or
683
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
684
 
685
endmodule
686
 
687
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
688
 
689
parameter width = 32;
690
parameter nr_of_ports = 6;
691
input [width-1:0] a5, a4, a3, a2, a1, a0;
692
input [nr_of_ports-1:0] sel;
693
output reg [width-1:0] dout;
694
 
695 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
696 18 unneback
integer i;
697
 
698
// and
699
assign tmp[0] = {width{sel[0]}} & a0;
700
assign tmp[1] = {width{sel[1]}} & a1;
701
assign tmp[2] = {width{sel[2]}} & a2;
702
assign tmp[3] = {width{sel[3]}} & a3;
703
assign tmp[4] = {width{sel[4]}} & a4;
704
assign tmp[5] = {width{sel[5]}} & a5;
705
 
706
// or
707
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
708
 
709
endmodule
710
//////////////////////////////////////////////////////////////////////
711
////                                                              ////
712 6 unneback
////  Versatile counter                                           ////
713
////                                                              ////
714
////  Description                                                 ////
715
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
716
////  counter                                                     ////
717
////                                                              ////
718
////  To Do:                                                      ////
719
////   - add LFSR with more taps                                  ////
720
////                                                              ////
721
////  Author(s):                                                  ////
722
////      - Michael Unneback, unneback@opencores.org              ////
723
////        ORSoC AB                                              ////
724
////                                                              ////
725
//////////////////////////////////////////////////////////////////////
726
////                                                              ////
727
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
728
////                                                              ////
729
//// This source file may be used and distributed without         ////
730
//// restriction provided that this copyright statement is not    ////
731
//// removed from the file and that any derivative work contains  ////
732
//// the original copyright notice and the associated disclaimer. ////
733
////                                                              ////
734
//// This source file is free software; you can redistribute it   ////
735
//// and/or modify it under the terms of the GNU Lesser General   ////
736
//// Public License as published by the Free Software Foundation; ////
737
//// either version 2.1 of the License, or (at your option) any   ////
738
//// later version.                                               ////
739
////                                                              ////
740
//// This source is distributed in the hope that it will be       ////
741
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
742
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
743
//// PURPOSE.  See the GNU Lesser General Public License for more ////
744
//// details.                                                     ////
745
////                                                              ////
746
//// You should have received a copy of the GNU Lesser General    ////
747
//// Public License along with this source; if not, download it   ////
748
//// from http://www.opencores.org/lgpl.shtml                     ////
749
////                                                              ////
750
//////////////////////////////////////////////////////////////////////
751
 
752
// binary counter
753 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
754 6 unneback
 
755
   parameter length = 4;
756
   input cke;
757
   output [length:1] q;
758
   input rst;
759
   input clk;
760
 
761
   parameter clear_value = 0;
762
   parameter set_value = 1;
763
   parameter wrap_value = 0;
764
   parameter level1_value = 15;
765
 
766
   reg  [length:1] qi;
767
   wire [length:1] q_next;
768
   assign q_next = qi + {{length-1{1'b0}},1'b1};
769
 
770
   always @ (posedge clk or posedge rst)
771
     if (rst)
772
       qi <= {length{1'b0}};
773
     else
774
     if (cke)
775
       qi <= q_next;
776
 
777
   assign q = qi;
778
 
779
endmodule
780
//////////////////////////////////////////////////////////////////////
781
////                                                              ////
782
////  Versatile counter                                           ////
783
////                                                              ////
784
////  Description                                                 ////
785
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
786
////  counter                                                     ////
787
////                                                              ////
788
////  To Do:                                                      ////
789
////   - add LFSR with more taps                                  ////
790
////                                                              ////
791
////  Author(s):                                                  ////
792
////      - Michael Unneback, unneback@opencores.org              ////
793
////        ORSoC AB                                              ////
794
////                                                              ////
795
//////////////////////////////////////////////////////////////////////
796
////                                                              ////
797
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
798
////                                                              ////
799
//// This source file may be used and distributed without         ////
800
//// restriction provided that this copyright statement is not    ////
801
//// removed from the file and that any derivative work contains  ////
802
//// the original copyright notice and the associated disclaimer. ////
803
////                                                              ////
804
//// This source file is free software; you can redistribute it   ////
805
//// and/or modify it under the terms of the GNU Lesser General   ////
806
//// Public License as published by the Free Software Foundation; ////
807
//// either version 2.1 of the License, or (at your option) any   ////
808
//// later version.                                               ////
809
////                                                              ////
810
//// This source is distributed in the hope that it will be       ////
811
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
812
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
813
//// PURPOSE.  See the GNU Lesser General Public License for more ////
814
//// details.                                                     ////
815
////                                                              ////
816
//// You should have received a copy of the GNU Lesser General    ////
817
//// Public License along with this source; if not, download it   ////
818
//// from http://www.opencores.org/lgpl.shtml                     ////
819
////                                                              ////
820
//////////////////////////////////////////////////////////////////////
821
 
822
// binary counter
823 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
824 6 unneback
 
825
   parameter length = 4;
826
   input clear;
827
   input cke;
828
   output [length:1] q;
829
   input rst;
830
   input clk;
831
 
832
   parameter clear_value = 0;
833
   parameter set_value = 1;
834
   parameter wrap_value = 0;
835
   parameter level1_value = 15;
836
 
837
   reg  [length:1] qi;
838
   wire [length:1] q_next;
839
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
840
 
841
   always @ (posedge clk or posedge rst)
842
     if (rst)
843
       qi <= {length{1'b0}};
844
     else
845
     if (cke)
846
       qi <= q_next;
847
 
848
   assign q = qi;
849
 
850
endmodule
851
//////////////////////////////////////////////////////////////////////
852
////                                                              ////
853
////  Versatile counter                                           ////
854
////                                                              ////
855
////  Description                                                 ////
856
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
857
////  counter                                                     ////
858
////                                                              ////
859
////  To Do:                                                      ////
860
////   - add LFSR with more taps                                  ////
861
////                                                              ////
862
////  Author(s):                                                  ////
863
////      - Michael Unneback, unneback@opencores.org              ////
864
////        ORSoC AB                                              ////
865
////                                                              ////
866
//////////////////////////////////////////////////////////////////////
867
////                                                              ////
868
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
869
////                                                              ////
870
//// This source file may be used and distributed without         ////
871
//// restriction provided that this copyright statement is not    ////
872
//// removed from the file and that any derivative work contains  ////
873
//// the original copyright notice and the associated disclaimer. ////
874
////                                                              ////
875
//// This source file is free software; you can redistribute it   ////
876
//// and/or modify it under the terms of the GNU Lesser General   ////
877
//// Public License as published by the Free Software Foundation; ////
878
//// either version 2.1 of the License, or (at your option) any   ////
879
//// later version.                                               ////
880
////                                                              ////
881
//// This source is distributed in the hope that it will be       ////
882
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
883
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
884
//// PURPOSE.  See the GNU Lesser General Public License for more ////
885
//// details.                                                     ////
886
////                                                              ////
887
//// You should have received a copy of the GNU Lesser General    ////
888
//// Public License along with this source; if not, download it   ////
889
//// from http://www.opencores.org/lgpl.shtml                     ////
890
////                                                              ////
891
//////////////////////////////////////////////////////////////////////
892
 
893
// binary counter
894 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
895 6 unneback
 
896
   parameter length = 4;
897
   input clear;
898
   input set;
899
   input cke;
900
   input rew;
901
   output [length:1] q;
902
   input rst;
903
   input clk;
904
 
905
   parameter clear_value = 0;
906
   parameter set_value = 1;
907
   parameter wrap_value = 0;
908
   parameter level1_value = 15;
909
 
910
   reg  [length:1] qi;
911
   wire  [length:1] q_next, q_next_fw, q_next_rew;
912
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
913
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
914
   assign q_next = rew ? q_next_rew : q_next_fw;
915
 
916
   always @ (posedge clk or posedge rst)
917
     if (rst)
918
       qi <= {length{1'b0}};
919
     else
920
     if (cke)
921
       qi <= q_next;
922
 
923
   assign q = qi;
924
 
925
endmodule
926
//////////////////////////////////////////////////////////////////////
927
////                                                              ////
928
////  Versatile counter                                           ////
929
////                                                              ////
930
////  Description                                                 ////
931
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
932
////  counter                                                     ////
933
////                                                              ////
934
////  To Do:                                                      ////
935
////   - add LFSR with more taps                                  ////
936
////                                                              ////
937
////  Author(s):                                                  ////
938
////      - Michael Unneback, unneback@opencores.org              ////
939
////        ORSoC AB                                              ////
940
////                                                              ////
941
//////////////////////////////////////////////////////////////////////
942
////                                                              ////
943
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
944
////                                                              ////
945
//// This source file may be used and distributed without         ////
946
//// restriction provided that this copyright statement is not    ////
947
//// removed from the file and that any derivative work contains  ////
948
//// the original copyright notice and the associated disclaimer. ////
949
////                                                              ////
950
//// This source file is free software; you can redistribute it   ////
951
//// and/or modify it under the terms of the GNU Lesser General   ////
952
//// Public License as published by the Free Software Foundation; ////
953
//// either version 2.1 of the License, or (at your option) any   ////
954
//// later version.                                               ////
955
////                                                              ////
956
//// This source is distributed in the hope that it will be       ////
957
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
958
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
959
//// PURPOSE.  See the GNU Lesser General Public License for more ////
960
//// details.                                                     ////
961
////                                                              ////
962
//// You should have received a copy of the GNU Lesser General    ////
963
//// Public License along with this source; if not, download it   ////
964
//// from http://www.opencores.org/lgpl.shtml                     ////
965
////                                                              ////
966
//////////////////////////////////////////////////////////////////////
967
 
968
// binary counter
969 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
970 6 unneback
 
971
   parameter length = 4;
972
   input cke;
973
   input rew;
974
   output reg level1;
975
   input rst;
976
   input clk;
977
 
978
   parameter clear_value = 0;
979
   parameter set_value = 1;
980
   parameter wrap_value = 1;
981
   parameter level1_value = 15;
982
 
983
   reg  [length:1] qi;
984
   wire  [length:1] q_next, q_next_fw, q_next_rew;
985
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
986
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
987
   assign q_next = rew ? q_next_rew : q_next_fw;
988
 
989
   always @ (posedge clk or posedge rst)
990
     if (rst)
991
       qi <= {length{1'b0}};
992
     else
993
     if (cke)
994
       qi <= q_next;
995
 
996
 
997
 
998
    always @ (posedge clk or posedge rst)
999
    if (rst)
1000
        level1 <= 1'b0;
1001
    else
1002
    if (cke)
1003
    if (q_next == level1_value)
1004
        level1 <= 1'b1;
1005
    else if (qi == level1_value & rew)
1006
        level1 <= 1'b0;
1007
endmodule
1008
//////////////////////////////////////////////////////////////////////
1009
////                                                              ////
1010
////  Versatile counter                                           ////
1011
////                                                              ////
1012
////  Description                                                 ////
1013
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1014
////  counter                                                     ////
1015
////                                                              ////
1016
////  To Do:                                                      ////
1017
////   - add LFSR with more taps                                  ////
1018
////                                                              ////
1019
////  Author(s):                                                  ////
1020
////      - Michael Unneback, unneback@opencores.org              ////
1021
////        ORSoC AB                                              ////
1022
////                                                              ////
1023
//////////////////////////////////////////////////////////////////////
1024
////                                                              ////
1025
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1026
////                                                              ////
1027
//// This source file may be used and distributed without         ////
1028
//// restriction provided that this copyright statement is not    ////
1029
//// removed from the file and that any derivative work contains  ////
1030
//// the original copyright notice and the associated disclaimer. ////
1031
////                                                              ////
1032
//// This source file is free software; you can redistribute it   ////
1033
//// and/or modify it under the terms of the GNU Lesser General   ////
1034
//// Public License as published by the Free Software Foundation; ////
1035
//// either version 2.1 of the License, or (at your option) any   ////
1036
//// later version.                                               ////
1037
////                                                              ////
1038
//// This source is distributed in the hope that it will be       ////
1039
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1040
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1041
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1042
//// details.                                                     ////
1043
////                                                              ////
1044
//// You should have received a copy of the GNU Lesser General    ////
1045
//// Public License along with this source; if not, download it   ////
1046
//// from http://www.opencores.org/lgpl.shtml                     ////
1047
////                                                              ////
1048
//////////////////////////////////////////////////////////////////////
1049
 
1050
// LFSR counter
1051 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1052 6 unneback
 
1053
   parameter length = 4;
1054
   output reg zq;
1055
   input rst;
1056
   input clk;
1057
 
1058
   parameter clear_value = 0;
1059
   parameter set_value = 1;
1060
   parameter wrap_value = 8;
1061
   parameter level1_value = 15;
1062
 
1063
   reg  [length:1] qi;
1064
   reg lfsr_fb;
1065
   wire [length:1] q_next;
1066
   reg [32:1] polynom;
1067
   integer i;
1068
 
1069
   always @ (qi)
1070
   begin
1071
        case (length)
1072
         2: polynom = 32'b11;                               // 0x3
1073
         3: polynom = 32'b110;                              // 0x6
1074
         4: polynom = 32'b1100;                             // 0xC
1075
         5: polynom = 32'b10100;                            // 0x14
1076
         6: polynom = 32'b110000;                           // 0x30
1077
         7: polynom = 32'b1100000;                          // 0x60
1078
         8: polynom = 32'b10111000;                         // 0xb8
1079
         9: polynom = 32'b100010000;                        // 0x110
1080
        10: polynom = 32'b1001000000;                       // 0x240
1081
        11: polynom = 32'b10100000000;                      // 0x500
1082
        12: polynom = 32'b100000101001;                     // 0x829
1083
        13: polynom = 32'b1000000001100;                    // 0x100C
1084
        14: polynom = 32'b10000000010101;                   // 0x2015
1085
        15: polynom = 32'b110000000000000;                  // 0x6000
1086
        16: polynom = 32'b1101000000001000;                 // 0xD008
1087
        17: polynom = 32'b10010000000000000;                // 0x12000
1088
        18: polynom = 32'b100000010000000000;               // 0x20400
1089
        19: polynom = 32'b1000000000000100011;              // 0x40023
1090
        20: polynom = 32'b10000010000000000000;             // 0x82000
1091
        21: polynom = 32'b101000000000000000000;            // 0x140000
1092
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1093
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1094
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1095
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1096
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1097
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1098
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1099
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1100
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1101
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1102
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1103
        default: polynom = 32'b0;
1104
        endcase
1105
        lfsr_fb = qi[length];
1106
        for (i=length-1; i>=1; i=i-1) begin
1107
            if (polynom[i])
1108
                lfsr_fb = lfsr_fb  ~^ qi[i];
1109
        end
1110
    end
1111
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1112
 
1113
   always @ (posedge clk or posedge rst)
1114
     if (rst)
1115
       qi <= {length{1'b0}};
1116
     else
1117
       qi <= q_next;
1118
 
1119
 
1120
 
1121
   always @ (posedge clk or posedge rst)
1122
     if (rst)
1123
       zq <= 1'b1;
1124
     else
1125
       zq <= q_next == {length{1'b0}};
1126
endmodule
1127
//////////////////////////////////////////////////////////////////////
1128
////                                                              ////
1129
////  Versatile counter                                           ////
1130
////                                                              ////
1131
////  Description                                                 ////
1132
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1133
////  counter                                                     ////
1134
////                                                              ////
1135
////  To Do:                                                      ////
1136
////   - add LFSR with more taps                                  ////
1137
////                                                              ////
1138
////  Author(s):                                                  ////
1139
////      - Michael Unneback, unneback@opencores.org              ////
1140
////        ORSoC AB                                              ////
1141
////                                                              ////
1142
//////////////////////////////////////////////////////////////////////
1143
////                                                              ////
1144
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1145
////                                                              ////
1146
//// This source file may be used and distributed without         ////
1147
//// restriction provided that this copyright statement is not    ////
1148
//// removed from the file and that any derivative work contains  ////
1149
//// the original copyright notice and the associated disclaimer. ////
1150
////                                                              ////
1151
//// This source file is free software; you can redistribute it   ////
1152
//// and/or modify it under the terms of the GNU Lesser General   ////
1153
//// Public License as published by the Free Software Foundation; ////
1154
//// either version 2.1 of the License, or (at your option) any   ////
1155
//// later version.                                               ////
1156
////                                                              ////
1157
//// This source is distributed in the hope that it will be       ////
1158
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1159
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1160
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1161
//// details.                                                     ////
1162
////                                                              ////
1163
//// You should have received a copy of the GNU Lesser General    ////
1164
//// Public License along with this source; if not, download it   ////
1165
//// from http://www.opencores.org/lgpl.shtml                     ////
1166
////                                                              ////
1167
//////////////////////////////////////////////////////////////////////
1168
 
1169
// LFSR counter
1170 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1171 6 unneback
 
1172
   parameter length = 4;
1173
   input cke;
1174
   output reg zq;
1175
   input rst;
1176
   input clk;
1177
 
1178
   parameter clear_value = 0;
1179
   parameter set_value = 1;
1180
   parameter wrap_value = 8;
1181
   parameter level1_value = 15;
1182
 
1183
   reg  [length:1] qi;
1184
   reg lfsr_fb;
1185
   wire [length:1] q_next;
1186
   reg [32:1] polynom;
1187
   integer i;
1188
 
1189
   always @ (qi)
1190
   begin
1191
        case (length)
1192
         2: polynom = 32'b11;                               // 0x3
1193
         3: polynom = 32'b110;                              // 0x6
1194
         4: polynom = 32'b1100;                             // 0xC
1195
         5: polynom = 32'b10100;                            // 0x14
1196
         6: polynom = 32'b110000;                           // 0x30
1197
         7: polynom = 32'b1100000;                          // 0x60
1198
         8: polynom = 32'b10111000;                         // 0xb8
1199
         9: polynom = 32'b100010000;                        // 0x110
1200
        10: polynom = 32'b1001000000;                       // 0x240
1201
        11: polynom = 32'b10100000000;                      // 0x500
1202
        12: polynom = 32'b100000101001;                     // 0x829
1203
        13: polynom = 32'b1000000001100;                    // 0x100C
1204
        14: polynom = 32'b10000000010101;                   // 0x2015
1205
        15: polynom = 32'b110000000000000;                  // 0x6000
1206
        16: polynom = 32'b1101000000001000;                 // 0xD008
1207
        17: polynom = 32'b10010000000000000;                // 0x12000
1208
        18: polynom = 32'b100000010000000000;               // 0x20400
1209
        19: polynom = 32'b1000000000000100011;              // 0x40023
1210
        20: polynom = 32'b10000010000000000000;             // 0x82000
1211
        21: polynom = 32'b101000000000000000000;            // 0x140000
1212
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1213
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1214
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1215
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1216
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1217
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1218
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1219
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1220
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1221
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1222
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1223
        default: polynom = 32'b0;
1224
        endcase
1225
        lfsr_fb = qi[length];
1226
        for (i=length-1; i>=1; i=i-1) begin
1227
            if (polynom[i])
1228
                lfsr_fb = lfsr_fb  ~^ qi[i];
1229
        end
1230
    end
1231
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1232
 
1233
   always @ (posedge clk or posedge rst)
1234
     if (rst)
1235
       qi <= {length{1'b0}};
1236
     else
1237
     if (cke)
1238
       qi <= q_next;
1239
 
1240
 
1241
 
1242
   always @ (posedge clk or posedge rst)
1243
     if (rst)
1244
       zq <= 1'b1;
1245
     else
1246
     if (cke)
1247
       zq <= q_next == {length{1'b0}};
1248
endmodule
1249
//////////////////////////////////////////////////////////////////////
1250
////                                                              ////
1251
////  Versatile counter                                           ////
1252
////                                                              ////
1253
////  Description                                                 ////
1254
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1255
////  counter                                                     ////
1256
////                                                              ////
1257
////  To Do:                                                      ////
1258
////   - add LFSR with more taps                                  ////
1259
////                                                              ////
1260
////  Author(s):                                                  ////
1261
////      - Michael Unneback, unneback@opencores.org              ////
1262
////        ORSoC AB                                              ////
1263
////                                                              ////
1264
//////////////////////////////////////////////////////////////////////
1265
////                                                              ////
1266
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1267
////                                                              ////
1268
//// This source file may be used and distributed without         ////
1269
//// restriction provided that this copyright statement is not    ////
1270
//// removed from the file and that any derivative work contains  ////
1271
//// the original copyright notice and the associated disclaimer. ////
1272
////                                                              ////
1273
//// This source file is free software; you can redistribute it   ////
1274
//// and/or modify it under the terms of the GNU Lesser General   ////
1275
//// Public License as published by the Free Software Foundation; ////
1276
//// either version 2.1 of the License, or (at your option) any   ////
1277
//// later version.                                               ////
1278
////                                                              ////
1279
//// This source is distributed in the hope that it will be       ////
1280
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1281
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1282
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1283
//// details.                                                     ////
1284
////                                                              ////
1285
//// You should have received a copy of the GNU Lesser General    ////
1286
//// Public License along with this source; if not, download it   ////
1287
//// from http://www.opencores.org/lgpl.shtml                     ////
1288
////                                                              ////
1289
//////////////////////////////////////////////////////////////////////
1290
 
1291
// LFSR counter
1292 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1293 6 unneback
 
1294
   parameter length = 4;
1295
   input cke;
1296
   input rew;
1297
   output reg level1;
1298
   input rst;
1299
   input clk;
1300
 
1301
   parameter clear_value = 0;
1302
   parameter set_value = 1;
1303
   parameter wrap_value = 8;
1304
   parameter level1_value = 15;
1305
 
1306
   reg  [length:1] qi;
1307
   reg lfsr_fb, lfsr_fb_rew;
1308
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1309
   reg [32:1] polynom_rew;
1310
   integer j;
1311
   reg [32:1] polynom;
1312
   integer i;
1313
 
1314
   always @ (qi)
1315
   begin
1316
        case (length)
1317
         2: polynom = 32'b11;                               // 0x3
1318
         3: polynom = 32'b110;                              // 0x6
1319
         4: polynom = 32'b1100;                             // 0xC
1320
         5: polynom = 32'b10100;                            // 0x14
1321
         6: polynom = 32'b110000;                           // 0x30
1322
         7: polynom = 32'b1100000;                          // 0x60
1323
         8: polynom = 32'b10111000;                         // 0xb8
1324
         9: polynom = 32'b100010000;                        // 0x110
1325
        10: polynom = 32'b1001000000;                       // 0x240
1326
        11: polynom = 32'b10100000000;                      // 0x500
1327
        12: polynom = 32'b100000101001;                     // 0x829
1328
        13: polynom = 32'b1000000001100;                    // 0x100C
1329
        14: polynom = 32'b10000000010101;                   // 0x2015
1330
        15: polynom = 32'b110000000000000;                  // 0x6000
1331
        16: polynom = 32'b1101000000001000;                 // 0xD008
1332
        17: polynom = 32'b10010000000000000;                // 0x12000
1333
        18: polynom = 32'b100000010000000000;               // 0x20400
1334
        19: polynom = 32'b1000000000000100011;              // 0x40023
1335
        20: polynom = 32'b10000010000000000000;             // 0x82000
1336
        21: polynom = 32'b101000000000000000000;            // 0x140000
1337
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1338
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1339
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1340
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1341
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1342
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1343
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1344
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1345
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1346
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1347
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1348
        default: polynom = 32'b0;
1349
        endcase
1350
        lfsr_fb = qi[length];
1351
        for (i=length-1; i>=1; i=i-1) begin
1352
            if (polynom[i])
1353
                lfsr_fb = lfsr_fb  ~^ qi[i];
1354
        end
1355
    end
1356
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1357
   always @ (qi)
1358
   begin
1359
        case (length)
1360
         2: polynom_rew = 32'b11;
1361
         3: polynom_rew = 32'b110;
1362
         4: polynom_rew = 32'b1100;
1363
         5: polynom_rew = 32'b10100;
1364
         6: polynom_rew = 32'b110000;
1365
         7: polynom_rew = 32'b1100000;
1366
         8: polynom_rew = 32'b10111000;
1367
         9: polynom_rew = 32'b100010000;
1368
        10: polynom_rew = 32'b1001000000;
1369
        11: polynom_rew = 32'b10100000000;
1370
        12: polynom_rew = 32'b100000101001;
1371
        13: polynom_rew = 32'b1000000001100;
1372
        14: polynom_rew = 32'b10000000010101;
1373
        15: polynom_rew = 32'b110000000000000;
1374
        16: polynom_rew = 32'b1101000000001000;
1375
        17: polynom_rew = 32'b10010000000000000;
1376
        18: polynom_rew = 32'b100000010000000000;
1377
        19: polynom_rew = 32'b1000000000000100011;
1378
        20: polynom_rew = 32'b10000010000000000000;
1379
        21: polynom_rew = 32'b101000000000000000000;
1380
        22: polynom_rew = 32'b1100000000000000000000;
1381
        23: polynom_rew = 32'b10000100000000000000000;
1382
        24: polynom_rew = 32'b111000010000000000000000;
1383
        25: polynom_rew = 32'b1001000000000000000000000;
1384
        26: polynom_rew = 32'b10000000000000000000100011;
1385
        27: polynom_rew = 32'b100000000000000000000010011;
1386
        28: polynom_rew = 32'b1100100000000000000000000000;
1387
        29: polynom_rew = 32'b10100000000000000000000000000;
1388
        30: polynom_rew = 32'b100000000000000000000000101001;
1389
        31: polynom_rew = 32'b1001000000000000000000000000000;
1390
        32: polynom_rew = 32'b10000000001000000000000000000011;
1391
        default: polynom_rew = 32'b0;
1392
        endcase
1393
        // rotate left
1394
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1395
        lfsr_fb_rew = qi[length];
1396
        for (i=length-1; i>=1; i=i-1) begin
1397
            if (polynom_rew[i])
1398
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1399
        end
1400
    end
1401
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1402
   assign q_next = rew ? q_next_rew : q_next_fw;
1403
 
1404
   always @ (posedge clk or posedge rst)
1405
     if (rst)
1406
       qi <= {length{1'b0}};
1407
     else
1408
     if (cke)
1409
       qi <= q_next;
1410
 
1411
 
1412
 
1413
    always @ (posedge clk or posedge rst)
1414
    if (rst)
1415
        level1 <= 1'b0;
1416
    else
1417
    if (cke)
1418
    if (q_next == level1_value)
1419
        level1 <= 1'b1;
1420
    else if (qi == level1_value & rew)
1421
        level1 <= 1'b0;
1422
endmodule
1423
//////////////////////////////////////////////////////////////////////
1424
////                                                              ////
1425
////  Versatile counter                                           ////
1426
////                                                              ////
1427
////  Description                                                 ////
1428
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1429
////  counter                                                     ////
1430
////                                                              ////
1431
////  To Do:                                                      ////
1432
////   - add LFSR with more taps                                  ////
1433
////                                                              ////
1434
////  Author(s):                                                  ////
1435
////      - Michael Unneback, unneback@opencores.org              ////
1436
////        ORSoC AB                                              ////
1437
////                                                              ////
1438
//////////////////////////////////////////////////////////////////////
1439
////                                                              ////
1440
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1441
////                                                              ////
1442
//// This source file may be used and distributed without         ////
1443
//// restriction provided that this copyright statement is not    ////
1444
//// removed from the file and that any derivative work contains  ////
1445
//// the original copyright notice and the associated disclaimer. ////
1446
////                                                              ////
1447
//// This source file is free software; you can redistribute it   ////
1448
//// and/or modify it under the terms of the GNU Lesser General   ////
1449
//// Public License as published by the Free Software Foundation; ////
1450
//// either version 2.1 of the License, or (at your option) any   ////
1451
//// later version.                                               ////
1452
////                                                              ////
1453
//// This source is distributed in the hope that it will be       ////
1454
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1455
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1456
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1457
//// details.                                                     ////
1458
////                                                              ////
1459
//// You should have received a copy of the GNU Lesser General    ////
1460
//// Public License along with this source; if not, download it   ////
1461
//// from http://www.opencores.org/lgpl.shtml                     ////
1462
////                                                              ////
1463
//////////////////////////////////////////////////////////////////////
1464
 
1465
// GRAY counter
1466 18 unneback
module vl_cnt_gray ( q, rst, clk);
1467 6 unneback
 
1468
   parameter length = 4;
1469
   output reg [length:1] q;
1470
   input rst;
1471
   input clk;
1472
 
1473
   parameter clear_value = 0;
1474
   parameter set_value = 1;
1475
   parameter wrap_value = 8;
1476
   parameter level1_value = 15;
1477
 
1478
   reg  [length:1] qi;
1479
   wire [length:1] q_next;
1480
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1481
 
1482
   always @ (posedge clk or posedge rst)
1483
     if (rst)
1484
       qi <= {length{1'b0}};
1485
     else
1486
       qi <= q_next;
1487
 
1488
   always @ (posedge clk or posedge rst)
1489
     if (rst)
1490
       q <= {length{1'b0}};
1491
     else
1492
         q <= (q_next>>1) ^ q_next;
1493
 
1494
endmodule
1495
//////////////////////////////////////////////////////////////////////
1496
////                                                              ////
1497
////  Versatile counter                                           ////
1498
////                                                              ////
1499
////  Description                                                 ////
1500
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1501
////  counter                                                     ////
1502
////                                                              ////
1503
////  To Do:                                                      ////
1504
////   - add LFSR with more taps                                  ////
1505
////                                                              ////
1506
////  Author(s):                                                  ////
1507
////      - Michael Unneback, unneback@opencores.org              ////
1508
////        ORSoC AB                                              ////
1509
////                                                              ////
1510
//////////////////////////////////////////////////////////////////////
1511
////                                                              ////
1512
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1513
////                                                              ////
1514
//// This source file may be used and distributed without         ////
1515
//// restriction provided that this copyright statement is not    ////
1516
//// removed from the file and that any derivative work contains  ////
1517
//// the original copyright notice and the associated disclaimer. ////
1518
////                                                              ////
1519
//// This source file is free software; you can redistribute it   ////
1520
//// and/or modify it under the terms of the GNU Lesser General   ////
1521
//// Public License as published by the Free Software Foundation; ////
1522
//// either version 2.1 of the License, or (at your option) any   ////
1523
//// later version.                                               ////
1524
////                                                              ////
1525
//// This source is distributed in the hope that it will be       ////
1526
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1527
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1528
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1529
//// details.                                                     ////
1530
////                                                              ////
1531
//// You should have received a copy of the GNU Lesser General    ////
1532
//// Public License along with this source; if not, download it   ////
1533
//// from http://www.opencores.org/lgpl.shtml                     ////
1534
////                                                              ////
1535
//////////////////////////////////////////////////////////////////////
1536
 
1537
// GRAY counter
1538 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1539 6 unneback
 
1540
   parameter length = 4;
1541
   input cke;
1542
   output reg [length:1] q;
1543
   input rst;
1544
   input clk;
1545
 
1546
   parameter clear_value = 0;
1547
   parameter set_value = 1;
1548
   parameter wrap_value = 8;
1549
   parameter level1_value = 15;
1550
 
1551
   reg  [length:1] qi;
1552
   wire [length:1] q_next;
1553
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1554
 
1555
   always @ (posedge clk or posedge rst)
1556
     if (rst)
1557
       qi <= {length{1'b0}};
1558
     else
1559
     if (cke)
1560
       qi <= q_next;
1561
 
1562
   always @ (posedge clk or posedge rst)
1563
     if (rst)
1564
       q <= {length{1'b0}};
1565
     else
1566
       if (cke)
1567
         q <= (q_next>>1) ^ q_next;
1568
 
1569
endmodule
1570
//////////////////////////////////////////////////////////////////////
1571
////                                                              ////
1572
////  Versatile counter                                           ////
1573
////                                                              ////
1574
////  Description                                                 ////
1575
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1576
////  counter                                                     ////
1577
////                                                              ////
1578
////  To Do:                                                      ////
1579
////   - add LFSR with more taps                                  ////
1580
////                                                              ////
1581
////  Author(s):                                                  ////
1582
////      - Michael Unneback, unneback@opencores.org              ////
1583
////        ORSoC AB                                              ////
1584
////                                                              ////
1585
//////////////////////////////////////////////////////////////////////
1586
////                                                              ////
1587
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1588
////                                                              ////
1589
//// This source file may be used and distributed without         ////
1590
//// restriction provided that this copyright statement is not    ////
1591
//// removed from the file and that any derivative work contains  ////
1592
//// the original copyright notice and the associated disclaimer. ////
1593
////                                                              ////
1594
//// This source file is free software; you can redistribute it   ////
1595
//// and/or modify it under the terms of the GNU Lesser General   ////
1596
//// Public License as published by the Free Software Foundation; ////
1597
//// either version 2.1 of the License, or (at your option) any   ////
1598
//// later version.                                               ////
1599
////                                                              ////
1600
//// This source is distributed in the hope that it will be       ////
1601
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1602
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1603
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1604
//// details.                                                     ////
1605
////                                                              ////
1606
//// You should have received a copy of the GNU Lesser General    ////
1607
//// Public License along with this source; if not, download it   ////
1608
//// from http://www.opencores.org/lgpl.shtml                     ////
1609
////                                                              ////
1610
//////////////////////////////////////////////////////////////////////
1611
 
1612
// GRAY counter
1613 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1614 6 unneback
 
1615
   parameter length = 4;
1616
   input cke;
1617
   output reg [length:1] q;
1618
   output [length:1] q_bin;
1619
   input rst;
1620
   input clk;
1621
 
1622
   parameter clear_value = 0;
1623
   parameter set_value = 1;
1624
   parameter wrap_value = 8;
1625
   parameter level1_value = 15;
1626
 
1627
   reg  [length:1] qi;
1628
   wire [length:1] q_next;
1629
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1630
 
1631
   always @ (posedge clk or posedge rst)
1632
     if (rst)
1633
       qi <= {length{1'b0}};
1634
     else
1635
     if (cke)
1636
       qi <= q_next;
1637
 
1638
   always @ (posedge clk or posedge rst)
1639
     if (rst)
1640
       q <= {length{1'b0}};
1641
     else
1642
       if (cke)
1643
         q <= (q_next>>1) ^ q_next;
1644
 
1645
   assign q_bin = qi;
1646
 
1647
endmodule
1648
//////////////////////////////////////////////////////////////////////
1649
////                                                              ////
1650
////  Versatile library, counters                                 ////
1651
////                                                              ////
1652
////  Description                                                 ////
1653
////  counters                                                    ////
1654
////                                                              ////
1655
////                                                              ////
1656
////  To Do:                                                      ////
1657
////   - add more counters                                        ////
1658
////                                                              ////
1659
////  Author(s):                                                  ////
1660
////      - Michael Unneback, unneback@opencores.org              ////
1661
////        ORSoC AB                                              ////
1662
////                                                              ////
1663
//////////////////////////////////////////////////////////////////////
1664
////                                                              ////
1665
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1666
////                                                              ////
1667
//// This source file may be used and distributed without         ////
1668
//// restriction provided that this copyright statement is not    ////
1669
//// removed from the file and that any derivative work contains  ////
1670
//// the original copyright notice and the associated disclaimer. ////
1671
////                                                              ////
1672
//// This source file is free software; you can redistribute it   ////
1673
//// and/or modify it under the terms of the GNU Lesser General   ////
1674
//// Public License as published by the Free Software Foundation; ////
1675
//// either version 2.1 of the License, or (at your option) any   ////
1676
//// later version.                                               ////
1677
////                                                              ////
1678
//// This source is distributed in the hope that it will be       ////
1679
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1680
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1681
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1682
//// details.                                                     ////
1683
////                                                              ////
1684
//// You should have received a copy of the GNU Lesser General    ////
1685
//// Public License along with this source; if not, download it   ////
1686
//// from http://www.opencores.org/lgpl.shtml                     ////
1687
////                                                              ////
1688
//////////////////////////////////////////////////////////////////////
1689
 
1690 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1691 6 unneback
 
1692
   parameter length = 4;
1693
   output reg [0:length-1] q;
1694
   input rst;
1695
   input clk;
1696
 
1697
    always @ (posedge clk or posedge rst)
1698
    if (rst)
1699
        q <= {1'b1,{length-1{1'b0}}};
1700
    else
1701
        q <= {q[length-1],q[0:length-2]};
1702
 
1703
endmodule
1704
 
1705 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1706 6 unneback
 
1707
   parameter length = 4;
1708
   input cke;
1709
   output reg [0:length-1] q;
1710
   input rst;
1711
   input clk;
1712
 
1713
    always @ (posedge clk or posedge rst)
1714
    if (rst)
1715
        q <= {1'b1,{length-1{1'b0}}};
1716
    else
1717
        if (cke)
1718
            q <= {q[length-1],q[0:length-2]};
1719
 
1720
endmodule
1721
 
1722 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1723 6 unneback
 
1724
   parameter length = 4;
1725
   input cke, clear;
1726
   output reg [0:length-1] q;
1727
   input rst;
1728
   input clk;
1729
 
1730
    always @ (posedge clk or posedge rst)
1731
    if (rst)
1732
        q <= {1'b1,{length-1{1'b0}}};
1733
    else
1734
        if (cke)
1735
            if (clear)
1736
                q <= {1'b1,{length-1{1'b0}}};
1737
            else
1738
                q <= q >> 1;
1739
 
1740
endmodule
1741
 
1742 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1743 6 unneback
 
1744
   parameter length = 4;
1745
   input cke, clear;
1746
   output reg [0:length-1] q;
1747
   input rst;
1748
   input clk;
1749
 
1750
    always @ (posedge clk or posedge rst)
1751
    if (rst)
1752
        q <= {1'b1,{length-1{1'b0}}};
1753
    else
1754
        if (cke)
1755
            if (clear)
1756
                q <= {1'b1,{length-1{1'b0}}};
1757
            else
1758
            q <= {q[length-1],q[0:length-2]};
1759
 
1760
endmodule
1761
//////////////////////////////////////////////////////////////////////
1762
////                                                              ////
1763
////  Versatile library, memories                                 ////
1764
////                                                              ////
1765
////  Description                                                 ////
1766
////  memories                                                    ////
1767
////                                                              ////
1768
////                                                              ////
1769
////  To Do:                                                      ////
1770
////   - add more memory types                                    ////
1771
////                                                              ////
1772
////  Author(s):                                                  ////
1773
////      - Michael Unneback, unneback@opencores.org              ////
1774
////        ORSoC AB                                              ////
1775
////                                                              ////
1776
//////////////////////////////////////////////////////////////////////
1777
////                                                              ////
1778
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1779
////                                                              ////
1780
//// This source file may be used and distributed without         ////
1781
//// restriction provided that this copyright statement is not    ////
1782
//// removed from the file and that any derivative work contains  ////
1783
//// the original copyright notice and the associated disclaimer. ////
1784
////                                                              ////
1785
//// This source file is free software; you can redistribute it   ////
1786
//// and/or modify it under the terms of the GNU Lesser General   ////
1787
//// Public License as published by the Free Software Foundation; ////
1788
//// either version 2.1 of the License, or (at your option) any   ////
1789
//// later version.                                               ////
1790
////                                                              ////
1791
//// This source is distributed in the hope that it will be       ////
1792
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1793
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1794
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1795
//// details.                                                     ////
1796
////                                                              ////
1797
//// You should have received a copy of the GNU Lesser General    ////
1798
//// Public License along with this source; if not, download it   ////
1799
//// from http://www.opencores.org/lgpl.shtml                     ////
1800
////                                                              ////
1801
//////////////////////////////////////////////////////////////////////
1802
 
1803
/// ROM
1804
 
1805 7 unneback
module vl_rom_init ( adr, q, clk);
1806
   parameter data_width = 32;
1807
   parameter addr_width = 8;
1808
   input [(addr_width-1):0]       adr;
1809
   output reg [(data_width-1):0] q;
1810
   input                         clk;
1811
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1812
   parameter memory_file = "vl_rom.vmem";
1813
   initial
1814
     begin
1815
        $readmemh(memory_file, rom);
1816
     end
1817
 
1818
   always @ (posedge clk)
1819
     q <= rom[adr];
1820 6 unneback
 
1821 7 unneback
endmodule
1822
 
1823 14 unneback
/*
1824 7 unneback
module vl_rom ( adr, q, clk);
1825
 
1826 6 unneback
parameter data_width = 32;
1827
parameter addr_width = 4;
1828
 
1829
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1830
    {32'h18000000},
1831
    {32'hA8200000},
1832
    {32'hA8200000},
1833
    {32'hA8200000},
1834
    {32'h44003000},
1835
    {32'h15000000},
1836
    {32'h15000000},
1837
    {32'h15000000},
1838
    {32'h15000000},
1839
    {32'h15000000},
1840
    {32'h15000000},
1841
    {32'h15000000},
1842
    {32'h15000000},
1843
    {32'h15000000},
1844
    {32'h15000000},
1845
    {32'h15000000}};
1846
 
1847 7 unneback
input [addr_width-1:0] adr;
1848 6 unneback
output reg [data_width-1:0] q;
1849
input clk;
1850
 
1851
always @ (posedge clk)
1852 7 unneback
    q <= data[adr];
1853 6 unneback
 
1854
endmodule
1855 14 unneback
*/
1856 6 unneback
// Single port RAM
1857
 
1858
module vl_ram ( d, adr, we, q, clk);
1859
   parameter data_width = 32;
1860
   parameter addr_width = 8;
1861
   input [(data_width-1):0]      d;
1862
   input [(addr_width-1):0]       adr;
1863
   input                         we;
1864 7 unneback
   output reg [(data_width-1):0] q;
1865 6 unneback
   input                         clk;
1866
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1867 7 unneback
   parameter init = 0;
1868
   parameter memory_file = "vl_ram.vmem";
1869
   generate if (init) begin : init_mem
1870
   initial
1871
     begin
1872
        $readmemh(memory_file, ram);
1873
     end
1874
   end
1875
   endgenerate
1876
 
1877 6 unneback
   always @ (posedge clk)
1878
   begin
1879
   if (we)
1880
     ram[adr] <= d;
1881
   q <= ram[adr];
1882
   end
1883
 
1884
endmodule
1885
 
1886 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1887
   parameter data_width = 32;
1888
   parameter addr_width = 8;
1889
   input [(data_width-1):0]      d;
1890
   input [(addr_width-1):0]       adr;
1891
   input [(addr_width/4)-1:0]    be;
1892
   input                         we;
1893
   output reg [(data_width-1):0] q;
1894
   input                         clk;
1895
 
1896
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1897
 
1898
   parameter init = 0;
1899
   parameter memory_file = "vl_ram.vmem";
1900
   generate if (init) begin : init_mem
1901
   initial
1902
     begin
1903
        $readmemh(memory_file, ram);
1904
     end
1905
   end
1906
   endgenerate
1907
 
1908
   genvar i;
1909
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1910
      always @ (posedge clk)
1911
      if (we & be[i])
1912
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1913
   end
1914
   endgenerate
1915
 
1916
   always @ (posedge clk)
1917
      q <= ram[adr];
1918
 
1919
endmodule
1920
 
1921
 
1922 6 unneback
// Dual port RAM
1923
 
1924
// ACTEL FPGA should not use logic to handle rw collision
1925
`ifdef ACTEL
1926
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
1927
`else
1928
        `define SYN
1929
`endif
1930
 
1931 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1932 6 unneback
   parameter data_width = 32;
1933
   parameter addr_width = 8;
1934
   input [(data_width-1):0]      d_a;
1935
   input [(addr_width-1):0]       adr_a;
1936
   input [(addr_width-1):0]       adr_b;
1937
   input                         we_a;
1938
   output [(data_width-1):0]      q_b;
1939
   input                         clk_a, clk_b;
1940
   reg [(addr_width-1):0]         adr_b_reg;
1941
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
1942 7 unneback
 
1943
   parameter init = 0;
1944
   parameter memory_file = "vl_ram.vmem";
1945
   generate if (init) begin : init_mem
1946
   initial
1947
     begin
1948
        $readmemh(memory_file, ram);
1949
     end
1950
   end
1951
   endgenerate
1952
 
1953 6 unneback
   always @ (posedge clk_a)
1954
   if (we_a)
1955
     ram[adr_a] <= d_a;
1956
   always @ (posedge clk_b)
1957
   adr_b_reg <= adr_b;
1958
   assign q_b = ram[adr_b_reg];
1959
endmodule
1960
 
1961 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1962 6 unneback
   parameter data_width = 32;
1963
   parameter addr_width = 8;
1964
   input [(data_width-1):0]      d_a;
1965
   input [(addr_width-1):0]       adr_a;
1966
   input [(addr_width-1):0]       adr_b;
1967
   input                         we_a;
1968
   output [(data_width-1):0]      q_b;
1969
   output reg [(data_width-1):0] q_a;
1970
   input                         clk_a, clk_b;
1971
   reg [(data_width-1):0]         q_b;
1972
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
1973 7 unneback
 
1974
   parameter init = 0;
1975
   parameter memory_file = "vl_ram.vmem";
1976
   generate if (init) begin : init_mem
1977
   initial
1978
     begin
1979
        $readmemh(memory_file, ram);
1980
     end
1981
   end
1982
   endgenerate
1983
 
1984 6 unneback
   always @ (posedge clk_a)
1985
     begin
1986
        q_a <= ram[adr_a];
1987
        if (we_a)
1988
             ram[adr_a] <= d_a;
1989
     end
1990
   always @ (posedge clk_b)
1991
          q_b <= ram[adr_b];
1992
endmodule
1993
 
1994 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1995 6 unneback
   parameter data_width = 32;
1996
   parameter addr_width = 8;
1997
   input [(data_width-1):0]      d_a;
1998
   input [(addr_width-1):0]       adr_a;
1999
   input [(addr_width-1):0]       adr_b;
2000
   input                         we_a;
2001
   output [(data_width-1):0]      q_b;
2002
   input [(data_width-1):0]       d_b;
2003
   output reg [(data_width-1):0] q_a;
2004
   input                         we_b;
2005
   input                         clk_a, clk_b;
2006
   reg [(data_width-1):0]         q_b;
2007
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
2008 7 unneback
 
2009
   parameter init = 0;
2010
   parameter memory_file = "vl_ram.vmem";
2011
   generate if (init) begin : init_mem
2012
   initial
2013
     begin
2014
        $readmemh(memory_file, ram);
2015
     end
2016
   end
2017
   endgenerate
2018
 
2019 6 unneback
   always @ (posedge clk_a)
2020
     begin
2021
        q_a <= ram[adr_a];
2022
        if (we_a)
2023
             ram[adr_a] <= d_a;
2024
     end
2025
   always @ (posedge clk_b)
2026
     begin
2027
        q_b <= ram[adr_b];
2028
        if (we_b)
2029
          ram[adr_b] <= d_b;
2030
     end
2031
endmodule
2032
 
2033
// Content addresable memory, CAM
2034
 
2035
// FIFO
2036
 
2037
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2038
 
2039 11 unneback
   parameter addr_width = 4;
2040
   parameter N = addr_width-1;
2041 6 unneback
 
2042
   parameter Q1 = 2'b00;
2043
   parameter Q2 = 2'b01;
2044
   parameter Q3 = 2'b11;
2045
   parameter Q4 = 2'b10;
2046
 
2047
   parameter going_empty = 1'b0;
2048
   parameter going_full  = 1'b1;
2049
 
2050
   input [N:0]  wptr, rptr;
2051 14 unneback
   output       fifo_empty;
2052 6 unneback
   output       fifo_full;
2053
   input        wclk, rclk, rst;
2054
 
2055
`ifndef GENERATE_DIRECTION_AS_LATCH
2056
   wire direction;
2057
`endif
2058
`ifdef GENERATE_DIRECTION_AS_LATCH
2059
   reg direction;
2060
`endif
2061
   reg  direction_set, direction_clr;
2062
 
2063
   wire async_empty, async_full;
2064
   wire fifo_full2;
2065 14 unneback
   wire fifo_empty2;
2066 6 unneback
 
2067
   // direction_set
2068
   always @ (wptr[N:N-1] or rptr[N:N-1])
2069
     case ({wptr[N:N-1],rptr[N:N-1]})
2070
       {Q1,Q2} : direction_set <= 1'b1;
2071
       {Q2,Q3} : direction_set <= 1'b1;
2072
       {Q3,Q4} : direction_set <= 1'b1;
2073
       {Q4,Q1} : direction_set <= 1'b1;
2074
       default : direction_set <= 1'b0;
2075
     endcase
2076
 
2077
   // direction_clear
2078
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2079
     if (rst)
2080
       direction_clr <= 1'b1;
2081
     else
2082
       case ({wptr[N:N-1],rptr[N:N-1]})
2083
         {Q2,Q1} : direction_clr <= 1'b1;
2084
         {Q3,Q2} : direction_clr <= 1'b1;
2085
         {Q4,Q3} : direction_clr <= 1'b1;
2086
         {Q1,Q4} : direction_clr <= 1'b1;
2087
         default : direction_clr <= 1'b0;
2088
       endcase
2089
 
2090
`ifndef GENERATE_DIRECTION_AS_LATCH
2091 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2092 6 unneback
`endif
2093
 
2094
`ifdef GENERATE_DIRECTION_AS_LATCH
2095
   always @ (posedge direction_set or posedge direction_clr)
2096
     if (direction_clr)
2097
       direction <= going_empty;
2098
     else
2099
       direction <= going_full;
2100
`endif
2101
 
2102
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2103
   assign async_full  = (wptr == rptr) && (direction==going_full);
2104
 
2105 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2106
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2107 6 unneback
 
2108
/*
2109
   always @ (posedge wclk or posedge rst or posedge async_full)
2110
     if (rst)
2111
       {fifo_full, fifo_full2} <= 2'b00;
2112
     else if (async_full)
2113
       {fifo_full, fifo_full2} <= 2'b11;
2114
     else
2115
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2116
*/
2117 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2118 6 unneback
     if (async_empty)
2119
       {fifo_empty, fifo_empty2} <= 2'b11;
2120
     else
2121 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2122 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2123
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2124 6 unneback
 
2125
endmodule // async_comp
2126
 
2127
module vl_fifo_1r1w_async (
2128
    d, wr, fifo_full, wr_clk, wr_rst,
2129
    q, rd, fifo_empty, rd_clk, rd_rst
2130
    );
2131
 
2132
parameter data_width = 18;
2133
parameter addr_width = 4;
2134
 
2135
// write side
2136
input  [data_width-1:0] d;
2137
input                   wr;
2138
output                  fifo_full;
2139
input                   wr_clk;
2140
input                   wr_rst;
2141
// read side
2142
output [data_width-1:0] q;
2143
input                   rd;
2144
output                  fifo_empty;
2145
input                   rd_clk;
2146
input                   rd_rst;
2147
 
2148
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
2149 21 unneback
/*
2150 6 unneback
vl_fifo_1r1w_async (
2151
    d, wr, fifo_full, wr_clk, wr_rst,
2152
    q, rd, fifo_empty, rd_clk, rd_rst
2153
    );
2154 21 unneback
*/
2155 18 unneback
vl_cnt_gray_ce_bin
2156 6 unneback
    # ( .length(addr_width))
2157
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2158
 
2159 18 unneback
vl_cnt_gray_ce_bin
2160 6 unneback
    # (.length(addr_width))
2161
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
2162
 
2163 7 unneback
vl_dpram_1r1w
2164 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2165
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2166
 
2167
vl_fifo_cmp_async
2168
    # (.addr_width(addr_width))
2169
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2170
 
2171
endmodule
2172
 
2173 8 unneback
module vl_fifo_2r2w_async (
2174 6 unneback
    // a side
2175
    a_d, a_wr, a_fifo_full,
2176
    a_q, a_rd, a_fifo_empty,
2177
    a_clk, a_rst,
2178
    // b side
2179
    b_d, b_wr, b_fifo_full,
2180
    b_q, b_rd, b_fifo_empty,
2181
    b_clk, b_rst
2182
    );
2183
 
2184
parameter data_width = 18;
2185
parameter addr_width = 4;
2186
 
2187
// a side
2188
input  [data_width-1:0] a_d;
2189
input                   a_wr;
2190
output                  a_fifo_full;
2191
output [data_width-1:0] a_q;
2192
input                   a_rd;
2193
output                  a_fifo_empty;
2194
input                   a_clk;
2195
input                   a_rst;
2196
 
2197
// b side
2198
input  [data_width-1:0] b_d;
2199
input                   b_wr;
2200
output                  b_fifo_full;
2201
output [data_width-1:0] b_q;
2202
input                   b_rd;
2203
output                  b_fifo_empty;
2204
input                   b_clk;
2205
input                   b_rst;
2206
 
2207
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2208
vl_fifo_1r1w_async_a (
2209
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2210
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2211
    );
2212
 
2213
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2214
vl_fifo_1r1w_async_b (
2215
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2216
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2217
    );
2218
 
2219
endmodule
2220
 
2221 8 unneback
module vl_fifo_2r2w_async_simplex (
2222 6 unneback
    // a side
2223
    a_d, a_wr, a_fifo_full,
2224
    a_q, a_rd, a_fifo_empty,
2225
    a_clk, a_rst,
2226
    // b side
2227
    b_d, b_wr, b_fifo_full,
2228
    b_q, b_rd, b_fifo_empty,
2229
    b_clk, b_rst
2230
    );
2231
 
2232
parameter data_width = 18;
2233
parameter addr_width = 4;
2234
 
2235
// a side
2236
input  [data_width-1:0] a_d;
2237
input                   a_wr;
2238
output                  a_fifo_full;
2239
output [data_width-1:0] a_q;
2240
input                   a_rd;
2241
output                  a_fifo_empty;
2242
input                   a_clk;
2243
input                   a_rst;
2244
 
2245
// b side
2246
input  [data_width-1:0] b_d;
2247
input                   b_wr;
2248
output                  b_fifo_full;
2249
output [data_width-1:0] b_q;
2250
input                   b_rd;
2251
output                  b_fifo_empty;
2252
input                   b_clk;
2253
input                   b_rst;
2254
 
2255
// adr_gen
2256
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2257
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2258
// dpram
2259
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2260
 
2261 18 unneback
vl_cnt_gray_ce_bin
2262 6 unneback
    # ( .length(addr_width))
2263
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2264
 
2265 18 unneback
vl_cnt_gray_ce_bin
2266 6 unneback
    # (.length(addr_width))
2267
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2268
 
2269 18 unneback
vl_cnt_gray_ce_bin
2270 6 unneback
    # ( .length(addr_width))
2271
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2272
 
2273 18 unneback
vl_cnt_gray_ce_bin
2274 6 unneback
    # (.length(addr_width))
2275
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2276
 
2277
// mux read or write adr to DPRAM
2278
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2279
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2280
 
2281 11 unneback
vl_dpram_2r2w
2282 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2283
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2284
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2285
 
2286 11 unneback
vl_fifo_cmp_async
2287 6 unneback
    # (.addr_width(addr_width))
2288
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2289
 
2290 11 unneback
vl_fifo_cmp_async
2291 6 unneback
    # (.addr_width(addr_width))
2292
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2293
 
2294
endmodule
2295 12 unneback
//////////////////////////////////////////////////////////////////////
2296
////                                                              ////
2297
////  Versatile library, wishbone stuff                           ////
2298
////                                                              ////
2299
////  Description                                                 ////
2300
////  Wishbone compliant modules                                  ////
2301
////                                                              ////
2302
////                                                              ////
2303
////  To Do:                                                      ////
2304
////   -                                                          ////
2305
////                                                              ////
2306
////  Author(s):                                                  ////
2307
////      - Michael Unneback, unneback@opencores.org              ////
2308
////        ORSoC AB                                              ////
2309
////                                                              ////
2310
//////////////////////////////////////////////////////////////////////
2311
////                                                              ////
2312
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2313
////                                                              ////
2314
//// This source file may be used and distributed without         ////
2315
//// restriction provided that this copyright statement is not    ////
2316
//// removed from the file and that any derivative work contains  ////
2317
//// the original copyright notice and the associated disclaimer. ////
2318
////                                                              ////
2319
//// This source file is free software; you can redistribute it   ////
2320
//// and/or modify it under the terms of the GNU Lesser General   ////
2321
//// Public License as published by the Free Software Foundation; ////
2322
//// either version 2.1 of the License, or (at your option) any   ////
2323
//// later version.                                               ////
2324
////                                                              ////
2325
//// This source is distributed in the hope that it will be       ////
2326
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2327
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2328
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2329
//// details.                                                     ////
2330
////                                                              ////
2331
//// You should have received a copy of the GNU Lesser General    ////
2332
//// Public License along with this source; if not, download it   ////
2333
//// from http://www.opencores.org/lgpl.shtml                     ////
2334
////                                                              ////
2335
//////////////////////////////////////////////////////////////////////
2336
 
2337
// async wb3 - wb3 bridge
2338
`timescale 1ns/1ns
2339 18 unneback
module vl_wb3wb3_bridge (
2340 12 unneback
        // wishbone slave side
2341
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2342
        // wishbone master side
2343
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2344
 
2345
input [31:0] wbs_dat_i;
2346
input [31:2] wbs_adr_i;
2347
input [3:0]  wbs_sel_i;
2348
input [1:0]  wbs_bte_i;
2349
input [2:0]  wbs_cti_i;
2350
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2351
output [31:0] wbs_dat_o;
2352 14 unneback
output wbs_ack_o;
2353 12 unneback
input wbs_clk, wbs_rst;
2354
 
2355
output [31:0] wbm_dat_o;
2356
output reg [31:2] wbm_adr_o;
2357
output [3:0]  wbm_sel_o;
2358
output reg [1:0]  wbm_bte_o;
2359
output reg [2:0]  wbm_cti_o;
2360 14 unneback
output reg wbm_we_o;
2361
output wbm_cyc_o;
2362 12 unneback
output wbm_stb_o;
2363
input [31:0]  wbm_dat_i;
2364
input wbm_ack_i;
2365
input wbm_clk, wbm_rst;
2366
 
2367
parameter addr_width = 4;
2368
 
2369
// bte
2370
parameter linear       = 2'b00;
2371
parameter wrap4        = 2'b01;
2372
parameter wrap8        = 2'b10;
2373
parameter wrap16       = 2'b11;
2374
// cti
2375
parameter classic      = 3'b000;
2376
parameter incburst     = 3'b010;
2377
parameter endofburst   = 3'b111;
2378
 
2379
parameter wbs_adr  = 1'b0;
2380
parameter wbs_data = 1'b1;
2381
 
2382
parameter wbm_adr0 = 2'b00;
2383
parameter wbm_adr1 = 2'b01;
2384
parameter wbm_data = 2'b10;
2385
 
2386
reg [1:0] wbs_bte_reg;
2387
reg wbs;
2388
wire wbs_eoc_alert, wbm_eoc_alert;
2389
reg wbs_eoc, wbm_eoc;
2390
reg [1:0] wbm;
2391
 
2392 14 unneback
wire [1:16] wbs_count, wbm_count;
2393 12 unneback
 
2394
wire [35:0] a_d, a_q, b_d, b_q;
2395
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2396
reg a_rd_reg;
2397
wire b_rd_adr, b_rd_data;
2398 14 unneback
wire b_rd_data_reg;
2399
wire [35:0] temp;
2400 12 unneback
 
2401
`define WE 5
2402
`define BTE 4:3
2403
`define CTI 2:0
2404
 
2405
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2406
always @ (posedge wbs_clk or posedge wbs_rst)
2407
if (wbs_rst)
2408
        wbs_eoc <= 1'b0;
2409
else
2410
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2411
                wbs_eoc <= wbs_bte_i==linear;
2412
        else if (wbs_eoc_alert & (a_rd | a_wr))
2413
                wbs_eoc <= 1'b1;
2414
 
2415 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2416 12 unneback
    cnt0 (
2417
        .cke(wbs_ack_o),
2418
        .clear(wbs_eoc),
2419
        .q(wbs_count),
2420
        .rst(wbs_rst),
2421
        .clk(wbs_clk));
2422
 
2423
always @ (posedge wbs_clk or posedge wbs_rst)
2424
if (wbs_rst)
2425
        wbs <= wbs_adr;
2426
else
2427
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
2428
                wbs <= wbs_data;
2429
        else if (wbs_eoc & wbs_ack_o)
2430
                wbs <= wbs_adr;
2431
 
2432
// wbs FIFO
2433
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
2434
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
2435
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2436
              1'b0;
2437
assign a_rd = !a_fifo_empty;
2438
always @ (posedge wbs_clk or posedge wbs_rst)
2439
if (wbs_rst)
2440
        a_rd_reg <= 1'b0;
2441
else
2442
        a_rd_reg <= a_rd;
2443
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2444
 
2445
assign wbs_dat_o = a_q[35:4];
2446
 
2447
always @ (posedge wbs_clk or posedge wbs_rst)
2448
if (wbs_rst)
2449 13 unneback
        wbs_bte_reg <= 2'b00;
2450 12 unneback
else
2451 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2452 12 unneback
 
2453
// wbm FIFO
2454
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2455
always @ (posedge wbm_clk or posedge wbm_rst)
2456
if (wbm_rst)
2457
        wbm_eoc <= 1'b0;
2458
else
2459
        if (wbm==wbm_adr0 & !b_fifo_empty)
2460
                wbm_eoc <= b_q[`BTE] == linear;
2461
        else if (wbm_eoc_alert & wbm_ack_i)
2462
                wbm_eoc <= 1'b1;
2463
 
2464
always @ (posedge wbm_clk or posedge wbm_rst)
2465
if (wbm_rst)
2466
        wbm <= wbm_adr0;
2467
else
2468
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2469
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2470
        (wbm==wbm_adr1 & !wbm_we_o) |
2471
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2472
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2473
 
2474
assign b_d = {wbm_dat_i,4'b1111};
2475
assign b_wr = !wbm_we_o & wbm_ack_i;
2476
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2477
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2478
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2479
                   1'b0;
2480
assign b_rd = b_rd_adr | b_rd_data;
2481
 
2482 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2483
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2484 12 unneback
 
2485
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2486
 
2487 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2488 12 unneback
    cnt1 (
2489
        .cke(wbm_ack_i),
2490
        .clear(wbm_eoc),
2491
        .q(wbm_count),
2492
        .rst(wbm_rst),
2493
        .clk(wbm_clk));
2494
 
2495
assign wbm_cyc_o = wbm==wbm_data;
2496
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
2497
                   (wbm==wbm_data) ? 1'b1 :
2498
                   1'b0;
2499
 
2500
always @ (posedge wbm_clk or posedge wbm_rst)
2501
if (wbm_rst)
2502
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2503
else begin
2504
        if (wbm==wbm_adr0 & !b_fifo_empty)
2505
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2506
        else if (wbm_eoc_alert & wbm_ack_i)
2507
                wbm_cti_o <= endofburst;
2508
end
2509
 
2510
//async_fifo_dw_simplex_top
2511
vl_fifo_2r2w_async_simplex
2512
# ( .data_width(36), .addr_width(addr_width))
2513
fifo (
2514
    // a side
2515
    .a_d(a_d),
2516
    .a_wr(a_wr),
2517
    .a_fifo_full(a_fifo_full),
2518
    .a_q(a_q),
2519
    .a_rd(a_rd),
2520
    .a_fifo_empty(a_fifo_empty),
2521
    .a_clk(wbs_clk),
2522
    .a_rst(wbs_rst),
2523
    // b side
2524
    .b_d(b_d),
2525
    .b_wr(b_wr),
2526
    .b_fifo_full(b_fifo_full),
2527
    .b_q(b_q),
2528
    .b_rd(b_rd),
2529
    .b_fifo_empty(b_fifo_empty),
2530
    .b_clk(wbm_clk),
2531
    .b_rst(wbm_rst)
2532
    );
2533
 
2534
endmodule
2535 17 unneback
 
2536
// WB ROM
2537 18 unneback
module vl_wb_boot_rom (
2538 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2539 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2540 17 unneback
 
2541 18 unneback
    parameter adr_hi = 31;
2542
    parameter adr_lo = 28;
2543
    parameter adr_sel = 4'hf;
2544
    parameter addr_width = 5;
2545
 
2546 17 unneback
`ifndef BOOT_ROM
2547
`define BOOT_ROM "boot_rom.v"
2548
`endif
2549
 
2550 18 unneback
    input [adr_hi:2]    wb_adr_i;
2551
    input               wb_stb_i;
2552
    input               wb_cyc_i;
2553
    output [31:0]        wb_dat_o;
2554
    output              wb_ack_o;
2555
    output              hit_o;
2556
    input               wb_clk;
2557
    input               wb_rst;
2558
 
2559
    wire hit;
2560
    reg [31:0] wb_dat;
2561
    reg wb_ack;
2562
 
2563
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2564 17 unneback
 
2565
always @ (posedge wb_clk or posedge wb_rst)
2566
    if (wb_rst)
2567 18 unneback
        wb_dat <= 32'h15000000;
2568 17 unneback
    else
2569 18 unneback
         case (wb_adr_i[addr_width-1:2])
2570 17 unneback
`include `BOOT_ROM
2571
           /*
2572
            // Zero r0 and jump to 0x00000100
2573 18 unneback
 
2574
            1 : wb_dat <= 32'hA8200000;
2575
            2 : wb_dat <= 32'hA8C00100;
2576
            3 : wb_dat <= 32'h44003000;
2577
            4 : wb_dat <= 32'h15000000;
2578 17 unneback
            */
2579
           default:
2580 18 unneback
             wb_dat <= 32'h00000000;
2581 17 unneback
 
2582
         endcase // case (wb_adr_i)
2583
 
2584
 
2585
always @ (posedge wb_clk or posedge wb_rst)
2586
    if (wb_rst)
2587 18 unneback
        wb_ack <= 1'b0;
2588 17 unneback
    else
2589 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2590 17 unneback
 
2591 18 unneback
assign hit_o = hit;
2592
assign wb_dat_o = wb_dat & {32{wb_ack}};
2593
assign wb_ack_o = wb_ack;
2594
 
2595 17 unneback
endmodule
2596 18 unneback
//////////////////////////////////////////////////////////////////////
2597
////                                                              ////
2598
////  Arithmetic functions                                        ////
2599
////                                                              ////
2600
////  Description                                                 ////
2601
////  Arithmetic functions for ALU and DSP                        ////
2602
////                                                              ////
2603
////                                                              ////
2604
////  To Do:                                                      ////
2605
////   -                                                          ////
2606
////                                                              ////
2607
////  Author(s):                                                  ////
2608
////      - Michael Unneback, unneback@opencores.org              ////
2609
////        ORSoC AB                                              ////
2610
////                                                              ////
2611
//////////////////////////////////////////////////////////////////////
2612
////                                                              ////
2613
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2614
////                                                              ////
2615
//// This source file may be used and distributed without         ////
2616
//// restriction provided that this copyright statement is not    ////
2617
//// removed from the file and that any derivative work contains  ////
2618
//// the original copyright notice and the associated disclaimer. ////
2619
////                                                              ////
2620
//// This source file is free software; you can redistribute it   ////
2621
//// and/or modify it under the terms of the GNU Lesser General   ////
2622
//// Public License as published by the Free Software Foundation; ////
2623
//// either version 2.1 of the License, or (at your option) any   ////
2624
//// later version.                                               ////
2625
////                                                              ////
2626
//// This source is distributed in the hope that it will be       ////
2627
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2628
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2629
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2630
//// details.                                                     ////
2631
////                                                              ////
2632
//// You should have received a copy of the GNU Lesser General    ////
2633
//// Public License along with this source; if not, download it   ////
2634
//// from http://www.opencores.org/lgpl.shtml                     ////
2635
////                                                              ////
2636
//////////////////////////////////////////////////////////////////////
2637
 
2638
// signed multiplication
2639
module vl_mults (a,b,p);
2640
parameter operand_a_width = 18;
2641
parameter operand_b_width = 18;
2642
parameter result_hi = 35;
2643
parameter result_lo = 0;
2644
input [operand_a_width-1:0] a;
2645
input [operand_b_width-1:0] b;
2646
output [result_hi:result_lo] p;
2647
wire signed [operand_a_width-1:0] ai;
2648
wire signed [operand_b_width-1:0] bi;
2649
wire signed [operand_a_width+operand_b_width-1:0] result;
2650
 
2651
    assign ai = a;
2652
    assign bi = b;
2653
    assign result = ai * bi;
2654
    assign p = result[result_hi:result_lo];
2655
 
2656
endmodule
2657
 
2658
module vl_mults18x18 (a,b,p);
2659
input [17:0] a,b;
2660
output [35:0] p;
2661
vl_mult
2662
    # (.operand_a_width(18), .operand_b_width(18))
2663
    mult0 (.a(a), .b(b), .p(p));
2664
endmodule
2665
 
2666
// unsigned multiplication
2667
module vl_mult (a,b,p);
2668
parameter operand_a_width = 18;
2669
parameter operand_b_width = 18;
2670
parameter result_hi = 35;
2671
parameter result_lo = 0;
2672
input [operand_a_width-1:0] a;
2673
input [operand_b_width-1:0] b;
2674
output [result_hi:result_hi] p;
2675
 
2676
wire [operand_a_width+operand_b_width-1:0] result;
2677
 
2678
    assign result = a * b;
2679
    assign p = result[result_hi:result_lo];
2680
 
2681
endmodule
2682
 
2683
// shift unit
2684
// supporting the following shift functions
2685
//   SLL
2686
//   SRL
2687
//   SRA
2688
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
2689
module vl_shift_unit_32( din, s, dout, opcode);
2690
input [31:0] din; // data in operand
2691
input [4:0] s; // shift operand
2692
input [1:0] opcode;
2693
output [31:0] dout;
2694
 
2695
parameter opcode_sll = 2'b00;
2696
//parameter opcode_srl = 2'b01;
2697
parameter opcode_sra = 2'b10;
2698
//parameter opcode_ror = 2'b11;
2699
 
2700
wire sll, sra;
2701
assign sll = opcode == opcode_sll;
2702
assign sra = opcode == opcode_sra;
2703
 
2704
wire [15:1] s1;
2705
wire [3:0] sign;
2706
wire [7:0] tmp [0:3];
2707
 
2708
// first stage is multiplier based
2709
// shift operand as fractional 8.7
2710
assign s1[15] = sll & s[2:0]==3'd7;
2711
assign s1[14] = sll & s[2:0]==3'd6;
2712
assign s1[13] = sll & s[2:0]==3'd5;
2713
assign s1[12] = sll & s[2:0]==3'd4;
2714
assign s1[11] = sll & s[2:0]==3'd3;
2715
assign s1[10] = sll & s[2:0]==3'd2;
2716
assign s1[ 9] = sll & s[2:0]==3'd1;
2717
assign s1[ 8] = s[2:0]==3'd0;
2718
assign s1[ 7] = !sll & s[2:0]==3'd1;
2719
assign s1[ 6] = !sll & s[2:0]==3'd2;
2720
assign s1[ 5] = !sll & s[2:0]==3'd3;
2721
assign s1[ 4] = !sll & s[2:0]==3'd4;
2722
assign s1[ 3] = !sll & s[2:0]==3'd5;
2723
assign s1[ 2] = !sll & s[2:0]==3'd6;
2724
assign s1[ 1] = !sll & s[2:0]==3'd7;
2725
 
2726
assign sign[3] = din[31] & sra;
2727
assign sign[2] = sign[3] & (&din[31:24]);
2728
assign sign[1] = sign[2] & (&din[23:16]);
2729
assign sign[0] = sign[1] & (&din[15:8]);</