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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
66
`ifdef SIM_GBUF
67
assign o=i;
68
`else
69
gbuf gbuf_i0 ( .CLK(i), .GL(o));
70
`endif
71
endmodule
72
`else
73
`ifdef ALTERA
74 21 unneback
//altera
75 6 unneback
`else
76
 
77
`timescale 1 ns/100 ps
78
module vl_gbuf ( i, o);
79
input i;
80
output o;
81
assign o = i;
82
endmodule
83
`endif // ALTERA
84
`endif //ACTEL
85
 
86
// sync reset
87 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
88 6 unneback
// output active high global reset sync with two DFFs 
89
`timescale 1 ns/100 ps
90
module vl_sync_rst ( rst_n_i, rst_o, clk);
91
input rst_n_i, clk;
92
output rst_o;
93 18 unneback
reg [1:0] tmp;
94 6 unneback
always @ (posedge clk or negedge rst_n_i)
95
if (!rst_n_i)
96 17 unneback
        tmp <= 2'b11;
97 6 unneback
else
98 17 unneback
        tmp <= {1'b0,tmp[0]};
99
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
100 6 unneback
endmodule
101
 
102
// vl_pll
103
`ifdef ACTEL
104 17 unneback
`timescale 1 ps/1 ps
105 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
106
parameter index = 0;
107
parameter number_of_clk = 1;
108 17 unneback
parameter period_time_0 = 20000;
109
parameter period_time_1 = 20000;
110
parameter period_time_2 = 20000;
111
parameter lock_delay = 2000000;
112 6 unneback
input clk_i, rst_n_i;
113
output lock;
114
output reg [0:number_of_clk-1] clk_o;
115
output [0:number_of_clk-1] rst_o;
116
 
117
`ifdef SIM_PLL
118
 
119
always
120
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
121
 
122
generate if (number_of_clk > 1)
123
always
124
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
125
endgenerate
126
 
127
generate if (number_of_clk > 2)
128
always
129
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
130
endgenerate
131
 
132
genvar i;
133
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
134
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
135
end
136
endgenerate
137
 
138
assign #lock_delay lock = rst_n_i;
139
 
140
endmodule
141
`else
142
generate if (number_of_clk==1 & index==0) begin
143
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==1 & index==1) begin
147
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
148
end
149
endgenerate // index==1
150
generate if (number_of_clk==1 & index==2) begin
151
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
152
end
153
endgenerate // index==2
154
generate if (number_of_clk==1 & index==3) begin
155
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
156
end
157
endgenerate // index==0
158
 
159
generate if (number_of_clk==2 & index==0) begin
160
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
161
end
162
endgenerate // index==0
163
generate if (number_of_clk==2 & index==1) begin
164
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
165
end
166
endgenerate // index==1
167
generate if (number_of_clk==2 & index==2) begin
168
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
169
end
170
endgenerate // index==2
171
generate if (number_of_clk==2 & index==3) begin
172
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
173
end
174
endgenerate // index==0
175
 
176
generate if (number_of_clk==3 & index==0) begin
177
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
178
end
179
endgenerate // index==0
180
generate if (number_of_clk==3 & index==1) begin
181
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
182
end
183
endgenerate // index==1
184
generate if (number_of_clk==3 & index==2) begin
185
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
186
end
187
endgenerate // index==2
188
generate if (number_of_clk==3 & index==3) begin
189
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
190
end
191
endgenerate // index==0
192
 
193
genvar i;
194
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
195
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
196
end
197
endgenerate
198
endmodule
199
`endif
200
 
201
`else
202
 
203
`ifdef ALTERA
204
 
205
`else
206
 
207
// generic PLL
208 17 unneback
`timescale 1 ps/1 ps
209 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
210
parameter index = 0;
211
parameter number_of_clk = 1;
212 17 unneback
parameter period_time_0 = 20000;
213
parameter period_time_1 = 20000;
214
parameter period_time_2 = 20000;
215 6 unneback
parameter lock_delay = 2000;
216
input clk_i, rst_n_i;
217
output lock;
218
output reg [0:number_of_clk-1] clk_o;
219
output [0:number_of_clk-1] rst_o;
220
 
221
always
222
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
223
 
224
generate if (number_of_clk > 1)
225
always
226
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
227
endgenerate
228
 
229
generate if (number_of_clk > 2)
230
always
231
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
232
endgenerate
233
 
234
genvar i;
235
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
236
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
237
end
238
endgenerate
239
 
240
assign #lock_delay lock = rst_n_i;
241
 
242
endmodule
243
 
244
`endif //altera
245 17 unneback
`endif //actel
246
//////////////////////////////////////////////////////////////////////
247 6 unneback
////                                                              ////
248
////  Versatile library, registers                                ////
249
////                                                              ////
250
////  Description                                                 ////
251
////  Different type of registers                                 ////
252
////                                                              ////
253
////                                                              ////
254
////  To Do:                                                      ////
255
////   - add more different registers                             ////
256
////                                                              ////
257
////  Author(s):                                                  ////
258
////      - Michael Unneback, unneback@opencores.org              ////
259
////        ORSoC AB                                              ////
260
////                                                              ////
261
//////////////////////////////////////////////////////////////////////
262
////                                                              ////
263
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
264
////                                                              ////
265
//// This source file may be used and distributed without         ////
266
//// restriction provided that this copyright statement is not    ////
267
//// removed from the file and that any derivative work contains  ////
268
//// the original copyright notice and the associated disclaimer. ////
269
////                                                              ////
270
//// This source file is free software; you can redistribute it   ////
271
//// and/or modify it under the terms of the GNU Lesser General   ////
272
//// Public License as published by the Free Software Foundation; ////
273
//// either version 2.1 of the License, or (at your option) any   ////
274
//// later version.                                               ////
275
////                                                              ////
276
//// This source is distributed in the hope that it will be       ////
277
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
278
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
279
//// PURPOSE.  See the GNU Lesser General Public License for more ////
280
//// details.                                                     ////
281
////                                                              ////
282
//// You should have received a copy of the GNU Lesser General    ////
283
//// Public License along with this source; if not, download it   ////
284
//// from http://www.opencores.org/lgpl.shtml                     ////
285
////                                                              ////
286
//////////////////////////////////////////////////////////////////////
287
 
288 18 unneback
module vl_dff ( d, q, clk, rst);
289 6 unneback
 
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
 
293
        input [width-1:0] d;
294
        input clk, rst;
295
        output reg [width-1:0] q;
296
 
297
        always @ (posedge clk or posedge rst)
298
        if (rst)
299
                q <= reset_value;
300
        else
301
                q <= d;
302
 
303
endmodule
304
 
305 18 unneback
module vl_dff_array ( d, q, clk, rst);
306 6 unneback
 
307
        parameter width = 1;
308
        parameter depth = 2;
309
        parameter reset_value = 1'b0;
310
 
311
        input [width-1:0] d;
312
        input clk, rst;
313
        output [width-1:0] q;
314
        reg  [0:depth-1] q_tmp [width-1:0];
315
        integer i;
316
        always @ (posedge clk or posedge rst)
317
        if (rst) begin
318
            for (i=0;i<depth;i=i+1)
319
                q_tmp[i] <= {width{reset_value}};
320
        end else begin
321
            q_tmp[0] <= d;
322
            for (i=1;i<depth;i=i+1)
323
                q_tmp[i] <= q_tmp[i-1];
324
        end
325
 
326
    assign q = q_tmp[depth-1];
327
 
328
endmodule
329
 
330 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
331 6 unneback
 
332
        parameter width = 1;
333
        parameter reset_value = 0;
334
 
335
        input [width-1:0] d;
336
        input ce, clk, rst;
337
        output reg [width-1:0] q;
338
 
339
        always @ (posedge clk or posedge rst)
340
        if (rst)
341
                q <= reset_value;
342
        else
343
                if (ce)
344
                        q <= d;
345
 
346
endmodule
347
 
348 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
349 8 unneback
 
350
        parameter width = 1;
351
        parameter reset_value = 0;
352
 
353
        input [width-1:0] d;
354 10 unneback
        input ce, clear, clk, rst;
355 8 unneback
        output reg [width-1:0] q;
356
 
357
        always @ (posedge clk or posedge rst)
358
        if (rst)
359
            q <= reset_value;
360
        else
361
            if (ce)
362
                if (clear)
363
                    q <= {width{1'b0}};
364
                else
365
                    q <= d;
366
 
367
endmodule
368
 
369 6 unneback
`ifdef ALTERA
370
// megafunction wizard: %LPM_FF%
371
// GENERATION: STANDARD
372
// VERSION: WM1.0
373
// MODULE: lpm_ff 
374
 
375
// ============================================================
376
// File Name: dff_sr.v
377
// Megafunction Name(s):
378
//                      lpm_ff
379
//
380
// Simulation Library Files(s):
381
//                      lpm
382
// ============================================================
383
// ************************************************************
384
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
385
//
386
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
387
// ************************************************************
388
 
389
 
390
//Copyright (C) 1991-2010 Altera Corporation
391
//Your use of Altera Corporation's design tools, logic functions 
392
//and other software and tools, and its AMPP partner logic 
393
//functions, and any output files from any of the foregoing 
394
//(including device programming or simulation files), and any 
395
//associated documentation or information are expressly subject 
396
//to the terms and conditions of the Altera Program License 
397
//Subscription Agreement, Altera MegaCore Function License 
398
//Agreement, or other applicable license agreement, including, 
399
//without limitation, that your use is for the sole purpose of 
400
//programming logic devices manufactured by Altera and sold by 
401
//Altera or its authorized distributors.  Please refer to the 
402
//applicable agreement for further details.
403
 
404
 
405
// synopsys translate_off
406
`timescale 1 ps / 1 ps
407
// synopsys translate_on
408 18 unneback
module vl_dff_sr (
409 6 unneback
        aclr,
410
        aset,
411
        clock,
412
        data,
413
        q);
414
 
415
        input     aclr;
416
        input     aset;
417
        input     clock;
418
        input     data;
419
        output    q;
420
 
421
        wire [0:0] sub_wire0;
422
        wire [0:0] sub_wire1 = sub_wire0[0:0];
423
        wire  q = sub_wire1;
424
        wire  sub_wire2 = data;
425
        wire  sub_wire3 = sub_wire2;
426
 
427
        lpm_ff  lpm_ff_component (
428
                                .aclr (aclr),
429
                                .clock (clock),
430
                                .data (sub_wire3),
431
                                .aset (aset),
432
                                .q (sub_wire0)
433
                                // synopsys translate_off
434
                                ,
435
                                .aload (),
436
                                .enable (),
437
                                .sclr (),
438
                                .sload (),
439
                                .sset ()
440
                                // synopsys translate_on
441
                                );
442
        defparam
443
                lpm_ff_component.lpm_fftype = "DFF",
444
                lpm_ff_component.lpm_type = "LPM_FF",
445
                lpm_ff_component.lpm_width = 1;
446
 
447
 
448
endmodule
449
 
450
// ============================================================
451
// CNX file retrieval info
452
// ============================================================
453
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
454
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
455
// Retrieval info: PRIVATE: ASET NUMERIC "1"
456
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
457
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
458
// Retrieval info: PRIVATE: DFF NUMERIC "1"
459
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
460
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
461
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
462
// Retrieval info: PRIVATE: SSET NUMERIC "0"
463
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
464
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
465
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
466
// Retrieval info: PRIVATE: nBit NUMERIC "1"
467
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
468
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
469
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
470
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
471
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
472
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
473
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
474
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
475
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
476
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
477
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
478
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
479
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
480
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
481
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
482
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
483
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
484
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
485
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
486
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
487
// Retrieval info: LIB_FILE: lpm
488
 
489
 
490
`else
491
 
492
 
493 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
494 6 unneback
 
495
    input         aclr;
496
    input         aset;
497
    input         clock;
498
    input         data;
499
    output reg    q;
500
 
501
   always @ (posedge clock or posedge aclr or posedge aset)
502
     if (aclr)
503
       q <= 1'b0;
504
     else if (aset)
505
       q <= 1'b1;
506
     else
507
       q <= data;
508
 
509
endmodule
510
 
511
`endif
512
 
513
// LATCH
514
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
515
`ifdef ALTERA
516 18 unneback
module vl_latch ( d, le, q, clk);
517 6 unneback
input d, le;
518
output q;
519
input clk;
520
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
521
endmodule
522
`else
523
module latch ( d, le, q, clk);
524
input d, le;
525
output q;
526
input clk;/*
527
   always @ (posedge direction_set or posedge direction_clr)
528
     if (direction_clr)
529
       direction <= going_empty;
530
     else
531
       direction <= going_full;*/
532
endmodule
533 15 unneback
`endif
534
 
535 18 unneback
module vl_shreg ( d, q, clk, rst);
536 17 unneback
parameter depth = 10;
537
input d;
538
output q;
539
input clk, rst;
540
 
541
reg [1:depth] dffs;
542
 
543
always @ (posedge clk or posedge rst)
544
if (rst)
545
    dffs <= {depth{1'b0}};
546
else
547
    dffs <= {d,dffs[1:depth-1]};
548
assign q = dffs[depth];
549
endmodule
550
 
551 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
552 17 unneback
parameter depth = 10;
553
input d, ce;
554
output q;
555
input clk, rst;
556
 
557
reg [1:depth] dffs;
558
 
559
always @ (posedge clk or posedge rst)
560
if (rst)
561
    dffs <= {depth{1'b0}};
562
else
563
    if (ce)
564
        dffs <= {d,dffs[1:depth-1]};
565
assign q = dffs[depth];
566
endmodule
567
 
568 18 unneback
module vl_delay ( d, q, clk, rst);
569 15 unneback
parameter depth = 10;
570
input d;
571
output q;
572
input clk, rst;
573
 
574
reg [1:depth] dffs;
575
 
576
always @ (posedge clk or posedge rst)
577
if (rst)
578
    dffs <= {depth{1'b0}};
579
else
580
    dffs <= {d,dffs[1:depth-1]};
581
assign q = dffs[depth];
582 17 unneback
endmodule
583
 
584 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
585 17 unneback
parameter depth = 10;
586
input d;
587
output q, emptyflag;
588
input clk, rst;
589
 
590
reg [1:depth] dffs;
591
 
592
always @ (posedge clk or posedge rst)
593
if (rst)
594
    dffs <= {depth{1'b0}};
595
else
596
    dffs <= {d,dffs[1:depth-1]};
597
assign q = dffs[depth];
598
assign emptyflag = !(|dffs);
599
endmodule
600
//////////////////////////////////////////////////////////////////////
601 6 unneback
////                                                              ////
602 18 unneback
////  Logic functions                                             ////
603
////                                                              ////
604
////  Description                                                 ////
605
////  Logic functions such as multiplexers                        ////
606
////                                                              ////
607
////                                                              ////
608
////  To Do:                                                      ////
609
////   -                                                          ////
610
////                                                              ////
611
////  Author(s):                                                  ////
612
////      - Michael Unneback, unneback@opencores.org              ////
613
////        ORSoC AB                                              ////
614
////                                                              ////
615
//////////////////////////////////////////////////////////////////////
616
////                                                              ////
617
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
618
////                                                              ////
619
//// This source file may be used and distributed without         ////
620
//// restriction provided that this copyright statement is not    ////
621
//// removed from the file and that any derivative work contains  ////
622
//// the original copyright notice and the associated disclaimer. ////
623
////                                                              ////
624
//// This source file is free software; you can redistribute it   ////
625
//// and/or modify it under the terms of the GNU Lesser General   ////
626
//// Public License as published by the Free Software Foundation; ////
627
//// either version 2.1 of the License, or (at your option) any   ////
628
//// later version.                                               ////
629
////                                                              ////
630
//// This source is distributed in the hope that it will be       ////
631
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
632
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
633
//// PURPOSE.  See the GNU Lesser General Public License for more ////
634
//// details.                                                     ////
635
////                                                              ////
636
//// You should have received a copy of the GNU Lesser General    ////
637
//// Public License along with this source; if not, download it   ////
638
//// from http://www.opencores.org/lgpl.shtml                     ////
639
////                                                              ////
640
//////////////////////////////////////////////////////////////////////
641
 
642
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
643
 
644
parameter width = 32;
645
parameter nr_of_ports = 4;
646
input [width-1:0] a3, a2, a1, a0;
647
input [nr_of_ports-1:0] sel;
648 22 unneback
output [width-1:0] dout;
649 18 unneback
 
650 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
651 18 unneback
integer i;
652
 
653
// and
654
assign tmp[0] = {width{sel[0]}} & a0;
655
assign tmp[1] = {width{sel[1]}} & a1;
656
assign tmp[2] = {width{sel[2]}} & a2;
657
assign tmp[3] = {width{sel[3]}} & a3;
658
 
659
// or
660
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
661
 
662
endmodule
663
 
664
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
665
 
666
parameter width = 32;
667
parameter nr_of_ports = 5;
668
input [width-1:0] a4, a3, a2, a1, a0;
669
input [nr_of_ports-1:0] sel;
670 22 unneback
output [width-1:0] dout;
671 18 unneback
 
672 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
673 18 unneback
integer i;
674
 
675
// and
676
assign tmp[0] = {width{sel[0]}} & a0;
677
assign tmp[1] = {width{sel[1]}} & a1;
678
assign tmp[2] = {width{sel[2]}} & a2;
679
assign tmp[3] = {width{sel[3]}} & a3;
680
assign tmp[4] = {width{sel[4]}} & a4;
681
 
682
// or
683
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
684
 
685
endmodule
686
 
687
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
688
 
689
parameter width = 32;
690
parameter nr_of_ports = 6;
691
input [width-1:0] a5, a4, a3, a2, a1, a0;
692
input [nr_of_ports-1:0] sel;
693 22 unneback
output [width-1:0] dout;
694 18 unneback
 
695 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
696 18 unneback
integer i;
697
 
698
// and
699
assign tmp[0] = {width{sel[0]}} & a0;
700
assign tmp[1] = {width{sel[1]}} & a1;
701
assign tmp[2] = {width{sel[2]}} & a2;
702
assign tmp[3] = {width{sel[3]}} & a3;
703
assign tmp[4] = {width{sel[4]}} & a4;
704
assign tmp[5] = {width{sel[5]}} & a5;
705
 
706
// or
707
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
708
 
709
endmodule
710
//////////////////////////////////////////////////////////////////////
711
////                                                              ////
712 6 unneback
////  Versatile counter                                           ////
713
////                                                              ////
714
////  Description                                                 ////
715
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
716
////  counter                                                     ////
717
////                                                              ////
718
////  To Do:                                                      ////
719
////   - add LFSR with more taps                                  ////
720
////                                                              ////
721
////  Author(s):                                                  ////
722
////      - Michael Unneback, unneback@opencores.org              ////
723
////        ORSoC AB                                              ////
724
////                                                              ////
725
//////////////////////////////////////////////////////////////////////
726
////                                                              ////
727
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
728
////                                                              ////
729
//// This source file may be used and distributed without         ////
730
//// restriction provided that this copyright statement is not    ////
731
//// removed from the file and that any derivative work contains  ////
732
//// the original copyright notice and the associated disclaimer. ////
733
////                                                              ////
734
//// This source file is free software; you can redistribute it   ////
735
//// and/or modify it under the terms of the GNU Lesser General   ////
736
//// Public License as published by the Free Software Foundation; ////
737
//// either version 2.1 of the License, or (at your option) any   ////
738
//// later version.                                               ////
739
////                                                              ////
740
//// This source is distributed in the hope that it will be       ////
741
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
742
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
743
//// PURPOSE.  See the GNU Lesser General Public License for more ////
744
//// details.                                                     ////
745
////                                                              ////
746
//// You should have received a copy of the GNU Lesser General    ////
747
//// Public License along with this source; if not, download it   ////
748
//// from http://www.opencores.org/lgpl.shtml                     ////
749
////                                                              ////
750
//////////////////////////////////////////////////////////////////////
751
 
752
// binary counter
753 22 unneback
module vl_cnt_bin ( q, rst, clk);
754
 
755
   parameter length = 4;
756
   output [length:1] q;
757
   input rst;
758
   input clk;
759
 
760
   parameter clear_value = 0;
761
   parameter set_value = 1;
762
   parameter wrap_value = 0;
763
   parameter level1_value = 15;
764
 
765
   reg  [length:1] qi;
766
   wire [length:1] q_next;
767
   assign q_next = qi + {{length-1{1'b0}},1'b1};
768
 
769
   always @ (posedge clk or posedge rst)
770
     if (rst)
771
       qi <= {length{1'b0}};
772
     else
773
       qi <= q_next;
774
 
775
   assign q = qi;
776
 
777
endmodule
778
//////////////////////////////////////////////////////////////////////
779
////                                                              ////
780
////  Versatile counter                                           ////
781
////                                                              ////
782
////  Description                                                 ////
783
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
784
////  counter                                                     ////
785
////                                                              ////
786
////  To Do:                                                      ////
787
////   - add LFSR with more taps                                  ////
788
////                                                              ////
789
////  Author(s):                                                  ////
790
////      - Michael Unneback, unneback@opencores.org              ////
791
////        ORSoC AB                                              ////
792
////                                                              ////
793
//////////////////////////////////////////////////////////////////////
794
////                                                              ////
795
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
796
////                                                              ////
797
//// This source file may be used and distributed without         ////
798
//// restriction provided that this copyright statement is not    ////
799
//// removed from the file and that any derivative work contains  ////
800
//// the original copyright notice and the associated disclaimer. ////
801
////                                                              ////
802
//// This source file is free software; you can redistribute it   ////
803
//// and/or modify it under the terms of the GNU Lesser General   ////
804
//// Public License as published by the Free Software Foundation; ////
805
//// either version 2.1 of the License, or (at your option) any   ////
806
//// later version.                                               ////
807
////                                                              ////
808
//// This source is distributed in the hope that it will be       ////
809
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
810
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
811
//// PURPOSE.  See the GNU Lesser General Public License for more ////
812
//// details.                                                     ////
813
////                                                              ////
814
//// You should have received a copy of the GNU Lesser General    ////
815
//// Public License along with this source; if not, download it   ////
816
//// from http://www.opencores.org/lgpl.shtml                     ////
817
////                                                              ////
818
//////////////////////////////////////////////////////////////////////
819
 
820
// binary counter
821
module vl_cnt_bin_clear ( clear, q, rst, clk);
822
 
823
   parameter length = 4;
824
   input clear;
825
   output [length:1] q;
826
   input rst;
827
   input clk;
828
 
829
   parameter clear_value = 0;
830
   parameter set_value = 1;
831
   parameter wrap_value = 0;
832
   parameter level1_value = 15;
833
 
834
   reg  [length:1] qi;
835
   wire [length:1] q_next;
836
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
837
 
838
   always @ (posedge clk or posedge rst)
839
     if (rst)
840
       qi <= {length{1'b0}};
841
     else
842
       qi <= q_next;
843
 
844
   assign q = qi;
845
 
846
endmodule
847
//////////////////////////////////////////////////////////////////////
848
////                                                              ////
849
////  Versatile counter                                           ////
850
////                                                              ////
851
////  Description                                                 ////
852
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
853
////  counter                                                     ////
854
////                                                              ////
855
////  To Do:                                                      ////
856
////   - add LFSR with more taps                                  ////
857
////                                                              ////
858
////  Author(s):                                                  ////
859
////      - Michael Unneback, unneback@opencores.org              ////
860
////        ORSoC AB                                              ////
861
////                                                              ////
862
//////////////////////////////////////////////////////////////////////
863
////                                                              ////
864
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
865
////                                                              ////
866
//// This source file may be used and distributed without         ////
867
//// restriction provided that this copyright statement is not    ////
868
//// removed from the file and that any derivative work contains  ////
869
//// the original copyright notice and the associated disclaimer. ////
870
////                                                              ////
871
//// This source file is free software; you can redistribute it   ////
872
//// and/or modify it under the terms of the GNU Lesser General   ////
873
//// Public License as published by the Free Software Foundation; ////
874
//// either version 2.1 of the License, or (at your option) any   ////
875
//// later version.                                               ////
876
////                                                              ////
877
//// This source is distributed in the hope that it will be       ////
878
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
879
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
880
//// PURPOSE.  See the GNU Lesser General Public License for more ////
881
//// details.                                                     ////
882
////                                                              ////
883
//// You should have received a copy of the GNU Lesser General    ////
884
//// Public License along with this source; if not, download it   ////
885
//// from http://www.opencores.org/lgpl.shtml                     ////
886
////                                                              ////
887
//////////////////////////////////////////////////////////////////////
888
 
889
// binary counter
890 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
891 6 unneback
 
892
   parameter length = 4;
893
   input cke;
894
   output [length:1] q;
895
   input rst;
896
   input clk;
897
 
898
   parameter clear_value = 0;
899
   parameter set_value = 1;
900
   parameter wrap_value = 0;
901
   parameter level1_value = 15;
902
 
903
   reg  [length:1] qi;
904
   wire [length:1] q_next;
905
   assign q_next = qi + {{length-1{1'b0}},1'b1};
906
 
907
   always @ (posedge clk or posedge rst)
908
     if (rst)
909
       qi <= {length{1'b0}};
910
     else
911
     if (cke)
912
       qi <= q_next;
913
 
914
   assign q = qi;
915
 
916
endmodule
917
//////////////////////////////////////////////////////////////////////
918
////                                                              ////
919
////  Versatile counter                                           ////
920
////                                                              ////
921
////  Description                                                 ////
922
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
923
////  counter                                                     ////
924
////                                                              ////
925
////  To Do:                                                      ////
926
////   - add LFSR with more taps                                  ////
927
////                                                              ////
928
////  Author(s):                                                  ////
929
////      - Michael Unneback, unneback@opencores.org              ////
930
////        ORSoC AB                                              ////
931
////                                                              ////
932
//////////////////////////////////////////////////////////////////////
933
////                                                              ////
934
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
935
////                                                              ////
936
//// This source file may be used and distributed without         ////
937
//// restriction provided that this copyright statement is not    ////
938
//// removed from the file and that any derivative work contains  ////
939
//// the original copyright notice and the associated disclaimer. ////
940
////                                                              ////
941
//// This source file is free software; you can redistribute it   ////
942
//// and/or modify it under the terms of the GNU Lesser General   ////
943
//// Public License as published by the Free Software Foundation; ////
944
//// either version 2.1 of the License, or (at your option) any   ////
945
//// later version.                                               ////
946
////                                                              ////
947
//// This source is distributed in the hope that it will be       ////
948
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
949
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
950
//// PURPOSE.  See the GNU Lesser General Public License for more ////
951
//// details.                                                     ////
952
////                                                              ////
953
//// You should have received a copy of the GNU Lesser General    ////
954
//// Public License along with this source; if not, download it   ////
955
//// from http://www.opencores.org/lgpl.shtml                     ////
956
////                                                              ////
957
//////////////////////////////////////////////////////////////////////
958
 
959
// binary counter
960 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
961 6 unneback
 
962
   parameter length = 4;
963
   input clear;
964
   input cke;
965
   output [length:1] q;
966
   input rst;
967
   input clk;
968
 
969
   parameter clear_value = 0;
970
   parameter set_value = 1;
971
   parameter wrap_value = 0;
972
   parameter level1_value = 15;
973
 
974
   reg  [length:1] qi;
975
   wire [length:1] q_next;
976
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
977
 
978
   always @ (posedge clk or posedge rst)
979
     if (rst)
980
       qi <= {length{1'b0}};
981
     else
982
     if (cke)
983
       qi <= q_next;
984
 
985
   assign q = qi;
986
 
987
endmodule
988
//////////////////////////////////////////////////////////////////////
989
////                                                              ////
990
////  Versatile counter                                           ////
991
////                                                              ////
992
////  Description                                                 ////
993
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
994
////  counter                                                     ////
995
////                                                              ////
996
////  To Do:                                                      ////
997
////   - add LFSR with more taps                                  ////
998
////                                                              ////
999
////  Author(s):                                                  ////
1000
////      - Michael Unneback, unneback@opencores.org              ////
1001
////        ORSoC AB                                              ////
1002
////                                                              ////
1003
//////////////////////////////////////////////////////////////////////
1004
////                                                              ////
1005
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1006
////                                                              ////
1007
//// This source file may be used and distributed without         ////
1008
//// restriction provided that this copyright statement is not    ////
1009
//// removed from the file and that any derivative work contains  ////
1010
//// the original copyright notice and the associated disclaimer. ////
1011
////                                                              ////
1012
//// This source file is free software; you can redistribute it   ////
1013
//// and/or modify it under the terms of the GNU Lesser General   ////
1014
//// Public License as published by the Free Software Foundation; ////
1015
//// either version 2.1 of the License, or (at your option) any   ////
1016
//// later version.                                               ////
1017
////                                                              ////
1018
//// This source is distributed in the hope that it will be       ////
1019
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1020
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1021
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1022
//// details.                                                     ////
1023
////                                                              ////
1024
//// You should have received a copy of the GNU Lesser General    ////
1025
//// Public License along with this source; if not, download it   ////
1026
//// from http://www.opencores.org/lgpl.shtml                     ////
1027
////                                                              ////
1028
//////////////////////////////////////////////////////////////////////
1029
 
1030
// binary counter
1031 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
1032 6 unneback
 
1033
   parameter length = 4;
1034
   input clear;
1035
   input set;
1036
   input cke;
1037
   input rew;
1038
   output [length:1] q;
1039
   input rst;
1040
   input clk;
1041
 
1042
   parameter clear_value = 0;
1043
   parameter set_value = 1;
1044
   parameter wrap_value = 0;
1045
   parameter level1_value = 15;
1046
 
1047
   reg  [length:1] qi;
1048
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1049
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1050
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1051
   assign q_next = rew ? q_next_rew : q_next_fw;
1052
 
1053
   always @ (posedge clk or posedge rst)
1054
     if (rst)
1055
       qi <= {length{1'b0}};
1056
     else
1057
     if (cke)
1058
       qi <= q_next;
1059
 
1060
   assign q = qi;
1061
 
1062
endmodule
1063
//////////////////////////////////////////////////////////////////////
1064
////                                                              ////
1065
////  Versatile counter                                           ////
1066
////                                                              ////
1067
////  Description                                                 ////
1068
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1069
////  counter                                                     ////
1070
////                                                              ////
1071
////  To Do:                                                      ////
1072
////   - add LFSR with more taps                                  ////
1073
////                                                              ////
1074
////  Author(s):                                                  ////
1075
////      - Michael Unneback, unneback@opencores.org              ////
1076
////        ORSoC AB                                              ////
1077
////                                                              ////
1078
//////////////////////////////////////////////////////////////////////
1079
////                                                              ////
1080
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1081
////                                                              ////
1082
//// This source file may be used and distributed without         ////
1083
//// restriction provided that this copyright statement is not    ////
1084
//// removed from the file and that any derivative work contains  ////
1085
//// the original copyright notice and the associated disclaimer. ////
1086
////                                                              ////
1087
//// This source file is free software; you can redistribute it   ////
1088
//// and/or modify it under the terms of the GNU Lesser General   ////
1089
//// Public License as published by the Free Software Foundation; ////
1090
//// either version 2.1 of the License, or (at your option) any   ////
1091
//// later version.                                               ////
1092
////                                                              ////
1093
//// This source is distributed in the hope that it will be       ////
1094
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1095
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1096
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1097
//// details.                                                     ////
1098
////                                                              ////
1099
//// You should have received a copy of the GNU Lesser General    ////
1100
//// Public License along with this source; if not, download it   ////
1101
//// from http://www.opencores.org/lgpl.shtml                     ////
1102
////                                                              ////
1103
//////////////////////////////////////////////////////////////////////
1104
 
1105
// binary counter
1106 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1107 6 unneback
 
1108
   parameter length = 4;
1109
   input cke;
1110
   input rew;
1111
   output reg level1;
1112
   input rst;
1113
   input clk;
1114
 
1115
   parameter clear_value = 0;
1116
   parameter set_value = 1;
1117
   parameter wrap_value = 1;
1118
   parameter level1_value = 15;
1119
 
1120
   reg  [length:1] qi;
1121
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1122
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1123
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1124
   assign q_next = rew ? q_next_rew : q_next_fw;
1125
 
1126
   always @ (posedge clk or posedge rst)
1127
     if (rst)
1128
       qi <= {length{1'b0}};
1129
     else
1130
     if (cke)
1131
       qi <= q_next;
1132
 
1133
 
1134
 
1135
    always @ (posedge clk or posedge rst)
1136
    if (rst)
1137
        level1 <= 1'b0;
1138
    else
1139
    if (cke)
1140
    if (q_next == level1_value)
1141
        level1 <= 1'b1;
1142
    else if (qi == level1_value & rew)
1143
        level1 <= 1'b0;
1144
endmodule
1145
//////////////////////////////////////////////////////////////////////
1146
////                                                              ////
1147
////  Versatile counter                                           ////
1148
////                                                              ////
1149
////  Description                                                 ////
1150
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1151
////  counter                                                     ////
1152
////                                                              ////
1153
////  To Do:                                                      ////
1154
////   - add LFSR with more taps                                  ////
1155
////                                                              ////
1156
////  Author(s):                                                  ////
1157
////      - Michael Unneback, unneback@opencores.org              ////
1158
////        ORSoC AB                                              ////
1159
////                                                              ////
1160
//////////////////////////////////////////////////////////////////////
1161
////                                                              ////
1162
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1163
////                                                              ////
1164
//// This source file may be used and distributed without         ////
1165
//// restriction provided that this copyright statement is not    ////
1166
//// removed from the file and that any derivative work contains  ////
1167
//// the original copyright notice and the associated disclaimer. ////
1168
////                                                              ////
1169
//// This source file is free software; you can redistribute it   ////
1170
//// and/or modify it under the terms of the GNU Lesser General   ////
1171
//// Public License as published by the Free Software Foundation; ////
1172
//// either version 2.1 of the License, or (at your option) any   ////
1173
//// later version.                                               ////
1174
////                                                              ////
1175
//// This source is distributed in the hope that it will be       ////
1176
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1177
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1178
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1179
//// details.                                                     ////
1180
////                                                              ////
1181
//// You should have received a copy of the GNU Lesser General    ////
1182
//// Public License along with this source; if not, download it   ////
1183
//// from http://www.opencores.org/lgpl.shtml                     ////
1184
////                                                              ////
1185
//////////////////////////////////////////////////////////////////////
1186
 
1187
// LFSR counter
1188 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1189 6 unneback
 
1190
   parameter length = 4;
1191
   output reg zq;
1192
   input rst;
1193
   input clk;
1194
 
1195
   parameter clear_value = 0;
1196
   parameter set_value = 1;
1197
   parameter wrap_value = 8;
1198
   parameter level1_value = 15;
1199
 
1200
   reg  [length:1] qi;
1201
   reg lfsr_fb;
1202
   wire [length:1] q_next;
1203
   reg [32:1] polynom;
1204
   integer i;
1205
 
1206
   always @ (qi)
1207
   begin
1208
        case (length)
1209
         2: polynom = 32'b11;                               // 0x3
1210
         3: polynom = 32'b110;                              // 0x6
1211
         4: polynom = 32'b1100;                             // 0xC
1212
         5: polynom = 32'b10100;                            // 0x14
1213
         6: polynom = 32'b110000;                           // 0x30
1214
         7: polynom = 32'b1100000;                          // 0x60
1215
         8: polynom = 32'b10111000;                         // 0xb8
1216
         9: polynom = 32'b100010000;                        // 0x110
1217
        10: polynom = 32'b1001000000;                       // 0x240
1218
        11: polynom = 32'b10100000000;                      // 0x500
1219
        12: polynom = 32'b100000101001;                     // 0x829
1220
        13: polynom = 32'b1000000001100;                    // 0x100C
1221
        14: polynom = 32'b10000000010101;                   // 0x2015
1222
        15: polynom = 32'b110000000000000;                  // 0x6000
1223
        16: polynom = 32'b1101000000001000;                 // 0xD008
1224
        17: polynom = 32'b10010000000000000;                // 0x12000
1225
        18: polynom = 32'b100000010000000000;               // 0x20400
1226
        19: polynom = 32'b1000000000000100011;              // 0x40023
1227
        20: polynom = 32'b10000010000000000000;             // 0x82000
1228
        21: polynom = 32'b101000000000000000000;            // 0x140000
1229
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1230
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1231
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1232
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1233
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1234
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1235
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1236
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1237
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1238
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1239
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1240
        default: polynom = 32'b0;
1241
        endcase
1242
        lfsr_fb = qi[length];
1243
        for (i=length-1; i>=1; i=i-1) begin
1244
            if (polynom[i])
1245
                lfsr_fb = lfsr_fb  ~^ qi[i];
1246
        end
1247
    end
1248
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1249
 
1250
   always @ (posedge clk or posedge rst)
1251
     if (rst)
1252
       qi <= {length{1'b0}};
1253
     else
1254
       qi <= q_next;
1255
 
1256
 
1257
 
1258
   always @ (posedge clk or posedge rst)
1259
     if (rst)
1260
       zq <= 1'b1;
1261
     else
1262
       zq <= q_next == {length{1'b0}};
1263
endmodule
1264
//////////////////////////////////////////////////////////////////////
1265
////                                                              ////
1266
////  Versatile counter                                           ////
1267
////                                                              ////
1268
////  Description                                                 ////
1269
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1270
////  counter                                                     ////
1271
////                                                              ////
1272
////  To Do:                                                      ////
1273
////   - add LFSR with more taps                                  ////
1274
////                                                              ////
1275
////  Author(s):                                                  ////
1276
////      - Michael Unneback, unneback@opencores.org              ////
1277
////        ORSoC AB                                              ////
1278
////                                                              ////
1279
//////////////////////////////////////////////////////////////////////
1280
////                                                              ////
1281
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1282
////                                                              ////
1283
//// This source file may be used and distributed without         ////
1284
//// restriction provided that this copyright statement is not    ////
1285
//// removed from the file and that any derivative work contains  ////
1286
//// the original copyright notice and the associated disclaimer. ////
1287
////                                                              ////
1288
//// This source file is free software; you can redistribute it   ////
1289
//// and/or modify it under the terms of the GNU Lesser General   ////
1290
//// Public License as published by the Free Software Foundation; ////
1291
//// either version 2.1 of the License, or (at your option) any   ////
1292
//// later version.                                               ////
1293
////                                                              ////
1294
//// This source is distributed in the hope that it will be       ////
1295
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1296
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1297
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1298
//// details.                                                     ////
1299
////                                                              ////
1300
//// You should have received a copy of the GNU Lesser General    ////
1301
//// Public License along with this source; if not, download it   ////
1302
//// from http://www.opencores.org/lgpl.shtml                     ////
1303
////                                                              ////
1304
//////////////////////////////////////////////////////////////////////
1305
 
1306
// LFSR counter
1307 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1308 6 unneback
 
1309
   parameter length = 4;
1310
   input cke;
1311
   output reg zq;
1312
   input rst;
1313
   input clk;
1314
 
1315
   parameter clear_value = 0;
1316
   parameter set_value = 1;
1317
   parameter wrap_value = 8;
1318
   parameter level1_value = 15;
1319
 
1320
   reg  [length:1] qi;
1321
   reg lfsr_fb;
1322
   wire [length:1] q_next;
1323
   reg [32:1] polynom;
1324
   integer i;
1325
 
1326
   always @ (qi)
1327
   begin
1328
        case (length)
1329
         2: polynom = 32'b11;                               // 0x3
1330
         3: polynom = 32'b110;                              // 0x6
1331
         4: polynom = 32'b1100;                             // 0xC
1332
         5: polynom = 32'b10100;                            // 0x14
1333
         6: polynom = 32'b110000;                           // 0x30
1334
         7: polynom = 32'b1100000;                          // 0x60
1335
         8: polynom = 32'b10111000;                         // 0xb8
1336
         9: polynom = 32'b100010000;                        // 0x110
1337
        10: polynom = 32'b1001000000;                       // 0x240
1338
        11: polynom = 32'b10100000000;                      // 0x500
1339
        12: polynom = 32'b100000101001;                     // 0x829
1340
        13: polynom = 32'b1000000001100;                    // 0x100C
1341
        14: polynom = 32'b10000000010101;                   // 0x2015
1342
        15: polynom = 32'b110000000000000;                  // 0x6000
1343
        16: polynom = 32'b1101000000001000;                 // 0xD008
1344
        17: polynom = 32'b10010000000000000;                // 0x12000
1345
        18: polynom = 32'b100000010000000000;               // 0x20400
1346
        19: polynom = 32'b1000000000000100011;              // 0x40023
1347
        20: polynom = 32'b10000010000000000000;             // 0x82000
1348
        21: polynom = 32'b101000000000000000000;            // 0x140000
1349
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1350
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1351
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1352
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1353
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1354
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1355
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1356
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1357
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1358
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1359
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1360
        default: polynom = 32'b0;
1361
        endcase
1362
        lfsr_fb = qi[length];
1363
        for (i=length-1; i>=1; i=i-1) begin
1364
            if (polynom[i])
1365
                lfsr_fb = lfsr_fb  ~^ qi[i];
1366
        end
1367
    end
1368
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1369
 
1370
   always @ (posedge clk or posedge rst)
1371
     if (rst)
1372
       qi <= {length{1'b0}};
1373
     else
1374
     if (cke)
1375
       qi <= q_next;
1376
 
1377
 
1378
 
1379
   always @ (posedge clk or posedge rst)
1380
     if (rst)
1381
       zq <= 1'b1;
1382
     else
1383
     if (cke)
1384
       zq <= q_next == {length{1'b0}};
1385
endmodule
1386
//////////////////////////////////////////////////////////////////////
1387
////                                                              ////
1388
////  Versatile counter                                           ////
1389
////                                                              ////
1390
////  Description                                                 ////
1391
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1392
////  counter                                                     ////
1393
////                                                              ////
1394
////  To Do:                                                      ////
1395
////   - add LFSR with more taps                                  ////
1396
////                                                              ////
1397
////  Author(s):                                                  ////
1398
////      - Michael Unneback, unneback@opencores.org              ////
1399
////        ORSoC AB                                              ////
1400
////                                                              ////
1401
//////////////////////////////////////////////////////////////////////
1402
////                                                              ////
1403
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1404
////                                                              ////
1405
//// This source file may be used and distributed without         ////
1406
//// restriction provided that this copyright statement is not    ////
1407
//// removed from the file and that any derivative work contains  ////
1408
//// the original copyright notice and the associated disclaimer. ////
1409
////                                                              ////
1410
//// This source file is free software; you can redistribute it   ////
1411
//// and/or modify it under the terms of the GNU Lesser General   ////
1412
//// Public License as published by the Free Software Foundation; ////
1413
//// either version 2.1 of the License, or (at your option) any   ////
1414
//// later version.                                               ////
1415
////                                                              ////
1416
//// This source is distributed in the hope that it will be       ////
1417
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1418
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1419
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1420
//// details.                                                     ////
1421
////                                                              ////
1422
//// You should have received a copy of the GNU Lesser General    ////
1423
//// Public License along with this source; if not, download it   ////
1424
//// from http://www.opencores.org/lgpl.shtml                     ////
1425
////                                                              ////
1426
//////////////////////////////////////////////////////////////////////
1427 22 unneback
 
1428
// LFSR counter
1429
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1430
 
1431
   parameter length = 4;
1432
   input cke;
1433
   output [length:1] q;
1434
   output reg zq;
1435
   input rst;
1436
   input clk;
1437
 
1438
   parameter clear_value = 0;
1439
   parameter set_value = 1;
1440
   parameter wrap_value = 8;
1441
   parameter level1_value = 15;
1442
 
1443
   reg  [length:1] qi;
1444
   reg lfsr_fb;
1445
   wire [length:1] q_next;
1446
   reg [32:1] polynom;
1447
   integer i;
1448
 
1449
   always @ (qi)
1450
   begin
1451
        case (length)
1452
         2: polynom = 32'b11;                               // 0x3
1453
         3: polynom = 32'b110;                              // 0x6
1454
         4: polynom = 32'b1100;                             // 0xC
1455
         5: polynom = 32'b10100;                            // 0x14
1456
         6: polynom = 32'b110000;                           // 0x30
1457
         7: polynom = 32'b1100000;                          // 0x60
1458
         8: polynom = 32'b10111000;                         // 0xb8
1459
         9: polynom = 32'b100010000;                        // 0x110
1460
        10: polynom = 32'b1001000000;                       // 0x240
1461
        11: polynom = 32'b10100000000;                      // 0x500
1462
        12: polynom = 32'b100000101001;                     // 0x829
1463
        13: polynom = 32'b1000000001100;                    // 0x100C
1464
        14: polynom = 32'b10000000010101;                   // 0x2015
1465
        15: polynom = 32'b110000000000000;                  // 0x6000
1466
        16: polynom = 32'b1101000000001000;                 // 0xD008
1467
        17: polynom = 32'b10010000000000000;                // 0x12000
1468
        18: polynom = 32'b100000010000000000;               // 0x20400
1469
        19: polynom = 32'b1000000000000100011;              // 0x40023
1470
        20: polynom = 32'b10000010000000000000;             // 0x82000
1471
        21: polynom = 32'b101000000000000000000;            // 0x140000
1472
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1473
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1474
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1475
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1476
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1477
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1478
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1479
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1480
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1481
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1482
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1483
        default: polynom = 32'b0;
1484
        endcase
1485
        lfsr_fb = qi[length];
1486
        for (i=length-1; i>=1; i=i-1) begin
1487
            if (polynom[i])
1488
                lfsr_fb = lfsr_fb  ~^ qi[i];
1489
        end
1490
    end
1491
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1492
 
1493
   always @ (posedge clk or posedge rst)
1494
     if (rst)
1495
       qi <= {length{1'b0}};
1496
     else
1497
     if (cke)
1498
       qi <= q_next;
1499
 
1500
   assign q = qi;
1501
 
1502
 
1503
   always @ (posedge clk or posedge rst)
1504
     if (rst)
1505
       zq <= 1'b1;
1506
     else
1507
     if (cke)
1508
       zq <= q_next == {length{1'b0}};
1509
endmodule
1510
//////////////////////////////////////////////////////////////////////
1511
////                                                              ////
1512
////  Versatile counter                                           ////
1513
////                                                              ////
1514
////  Description                                                 ////
1515
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1516
////  counter                                                     ////
1517
////                                                              ////
1518
////  To Do:                                                      ////
1519
////   - add LFSR with more taps                                  ////
1520
////                                                              ////
1521
////  Author(s):                                                  ////
1522
////      - Michael Unneback, unneback@opencores.org              ////
1523
////        ORSoC AB                                              ////
1524
////                                                              ////
1525
//////////////////////////////////////////////////////////////////////
1526
////                                                              ////
1527
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1528
////                                                              ////
1529
//// This source file may be used and distributed without         ////
1530
//// restriction provided that this copyright statement is not    ////
1531
//// removed from the file and that any derivative work contains  ////
1532
//// the original copyright notice and the associated disclaimer. ////
1533
////                                                              ////
1534
//// This source file is free software; you can redistribute it   ////
1535
//// and/or modify it under the terms of the GNU Lesser General   ////
1536
//// Public License as published by the Free Software Foundation; ////
1537
//// either version 2.1 of the License, or (at your option) any   ////
1538
//// later version.                                               ////
1539
////                                                              ////
1540
//// This source is distributed in the hope that it will be       ////
1541
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1542
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1543
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1544
//// details.                                                     ////
1545
////                                                              ////
1546
//// You should have received a copy of the GNU Lesser General    ////
1547
//// Public License along with this source; if not, download it   ////
1548
//// from http://www.opencores.org/lgpl.shtml                     ////
1549
////                                                              ////
1550
//////////////////////////////////////////////////////////////////////
1551 6 unneback
 
1552
// LFSR counter
1553 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1554 6 unneback
 
1555
   parameter length = 4;
1556
   input cke;
1557
   input rew;
1558
   output reg level1;
1559
   input rst;
1560
   input clk;
1561
 
1562
   parameter clear_value = 0;
1563
   parameter set_value = 1;
1564
   parameter wrap_value = 8;
1565
   parameter level1_value = 15;
1566
 
1567
   reg  [length:1] qi;
1568
   reg lfsr_fb, lfsr_fb_rew;
1569
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1570
   reg [32:1] polynom_rew;
1571
   integer j;
1572
   reg [32:1] polynom;
1573
   integer i;
1574
 
1575
   always @ (qi)
1576
   begin
1577
        case (length)
1578
         2: polynom = 32'b11;                               // 0x3
1579
         3: polynom = 32'b110;                              // 0x6
1580
         4: polynom = 32'b1100;                             // 0xC
1581
         5: polynom = 32'b10100;                            // 0x14
1582
         6: polynom = 32'b110000;                           // 0x30
1583
         7: polynom = 32'b1100000;                          // 0x60
1584
         8: polynom = 32'b10111000;                         // 0xb8
1585
         9: polynom = 32'b100010000;                        // 0x110
1586
        10: polynom = 32'b1001000000;                       // 0x240
1587
        11: polynom = 32'b10100000000;                      // 0x500
1588
        12: polynom = 32'b100000101001;                     // 0x829
1589
        13: polynom = 32'b1000000001100;                    // 0x100C
1590
        14: polynom = 32'b10000000010101;                   // 0x2015
1591
        15: polynom = 32'b110000000000000;                  // 0x6000
1592
        16: polynom = 32'b1101000000001000;                 // 0xD008
1593
        17: polynom = 32'b10010000000000000;                // 0x12000
1594
        18: polynom = 32'b100000010000000000;               // 0x20400
1595
        19: polynom = 32'b1000000000000100011;              // 0x40023
1596
        20: polynom = 32'b10000010000000000000;             // 0x82000
1597
        21: polynom = 32'b101000000000000000000;            // 0x140000
1598
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1599
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1600
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1601
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1602
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1603
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1604
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1605
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1606
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1607
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1608
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1609
        default: polynom = 32'b0;
1610
        endcase
1611
        lfsr_fb = qi[length];
1612
        for (i=length-1; i>=1; i=i-1) begin
1613
            if (polynom[i])
1614
                lfsr_fb = lfsr_fb  ~^ qi[i];
1615
        end
1616
    end
1617
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1618
   always @ (qi)
1619
   begin
1620
        case (length)
1621
         2: polynom_rew = 32'b11;
1622
         3: polynom_rew = 32'b110;
1623
         4: polynom_rew = 32'b1100;
1624
         5: polynom_rew = 32'b10100;
1625
         6: polynom_rew = 32'b110000;
1626
         7: polynom_rew = 32'b1100000;
1627
         8: polynom_rew = 32'b10111000;
1628
         9: polynom_rew = 32'b100010000;
1629
        10: polynom_rew = 32'b1001000000;
1630
        11: polynom_rew = 32'b10100000000;
1631
        12: polynom_rew = 32'b100000101001;
1632
        13: polynom_rew = 32'b1000000001100;
1633
        14: polynom_rew = 32'b10000000010101;
1634
        15: polynom_rew = 32'b110000000000000;
1635
        16: polynom_rew = 32'b1101000000001000;
1636
        17: polynom_rew = 32'b10010000000000000;
1637
        18: polynom_rew = 32'b100000010000000000;
1638
        19: polynom_rew = 32'b1000000000000100011;
1639
        20: polynom_rew = 32'b10000010000000000000;
1640
        21: polynom_rew = 32'b101000000000000000000;
1641
        22: polynom_rew = 32'b1100000000000000000000;
1642
        23: polynom_rew = 32'b10000100000000000000000;
1643
        24: polynom_rew = 32'b111000010000000000000000;
1644
        25: polynom_rew = 32'b1001000000000000000000000;
1645
        26: polynom_rew = 32'b10000000000000000000100011;
1646
        27: polynom_rew = 32'b100000000000000000000010011;
1647
        28: polynom_rew = 32'b1100100000000000000000000000;
1648
        29: polynom_rew = 32'b10100000000000000000000000000;
1649
        30: polynom_rew = 32'b100000000000000000000000101001;
1650
        31: polynom_rew = 32'b1001000000000000000000000000000;
1651
        32: polynom_rew = 32'b10000000001000000000000000000011;
1652
        default: polynom_rew = 32'b0;
1653
        endcase
1654
        // rotate left
1655
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1656
        lfsr_fb_rew = qi[length];
1657
        for (i=length-1; i>=1; i=i-1) begin
1658
            if (polynom_rew[i])
1659
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1660
        end
1661
    end
1662
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1663
   assign q_next = rew ? q_next_rew : q_next_fw;
1664
 
1665
   always @ (posedge clk or posedge rst)
1666
     if (rst)
1667
       qi <= {length{1'b0}};
1668
     else
1669
     if (cke)
1670
       qi <= q_next;
1671
 
1672
 
1673
 
1674
    always @ (posedge clk or posedge rst)
1675
    if (rst)
1676
        level1 <= 1'b0;
1677
    else
1678
    if (cke)
1679
    if (q_next == level1_value)
1680
        level1 <= 1'b1;
1681
    else if (qi == level1_value & rew)
1682
        level1 <= 1'b0;
1683
endmodule
1684
//////////////////////////////////////////////////////////////////////
1685
////                                                              ////
1686
////  Versatile counter                                           ////
1687
////                                                              ////
1688
////  Description                                                 ////
1689
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1690
////  counter                                                     ////
1691
////                                                              ////
1692
////  To Do:                                                      ////
1693
////   - add LFSR with more taps                                  ////
1694
////                                                              ////
1695
////  Author(s):                                                  ////
1696
////      - Michael Unneback, unneback@opencores.org              ////
1697
////        ORSoC AB                                              ////
1698
////                                                              ////
1699
//////////////////////////////////////////////////////////////////////
1700
////                                                              ////
1701
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1702
////                                                              ////
1703
//// This source file may be used and distributed without         ////
1704
//// restriction provided that this copyright statement is not    ////
1705
//// removed from the file and that any derivative work contains  ////
1706
//// the original copyright notice and the associated disclaimer. ////
1707
////                                                              ////
1708
//// This source file is free software; you can redistribute it   ////
1709
//// and/or modify it under the terms of the GNU Lesser General   ////
1710
//// Public License as published by the Free Software Foundation; ////
1711
//// either version 2.1 of the License, or (at your option) any   ////
1712
//// later version.                                               ////
1713
////                                                              ////
1714
//// This source is distributed in the hope that it will be       ////
1715
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1716
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1717
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1718
//// details.                                                     ////
1719
////                                                              ////
1720
//// You should have received a copy of the GNU Lesser General    ////
1721
//// Public License along with this source; if not, download it   ////
1722
//// from http://www.opencores.org/lgpl.shtml                     ////
1723
////                                                              ////
1724
//////////////////////////////////////////////////////////////////////
1725
 
1726
// GRAY counter
1727 18 unneback
module vl_cnt_gray ( q, rst, clk);
1728 6 unneback
 
1729
   parameter length = 4;
1730
   output reg [length:1] q;
1731
   input rst;
1732
   input clk;
1733
 
1734
   parameter clear_value = 0;
1735
   parameter set_value = 1;
1736
   parameter wrap_value = 8;
1737
   parameter level1_value = 15;
1738
 
1739
   reg  [length:1] qi;
1740
   wire [length:1] q_next;
1741
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1742
 
1743
   always @ (posedge clk or posedge rst)
1744
     if (rst)
1745
       qi <= {length{1'b0}};
1746
     else
1747
       qi <= q_next;
1748
 
1749
   always @ (posedge clk or posedge rst)
1750
     if (rst)
1751
       q <= {length{1'b0}};
1752
     else
1753
         q <= (q_next>>1) ^ q_next;
1754
 
1755
endmodule
1756
//////////////////////////////////////////////////////////////////////
1757
////                                                              ////
1758
////  Versatile counter                                           ////
1759
////                                                              ////
1760
////  Description                                                 ////
1761
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1762
////  counter                                                     ////
1763
////                                                              ////
1764
////  To Do:                                                      ////
1765
////   - add LFSR with more taps                                  ////
1766
////                                                              ////
1767
////  Author(s):                                                  ////
1768
////      - Michael Unneback, unneback@opencores.org              ////
1769
////        ORSoC AB                                              ////
1770
////                                                              ////
1771
//////////////////////////////////////////////////////////////////////
1772
////                                                              ////
1773
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1774
////                                                              ////
1775
//// This source file may be used and distributed without         ////
1776
//// restriction provided that this copyright statement is not    ////
1777
//// removed from the file and that any derivative work contains  ////
1778
//// the original copyright notice and the associated disclaimer. ////
1779
////                                                              ////
1780
//// This source file is free software; you can redistribute it   ////
1781
//// and/or modify it under the terms of the GNU Lesser General   ////
1782
//// Public License as published by the Free Software Foundation; ////
1783
//// either version 2.1 of the License, or (at your option) any   ////
1784
//// later version.                                               ////
1785
////                                                              ////
1786
//// This source is distributed in the hope that it will be       ////
1787
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1788
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1789
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1790
//// details.                                                     ////
1791
////                                                              ////
1792
//// You should have received a copy of the GNU Lesser General    ////
1793
//// Public License along with this source; if not, download it   ////
1794
//// from http://www.opencores.org/lgpl.shtml                     ////
1795
////                                                              ////
1796
//////////////////////////////////////////////////////////////////////
1797
 
1798
// GRAY counter
1799 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1800 6 unneback
 
1801
   parameter length = 4;
1802
   input cke;
1803
   output reg [length:1] q;
1804
   input rst;
1805
   input clk;
1806
 
1807
   parameter clear_value = 0;
1808
   parameter set_value = 1;
1809
   parameter wrap_value = 8;
1810
   parameter level1_value = 15;
1811
 
1812
   reg  [length:1] qi;
1813
   wire [length:1] q_next;
1814
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1815
 
1816
   always @ (posedge clk or posedge rst)
1817
     if (rst)
1818
       qi <= {length{1'b0}};
1819
     else
1820
     if (cke)
1821
       qi <= q_next;
1822
 
1823
   always @ (posedge clk or posedge rst)
1824
     if (rst)
1825
       q <= {length{1'b0}};
1826
     else
1827
       if (cke)
1828
         q <= (q_next>>1) ^ q_next;
1829
 
1830
endmodule
1831
//////////////////////////////////////////////////////////////////////
1832
////                                                              ////
1833
////  Versatile counter                                           ////
1834
////                                                              ////
1835
////  Description                                                 ////
1836
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1837
////  counter                                                     ////
1838
////                                                              ////
1839
////  To Do:                                                      ////
1840
////   - add LFSR with more taps                                  ////
1841
////                                                              ////
1842
////  Author(s):                                                  ////
1843
////      - Michael Unneback, unneback@opencores.org              ////
1844
////        ORSoC AB                                              ////
1845
////                                                              ////
1846
//////////////////////////////////////////////////////////////////////
1847
////                                                              ////
1848
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1849
////                                                              ////
1850
//// This source file may be used and distributed without         ////
1851
//// restriction provided that this copyright statement is not    ////
1852
//// removed from the file and that any derivative work contains  ////
1853
//// the original copyright notice and the associated disclaimer. ////
1854
////                                                              ////
1855
//// This source file is free software; you can redistribute it   ////
1856
//// and/or modify it under the terms of the GNU Lesser General   ////
1857
//// Public License as published by the Free Software Foundation; ////
1858
//// either version 2.1 of the License, or (at your option) any   ////
1859
//// later version.                                               ////
1860
////                                                              ////
1861
//// This source is distributed in the hope that it will be       ////
1862
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1863
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1864
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1865
//// details.                                                     ////
1866
////                                                              ////
1867
//// You should have received a copy of the GNU Lesser General    ////
1868
//// Public License along with this source; if not, download it   ////
1869
//// from http://www.opencores.org/lgpl.shtml                     ////
1870
////                                                              ////
1871
//////////////////////////////////////////////////////////////////////
1872
 
1873
// GRAY counter
1874 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1875 6 unneback
 
1876
   parameter length = 4;
1877
   input cke;
1878
   output reg [length:1] q;
1879
   output [length:1] q_bin;
1880
   input rst;
1881
   input clk;
1882
 
1883
   parameter clear_value = 0;
1884
   parameter set_value = 1;
1885
   parameter wrap_value = 8;
1886
   parameter level1_value = 15;
1887
 
1888
   reg  [length:1] qi;
1889
   wire [length:1] q_next;
1890
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1891
 
1892
   always @ (posedge clk or posedge rst)
1893
     if (rst)
1894
       qi <= {length{1'b0}};
1895
     else
1896
     if (cke)
1897
       qi <= q_next;
1898
 
1899
   always @ (posedge clk or posedge rst)
1900
     if (rst)
1901
       q <= {length{1'b0}};
1902
     else
1903
       if (cke)
1904
         q <= (q_next>>1) ^ q_next;
1905
 
1906
   assign q_bin = qi;
1907
 
1908
endmodule
1909
//////////////////////////////////////////////////////////////////////
1910
////                                                              ////
1911
////  Versatile library, counters                                 ////
1912
////                                                              ////
1913
////  Description                                                 ////
1914
////  counters                                                    ////
1915
////                                                              ////
1916
////                                                              ////
1917
////  To Do:                                                      ////
1918
////   - add more counters                                        ////
1919
////                                                              ////
1920
////  Author(s):                                                  ////
1921
////      - Michael Unneback, unneback@opencores.org              ////
1922
////        ORSoC AB                                              ////
1923
////                                                              ////
1924
//////////////////////////////////////////////////////////////////////
1925
////                                                              ////
1926
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1927
////                                                              ////
1928
//// This source file may be used and distributed without         ////
1929
//// restriction provided that this copyright statement is not    ////
1930
//// removed from the file and that any derivative work contains  ////
1931
//// the original copyright notice and the associated disclaimer. ////
1932
////                                                              ////
1933
//// This source file is free software; you can redistribute it   ////
1934
//// and/or modify it under the terms of the GNU Lesser General   ////
1935
//// Public License as published by the Free Software Foundation; ////
1936
//// either version 2.1 of the License, or (at your option) any   ////
1937
//// later version.                                               ////
1938
////                                                              ////
1939
//// This source is distributed in the hope that it will be       ////
1940
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1941
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1942
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1943
//// details.                                                     ////
1944
////                                                              ////
1945
//// You should have received a copy of the GNU Lesser General    ////
1946
//// Public License along with this source; if not, download it   ////
1947
//// from http://www.opencores.org/lgpl.shtml                     ////
1948
////                                                              ////
1949
//////////////////////////////////////////////////////////////////////
1950
 
1951 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1952 6 unneback
 
1953
   parameter length = 4;
1954
   output reg [0:length-1] q;
1955
   input rst;
1956
   input clk;
1957
 
1958
    always @ (posedge clk or posedge rst)
1959
    if (rst)
1960
        q <= {1'b1,{length-1{1'b0}}};
1961
    else
1962
        q <= {q[length-1],q[0:length-2]};
1963
 
1964
endmodule
1965
 
1966 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1967 6 unneback
 
1968
   parameter length = 4;
1969
   input cke;
1970
   output reg [0:length-1] q;
1971
   input rst;
1972
   input clk;
1973
 
1974
    always @ (posedge clk or posedge rst)
1975
    if (rst)
1976
        q <= {1'b1,{length-1{1'b0}}};
1977
    else
1978
        if (cke)
1979
            q <= {q[length-1],q[0:length-2]};
1980
 
1981
endmodule
1982
 
1983 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1984 6 unneback
 
1985
   parameter length = 4;
1986
   input cke, clear;
1987
   output reg [0:length-1] q;
1988
   input rst;
1989
   input clk;
1990
 
1991
    always @ (posedge clk or posedge rst)
1992
    if (rst)
1993
        q <= {1'b1,{length-1{1'b0}}};
1994
    else
1995
        if (cke)
1996
            if (clear)
1997
                q <= {1'b1,{length-1{1'b0}}};
1998
            else
1999
                q <= q >> 1;
2000
 
2001
endmodule
2002
 
2003 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2004 6 unneback
 
2005
   parameter length = 4;
2006
   input cke, clear;
2007
   output reg [0:length-1] q;
2008
   input rst;
2009
   input clk;
2010
 
2011
    always @ (posedge clk or posedge rst)
2012
    if (rst)
2013
        q <= {1'b1,{length-1{1'b0}}};
2014
    else
2015
        if (cke)
2016
            if (clear)
2017
                q <= {1'b1,{length-1{1'b0}}};
2018
            else
2019
            q <= {q[length-1],q[0:length-2]};
2020
 
2021
endmodule
2022
//////////////////////////////////////////////////////////////////////
2023
////                                                              ////
2024
////  Versatile library, memories                                 ////
2025
////                                                              ////
2026
////  Description                                                 ////
2027
////  memories                                                    ////
2028
////                                                              ////
2029
////                                                              ////
2030
////  To Do:                                                      ////
2031
////   - add more memory types                                    ////
2032
////                                                              ////
2033
////  Author(s):                                                  ////
2034
////      - Michael Unneback, unneback@opencores.org              ////
2035
////        ORSoC AB                                              ////
2036
////                                                              ////
2037
//////////////////////////////////////////////////////////////////////
2038
////                                                              ////
2039
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2040
////                                                              ////
2041
//// This source file may be used and distributed without         ////
2042
//// restriction provided that this copyright statement is not    ////
2043
//// removed from the file and that any derivative work contains  ////
2044
//// the original copyright notice and the associated disclaimer. ////
2045
////                                                              ////
2046
//// This source file is free software; you can redistribute it   ////
2047
//// and/or modify it under the terms of the GNU Lesser General   ////
2048
//// Public License as published by the Free Software Foundation; ////
2049
//// either version 2.1 of the License, or (at your option) any   ////
2050
//// later version.                                               ////
2051
////                                                              ////
2052
//// This source is distributed in the hope that it will be       ////
2053
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2054
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2055
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2056
//// details.                                                     ////
2057
////                                                              ////
2058
//// You should have received a copy of the GNU Lesser General    ////
2059
//// Public License along with this source; if not, download it   ////
2060
//// from http://www.opencores.org/lgpl.shtml                     ////
2061
////                                                              ////
2062
//////////////////////////////////////////////////////////////////////
2063
 
2064
/// ROM
2065
 
2066 7 unneback
module vl_rom_init ( adr, q, clk);
2067
   parameter data_width = 32;
2068
   parameter addr_width = 8;
2069
   input [(addr_width-1):0]       adr;
2070
   output reg [(data_width-1):0] q;
2071
   input                         clk;
2072
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2073
   parameter memory_file = "vl_rom.vmem";
2074
   initial
2075
     begin
2076
        $readmemh(memory_file, rom);
2077
     end
2078
 
2079
   always @ (posedge clk)
2080
     q <= rom[adr];
2081 6 unneback
 
2082 7 unneback
endmodule
2083
 
2084 14 unneback
/*
2085 7 unneback
module vl_rom ( adr, q, clk);
2086
 
2087 6 unneback
parameter data_width = 32;
2088
parameter addr_width = 4;
2089
 
2090
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2091
    {32'h18000000},
2092
    {32'hA8200000},
2093
    {32'hA8200000},
2094
    {32'hA8200000},
2095
    {32'h44003000},
2096
    {32'h15000000},
2097
    {32'h15000000},
2098
    {32'h15000000},
2099
    {32'h15000000},
2100
    {32'h15000000},
2101
    {32'h15000000},
2102
    {32'h15000000},
2103
    {32'h15000000},
2104
    {32'h15000000},
2105
    {32'h15000000},
2106
    {32'h15000000}};
2107
 
2108 7 unneback
input [addr_width-1:0] adr;
2109 6 unneback
output reg [data_width-1:0] q;
2110
input clk;
2111
 
2112
always @ (posedge clk)
2113 7 unneback
    q <= data[adr];
2114 6 unneback
 
2115
endmodule
2116 14 unneback
*/
2117 6 unneback
// Single port RAM
2118
 
2119
module vl_ram ( d, adr, we, q, clk);
2120
   parameter data_width = 32;
2121
   parameter addr_width = 8;
2122
   input [(data_width-1):0]      d;
2123
   input [(addr_width-1):0]       adr;
2124
   input                         we;
2125 7 unneback
   output reg [(data_width-1):0] q;
2126 6 unneback
   input                         clk;
2127
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2128 7 unneback
   parameter init = 0;
2129
   parameter memory_file = "vl_ram.vmem";
2130
   generate if (init) begin : init_mem
2131
   initial
2132
     begin
2133
        $readmemh(memory_file, ram);
2134
     end
2135
   end
2136
   endgenerate
2137
 
2138 6 unneback
   always @ (posedge clk)
2139
   begin
2140
   if (we)
2141
     ram[adr] <= d;
2142
   q <= ram[adr];
2143
   end
2144
 
2145
endmodule
2146
 
2147 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2148
   parameter data_width = 32;
2149
   parameter addr_width = 8;
2150
   input [(data_width-1):0]      d;
2151
   input [(addr_width-1):0]       adr;
2152
   input [(addr_width/4)-1:0]    be;
2153
   input                         we;
2154
   output reg [(data_width-1):0] q;
2155
   input                         clk;
2156
 
2157
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2158
 
2159
   parameter init = 0;
2160
   parameter memory_file = "vl_ram.vmem";
2161
   generate if (init) begin : init_mem
2162
   initial
2163
     begin
2164
        $readmemh(memory_file, ram);
2165
     end
2166
   end
2167
   endgenerate
2168
 
2169
   genvar i;
2170
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2171
      always @ (posedge clk)
2172
      if (we & be[i])
2173
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2174
   end
2175
   endgenerate
2176
 
2177
   always @ (posedge clk)
2178
      q <= ram[adr];
2179
 
2180
endmodule
2181
 
2182
 
2183 6 unneback
// Dual port RAM
2184
 
2185
// ACTEL FPGA should not use logic to handle rw collision
2186
`ifdef ACTEL
2187
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
2188
`else
2189
        `define SYN
2190
`endif
2191
 
2192 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2193 6 unneback
   parameter data_width = 32;
2194
   parameter addr_width = 8;
2195
   input [(data_width-1):0]      d_a;
2196
   input [(addr_width-1):0]       adr_a;
2197
   input [(addr_width-1):0]       adr_b;
2198
   input                         we_a;
2199
   output [(data_width-1):0]      q_b;
2200
   input                         clk_a, clk_b;
2201
   reg [(addr_width-1):0]         adr_b_reg;
2202
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
2203 7 unneback
 
2204
   parameter init = 0;
2205
   parameter memory_file = "vl_ram.vmem";
2206
   generate if (init) begin : init_mem
2207
   initial
2208
     begin
2209
        $readmemh(memory_file, ram);
2210
     end
2211
   end
2212
   endgenerate
2213
 
2214 6 unneback
   always @ (posedge clk_a)
2215
   if (we_a)
2216
     ram[adr_a] <= d_a;
2217
   always @ (posedge clk_b)
2218
   adr_b_reg <= adr_b;
2219
   assign q_b = ram[adr_b_reg];
2220
endmodule
2221
 
2222 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2223 6 unneback
   parameter data_width = 32;
2224
   parameter addr_width = 8;
2225
   input [(data_width-1):0]      d_a;
2226
   input [(addr_width-1):0]       adr_a;
2227
   input [(addr_width-1):0]       adr_b;
2228
   input                         we_a;
2229
   output [(data_width-1):0]      q_b;
2230
   output reg [(data_width-1):0] q_a;
2231
   input                         clk_a, clk_b;
2232
   reg [(data_width-1):0]         q_b;
2233
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
2234 7 unneback
 
2235
   parameter init = 0;
2236
   parameter memory_file = "vl_ram.vmem";
2237
   generate if (init) begin : init_mem
2238
   initial
2239
     begin
2240
        $readmemh(memory_file, ram);
2241
     end
2242
   end
2243
   endgenerate
2244
 
2245 6 unneback
   always @ (posedge clk_a)
2246
     begin
2247
        q_a <= ram[adr_a];
2248
        if (we_a)
2249
             ram[adr_a] <= d_a;
2250
     end
2251
   always @ (posedge clk_b)
2252
          q_b <= ram[adr_b];
2253
endmodule
2254
 
2255 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2256 6 unneback
   parameter data_width = 32;
2257
   parameter addr_width = 8;
2258
   input [(data_width-1):0]      d_a;
2259
   input [(addr_width-1):0]       adr_a;
2260
   input [(addr_width-1):0]       adr_b;
2261
   input                         we_a;
2262
   output [(data_width-1):0]      q_b;
2263
   input [(data_width-1):0]       d_b;
2264
   output reg [(data_width-1):0] q_a;
2265
   input                         we_b;
2266
   input                         clk_a, clk_b;
2267
   reg [(data_width-1):0]         q_b;
2268
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
2269 7 unneback
 
2270
   parameter init = 0;
2271
   parameter memory_file = "vl_ram.vmem";
2272
   generate if (init) begin : init_mem
2273
   initial
2274
     begin
2275
        $readmemh(memory_file, ram);
2276
     end
2277
   end
2278
   endgenerate
2279
 
2280 6 unneback
   always @ (posedge clk_a)
2281
     begin
2282
        q_a <= ram[adr_a];
2283
        if (we_a)
2284
             ram[adr_a] <= d_a;
2285
     end
2286
   always @ (posedge clk_b)
2287
     begin
2288
        q_b <= ram[adr_b];
2289
        if (we_b)
2290
          ram[adr_b] <= d_b;
2291
     end
2292
endmodule
2293
 
2294
// Content addresable memory, CAM
2295
 
2296
// FIFO
2297
 
2298
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2299
 
2300 11 unneback
   parameter addr_width = 4;
2301
   parameter N = addr_width-1;
2302 6 unneback
 
2303
   parameter Q1 = 2'b00;
2304
   parameter Q2 = 2'b01;
2305
   parameter Q3 = 2'b11;
2306
   parameter Q4 = 2'b10;
2307
 
2308
   parameter going_empty = 1'b0;
2309
   parameter going_full  = 1'b1;
2310
 
2311
   input [N:0]  wptr, rptr;
2312 14 unneback
   output       fifo_empty;
2313 6 unneback
   output       fifo_full;
2314
   input        wclk, rclk, rst;
2315
 
2316
`ifndef GENERATE_DIRECTION_AS_LATCH
2317
   wire direction;
2318
`endif
2319
`ifdef GENERATE_DIRECTION_AS_LATCH
2320
   reg direction;
2321
`endif
2322
   reg  direction_set, direction_clr;
2323
 
2324
   wire async_empty, async_full;
2325
   wire fifo_full2;
2326 14 unneback
   wire fifo_empty2;
2327 6 unneback
 
2328
   // direction_set
2329
   always @ (wptr[N:N-1] or rptr[N:N-1])
2330
     case ({wptr[N:N-1],rptr[N:N-1]})
2331
       {Q1,Q2} : direction_set <= 1'b1;
2332
       {Q2,Q3} : direction_set <= 1'b1;
2333
       {Q3,Q4} : direction_set <= 1'b1;
2334
       {Q4,Q1} : direction_set <= 1'b1;
2335
       default : direction_set <= 1'b0;
2336
     endcase
2337
 
2338
   // direction_clear
2339
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2340
     if (rst)
2341
       direction_clr <= 1'b1;
2342
     else
2343
       case ({wptr[N:N-1],rptr[N:N-1]})
2344
         {Q2,Q1} : direction_clr <= 1'b1;
2345
         {Q3,Q2} : direction_clr <= 1'b1;
2346
         {Q4,Q3} : direction_clr <= 1'b1;
2347
         {Q1,Q4} : direction_clr <= 1'b1;
2348
         default : direction_clr <= 1'b0;
2349
       endcase
2350
 
2351
`ifndef GENERATE_DIRECTION_AS_LATCH
2352 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2353 6 unneback
`endif
2354
 
2355
`ifdef GENERATE_DIRECTION_AS_LATCH
2356
   always @ (posedge direction_set or posedge direction_clr)
2357
     if (direction_clr)
2358
       direction <= going_empty;
2359
     else
2360
       direction <= going_full;
2361
`endif
2362
 
2363
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2364
   assign async_full  = (wptr == rptr) && (direction==going_full);
2365
 
2366 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2367
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2368 6 unneback
 
2369
/*
2370
   always @ (posedge wclk or posedge rst or posedge async_full)
2371
     if (rst)
2372
       {fifo_full, fifo_full2} <= 2'b00;
2373
     else if (async_full)
2374
       {fifo_full, fifo_full2} <= 2'b11;
2375
     else
2376
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2377
*/
2378 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2379 6 unneback
     if (async_empty)
2380
       {fifo_empty, fifo_empty2} <= 2'b11;
2381
     else
2382 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2383 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2384
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2385 6 unneback
 
2386
endmodule // async_comp
2387
 
2388
module vl_fifo_1r1w_async (
2389
    d, wr, fifo_full, wr_clk, wr_rst,
2390
    q, rd, fifo_empty, rd_clk, rd_rst
2391
    );
2392
 
2393
parameter data_width = 18;
2394
parameter addr_width = 4;
2395
 
2396
// write side
2397
input  [data_width-1:0] d;
2398
input                   wr;
2399
output                  fifo_full;
2400
input                   wr_clk;
2401
input                   wr_rst;
2402
// read side
2403
output [data_width-1:0] q;
2404
input                   rd;
2405
output                  fifo_empty;
2406
input                   rd_clk;
2407
input                   rd_rst;
2408
 
2409
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
2410 21 unneback
/*
2411 6 unneback
vl_fifo_1r1w_async (
2412
    d, wr, fifo_full, wr_clk, wr_rst,
2413
    q, rd, fifo_empty, rd_clk, rd_rst
2414
    );
2415 21 unneback
*/
2416 18 unneback
vl_cnt_gray_ce_bin
2417 6 unneback
    # ( .length(addr_width))
2418
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2419
 
2420 18 unneback
vl_cnt_gray_ce_bin
2421 6 unneback
    # (.length(addr_width))
2422
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
2423
 
2424 7 unneback
vl_dpram_1r1w
2425 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2426
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2427
 
2428
vl_fifo_cmp_async
2429
    # (.addr_width(addr_width))
2430
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2431
 
2432
endmodule
2433
 
2434 8 unneback
module vl_fifo_2r2w_async (
2435 6 unneback
    // a side
2436
    a_d, a_wr, a_fifo_full,
2437
    a_q, a_rd, a_fifo_empty,
2438
    a_clk, a_rst,
2439
    // b side
2440
    b_d, b_wr, b_fifo_full,
2441
    b_q, b_rd, b_fifo_empty,
2442
    b_clk, b_rst
2443
    );
2444
 
2445
parameter data_width = 18;
2446
parameter addr_width = 4;
2447
 
2448
// a side
2449
input  [data_width-1:0] a_d;
2450
input                   a_wr;
2451
output                  a_fifo_full;
2452
output [data_width-1:0] a_q;
2453
input                   a_rd;
2454
output                  a_fifo_empty;
2455
input                   a_clk;
2456
input                   a_rst;
2457
 
2458
// b side
2459
input  [data_width-1:0] b_d;
2460
input                   b_wr;
2461
output                  b_fifo_full;
2462
output [data_width-1:0] b_q;
2463
input                   b_rd;
2464
output                  b_fifo_empty;
2465
input                   b_clk;
2466
input                   b_rst;
2467
 
2468
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2469
vl_fifo_1r1w_async_a (
2470
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2471
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2472
    );
2473
 
2474
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2475
vl_fifo_1r1w_async_b (
2476
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2477
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2478
    );
2479
 
2480
endmodule
2481
 
2482 8 unneback
module vl_fifo_2r2w_async_simplex (
2483 6 unneback
    // a side
2484
    a_d, a_wr, a_fifo_full,
2485
    a_q, a_rd, a_fifo_empty,
2486
    a_clk, a_rst,
2487
    // b side
2488
    b_d, b_wr, b_fifo_full,
2489
    b_q, b_rd, b_fifo_empty,
2490
    b_clk, b_rst
2491
    );
2492
 
2493
parameter data_width = 18;
2494
parameter addr_width = 4;
2495
 
2496
// a side
2497
input  [data_width-1:0] a_d;
2498
input                   a_wr;
2499
output                  a_fifo_full;
2500
output [data_width-1:0] a_q;
2501
input                   a_rd;
2502
output                  a_fifo_empty;
2503
input                   a_clk;
2504
input                   a_rst;
2505
 
2506
// b side
2507
input  [data_width-1:0] b_d;
2508
input                   b_wr;
2509
output                  b_fifo_full;
2510
output [data_width-1:0] b_q;
2511
input                   b_rd;
2512
output                  b_fifo_empty;
2513
input                   b_clk;
2514
input                   b_rst;
2515
 
2516
// adr_gen
2517
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2518
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2519
// dpram
2520
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2521
 
2522 18 unneback
vl_cnt_gray_ce_bin
2523 6 unneback
    # ( .length(addr_width))
2524
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2525
 
2526 18 unneback
vl_cnt_gray_ce_bin
2527 6 unneback
    # (.length(addr_width))
2528
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2529
 
2530 18 unneback
vl_cnt_gray_ce_bin
2531 6 unneback
    # ( .length(addr_width))
2532
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2533
 
2534 18 unneback
vl_cnt_gray_ce_bin
2535 6 unneback
    # (.length(addr_width))
2536
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2537
 
2538
// mux read or write adr to DPRAM
2539
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2540
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2541
 
2542 11 unneback
vl_dpram_2r2w
2543 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2544
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2545
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2546
 
2547 11 unneback
vl_fifo_cmp_async
2548 6 unneback
    # (.addr_width(addr_width))
2549
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2550
 
2551 11 unneback
vl_fifo_cmp_async
2552 6 unneback
    # (.addr_width(addr_width))
2553
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2554
 
2555
endmodule
2556 12 unneback
//////////////////////////////////////////////////////////////////////
2557
////                                                              ////
2558
////  Versatile library, wishbone stuff                           ////
2559
////                                                              ////
2560
////  Description                                                 ////
2561
////  Wishbone compliant modules                                  ////
2562
////                                                              ////
2563
////                                                              ////
2564
////  To Do:                                                      ////
2565
////   -                                                          ////
2566
////                                                              ////
2567
////  Author(s):                                                  ////
2568
////      - Michael Unneback, unneback@opencores.org              ////
2569
////        ORSoC AB                                              ////
2570
////                                                              ////
2571
//////////////////////////////////////////////////////////////////////
2572
////                                                              ////
2573
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2574
////                                                              ////
2575
//// This source file may be used and distributed without         ////
2576
//// restriction provided that this copyright statement is not    ////
2577
//// removed from the file and that any derivative work contains  ////
2578
//// the original copyright notice and the associated disclaimer. ////
2579
////                                                              ////
2580
//// This source file is free software; you can redistribute it   ////
2581
//// and/or modify it under the terms of the GNU Lesser General   ////
2582
//// Public License as published by the Free Software Foundation; ////
2583
//// either version 2.1 of the License, or (at your option) any   ////
2584
//// later version.                                               ////
2585
////                                                              ////
2586
//// This source is distributed in the hope that it will be       ////
2587
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2588
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2589
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2590
//// details.                                                     ////
2591
////                                                              ////
2592
//// You should have received a copy of the GNU Lesser General    ////
2593
//// Public License along with this source; if not, download it   ////
2594
//// from http://www.opencores.org/lgpl.shtml                     ////
2595
////                                                              ////
2596
//////////////////////////////////////////////////////////////////////
2597
 
2598
// async wb3 - wb3 bridge
2599
`timescale 1ns/1ns
2600 18 unneback
module vl_wb3wb3_bridge (
2601 12 unneback
        // wishbone slave side
2602
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2603
        // wishbone master side
2604
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2605
 
2606
input [31:0] wbs_dat_i;
2607
input [31:2] wbs_adr_i;
2608
input [3:0]  wbs_sel_i;
2609
input [1:0]  wbs_bte_i;
2610
input [2:0]  wbs_cti_i;
2611
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2612
output [31:0] wbs_dat_o;
2613 14 unneback
output wbs_ack_o;
2614 12 unneback
input wbs_clk, wbs_rst;
2615
 
2616
output [31:0] wbm_dat_o;
2617
output reg [31:2] wbm_adr_o;
2618
output [3:0]  wbm_sel_o;
2619
output reg [1:0]  wbm_bte_o;
2620
output reg [2:0]  wbm_cti_o;
2621 14 unneback
output reg wbm_we_o;
2622
output wbm_cyc_o;
2623 12 unneback
output wbm_stb_o;
2624
input [31:0]  wbm_dat_i;
2625
input wbm_ack_i;
2626
input wbm_clk, wbm_rst;
2627
 
2628
parameter addr_width = 4;
2629
 
2630
// bte
2631
parameter linear       = 2'b00;
2632
parameter wrap4        = 2'b01;
2633
parameter wrap8        = 2'b10;
2634
parameter wrap16       = 2'b11;
2635
// cti
2636
parameter classic      = 3'b000;
2637
parameter incburst     = 3'b010;
2638
parameter endofburst   = 3'b111;
2639
 
2640
parameter wbs_adr  = 1'b0;
2641
parameter wbs_data = 1'b1;
2642
 
2643
parameter wbm_adr0 = 2'b00;
2644
parameter wbm_adr1 = 2'b01;
2645
parameter wbm_data = 2'b10;
2646
 
2647
reg [1:0] wbs_bte_reg;
2648
reg wbs;
2649
wire wbs_eoc_alert, wbm_eoc_alert;
2650
reg wbs_eoc, wbm_eoc;
2651
reg [1:0] wbm;
2652
 
2653 14 unneback
wire [1:16] wbs_count, wbm_count;
2654 12 unneback
 
2655
wire [35:0] a_d, a_q, b_d, b_q;
2656
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2657
reg a_rd_reg;
2658
wire b_rd_adr, b_rd_data;
2659 14 unneback
wire b_rd_data_reg;
2660
wire [35:0] temp;
2661 12 unneback
 
2662
`define WE 5
2663
`define BTE 4:3
2664
`define CTI 2:0
2665
 
2666
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2667
always @ (posedge wbs_clk or posedge wbs_rst)
2668
if (wbs_rst)
2669
        wbs_eoc <= 1'b0;
2670
else
2671
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2672
                wbs_eoc <= wbs_bte_i==linear;
2673
        else if (wbs_eoc_alert & (a_rd | a_wr))
2674
                wbs_eoc <= 1'b1;
2675
 
2676 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2677 12 unneback
    cnt0 (
2678
        .cke(wbs_ack_o),
2679
        .clear(wbs_eoc),
2680
        .q(wbs_count),
2681
        .rst(wbs_rst),
2682
        .clk(wbs_clk));
2683
 
2684
always @ (posedge wbs_clk or posedge wbs_rst)
2685
if (wbs_rst)
2686
        wbs <= wbs_adr;
2687
else
2688
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
2689
                wbs <= wbs_data;
2690
        else if (wbs_eoc & wbs_ack_o)
2691
                wbs <= wbs_adr;
2692
 
2693
// wbs FIFO
2694
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
2695
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
2696
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2697
              1'b0;
2698
assign a_rd = !a_fifo_empty;
2699
always @ (posedge wbs_clk or posedge wbs_rst)
2700
if (wbs_rst)
2701
        a_rd_reg <= 1'b0;
2702
else
2703
        a_rd_reg <= a_rd;
2704
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2705
 
2706
assign wbs_dat_o = a_q[35:4];
2707
 
2708
always @ (posedge wbs_clk or posedge wbs_rst)
2709
if (wbs_rst)
2710 13 unneback
        wbs_bte_reg <= 2'b00;
2711 12 unneback
else
2712 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2713 12 unneback
 
2714
// wbm FIFO
2715
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2716
always @ (posedge wbm_clk or posedge wbm_rst)
2717
if (wbm_rst)
2718
        wbm_eoc <= 1'b0;
2719
else
2720
        if (wbm==wbm_adr0 & !b_fifo_empty)
2721
                wbm_eoc <= b_q[`BTE] == linear;
2722
        else if (wbm_eoc_alert & wbm_ack_i)
2723
                wbm_eoc <= 1'b1;
2724
 
2725
always @ (posedge wbm_clk or posedge wbm_rst)
2726
if (wbm_rst)
2727
        wbm <= wbm_adr0;
2728
else
2729
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2730
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2731
        (wbm==wbm_adr1 & !wbm_we_o) |
2732
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2733
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2734
 
2735
assign b_d = {wbm_dat_i,4'b1111};
2736
assign b_wr = !wbm_we_o & wbm_ack_i;
2737
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2738
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2739
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2740
                   1'b0;
2741
assign b_rd = b_rd_adr | b_rd_data;
2742
 
2743 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2744
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2745 12 unneback
 
2746
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2747
 
2748 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2749 12 unneback
    cnt1 (
2750
        .cke(wbm_ack_i),
2751
        .clear(wbm_eoc),
2752
        .q(wbm_count),
2753
        .rst(wbm_rst),
2754
        .clk(wbm_clk));
2755
 
2756
assign wbm_cyc_o = wbm