Subversion Repositories versatile_library

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile library, clock and reset                          ////

////                                                              ////

////  Description                                                 ////

////  Logic related to clock and reset                            ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////   - add more different registers                             ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// Global buffer

// usage:

// use to enable global buffers for high fan out signals such as clock and reset

`ifdef ACTEL

`timescale 1 ns/100 ps

// Version: 8.4 8.4.0.33

module gbuf(GL,CLK);

output GL;

input  CLK;

    wire GND;

    GND GND_1_net(.Y(GND));

    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),

        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;

endmodule

`timescale 1 ns/1 ns

module vl_gbuf ( i, o);

input i;

output o;

`ifdef SIM_GBUF

assign o=i;

`else

gbuf gbuf_i0 ( .CLK(i), .GL(o));

`endif

endmodule

`else

`ifdef ALTERA

//altera

`else

`timescale 1 ns/100 ps

module vl_gbuf ( i, o);

input i;

output o;

assign o = i;

endmodule

`endif // ALTERA

`endif //ACTEL

// sync reset

// input active lo async reset, normally from external reset generator and/or switch

// output active high global reset sync with two DFFs 

`timescale 1 ns/100 ps

module vl_sync_rst ( rst_n_i, rst_o, clk);

input rst_n_i, clk;

output rst_o;

reg [1:0] tmp;

always @ (posedge clk or negedge rst_n_i)

if (!rst_n_i)

        tmp <= 2'b11;

else

        tmp <= {1'b0,tmp[0]};

vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));

endmodule

// vl_pll

`ifdef ACTEL

`timescale 1 ps/1 ps

module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);

parameter index = 0;

parameter number_of_clk = 1;

parameter period_time_0 = 20000;

parameter period_time_1 = 20000;

parameter period_time_2 = 20000;

parameter lock_delay = 2000000;

input clk_i, rst_n_i;

output lock;

output reg [0:number_of_clk-1] clk_o;

output [0:number_of_clk-1] rst_o;

`ifdef SIM_PLL

always

     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];

generate if (number_of_clk > 1)

always

     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];

endgenerate

generate if (number_of_clk > 2)

always

     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];

endgenerate

genvar i;

generate for (i=0;i<number_of_clk;i=i+1) begin: clock

     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));

end

endgenerate

assign #lock_delay lock = rst_n_i;

endmodule

`else

generate if (number_of_clk==1 & index==0) begin

        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

end

endgenerate // index==0

generate if (number_of_clk==1 & index==1) begin

        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

end

endgenerate // index==1

generate if (number_of_clk==1 & index==2) begin

        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

end

endgenerate // index==2

generate if (number_of_clk==1 & index==3) begin

        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

end

endgenerate // index==0

generate if (number_of_clk==2 & index==0) begin

        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

end

endgenerate // index==0

generate if (number_of_clk==2 & index==1) begin

        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

end

endgenerate // index==1

generate if (number_of_clk==2 & index==2) begin

        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

end

endgenerate // index==2

generate if (number_of_clk==2 & index==3) begin

        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

end

endgenerate // index==0

generate if (number_of_clk==3 & index==0) begin

        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

end

endgenerate // index==0

generate if (number_of_clk==3 & index==1) begin

        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

end

endgenerate // index==1

generate if (number_of_clk==3 & index==2) begin

        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

end

endgenerate // index==2

generate if (number_of_clk==3 & index==3) begin

        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

end

endgenerate // index==0

genvar i;

generate for (i=0;i<number_of_clk;i=i+1) begin: clock

        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));

end

endgenerate

endmodule

`endif

`else

`ifdef ALTERA

`else

// generic PLL

`timescale 1 ps/1 ps

module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);

parameter index = 0;

parameter number_of_clk = 1;

parameter period_time_0 = 20000;

parameter period_time_1 = 20000;

parameter period_time_2 = 20000;

parameter lock_delay = 2000;

input clk_i, rst_n_i;

output lock;

output reg [0:number_of_clk-1] clk_o;

output [0:number_of_clk-1] rst_o;

always

     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];

generate if (number_of_clk > 1)

always

     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];

endgenerate

generate if (number_of_clk > 2)

always

     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];

endgenerate

genvar i;

generate for (i=0;i<number_of_clk;i=i+1) begin: clock

     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));

end

endgenerate

assign #lock_delay lock = rst_n_i;

endmodule

`endif //altera

`endif //actel

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile library, registers                                ////

////                                                              ////

////  Description                                                 ////

////  Different type of registers                                 ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////   - add more different registers                             ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

module vl_dff ( d, q, clk, rst);

        parameter width = 1;

        parameter reset_value = 0;

        input [width-1:0] d;

        input clk, rst;

        output reg [width-1:0] q;

        always @ (posedge clk or posedge rst)

        if (rst)

                q <= reset_value;

        else

                q <= d;

endmodule

module vl_dff_array ( d, q, clk, rst);

        parameter width = 1;

        parameter depth = 2;

        parameter reset_value = 1'b0;

        input [width-1:0] d;

        input clk, rst;

        output [width-1:0] q;

        reg  [0:depth-1] q_tmp [width-1:0];

        integer i;

        always @ (posedge clk or posedge rst)

        if (rst) begin

            for (i=0;i<depth;i=i+1)

                q_tmp[i] <= {width{reset_value}};

        end else begin

            q_tmp[0] <= d;

            for (i=1;i<depth;i=i+1)

                q_tmp[i] <= q_tmp[i-1];

        end

    assign q = q_tmp[depth-1];

endmodule

module vl_dff_ce ( d, ce, q, clk, rst);

        parameter width = 1;

        parameter reset_value = 0;

        input [width-1:0] d;

        input ce, clk, rst;

        output reg [width-1:0] q;

        always @ (posedge clk or posedge rst)

        if (rst)

                q <= reset_value;

        else

                if (ce)

                        q <= d;

endmodule

module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);

        parameter width = 1;

        parameter reset_value = 0;

        input [width-1:0] d;

        input ce, clear, clk, rst;

        output reg [width-1:0] q;

        always @ (posedge clk or posedge rst)

        if (rst)

            q <= reset_value;

        else

            if (ce)

                if (clear)

                    q <= {width{1'b0}};

                else

                    q <= d;

endmodule

module vl_dff_ce_set ( d, ce, set, q, clk, rst);

        parameter width = 1;

        parameter reset_value = 0;

        input [width-1:0] d;

        input ce, set, clk, rst;

        output reg [width-1:0] q;

        always @ (posedge clk or posedge rst)

        if (rst)

            q <= reset_value;

        else

            if (ce)

                if (set)

                    q <= {width{1'b1}};

                else

                    q <= d;

endmodule

module vl_spr ( sp, r, q, clk, rst);

        parameter width = 1;

        parameter reset_value = 0;

        input sp, r;

        output reg q;

        input clk, rst;

        always @ (posedge clk or posedge rst)

        if (rst)

            q <= reset_value;

        else

            if (sp)

                q <= 1'b1;

            else if (r)

                q <= 1'b0;

endmodule

module vl_srp ( s, rp, q, clk, rst);

        parameter width = 1;

        parameter reset_value = 0;

        input s, rp;

        output reg q;

        input clk, rst;

        always @ (posedge clk or posedge rst)

        if (rst)

            q <= reset_value;

        else

            if (rp)

                q <= 1'b0;

            else if (s)

                q <= 1'b1;

endmodule

`ifdef ALTERA

// megafunction wizard: %LPM_FF%

// GENERATION: STANDARD

// VERSION: WM1.0

// MODULE: lpm_ff 

// ============================================================

// File Name: dff_sr.v

// Megafunction Name(s):

//                      lpm_ff

//

// Simulation Library Files(s):

//                      lpm

// ============================================================

// ************************************************************

// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

//

// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version

// ************************************************************

//Copyright (C) 1991-2010 Altera Corporation

//Your use of Altera Corporation's design tools, logic functions 

//and other software and tools, and its AMPP partner logic 

//functions, and any output files from any of the foregoing 

//(including device programming or simulation files), and any 

//associated documentation or information are expressly subject 

//to the terms and conditions of the Altera Program License 

//Subscription Agreement, Altera MegaCore Function License 

//Agreement, or other applicable license agreement, including, 

//without limitation, that your use is for the sole purpose of 

//programming logic devices manufactured by Altera and sold by 

//Altera or its authorized distributors.  Please refer to the 

//applicable agreement for further details.

// synopsys translate_off

`timescale 1 ps / 1 ps

// synopsys translate_on

module vl_dff_sr (

        aclr,

        aset,

        clock,

        data,

        q);

        input     aclr;

        input     aset;

        input     clock;

        input     data;

        output    q;

        wire [0:0] sub_wire0;

        wire [0:0] sub_wire1 = sub_wire0[0:0];

        wire  q = sub_wire1;

        wire  sub_wire2 = data;

        wire  sub_wire3 = sub_wire2;

        lpm_ff  lpm_ff_component (

                                .aclr (aclr),

                                .clock (clock),

                                .data (sub_wire3),

                                .aset (aset),

                                .q (sub_wire0)

                                // synopsys translate_off

                                ,

                                .aload (),

                                .enable (),

                                .sclr (),

                                .sload (),

                                .sset ()

                                // synopsys translate_on

                                );

        defparam

                lpm_ff_component.lpm_fftype = "DFF",

                lpm_ff_component.lpm_type = "LPM_FF",

                lpm_ff_component.lpm_width = 1;

endmodule

// ============================================================

// CNX file retrieval info

// ============================================================

// Retrieval info: PRIVATE: ACLR NUMERIC "1"

// Retrieval info: PRIVATE: ALOAD NUMERIC "0"

// Retrieval info: PRIVATE: ASET NUMERIC "1"

// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"

// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"

// Retrieval info: PRIVATE: DFF NUMERIC "1"

// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"

// Retrieval info: PRIVATE: SCLR NUMERIC "0"

// Retrieval info: PRIVATE: SLOAD NUMERIC "0"

// Retrieval info: PRIVATE: SSET NUMERIC "0"

// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"

// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"

// Retrieval info: PRIVATE: nBit NUMERIC "1"

// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"

// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"

// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"

// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr

// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset

// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock

// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data

// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q

// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0

// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0

// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0

// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0

// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0

// Retrieval info: LIBRARY: lpm lpm.lpm_components.all

// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE

// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE

// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE

// Retrieval info: LIB_FILE: lpm

`else

module vl_dff_sr ( aclr, aset, clock, data, q);

    input         aclr;

    input         aset;

    input         clock;

    input         data;

    output reg    q;

   always @ (posedge clock or posedge aclr or posedge aset)

     if (aclr)

       q <= 1'b0;

     else if (aset)

       q <= 1'b1;

     else

       q <= data;

endmodule

`endif

// LATCH

// For targtes not supporting LATCH use dff_sr with clk=1 and data=1

`ifdef ALTERA

module vl_latch ( d, le, q, clk);

input d, le;

output q;

input clk;

dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));

endmodule

`else

module latch ( d, le, q, clk);

input d, le;

output q;

input clk;/*

   always @ (posedge direction_set or posedge direction_clr)

     if (direction_clr)

       direction <= going_empty;

     else

       direction <= going_full;*/

endmodule

`endif

module vl_shreg ( d, q, clk, rst);

parameter depth = 10;

input d;

output q;

input clk, rst;

reg [1:depth] dffs;

always @ (posedge clk or posedge rst)

if (rst)

    dffs <= {depth{1'b0}};

else

    dffs <= {d,dffs[1:depth-1]};

assign q = dffs[depth];

endmodule

module vl_shreg_ce ( d, ce, q, clk, rst);

parameter depth = 10;

input d, ce;

output q;

input clk, rst;

reg [1:depth] dffs;

always @ (posedge clk or posedge rst)

if (rst)

    dffs <= {depth{1'b0}};

else

    if (ce)

        dffs <= {d,dffs[1:depth-1]};

assign q = dffs[depth];

endmodule

module vl_delay ( d, q, clk, rst);

parameter depth = 10;

input d;

output q;

input clk, rst;

reg [1:depth] dffs;

always @ (posedge clk or posedge rst)

if (rst)

    dffs <= {depth{1'b0}};

else

    dffs <= {d,dffs[1:depth-1]};

assign q = dffs[depth];

endmodule

module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);