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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
66
`ifdef SIM_GBUF
67
assign o=i;
68
`else
69
gbuf gbuf_i0 ( .CLK(i), .GL(o));
70
`endif
71
endmodule
72
`else
73
`ifdef ALTERA
74 21 unneback
//altera
75 6 unneback
`else
76
 
77
`timescale 1 ns/100 ps
78
module vl_gbuf ( i, o);
79
input i;
80
output o;
81
assign o = i;
82
endmodule
83
`endif // ALTERA
84
`endif //ACTEL
85
 
86
// sync reset
87 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
88 6 unneback
// output active high global reset sync with two DFFs 
89
`timescale 1 ns/100 ps
90
module vl_sync_rst ( rst_n_i, rst_o, clk);
91
input rst_n_i, clk;
92
output rst_o;
93 18 unneback
reg [1:0] tmp;
94 6 unneback
always @ (posedge clk or negedge rst_n_i)
95
if (!rst_n_i)
96 17 unneback
        tmp <= 2'b11;
97 6 unneback
else
98 17 unneback
        tmp <= {1'b0,tmp[0]};
99
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
100 6 unneback
endmodule
101
 
102
// vl_pll
103
`ifdef ACTEL
104 17 unneback
`timescale 1 ps/1 ps
105 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
106
parameter index = 0;
107
parameter number_of_clk = 1;
108 17 unneback
parameter period_time_0 = 20000;
109
parameter period_time_1 = 20000;
110
parameter period_time_2 = 20000;
111
parameter lock_delay = 2000000;
112 6 unneback
input clk_i, rst_n_i;
113
output lock;
114
output reg [0:number_of_clk-1] clk_o;
115
output [0:number_of_clk-1] rst_o;
116
 
117
`ifdef SIM_PLL
118
 
119
always
120
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
121
 
122
generate if (number_of_clk > 1)
123
always
124
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
125
endgenerate
126
 
127
generate if (number_of_clk > 2)
128
always
129
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
130
endgenerate
131
 
132
genvar i;
133
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
134
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
135
end
136
endgenerate
137
 
138
assign #lock_delay lock = rst_n_i;
139
 
140
endmodule
141
`else
142
generate if (number_of_clk==1 & index==0) begin
143
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==1 & index==1) begin
147
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
148
end
149
endgenerate // index==1
150
generate if (number_of_clk==1 & index==2) begin
151
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
152
end
153
endgenerate // index==2
154
generate if (number_of_clk==1 & index==3) begin
155
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
156
end
157
endgenerate // index==0
158
 
159
generate if (number_of_clk==2 & index==0) begin
160
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
161
end
162
endgenerate // index==0
163
generate if (number_of_clk==2 & index==1) begin
164
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
165
end
166
endgenerate // index==1
167
generate if (number_of_clk==2 & index==2) begin
168
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
169
end
170
endgenerate // index==2
171
generate if (number_of_clk==2 & index==3) begin
172
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
173
end
174
endgenerate // index==0
175
 
176
generate if (number_of_clk==3 & index==0) begin
177
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
178
end
179
endgenerate // index==0
180
generate if (number_of_clk==3 & index==1) begin
181
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
182
end
183
endgenerate // index==1
184
generate if (number_of_clk==3 & index==2) begin
185
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
186
end
187
endgenerate // index==2
188
generate if (number_of_clk==3 & index==3) begin
189
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
190
end
191
endgenerate // index==0
192
 
193
genvar i;
194
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
195
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
196
end
197
endgenerate
198
endmodule
199
`endif
200
 
201
`else
202
 
203
`ifdef ALTERA
204
 
205
`else
206
 
207
// generic PLL
208 17 unneback
`timescale 1 ps/1 ps
209 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
210
parameter index = 0;
211
parameter number_of_clk = 1;
212 17 unneback
parameter period_time_0 = 20000;
213
parameter period_time_1 = 20000;
214
parameter period_time_2 = 20000;
215 6 unneback
parameter lock_delay = 2000;
216
input clk_i, rst_n_i;
217
output lock;
218
output reg [0:number_of_clk-1] clk_o;
219
output [0:number_of_clk-1] rst_o;
220
 
221
always
222
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
223
 
224
generate if (number_of_clk > 1)
225
always
226
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
227
endgenerate
228
 
229
generate if (number_of_clk > 2)
230
always
231
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
232
endgenerate
233
 
234
genvar i;
235
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
236
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
237
end
238
endgenerate
239
 
240
assign #lock_delay lock = rst_n_i;
241
 
242
endmodule
243
 
244
`endif //altera
245 17 unneback
`endif //actel
246
//////////////////////////////////////////////////////////////////////
247 6 unneback
////                                                              ////
248
////  Versatile library, registers                                ////
249
////                                                              ////
250
////  Description                                                 ////
251
////  Different type of registers                                 ////
252
////                                                              ////
253
////                                                              ////
254
////  To Do:                                                      ////
255
////   - add more different registers                             ////
256
////                                                              ////
257
////  Author(s):                                                  ////
258
////      - Michael Unneback, unneback@opencores.org              ////
259
////        ORSoC AB                                              ////
260
////                                                              ////
261
//////////////////////////////////////////////////////////////////////
262
////                                                              ////
263
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
264
////                                                              ////
265
//// This source file may be used and distributed without         ////
266
//// restriction provided that this copyright statement is not    ////
267
//// removed from the file and that any derivative work contains  ////
268
//// the original copyright notice and the associated disclaimer. ////
269
////                                                              ////
270
//// This source file is free software; you can redistribute it   ////
271
//// and/or modify it under the terms of the GNU Lesser General   ////
272
//// Public License as published by the Free Software Foundation; ////
273
//// either version 2.1 of the License, or (at your option) any   ////
274
//// later version.                                               ////
275
////                                                              ////
276
//// This source is distributed in the hope that it will be       ////
277
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
278
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
279
//// PURPOSE.  See the GNU Lesser General Public License for more ////
280
//// details.                                                     ////
281
////                                                              ////
282
//// You should have received a copy of the GNU Lesser General    ////
283
//// Public License along with this source; if not, download it   ////
284
//// from http://www.opencores.org/lgpl.shtml                     ////
285
////                                                              ////
286
//////////////////////////////////////////////////////////////////////
287
 
288 18 unneback
module vl_dff ( d, q, clk, rst);
289 6 unneback
 
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
 
293
        input [width-1:0] d;
294
        input clk, rst;
295
        output reg [width-1:0] q;
296
 
297
        always @ (posedge clk or posedge rst)
298
        if (rst)
299
                q <= reset_value;
300
        else
301
                q <= d;
302
 
303
endmodule
304
 
305 18 unneback
module vl_dff_array ( d, q, clk, rst);
306 6 unneback
 
307
        parameter width = 1;
308
        parameter depth = 2;
309
        parameter reset_value = 1'b0;
310
 
311
        input [width-1:0] d;
312
        input clk, rst;
313
        output [width-1:0] q;
314
        reg  [0:depth-1] q_tmp [width-1:0];
315
        integer i;
316
        always @ (posedge clk or posedge rst)
317
        if (rst) begin
318
            for (i=0;i<depth;i=i+1)
319
                q_tmp[i] <= {width{reset_value}};
320
        end else begin
321
            q_tmp[0] <= d;
322
            for (i=1;i<depth;i=i+1)
323
                q_tmp[i] <= q_tmp[i-1];
324
        end
325
 
326
    assign q = q_tmp[depth-1];
327
 
328
endmodule
329
 
330 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
331 6 unneback
 
332
        parameter width = 1;
333
        parameter reset_value = 0;
334
 
335
        input [width-1:0] d;
336
        input ce, clk, rst;
337
        output reg [width-1:0] q;
338
 
339
        always @ (posedge clk or posedge rst)
340
        if (rst)
341
                q <= reset_value;
342
        else
343
                if (ce)
344
                        q <= d;
345
 
346
endmodule
347
 
348 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
349 8 unneback
 
350
        parameter width = 1;
351
        parameter reset_value = 0;
352
 
353
        input [width-1:0] d;
354 10 unneback
        input ce, clear, clk, rst;
355 8 unneback
        output reg [width-1:0] q;
356
 
357
        always @ (posedge clk or posedge rst)
358
        if (rst)
359
            q <= reset_value;
360
        else
361
            if (ce)
362
                if (clear)
363
                    q <= {width{1'b0}};
364
                else
365
                    q <= d;
366
 
367
endmodule
368
 
369 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
370
 
371
        parameter width = 1;
372
        parameter reset_value = 0;
373
 
374
        input [width-1:0] d;
375
        input ce, set, clk, rst;
376
        output reg [width-1:0] q;
377
 
378
        always @ (posedge clk or posedge rst)
379
        if (rst)
380
            q <= reset_value;
381
        else
382
            if (ce)
383
                if (set)
384
                    q <= {width{1'b1}};
385
                else
386
                    q <= d;
387
 
388
endmodule
389
 
390 29 unneback
module vl_spr ( sp, r, q, clk, rst);
391
 
392
        parameter width = 1;
393
        parameter reset_value = 0;
394
 
395
        input sp, r;
396
        output reg q;
397
        input clk, rst;
398
 
399
        always @ (posedge clk or posedge rst)
400
        if (rst)
401
            q <= reset_value;
402
        else
403
            if (sp)
404
                q <= 1'b1;
405
            else if (r)
406
                q <= 1'b0;
407
 
408
endmodule
409
 
410
module vl_srp ( s, rp, q, clk, rst);
411
 
412
        parameter width = 1;
413
        parameter reset_value = 0;
414
 
415
        input s, rp;
416
        output reg q;
417
        input clk, rst;
418
 
419
        always @ (posedge clk or posedge rst)
420
        if (rst)
421
            q <= reset_value;
422
        else
423
            if (rp)
424
                q <= 1'b0;
425
            else if (s)
426
                q <= 1'b1;
427
 
428
endmodule
429
 
430
 
431 6 unneback
`ifdef ALTERA
432
// megafunction wizard: %LPM_FF%
433
// GENERATION: STANDARD
434
// VERSION: WM1.0
435
// MODULE: lpm_ff 
436
 
437
// ============================================================
438
// File Name: dff_sr.v
439
// Megafunction Name(s):
440
//                      lpm_ff
441
//
442
// Simulation Library Files(s):
443
//                      lpm
444
// ============================================================
445
// ************************************************************
446
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
447
//
448
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
449
// ************************************************************
450
 
451
 
452
//Copyright (C) 1991-2010 Altera Corporation
453
//Your use of Altera Corporation's design tools, logic functions 
454
//and other software and tools, and its AMPP partner logic 
455
//functions, and any output files from any of the foregoing 
456
//(including device programming or simulation files), and any 
457
//associated documentation or information are expressly subject 
458
//to the terms and conditions of the Altera Program License 
459
//Subscription Agreement, Altera MegaCore Function License 
460
//Agreement, or other applicable license agreement, including, 
461
//without limitation, that your use is for the sole purpose of 
462
//programming logic devices manufactured by Altera and sold by 
463
//Altera or its authorized distributors.  Please refer to the 
464
//applicable agreement for further details.
465
 
466
 
467
// synopsys translate_off
468
`timescale 1 ps / 1 ps
469
// synopsys translate_on
470 18 unneback
module vl_dff_sr (
471 6 unneback
        aclr,
472
        aset,
473
        clock,
474
        data,
475
        q);
476
 
477
        input     aclr;
478
        input     aset;
479
        input     clock;
480
        input     data;
481
        output    q;
482
 
483
        wire [0:0] sub_wire0;
484
        wire [0:0] sub_wire1 = sub_wire0[0:0];
485
        wire  q = sub_wire1;
486
        wire  sub_wire2 = data;
487
        wire  sub_wire3 = sub_wire2;
488
 
489
        lpm_ff  lpm_ff_component (
490
                                .aclr (aclr),
491
                                .clock (clock),
492
                                .data (sub_wire3),
493
                                .aset (aset),
494
                                .q (sub_wire0)
495
                                // synopsys translate_off
496
                                ,
497
                                .aload (),
498
                                .enable (),
499
                                .sclr (),
500
                                .sload (),
501
                                .sset ()
502
                                // synopsys translate_on
503
                                );
504
        defparam
505
                lpm_ff_component.lpm_fftype = "DFF",
506
                lpm_ff_component.lpm_type = "LPM_FF",
507
                lpm_ff_component.lpm_width = 1;
508
 
509
 
510
endmodule
511
 
512
// ============================================================
513
// CNX file retrieval info
514
// ============================================================
515
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
516
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
517
// Retrieval info: PRIVATE: ASET NUMERIC "1"
518
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
519
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
520
// Retrieval info: PRIVATE: DFF NUMERIC "1"
521
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
522
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
523
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
524
// Retrieval info: PRIVATE: SSET NUMERIC "0"
525
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
526
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
527
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
528
// Retrieval info: PRIVATE: nBit NUMERIC "1"
529
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
530
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
531
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
532
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
533
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
534
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
535
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
536
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
537
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
538
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
539
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
540
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
541
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
542
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
543
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
544
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
545
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
546
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
547
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
548
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
549
// Retrieval info: LIB_FILE: lpm
550
 
551
 
552
`else
553
 
554
 
555 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
556 6 unneback
 
557
    input         aclr;
558
    input         aset;
559
    input         clock;
560
    input         data;
561
    output reg    q;
562
 
563
   always @ (posedge clock or posedge aclr or posedge aset)
564
     if (aclr)
565
       q <= 1'b0;
566
     else if (aset)
567
       q <= 1'b1;
568
     else
569
       q <= data;
570
 
571
endmodule
572
 
573
`endif
574
 
575
// LATCH
576
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
577
`ifdef ALTERA
578 18 unneback
module vl_latch ( d, le, q, clk);
579 6 unneback
input d, le;
580
output q;
581
input clk;
582
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
583
endmodule
584
`else
585
module latch ( d, le, q, clk);
586
input d, le;
587
output q;
588
input clk;/*
589
   always @ (posedge direction_set or posedge direction_clr)
590
     if (direction_clr)
591
       direction <= going_empty;
592
     else
593
       direction <= going_full;*/
594
endmodule
595 15 unneback
`endif
596
 
597 18 unneback
module vl_shreg ( d, q, clk, rst);
598 17 unneback
parameter depth = 10;
599
input d;
600
output q;
601
input clk, rst;
602
 
603
reg [1:depth] dffs;
604
 
605
always @ (posedge clk or posedge rst)
606
if (rst)
607
    dffs <= {depth{1'b0}};
608
else
609
    dffs <= {d,dffs[1:depth-1]};
610
assign q = dffs[depth];
611
endmodule
612
 
613 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
614 17 unneback
parameter depth = 10;
615
input d, ce;
616
output q;
617
input clk, rst;
618
 
619
reg [1:depth] dffs;
620
 
621
always @ (posedge clk or posedge rst)
622
if (rst)
623
    dffs <= {depth{1'b0}};
624
else
625
    if (ce)
626
        dffs <= {d,dffs[1:depth-1]};
627
assign q = dffs[depth];
628
endmodule
629
 
630 18 unneback
module vl_delay ( d, q, clk, rst);
631 15 unneback
parameter depth = 10;
632
input d;
633
output q;
634
input clk, rst;
635
 
636
reg [1:depth] dffs;
637
 
638
always @ (posedge clk or posedge rst)
639
if (rst)
640
    dffs <= {depth{1'b0}};
641
else
642
    dffs <= {d,dffs[1:depth-1]};
643
assign q = dffs[depth];
644 17 unneback
endmodule
645
 
646 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
647 17 unneback
parameter depth = 10;
648
input d;
649
output q, emptyflag;
650
input clk, rst;
651
 
652
reg [1:depth] dffs;
653
 
654
always @ (posedge clk or posedge rst)
655
if (rst)
656
    dffs <= {depth{1'b0}};
657
else
658
    dffs <= {d,dffs[1:depth-1]};
659
assign q = dffs[depth];
660
assign emptyflag = !(|dffs);
661
endmodule
662
//////////////////////////////////////////////////////////////////////
663 6 unneback
////                                                              ////
664 18 unneback
////  Logic functions                                             ////
665
////                                                              ////
666
////  Description                                                 ////
667
////  Logic functions such as multiplexers                        ////
668
////                                                              ////
669
////                                                              ////
670
////  To Do:                                                      ////
671
////   -                                                          ////
672
////                                                              ////
673
////  Author(s):                                                  ////
674
////      - Michael Unneback, unneback@opencores.org              ////
675
////        ORSoC AB                                              ////
676
////                                                              ////
677
//////////////////////////////////////////////////////////////////////
678
////                                                              ////
679
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
680
////                                                              ////
681
//// This source file may be used and distributed without         ////
682
//// restriction provided that this copyright statement is not    ////
683
//// removed from the file and that any derivative work contains  ////
684
//// the original copyright notice and the associated disclaimer. ////
685
////                                                              ////
686
//// This source file is free software; you can redistribute it   ////
687
//// and/or modify it under the terms of the GNU Lesser General   ////
688
//// Public License as published by the Free Software Foundation; ////
689
//// either version 2.1 of the License, or (at your option) any   ////
690
//// later version.                                               ////
691
////                                                              ////
692
//// This source is distributed in the hope that it will be       ////
693
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
694
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
695
//// PURPOSE.  See the GNU Lesser General Public License for more ////
696
//// details.                                                     ////
697
////                                                              ////
698
//// You should have received a copy of the GNU Lesser General    ////
699
//// Public License along with this source; if not, download it   ////
700
//// from http://www.opencores.org/lgpl.shtml                     ////
701
////                                                              ////
702
//////////////////////////////////////////////////////////////////////
703
 
704
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
705
 
706
parameter width = 32;
707
parameter nr_of_ports = 4;
708
input [width-1:0] a3, a2, a1, a0;
709
input [nr_of_ports-1:0] sel;
710 22 unneback
output [width-1:0] dout;
711 18 unneback
 
712 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
713 18 unneback
integer i;
714
 
715
// and
716
assign tmp[0] = {width{sel[0]}} & a0;
717
assign tmp[1] = {width{sel[1]}} & a1;
718
assign tmp[2] = {width{sel[2]}} & a2;
719
assign tmp[3] = {width{sel[3]}} & a3;
720
 
721
// or
722
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
723
 
724
endmodule
725
 
726
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
727
 
728
parameter width = 32;
729
parameter nr_of_ports = 5;
730
input [width-1:0] a4, a3, a2, a1, a0;
731
input [nr_of_ports-1:0] sel;
732 22 unneback
output [width-1:0] dout;
733 18 unneback
 
734 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
735 18 unneback
integer i;
736
 
737
// and
738
assign tmp[0] = {width{sel[0]}} & a0;
739
assign tmp[1] = {width{sel[1]}} & a1;
740
assign tmp[2] = {width{sel[2]}} & a2;
741
assign tmp[3] = {width{sel[3]}} & a3;
742
assign tmp[4] = {width{sel[4]}} & a4;
743
 
744
// or
745
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
746
 
747
endmodule
748
 
749
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
750
 
751
parameter width = 32;
752
parameter nr_of_ports = 6;
753
input [width-1:0] a5, a4, a3, a2, a1, a0;
754
input [nr_of_ports-1:0] sel;
755 22 unneback
output [width-1:0] dout;
756 18 unneback
 
757 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
758 18 unneback
integer i;
759
 
760
// and
761
assign tmp[0] = {width{sel[0]}} & a0;
762
assign tmp[1] = {width{sel[1]}} & a1;
763
assign tmp[2] = {width{sel[2]}} & a2;
764
assign tmp[3] = {width{sel[3]}} & a3;
765
assign tmp[4] = {width{sel[4]}} & a4;
766
assign tmp[5] = {width{sel[5]}} & a5;
767
 
768
// or
769
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
770
 
771
endmodule
772
//////////////////////////////////////////////////////////////////////
773
////                                                              ////
774 6 unneback
////  Versatile counter                                           ////
775
////                                                              ////
776
////  Description                                                 ////
777
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
778
////  counter                                                     ////
779
////                                                              ////
780
////  To Do:                                                      ////
781
////   - add LFSR with more taps                                  ////
782
////                                                              ////
783
////  Author(s):                                                  ////
784
////      - Michael Unneback, unneback@opencores.org              ////
785
////        ORSoC AB                                              ////
786
////                                                              ////
787
//////////////////////////////////////////////////////////////////////
788
////                                                              ////
789
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
790
////                                                              ////
791
//// This source file may be used and distributed without         ////
792
//// restriction provided that this copyright statement is not    ////
793
//// removed from the file and that any derivative work contains  ////
794
//// the original copyright notice and the associated disclaimer. ////
795
////                                                              ////
796
//// This source file is free software; you can redistribute it   ////
797
//// and/or modify it under the terms of the GNU Lesser General   ////
798
//// Public License as published by the Free Software Foundation; ////
799
//// either version 2.1 of the License, or (at your option) any   ////
800
//// later version.                                               ////
801
////                                                              ////
802
//// This source is distributed in the hope that it will be       ////
803
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
804
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
805
//// PURPOSE.  See the GNU Lesser General Public License for more ////
806
//// details.                                                     ////
807
////                                                              ////
808
//// You should have received a copy of the GNU Lesser General    ////
809
//// Public License along with this source; if not, download it   ////
810
//// from http://www.opencores.org/lgpl.shtml                     ////
811
////                                                              ////
812
//////////////////////////////////////////////////////////////////////
813
 
814
// binary counter
815 22 unneback
module vl_cnt_bin ( q, rst, clk);
816
 
817
   parameter length = 4;
818
   output [length:1] q;
819
   input rst;
820
   input clk;
821
 
822
   parameter clear_value = 0;
823
   parameter set_value = 1;
824
   parameter wrap_value = 0;
825
   parameter level1_value = 15;
826
 
827
   reg  [length:1] qi;
828
   wire [length:1] q_next;
829
   assign q_next = qi + {{length-1{1'b0}},1'b1};
830
 
831
   always @ (posedge clk or posedge rst)
832
     if (rst)
833
       qi <= {length{1'b0}};
834
     else
835
       qi <= q_next;
836
 
837
   assign q = qi;
838
 
839
endmodule
840
//////////////////////////////////////////////////////////////////////
841
////                                                              ////
842
////  Versatile counter                                           ////
843
////                                                              ////
844
////  Description                                                 ////
845
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
846
////  counter                                                     ////
847
////                                                              ////
848
////  To Do:                                                      ////
849
////   - add LFSR with more taps                                  ////
850
////                                                              ////
851
////  Author(s):                                                  ////
852
////      - Michael Unneback, unneback@opencores.org              ////
853
////        ORSoC AB                                              ////
854
////                                                              ////
855
//////////////////////////////////////////////////////////////////////
856
////                                                              ////
857
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
858
////                                                              ////
859
//// This source file may be used and distributed without         ////
860
//// restriction provided that this copyright statement is not    ////
861
//// removed from the file and that any derivative work contains  ////
862
//// the original copyright notice and the associated disclaimer. ////
863
////                                                              ////
864
//// This source file is free software; you can redistribute it   ////
865
//// and/or modify it under the terms of the GNU Lesser General   ////
866
//// Public License as published by the Free Software Foundation; ////
867
//// either version 2.1 of the License, or (at your option) any   ////
868
//// later version.                                               ////
869
////                                                              ////
870
//// This source is distributed in the hope that it will be       ////
871
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
872
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
873
//// PURPOSE.  See the GNU Lesser General Public License for more ////
874
//// details.                                                     ////
875
////                                                              ////
876
//// You should have received a copy of the GNU Lesser General    ////
877
//// Public License along with this source; if not, download it   ////
878
//// from http://www.opencores.org/lgpl.shtml                     ////
879
////                                                              ////
880
//////////////////////////////////////////////////////////////////////
881
 
882
// binary counter
883
module vl_cnt_bin_clear ( clear, q, rst, clk);
884
 
885
   parameter length = 4;
886
   input clear;
887
   output [length:1] q;
888
   input rst;
889
   input clk;
890
 
891
   parameter clear_value = 0;
892
   parameter set_value = 1;
893
   parameter wrap_value = 0;
894
   parameter level1_value = 15;
895
 
896
   reg  [length:1] qi;
897
   wire [length:1] q_next;
898
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
899
 
900
   always @ (posedge clk or posedge rst)
901
     if (rst)
902
       qi <= {length{1'b0}};
903
     else
904
       qi <= q_next;
905
 
906
   assign q = qi;
907
 
908
endmodule
909
//////////////////////////////////////////////////////////////////////
910
////                                                              ////
911
////  Versatile counter                                           ////
912
////                                                              ////
913
////  Description                                                 ////
914
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
915
////  counter                                                     ////
916
////                                                              ////
917
////  To Do:                                                      ////
918
////   - add LFSR with more taps                                  ////
919
////                                                              ////
920
////  Author(s):                                                  ////
921
////      - Michael Unneback, unneback@opencores.org              ////
922
////        ORSoC AB                                              ////
923
////                                                              ////
924
//////////////////////////////////////////////////////////////////////
925
////                                                              ////
926
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
927
////                                                              ////
928
//// This source file may be used and distributed without         ////
929
//// restriction provided that this copyright statement is not    ////
930
//// removed from the file and that any derivative work contains  ////
931
//// the original copyright notice and the associated disclaimer. ////
932
////                                                              ////
933
//// This source file is free software; you can redistribute it   ////
934
//// and/or modify it under the terms of the GNU Lesser General   ////
935
//// Public License as published by the Free Software Foundation; ////
936
//// either version 2.1 of the License, or (at your option) any   ////
937
//// later version.                                               ////
938
////                                                              ////
939
//// This source is distributed in the hope that it will be       ////
940
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
941
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
942
//// PURPOSE.  See the GNU Lesser General Public License for more ////
943
//// details.                                                     ////
944
////                                                              ////
945
//// You should have received a copy of the GNU Lesser General    ////
946
//// Public License along with this source; if not, download it   ////
947
//// from http://www.opencores.org/lgpl.shtml                     ////
948
////                                                              ////
949
//////////////////////////////////////////////////////////////////////
950
 
951
// binary counter
952 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
953 6 unneback
 
954
   parameter length = 4;
955
   input cke;
956
   output [length:1] q;
957
   input rst;
958
   input clk;
959
 
960
   parameter clear_value = 0;
961
   parameter set_value = 1;
962
   parameter wrap_value = 0;
963
   parameter level1_value = 15;
964
 
965
   reg  [length:1] qi;
966
   wire [length:1] q_next;
967
   assign q_next = qi + {{length-1{1'b0}},1'b1};
968
 
969
   always @ (posedge clk or posedge rst)
970
     if (rst)
971
       qi <= {length{1'b0}};
972
     else
973
     if (cke)
974
       qi <= q_next;
975
 
976
   assign q = qi;
977
 
978
endmodule
979
//////////////////////////////////////////////////////////////////////
980
////                                                              ////
981
////  Versatile counter                                           ////
982
////                                                              ////
983
////  Description                                                 ////
984
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
985
////  counter                                                     ////
986
////                                                              ////
987
////  To Do:                                                      ////
988
////   - add LFSR with more taps                                  ////
989
////                                                              ////
990
////  Author(s):                                                  ////
991
////      - Michael Unneback, unneback@opencores.org              ////
992
////        ORSoC AB                                              ////
993
////                                                              ////
994
//////////////////////////////////////////////////////////////////////
995
////                                                              ////
996
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
997
////                                                              ////
998
//// This source file may be used and distributed without         ////
999
//// restriction provided that this copyright statement is not    ////
1000
//// removed from the file and that any derivative work contains  ////
1001
//// the original copyright notice and the associated disclaimer. ////
1002
////                                                              ////
1003
//// This source file is free software; you can redistribute it   ////
1004
//// and/or modify it under the terms of the GNU Lesser General   ////
1005
//// Public License as published by the Free Software Foundation; ////
1006
//// either version 2.1 of the License, or (at your option) any   ////
1007
//// later version.                                               ////
1008
////                                                              ////
1009
//// This source is distributed in the hope that it will be       ////
1010
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1011
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1012
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1013
//// details.                                                     ////
1014
////                                                              ////
1015
//// You should have received a copy of the GNU Lesser General    ////
1016
//// Public License along with this source; if not, download it   ////
1017
//// from http://www.opencores.org/lgpl.shtml                     ////
1018
////                                                              ////
1019
//////////////////////////////////////////////////////////////////////
1020
 
1021
// binary counter
1022 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
1023 6 unneback
 
1024
   parameter length = 4;
1025
   input clear;
1026
   input cke;
1027
   output [length:1] q;
1028
   input rst;
1029
   input clk;
1030
 
1031
   parameter clear_value = 0;
1032
   parameter set_value = 1;
1033
   parameter wrap_value = 0;
1034
   parameter level1_value = 15;
1035
 
1036
   reg  [length:1] qi;
1037
   wire [length:1] q_next;
1038
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1039
 
1040
   always @ (posedge clk or posedge rst)
1041
     if (rst)
1042
       qi <= {length{1'b0}};
1043
     else
1044
     if (cke)
1045
       qi <= q_next;
1046
 
1047
   assign q = qi;
1048
 
1049
endmodule
1050
//////////////////////////////////////////////////////////////////////
1051
////                                                              ////
1052
////  Versatile counter                                           ////
1053
////                                                              ////
1054
////  Description                                                 ////
1055
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1056
////  counter                                                     ////
1057
////                                                              ////
1058
////  To Do:                                                      ////
1059
////   - add LFSR with more taps                                  ////
1060
////                                                              ////
1061
////  Author(s):                                                  ////
1062
////      - Michael Unneback, unneback@opencores.org              ////
1063
////        ORSoC AB                                              ////
1064
////                                                              ////
1065
//////////////////////////////////////////////////////////////////////
1066
////                                                              ////
1067
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1068
////                                                              ////
1069
//// This source file may be used and distributed without         ////
1070
//// restriction provided that this copyright statement is not    ////
1071
//// removed from the file and that any derivative work contains  ////
1072
//// the original copyright notice and the associated disclaimer. ////
1073
////                                                              ////
1074
//// This source file is free software; you can redistribute it   ////
1075
//// and/or modify it under the terms of the GNU Lesser General   ////
1076
//// Public License as published by the Free Software Foundation; ////
1077
//// either version 2.1 of the License, or (at your option) any   ////
1078
//// later version.                                               ////
1079
////                                                              ////
1080
//// This source is distributed in the hope that it will be       ////
1081
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1082
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1083
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1084
//// details.                                                     ////
1085
////                                                              ////
1086
//// You should have received a copy of the GNU Lesser General    ////
1087
//// Public License along with this source; if not, download it   ////
1088
//// from http://www.opencores.org/lgpl.shtml                     ////
1089
////                                                              ////
1090
//////////////////////////////////////////////////////////////////////
1091
 
1092
// binary counter
1093 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
1094
 
1095
   parameter length = 4;
1096
   input clear;
1097
   input cke;
1098
   output [length:1] q;
1099
   output reg level1;
1100
   output reg level2;
1101
   input rst;
1102
   input clk;
1103
 
1104
   parameter clear_value = 0;
1105
   parameter set_value = 1;
1106
   parameter wrap_value = 7;
1107
   parameter level1_value = 15;
1108
 
1109
   wire rew;
1110
   assign rew=1'b0;
1111
   reg  [length:1] qi;
1112
   wire [length:1] q_next;
1113
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1114
 
1115
   always @ (posedge clk or posedge rst)
1116
     if (rst)
1117
       qi <= {length{1'b0}};
1118
     else
1119
     if (cke)
1120
       qi <= q_next;
1121
 
1122
   assign q = qi;
1123
 
1124
 
1125
    always @ (posedge clk or posedge rst)
1126
    if (rst)
1127
        level1 <= 1'b0;
1128
    else
1129
    if (cke)
1130
    if (clear)
1131
        level1 <= 1'b0;
1132
    else if (q_next == level1_value)
1133
        level1 <= 1'b1;
1134
    else if (qi == level1_value & rew)
1135
        level1 <= 1'b0;
1136
 
1137
    always @ (posedge clk or posedge rst)
1138
    if (rst)
1139
        level2 <= 1'b0;
1140
    else
1141
    if (cke)
1142
    if (clear)
1143
        level2 <= 1'b0;
1144
    else if (q_next == level2_value)
1145
        level2 <= 1'b1;
1146
    else if (qi == level2_value & rew)
1147
        level2 <= 1'b0;
1148
endmodule
1149
//////////////////////////////////////////////////////////////////////
1150
////                                                              ////
1151
////  Versatile counter                                           ////
1152
////                                                              ////
1153
////  Description                                                 ////
1154
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1155
////  counter                                                     ////
1156
////                                                              ////
1157
////  To Do:                                                      ////
1158
////   - add LFSR with more taps                                  ////
1159
////                                                              ////
1160
////  Author(s):                                                  ////
1161
////      - Michael Unneback, unneback@opencores.org              ////
1162
////        ORSoC AB                                              ////
1163
////                                                              ////
1164
//////////////////////////////////////////////////////////////////////
1165
////                                                              ////
1166
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1167
////                                                              ////
1168
//// This source file may be used and distributed without         ////
1169
//// restriction provided that this copyright statement is not    ////
1170
//// removed from the file and that any derivative work contains  ////
1171
//// the original copyright notice and the associated disclaimer. ////
1172
////                                                              ////
1173
//// This source file is free software; you can redistribute it   ////
1174
//// and/or modify it under the terms of the GNU Lesser General   ////
1175
//// Public License as published by the Free Software Foundation; ////
1176
//// either version 2.1 of the License, or (at your option) any   ////
1177
//// later version.                                               ////
1178
////                                                              ////
1179
//// This source is distributed in the hope that it will be       ////
1180
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1181
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1182
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1183
//// details.                                                     ////
1184
////                                                              ////
1185
//// You should have received a copy of the GNU Lesser General    ////
1186
//// Public License along with this source; if not, download it   ////
1187
//// from http://www.opencores.org/lgpl.shtml                     ////
1188
////                                                              ////
1189
//////////////////////////////////////////////////////////////////////
1190
 
1191
// binary counter
1192 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
1193 6 unneback
 
1194
   parameter length = 4;
1195
   input clear;
1196
   input set;
1197
   input cke;
1198
   input rew;
1199
   output [length:1] q;
1200
   input rst;
1201
   input clk;
1202
 
1203
   parameter clear_value = 0;
1204
   parameter set_value = 1;
1205
   parameter wrap_value = 0;
1206
   parameter level1_value = 15;
1207
 
1208
   reg  [length:1] qi;
1209
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1210
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1211
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1212
   assign q_next = rew ? q_next_rew : q_next_fw;
1213
 
1214
   always @ (posedge clk or posedge rst)
1215
     if (rst)
1216
       qi <= {length{1'b0}};
1217
     else
1218
     if (cke)
1219
       qi <= q_next;
1220
 
1221
   assign q = qi;
1222
 
1223
endmodule
1224
//////////////////////////////////////////////////////////////////////
1225
////                                                              ////
1226
////  Versatile counter                                           ////
1227
////                                                              ////
1228
////  Description                                                 ////
1229
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1230
////  counter                                                     ////
1231
////                                                              ////
1232
////  To Do:                                                      ////
1233
////   - add LFSR with more taps                                  ////
1234
////                                                              ////
1235
////  Author(s):                                                  ////
1236
////      - Michael Unneback, unneback@opencores.org              ////
1237
////        ORSoC AB                                              ////
1238
////                                                              ////
1239
//////////////////////////////////////////////////////////////////////
1240
////                                                              ////
1241
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1242
////                                                              ////
1243
//// This source file may be used and distributed without         ////
1244
//// restriction provided that this copyright statement is not    ////
1245
//// removed from the file and that any derivative work contains  ////
1246
//// the original copyright notice and the associated disclaimer. ////
1247
////                                                              ////
1248
//// This source file is free software; you can redistribute it   ////
1249
//// and/or modify it under the terms of the GNU Lesser General   ////
1250
//// Public License as published by the Free Software Foundation; ////
1251
//// either version 2.1 of the License, or (at your option) any   ////
1252
//// later version.                                               ////
1253
////                                                              ////
1254
//// This source is distributed in the hope that it will be       ////
1255
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1256
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1257
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1258
//// details.                                                     ////
1259
////                                                              ////
1260
//// You should have received a copy of the GNU Lesser General    ////
1261
//// Public License along with this source; if not, download it   ////
1262
//// from http://www.opencores.org/lgpl.shtml                     ////
1263
////                                                              ////
1264
//////////////////////////////////////////////////////////////////////
1265
 
1266
// binary counter
1267 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1268 6 unneback
 
1269
   parameter length = 4;
1270
   input cke;
1271
   input rew;
1272
   output reg level1;
1273
   input rst;
1274
   input clk;
1275
 
1276
   parameter clear_value = 0;
1277
   parameter set_value = 1;
1278
   parameter wrap_value = 1;
1279
   parameter level1_value = 15;
1280
 
1281 29 unneback
   wire clear;
1282
   assign clear=1'b0;
1283 6 unneback
   reg  [length:1] qi;
1284
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1285
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1286
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1287
   assign q_next = rew ? q_next_rew : q_next_fw;
1288
 
1289
   always @ (posedge clk or posedge rst)
1290
     if (rst)
1291
       qi <= {length{1'b0}};
1292
     else
1293
     if (cke)
1294
       qi <= q_next;
1295
 
1296
 
1297
 
1298
    always @ (posedge clk or posedge rst)
1299
    if (rst)
1300
        level1 <= 1'b0;
1301
    else
1302
    if (cke)
1303 29 unneback
    if (clear)
1304
        level1 <= 1'b0;
1305
    else if (q_next == level1_value)
1306 6 unneback
        level1 <= 1'b1;
1307
    else if (qi == level1_value & rew)
1308
        level1 <= 1'b0;
1309
endmodule
1310
//////////////////////////////////////////////////////////////////////
1311
////                                                              ////
1312
////  Versatile counter                                           ////
1313
////                                                              ////
1314
////  Description                                                 ////
1315
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1316
////  counter                                                     ////
1317
////                                                              ////
1318
////  To Do:                                                      ////
1319
////   - add LFSR with more taps                                  ////
1320
////                                                              ////
1321
////  Author(s):                                                  ////
1322
////      - Michael Unneback, unneback@opencores.org              ////
1323
////        ORSoC AB                                              ////
1324
////                                                              ////
1325
//////////////////////////////////////////////////////////////////////
1326
////                                                              ////
1327
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1328
////                                                              ////
1329
//// This source file may be used and distributed without         ////
1330
//// restriction provided that this copyright statement is not    ////
1331
//// removed from the file and that any derivative work contains  ////
1332
//// the original copyright notice and the associated disclaimer. ////
1333
////                                                              ////
1334
//// This source file is free software; you can redistribute it   ////
1335
//// and/or modify it under the terms of the GNU Lesser General   ////
1336
//// Public License as published by the Free Software Foundation; ////
1337
//// either version 2.1 of the License, or (at your option) any   ////
1338
//// later version.                                               ////
1339
////                                                              ////
1340
//// This source is distributed in the hope that it will be       ////
1341
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1342
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1343
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1344
//// details.                                                     ////
1345
////                                                              ////
1346
//// You should have received a copy of the GNU Lesser General    ////
1347
//// Public License along with this source; if not, download it   ////
1348
//// from http://www.opencores.org/lgpl.shtml                     ////
1349
////                                                              ////
1350
//////////////////////////////////////////////////////////////////////
1351
 
1352 25 unneback
// binary counter
1353
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1354
 
1355
   parameter length = 4;
1356
   input cke;
1357
   input rew;
1358
   output reg zq;
1359
   output reg level1;
1360
   input rst;
1361
   input clk;
1362
 
1363
   parameter clear_value = 0;
1364
   parameter set_value = 1;
1365
   parameter wrap_value = 1;
1366
   parameter level1_value = 15;
1367
 
1368 29 unneback
   wire clear;
1369
   assign clear=1'b0;
1370 25 unneback
   reg  [length:1] qi;
1371
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1372
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1373
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1374
   assign q_next = rew ? q_next_rew : q_next_fw;
1375
 
1376
   always @ (posedge clk or posedge rst)
1377
     if (rst)
1378
       qi <= {length{1'b0}};
1379
     else
1380
     if (cke)
1381
       qi <= q_next;
1382
 
1383
 
1384
 
1385
   always @ (posedge clk or posedge rst)
1386
     if (rst)
1387
       zq <= 1'b1;
1388
     else
1389
     if (cke)
1390
       zq <= q_next == {length{1'b0}};
1391
 
1392
    always @ (posedge clk or posedge rst)
1393
    if (rst)
1394
        level1 <= 1'b0;
1395
    else
1396
    if (cke)
1397 29 unneback
    if (clear)
1398
        level1 <= 1'b0;
1399
    else if (q_next == level1_value)
1400 25 unneback
        level1 <= 1'b1;
1401
    else if (qi == level1_value & rew)
1402
        level1 <= 1'b0;
1403
endmodule
1404
//////////////////////////////////////////////////////////////////////
1405
////                                                              ////
1406
////  Versatile counter                                           ////
1407
////                                                              ////
1408
////  Description                                                 ////
1409
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1410
////  counter                                                     ////
1411
////                                                              ////
1412
////  To Do:                                                      ////
1413
////   - add LFSR with more taps                                  ////
1414
////                                                              ////
1415
////  Author(s):                                                  ////
1416
////      - Michael Unneback, unneback@opencores.org              ////
1417
////        ORSoC AB                                              ////
1418
////                                                              ////
1419
//////////////////////////////////////////////////////////////////////
1420
////                                                              ////
1421
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1422
////                                                              ////
1423
//// This source file may be used and distributed without         ////
1424
//// restriction provided that this copyright statement is not    ////
1425
//// removed from the file and that any derivative work contains  ////
1426
//// the original copyright notice and the associated disclaimer. ////
1427
////                                                              ////
1428
//// This source file is free software; you can redistribute it   ////
1429
//// and/or modify it under the terms of the GNU Lesser General   ////
1430
//// Public License as published by the Free Software Foundation; ////
1431
//// either version 2.1 of the License, or (at your option) any   ////
1432
//// later version.                                               ////
1433
////                                                              ////
1434
//// This source is distributed in the hope that it will be       ////
1435
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1436
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1437
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1438
//// details.                                                     ////
1439
////                                                              ////
1440
//// You should have received a copy of the GNU Lesser General    ////
1441
//// Public License along with this source; if not, download it   ////
1442
//// from http://www.opencores.org/lgpl.shtml                     ////
1443
////                                                              ////
1444
//////////////////////////////////////////////////////////////////////
1445
 
1446
// binary counter
1447
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1448
 
1449
   parameter length = 4;
1450
   input cke;
1451
   input rew;
1452
   output [length:1] q;
1453
   output reg zq;
1454
   output reg level1;
1455
   input rst;
1456
   input clk;
1457
 
1458
   parameter clear_value = 0;
1459
   parameter set_value = 1;
1460
   parameter wrap_value = 1;
1461
   parameter level1_value = 15;
1462
 
1463 29 unneback
   wire clear;
1464
   assign clear=1'b0;
1465 25 unneback
   reg  [length:1] qi;
1466
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1467
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1468
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1469
   assign q_next = rew ? q_next_rew : q_next_fw;
1470
 
1471
   always @ (posedge clk or posedge rst)
1472
     if (rst)
1473
       qi <= {length{1'b0}};
1474
     else
1475
     if (cke)
1476
       qi <= q_next;
1477
 
1478
   assign q = qi;
1479
 
1480
 
1481
   always @ (posedge clk or posedge rst)
1482
     if (rst)
1483
       zq <= 1'b1;
1484
     else
1485
     if (cke)
1486
       zq <= q_next == {length{1'b0}};
1487
 
1488
    always @ (posedge clk or posedge rst)
1489
    if (rst)
1490
        level1 <= 1'b0;
1491
    else
1492
    if (cke)
1493 29 unneback
    if (clear)
1494
        level1 <= 1'b0;
1495
    else if (q_next == level1_value)
1496 25 unneback
        level1 <= 1'b1;
1497
    else if (qi == level1_value & rew)
1498
        level1 <= 1'b0;
1499
endmodule
1500
//////////////////////////////////////////////////////////////////////
1501
////                                                              ////
1502
////  Versatile counter                                           ////
1503
////                                                              ////
1504
////  Description                                                 ////
1505
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1506
////  counter                                                     ////
1507
////                                                              ////
1508
////  To Do:                                                      ////
1509
////   - add LFSR with more taps                                  ////
1510
////                                                              ////
1511
////  Author(s):                                                  ////
1512
////      - Michael Unneback, unneback@opencores.org              ////
1513
////        ORSoC AB                                              ////
1514
////                                                              ////
1515
//////////////////////////////////////////////////////////////////////
1516
////                                                              ////
1517
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1518
////                                                              ////
1519
//// This source file may be used and distributed without         ////
1520
//// restriction provided that this copyright statement is not    ////
1521
//// removed from the file and that any derivative work contains  ////
1522
//// the original copyright notice and the associated disclaimer. ////
1523
////                                                              ////
1524
//// This source file is free software; you can redistribute it   ////
1525
//// and/or modify it under the terms of the GNU Lesser General   ////
1526
//// Public License as published by the Free Software Foundation; ////
1527
//// either version 2.1 of the License, or (at your option) any   ////
1528
//// later version.                                               ////
1529
////                                                              ////
1530
//// This source is distributed in the hope that it will be       ////
1531
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1532
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1533
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1534
//// details.                                                     ////
1535
////                                                              ////
1536
//// You should have received a copy of the GNU Lesser General    ////
1537
//// Public License along with this source; if not, download it   ////
1538
//// from http://www.opencores.org/lgpl.shtml                     ////
1539
////                                                              ////
1540
//////////////////////////////////////////////////////////////////////
1541
 
1542 6 unneback
// LFSR counter
1543 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1544 6 unneback
 
1545
   parameter length = 4;
1546
   output reg zq;
1547
   input rst;
1548
   input clk;
1549
 
1550
   parameter clear_value = 0;
1551
   parameter set_value = 1;
1552
   parameter wrap_value = 8;
1553
   parameter level1_value = 15;
1554
 
1555
   reg  [length:1] qi;
1556
   reg lfsr_fb;
1557
   wire [length:1] q_next;
1558
   reg [32:1] polynom;
1559
   integer i;
1560
 
1561
   always @ (qi)
1562
   begin
1563
        case (length)
1564
         2: polynom = 32'b11;                               // 0x3
1565
         3: polynom = 32'b110;                              // 0x6
1566
         4: polynom = 32'b1100;                             // 0xC
1567
         5: polynom = 32'b10100;                            // 0x14
1568
         6: polynom = 32'b110000;                           // 0x30
1569
         7: polynom = 32'b1100000;                          // 0x60
1570
         8: polynom = 32'b10111000;                         // 0xb8
1571
         9: polynom = 32'b100010000;                        // 0x110
1572
        10: polynom = 32'b1001000000;                       // 0x240
1573
        11: polynom = 32'b10100000000;                      // 0x500
1574
        12: polynom = 32'b100000101001;                     // 0x829
1575
        13: polynom = 32'b1000000001100;                    // 0x100C
1576
        14: polynom = 32'b10000000010101;                   // 0x2015
1577
        15: polynom = 32'b110000000000000;                  // 0x6000
1578
        16: polynom = 32'b1101000000001000;                 // 0xD008
1579
        17: polynom = 32'b10010000000000000;                // 0x12000
1580
        18: polynom = 32'b100000010000000000;               // 0x20400
1581
        19: polynom = 32'b1000000000000100011;              // 0x40023
1582
        20: polynom = 32'b10000010000000000000;             // 0x82000
1583
        21: polynom = 32'b101000000000000000000;            // 0x140000
1584
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1585
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1586
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1587
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1588
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1589
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1590
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1591
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1592
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1593
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1594
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1595
        default: polynom = 32'b0;
1596
        endcase
1597
        lfsr_fb = qi[length];
1598
        for (i=length-1; i>=1; i=i-1) begin
1599
            if (polynom[i])
1600
                lfsr_fb = lfsr_fb  ~^ qi[i];
1601
        end
1602
    end
1603
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1604
 
1605
   always @ (posedge clk or posedge rst)
1606
     if (rst)
1607
       qi <= {length{1'b0}};
1608
     else
1609
       qi <= q_next;
1610
 
1611
 
1612
 
1613
   always @ (posedge clk or posedge rst)
1614
     if (rst)
1615
       zq <= 1'b1;
1616
     else
1617
       zq <= q_next == {length{1'b0}};
1618
endmodule
1619
//////////////////////////////////////////////////////////////////////
1620
////                                                              ////
1621
////  Versatile counter                                           ////
1622
////                                                              ////
1623
////  Description                                                 ////
1624
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1625
////  counter                                                     ////
1626
////                                                              ////
1627
////  To Do:                                                      ////
1628
////   - add LFSR with more taps                                  ////
1629
////                                                              ////
1630
////  Author(s):                                                  ////
1631
////      - Michael Unneback, unneback@opencores.org              ////
1632
////        ORSoC AB                                              ////
1633
////                                                              ////
1634
//////////////////////////////////////////////////////////////////////
1635
////                                                              ////
1636
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1637
////                                                              ////
1638
//// This source file may be used and distributed without         ////
1639
//// restriction provided that this copyright statement is not    ////
1640
//// removed from the file and that any derivative work contains  ////
1641
//// the original copyright notice and the associated disclaimer. ////
1642
////                                                              ////
1643
//// This source file is free software; you can redistribute it   ////
1644
//// and/or modify it under the terms of the GNU Lesser General   ////
1645
//// Public License as published by the Free Software Foundation; ////
1646
//// either version 2.1 of the License, or (at your option) any   ////
1647
//// later version.                                               ////
1648
////                                                              ////
1649
//// This source is distributed in the hope that it will be       ////
1650
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1651
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1652
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1653
//// details.                                                     ////
1654
////                                                              ////
1655
//// You should have received a copy of the GNU Lesser General    ////
1656
//// Public License along with this source; if not, download it   ////
1657
//// from http://www.opencores.org/lgpl.shtml                     ////
1658
////                                                              ////
1659
//////////////////////////////////////////////////////////////////////
1660
 
1661
// LFSR counter
1662 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1663 6 unneback
 
1664
   parameter length = 4;
1665
   input cke;
1666
   output reg zq;
1667
   input rst;
1668
   input clk;
1669
 
1670
   parameter clear_value = 0;
1671
   parameter set_value = 1;
1672
   parameter wrap_value = 8;
1673
   parameter level1_value = 15;
1674
 
1675
   reg  [length:1] qi;
1676
   reg lfsr_fb;
1677
   wire [length:1] q_next;
1678
   reg [32:1] polynom;
1679
   integer i;
1680
 
1681
   always @ (qi)
1682
   begin
1683
        case (length)
1684
         2: polynom = 32'b11;                               // 0x3
1685
         3: polynom = 32'b110;                              // 0x6
1686
         4: polynom = 32'b1100;                             // 0xC
1687
         5: polynom = 32'b10100;                            // 0x14
1688
         6: polynom = 32'b110000;                           // 0x30
1689
         7: polynom = 32'b1100000;                          // 0x60
1690
         8: polynom = 32'b10111000;                         // 0xb8
1691
         9: polynom = 32'b100010000;                        // 0x110
1692
        10: polynom = 32'b1001000000;                       // 0x240
1693
        11: polynom = 32'b10100000000;                      // 0x500
1694
        12: polynom = 32'b100000101001;                     // 0x829
1695
        13: polynom = 32'b1000000001100;                    // 0x100C
1696
        14: polynom = 32'b10000000010101;                   // 0x2015
1697
        15: polynom = 32'b110000000000000;                  // 0x6000
1698
        16: polynom = 32'b1101000000001000;                 // 0xD008
1699
        17: polynom = 32'b10010000000000000;                // 0x12000
1700
        18: polynom = 32'b100000010000000000;               // 0x20400
1701
        19: polynom = 32'b1000000000000100011;              // 0x40023
1702
        20: polynom = 32'b10000010000000000000;             // 0x82000
1703
        21: polynom = 32'b101000000000000000000;            // 0x140000
1704
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1705
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1706
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1707
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1708
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1709
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1710
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1711
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1712
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1713
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1714
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1715
        default: polynom = 32'b0;
1716
        endcase
1717
        lfsr_fb = qi[length];
1718
        for (i=length-1; i>=1; i=i-1) begin
1719
            if (polynom[i])
1720
                lfsr_fb = lfsr_fb  ~^ qi[i];
1721
        end
1722
    end
1723
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1724
 
1725
   always @ (posedge clk or posedge rst)
1726
     if (rst)
1727
       qi <= {length{1'b0}};
1728
     else
1729
     if (cke)
1730
       qi <= q_next;
1731
 
1732
 
1733
 
1734
   always @ (posedge clk or posedge rst)
1735
     if (rst)
1736
       zq <= 1'b1;
1737
     else
1738
     if (cke)
1739
       zq <= q_next == {length{1'b0}};
1740
endmodule
1741
//////////////////////////////////////////////////////////////////////
1742
////                                                              ////
1743
////  Versatile counter                                           ////
1744
////                                                              ////
1745
////  Description                                                 ////
1746
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1747
////  counter                                                     ////
1748
////                                                              ////
1749
////  To Do:                                                      ////
1750
////   - add LFSR with more taps                                  ////
1751
////                                                              ////
1752
////  Author(s):                                                  ////
1753
////      - Michael Unneback, unneback@opencores.org              ////
1754
////        ORSoC AB                                              ////
1755
////                                                              ////
1756
//////////////////////////////////////////////////////////////////////
1757
////                                                              ////
1758
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1759
////                                                              ////
1760
//// This source file may be used and distributed without         ////
1761
//// restriction provided that this copyright statement is not    ////
1762
//// removed from the file and that any derivative work contains  ////
1763
//// the original copyright notice and the associated disclaimer. ////
1764
////                                                              ////
1765
//// This source file is free software; you can redistribute it   ////
1766
//// and/or modify it under the terms of the GNU Lesser General   ////
1767
//// Public License as published by the Free Software Foundation; ////
1768
//// either version 2.1 of the License, or (at your option) any   ////
1769
//// later version.                                               ////
1770
////                                                              ////
1771
//// This source is distributed in the hope that it will be       ////
1772
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1773
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1774
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1775
//// details.                                                     ////
1776
////                                                              ////
1777
//// You should have received a copy of the GNU Lesser General    ////
1778
//// Public License along with this source; if not, download it   ////
1779
//// from http://www.opencores.org/lgpl.shtml                     ////
1780
////                                                              ////
1781
//////////////////////////////////////////////////////////////////////
1782 22 unneback
 
1783
// LFSR counter
1784 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1785
 
1786
   parameter length = 4;
1787
   input cke;
1788
   output [length:1] q;
1789
   input rst;
1790
   input clk;
1791
 
1792
   parameter clear_value = 0;
1793
   parameter set_value = 1;
1794
   parameter wrap_value = 8;
1795
   parameter level1_value = 15;
1796
 
1797
   reg  [length:1] qi;
1798
   reg lfsr_fb;
1799
   wire [length:1] q_next;
1800
   reg [32:1] polynom;
1801
   integer i;
1802
 
1803
   always @ (qi)
1804
   begin
1805
        case (length)
1806
         2: polynom = 32'b11;                               // 0x3
1807
         3: polynom = 32'b110;                              // 0x6
1808
         4: polynom = 32'b1100;                             // 0xC
1809
         5: polynom = 32'b10100;                            // 0x14
1810
         6: polynom = 32'b110000;                           // 0x30
1811
         7: polynom = 32'b1100000;                          // 0x60
1812
         8: polynom = 32'b10111000;                         // 0xb8
1813
         9: polynom = 32'b100010000;                        // 0x110
1814
        10: polynom = 32'b1001000000;                       // 0x240
1815
        11: polynom = 32'b10100000000;                      // 0x500
1816
        12: polynom = 32'b100000101001;                     // 0x829
1817
        13: polynom = 32'b1000000001100;                    // 0x100C
1818
        14: polynom = 32'b10000000010101;                   // 0x2015
1819
        15: polynom = 32'b110000000000000;                  // 0x6000
1820
        16: polynom = 32'b1101000000001000;                 // 0xD008
1821
        17: polynom = 32'b10010000000000000;                // 0x12000
1822
        18: polynom = 32'b100000010000000000;               // 0x20400
1823
        19: polynom = 32'b1000000000000100011;              // 0x40023
1824
        20: polynom = 32'b10000010000000000000;             // 0x82000
1825
        21: polynom = 32'b101000000000000000000;            // 0x140000
1826
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1827
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1828
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1829
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1830
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1831
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1832
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1833
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1834
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1835
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1836
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1837
        default: polynom = 32'b0;
1838
        endcase
1839
        lfsr_fb = qi[length];
1840
        for (i=length-1; i>=1; i=i-1) begin
1841
            if (polynom[i])
1842
                lfsr_fb = lfsr_fb  ~^ qi[i];
1843
        end
1844
    end
1845
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1846
 
1847
   always @ (posedge clk or posedge rst)
1848
     if (rst)
1849
       qi <= {length{1'b0}};
1850
     else
1851
     if (cke)
1852
       qi <= q_next;
1853
 
1854
   assign q = qi;
1855
 
1856
endmodule
1857
//////////////////////////////////////////////////////////////////////
1858
////                                                              ////
1859
////  Versatile counter                                           ////
1860
////                                                              ////
1861
////  Description                                                 ////
1862
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1863
////  counter                                                     ////
1864
////                                                              ////
1865
////  To Do:                                                      ////
1866
////   - add LFSR with more taps                                  ////
1867
////                                                              ////
1868
////  Author(s):                                                  ////
1869
////      - Michael Unneback, unneback@opencores.org              ////
1870
////        ORSoC AB                                              ////
1871
////                                                              ////
1872
//////////////////////////////////////////////////////////////////////
1873
////                                                              ////
1874
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1875
////                                                              ////
1876
//// This source file may be used and distributed without         ////
1877
//// restriction provided that this copyright statement is not    ////
1878
//// removed from the file and that any derivative work contains  ////
1879
//// the original copyright notice and the associated disclaimer. ////
1880
////                                                              ////
1881
//// This source file is free software; you can redistribute it   ////
1882
//// and/or modify it under the terms of the GNU Lesser General   ////
1883
//// Public License as published by the Free Software Foundation; ////
1884
//// either version 2.1 of the License, or (at your option) any   ////
1885
//// later version.                                               ////
1886
////                                                              ////
1887
//// This source is distributed in the hope that it will be       ////
1888
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1889
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1890
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1891
//// details.                                                     ////
1892
////                                                              ////
1893
//// You should have received a copy of the GNU Lesser General    ////
1894
//// Public License along with this source; if not, download it   ////
1895
//// from http://www.opencores.org/lgpl.shtml                     ////
1896
////                                                              ////
1897
//////////////////////////////////////////////////////////////////////
1898
 
1899
// LFSR counter
1900
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1901
 
1902
   parameter length = 4;
1903
   input clear;
1904
   input cke;
1905
   output [length:1] q;
1906
   input rst;
1907
   input clk;
1908
 
1909
   parameter clear_value = 0;
1910
   parameter set_value = 1;
1911
   parameter wrap_value = 8;
1912
   parameter level1_value = 15;
1913
 
1914
   reg  [length:1] qi;
1915
   reg lfsr_fb;
1916
   wire [length:1] q_next;
1917
   reg [32:1] polynom;
1918
   integer i;
1919
 
1920
   always @ (qi)
1921
   begin
1922
        case (length)
1923
         2: polynom = 32'b11;                               // 0x3
1924
         3: polynom = 32'b110;                              // 0x6
1925
         4: polynom = 32'b1100;                             // 0xC
1926
         5: polynom = 32'b10100;                            // 0x14
1927
         6: polynom = 32'b110000;                           // 0x30
1928
         7: polynom = 32'b1100000;                          // 0x60
1929
         8: polynom = 32'b10111000;                         // 0xb8
1930
         9: polynom = 32'b100010000;                        // 0x110
1931
        10: polynom = 32'b1001000000;                       // 0x240
1932
        11: polynom = 32'b10100000000;                      // 0x500
1933
        12: polynom = 32'b100000101001;                     // 0x829
1934
        13: polynom = 32'b1000000001100;                    // 0x100C
1935
        14: polynom = 32'b10000000010101;                   // 0x2015
1936
        15: polynom = 32'b110000000000000;                  // 0x6000
1937
        16: polynom = 32'b1101000000001000;                 // 0xD008
1938
        17: polynom = 32'b10010000000000000;                // 0x12000
1939
        18: polynom = 32'b100000010000000000;               // 0x20400
1940
        19: polynom = 32'b1000000000000100011;              // 0x40023
1941
        20: polynom = 32'b10000010000000000000;             // 0x82000
1942
        21: polynom = 32'b101000000000000000000;            // 0x140000
1943
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1944
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1945
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1946
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1947
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1948
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1949
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1950
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1951
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1952
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1953
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1954
        default: polynom = 32'b0;
1955
        endcase
1956
        lfsr_fb = qi[length];
1957
        for (i=length-1; i>=1; i=i-1) begin
1958
            if (polynom[i])
1959
                lfsr_fb = lfsr_fb  ~^ qi[i];
1960
        end
1961
    end
1962
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1963
 
1964
   always @ (posedge clk or posedge rst)
1965
     if (rst)
1966
       qi <= {length{1'b0}};
1967
     else
1968
     if (cke)
1969
       qi <= q_next;
1970
 
1971
   assign q = qi;
1972
 
1973
endmodule
1974
//////////////////////////////////////////////////////////////////////
1975
////                                                              ////
1976
////  Versatile counter                                           ////
1977
////                                                              ////
1978
////  Description                                                 ////
1979
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1980
////  counter                                                     ////
1981
////                                                              ////
1982
////  To Do:                                                      ////
1983
////   - add LFSR with more taps                                  ////
1984
////                                                              ////
1985
////  Author(s):                                                  ////
1986
////      - Michael Unneback, unneback@opencores.org              ////
1987
////        ORSoC AB                                              ////
1988
////                                                              ////
1989
//////////////////////////////////////////////////////////////////////
1990
////                                                              ////
1991
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1992
////                                                              ////
1993
//// This source file may be used and distributed without         ////
1994
//// restriction provided that this copyright statement is not    ////
1995
//// removed from the file and that any derivative work contains  ////
1996
//// the original copyright notice and the associated disclaimer. ////
1997
////                                                              ////
1998
//// This source file is free software; you can redistribute it   ////
1999
//// and/or modify it under the terms of the GNU Lesser General   ////
2000
//// Public License as published by the Free Software Foundation; ////
2001
//// either version 2.1 of the License, or (at your option) any   ////
2002
//// later version.                                               ////
2003
////                                                              ////
2004
//// This source is distributed in the hope that it will be       ////
2005
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2006
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2007
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2008
//// details.                                                     ////
2009
////                                                              ////
2010
//// You should have received a copy of the GNU Lesser General    ////
2011
//// Public License along with this source; if not, download it   ////
2012
//// from http://www.opencores.org/lgpl.shtml                     ////
2013
////                                                              ////
2014
//////////////////////////////////////////////////////////////////////
2015
 
2016
// LFSR counter
2017 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
2018
 
2019
   parameter length = 4;
2020
   input cke;
2021
   output [length:1] q;
2022
   output reg zq;
2023
   input rst;
2024
   input clk;
2025
 
2026
   parameter clear_value = 0;
2027
   parameter set_value = 1;
2028
   parameter wrap_value = 8;
2029
   parameter level1_value = 15;
2030
 
2031
   reg  [length:1] qi;
2032
   reg lfsr_fb;
2033
   wire [length:1] q_next;
2034
   reg [32:1] polynom;
2035
   integer i;
2036
 
2037
   always @ (qi)
2038
   begin
2039
        case (length)
2040
         2: polynom = 32'b11;                               // 0x3
2041
         3: polynom = 32'b110;                              // 0x6
2042
         4: polynom = 32'b1100;                             // 0xC
2043
         5: polynom = 32'b10100;                            // 0x14
2044
         6: polynom = 32'b110000;                           // 0x30
2045
         7: polynom = 32'b1100000;                          // 0x60
2046
         8: polynom = 32'b10111000;                         // 0xb8
2047
         9: polynom = 32'b100010000;                        // 0x110
2048
        10: polynom = 32'b1001000000;                       // 0x240
2049
        11: polynom = 32'b10100000000;                      // 0x500
2050
        12: polynom = 32'b100000101001;                     // 0x829
2051
        13: polynom = 32'b1000000001100;                    // 0x100C
2052
        14: polynom = 32'b10000000010101;                   // 0x2015
2053
        15: polynom = 32'b110000000000000;                  // 0x6000
2054
        16: polynom = 32'b1101000000001000;                 // 0xD008
2055
        17: polynom = 32'b10010000000000000;                // 0x12000
2056
        18: polynom = 32'b100000010000000000;               // 0x20400
2057
        19: polynom = 32'b1000000000000100011;              // 0x40023
2058
        20: polynom = 32'b10000010000000000000;             // 0x82000
2059
        21: polynom = 32'b101000000000000000000;            // 0x140000
2060
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2061
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2062
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2063
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2064
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2065
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2066
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2067
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2068
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2069
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2070
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2071
        default: polynom = 32'b0;
2072
        endcase
2073
        lfsr_fb = qi[length];
2074
        for (i=length-1; i>=1; i=i-1) begin
2075
            if (polynom[i])
2076
                lfsr_fb = lfsr_fb  ~^ qi[i];
2077
        end
2078
    end
2079
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2080
 
2081
   always @ (posedge clk or posedge rst)
2082
     if (rst)
2083
       qi <= {length{1'b0}};
2084
     else
2085
     if (cke)
2086
       qi <= q_next;
2087
 
2088
   assign q = qi;
2089
 
2090
 
2091
   always @ (posedge clk or posedge rst)
2092
     if (rst)
2093
       zq <= 1'b1;
2094
     else
2095
     if (cke)
2096
       zq <= q_next == {length{1'b0}};
2097
endmodule
2098
//////////////////////////////////////////////////////////////////////
2099
////                                                              ////
2100
////  Versatile counter                                           ////
2101
////                                                              ////
2102
////  Description                                                 ////
2103
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2104
////  counter                                                     ////
2105
////                                                              ////
2106
////  To Do:                                                      ////
2107
////   - add LFSR with more taps                                  ////
2108
////                                                              ////
2109
////  Author(s):                                                  ////
2110
////      - Michael Unneback, unneback@opencores.org              ////
2111
////        ORSoC AB                                              ////
2112
////                                                              ////
2113
//////////////////////////////////////////////////////////////////////
2114
////                                                              ////
2115
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2116
////                                                              ////
2117
//// This source file may be used and distributed without         ////
2118
//// restriction provided that this copyright statement is not    ////
2119
//// removed from the file and that any derivative work contains  ////
2120
//// the original copyright notice and the associated disclaimer. ////
2121
////                                                              ////
2122
//// This source file is free software; you can redistribute it   ////
2123
//// and/or modify it under the terms of the GNU Lesser General   ////
2124
//// Public License as published by the Free Software Foundation; ////
2125
//// either version 2.1 of the License, or (at your option) any   ////
2126
//// later version.                                               ////
2127
////                                                              ////
2128
//// This source is distributed in the hope that it will be       ////
2129
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2130
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2131
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2132
//// details.                                                     ////
2133
////                                                              ////
2134
//// You should have received a copy of the GNU Lesser General    ////
2135
//// Public License along with this source; if not, download it   ////
2136
//// from http://www.opencores.org/lgpl.shtml                     ////
2137
////                                                              ////
2138
//////////////////////////////////////////////////////////////////////
2139 6 unneback
 
2140
// LFSR counter
2141 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
2142 6 unneback
 
2143
   parameter length = 4;
2144
   input cke;
2145
   input rew;
2146
   output reg level1;
2147
   input rst;
2148
   input clk;
2149
 
2150
   parameter clear_value = 0;
2151
   parameter set_value = 1;
2152
   parameter wrap_value = 8;
2153
   parameter level1_value = 15;
2154
 
2155 29 unneback
   wire clear;
2156
   assign clear=1'b0;
2157 6 unneback
   reg  [length:1] qi;
2158
   reg lfsr_fb, lfsr_fb_rew;
2159
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2160
   reg [32:1] polynom_rew;
2161
   integer j;
2162
   reg [32:1] polynom;
2163
   integer i;
2164
 
2165
   always @ (qi)
2166
   begin
2167
        case (length)
2168
         2: polynom = 32'b11;                               // 0x3
2169
         3: polynom = 32'b110;                              // 0x6
2170
         4: polynom = 32'b1100;                             // 0xC
2171
         5: polynom = 32'b10100;                            // 0x14
2172
         6: polynom = 32'b110000;                           // 0x30
2173
         7: polynom = 32'b1100000;                          // 0x60
2174
         8: polynom = 32'b10111000;                         // 0xb8
2175
         9: polynom = 32'b100010000;                        // 0x110
2176
        10: polynom = 32'b1001000000;                       // 0x240
2177
        11: polynom = 32'b10100000000;                      // 0x500
2178
        12: polynom = 32'b100000101001;                     // 0x829
2179
        13: polynom = 32'b1000000001100;                    // 0x100C
2180
        14: polynom = 32'b10000000010101;                   // 0x2015
2181
        15: polynom = 32'b110000000000000;                  // 0x6000
2182
        16: polynom = 32'b1101000000001000;                 // 0xD008
2183
        17: polynom = 32'b10010000000000000;                // 0x12000
2184
        18: polynom = 32'b100000010000000000;               // 0x20400
2185
        19: polynom = 32'b1000000000000100011;              // 0x40023
2186
        20: polynom = 32'b10000010000000000000;             // 0x82000
2187
        21: polynom = 32'b101000000000000000000;            // 0x140000
2188
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2189
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2190
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2191
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2192
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2193
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2194
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2195
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2196
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2197
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2198
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2199
        default: polynom = 32'b0;
2200
        endcase
2201
        lfsr_fb = qi[length];
2202
        for (i=length-1; i>=1; i=i-1) begin
2203
            if (polynom[i])
2204
                lfsr_fb = lfsr_fb  ~^ qi[i];
2205
        end
2206
    end
2207
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2208
   always @ (qi)
2209
   begin
2210
        case (length)
2211
         2: polynom_rew = 32'b11;
2212
         3: polynom_rew = 32'b110;
2213
         4: polynom_rew = 32'b1100;
2214
         5: polynom_rew = 32'b10100;
2215
         6: polynom_rew = 32'b110000;
2216
         7: polynom_rew = 32'b1100000;
2217
         8: polynom_rew = 32'b10111000;
2218
         9: polynom_rew = 32'b100010000;
2219
        10: polynom_rew = 32'b1001000000;
2220
        11: polynom_rew = 32'b10100000000;
2221
        12: polynom_rew = 32'b100000101001;
2222
        13: polynom_rew = 32'b1000000001100;
2223
        14: polynom_rew = 32'b10000000010101;
2224
        15: polynom_rew = 32'b110000000000000;
2225
        16: polynom_rew = 32'b1101000000001000;
2226
        17: polynom_rew = 32'b10010000000000000;
2227
        18: polynom_rew = 32'b100000010000000000;
2228
        19: polynom_rew = 32'b1000000000000100011;
2229
        20: polynom_rew = 32'b10000010000000000000;
2230
        21: polynom_rew = 32'b101000000000000000000;
2231
        22: polynom_rew = 32'b1100000000000000000000;
2232
        23: polynom_rew = 32'b10000100000000000000000;
2233
        24: polynom_rew = 32'b111000010000000000000000;
2234
        25: polynom_rew = 32'b1001000000000000000000000;
2235
        26: polynom_rew = 32'b10000000000000000000100011;
2236
        27: polynom_rew = 32'b100000000000000000000010011;
2237
        28: polynom_rew = 32'b1100100000000000000000000000;
2238
        29: polynom_rew = 32'b10100000000000000000000000000;
2239
        30: polynom_rew = 32'b100000000000000000000000101001;
2240
        31: polynom_rew = 32'b1001000000000000000000000000000;
2241
        32: polynom_rew = 32'b10000000001000000000000000000011;
2242
        default: polynom_rew = 32'b0;
2243
        endcase
2244
        // rotate left
2245
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2246
        lfsr_fb_rew = qi[length];
2247
        for (i=length-1; i>=1; i=i-1) begin
2248
            if (polynom_rew[i])
2249
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2250
        end
2251
    end
2252
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2253
   assign q_next = rew ? q_next_rew : q_next_fw;
2254
 
2255
   always @ (posedge clk or posedge rst)
2256
     if (rst)
2257
       qi <= {length{1'b0}};
2258
     else
2259
     if (cke)
2260
       qi <= q_next;
2261
 
2262
 
2263
 
2264
    always @ (posedge clk or posedge rst)
2265
    if (rst)
2266
        level1 <= 1'b0;
2267
    else
2268
    if (cke)
2269 29 unneback
    if (clear)
2270
        level1 <= 1'b0;
2271
    else if (q_next == level1_value)
2272 6 unneback
        level1 <= 1'b1;
2273
    else if (qi == level1_value & rew)
2274
        level1 <= 1'b0;
2275
endmodule
2276
//////////////////////////////////////////////////////////////////////
2277
////                                                              ////
2278
////  Versatile counter                                           ////
2279
////                                                              ////
2280
////  Description                                                 ////
2281
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2282
////  counter                                                     ////
2283
////                                                              ////
2284
////  To Do:                                                      ////
2285
////   - add LFSR with more taps                                  ////
2286
////                                                              ////
2287
////  Author(s):                                                  ////
2288
////      - Michael Unneback, unneback@opencores.org              ////
2289
////        ORSoC AB                                              ////
2290
////                                                              ////
2291
//////////////////////////////////////////////////////////////////////
2292
////                                                              ////
2293
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2294
////                                                              ////
2295
//// This source file may be used and distributed without         ////
2296
//// restriction provided that this copyright statement is not    ////
2297
//// removed from the file and that any derivative work contains  ////
2298
//// the original copyright notice and the associated disclaimer. ////
2299
////                                                              ////
2300
//// This source file is free software; you can redistribute it   ////
2301
//// and/or modify it under the terms of the GNU Lesser General   ////
2302
//// Public License as published by the Free Software Foundation; ////
2303
//// either version 2.1 of the License, or (at your option) any   ////
2304
//// later version.                                               ////
2305
////                                                              ////
2306
//// This source is distributed in the hope that it will be       ////
2307
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2308
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2309
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2310
//// details.                                                     ////
2311
////                                                              ////
2312
//// You should have received a copy of the GNU Lesser General    ////
2313
//// Public License along with this source; if not, download it   ////
2314
//// from http://www.opencores.org/lgpl.shtml                     ////
2315
////                                                              ////
2316
//////////////////////////////////////////////////////////////////////
2317
 
2318
// GRAY counter
2319 18 unneback
module vl_cnt_gray ( q, rst, clk);
2320 6 unneback
 
2321
   parameter length = 4;
2322
   output reg [length:1] q;
2323
   input rst;
2324
   input clk;
2325
 
2326
   parameter clear_value = 0;
2327
   parameter set_value = 1;
2328
   parameter wrap_value = 8;
2329
   parameter level1_value = 15;
2330
 
2331
   reg  [length:1] qi;
2332
   wire [length:1] q_next;
2333
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2334
 
2335
   always @ (posedge clk or posedge rst)
2336
     if (rst)
2337
       qi <= {length{1'b0}};
2338
     else
2339
       qi <= q_next;
2340
 
2341
   always @ (posedge clk or posedge rst)
2342
     if (rst)
2343
       q <= {length{1'b0}};
2344
     else
2345
         q <= (q_next>>1) ^ q_next;
2346
 
2347
endmodule
2348
//////////////////////////////////////////////////////////////////////
2349
////                                                              ////
2350
////  Versatile counter                                           ////
2351
////                                                              ////
2352
////  Description                                                 ////
2353
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2354
////  counter                                                     ////
2355
////                                                              ////
2356
////  To Do:                                                      ////
2357
////   - add LFSR with more taps                                  ////
2358
////                                                              ////
2359
////  Author(s):                                                  ////
2360
////      - Michael Unneback, unneback@opencores.org              ////
2361
////        ORSoC AB                                              ////
2362
////                                                              ////
2363
//////////////////////////////////////////////////////////////////////
2364
////                                                              ////
2365
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2366
////                                                              ////
2367
//// This source file may be used and distributed without         ////
2368
//// restriction provided that this copyright statement is not    ////
2369
//// removed from the file and that any derivative work contains  ////
2370
//// the original copyright notice and the associated disclaimer. ////
2371
////                                                              ////
2372
//// This source file is free software; you can redistribute it   ////
2373
//// and/or modify it under the terms of the GNU Lesser General   ////
2374
//// Public License as published by the Free Software Foundation; ////
2375
//// either version 2.1 of the License, or (at your option) any   ////
2376
//// later version.                                               ////
2377
////                                                              ////
2378
//// This source is distributed in the hope that it will be       ////
2379
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2380
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2381
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2382
//// details.                                                     ////
2383
////                                                              ////
2384
//// You should have received a copy of the GNU Lesser General    ////
2385
//// Public License along with this source; if not, download it   ////
2386
//// from http://www.opencores.org/lgpl.shtml                     ////
2387
////                                                              ////
2388
//////////////////////////////////////////////////////////////////////
2389
 
2390
// GRAY counter
2391 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
2392 6 unneback
 
2393
   parameter length = 4;
2394
   input cke;
2395
   output reg [length:1] q;
2396
   input rst;
2397
   input clk;
2398
 
2399
   parameter clear_value = 0;
2400
   parameter set_value = 1;
2401
   parameter wrap_value = 8;
2402
   parameter level1_value = 15;
2403
 
2404
   reg  [length:1] qi;
2405
   wire [length:1] q_next;
2406
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2407
 
2408
   always @ (posedge clk or posedge rst)
2409
     if (rst)
2410
       qi <= {length{1'b0}};
2411
     else
2412
     if (cke)
2413
       qi <= q_next;
2414
 
2415
   always @ (posedge clk or posedge rst)
2416
     if (rst)
2417
       q <= {length{1'b0}};
2418
     else
2419
       if (cke)
2420
         q <= (q_next>>1) ^ q_next;
2421
 
2422
endmodule
2423
//////////////////////////////////////////////////////////////////////
2424
////                                                              ////
2425
////  Versatile counter                                           ////
2426
////                                                              ////
2427
////  Description                                                 ////
2428
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2429
////  counter                                                     ////
2430
////                                                              ////
2431
////  To Do:                                                      ////
2432
////   - add LFSR with more taps                                  ////
2433
////                                                              ////
2434
////  Author(s):                                                  ////
2435
////      - Michael Unneback, unneback@opencores.org              ////
2436
////        ORSoC AB                                              ////
2437
////                                                              ////
2438
//////////////////////////////////////////////////////////////////////
2439
////                                                              ////
2440
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2441
////                                                              ////
2442
//// This source file may be used and distributed without         ////
2443
//// restriction provided that this copyright statement is not    ////
2444
//// removed from the file and that any derivative work contains  ////
2445
//// the original copyright notice and the associated disclaimer. ////
2446
////                                                              ////
2447
//// This source file is free software; you can redistribute it   ////
2448
//// and/or modify it under the terms of the GNU Lesser General   ////
2449
//// Public License as published by the Free Software Foundation; ////
2450
//// either version 2.1 of the License, or (at your option) any   ////
2451
//// later version.                                               ////
2452
////                                                              ////
2453
//// This source is distributed in the hope that it will be       ////
2454
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2455
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2456
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2457
//// details.                                                     ////
2458
////                                                              ////
2459
//// You should have received a copy of the GNU Lesser General    ////
2460
//// Public License along with this source; if not, download it   ////
2461
//// from http://www.opencores.org/lgpl.shtml                     ////
2462
////                                                              ////
2463
//////////////////////////////////////////////////////////////////////
2464
 
2465
// GRAY counter
2466 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2467 6 unneback
 
2468
   parameter length = 4;
2469
   input cke;
2470
   output reg [length:1] q;
2471
   output [length:1] q_bin;
2472
   input rst;
2473
   input clk;
2474
 
2475
   parameter clear_value = 0;
2476
   parameter set_value = 1;
2477
   parameter wrap_value = 8;
2478
   parameter level1_value = 15;
2479
 
2480
   reg  [length:1] qi;
2481
   wire [length:1] q_next;
2482
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2483
 
2484
   always @ (posedge clk or posedge rst)
2485
     if (rst)
2486
       qi <= {length{1'b0}};
2487
     else
2488
     if (cke)
2489
       qi <= q_next;
2490
 
2491
   always @ (posedge clk or posedge rst)
2492
     if (rst)
2493
       q <= {length{1'b0}};
2494
     else
2495
       if (cke)
2496
         q <= (q_next>>1) ^ q_next;
2497
 
2498
   assign q_bin = qi;
2499
 
2500
endmodule
2501
//////////////////////////////////////////////////////////////////////
2502
////                                                              ////
2503
////  Versatile library, counters                                 ////
2504
////                                                              ////
2505
////  Description                                                 ////
2506
////  counters                                                    ////
2507
////                                                              ////
2508
////                                                              ////
2509
////  To Do:                                                      ////
2510
////   - add more counters                                        ////
2511
////                                                              ////
2512
////  Author(s):                                                  ////
2513
////      - Michael Unneback, unneback@opencores.org              ////
2514
////        ORSoC AB                                              ////
2515
////                                                              ////
2516
//////////////////////////////////////////////////////////////////////
2517
////                                                              ////
2518
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2519
////                                                              ////
2520
//// This source file may be used and distributed without         ////
2521
//// restriction provided that this copyright statement is not    ////
2522
//// removed from the file and that any derivative work contains  ////
2523
//// the original copyright notice and the associated disclaimer. ////
2524
////                                                              ////
2525
//// This source file is free software; you can redistribute it   ////
2526
//// and/or modify it under the terms of the GNU Lesser General   ////
2527
//// Public License as published by the Free Software Foundation; ////
2528
//// either version 2.1 of the License, or (at your option) any   ////
2529
//// later version.                                               ////
2530
////                                                              ////
2531
//// This source is distributed in the hope that it will be       ////
2532
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2533
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2534
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2535
//// details.                                                     ////
2536
////                                                              ////
2537
//// You should have received a copy of the GNU Lesser General    ////
2538
//// Public License along with this source; if not, download it   ////
2539
//// from http://www.opencores.org/lgpl.shtml                     ////
2540
////                                                              ////
2541
//////////////////////////////////////////////////////////////////////
2542
 
2543 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2544 6 unneback
 
2545
   parameter length = 4;
2546
   output reg [0:length-1] q;
2547
   input rst;
2548
   input clk;
2549
 
2550
    always @ (posedge clk or posedge rst)
2551
    if (rst)
2552
        q <= {1'b1,{length-1{1'b0}}};
2553
    else
2554
        q <= {q[length-1],q[0:length-2]};
2555
 
2556
endmodule
2557
 
2558 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2559 6 unneback
 
2560
   parameter length = 4;
2561
   input cke;
2562
   output reg [0:length-1] q;
2563
   input rst;
2564
   input clk;
2565
 
2566
    always @ (posedge clk or posedge rst)
2567
    if (rst)
2568
        q <= {1'b1,{length-1{1'b0}}};
2569
    else
2570
        if (cke)
2571
            q <= {q[length-1],q[0:length-2]};
2572
 
2573
endmodule
2574
 
2575 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2576 6 unneback
 
2577
   parameter length = 4;
2578
   input cke, clear;
2579
   output reg [0:length-1] q;
2580
   input rst;
2581
   input clk;
2582
 
2583
    always @ (posedge clk or posedge rst)
2584
    if (rst)
2585
        q <= {1'b1,{length-1{1'b0}}};
2586
    else
2587
        if (cke)
2588
            if (clear)
2589
                q <= {1'b1,{length-1{1'b0}}};
2590
            else
2591
                q <= q >> 1;
2592
 
2593
endmodule
2594
 
2595 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2596 6 unneback
 
2597
   parameter length = 4;
2598
   input cke, clear;
2599
   output reg [0:length-1] q;
2600
   input rst;
2601
   input clk;
2602
 
2603
    always @ (posedge clk or posedge rst)
2604
    if (rst)
2605
        q <= {1'b1,{length-1{1'b0}}};
2606
    else
2607
        if (cke)
2608
            if (clear)
2609
                q <= {1'b1,{length-1{1'b0}}};
2610
            else
2611
            q <= {q[length-1],q[0:length-2]};
2612
 
2613
endmodule
2614
//////////////////////////////////////////////////////////////////////
2615
////                                                              ////
2616
////  Versatile library, memories                                 ////
2617
////                                                              ////
2618
////  Description                                                 ////
2619
////  memories                                                    ////
2620
////                                                              ////
2621
////                                                              ////
2622
////  To Do:                                                      ////
2623
////   - add more memory types                                    ////
2624
////                                                              ////
2625
////  Author(s):                                                  ////
2626
////      - Michael Unneback, unneback@opencores.org              ////
2627
////        ORSoC AB                                              ////
2628
////                                                              ////
2629
//////////////////////////////////////////////////////////////////////
2630
////                                                              ////
2631
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2632
////                                                              ////
2633
//// This source file may be used and distributed without         ////
2634
//// restriction provided that this copyright statement is not    ////
2635
//// removed from the file and that any derivative work contains  ////
2636
//// the original copyright notice and the associated disclaimer. ////
2637
////                                                              ////
2638
//// This source file is free software; you can redistribute it   ////
2639
//// and/or modify it under the terms of the GNU Lesser General   ////
2640
//// Public License as published by the Free Software Foundation; ////
2641
//// either version 2.1 of the License, or (at your option) any   ////
2642
//// later version.                                               ////
2643
////                                                              ////
2644
//// This source is distributed in the hope that it will be       ////
2645
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2646
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2647
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2648
//// details.                                                     ////
2649
////                                                              ////
2650
//// You should have received a copy of the GNU Lesser General    ////
2651
//// Public License along with this source; if not, download it   ////
2652
//// from http://www.opencores.org/lgpl.shtml                     ////
2653
////                                                              ////
2654
//////////////////////////////////////////////////////////////////////
2655
 
2656
/// ROM
2657
 
2658 7 unneback
module vl_rom_init ( adr, q, clk);
2659
   parameter data_width = 32;
2660
   parameter addr_width = 8;
2661
   input [(addr_width-1):0]       adr;
2662
   output reg [(data_width-1):0] q;
2663
   input                         clk;
2664
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2665
   parameter memory_file = "vl_rom.vmem";
2666
   initial
2667
     begin
2668
        $readmemh(memory_file, rom);
2669
     end
2670
 
2671
   always @ (posedge clk)
2672
     q <= rom[adr];
2673 6 unneback
 
2674 7 unneback
endmodule
2675
 
2676 14 unneback
/*
2677 7 unneback
module vl_rom ( adr, q, clk);
2678
 
2679 6 unneback
parameter data_width = 32;
2680
parameter addr_width = 4;
2681
 
2682
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2683
    {32'h18000000},
2684
    {32'hA8200000},
2685
    {32'hA8200000},
2686
    {32'hA8200000},
2687
    {32'h44003000},
2688
    {32'h15000000},
2689
    {32'h15000000},
2690
    {32'h15000000},
2691
    {32'h15000000},
2692
    {32'h15000000},
2693
    {32'h15000000},
2694
    {32'h15000000},
2695
    {32'h15000000},
2696
    {32'h15000000},
2697
    {32'h15000000},
2698
    {32'h15000000}};
2699
 
2700 7 unneback
input [addr_width-1:0] adr;
2701 6 unneback
output reg [data_width-1:0] q;
2702
input clk;
2703
 
2704
always @ (posedge clk)
2705 7 unneback
    q <= data[adr];
2706 6 unneback
 
2707
endmodule
2708 14 unneback
*/
2709 6 unneback
// Single port RAM
2710
 
2711
module vl_ram ( d, adr, we, q, clk);
2712
   parameter data_width = 32;
2713
   parameter addr_width = 8;
2714
   input [(data_width-1):0]      d;
2715
   input [(addr_width-1):0]       adr;
2716
   input                         we;
2717 7 unneback
   output reg [(data_width-1):0] q;
2718 6 unneback
   input                         clk;
2719
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2720 7 unneback
   parameter init = 0;
2721
   parameter memory_file = "vl_ram.vmem";
2722
   generate if (init) begin : init_mem
2723
   initial
2724
     begin
2725
        $readmemh(memory_file, ram);
2726
     end
2727
   end
2728
   endgenerate
2729
 
2730 6 unneback
   always @ (posedge clk)
2731
   begin
2732
   if (we)
2733
     ram[adr] <= d;
2734
   q <= ram[adr];
2735
   end
2736
 
2737
endmodule
2738
 
2739 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2740
   parameter data_width = 32;
2741
   parameter addr_width = 8;
2742
   input [(data_width-1):0]      d;
2743
   input [(addr_width-1):0]       adr;
2744
   input [(addr_width/4)-1:0]    be;
2745
   input                         we;
2746
   output reg [(data_width-1):0] q;
2747
   input                         clk;
2748
 
2749
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2750
 
2751
   parameter init = 0;
2752
   parameter memory_file = "vl_ram.vmem";
2753
   generate if (init) begin : init_mem
2754
   initial
2755
     begin
2756
        $readmemh(memory_file, ram);
2757
     end
2758
   end
2759
   endgenerate
2760
 
2761
   genvar i;
2762
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2763
      always @ (posedge clk)
2764
      if (we & be[i])
2765
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2766
   end
2767
   endgenerate
2768
 
2769
   always @ (posedge clk)
2770
      q <= ram[adr];
2771
 
2772
endmodule
2773
 
2774
 
2775 6 unneback
// Dual port RAM
2776
 
2777
// ACTEL FPGA should not use logic to handle rw collision
2778
`ifdef ACTEL
2779
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
2780
`else
2781
        `define SYN
2782
`endif
2783
 
2784 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2785 6 unneback
   parameter data_width = 32;
2786
   parameter addr_width = 8;
2787
   input [(data_width-1):0]      d_a;
2788
   input [(addr_width-1):0]       adr_a;
2789
   input [(addr_width-1):0]       adr_b;
2790
   input                         we_a;
2791
   output [(data_width-1):0]      q_b;
2792
   input                         clk_a, clk_b;
2793
   reg [(addr_width-1):0]         adr_b_reg;
2794
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
2795 7 unneback
 
2796
   parameter init = 0;
2797
   parameter memory_file = "vl_ram.vmem";
2798
   generate if (init) begin : init_mem
2799
   initial
2800
     begin
2801
        $readmemh(memory_file, ram);
2802
     end
2803
   end
2804
   endgenerate
2805
 
2806 6 unneback
   always @ (posedge clk_a)
2807
   if (we_a)
2808
     ram[adr_a]