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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 40

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1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5
`ifdef ALL
6
 
7
`define GBUF
8
`define SYNC_RST
9
`define PLL
10
 
11
`define MULTS
12
`define MULTS18X18
13
`define MULT
14
`define SHIFT_UNIT_32
15
`define LOGIC_UNIT
16
 
17
`define CNT_SHREG_WRAP
18
`define CNT_SHREG_CE_WRAP
19
`define CNT_SHREG_CE_CLEAR
20
`define CNT_SHREG_CE_CLEAR_WRAP
21
 
22
`define MUX_ANDOR
23
`define MUX2_ANDOR
24
`define MUX3_ANDOR
25
`define MUX4_ANDOR
26
`define MUX5_ANDOR
27
`define MUX6_ANDOR
28
 
29
`define ROM_INIT
30
`define RAM
31
`define RAM_BE
32
`define DPRAM_1R1W
33
`define DPRAM_2R1W
34
`define DPRAM_2R2W
35
`define FIFO_1R1W_FILL_LEVEL_SYNC
36
`define FIFO_2R2W_SYNC_SIMPLEX
37
`define FIFO_CMP_ASYNC
38
`define FIFO_1R1W_ASYNC
39
`define FIFO_2R2W_ASYNC
40
`define FIFO_2R2W_ASYNC_SIMPLEX
41
 
42
`define DFF
43
`define DFF_ARRAY
44
`define DFF_CE
45
`define DFF_CE_CLEAR
46
`define DF_CE_SET
47
`define SPR
48
`define SRP
49
`define DFF_SR
50
`define LATCH
51
`define SHREG
52
`define SHREG_CE
53
`define DELAY
54
`define DELAY_EMPTYFLAG
55
 
56
`define WB3WB3_BRIDGE
57
`define WB3_ARBITER_TYPE1
58
`define WB_BOOT_ROM
59
`define WB_DPRAM
60
 
61
`endif
62
 
63
`ifdef PLL
64
`ifndef SYNC_RST
65
`define SYNC_RST
66
`endif
67
`endif
68
 
69
`ifdef SYNC_RST
70
`ifndef GBUF
71
`define GBUF
72
`endif
73
`endif
74
 
75
`ifdef WB_DPRAM
76
`ifndef DPRAM_2R2W
77
`define DPRAM_2R2W
78
`endif
79
`ifndef SPR
80
`define SPR
81
`endif
82
`endif
83
 
84
`ifdef WB3_ARBITER_TYPE1
85
`ifndef MUX_ANDOR
86
`define MUX_ANDOR
87
`endif
88
`endif
89
 
90
`ifdef WB3WB3_BRIDGE
91
`ifndef CNT_SHREG_CE_CLEAR
92
`define CNT_SHREG_CE_CLEAR
93
`endif
94
`ifndef DFF
95
`define DFF
96
`endif
97
`ifndef DFF_CE
98
`define DFF_CE
99
`endif
100
`ifndef CNT_SHREG_CE_CLEAR
101
`define CNT_SHREG_CE_CLEAR
102
`endif
103
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
104
`define FIFO_2R2W_ASYNC_SIMPLEX
105
`endif
106
`endif
107
 
108
`ifdef MULTS18X18
109
`ifndef MULTS
110
`define MULTS
111
`endif
112
`endif
113
 
114
`ifdef SHIFT_UNIT_32
115
`ifndef MULTS
116
`define MULTS
117
`endif
118
`endif
119
 
120
`ifdef MUX2_ANDOR
121
`ifndef MUX_ANDOR
122
`define MUX_ANDOR
123
`endif
124
`endif
125
 
126
`ifdef MUX3_ANDOR
127
`ifndef MUX_ANDOR
128
`define MUX_ANDOR
129
`endif
130
`endif
131
 
132
`ifdef MUX4_ANDOR
133
`ifndef MUX_ANDOR
134
`define MUX_ANDOR
135
`endif
136
`endif
137
 
138
`ifdef MUX5_ANDOR
139
`ifndef MUX_ANDOR
140
`define MUX_ANDOR
141
`endif
142
`endif
143
 
144
`ifdef MUX6_ANDOR
145
`ifndef MUX_ANDOR
146
`define MUX_ANDOR
147
`endif
148
`endif
149
 
150
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
151
`ifndef CNT_BIN_CE
152
`define CNT_BIN_CE
153
`endif
154
`ifndef DPRAM_1R1W
155
`define DPRAM_1R1W
156
`endif
157
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
158
`define CNT_BIN_CE_REW_Q_ZQ_L1
159
`endif
160
`endif
161
 
162
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
163
`ifndef CNT_LFSR_CE
164
`define CNT_LFSR_CE
165
`endif
166
`ifndef DPRAM_2R2W
167
`define DPRAM_2R2W
168
`endif
169
`ifndef CNT_BIN_CE_REW_ZQ_L1
170
`define CNT_BIN_CE_REW_ZQ_L1
171
`endif
172
`endif
173
 
174
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
175
`ifndef CNT_GRAY_CE_BIN
176
`define CNT_GRAY_CE_BIN
177
`endif
178
`ifndef DPRAM_2R2W
179
`define DPRAM_2R2W
180
`endif
181
`ifndef FIFO_CMP_ASYNC
182
`define FIFO_CMP_ASYNC
183
`endif
184
`endif
185
 
186
`ifdef FIFO_2R2W_ASYNC
187
`ifndef FIFO_1R1W_ASYNC
188
`define FIFO_1R1W_ASYNC
189
`endif
190
`endif
191
 
192
`ifdef FIFO_1R1W_ASYNC
193
`ifndef CNT_GRAY_CE_BIN
194
`define CNT_GRAY_CE_BIN
195
`endif
196
`ifndef DPRAM_1R1W
197
`define DPRAM_1R1W
198
`endif
199
`ifndef FIFO_CMP_ASYNC
200
`define FIFO_CMP_ASYNC
201
`endif
202
`endif
203
 
204
`ifdef FIFO_CMP_ASYNC
205
`ifndef DFF_SR
206
`define DFF_SR
207
`endif
208
`ifndef DFF
209
`define DFF
210
`endif
211
`endif
212 6 unneback
//////////////////////////////////////////////////////////////////////
213
////                                                              ////
214
////  Versatile library, clock and reset                          ////
215
////                                                              ////
216
////  Description                                                 ////
217
////  Logic related to clock and reset                            ////
218
////                                                              ////
219
////                                                              ////
220
////  To Do:                                                      ////
221
////   - add more different registers                             ////
222
////                                                              ////
223
////  Author(s):                                                  ////
224
////      - Michael Unneback, unneback@opencores.org              ////
225
////        ORSoC AB                                              ////
226
////                                                              ////
227
//////////////////////////////////////////////////////////////////////
228
////                                                              ////
229
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
230
////                                                              ////
231
//// This source file may be used and distributed without         ////
232
//// restriction provided that this copyright statement is not    ////
233
//// removed from the file and that any derivative work contains  ////
234
//// the original copyright notice and the associated disclaimer. ////
235
////                                                              ////
236
//// This source file is free software; you can redistribute it   ////
237
//// and/or modify it under the terms of the GNU Lesser General   ////
238
//// Public License as published by the Free Software Foundation; ////
239
//// either version 2.1 of the License, or (at your option) any   ////
240
//// later version.                                               ////
241
////                                                              ////
242
//// This source is distributed in the hope that it will be       ////
243
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
244
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
245
//// PURPOSE.  See the GNU Lesser General Public License for more ////
246
//// details.                                                     ////
247
////                                                              ////
248
//// You should have received a copy of the GNU Lesser General    ////
249
//// Public License along with this source; if not, download it   ////
250
//// from http://www.opencores.org/lgpl.shtml                     ////
251
////                                                              ////
252
//////////////////////////////////////////////////////////////////////
253
 
254
// Global buffer
255
// usage:
256
// use to enable global buffers for high fan out signals such as clock and reset
257
 
258
`ifdef ACTEL
259 40 unneback
`ifdef GBUF
260 6 unneback
`timescale 1 ns/100 ps
261
// Version: 8.4 8.4.0.33
262
module gbuf(GL,CLK);
263
output GL;
264
input  CLK;
265
 
266
    wire GND;
267
 
268
    GND GND_1_net(.Y(GND));
269
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
270
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
271
 
272
endmodule
273
`timescale 1 ns/1 ns
274 40 unneback
`define MODULE gbuf
275
module `BASE`MODULE ( i, o);
276
`undef MODULE
277 6 unneback
input i;
278
output o;
279
`ifdef SIM_GBUF
280
assign o=i;
281
`else
282
gbuf gbuf_i0 ( .CLK(i), .GL(o));
283
`endif
284
endmodule
285 40 unneback
`endif
286 33 unneback
 
287 6 unneback
`else
288 33 unneback
 
289 40 unneback
`ifdef ALTERA
290
`ifdef GBUF
291 21 unneback
//altera
292 40 unneback
`define MODULE gbuf
293
module `BASE`MODULE ( i, o);
294
`undef MODULE
295 33 unneback
input i;
296
output o;
297
assign o = i;
298
endmodule
299 40 unneback
`endif
300 33 unneback
 
301 6 unneback
`else
302
 
303 40 unneback
`ifdef GBUF
304 6 unneback
`timescale 1 ns/100 ps
305 40 unneback
`define MODULE
306
module `BASE`MODULE ( i, o);
307
`undef MODULE
308 6 unneback
input i;
309
output o;
310
assign o = i;
311
endmodule
312 40 unneback
`endif
313 6 unneback
`endif // ALTERA
314
`endif //ACTEL
315
 
316 40 unneback
`ifdef SYNC_RST
317 6 unneback
// sync reset
318 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
319 6 unneback
// output active high global reset sync with two DFFs 
320
`timescale 1 ns/100 ps
321 40 unneback
`define MODULE sync_rst
322
module `BASE`MODULE ( rst_n_i, rst_o, clk);
323
`undef MODULE
324 6 unneback
input rst_n_i, clk;
325
output rst_o;
326 18 unneback
reg [1:0] tmp;
327 6 unneback
always @ (posedge clk or negedge rst_n_i)
328
if (!rst_n_i)
329 17 unneback
        tmp <= 2'b11;
330 6 unneback
else
331 33 unneback
        tmp <= {1'b0,tmp[1]};
332 40 unneback
`define MODULE gbuf
333
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
334
`undef MODULE
335 6 unneback
endmodule
336 40 unneback
`endif
337 6 unneback
 
338 40 unneback
`ifdef PLL
339 6 unneback
// vl_pll
340
`ifdef ACTEL
341 32 unneback
///////////////////////////////////////////////////////////////////////////////
342 17 unneback
`timescale 1 ps/1 ps
343 40 unneback
`define MODULE pll
344
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
345
`undef MODULE
346 6 unneback
parameter index = 0;
347
parameter number_of_clk = 1;
348 17 unneback
parameter period_time_0 = 20000;
349
parameter period_time_1 = 20000;
350
parameter period_time_2 = 20000;
351
parameter lock_delay = 2000000;
352 6 unneback
input clk_i, rst_n_i;
353
output lock;
354
output reg [0:number_of_clk-1] clk_o;
355
output [0:number_of_clk-1] rst_o;
356
 
357
`ifdef SIM_PLL
358
 
359
always
360
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
361
 
362
generate if (number_of_clk > 1)
363
always
364
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
365
endgenerate
366
 
367
generate if (number_of_clk > 2)
368
always
369
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
370
endgenerate
371
 
372
genvar i;
373
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
374
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
375
end
376
endgenerate
377
 
378
assign #lock_delay lock = rst_n_i;
379
 
380
endmodule
381
`else
382
generate if (number_of_clk==1 & index==0) begin
383
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
384
end
385
endgenerate // index==0
386
generate if (number_of_clk==1 & index==1) begin
387
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
388
end
389
endgenerate // index==1
390
generate if (number_of_clk==1 & index==2) begin
391
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
392
end
393
endgenerate // index==2
394
generate if (number_of_clk==1 & index==3) begin
395
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
396
end
397
endgenerate // index==0
398
 
399
generate if (number_of_clk==2 & index==0) begin
400
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
401
end
402
endgenerate // index==0
403
generate if (number_of_clk==2 & index==1) begin
404
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
405
end
406
endgenerate // index==1
407
generate if (number_of_clk==2 & index==2) begin
408
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
409
end
410
endgenerate // index==2
411
generate if (number_of_clk==2 & index==3) begin
412
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
413
end
414
endgenerate // index==0
415
 
416
generate if (number_of_clk==3 & index==0) begin
417
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
418
end
419
endgenerate // index==0
420
generate if (number_of_clk==3 & index==1) begin
421
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
422
end
423
endgenerate // index==1
424
generate if (number_of_clk==3 & index==2) begin
425
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
426
end
427
endgenerate // index==2
428
generate if (number_of_clk==3 & index==3) begin
429
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
430
end
431
endgenerate // index==0
432
 
433
genvar i;
434
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
435 40 unneback
`define MODULE sync_rst
436
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
437
`undef MODULE
438 6 unneback
end
439
endgenerate
440
endmodule
441
`endif
442 32 unneback
///////////////////////////////////////////////////////////////////////////////
443 6 unneback
 
444
`else
445
 
446 32 unneback
///////////////////////////////////////////////////////////////////////////////
447 6 unneback
`ifdef ALTERA
448
 
449 32 unneback
`timescale 1 ps/1 ps
450 40 unneback
`define MODULE pll
451
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
452
`undef MODULE
453 32 unneback
parameter index = 0;
454
parameter number_of_clk = 1;
455
parameter period_time_0 = 20000;
456
parameter period_time_1 = 20000;
457
parameter period_time_2 = 20000;
458
parameter period_time_3 = 20000;
459
parameter period_time_4 = 20000;
460
parameter lock_delay = 2000000;
461
input clk_i, rst_n_i;
462
output lock;
463
output reg [0:number_of_clk-1] clk_o;
464
output [0:number_of_clk-1] rst_o;
465
 
466
`ifdef SIM_PLL
467
 
468
always
469
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
470
 
471
generate if (number_of_clk > 1)
472
always
473
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
474
endgenerate
475
 
476
generate if (number_of_clk > 2)
477
always
478
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
479
endgenerate
480
 
481 33 unneback
generate if (number_of_clk > 3)
482 32 unneback
always
483
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
484
endgenerate
485
 
486 33 unneback
generate if (number_of_clk > 4)
487 32 unneback
always
488
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
489
endgenerate
490
 
491
genvar i;
492
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
493
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
494
end
495
endgenerate
496
 
497 33 unneback
//assign #lock_delay lock = rst_n_i;
498
assign lock = rst_n_i;
499 32 unneback
 
500
endmodule
501 6 unneback
`else
502
 
503 33 unneback
`ifdef VL_PLL0
504
`ifdef VL_PLL0_CLK1
505
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
506
`endif
507
`ifdef VL_PLL0_CLK2
508
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
509
`endif
510
`ifdef VL_PLL0_CLK3
511
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
512
`endif
513
`ifdef VL_PLL0_CLK4
514
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
515
`endif
516
`ifdef VL_PLL0_CLK5
517
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
518
`endif
519
`endif
520 32 unneback
 
521 33 unneback
`ifdef VL_PLL1
522
`ifdef VL_PLL1_CLK1
523
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
524
`endif
525
`ifdef VL_PLL1_CLK2
526
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
527
`endif
528
`ifdef VL_PLL1_CLK3
529
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
530
`endif
531
`ifdef VL_PLL1_CLK4
532
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
533
`endif
534
`ifdef VL_PLL1_CLK5
535
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
536
`endif
537
`endif
538 32 unneback
 
539 33 unneback
`ifdef VL_PLL2
540
`ifdef VL_PLL2_CLK1
541
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
542
`endif
543
`ifdef VL_PLL2_CLK2
544
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
545
`endif
546
`ifdef VL_PLL2_CLK3
547
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
548
`endif
549
`ifdef VL_PLL2_CLK4
550
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
551
`endif
552
`ifdef VL_PLL2_CLK5
553
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
554
`endif
555
`endif
556 32 unneback
 
557 33 unneback
`ifdef VL_PLL3
558
`ifdef VL_PLL3_CLK1
559
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
560
`endif
561
`ifdef VL_PLL3_CLK2
562
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
563
`endif
564
`ifdef VL_PLL3_CLK3
565
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
566
`endif
567
`ifdef VL_PLL3_CLK4
568
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
569
`endif
570
`ifdef VL_PLL3_CLK5
571
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
572
`endif
573
`endif
574 32 unneback
 
575
genvar i;
576
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
577 40 unneback
`define MODULE sync_rst
578
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
579
`undef MODULE
580 32 unneback
end
581
endgenerate
582
endmodule
583
`endif
584
///////////////////////////////////////////////////////////////////////////////
585
 
586
`else
587
 
588 6 unneback
// generic PLL
589 17 unneback
`timescale 1 ps/1 ps
590 40 unneback
`define MODULE pll
591
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
592
`undef MODULE
593 6 unneback
parameter index = 0;
594
parameter number_of_clk = 1;
595 17 unneback
parameter period_time_0 = 20000;
596
parameter period_time_1 = 20000;
597
parameter period_time_2 = 20000;
598 6 unneback
parameter lock_delay = 2000;
599
input clk_i, rst_n_i;
600
output lock;
601
output reg [0:number_of_clk-1] clk_o;
602
output [0:number_of_clk-1] rst_o;
603
 
604
always
605
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
606
 
607
generate if (number_of_clk > 1)
608
always
609
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
610
endgenerate
611
 
612
generate if (number_of_clk > 2)
613
always
614
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
615
endgenerate
616
 
617
genvar i;
618
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
619 40 unneback
`define MODULE sync_rst
620
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
621
`undef MODULE
622 6 unneback
end
623
endgenerate
624
 
625
assign #lock_delay lock = rst_n_i;
626
 
627
endmodule
628
 
629
`endif //altera
630 17 unneback
`endif //actel
631 40 unneback
`undef MODULE
632
`endif//////////////////////////////////////////////////////////////////////
633 6 unneback
////                                                              ////
634
////  Versatile library, registers                                ////
635
////                                                              ////
636
////  Description                                                 ////
637
////  Different type of registers                                 ////
638
////                                                              ////
639
////                                                              ////
640
////  To Do:                                                      ////
641
////   - add more different registers                             ////
642
////                                                              ////
643
////  Author(s):                                                  ////
644
////      - Michael Unneback, unneback@opencores.org              ////
645
////        ORSoC AB                                              ////
646
////                                                              ////
647
//////////////////////////////////////////////////////////////////////
648
////                                                              ////
649
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
650
////                                                              ////
651
//// This source file may be used and distributed without         ////
652
//// restriction provided that this copyright statement is not    ////
653
//// removed from the file and that any derivative work contains  ////
654
//// the original copyright notice and the associated disclaimer. ////
655
////                                                              ////
656
//// This source file is free software; you can redistribute it   ////
657
//// and/or modify it under the terms of the GNU Lesser General   ////
658
//// Public License as published by the Free Software Foundation; ////
659
//// either version 2.1 of the License, or (at your option) any   ////
660
//// later version.                                               ////
661
////                                                              ////
662
//// This source is distributed in the hope that it will be       ////
663
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
664
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
665
//// PURPOSE.  See the GNU Lesser General Public License for more ////
666
//// details.                                                     ////
667
////                                                              ////
668
//// You should have received a copy of the GNU Lesser General    ////
669
//// Public License along with this source; if not, download it   ////
670
//// from http://www.opencores.org/lgpl.shtml                     ////
671
////                                                              ////
672
//////////////////////////////////////////////////////////////////////
673
 
674 40 unneback
`ifdef DFF
675
`define MODULE dff
676
module `BASE`MODULE ( d, q, clk, rst);
677
`undef MODULE
678 6 unneback
        parameter width = 1;
679
        parameter reset_value = 0;
680
 
681
        input [width-1:0] d;
682
        input clk, rst;
683
        output reg [width-1:0] q;
684
 
685
        always @ (posedge clk or posedge rst)
686
        if (rst)
687
                q <= reset_value;
688
        else
689
                q <= d;
690
 
691
endmodule
692 40 unneback
`endif
693 6 unneback
 
694 40 unneback
`ifdef DFF_ARRAY
695
`define MODULE dff_array
696
module `BASE`MODULE ( d, q, clk, rst);
697
`undef MODULE
698 6 unneback
 
699
        parameter width = 1;
700
        parameter depth = 2;
701
        parameter reset_value = 1'b0;
702
 
703
        input [width-1:0] d;
704
        input clk, rst;
705
        output [width-1:0] q;
706
        reg  [0:depth-1] q_tmp [width-1:0];
707
        integer i;
708
        always @ (posedge clk or posedge rst)
709
        if (rst) begin
710
            for (i=0;i<depth;i=i+1)
711
                q_tmp[i] <= {width{reset_value}};
712
        end else begin
713
            q_tmp[0] <= d;
714
            for (i=1;i<depth;i=i+1)
715
                q_tmp[i] <= q_tmp[i-1];
716
        end
717
 
718
    assign q = q_tmp[depth-1];
719
 
720
endmodule
721 40 unneback
`endif
722 6 unneback
 
723 40 unneback
`ifdef DFF_CE
724
`define MODULE dff_ce
725
module `BASE`MODULE ( d, ce, q, clk, rst);
726
`undef MODULE
727 6 unneback
 
728
        parameter width = 1;
729
        parameter reset_value = 0;
730
 
731
        input [width-1:0] d;
732
        input ce, clk, rst;
733
        output reg [width-1:0] q;
734
 
735
        always @ (posedge clk or posedge rst)
736
        if (rst)
737
                q <= reset_value;
738
        else
739
                if (ce)
740
                        q <= d;
741
 
742
endmodule
743 40 unneback
`endif
744 6 unneback
 
745 40 unneback
`ifdef DFF_CE_CLEAR
746
`define MODULE dff_ce_clear
747
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
748
`undef MODULE
749 8 unneback
 
750
        parameter width = 1;
751
        parameter reset_value = 0;
752
 
753
        input [width-1:0] d;
754 10 unneback
        input ce, clear, clk, rst;
755 8 unneback
        output reg [width-1:0] q;
756
 
757
        always @ (posedge clk or posedge rst)
758
        if (rst)
759
            q <= reset_value;
760
        else
761
            if (ce)
762
                if (clear)
763
                    q <= {width{1'b0}};
764
                else
765
                    q <= d;
766
 
767
endmodule
768 40 unneback
`endif
769 8 unneback
 
770 40 unneback
`ifdef DF_CE_SET
771
`define MODULE dff_ce_set
772
module `BASE`MODULE ( d, ce, set, q, clk, rst);
773
`undef MODULE
774 24 unneback
 
775
        parameter width = 1;
776
        parameter reset_value = 0;
777
 
778
        input [width-1:0] d;
779
        input ce, set, clk, rst;
780
        output reg [width-1:0] q;
781
 
782
        always @ (posedge clk or posedge rst)
783
        if (rst)
784
            q <= reset_value;
785
        else
786
            if (ce)
787
                if (set)
788
                    q <= {width{1'b1}};
789
                else
790
                    q <= d;
791
 
792
endmodule
793 40 unneback
`endif
794 24 unneback
 
795 40 unneback
`ifdef SPR
796
`define MODULE spr
797
module `BASE`MODULE ( sp, r, q, clk, rst);
798
`undef MODULE
799
 
800 29 unneback
        parameter width = 1;
801
        parameter reset_value = 0;
802
 
803
        input sp, r;
804
        output reg q;
805
        input clk, rst;
806
 
807
        always @ (posedge clk or posedge rst)
808
        if (rst)
809
            q <= reset_value;
810
        else
811
            if (sp)
812
                q <= 1'b1;
813
            else if (r)
814
                q <= 1'b0;
815
 
816
endmodule
817 40 unneback
`endif
818 29 unneback
 
819 40 unneback
`ifdef SRP
820
`define MODULE srp
821
module `BASE`MODULE ( s, rp, q, clk, rst);
822
`undef MODULE
823
 
824 29 unneback
        parameter width = 1;
825
        parameter reset_value = 0;
826
 
827
        input s, rp;
828
        output reg q;
829
        input clk, rst;
830
 
831
        always @ (posedge clk or posedge rst)
832
        if (rst)
833
            q <= reset_value;
834
        else
835
            if (rp)
836
                q <= 1'b0;
837
            else if (s)
838
                q <= 1'b1;
839
 
840
endmodule
841 40 unneback
`endif
842 29 unneback
 
843 40 unneback
`ifdef ALTERA
844 29 unneback
 
845 40 unneback
`ifdef DFF_SR
846 6 unneback
// megafunction wizard: %LPM_FF%
847
// GENERATION: STANDARD
848
// VERSION: WM1.0
849
// MODULE: lpm_ff 
850
 
851
// ============================================================
852
// File Name: dff_sr.v
853
// Megafunction Name(s):
854
//                      lpm_ff
855
//
856
// Simulation Library Files(s):
857
//                      lpm
858
// ============================================================
859
// ************************************************************
860
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
861
//
862
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
863
// ************************************************************
864
 
865
 
866
//Copyright (C) 1991-2010 Altera Corporation
867
//Your use of Altera Corporation's design tools, logic functions 
868
//and other software and tools, and its AMPP partner logic 
869
//functions, and any output files from any of the foregoing 
870
//(including device programming or simulation files), and any 
871
//associated documentation or information are expressly subject 
872
//to the terms and conditions of the Altera Program License 
873
//Subscription Agreement, Altera MegaCore Function License 
874
//Agreement, or other applicable license agreement, including, 
875
//without limitation, that your use is for the sole purpose of 
876
//programming logic devices manufactured by Altera and sold by 
877
//Altera or its authorized distributors.  Please refer to the 
878
//applicable agreement for further details.
879
 
880
 
881
// synopsys translate_off
882
`timescale 1 ps / 1 ps
883
// synopsys translate_on
884 40 unneback
`define MODULE dff_sr
885
module `BASE`MODULE (
886
`undef MODULE
887
 
888 6 unneback
        aclr,
889
        aset,
890
        clock,
891
        data,
892
        q);
893
 
894
        input     aclr;
895
        input     aset;
896
        input     clock;
897
        input     data;
898
        output    q;
899
 
900
        wire [0:0] sub_wire0;
901
        wire [0:0] sub_wire1 = sub_wire0[0:0];
902
        wire  q = sub_wire1;
903
        wire  sub_wire2 = data;
904
        wire  sub_wire3 = sub_wire2;
905
 
906
        lpm_ff  lpm_ff_component (
907
                                .aclr (aclr),
908
                                .clock (clock),
909
                                .data (sub_wire3),
910
                                .aset (aset),
911
                                .q (sub_wire0)
912
                                // synopsys translate_off
913
                                ,
914
                                .aload (),
915
                                .enable (),
916
                                .sclr (),
917
                                .sload (),
918
                                .sset ()
919
                                // synopsys translate_on
920
                                );
921
        defparam
922
                lpm_ff_component.lpm_fftype = "DFF",
923
                lpm_ff_component.lpm_type = "LPM_FF",
924
                lpm_ff_component.lpm_width = 1;
925
 
926
 
927
endmodule
928
 
929
// ============================================================
930
// CNX file retrieval info
931
// ============================================================
932
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
933
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
934
// Retrieval info: PRIVATE: ASET NUMERIC "1"
935
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
936
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
937
// Retrieval info: PRIVATE: DFF NUMERIC "1"
938
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
939
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
940
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
941
// Retrieval info: PRIVATE: SSET NUMERIC "0"
942
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
943
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
944
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
945
// Retrieval info: PRIVATE: nBit NUMERIC "1"
946
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
947
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
948
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
949
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
950
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
951
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
952
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
953
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
954
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
955
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
956
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
957
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
958
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
959
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
960
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
961
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
962
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
963
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
964
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
965
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
966
// Retrieval info: LIB_FILE: lpm
967 40 unneback
`endif
968 6 unneback
 
969
`else
970
 
971 40 unneback
`ifdef DFF_SR
972
`define MODULE dff_sr
973
module `BASE`MODULE ( aclr, aset, clock, data, q);
974
`undef MODULE
975 6 unneback
 
976
    input         aclr;
977
    input         aset;
978
    input         clock;
979
    input         data;
980
    output reg    q;
981
 
982
   always @ (posedge clock or posedge aclr or posedge aset)
983
     if (aclr)
984
       q <= 1'b0;
985
     else if (aset)
986
       q <= 1'b1;
987
     else
988
       q <= data;
989
 
990
endmodule
991 40 unneback
`endif
992 6 unneback
 
993
`endif
994
 
995
// LATCH
996
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
997
`ifdef ALTERA
998 40 unneback
 
999
`ifdef LATCH
1000
`define MODULE latch
1001
module `BASE`MODULE ( d, le, q, clk);
1002
`undef MODULE
1003 6 unneback
input d, le;
1004
output q;
1005
input clk;
1006
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1007
endmodule
1008 40 unneback
`endif
1009
 
1010 6 unneback
`else
1011 40 unneback
 
1012
`ifdef LATCH
1013
`define MODULE latch
1014
module `BASE`MODULE ( d, le, q, clk);
1015
`undef MODULE
1016 6 unneback
input d, le;
1017
output q;
1018
input clk;/*
1019
   always @ (posedge direction_set or posedge direction_clr)
1020
     if (direction_clr)
1021
       direction <= going_empty;
1022
     else
1023
       direction <= going_full;*/
1024
endmodule
1025 15 unneback
`endif
1026
 
1027 40 unneback
`endif
1028
 
1029
`ifdef SHREG
1030
`define MODULE shreg
1031
module `BASE`MODULE ( d, q, clk, rst);
1032
`undef MODULE
1033
 
1034 17 unneback
parameter depth = 10;
1035
input d;
1036
output q;
1037
input clk, rst;
1038
 
1039
reg [1:depth] dffs;
1040
 
1041
always @ (posedge clk or posedge rst)
1042
if (rst)
1043
    dffs <= {depth{1'b0}};
1044
else
1045
    dffs <= {d,dffs[1:depth-1]};
1046
assign q = dffs[depth];
1047
endmodule
1048 40 unneback
`endif
1049 17 unneback
 
1050 40 unneback
`ifdef SHREG_CE
1051
`define MODULE shreg_ce
1052
module `BASE`MODULE ( d, ce, q, clk, rst);
1053
`undef MODULE
1054 17 unneback
parameter depth = 10;
1055
input d, ce;
1056
output q;
1057
input clk, rst;
1058
 
1059
reg [1:depth] dffs;
1060
 
1061
always @ (posedge clk or posedge rst)
1062
if (rst)
1063
    dffs <= {depth{1'b0}};
1064
else
1065
    if (ce)
1066
        dffs <= {d,dffs[1:depth-1]};
1067
assign q = dffs[depth];
1068
endmodule
1069 40 unneback
`endif
1070 17 unneback
 
1071 40 unneback
`ifdef DELAY
1072
`define MODULE delay
1073
module `BASE`MODULE ( d, q, clk, rst);
1074
`undef MODULE
1075 15 unneback
parameter depth = 10;
1076
input d;
1077
output q;
1078
input clk, rst;
1079
 
1080
reg [1:depth] dffs;
1081
 
1082
always @ (posedge clk or posedge rst)
1083
if (rst)
1084
    dffs <= {depth{1'b0}};
1085
else
1086
    dffs <= {d,dffs[1:depth-1]};
1087
assign q = dffs[depth];
1088 17 unneback
endmodule
1089 40 unneback
`endif
1090 17 unneback
 
1091 40 unneback
`ifdef DELAY_EMPTYFLAG
1092
`define MODULE delay_emptyflag
1093 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
1094 40 unneback
`undef MODULE
1095 17 unneback
parameter depth = 10;
1096
input d;
1097
output q, emptyflag;
1098
input clk, rst;
1099
 
1100
reg [1:depth] dffs;
1101
 
1102
always @ (posedge clk or posedge rst)
1103
if (rst)
1104
    dffs <= {depth{1'b0}};
1105
else
1106
    dffs <= {d,dffs[1:depth-1]};
1107
assign q = dffs[depth];
1108
assign emptyflag = !(|dffs);
1109
endmodule
1110 40 unneback
`endif
1111 17 unneback
//////////////////////////////////////////////////////////////////////
1112 6 unneback
////                                                              ////
1113 18 unneback
////  Logic functions                                             ////
1114
////                                                              ////
1115
////  Description                                                 ////
1116
////  Logic functions such as multiplexers                        ////
1117
////                                                              ////
1118
////                                                              ////
1119
////  To Do:                                                      ////
1120
////   -                                                          ////
1121
////                                                              ////
1122
////  Author(s):                                                  ////
1123
////      - Michael Unneback, unneback@opencores.org              ////
1124
////        ORSoC AB                                              ////
1125
////                                                              ////
1126
//////////////////////////////////////////////////////////////////////
1127
////                                                              ////
1128
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1129
////                                                              ////
1130
//// This source file may be used and distributed without         ////
1131
//// restriction provided that this copyright statement is not    ////
1132
//// removed from the file and that any derivative work contains  ////
1133
//// the original copyright notice and the associated disclaimer. ////
1134
////                                                              ////
1135
//// This source file is free software; you can redistribute it   ////
1136
//// and/or modify it under the terms of the GNU Lesser General   ////
1137
//// Public License as published by the Free Software Foundation; ////
1138
//// either version 2.1 of the License, or (at your option) any   ////
1139
//// later version.                                               ////
1140
////                                                              ////
1141
//// This source is distributed in the hope that it will be       ////
1142
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1143
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1144
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1145
//// details.                                                     ////
1146
////                                                              ////
1147
//// You should have received a copy of the GNU Lesser General    ////
1148
//// Public License along with this source; if not, download it   ////
1149
//// from http://www.opencores.org/lgpl.shtml                     ////
1150
////                                                              ////
1151
//////////////////////////////////////////////////////////////////////
1152 40 unneback
`ifdef MUX_ANDOR
1153
`define MODULE mux_andor
1154
module `BASE`MODULE ( a, sel, dout);
1155
`undef MODULE
1156 36 unneback
 
1157
parameter width = 32;
1158
parameter nr_of_ports = 4;
1159
 
1160
input [nr_of_ports*width-1:0] a;
1161
input [nr_of_ports-1:0] sel;
1162
output reg [width-1:0] dout;
1163
 
1164 38 unneback
integer i,j;
1165
 
1166 36 unneback
always @ (a, sel)
1167
begin
1168
    dout = a[width-1:0] & {width{sel[0]}};
1169
    for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
1170 38 unneback
        for (j=0;j<32;j=j+1)
1171
            dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
1172 36 unneback
end
1173
 
1174
endmodule
1175 40 unneback
`endif
1176 36 unneback
 
1177 40 unneback
`ifdef MUX2_ANDOR
1178
`define MODULE mux2_andor
1179
module `BASE`MODULE ( a1, a0, sel, dout);
1180
`undef MODULE
1181 18 unneback
 
1182 34 unneback
parameter width = 32;
1183 35 unneback
localparam nr_of_ports = 2;
1184 34 unneback
input [width-1:0] a1, a0;
1185
input [nr_of_ports-1:0] sel;
1186
output [width-1:0] dout;
1187
 
1188 40 unneback
`define MODULE mux_andor
1189
`BASE`MODULE
1190 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1191 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1192 40 unneback
`undef MODULE
1193
 
1194 34 unneback
endmodule
1195 40 unneback
`endif
1196 34 unneback
 
1197 40 unneback
`ifdef MUX3_ANDOR
1198
`define MODULE mux3_andor
1199
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1200
`undef MODULE
1201 34 unneback
 
1202
parameter width = 32;
1203 35 unneback
localparam nr_of_ports = 3;
1204 34 unneback
input [width-1:0] a2, a1, a0;
1205
input [nr_of_ports-1:0] sel;
1206
output [width-1:0] dout;
1207
 
1208 40 unneback
`define MODULE mux_andor
1209
`BASE`MODULE
1210 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1211 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1212 40 unneback
`undef MODULE
1213 34 unneback
endmodule
1214 40 unneback
`endif
1215 34 unneback
 
1216 40 unneback
`ifdef MUX4_ANDOR
1217
`define MODULE mux4_andor
1218
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1219
`undef MODULE
1220 18 unneback
 
1221
parameter width = 32;
1222 35 unneback
localparam nr_of_ports = 4;
1223 18 unneback
input [width-1:0] a3, a2, a1, a0;
1224
input [nr_of_ports-1:0] sel;
1225 22 unneback
output [width-1:0] dout;
1226 18 unneback
 
1227 40 unneback
`define MODULE mux_andor
1228
`BASE`MODULE
1229 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1230 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1231 40 unneback
`undef MODULE
1232 18 unneback
 
1233
endmodule
1234 40 unneback
`endif
1235 18 unneback
 
1236 40 unneback
`ifdef MUX5_ANDOR
1237
`define MODULE mux5_andor
1238
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1239
`undef MODULE
1240 18 unneback
 
1241
parameter width = 32;
1242 35 unneback
localparam nr_of_ports = 5;
1243 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1244
input [nr_of_ports-1:0] sel;
1245 22 unneback
output [width-1:0] dout;
1246 18 unneback
 
1247 40 unneback
`define MODULE mux_andor
1248
`BASE`MODULE
1249 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1250 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1251 40 unneback
`undef MODULE
1252 18 unneback
 
1253
endmodule
1254 40 unneback
`endif
1255 18 unneback
 
1256 40 unneback
`ifdef MUX6_ANDOR
1257
`define MODULE mux6_andor
1258
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1259
`undef MODULE
1260 18 unneback
 
1261
parameter width = 32;
1262 35 unneback
localparam nr_of_ports = 6;
1263 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1264
input [nr_of_ports-1:0] sel;
1265 22 unneback
output [width-1:0] dout;
1266 18 unneback
 
1267 40 unneback
`define MODULE mux_andor
1268
`BASE`MODULE
1269 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1270 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1271 40 unneback
`undef MODULE
1272 18 unneback
 
1273
endmodule
1274 40 unneback
`endif
1275
`ifdef CNT_BIN
1276 18 unneback
//////////////////////////////////////////////////////////////////////
1277
////                                                              ////
1278 6 unneback
////  Versatile counter                                           ////
1279
////                                                              ////
1280
////  Description                                                 ////
1281
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1282
////  counter                                                     ////
1283
////                                                              ////
1284
////  To Do:                                                      ////
1285
////   - add LFSR with more taps                                  ////
1286
////                                                              ////
1287
////  Author(s):                                                  ////
1288
////      - Michael Unneback, unneback@opencores.org              ////
1289
////        ORSoC AB                                              ////
1290
////                                                              ////
1291
//////////////////////////////////////////////////////////////////////
1292
////                                                              ////
1293
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1294
////                                                              ////
1295
//// This source file may be used and distributed without         ////
1296
//// restriction provided that this copyright statement is not    ////
1297
//// removed from the file and that any derivative work contains  ////
1298
//// the original copyright notice and the associated disclaimer. ////
1299
////                                                              ////
1300
//// This source file is free software; you can redistribute it   ////
1301
//// and/or modify it under the terms of the GNU Lesser General   ////
1302
//// Public License as published by the Free Software Foundation; ////
1303
//// either version 2.1 of the License, or (at your option) any   ////
1304
//// later version.                                               ////
1305
////                                                              ////
1306
//// This source is distributed in the hope that it will be       ////
1307
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1308
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1309
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1310
//// details.                                                     ////
1311
////                                                              ////
1312
//// You should have received a copy of the GNU Lesser General    ////
1313
//// Public License along with this source; if not, download it   ////
1314
//// from http://www.opencores.org/lgpl.shtml                     ////
1315
////                                                              ////
1316
//////////////////////////////////////////////////////////////////////
1317
 
1318
// binary counter
1319 22 unneback
 
1320 40 unneback
`define MODULE cnt_bin
1321
module `BASE`MODULE (
1322
`undef MODULE
1323
 q, rst, clk);
1324
 
1325 22 unneback
   parameter length = 4;
1326
   output [length:1] q;
1327
   input rst;
1328
   input clk;
1329
 
1330
   parameter clear_value = 0;
1331
   parameter set_value = 1;
1332
   parameter wrap_value = 0;
1333
   parameter level1_value = 15;
1334
 
1335
   reg  [length:1] qi;
1336
   wire [length:1] q_next;
1337
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1338
 
1339
   always @ (posedge clk or posedge rst)
1340
     if (rst)
1341
       qi <= {length{1'b0}};
1342
     else
1343
       qi <= q_next;
1344
 
1345
   assign q = qi;
1346
 
1347
endmodule
1348 40 unneback
`endif
1349
`ifdef CNT_BIN_CLEAR
1350 22 unneback
//////////////////////////////////////////////////////////////////////
1351
////                                                              ////
1352
////  Versatile counter                                           ////
1353
////                                                              ////
1354
////  Description                                                 ////
1355
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1356
////  counter                                                     ////
1357
////                                                              ////
1358
////  To Do:                                                      ////
1359
////   - add LFSR with more taps                                  ////
1360
////                                                              ////
1361
////  Author(s):                                                  ////
1362
////      - Michael Unneback, unneback@opencores.org              ////
1363
////        ORSoC AB                                              ////
1364
////                                                              ////
1365
//////////////////////////////////////////////////////////////////////
1366
////                                                              ////
1367
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1368
////                                                              ////
1369
//// This source file may be used and distributed without         ////
1370
//// restriction provided that this copyright statement is not    ////
1371
//// removed from the file and that any derivative work contains  ////
1372
//// the original copyright notice and the associated disclaimer. ////
1373
////                                                              ////
1374
//// This source file is free software; you can redistribute it   ////
1375
//// and/or modify it under the terms of the GNU Lesser General   ////
1376
//// Public License as published by the Free Software Foundation; ////
1377
//// either version 2.1 of the License, or (at your option) any   ////
1378
//// later version.                                               ////
1379
////                                                              ////
1380
//// This source is distributed in the hope that it will be       ////
1381
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1382
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1383
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1384
//// details.                                                     ////
1385
////                                                              ////
1386
//// You should have received a copy of the GNU Lesser General    ////
1387
//// Public License along with this source; if not, download it   ////
1388
//// from http://www.opencores.org/lgpl.shtml                     ////
1389
////                                                              ////
1390
//////////////////////////////////////////////////////////////////////
1391
 
1392
// binary counter
1393
 
1394 40 unneback
`define MODULE cnt_bin_clear
1395
module `BASE`MODULE (
1396
`undef MODULE
1397
 clear, q, rst, clk);
1398
 
1399 22 unneback
   parameter length = 4;
1400
   input clear;
1401
   output [length:1] q;
1402
   input rst;
1403
   input clk;
1404
 
1405
   parameter clear_value = 0;
1406
   parameter set_value = 1;
1407
   parameter wrap_value = 0;
1408
   parameter level1_value = 15;
1409
 
1410
   reg  [length:1] qi;
1411
   wire [length:1] q_next;
1412
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1413
 
1414
   always @ (posedge clk or posedge rst)
1415
     if (rst)
1416
       qi <= {length{1'b0}};
1417
     else
1418
       qi <= q_next;
1419
 
1420
   assign q = qi;
1421
 
1422
endmodule
1423 40 unneback
`endif
1424
`ifdef CNT_BIN_CE
1425 22 unneback
//////////////////////////////////////////////////////////////////////
1426
////                                                              ////
1427
////  Versatile counter                                           ////
1428
////                                                              ////
1429
////  Description                                                 ////
1430
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1431
////  counter                                                     ////
1432
////                                                              ////
1433
////  To Do:                                                      ////
1434
////   - add LFSR with more taps                                  ////
1435
////                                                              ////
1436
////  Author(s):                                                  ////
1437
////      - Michael Unneback, unneback@opencores.org              ////
1438
////        ORSoC AB                                              ////
1439
////                                                              ////
1440
//////////////////////////////////////////////////////////////////////
1441
////                                                              ////
1442
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1443
////                                                              ////
1444
//// This source file may be used and distributed without         ////
1445
//// restriction provided that this copyright statement is not    ////
1446
//// removed from the file and that any derivative work contains  ////
1447
//// the original copyright notice and the associated disclaimer. ////
1448
////                                                              ////
1449
//// This source file is free software; you can redistribute it   ////
1450
//// and/or modify it under the terms of the GNU Lesser General   ////
1451
//// Public License as published by the Free Software Foundation; ////
1452
//// either version 2.1 of the License, or (at your option) any   ////
1453
//// later version.                                               ////
1454
////                                                              ////
1455
//// This source is distributed in the hope that it will be       ////
1456
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1457
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1458
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1459
//// details.                                                     ////
1460
////                                                              ////
1461
//// You should have received a copy of the GNU Lesser General    ////
1462
//// Public License along with this source; if not, download it   ////
1463
//// from http://www.opencores.org/lgpl.shtml                     ////
1464
////                                                              ////
1465
//////////////////////////////////////////////////////////////////////
1466
 
1467
// binary counter
1468 6 unneback
 
1469 40 unneback
`define MODULE cnt_bin_ce
1470
module `BASE`MODULE (
1471
`undef MODULE
1472
 cke, q, rst, clk);
1473
 
1474 6 unneback
   parameter length = 4;
1475
   input cke;
1476
   output [length:1] q;
1477
   input rst;
1478
   input clk;
1479
 
1480
   parameter clear_value = 0;
1481
   parameter set_value = 1;
1482
   parameter wrap_value = 0;
1483
   parameter level1_value = 15;
1484
 
1485
   reg  [length:1] qi;
1486
   wire [length:1] q_next;
1487
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1488
 
1489
   always @ (posedge clk or posedge rst)
1490
     if (rst)
1491
       qi <= {length{1'b0}};
1492
     else
1493
     if (cke)
1494
       qi <= q_next;
1495
 
1496
   assign q = qi;
1497
 
1498
endmodule
1499 40 unneback
`endif
1500
`ifdef CNT_BIN_CE_CLEAR
1501 6 unneback
//////////////////////////////////////////////////////////////////////
1502
////                                                              ////
1503
////  Versatile counter                                           ////
1504
////                                                              ////
1505
////  Description                                                 ////
1506
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1507
////  counter                                                     ////
1508
////                                                              ////
1509
////  To Do:                                                      ////
1510
////   - add LFSR with more taps                                  ////
1511
////                                                              ////
1512
////  Author(s):                                                  ////
1513
////      - Michael Unneback, unneback@opencores.org              ////
1514
////        ORSoC AB                                              ////
1515
////                                                              ////
1516
//////////////////////////////////////////////////////////////////////
1517
////                                                              ////
1518
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1519
////                                                              ////
1520
//// This source file may be used and distributed without         ////
1521
//// restriction provided that this copyright statement is not    ////
1522
//// removed from the file and that any derivative work contains  ////
1523
//// the original copyright notice and the associated disclaimer. ////
1524
////                                                              ////
1525
//// This source file is free software; you can redistribute it   ////
1526
//// and/or modify it under the terms of the GNU Lesser General   ////
1527
//// Public License as published by the Free Software Foundation; ////
1528
//// either version 2.1 of the License, or (at your option) any   ////
1529
//// later version.                                               ////
1530
////                                                              ////
1531
//// This source is distributed in the hope that it will be       ////
1532
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1533
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1534
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1535
//// details.                                                     ////
1536
////                                                              ////
1537
//// You should have received a copy of the GNU Lesser General    ////
1538
//// Public License along with this source; if not, download it   ////
1539
//// from http://www.opencores.org/lgpl.shtml                     ////
1540
////                                                              ////
1541
//////////////////////////////////////////////////////////////////////
1542
 
1543
// binary counter
1544
 
1545 40 unneback
`define MODULE cnt_bin_ce_clear
1546
module `BASE`MODULE (
1547
`undef MODULE
1548
 clear, cke, q, rst, clk);
1549
 
1550 6 unneback
   parameter length = 4;
1551
   input clear;
1552
   input cke;
1553
   output [length:1] q;
1554
   input rst;
1555
   input clk;
1556
 
1557
   parameter clear_value = 0;
1558
   parameter set_value = 1;
1559
   parameter wrap_value = 0;
1560
   parameter level1_value = 15;
1561
 
1562
   reg  [length:1] qi;
1563
   wire [length:1] q_next;
1564
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1565
 
1566
   always @ (posedge clk or posedge rst)
1567
     if (rst)
1568
       qi <= {length{1'b0}};
1569
     else
1570
     if (cke)
1571
       qi <= q_next;
1572
 
1573
   assign q = qi;
1574
 
1575
endmodule
1576 40 unneback
`endif
1577
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1578 6 unneback
//////////////////////////////////////////////////////////////////////
1579
////                                                              ////
1580
////  Versatile counter                                           ////
1581
////                                                              ////
1582
////  Description                                                 ////
1583
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1584
////  counter                                                     ////
1585
////                                                              ////
1586
////  To Do:                                                      ////
1587
////   - add LFSR with more taps                                  ////
1588
////                                                              ////
1589
////  Author(s):                                                  ////
1590
////      - Michael Unneback, unneback@opencores.org              ////
1591
////        ORSoC AB                                              ////
1592
////                                                              ////
1593
//////////////////////////////////////////////////////////////////////
1594
////                                                              ////
1595
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1596
////                                                              ////
1597
//// This source file may be used and distributed without         ////
1598
//// restriction provided that this copyright statement is not    ////
1599
//// removed from the file and that any derivative work contains  ////
1600
//// the original copyright notice and the associated disclaimer. ////
1601
////                                                              ////
1602
//// This source file is free software; you can redistribute it   ////
1603
//// and/or modify it under the terms of the GNU Lesser General   ////
1604
//// Public License as published by the Free Software Foundation; ////
1605
//// either version 2.1 of the License, or (at your option) any   ////
1606
//// later version.                                               ////
1607
////                                                              ////
1608
//// This source is distributed in the hope that it will be       ////
1609
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1610
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1611
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1612
//// details.                                                     ////
1613
////                                                              ////
1614
//// You should have received a copy of the GNU Lesser General    ////
1615
//// Public License along with this source; if not, download it   ////
1616
//// from http://www.opencores.org/lgpl.shtml                     ////
1617
////                                                              ////
1618
//////////////////////////////////////////////////////////////////////
1619
 
1620
// binary counter
1621 29 unneback
 
1622 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1623
module `BASE`MODULE (
1624
`undef MODULE
1625
 clear, cke, q, level1, level2, rst, clk);
1626
 
1627 29 unneback
   parameter length = 4;
1628
   input clear;
1629
   input cke;
1630
   output [length:1] q;
1631
   output reg level1;
1632
   output reg level2;
1633
   input rst;
1634
   input clk;
1635
 
1636
   parameter clear_value = 0;
1637
   parameter set_value = 1;
1638 30 unneback
   parameter wrap_value = 15;
1639
   parameter level1_value = 8;
1640
   parameter level2_value = 15;
1641 29 unneback
 
1642
   wire rew;
1643 30 unneback
   assign rew = 1'b0;
1644 29 unneback
   reg  [length:1] qi;
1645
   wire [length:1] q_next;
1646
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1647
 
1648
   always @ (posedge clk or posedge rst)
1649
     if (rst)
1650
       qi <= {length{1'b0}};
1651
     else
1652
     if (cke)
1653
       qi <= q_next;
1654
 
1655
   assign q = qi;
1656
 
1657
 
1658
    always @ (posedge clk or posedge rst)
1659
    if (rst)
1660
        level1 <= 1'b0;
1661
    else
1662
    if (cke)
1663
    if (clear)
1664
        level1 <= 1'b0;
1665
    else if (q_next == level1_value)
1666
        level1 <= 1'b1;
1667
    else if (qi == level1_value & rew)
1668
        level1 <= 1'b0;
1669
 
1670
    always @ (posedge clk or posedge rst)
1671
    if (rst)
1672
        level2 <= 1'b0;
1673
    else
1674
    if (cke)
1675
    if (clear)
1676
        level2 <= 1'b0;
1677
    else if (q_next == level2_value)
1678
        level2 <= 1'b1;
1679
    else if (qi == level2_value & rew)
1680
        level2 <= 1'b0;
1681
endmodule
1682 40 unneback
`endif
1683
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1684 29 unneback
//////////////////////////////////////////////////////////////////////
1685
////                                                              ////
1686
////  Versatile counter                                           ////
1687
////                                                              ////
1688
////  Description                                                 ////
1689
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1690
////  counter                                                     ////
1691
////                                                              ////
1692
////  To Do:                                                      ////
1693
////   - add LFSR with more taps                                  ////
1694
////                                                              ////
1695
////  Author(s):                                                  ////
1696
////      - Michael Unneback, unneback@opencores.org              ////
1697
////        ORSoC AB                                              ////
1698
////                                                              ////
1699
//////////////////////////////////////////////////////////////////////
1700
////                                                              ////
1701
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1702
////                                                              ////
1703
//// This source file may be used and distributed without         ////
1704
//// restriction provided that this copyright statement is not    ////
1705
//// removed from the file and that any derivative work contains  ////
1706
//// the original copyright notice and the associated disclaimer. ////
1707
////                                                              ////
1708
//// This source file is free software; you can redistribute it   ////
1709
//// and/or modify it under the terms of the GNU Lesser General   ////
1710
//// Public License as published by the Free Software Foundation; ////
1711
//// either version 2.1 of the License, or (at your option) any   ////
1712
//// later version.                                               ////
1713
////                                                              ////
1714
//// This source is distributed in the hope that it will be       ////
1715
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1716
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1717
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1718
//// details.                                                     ////
1719
////                                                              ////
1720
//// You should have received a copy of the GNU Lesser General    ////
1721
//// Public License along with this source; if not, download it   ////
1722
//// from http://www.opencores.org/lgpl.shtml                     ////
1723
////                                                              ////
1724
//////////////////////////////////////////////////////////////////////
1725
 
1726
// binary counter
1727 6 unneback
 
1728 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1729
module `BASE`MODULE (
1730
`undef MODULE
1731
 clear, set, cke, rew, q, rst, clk);
1732
 
1733 6 unneback
   parameter length = 4;
1734
   input clear;
1735
   input set;
1736
   input cke;
1737
   input rew;
1738
   output [length:1] q;
1739
   input rst;
1740
   input clk;
1741
 
1742
   parameter clear_value = 0;
1743
   parameter set_value = 1;
1744
   parameter wrap_value = 0;
1745
   parameter level1_value = 15;
1746
 
1747
   reg  [length:1] qi;
1748
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1749
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1750
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1751
   assign q_next = rew ? q_next_rew : q_next_fw;
1752
 
1753
   always @ (posedge clk or posedge rst)
1754
     if (rst)
1755
       qi <= {length{1'b0}};
1756
     else
1757
     if (cke)
1758
       qi <= q_next;
1759
 
1760
   assign q = qi;
1761
 
1762
endmodule
1763 40 unneback
`endif
1764
`ifdef CNT_BIN_CE_REW_L1
1765 6 unneback
//////////////////////////////////////////////////////////////////////
1766
////                                                              ////
1767
////  Versatile counter                                           ////
1768
////                                                              ////
1769
////  Description                                                 ////
1770
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1771
////  counter                                                     ////
1772
////                                                              ////
1773
////  To Do:                                                      ////
1774
////   - add LFSR with more taps                                  ////
1775
////                                                              ////
1776
////  Author(s):                                                  ////
1777
////      - Michael Unneback, unneback@opencores.org              ////
1778
////        ORSoC AB                                              ////
1779
////                                                              ////
1780
//////////////////////////////////////////////////////////////////////
1781
////                                                              ////
1782
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1783
////                                                              ////
1784
//// This source file may be used and distributed without         ////
1785
//// restriction provided that this copyright statement is not    ////
1786
//// removed from the file and that any derivative work contains  ////
1787
//// the original copyright notice and the associated disclaimer. ////
1788
////                                                              ////
1789
//// This source file is free software; you can redistribute it   ////
1790
//// and/or modify it under the terms of the GNU Lesser General   ////
1791
//// Public License as published by the Free Software Foundation; ////
1792
//// either version 2.1 of the License, or (at your option) any   ////
1793
//// later version.                                               ////
1794
////                                                              ////
1795
//// This source is distributed in the hope that it will be       ////
1796
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1797
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1798
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1799
//// details.                                                     ////
1800
////                                                              ////
1801
//// You should have received a copy of the GNU Lesser General    ////
1802
//// Public License along with this source; if not, download it   ////
1803
//// from http://www.opencores.org/lgpl.shtml                     ////
1804
////                                                              ////
1805
//////////////////////////////////////////////////////////////////////
1806
 
1807
// binary counter
1808
 
1809 40 unneback
`define MODULE cnt_bin_ce_rew_l1
1810
module `BASE`MODULE (
1811
`undef MODULE
1812
 cke, rew, level1, rst, clk);
1813
 
1814 6 unneback
   parameter length = 4;
1815
   input cke;
1816
   input rew;
1817
   output reg level1;
1818
   input rst;
1819
   input clk;
1820
 
1821
   parameter clear_value = 0;
1822
   parameter set_value = 1;
1823
   parameter wrap_value = 1;
1824
   parameter level1_value = 15;
1825
 
1826 29 unneback
   wire clear;
1827 30 unneback
   assign clear = 1'b0;
1828 6 unneback
   reg  [length:1] qi;
1829
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1830
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1831
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1832
   assign q_next = rew ? q_next_rew : q_next_fw;
1833
 
1834
   always @ (posedge clk or posedge rst)
1835
     if (rst)
1836
       qi <= {length{1'b0}};
1837
     else
1838
     if (cke)
1839
       qi <= q_next;
1840
 
1841
 
1842
 
1843
    always @ (posedge clk or posedge rst)
1844
    if (rst)
1845
        level1 <= 1'b0;
1846
    else
1847
    if (cke)
1848 29 unneback
    if (clear)
1849
        level1 <= 1'b0;
1850
    else if (q_next == level1_value)
1851 6 unneback
        level1 <= 1'b1;
1852
    else if (qi == level1_value & rew)
1853
        level1 <= 1'b0;
1854
endmodule
1855 40 unneback
`endif
1856
`ifdef CNT_BIN_CE_REW_ZQ_L1
1857 6 unneback
//////////////////////////////////////////////////////////////////////
1858
////                                                              ////
1859
////  Versatile counter                                           ////
1860
////                                                              ////
1861
////  Description                                                 ////
1862
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1863
////  counter                                                     ////
1864
////                                                              ////
1865
////  To Do:                                                      ////
1866
////   - add LFSR with more taps                                  ////
1867
////                                                              ////
1868
////  Author(s):                                                  ////
1869
////      - Michael Unneback, unneback@opencores.org              ////
1870
////        ORSoC AB                                              ////
1871
////                                                              ////
1872
//////////////////////////////////////////////////////////////////////
1873
////                                                              ////
1874
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1875
////                                                              ////
1876
//// This source file may be used and distributed without         ////
1877
//// restriction provided that this copyright statement is not    ////
1878
//// removed from the file and that any derivative work contains  ////
1879
//// the original copyright notice and the associated disclaimer. ////
1880
////                                                              ////
1881
//// This source file is free software; you can redistribute it   ////
1882
//// and/or modify it under the terms of the GNU Lesser General   ////
1883
//// Public License as published by the Free Software Foundation; ////
1884
//// either version 2.1 of the License, or (at your option) any   ////
1885
//// later version.                                               ////
1886
////                                                              ////
1887
//// This source is distributed in the hope that it will be       ////
1888
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1889
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1890
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1891
//// details.                                                     ////
1892
////                                                              ////
1893
//// You should have received a copy of the GNU Lesser General    ////
1894
//// Public License along with this source; if not, download it   ////
1895
//// from http://www.opencores.org/lgpl.shtml                     ////
1896
////                                                              ////
1897
//////////////////////////////////////////////////////////////////////
1898
 
1899 25 unneback
// binary counter
1900
 
1901 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
1902
module `BASE`MODULE (
1903
`undef MODULE
1904
 cke, rew, zq, level1, rst, clk);
1905
 
1906 25 unneback
   parameter length = 4;
1907
   input cke;
1908
   input rew;
1909
   output reg zq;
1910
   output reg level1;
1911
   input rst;
1912
   input clk;
1913
 
1914
   parameter clear_value = 0;
1915
   parameter set_value = 1;
1916
   parameter wrap_value = 1;
1917
   parameter level1_value = 15;
1918
 
1919 29 unneback
   wire clear;
1920 30 unneback
   assign clear = 1'b0;
1921 25 unneback
   reg  [length:1] qi;
1922
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1923
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1924
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1925
   assign q_next = rew ? q_next_rew : q_next_fw;
1926
 
1927
   always @ (posedge clk or posedge rst)
1928
     if (rst)
1929
       qi <= {length{1'b0}};
1930
     else
1931
     if (cke)
1932
       qi <= q_next;
1933
 
1934
 
1935
 
1936
   always @ (posedge clk or posedge rst)
1937
     if (rst)
1938
       zq <= 1'b1;
1939
     else
1940
     if (cke)
1941
       zq <= q_next == {length{1'b0}};
1942
 
1943
    always @ (posedge clk or posedge rst)
1944
    if (rst)
1945
        level1 <= 1'b0;
1946
    else
1947
    if (cke)
1948 29 unneback
    if (clear)
1949
        level1 <= 1'b0;
1950
    else if (q_next == level1_value)
1951 25 unneback
        level1 <= 1'b1;
1952
    else if (qi == level1_value & rew)
1953
        level1 <= 1'b0;
1954
endmodule
1955 40 unneback
`endif
1956
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
1957 25 unneback
//////////////////////////////////////////////////////////////////////
1958
////                                                              ////
1959
////  Versatile counter                                           ////
1960
////                                                              ////
1961
////  Description                                                 ////
1962
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1963
////  counter                                                     ////
1964
////                                                              ////
1965
////  To Do:                                                      ////
1966
////   - add LFSR with more taps                                  ////
1967
////                                                              ////
1968
////  Author(s):                                                  ////
1969
////      - Michael Unneback, unneback@opencores.org              ////
1970
////        ORSoC AB                                              ////
1971
////                                                              ////
1972
//////////////////////////////////////////////////////////////////////
1973
////                                                              ////
1974
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1975
////                                                              ////
1976
//// This source file may be used and distributed without         ////
1977
//// restriction provided that this copyright statement is not    ////
1978
//// removed from the file and that any derivative work contains  ////
1979
//// the original copyright notice and the associated disclaimer. ////
1980
////                                                              ////
1981
//// This source file is free software; you can redistribute it   ////
1982
//// and/or modify it under the terms of the GNU Lesser General   ////
1983
//// Public License as published by the Free Software Foundation; ////
1984
//// either version 2.1 of the License, or (at your option) any   ////
1985
//// later version.                                               ////
1986
////                                                              ////
1987
//// This source is distributed in the hope that it will be       ////
1988
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1989
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1990
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1991
//// details.                                                     ////
1992
////                                                              ////
1993
//// You should have received a copy of the GNU Lesser General    ////
1994
//// Public License along with this source; if not, download it   ////
1995
//// from http://www.opencores.org/lgpl.shtml                     ////
1996
////                                                              ////
1997
//////////////////////////////////////////////////////////////////////
1998
 
1999
// binary counter
2000
 
2001 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2002
module `BASE`MODULE (
2003
`undef MODULE
2004
 cke, rew, q, zq, level1, rst, clk);
2005
 
2006 25 unneback
   parameter length = 4;
2007
   input cke;
2008
   input rew;
2009
   output [length:1] q;
2010
   output reg zq;
2011
   output reg level1;
2012
   input rst;
2013
   input clk;
2014
 
2015
   parameter clear_value = 0;
2016
   parameter set_value = 1;
2017
   parameter wrap_value = 1;
2018
   parameter level1_value = 15;
2019
 
2020 29 unneback
   wire clear;
2021 30 unneback
   assign clear = 1'b0;
2022 25 unneback
   reg  [length:1] qi;
2023
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2024
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2025
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2026
   assign q_next = rew ? q_next_rew : q_next_fw;
2027
 
2028
   always @ (posedge clk or posedge rst)
2029
     if (rst)
2030
       qi <= {length{1'b0}};
2031
     else
2032
     if (cke)
2033
       qi <= q_next;
2034
 
2035
   assign q = qi;
2036
 
2037
 
2038
   always @ (posedge clk or posedge rst)
2039
     if (rst)
2040
       zq <= 1'b1;
2041
     else
2042
     if (cke)
2043
       zq <= q_next == {length{1'b0}};
2044
 
2045
    always @ (posedge clk or posedge rst)
2046
    if (rst)
2047
        level1 <= 1'b0;
2048
    else
2049
    if (cke)
2050 29 unneback
    if (clear)
2051
        level1 <= 1'b0;
2052
    else if (q_next == level1_value)
2053 25 unneback
        level1 <= 1'b1;
2054
    else if (qi == level1_value & rew)
2055
        level1 <= 1'b0;
2056
endmodule
2057 40 unneback
`endif
2058
`ifdef CNT_LFSR_ZQ
2059 25 unneback
//////////////////////////////////////////////////////////////////////
2060
////                                                              ////
2061
////  Versatile counter                                           ////
2062
////                                                              ////
2063
////  Description                                                 ////
2064
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2065
////  counter                                                     ////
2066
////                                                              ////
2067
////  To Do:                                                      ////
2068
////   - add LFSR with more taps                                  ////
2069
////                                                              ////
2070
////  Author(s):                                                  ////
2071
////      - Michael Unneback, unneback@opencores.org              ////
2072
////        ORSoC AB                                              ////
2073
////                                                              ////
2074
//////////////////////////////////////////////////////////////////////
2075
////                                                              ////
2076
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2077
////                                                              ////
2078
//// This source file may be used and distributed without         ////
2079
//// restriction provided that this copyright statement is not    ////
2080
//// removed from the file and that any derivative work contains  ////
2081
//// the original copyright notice and the associated disclaimer. ////
2082
////                                                              ////
2083
//// This source file is free software; you can redistribute it   ////
2084
//// and/or modify it under the terms of the GNU Lesser General   ////
2085
//// Public License as published by the Free Software Foundation; ////
2086
//// either version 2.1 of the License, or (at your option) any   ////
2087
//// later version.                                               ////
2088
////                                                              ////
2089
//// This source is distributed in the hope that it will be       ////
2090
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2091
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2092
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2093
//// details.                                                     ////
2094
////                                                              ////
2095
//// You should have received a copy of the GNU Lesser General    ////
2096
//// Public License along with this source; if not, download it   ////
2097
//// from http://www.opencores.org/lgpl.shtml                     ////
2098
////                                                              ////
2099
//////////////////////////////////////////////////////////////////////
2100
 
2101 6 unneback
// LFSR counter
2102
 
2103 40 unneback
`define MODULE cnt_lfsr_zq
2104
module `BASE`MODULE (
2105
`undef MODULE
2106
 zq, rst, clk);
2107
 
2108 6 unneback
   parameter length = 4;
2109
   output reg zq;
2110
   input rst;
2111
   input clk;
2112
 
2113
   parameter clear_value = 0;
2114
   parameter set_value = 1;
2115
   parameter wrap_value = 8;
2116
   parameter level1_value = 15;
2117
 
2118
   reg  [length:1] qi;
2119
   reg lfsr_fb;
2120
   wire [length:1] q_next;
2121
   reg [32:1] polynom;
2122
   integer i;
2123
 
2124
   always @ (qi)
2125
   begin
2126
        case (length)
2127
         2: polynom = 32'b11;                               // 0x3
2128
         3: polynom = 32'b110;                              // 0x6
2129
         4: polynom = 32'b1100;                             // 0xC
2130
         5: polynom = 32'b10100;                            // 0x14
2131
         6: polynom = 32'b110000;                           // 0x30
2132
         7: polynom = 32'b1100000;                          // 0x60
2133
         8: polynom = 32'b10111000;                         // 0xb8
2134
         9: polynom = 32'b100010000;                        // 0x110
2135
        10: polynom = 32'b1001000000;                       // 0x240
2136
        11: polynom = 32'b10100000000;                      // 0x500
2137
        12: polynom = 32'b100000101001;                     // 0x829
2138
        13: polynom = 32'b1000000001100;                    // 0x100C
2139
        14: polynom = 32'b10000000010101;                   // 0x2015
2140
        15: polynom = 32'b110000000000000;                  // 0x6000
2141
        16: polynom = 32'b1101000000001000;                 // 0xD008
2142
        17: polynom = 32'b10010000000000000;                // 0x12000
2143
        18: polynom = 32'b100000010000000000;               // 0x20400
2144
        19: polynom = 32'b1000000000000100011;              // 0x40023
2145 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2146 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2147
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2148
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2149
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2150
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2151
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2152
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2153
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2154
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2155
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2156
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2157
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2158
        default: polynom = 32'b0;
2159
        endcase
2160
        lfsr_fb = qi[length];
2161
        for (i=length-1; i>=1; i=i-1) begin
2162
            if (polynom[i])
2163
                lfsr_fb = lfsr_fb  ~^ qi[i];
2164
        end
2165
    end
2166
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2167
 
2168
   always @ (posedge clk or posedge rst)
2169
     if (rst)
2170
       qi <= {length{1'b0}};
2171
     else
2172
       qi <= q_next;
2173
 
2174
 
2175
 
2176
   always @ (posedge clk or posedge rst)
2177
     if (rst)
2178
       zq <= 1'b1;
2179
     else
2180
       zq <= q_next == {length{1'b0}};
2181
endmodule
2182 40 unneback
`endif
2183
`ifdef CNT_LFSR_CE_ZQ
2184 6 unneback
//////////////////////////////////////////////////////////////////////
2185
////                                                              ////
2186
////  Versatile counter                                           ////
2187
////                                                              ////
2188
////  Description                                                 ////
2189
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2190
////  counter                                                     ////
2191
////                                                              ////
2192
////  To Do:                                                      ////
2193
////   - add LFSR with more taps                                  ////
2194
////                                                              ////
2195
////  Author(s):                                                  ////
2196
////      - Michael Unneback, unneback@opencores.org              ////
2197
////        ORSoC AB                                              ////
2198
////                                                              ////
2199
//////////////////////////////////////////////////////////////////////
2200
////                                                              ////
2201
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2202
////                                                              ////
2203
//// This source file may be used and distributed without         ////
2204
//// restriction provided that this copyright statement is not    ////
2205
//// removed from the file and that any derivative work contains  ////
2206
//// the original copyright notice and the associated disclaimer. ////
2207
////                                                              ////
2208
//// This source file is free software; you can redistribute it   ////
2209
//// and/or modify it under the terms of the GNU Lesser General   ////
2210
//// Public License as published by the Free Software Foundation; ////
2211
//// either version 2.1 of the License, or (at your option) any   ////
2212
//// later version.                                               ////
2213
////                                                              ////
2214
//// This source is distributed in the hope that it will be       ////
2215
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2216
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2217
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2218
//// details.                                                     ////
2219
////                                                              ////
2220
//// You should have received a copy of the GNU Lesser General    ////
2221
//// Public License along with this source; if not, download it   ////
2222
//// from http://www.opencores.org/lgpl.shtml                     ////
2223
////                                                              ////
2224
//////////////////////////////////////////////////////////////////////
2225
 
2226
// LFSR counter
2227
 
2228 40 unneback
`define MODULE cnt_lfsr_ce_zq
2229
module `BASE`MODULE (
2230
`undef MODULE
2231
 cke, zq, rst, clk);
2232
 
2233 6 unneback
   parameter length = 4;
2234
   input cke;
2235
   output reg zq;
2236
   input rst;
2237
   input clk;
2238
 
2239
   parameter clear_value = 0;
2240
   parameter set_value = 1;
2241
   parameter wrap_value = 8;
2242
   parameter level1_value = 15;
2243
 
2244
   reg  [length:1] qi;
2245
   reg lfsr_fb;
2246
   wire [length:1] q_next;
2247
   reg [32:1] polynom;
2248
   integer i;
2249
 
2250
   always @ (qi)
2251
   begin
2252
        case (length)
2253
         2: polynom = 32'b11;                               // 0x3
2254
         3: polynom = 32'b110;                              // 0x6
2255
         4: polynom = 32'b1100;                             // 0xC
2256
         5: polynom = 32'b10100;                            // 0x14
2257
         6: polynom = 32'b110000;                           // 0x30
2258
         7: polynom = 32'b1100000;                          // 0x60
2259
         8: polynom = 32'b10111000;                         // 0xb8
2260
         9: polynom = 32'b100010000;                        // 0x110
2261
        10: polynom = 32'b1001000000;                       // 0x240
2262
        11: polynom = 32'b10100000000;                      // 0x500
2263
        12: polynom = 32'b100000101001;                     // 0x829
2264
        13: polynom = 32'b1000000001100;                    // 0x100C
2265
        14: polynom = 32'b10000000010101;                   // 0x2015
2266
        15: polynom = 32'b110000000000000;                  // 0x6000
2267
        16: polynom = 32'b1101000000001000;                 // 0xD008
2268
        17: polynom = 32'b10010000000000000;                // 0x12000
2269
        18: polynom = 32'b100000010000000000;               // 0x20400
2270
        19: polynom = 32'b1000000000000100011;              // 0x40023
2271 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2272 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2273
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2274
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2275
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2276
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2277
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2278
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2279
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2280
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2281
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2282
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2283
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2284
        default: polynom = 32'b0;
2285
        endcase
2286
        lfsr_fb = qi[length];
2287
        for (i=length-1; i>=1; i=i-1) begin
2288
            if (polynom[i])
2289
                lfsr_fb = lfsr_fb  ~^ qi[i];
2290
        end
2291
    end
2292
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2293
 
2294
   always @ (posedge clk or posedge rst)
2295
     if (rst)
2296
       qi <= {length{1'b0}};
2297
     else
2298
     if (cke)
2299
       qi <= q_next;
2300
 
2301
 
2302
 
2303
   always @ (posedge clk or posedge rst)
2304
     if (rst)
2305
       zq <= 1'b1;
2306
     else
2307
     if (cke)
2308
       zq <= q_next == {length{1'b0}};
2309
endmodule
2310 40 unneback
`endif
2311
`ifdef CNT_LFSR_CE_Q
2312 6 unneback
//////////////////////////////////////////////////////////////////////
2313
////                                                              ////
2314
////  Versatile counter                                           ////
2315
////                                                              ////
2316
////  Description                                                 ////
2317
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2318
////  counter                                                     ////
2319
////                                                              ////
2320
////  To Do:                                                      ////
2321
////   - add LFSR with more taps                                  ////
2322
////                                                              ////
2323
////  Author(s):                                                  ////
2324
////      - Michael Unneback, unneback@opencores.org              ////
2325
////        ORSoC AB                                              ////
2326
////                                                              ////
2327
//////////////////////////////////////////////////////////////////////
2328
////                                                              ////
2329
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2330
////                                                              ////
2331
//// This source file may be used and distributed without         ////
2332
//// restriction provided that this copyright statement is not    ////
2333
//// removed from the file and that any derivative work contains  ////
2334
//// the original copyright notice and the associated disclaimer. ////
2335
////                                                              ////
2336
//// This source file is free software; you can redistribute it   ////
2337
//// and/or modify it under the terms of the GNU Lesser General   ////
2338
//// Public License as published by the Free Software Foundation; ////
2339
//// either version 2.1 of the License, or (at your option) any   ////
2340
//// later version.                                               ////
2341
////                                                              ////
2342
//// This source is distributed in the hope that it will be       ////
2343
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2344
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2345
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2346
//// details.                                                     ////
2347
////                                                              ////
2348
//// You should have received a copy of the GNU Lesser General    ////
2349
//// Public License along with this source; if not, download it   ////
2350
//// from http://www.opencores.org/lgpl.shtml                     ////
2351
////                                                              ////
2352
//////////////////////////////////////////////////////////////////////
2353 22 unneback
 
2354
// LFSR counter
2355 27 unneback
 
2356 40 unneback
`define MODULE cnt_lfsr_ce_q
2357
module `BASE`MODULE (
2358
`undef MODULE
2359
 cke, q, rst, clk);
2360
 
2361 27 unneback
   parameter length = 4;
2362
   input cke;
2363
   output [length:1] q;
2364
   input rst;
2365
   input clk;
2366
 
2367
   parameter clear_value = 0;
2368
   parameter set_value = 1;
2369
   parameter wrap_value = 8;
2370
   parameter level1_value = 15;
2371
 
2372
   reg  [length:1] qi;
2373
   reg lfsr_fb;
2374
   wire [length:1] q_next;
2375
   reg [32:1] polynom;
2376
   integer i;
2377
 
2378
   always @ (qi)
2379
   begin
2380
        case (length)
2381
         2: polynom = 32'b11;                               // 0x3
2382
         3: polynom = 32'b110;                              // 0x6
2383
         4: polynom = 32'b1100;                             // 0xC
2384
         5: polynom = 32'b10100;                            // 0x14
2385
         6: polynom = 32'b110000;                           // 0x30
2386
         7: polynom = 32'b1100000;                          // 0x60
2387
         8: polynom = 32'b10111000;                         // 0xb8
2388
         9: polynom = 32'b100010000;                        // 0x110
2389
        10: polynom = 32'b1001000000;                       // 0x240
2390
        11: polynom = 32'b10100000000;                      // 0x500
2391
        12: polynom = 32'b100000101001;                     // 0x829
2392
        13: polynom = 32'b1000000001100;                    // 0x100C
2393
        14: polynom = 32'b10000000010101;                   // 0x2015
2394
        15: polynom = 32'b110000000000000;                  // 0x6000
2395
        16: polynom = 32'b1101000000001000;                 // 0xD008
2396
        17: polynom = 32'b10010000000000000;                // 0x12000
2397
        18: polynom = 32'b100000010000000000;               // 0x20400
2398
        19: polynom = 32'b1000000000000100011;              // 0x40023
2399 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2400 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2401
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2402
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2403
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2404
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2405
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2406
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2407
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2408
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2409
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2410
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2411
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2412
        default: polynom = 32'b0;
2413
        endcase
2414
        lfsr_fb = qi[length];
2415
        for (i=length-1; i>=1; i=i-1) begin
2416
            if (polynom[i])
2417
                lfsr_fb = lfsr_fb  ~^ qi[i];
2418
        end
2419
    end
2420
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2421
 
2422
   always @ (posedge clk or posedge rst)
2423
     if (rst)
2424
       qi <= {length{1'b0}};
2425
     else
2426
     if (cke)
2427
       qi <= q_next;
2428
 
2429
   assign q = qi;
2430
 
2431
endmodule
2432 40 unneback
`endif
2433
`ifdef CNT_LFSR_CE_CLEAR_Q
2434 27 unneback
//////////////////////////////////////////////////////////////////////
2435
////                                                              ////
2436
////  Versatile counter                                           ////
2437
////                                                              ////
2438
////  Description                                                 ////
2439
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2440
////  counter                                                     ////
2441
////                                                              ////
2442
////  To Do:                                                      ////
2443
////   - add LFSR with more taps                                  ////
2444
////                                                              ////
2445
////  Author(s):                                                  ////
2446
////      - Michael Unneback, unneback@opencores.org              ////
2447
////        ORSoC AB                                              ////
2448
////                                                              ////
2449
//////////////////////////////////////////////////////////////////////
2450
////                                                              ////
2451
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2452
////                                                              ////
2453
//// This source file may be used and distributed without         ////
2454
//// restriction provided that this copyright statement is not    ////
2455
//// removed from the file and that any derivative work contains  ////
2456
//// the original copyright notice and the associated disclaimer. ////
2457
////                                                              ////
2458
//// This source file is free software; you can redistribute it   ////
2459
//// and/or modify it under the terms of the GNU Lesser General   ////
2460
//// Public License as published by the Free Software Foundation; ////
2461
//// either version 2.1 of the License, or (at your option) any   ////
2462
//// later version.                                               ////
2463
////                                                              ////
2464
//// This source is distributed in the hope that it will be       ////
2465
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2466
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2467
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2468
//// details.                                                     ////
2469
////                                                              ////
2470
//// You should have received a copy of the GNU Lesser General    ////
2471
//// Public License along with this source; if not, download it   ////
2472
//// from http://www.opencores.org/lgpl.shtml                     ////
2473
////                                                              ////
2474
//////////////////////////////////////////////////////////////////////
2475
 
2476
// LFSR counter
2477
 
2478 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2479
module `BASE`MODULE (
2480
`undef MODULE
2481
 clear, cke, q, rst, clk);
2482
 
2483 27 unneback
   parameter length = 4;
2484
   input clear;
2485
   input cke;
2486
   output [length:1] q;
2487
   input rst;
2488
   input clk;
2489
 
2490
   parameter clear_value = 0;
2491
   parameter set_value = 1;
2492
   parameter wrap_value = 8;
2493
   parameter level1_value = 15;
2494
 
2495
   reg  [length:1] qi;
2496
   reg lfsr_fb;
2497
   wire [length:1] q_next;
2498
   reg [32:1] polynom;
2499
   integer i;
2500
 
2501
   always @ (qi)
2502
   begin
2503
        case (length)
2504
         2: polynom = 32'b11;                               // 0x3
2505
         3: polynom = 32'b110;                              // 0x6
2506
         4: polynom = 32'b1100;                             // 0xC
2507
         5: polynom = 32'b10100;                            // 0x14
2508
         6: polynom = 32'b110000;                           // 0x30
2509
         7: polynom = 32'b1100000;                          // 0x60
2510
         8: polynom = 32'b10111000;                         // 0xb8
2511
         9: polynom = 32'b100010000;                        // 0x110
2512
        10: polynom = 32'b1001000000;                       // 0x240
2513
        11: polynom = 32'b10100000000;                      // 0x500
2514
        12: polynom = 32'b100000101001;                     // 0x829
2515
        13: polynom = 32'b1000000001100;                    // 0x100C
2516
        14: polynom = 32'b10000000010101;                   // 0x2015
2517
        15: polynom = 32'b110000000000000;                  // 0x6000
2518
        16: polynom = 32'b1101000000001000;                 // 0xD008
2519
        17: polynom = 32'b10010000000000000;                // 0x12000
2520
        18: polynom = 32'b100000010000000000;               // 0x20400
2521
        19: polynom = 32'b1000000000000100011;              // 0x40023
2522 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2523 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2524
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2525
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2526
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2527
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2528
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2529
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2530
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2531
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2532
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2533
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2534
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2535
        default: polynom = 32'b0;
2536
        endcase
2537
        lfsr_fb = qi[length];
2538
        for (i=length-1; i>=1; i=i-1) begin
2539
            if (polynom[i])
2540
                lfsr_fb = lfsr_fb  ~^ qi[i];
2541
        end
2542
    end
2543
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2544
 
2545
   always @ (posedge clk or posedge rst)
2546
     if (rst)
2547
       qi <= {length{1'b0}};
2548
     else
2549
     if (cke)
2550
       qi <= q_next;
2551
 
2552
   assign q = qi;
2553
 
2554
endmodule
2555 40 unneback
`endif
2556
`ifdef CNT_LFSR_CE_Q_ZQ
2557 27 unneback
//////////////////////////////////////////////////////////////////////
2558
////                                                              ////
2559
////  Versatile counter                                           ////
2560
////                                                              ////
2561
////  Description                                                 ////
2562
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2563
////  counter                                                     ////
2564
////                                                              ////
2565
////  To Do:                                                      ////
2566
////   - add LFSR with more taps                                  ////
2567
////                                                              ////
2568
////  Author(s):                                                  ////
2569
////      - Michael Unneback, unneback@opencores.org              ////
2570
////        ORSoC AB                                              ////
2571
////                                                              ////
2572
//////////////////////////////////////////////////////////////////////
2573
////                                                              ////
2574
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2575
////                                                              ////
2576
//// This source file may be used and distributed without         ////
2577
//// restriction provided that this copyright statement is not    ////
2578
//// removed from the file and that any derivative work contains  ////
2579
//// the original copyright notice and the associated disclaimer. ////
2580
////                                                              ////
2581
//// This source file is free software; you can redistribute it   ////
2582
//// and/or modify it under the terms of the GNU Lesser General   ////
2583
//// Public License as published by the Free Software Foundation; ////
2584
//// either version 2.1 of the License, or (at your option) any   ////
2585
//// later version.                                               ////
2586
////                                                              ////
2587
//// This source is distributed in the hope that it will be       ////
2588
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2589
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2590
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2591
//// details.                                                     ////
2592
////                                                              ////
2593
//// You should have received a copy of the GNU Lesser General    ////
2594
//// Public License along with this source; if not, download it   ////
2595
//// from http://www.opencores.org/lgpl.shtml                     ////
2596
////                                                              ////
2597
//////////////////////////////////////////////////////////////////////
2598
 
2599
// LFSR counter
2600 22 unneback
 
2601 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
2602
module `BASE`MODULE (
2603
`undef MODULE
2604
 cke, q, zq, rst, clk);
2605
 
2606 22 unneback
   parameter length = 4;
2607
   input cke;
2608
   output [length:1] q;
2609
   output reg zq;
2610
   input rst;
2611
   input clk;
2612
 
2613
   parameter clear_value = 0;
2614
   parameter set_value = 1;
2615
   parameter wrap_value = 8;
2616
   parameter level1_value = 15;
2617
 
2618
   reg  [length:1] qi;
2619
   reg lfsr_fb;
2620
   wire [length:1] q_next;
2621
   reg [32:1] polynom;
2622
   integer i;
2623
 
2624
   always @ (qi)
2625
   begin
2626
        case (length)
2627
         2: polynom = 32'b11;                               // 0x3
2628
         3: polynom = 32'b110;                              // 0x6
2629
         4: polynom = 32'b1100;                             // 0xC
2630
         5: polynom = 32'b10100;                            // 0x14
2631
         6: polynom = 32'b110000;                           // 0x30
2632
         7: polynom = 32'b1100000;                          // 0x60
2633
         8: polynom = 32'b10111000;                         // 0xb8
2634
         9: polynom = 32'b100010000;                        // 0x110
2635
        10: polynom = 32'b1001000000;                       // 0x240
2636
        11: polynom = 32'b10100000000;                      // 0x500
2637
        12: polynom = 32'b100000101001;                     // 0x829
2638
        13: polynom = 32'b1000000001100;                    // 0x100C
2639
        14: polynom = 32'b10000000010101;                   // 0x2015
2640
        15: polynom = 32'b110000000000000;                  // 0x6000
2641
        16: polynom = 32'b1101000000001000;                 // 0xD008
2642
        17: polynom = 32'b10010000000000000;                // 0x12000
2643
        18: polynom = 32'b100000010000000000;               // 0x20400
2644
        19: polynom = 32'b1000000000000100011;              // 0x40023
2645 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2646 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2647
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2648
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2649
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2650
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2651
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2652
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2653
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2654
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2655
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2656
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2657
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2658
        default: polynom = 32'b0;
2659
        endcase
2660
        lfsr_fb = qi[length];
2661
        for (i=length-1; i>=1; i=i-1) begin
2662
            if (polynom[i])
2663
                lfsr_fb = lfsr_fb  ~^ qi[i];
2664
        end
2665
    end
2666
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2667
 
2668
   always @ (posedge clk or posedge rst)
2669
     if (rst)
2670
       qi <= {length{1'b0}};
2671
     else
2672
     if (cke)
2673
       qi <= q_next;
2674
 
2675
   assign q = qi;
2676
 
2677
 
2678
   always @ (posedge clk or posedge rst)
2679
     if (rst)
2680
       zq <= 1'b1;
2681
     else
2682
     if (cke)
2683
       zq <= q_next == {length{1'b0}};
2684
endmodule
2685 40 unneback
`endif
2686
`ifdef CNT_LFSR_CE_REW_L1
2687 22 unneback
//////////////////////////////////////////////////////////////////////
2688
////                                                              ////
2689
////  Versatile counter                                           ////
2690
////                                                              ////
2691
////  Description                                                 ////
2692
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2693
////  counter                                                     ////
2694
////                                                              ////
2695
////  To Do:                                                      ////
2696
////   - add LFSR with more taps                                  ////
2697
////                                                              ////
2698
////  Author(s):                                                  ////
2699
////      - Michael Unneback, unneback@opencores.org              ////
2700
////        ORSoC AB                                              ////
2701
////                                                              ////
2702
//////////////////////////////////////////////////////////////////////
2703
////                                                              ////
2704
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2705
////                                                              ////
2706
//// This source file may be used and distributed without         ////
2707
//// restriction provided that this copyright statement is not    ////
2708
//// removed from the file and that any derivative work contains  ////
2709
//// the original copyright notice and the associated disclaimer. ////
2710
////                                                              ////
2711
//// This source file is free software; you can redistribute it   ////
2712
//// and/or modify it under the terms of the GNU Lesser General   ////
2713
//// Public License as published by the Free Software Foundation; ////
2714
//// either version 2.1 of the License, or (at your option) any   ////
2715
//// later version.                                               ////
2716
////                                                              ////
2717
//// This source is distributed in the hope that it will be       ////
2718
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2719
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2720
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2721
//// details.                                                     ////
2722
////                                                              ////
2723
//// You should have received a copy of the GNU Lesser General    ////
2724
//// Public License along with this source; if not, download it   ////
2725
//// from http://www.opencores.org/lgpl.shtml                     ////
2726
////                                                              ////
2727
//////////////////////////////////////////////////////////////////////
2728 6 unneback
 
2729
// LFSR counter
2730
 
2731 40 unneback
`define MODULE cnt_lfsr_ce_rew_l1
2732
module `BASE`MODULE (
2733
`undef MODULE
2734
 cke, rew, level1, rst, clk);
2735
 
2736 6 unneback
   parameter length = 4;
2737
   input cke;
2738
   input rew;
2739
   output reg level1;
2740
   input rst;
2741
   input clk;
2742
 
2743
   parameter clear_value = 0;
2744
   parameter set_value = 1;
2745
   parameter wrap_value = 8;
2746
   parameter level1_value = 15;
2747
 
2748 29 unneback
   wire clear;
2749 30 unneback
   assign clear = 1'b0;
2750 6 unneback
   reg  [length:1] qi;
2751
   reg lfsr_fb, lfsr_fb_rew;
2752
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2753
   reg [32:1] polynom_rew;
2754
   integer j;
2755
   reg [32:1] polynom;
2756
   integer i;
2757
 
2758
   always @ (qi)
2759
   begin
2760
        case (length)
2761
         2: polynom = 32'b11;                               // 0x3
2762
         3: polynom = 32'b110;                              // 0x6
2763
         4: polynom = 32'b1100;                             // 0xC
2764
         5: polynom = 32'b10100;                            // 0x14
2765
         6: polynom = 32'b110000;                           // 0x30
2766
         7: polynom = 32'b1100000;                          // 0x60
2767
         8: polynom = 32'b10111000;                         // 0xb8
2768
         9: polynom = 32'b100010000;                        // 0x110
2769
        10: polynom = 32'b1001000000;                       // 0x240
2770
        11: polynom = 32'b10100000000;                      // 0x500
2771
        12: polynom = 32'b100000101001;                     // 0x829
2772
        13: polynom = 32'b1000000001100;                    // 0x100C
2773
        14: polynom = 32'b10000000010101;                   // 0x2015
2774
        15: polynom = 32'b110000000000000;                  // 0x6000
2775
        16: polynom = 32'b1101000000001000;                 // 0xD008
2776
        17: polynom = 32'b10010000000000000;                // 0x12000
2777
        18: polynom = 32'b100000010000000000;               // 0x20400
2778
        19: polynom = 32'b1000000000000100011;              // 0x40023
2779 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2780 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2781
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2782
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2783
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2784
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2785
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2786
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2787
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2788
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2789
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2790
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2791
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2792
        default: polynom = 32'b0;
2793
        endcase
2794
        lfsr_fb = qi[length];
2795
        for (i=length-1; i>=1; i=i-1) begin
2796
            if (polynom[i])
2797
                lfsr_fb = lfsr_fb  ~^ qi[i];
2798
        end
2799
    end
2800
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2801
   always @ (qi)
2802
   begin
2803
        case (length)