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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 43

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 
`ifdef ALL
6 
 
7 
`define GBUF
8 
`define SYNC_RST
9 
`define PLL
10 
 
11 
`define MULTS
12 
`define MULTS18X18
13 
`define MULT
14 
`define SHIFT_UNIT_32
15 
`define LOGIC_UNIT
16 
 
17 
`define CNT_SHREG_WRAP
18 
`define CNT_SHREG_CE_WRAP
19 
`define CNT_SHREG_CE_CLEAR
20 
`define CNT_SHREG_CE_CLEAR_WRAP
21 
 
22 
`define MUX_ANDOR
23 
`define MUX2_ANDOR
24 
`define MUX3_ANDOR
25 
`define MUX4_ANDOR
26 
`define MUX5_ANDOR
27 
`define MUX6_ANDOR
28 43 unneback 
`define PARITY
29 40 unneback 
 
30 
`define ROM_INIT
31 
`define RAM
32 
`define RAM_BE
33 
`define DPRAM_1R1W
34 
`define DPRAM_2R1W
35 
`define DPRAM_2R2W
36 
`define FIFO_1R1W_FILL_LEVEL_SYNC
37 
`define FIFO_2R2W_SYNC_SIMPLEX
38 
`define FIFO_CMP_ASYNC
39 
`define FIFO_1R1W_ASYNC
40 
`define FIFO_2R2W_ASYNC
41 
`define FIFO_2R2W_ASYNC_SIMPLEX
42 
 
43 
`define DFF
44 
`define DFF_ARRAY
45 
`define DFF_CE
46 
`define DFF_CE_CLEAR
47 
`define DF_CE_SET
48 
`define SPR
49 
`define SRP
50 
`define DFF_SR
51 
`define LATCH
52 
`define SHREG
53 
`define SHREG_CE
54 
`define DELAY
55 
`define DELAY_EMPTYFLAG
56 
 
57 
`define WB3WB3_BRIDGE
58 
`define WB3_ARBITER_TYPE1
59 
`define WB_BOOT_ROM
60 
`define WB_DPRAM
61 
 
62 
`endif
63 
 
64 
`ifdef PLL
65 
`ifndef SYNC_RST
66 
`define SYNC_RST
67 
`endif
68 
`endif
69 
 
70 
`ifdef SYNC_RST
71 
`ifndef GBUF
72 
`define GBUF
73 
`endif
74 
`endif
75 
 
76 
`ifdef WB_DPRAM
77 
`ifndef DPRAM_2R2W
78 
`define DPRAM_2R2W
79 
`endif
80 
`ifndef SPR
81 
`define SPR
82 
`endif
83 
`endif
84 
 
85 
`ifdef WB3_ARBITER_TYPE1
86 42 unneback 
`ifndef SPR
87 
`define SPR
88 
`endif
89 40 unneback 
`ifndef MUX_ANDOR
90 
`define MUX_ANDOR
91 
`endif
92 
`endif
93 
 
94 
`ifdef WB3WB3_BRIDGE
95 
`ifndef CNT_SHREG_CE_CLEAR
96 
`define CNT_SHREG_CE_CLEAR
97 
`endif
98 
`ifndef DFF
99 
`define DFF
100 
`endif
101 
`ifndef DFF_CE
102 
`define DFF_CE
103 
`endif
104 
`ifndef CNT_SHREG_CE_CLEAR
105 
`define CNT_SHREG_CE_CLEAR
106 
`endif
107 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
108 
`define FIFO_2R2W_ASYNC_SIMPLEX
109 
`endif
110 
`endif
111 
 
112 
`ifdef MULTS18X18
113 
`ifndef MULTS
114 
`define MULTS
115 
`endif
116 
`endif
117 
 
118 
`ifdef SHIFT_UNIT_32
119 
`ifndef MULTS
120 
`define MULTS
121 
`endif
122 
`endif
123 
 
124 
`ifdef MUX2_ANDOR
125 
`ifndef MUX_ANDOR
126 
`define MUX_ANDOR
127 
`endif
128 
`endif
129 
 
130 
`ifdef MUX3_ANDOR
131 
`ifndef MUX_ANDOR
132 
`define MUX_ANDOR
133 
`endif
134 
`endif
135 
 
136 
`ifdef MUX4_ANDOR
137 
`ifndef MUX_ANDOR
138 
`define MUX_ANDOR
139 
`endif
140 
`endif
141 
 
142 
`ifdef MUX5_ANDOR
143 
`ifndef MUX_ANDOR
144 
`define MUX_ANDOR
145 
`endif
146 
`endif
147 
 
148 
`ifdef MUX6_ANDOR
149 
`ifndef MUX_ANDOR
150 
`define MUX_ANDOR
151 
`endif
152 
`endif
153 
 
154 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
155 
`ifndef CNT_BIN_CE
156 
`define CNT_BIN_CE
157 
`endif
158 
`ifndef DPRAM_1R1W
159 
`define DPRAM_1R1W
160 
`endif
161 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
162 
`define CNT_BIN_CE_REW_Q_ZQ_L1
163 
`endif
164 
`endif
165 
 
166 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
167 
`ifndef CNT_LFSR_CE
168 
`define CNT_LFSR_CE
169 
`endif
170 
`ifndef DPRAM_2R2W
171 
`define DPRAM_2R2W
172 
`endif
173 
`ifndef CNT_BIN_CE_REW_ZQ_L1
174 
`define CNT_BIN_CE_REW_ZQ_L1
175 
`endif
176 
`endif
177 
 
178 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
179 
`ifndef CNT_GRAY_CE_BIN
180 
`define CNT_GRAY_CE_BIN
181 
`endif
182 
`ifndef DPRAM_2R2W
183 
`define DPRAM_2R2W
184 
`endif
185 
`ifndef FIFO_CMP_ASYNC
186 
`define FIFO_CMP_ASYNC
187 
`endif
188 
`endif
189 
 
190 
`ifdef FIFO_2R2W_ASYNC
191 
`ifndef FIFO_1R1W_ASYNC
192 
`define FIFO_1R1W_ASYNC
193 
`endif
194 
`endif
195 
 
196 
`ifdef FIFO_1R1W_ASYNC
197 
`ifndef CNT_GRAY_CE_BIN
198 
`define CNT_GRAY_CE_BIN
199 
`endif
200 
`ifndef DPRAM_1R1W
201 
`define DPRAM_1R1W
202 
`endif
203 
`ifndef FIFO_CMP_ASYNC
204 
`define FIFO_CMP_ASYNC
205 
`endif
206 
`endif
207 
 
208 
`ifdef FIFO_CMP_ASYNC
209 
`ifndef DFF_SR
210 
`define DFF_SR
211 
`endif
212 
`ifndef DFF
213 
`define DFF
214 
`endif
215 
`endif
216 6 unneback 
//////////////////////////////////////////////////////////////////////
217 
////                                                              ////
218 
////  Versatile library, clock and reset                          ////
219 
////                                                              ////
220 
////  Description                                                 ////
221 
////  Logic related to clock and reset                            ////
222 
////                                                              ////
223 
////                                                              ////
224 
////  To Do:                                                      ////
225 
////   - add more different registers                             ////
226 
////                                                              ////
227 
////  Author(s):                                                  ////
228 
////      - Michael Unneback, unneback@opencores.org              ////
229 
////        ORSoC AB                                              ////
230 
////                                                              ////
231 
//////////////////////////////////////////////////////////////////////
232 
////                                                              ////
233 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
234 
////                                                              ////
235 
//// This source file may be used and distributed without         ////
236 
//// restriction provided that this copyright statement is not    ////
237 
//// removed from the file and that any derivative work contains  ////
238 
//// the original copyright notice and the associated disclaimer. ////
239 
////                                                              ////
240 
//// This source file is free software; you can redistribute it   ////
241 
//// and/or modify it under the terms of the GNU Lesser General   ////
242 
//// Public License as published by the Free Software Foundation; ////
243 
//// either version 2.1 of the License, or (at your option) any   ////
244 
//// later version.                                               ////
245 
////                                                              ////
246 
//// This source is distributed in the hope that it will be       ////
247 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
248 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
249 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
250 
//// details.                                                     ////
251 
////                                                              ////
252 
//// You should have received a copy of the GNU Lesser General    ////
253 
//// Public License along with this source; if not, download it   ////
254 
//// from http://www.opencores.org/lgpl.shtml                     ////
255 
////                                                              ////
256 
//////////////////////////////////////////////////////////////////////
257 
 
258 
// Global buffer
259 
// usage:
260 
// use to enable global buffers for high fan out signals such as clock and reset
261 
 
262 
`ifdef ACTEL
263 40 unneback 
`ifdef GBUF
264 6 unneback 
`timescale 1 ns/100 ps
265 
// Version: 8.4 8.4.0.33
266 
module gbuf(GL,CLK);
267 
output GL;
268 
input  CLK;
269 
 
270 
    wire GND;
271 
 
272 
    GND GND_1_net(.Y(GND));
273 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
274 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
275 
 
276 
endmodule
277 
`timescale 1 ns/1 ns
278 40 unneback 
`define MODULE gbuf
279 
module `BASE`MODULE ( i, o);
280 
`undef MODULE
281 6 unneback 
input i;
282 
output o;
283 
`ifdef SIM_GBUF
284 
assign o=i;
285 
`else
286 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
287 
`endif
288 
endmodule
289 40 unneback 
`endif
290 33 unneback 
 
291 6 unneback 
`else
292 33 unneback 
 
293 40 unneback 
`ifdef ALTERA
294 
`ifdef GBUF
295 21 unneback 
//altera
296 40 unneback 
`define MODULE gbuf
297 
module `BASE`MODULE ( i, o);
298 
`undef MODULE
299 33 unneback 
input i;
300 
output o;
301 
assign o = i;
302 
endmodule
303 40 unneback 
`endif
304 33 unneback 
 
305 6 unneback 
`else
306 
 
307 40 unneback 
`ifdef GBUF
308 6 unneback 
`timescale 1 ns/100 ps
309 40 unneback 
`define MODULE
310 
module `BASE`MODULE ( i, o);
311 
`undef MODULE
312 6 unneback 
input i;
313 
output o;
314 
assign o = i;
315 
endmodule
316 40 unneback 
`endif
317 6 unneback 
`endif // ALTERA
318 
`endif //ACTEL
319 
 
320 40 unneback 
`ifdef SYNC_RST
321 6 unneback 
// sync reset
322 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
323 6 unneback 
// output active high global reset sync with two DFFs
324 
`timescale 1 ns/100 ps
325 40 unneback 
`define MODULE sync_rst
326 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
327 
`undef MODULE
328 6 unneback 
input rst_n_i, clk;
329 
output rst_o;
330 18 unneback 
reg [1:0] tmp;
331 6 unneback 
always @ (posedge clk or negedge rst_n_i)
332 
if (!rst_n_i)
333 17 unneback 
        tmp <= 2'b11;
334 6 unneback 
else
335 33 unneback 
        tmp <= {1'b0,tmp[1]};
336 40 unneback 
`define MODULE gbuf
337 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
338 
`undef MODULE
339 6 unneback 
endmodule
340 40 unneback 
`endif
341 6 unneback 
 
342 40 unneback 
`ifdef PLL
343 6 unneback 
// vl_pll
344 
`ifdef ACTEL
345 32 unneback 
///////////////////////////////////////////////////////////////////////////////
346 17 unneback 
`timescale 1 ps/1 ps
347 40 unneback 
`define MODULE pll
348 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
349 
`undef MODULE
350 6 unneback 
parameter index = 0;
351 
parameter number_of_clk = 1;
352 17 unneback 
parameter period_time_0 = 20000;
353 
parameter period_time_1 = 20000;
354 
parameter period_time_2 = 20000;
355 
parameter lock_delay = 2000000;
356 6 unneback 
input clk_i, rst_n_i;
357 
output lock;
358 
output reg [0:number_of_clk-1] clk_o;
359 
output [0:number_of_clk-1] rst_o;
360 
 
361 
`ifdef SIM_PLL
362 
 
363 
always
364 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
365 
 
366 
generate if (number_of_clk > 1)
367 
always
368 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
369 
endgenerate
370 
 
371 
generate if (number_of_clk > 2)
372 
always
373 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
374 
endgenerate
375 
 
376 
genvar i;
377 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
378 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
379 
end
380 
endgenerate
381 
 
382 
assign #lock_delay lock = rst_n_i;
383 
 
384 
endmodule
385 
`else
386 
generate if (number_of_clk==1 & index==0) begin
387 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
388 
end
389 
endgenerate // index==0
390 
generate if (number_of_clk==1 & index==1) begin
391 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
392 
end
393 
endgenerate // index==1
394 
generate if (number_of_clk==1 & index==2) begin
395 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
396 
end
397 
endgenerate // index==2
398 
generate if (number_of_clk==1 & index==3) begin
399 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
400 
end
401 
endgenerate // index==0
402 
 
403 
generate if (number_of_clk==2 & index==0) begin
404 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
405 
end
406 
endgenerate // index==0
407 
generate if (number_of_clk==2 & index==1) begin
408 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
409 
end
410 
endgenerate // index==1
411 
generate if (number_of_clk==2 & index==2) begin
412 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
413 
end
414 
endgenerate // index==2
415 
generate if (number_of_clk==2 & index==3) begin
416 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
417 
end
418 
endgenerate // index==0
419 
 
420 
generate if (number_of_clk==3 & index==0) begin
421 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
422 
end
423 
endgenerate // index==0
424 
generate if (number_of_clk==3 & index==1) begin
425 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
426 
end
427 
endgenerate // index==1
428 
generate if (number_of_clk==3 & index==2) begin
429 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
430 
end
431 
endgenerate // index==2
432 
generate if (number_of_clk==3 & index==3) begin
433 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
434 
end
435 
endgenerate // index==0
436 
 
437 
genvar i;
438 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
439 40 unneback 
`define MODULE sync_rst
440 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
441 
`undef MODULE
442 6 unneback 
end
443 
endgenerate
444 
endmodule
445 
`endif
446 32 unneback 
///////////////////////////////////////////////////////////////////////////////
447 6 unneback 
 
448 
`else
449 
 
450 32 unneback 
///////////////////////////////////////////////////////////////////////////////
451 6 unneback 
`ifdef ALTERA
452 
 
453 32 unneback 
`timescale 1 ps/1 ps
454 40 unneback 
`define MODULE pll
455 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
456 
`undef MODULE
457 32 unneback 
parameter index = 0;
458 
parameter number_of_clk = 1;
459 
parameter period_time_0 = 20000;
460 
parameter period_time_1 = 20000;
461 
parameter period_time_2 = 20000;
462 
parameter period_time_3 = 20000;
463 
parameter period_time_4 = 20000;
464 
parameter lock_delay = 2000000;
465 
input clk_i, rst_n_i;
466 
output lock;
467 
output reg [0:number_of_clk-1] clk_o;
468 
output [0:number_of_clk-1] rst_o;
469 
 
470 
`ifdef SIM_PLL
471 
 
472 
always
473 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
474 
 
475 
generate if (number_of_clk > 1)
476 
always
477 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
478 
endgenerate
479 
 
480 
generate if (number_of_clk > 2)
481 
always
482 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
483 
endgenerate
484 
 
485 33 unneback 
generate if (number_of_clk > 3)
486 32 unneback 
always
487 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
488 
endgenerate
489 
 
490 33 unneback 
generate if (number_of_clk > 4)
491 32 unneback 
always
492 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
493 
endgenerate
494 
 
495 
genvar i;
496 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
497 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
498 
end
499 
endgenerate
500 
 
501 33 unneback 
//assign #lock_delay lock = rst_n_i;
502 
assign lock = rst_n_i;
503 32 unneback 
 
504 
endmodule
505 6 unneback 
`else
506 
 
507 33 unneback 
`ifdef VL_PLL0
508 
`ifdef VL_PLL0_CLK1
509 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
510 
`endif
511 
`ifdef VL_PLL0_CLK2
512 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
513 
`endif
514 
`ifdef VL_PLL0_CLK3
515 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
516 
`endif
517 
`ifdef VL_PLL0_CLK4
518 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
519 
`endif
520 
`ifdef VL_PLL0_CLK5
521 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
522 
`endif
523 
`endif
524 32 unneback 
 
525 33 unneback 
`ifdef VL_PLL1
526 
`ifdef VL_PLL1_CLK1
527 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
528 
`endif
529 
`ifdef VL_PLL1_CLK2
530 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
531 
`endif
532 
`ifdef VL_PLL1_CLK3
533 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
534 
`endif
535 
`ifdef VL_PLL1_CLK4
536 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
537 
`endif
538 
`ifdef VL_PLL1_CLK5
539 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
540 
`endif
541 
`endif
542 32 unneback 
 
543 33 unneback 
`ifdef VL_PLL2
544 
`ifdef VL_PLL2_CLK1
545 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
546 
`endif
547 
`ifdef VL_PLL2_CLK2
548 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
549 
`endif
550 
`ifdef VL_PLL2_CLK3
551 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
552 
`endif
553 
`ifdef VL_PLL2_CLK4
554 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
555 
`endif
556 
`ifdef VL_PLL2_CLK5
557 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
558 
`endif
559 
`endif
560 32 unneback 
 
561 33 unneback 
`ifdef VL_PLL3
562 
`ifdef VL_PLL3_CLK1
563 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
564 
`endif
565 
`ifdef VL_PLL3_CLK2
566 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
567 
`endif
568 
`ifdef VL_PLL3_CLK3
569 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
570 
`endif
571 
`ifdef VL_PLL3_CLK4
572 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
573 
`endif
574 
`ifdef VL_PLL3_CLK5
575 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
576 
`endif
577 
`endif
578 32 unneback 
 
579 
genvar i;
580 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
581 40 unneback 
`define MODULE sync_rst
582 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
583 
`undef MODULE
584 32 unneback 
end
585 
endgenerate
586 
endmodule
587 
`endif
588 
///////////////////////////////////////////////////////////////////////////////
589 
 
590 
`else
591 
 
592 6 unneback 
// generic PLL
593 17 unneback 
`timescale 1 ps/1 ps
594 40 unneback 
`define MODULE pll
595 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
596 
`undef MODULE
597 6 unneback 
parameter index = 0;
598 
parameter number_of_clk = 1;
599 17 unneback 
parameter period_time_0 = 20000;
600 
parameter period_time_1 = 20000;
601 
parameter period_time_2 = 20000;
602 6 unneback 
parameter lock_delay = 2000;
603 
input clk_i, rst_n_i;
604 
output lock;
605 
output reg [0:number_of_clk-1] clk_o;
606 
output [0:number_of_clk-1] rst_o;
607 
 
608 
always
609 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
610 
 
611 
generate if (number_of_clk > 1)
612 
always
613 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
614 
endgenerate
615 
 
616 
generate if (number_of_clk > 2)
617 
always
618 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
619 
endgenerate
620 
 
621 
genvar i;
622 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
623 40 unneback 
`define MODULE sync_rst
624 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
625 
`undef MODULE
626 6 unneback 
end
627 
endgenerate
628 
 
629 
assign #lock_delay lock = rst_n_i;
630 
 
631 
endmodule
632 
 
633 
`endif //altera
634 17 unneback 
`endif //actel
635 40 unneback 
`undef MODULE
636 
`endif//////////////////////////////////////////////////////////////////////
637 6 unneback 
////                                                              ////
638 
////  Versatile library, registers                                ////
639 
////                                                              ////
640 
////  Description                                                 ////
641 
////  Different type of registers                                 ////
642 
////                                                              ////
643 
////                                                              ////
644 
////  To Do:                                                      ////
645 
////   - add more different registers                             ////
646 
////                                                              ////
647 
////  Author(s):                                                  ////
648 
////      - Michael Unneback, unneback@opencores.org              ////
649 
////        ORSoC AB                                              ////
650 
////                                                              ////
651 
//////////////////////////////////////////////////////////////////////
652 
////                                                              ////
653 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
654 
////                                                              ////
655 
//// This source file may be used and distributed without         ////
656 
//// restriction provided that this copyright statement is not    ////
657 
//// removed from the file and that any derivative work contains  ////
658 
//// the original copyright notice and the associated disclaimer. ////
659 
////                                                              ////
660 
//// This source file is free software; you can redistribute it   ////
661 
//// and/or modify it under the terms of the GNU Lesser General   ////
662 
//// Public License as published by the Free Software Foundation; ////
663 
//// either version 2.1 of the License, or (at your option) any   ////
664 
//// later version.                                               ////
665 
////                                                              ////
666 
//// This source is distributed in the hope that it will be       ////
667 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
668 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
669 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
670 
//// details.                                                     ////
671 
////                                                              ////
672 
//// You should have received a copy of the GNU Lesser General    ////
673 
//// Public License along with this source; if not, download it   ////
674 
//// from http://www.opencores.org/lgpl.shtml                     ////
675 
////                                                              ////
676 
//////////////////////////////////////////////////////////////////////
677 
 
678 40 unneback 
`ifdef DFF
679 
`define MODULE dff
680 
module `BASE`MODULE ( d, q, clk, rst);
681 
`undef MODULE
682 6 unneback 
        parameter width = 1;
683 
        parameter reset_value = 0;
684 
 
685 
        input [width-1:0] d;
686 
        input clk, rst;
687 
        output reg [width-1:0] q;
688 
 
689 
        always @ (posedge clk or posedge rst)
690 
        if (rst)
691 
                q <= reset_value;
692 
        else
693 
                q <= d;
694 
 
695 
endmodule
696 40 unneback 
`endif
697 6 unneback 
 
698 40 unneback 
`ifdef DFF_ARRAY
699 
`define MODULE dff_array
700 
module `BASE`MODULE ( d, q, clk, rst);
701 
`undef MODULE
702 6 unneback 
 
703 
        parameter width = 1;
704 
        parameter depth = 2;
705 
        parameter reset_value = 1'b0;
706 
 
707 
        input [width-1:0] d;
708 
        input clk, rst;
709 
        output [width-1:0] q;
710 
        reg  [0:depth-1] q_tmp [width-1:0];
711 
        integer i;
712 
        always @ (posedge clk or posedge rst)
713 
        if (rst) begin
714 
            for (i=0;i<depth;i=i+1)
715 
                q_tmp[i] <= {width{reset_value}};
716 
        end else begin
717 
            q_tmp[0] <= d;
718 
            for (i=1;i<depth;i=i+1)
719 
                q_tmp[i] <= q_tmp[i-1];
720 
        end
721 
 
722 
    assign q = q_tmp[depth-1];
723 
 
724 
endmodule
725 40 unneback 
`endif
726 6 unneback 
 
727 40 unneback 
`ifdef DFF_CE
728 
`define MODULE dff_ce
729 
module `BASE`MODULE ( d, ce, q, clk, rst);
730 
`undef MODULE
731 6 unneback 
 
732 
        parameter width = 1;
733 
        parameter reset_value = 0;
734 
 
735 
        input [width-1:0] d;
736 
        input ce, clk, rst;
737 
        output reg [width-1:0] q;
738 
 
739 
        always @ (posedge clk or posedge rst)
740 
        if (rst)
741 
                q <= reset_value;
742 
        else
743 
                if (ce)
744 
                        q <= d;
745 
 
746 
endmodule
747 40 unneback 
`endif
748 6 unneback 
 
749 40 unneback 
`ifdef DFF_CE_CLEAR
750 
`define MODULE dff_ce_clear
751 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
752 
`undef MODULE
753 8 unneback 
 
754 
        parameter width = 1;
755 
        parameter reset_value = 0;
756 
 
757 
        input [width-1:0] d;
758 10 unneback 
        input ce, clear, clk, rst;
759 8 unneback 
        output reg [width-1:0] q;
760 
 
761 
        always @ (posedge clk or posedge rst)
762 
        if (rst)
763 
            q <= reset_value;
764 
        else
765 
            if (ce)
766 
                if (clear)
767 
                    q <= {width{1'b0}};
768 
                else
769 
                    q <= d;
770 
 
771 
endmodule
772 40 unneback 
`endif
773 8 unneback 
 
774 40 unneback 
`ifdef DF_CE_SET
775 
`define MODULE dff_ce_set
776 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
777 
`undef MODULE
778 24 unneback 
 
779 
        parameter width = 1;
780 
        parameter reset_value = 0;
781 
 
782 
        input [width-1:0] d;
783 
        input ce, set, clk, rst;
784 
        output reg [width-1:0] q;
785 
 
786 
        always @ (posedge clk or posedge rst)
787 
        if (rst)
788 
            q <= reset_value;
789 
        else
790 
            if (ce)
791 
                if (set)
792 
                    q <= {width{1'b1}};
793 
                else
794 
                    q <= d;
795 
 
796 
endmodule
797 40 unneback 
`endif
798 24 unneback 
 
799 40 unneback 
`ifdef SPR
800 
`define MODULE spr
801 
module `BASE`MODULE ( sp, r, q, clk, rst);
802 
`undef MODULE
803 
 
804 29 unneback 
        parameter width = 1;
805 
        parameter reset_value = 0;
806 
 
807 
        input sp, r;
808 
        output reg q;
809 
        input clk, rst;
810 
 
811 
        always @ (posedge clk or posedge rst)
812 
        if (rst)
813 
            q <= reset_value;
814 
        else
815 
            if (sp)
816 
                q <= 1'b1;
817 
            else if (r)
818 
                q <= 1'b0;
819 
 
820 
endmodule
821 40 unneback 
`endif
822 29 unneback 
 
823 40 unneback 
`ifdef SRP
824 
`define MODULE srp
825 
module `BASE`MODULE ( s, rp, q, clk, rst);
826 
`undef MODULE
827 
 
828 29 unneback 
        parameter width = 1;
829 
        parameter reset_value = 0;
830 
 
831 
        input s, rp;
832 
        output reg q;
833 
        input clk, rst;
834 
 
835 
        always @ (posedge clk or posedge rst)
836 
        if (rst)
837 
            q <= reset_value;
838 
        else
839 
            if (rp)
840 
                q <= 1'b0;
841 
            else if (s)
842 
                q <= 1'b1;
843 
 
844 
endmodule
845 40 unneback 
`endif
846 29 unneback 
 
847 40 unneback 
`ifdef ALTERA
848 29 unneback 
 
849 40 unneback 
`ifdef DFF_SR
850 6 unneback 
// megafunction wizard: %LPM_FF%
851 
// GENERATION: STANDARD
852 
// VERSION: WM1.0
853 
// MODULE: lpm_ff
854 
 
855 
// ============================================================
856 
// File Name: dff_sr.v
857 
// Megafunction Name(s):
858 
//                      lpm_ff
859 
//
860 
// Simulation Library Files(s):
861 
//                      lpm
862 
// ============================================================
863 
// ************************************************************
864 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
865 
//
866 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
867 
// ************************************************************
868 
 
869 
 
870 
//Copyright (C) 1991-2010 Altera Corporation
871 
//Your use of Altera Corporation's design tools, logic functions
872 
//and other software and tools, and its AMPP partner logic
873 
//functions, and any output files from any of the foregoing
874 
//(including device programming or simulation files), and any
875 
//associated documentation or information are expressly subject
876 
//to the terms and conditions of the Altera Program License
877 
//Subscription Agreement, Altera MegaCore Function License
878 
//Agreement, or other applicable license agreement, including,
879 
//without limitation, that your use is for the sole purpose of
880 
//programming logic devices manufactured by Altera and sold by
881 
//Altera or its authorized distributors.  Please refer to the
882 
//applicable agreement for further details.
883 
 
884 
 
885 
// synopsys translate_off
886 
`timescale 1 ps / 1 ps
887 
// synopsys translate_on
888 40 unneback 
`define MODULE dff_sr
889 
module `BASE`MODULE (
890 
`undef MODULE
891 
 
892 6 unneback 
        aclr,
893 
        aset,
894 
        clock,
895 
        data,
896 
        q);
897 
 
898 
        input     aclr;
899 
        input     aset;
900 
        input     clock;
901 
        input     data;
902 
        output    q;
903 
 
904 
        wire [0:0] sub_wire0;
905 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
906 
        wire  q = sub_wire1;
907 
        wire  sub_wire2 = data;
908 
        wire  sub_wire3 = sub_wire2;
909 
 
910 
        lpm_ff  lpm_ff_component (
911 
                                .aclr (aclr),
912 
                                .clock (clock),
913 
                                .data (sub_wire3),
914 
                                .aset (aset),
915 
                                .q (sub_wire0)
916 
                                // synopsys translate_off
917 
                                ,
918 
                                .aload (),
919 
                                .enable (),
920 
                                .sclr (),
921 
                                .sload (),
922 
                                .sset ()
923 
                                // synopsys translate_on
924 
                                );
925 
        defparam
926 
                lpm_ff_component.lpm_fftype = "DFF",
927 
                lpm_ff_component.lpm_type = "LPM_FF",
928 
                lpm_ff_component.lpm_width = 1;
929 
 
930 
 
931 
endmodule
932 
 
933 
// ============================================================
934 
// CNX file retrieval info
935 
// ============================================================
936 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
937 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
938 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
939 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
940 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
941 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
942 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
943 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
944 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
945 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
946 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
947 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
948 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
949 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
950 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
951 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
952 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
953 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
954 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
955 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
956 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
957 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
958 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
959 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
960 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
961 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
962 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
963 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
964 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
965 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
966 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
967 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
968 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
969 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
970 
// Retrieval info: LIB_FILE: lpm
971 40 unneback 
`endif
972 6 unneback 
 
973 
`else
974 
 
975 40 unneback 
`ifdef DFF_SR
976 
`define MODULE dff_sr
977 
module `BASE`MODULE ( aclr, aset, clock, data, q);
978 
`undef MODULE
979 6 unneback 
 
980 
    input         aclr;
981 
    input         aset;
982 
    input         clock;
983 
    input         data;
984 
    output reg    q;
985 
 
986 
   always @ (posedge clock or posedge aclr or posedge aset)
987 
     if (aclr)
988 
       q <= 1'b0;
989 
     else if (aset)
990 
       q <= 1'b1;
991 
     else
992 
       q <= data;
993 
 
994 
endmodule
995 40 unneback 
`endif
996 6 unneback 
 
997 
`endif
998 
 
999 
// LATCH
1000 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1001 
`ifdef ALTERA
1002 40 unneback 
 
1003 
`ifdef LATCH
1004 
`define MODULE latch
1005 
module `BASE`MODULE ( d, le, q, clk);
1006 
`undef MODULE
1007 6 unneback 
input d, le;
1008 
output q;
1009 
input clk;
1010 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1011 
endmodule
1012 40 unneback 
`endif
1013 
 
1014 6 unneback 
`else
1015 40 unneback 
 
1016 
`ifdef LATCH
1017 
`define MODULE latch
1018 
module `BASE`MODULE ( d, le, q, clk);
1019 
`undef MODULE
1020 6 unneback 
input d, le;
1021 
output q;
1022 
input clk;/*
1023 
   always @ (posedge direction_set or posedge direction_clr)
1024 
     if (direction_clr)
1025 
       direction <= going_empty;
1026 
     else
1027 
       direction <= going_full;*/
1028 
endmodule
1029 15 unneback 
`endif
1030 
 
1031 40 unneback 
`endif
1032 
 
1033 
`ifdef SHREG
1034 
`define MODULE shreg
1035 
module `BASE`MODULE ( d, q, clk, rst);
1036 
`undef MODULE
1037 
 
1038 17 unneback 
parameter depth = 10;
1039 
input d;
1040 
output q;
1041 
input clk, rst;
1042 
 
1043 
reg [1:depth] dffs;
1044 
 
1045 
always @ (posedge clk or posedge rst)
1046 
if (rst)
1047 
    dffs <= {depth{1'b0}};
1048 
else
1049 
    dffs <= {d,dffs[1:depth-1]};
1050 
assign q = dffs[depth];
1051 
endmodule
1052 40 unneback 
`endif
1053 17 unneback 
 
1054 40 unneback 
`ifdef SHREG_CE
1055 
`define MODULE shreg_ce
1056 
module `BASE`MODULE ( d, ce, q, clk, rst);
1057 
`undef MODULE
1058 17 unneback 
parameter depth = 10;
1059 
input d, ce;
1060 
output q;
1061 
input clk, rst;
1062 
 
1063 
reg [1:depth] dffs;
1064 
 
1065 
always @ (posedge clk or posedge rst)
1066 
if (rst)
1067 
    dffs <= {depth{1'b0}};
1068 
else
1069 
    if (ce)
1070 
        dffs <= {d,dffs[1:depth-1]};
1071 
assign q = dffs[depth];
1072 
endmodule
1073 40 unneback 
`endif
1074 17 unneback 
 
1075 40 unneback 
`ifdef DELAY
1076 
`define MODULE delay
1077 
module `BASE`MODULE ( d, q, clk, rst);
1078 
`undef MODULE
1079 15 unneback 
parameter depth = 10;
1080 
input d;
1081 
output q;
1082 
input clk, rst;
1083 
 
1084 
reg [1:depth] dffs;
1085 
 
1086 
always @ (posedge clk or posedge rst)
1087 
if (rst)
1088 
    dffs <= {depth{1'b0}};
1089 
else
1090 
    dffs <= {d,dffs[1:depth-1]};
1091 
assign q = dffs[depth];
1092 17 unneback 
endmodule
1093 40 unneback 
`endif
1094 17 unneback 
 
1095 40 unneback 
`ifdef DELAY_EMPTYFLAG
1096 
`define MODULE delay_emptyflag
1097 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1098 40 unneback 
`undef MODULE
1099 17 unneback 
parameter depth = 10;
1100 
input d;
1101 
output q, emptyflag;
1102 
input clk, rst;
1103 
 
1104 
reg [1:depth] dffs;
1105 
 
1106 
always @ (posedge clk or posedge rst)
1107 
if (rst)
1108 
    dffs <= {depth{1'b0}};
1109 
else
1110 
    dffs <= {d,dffs[1:depth-1]};
1111 
assign q = dffs[depth];
1112 
assign emptyflag = !(|dffs);
1113 
endmodule
1114 40 unneback 
`endif
1115 17 unneback 
//////////////////////////////////////////////////////////////////////
1116 6 unneback 
////                                                              ////
1117 18 unneback 
////  Logic functions                                             ////
1118 
////                                                              ////
1119 
////  Description                                                 ////
1120 
////  Logic functions such as multiplexers                        ////
1121 
////                                                              ////
1122 
////                                                              ////
1123 
////  To Do:                                                      ////
1124 
////   -                                                          ////
1125 
////                                                              ////
1126 
////  Author(s):                                                  ////
1127 
////      - Michael Unneback, unneback@opencores.org              ////
1128 
////        ORSoC AB                                              ////
1129 
////                                                              ////
1130 
//////////////////////////////////////////////////////////////////////
1131 
////                                                              ////
1132 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1133 
////                                                              ////
1134 
//// This source file may be used and distributed without         ////
1135 
//// restriction provided that this copyright statement is not    ////
1136 
//// removed from the file and that any derivative work contains  ////
1137 
//// the original copyright notice and the associated disclaimer. ////
1138 
////                                                              ////
1139 
//// This source file is free software; you can redistribute it   ////
1140 
//// and/or modify it under the terms of the GNU Lesser General   ////
1141 
//// Public License as published by the Free Software Foundation; ////
1142 
//// either version 2.1 of the License, or (at your option) any   ////
1143 
//// later version.                                               ////
1144 
////                                                              ////
1145 
//// This source is distributed in the hope that it will be       ////
1146 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1147 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1148 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1149 
//// details.                                                     ////
1150 
////                                                              ////
1151 
//// You should have received a copy of the GNU Lesser General    ////
1152 
//// Public License along with this source; if not, download it   ////
1153 
//// from http://www.opencores.org/lgpl.shtml                     ////
1154 
////                                                              ////
1155 
//////////////////////////////////////////////////////////////////////
1156 40 unneback 
`ifdef MUX_ANDOR
1157 
`define MODULE mux_andor
1158 
module `BASE`MODULE ( a, sel, dout);
1159 
`undef MODULE
1160 36 unneback 
 
1161 
parameter width = 32;
1162 
parameter nr_of_ports = 4;
1163 
 
1164 
input [nr_of_ports*width-1:0] a;
1165 
input [nr_of_ports-1:0] sel;
1166 
output reg [width-1:0] dout;
1167 
 
1168 38 unneback 
integer i,j;
1169 
 
1170 36 unneback 
always @ (a, sel)
1171 
begin
1172 
    dout = a[width-1:0] & {width{sel[0]}};
1173 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1174 
        for (j=0;j<width;j=j+1)
1175 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1176 36 unneback 
end
1177 
 
1178 
endmodule
1179 40 unneback 
`endif
1180 36 unneback 
 
1181 40 unneback 
`ifdef MUX2_ANDOR
1182 
`define MODULE mux2_andor
1183 
module `BASE`MODULE ( a1, a0, sel, dout);
1184 
`undef MODULE
1185 18 unneback 
 
1186 34 unneback 
parameter width = 32;
1187 35 unneback 
localparam nr_of_ports = 2;
1188 34 unneback 
input [width-1:0] a1, a0;
1189 
input [nr_of_ports-1:0] sel;
1190 
output [width-1:0] dout;
1191 
 
1192 40 unneback 
`define MODULE mux_andor
1193 
`BASE`MODULE
1194 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1195 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1196 40 unneback 
`undef MODULE
1197 
 
1198 34 unneback 
endmodule
1199 40 unneback 
`endif
1200 34 unneback 
 
1201 40 unneback 
`ifdef MUX3_ANDOR
1202 
`define MODULE mux3_andor
1203 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1204 
`undef MODULE
1205 34 unneback 
 
1206 
parameter width = 32;
1207 35 unneback 
localparam nr_of_ports = 3;
1208 34 unneback 
input [width-1:0] a2, a1, a0;
1209 
input [nr_of_ports-1:0] sel;
1210 
output [width-1:0] dout;
1211 
 
1212 40 unneback 
`define MODULE mux_andor
1213 
`BASE`MODULE
1214 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1215 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1216 40 unneback 
`undef MODULE
1217 34 unneback 
endmodule
1218 40 unneback 
`endif
1219 34 unneback 
 
1220 40 unneback 
`ifdef MUX4_ANDOR
1221 
`define MODULE mux4_andor
1222 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1223 
`undef MODULE
1224 18 unneback 
 
1225 
parameter width = 32;
1226 35 unneback 
localparam nr_of_ports = 4;
1227 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1228 
input [nr_of_ports-1:0] sel;
1229 22 unneback 
output [width-1:0] dout;
1230 18 unneback 
 
1231 40 unneback 
`define MODULE mux_andor
1232 
`BASE`MODULE
1233 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1234 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1235 40 unneback 
`undef MODULE
1236 18 unneback 
 
1237 
endmodule
1238 40 unneback 
`endif
1239 18 unneback 
 
1240 40 unneback 
`ifdef MUX5_ANDOR
1241 
`define MODULE mux5_andor
1242 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1243 
`undef MODULE
1244 18 unneback 
 
1245 
parameter width = 32;
1246 35 unneback 
localparam nr_of_ports = 5;
1247 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1248 
input [nr_of_ports-1:0] sel;
1249 22 unneback 
output [width-1:0] dout;
1250 18 unneback 
 
1251 40 unneback 
`define MODULE mux_andor
1252 
`BASE`MODULE
1253 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1254 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1255 40 unneback 
`undef MODULE
1256 18 unneback 
 
1257 
endmodule
1258 40 unneback 
`endif
1259 18 unneback 
 
1260 40 unneback 
`ifdef MUX6_ANDOR
1261 
`define MODULE mux6_andor
1262 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1263 
`undef MODULE
1264 18 unneback 
 
1265 
parameter width = 32;
1266 35 unneback 
localparam nr_of_ports = 6;
1267 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1268 
input [nr_of_ports-1:0] sel;
1269 22 unneback 
output [width-1:0] dout;
1270 18 unneback 
 
1271 40 unneback 
`define MODULE mux_andor
1272 
`BASE`MODULE
1273 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1274 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1275 40 unneback 
`undef MODULE
1276 18 unneback 
 
1277 
endmodule
1278 40 unneback 
`endif
1279 43 unneback 
 
1280 
`ifdef PARITY
1281 
 
1282 
`define MODULE parity_generate
1283 
module `BASE`MODULE (data, parity);
1284 
`undef MODULE
1285 
parameter word_size = 32;
1286 
parameter chunk_size = 8;
1287 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1288 
input [word_size-1:0] data;
1289 
output reg [word_size/chunk_size-1:0] parity;
1290 
integer i,j;
1291 
always @ (data)
1292 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1293 
    parity[i] = parity_type;
1294 
    for (j=0;j<chunk_size;j=j+1) begin
1295 
        parity[i] = data[i+j] ^ parity[i];
1296 
    end
1297 
end
1298 
endmodule
1299 
 
1300 
`define MODULE parity_check
1301 
module `BASE`MODULE( data, parity, parity_error);
1302 
`undef MODULE
1303 
parameter word_size = 32;
1304 
parameter chunk_size = 8;
1305 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1306 
input [word_size-1:0] data;
1307 
input [word_size/chunk_size-1:0] parity;
1308 
output parity_error;
1309 
reg [chunk_size-1:0] error_flag;
1310 
integer i,j;
1311 
always @ (data or parity)
1312 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1313 
    error_flag[i] = parity[i] ^ parity_type;
1314 
    for (j=0;j<chunk_size;j=j+1) begin
1315 
        error_flag[i] = data[i+j] ^ error_flag[i];
1316 
    end
1317 
end
1318 
assign parity_error = |error_flag;
1319 
endmodule
1320 
 
1321 
`endif`ifdef CNT_BIN
1322 18 unneback 
//////////////////////////////////////////////////////////////////////
1323 
////                                                              ////
1324 6 unneback 
////  Versatile counter                                           ////
1325 
////                                                              ////
1326 
////  Description                                                 ////
1327 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1328 
////  counter                                                     ////
1329 
////                                                              ////
1330 
////  To Do:                                                      ////
1331 
////   - add LFSR with more taps                                  ////
1332 
////                                                              ////
1333 
////  Author(s):                                                  ////
1334 
////      - Michael Unneback, unneback@opencores.org              ////
1335 
////        ORSoC AB                                              ////
1336 
////                                                              ////
1337 
//////////////////////////////////////////////////////////////////////
1338 
////                                                              ////
1339 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1340 
////                                                              ////
1341 
//// This source file may be used and distributed without         ////
1342 
//// restriction provided that this copyright statement is not    ////
1343 
//// removed from the file and that any derivative work contains  ////
1344 
//// the original copyright notice and the associated disclaimer. ////
1345 
////                                                              ////
1346 
//// This source file is free software; you can redistribute it   ////
1347 
//// and/or modify it under the terms of the GNU Lesser General   ////
1348 
//// Public License as published by the Free Software Foundation; ////
1349 
//// either version 2.1 of the License, or (at your option) any   ////
1350 
//// later version.                                               ////
1351 
////                                                              ////
1352 
//// This source is distributed in the hope that it will be       ////
1353 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1354 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1355 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1356 
//// details.                                                     ////
1357 
////                                                              ////
1358 
//// You should have received a copy of the GNU Lesser General    ////
1359 
//// Public License along with this source; if not, download it   ////
1360 
//// from http://www.opencores.org/lgpl.shtml                     ////
1361 
////                                                              ////
1362 
//////////////////////////////////////////////////////////////////////
1363 
 
1364 
// binary counter
1365 22 unneback 
 
1366 40 unneback 
`define MODULE cnt_bin
1367 
module `BASE`MODULE (
1368 
`undef MODULE
1369 
 q, rst, clk);
1370 
 
1371 22 unneback 
   parameter length = 4;
1372 
   output [length:1] q;
1373 
   input rst;
1374 
   input clk;
1375 
 
1376 
   parameter clear_value = 0;
1377 
   parameter set_value = 1;
1378 
   parameter wrap_value = 0;
1379 
   parameter level1_value = 15;
1380 
 
1381 
   reg  [length:1] qi;
1382 
   wire [length:1] q_next;
1383 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1384 
 
1385 
   always @ (posedge clk or posedge rst)
1386 
     if (rst)
1387 
       qi <= {length{1'b0}};
1388 
     else
1389 
       qi <= q_next;
1390 
 
1391 
   assign q = qi;
1392 
 
1393 
endmodule
1394 40 unneback 
`endif
1395 
`ifdef CNT_BIN_CLEAR
1396 22 unneback 
//////////////////////////////////////////////////////////////////////
1397 
////                                                              ////
1398 
////  Versatile counter                                           ////
1399 
////                                                              ////
1400 
////  Description                                                 ////
1401 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1402 
////  counter                                                     ////
1403 
////                                                              ////
1404 
////  To Do:                                                      ////
1405 
////   - add LFSR with more taps                                  ////
1406 
////                                                              ////
1407 
////  Author(s):                                                  ////
1408 
////      - Michael Unneback, unneback@opencores.org              ////
1409 
////        ORSoC AB                                              ////
1410 
////                                                              ////
1411 
//////////////////////////////////////////////////////////////////////
1412 
////                                                              ////
1413 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1414 
////                                                              ////
1415 
//// This source file may be used and distributed without         ////
1416 
//// restriction provided that this copyright statement is not    ////
1417 
//// removed from the file and that any derivative work contains  ////
1418 
//// the original copyright notice and the associated disclaimer. ////
1419 
////                                                              ////
1420 
//// This source file is free software; you can redistribute it   ////
1421 
//// and/or modify it under the terms of the GNU Lesser General   ////
1422 
//// Public License as published by the Free Software Foundation; ////
1423 
//// either version 2.1 of the License, or (at your option) any   ////
1424 
//// later version.                                               ////
1425 
////                                                              ////
1426 
//// This source is distributed in the hope that it will be       ////
1427 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1428 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1429 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1430 
//// details.                                                     ////
1431 
////                                                              ////
1432 
//// You should have received a copy of the GNU Lesser General    ////
1433 
//// Public License along with this source; if not, download it   ////
1434 
//// from http://www.opencores.org/lgpl.shtml                     ////
1435 
////                                                              ////
1436 
//////////////////////////////////////////////////////////////////////
1437 
 
1438 
// binary counter
1439 
 
1440 40 unneback 
`define MODULE cnt_bin_clear
1441 
module `BASE`MODULE (
1442 
`undef MODULE
1443 
 clear, q, rst, clk);
1444 
 
1445 22 unneback 
   parameter length = 4;
1446 
   input clear;
1447 
   output [length:1] q;
1448 
   input rst;
1449 
   input clk;
1450 
 
1451 
   parameter clear_value = 0;
1452 
   parameter set_value = 1;
1453 
   parameter wrap_value = 0;
1454 
   parameter level1_value = 15;
1455 
 
1456 
   reg  [length:1] qi;
1457 
   wire [length:1] q_next;
1458 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1459 
 
1460 
   always @ (posedge clk or posedge rst)
1461 
     if (rst)
1462 
       qi <= {length{1'b0}};
1463 
     else
1464 
       qi <= q_next;
1465 
 
1466 
   assign q = qi;
1467 
 
1468 
endmodule
1469 40 unneback 
`endif
1470 
`ifdef CNT_BIN_CE
1471 22 unneback 
//////////////////////////////////////////////////////////////////////
1472 
////                                                              ////
1473 
////  Versatile counter                                           ////
1474 
////                                                              ////
1475 
////  Description                                                 ////
1476 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1477 
////  counter                                                     ////
1478 
////                                                              ////
1479 
////  To Do:                                                      ////
1480 
////   - add LFSR with more taps                                  ////
1481 
////                                                              ////
1482 
////  Author(s):                                                  ////
1483 
////      - Michael Unneback, unneback@opencores.org              ////
1484 
////        ORSoC AB                                              ////
1485 
////                                                              ////
1486 
//////////////////////////////////////////////////////////////////////
1487 
////                                                              ////
1488 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1489 
////                                                              ////
1490 
//// This source file may be used and distributed without         ////
1491 
//// restriction provided that this copyright statement is not    ////
1492 
//// removed from the file and that any derivative work contains  ////
1493 
//// the original copyright notice and the associated disclaimer. ////
1494 
////                                                              ////
1495 
//// This source file is free software; you can redistribute it   ////
1496 
//// and/or modify it under the terms of the GNU Lesser General   ////
1497 
//// Public License as published by the Free Software Foundation; ////
1498 
//// either version 2.1 of the License, or (at your option) any   ////
1499 
//// later version.                                               ////
1500 
////                                                              ////
1501 
//// This source is distributed in the hope that it will be       ////
1502 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1503 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1504 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1505 
//// details.                                                     ////
1506 
////                                                              ////
1507 
//// You should have received a copy of the GNU Lesser General    ////
1508 
//// Public License along with this source; if not, download it   ////
1509 
//// from http://www.opencores.org/lgpl.shtml                     ////
1510 
////                                                              ////
1511 
//////////////////////////////////////////////////////////////////////
1512 
 
1513 
// binary counter
1514 6 unneback 
 
1515 40 unneback 
`define MODULE cnt_bin_ce
1516 
module `BASE`MODULE (
1517 
`undef MODULE
1518 
 cke, q, rst, clk);
1519 
 
1520 6 unneback 
   parameter length = 4;
1521 
   input cke;
1522 
   output [length:1] q;
1523 
   input rst;
1524 
   input clk;
1525 
 
1526 
   parameter clear_value = 0;
1527 
   parameter set_value = 1;
1528 
   parameter wrap_value = 0;
1529 
   parameter level1_value = 15;
1530 
 
1531 
   reg  [length:1] qi;
1532 
   wire [length:1] q_next;
1533 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1534 
 
1535 
   always @ (posedge clk or posedge rst)
1536 
     if (rst)
1537 
       qi <= {length{1'b0}};
1538 
     else
1539 
     if (cke)
1540 
       qi <= q_next;
1541 
 
1542 
   assign q = qi;
1543 
 
1544 
endmodule
1545 40 unneback 
`endif
1546 
`ifdef CNT_BIN_CE_CLEAR
1547 6 unneback 
//////////////////////////////////////////////////////////////////////
1548 
////                                                              ////
1549 
////  Versatile counter                                           ////
1550 
////                                                              ////
1551 
////  Description                                                 ////
1552 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1553 
////  counter                                                     ////
1554 
////                                                              ////
1555 
////  To Do:                                                      ////
1556 
////   - add LFSR with more taps                                  ////
1557 
////                                                              ////
1558 
////  Author(s):                                                  ////
1559 
////      - Michael Unneback, unneback@opencores.org              ////
1560 
////        ORSoC AB                                              ////
1561 
////                                                              ////
1562 
//////////////////////////////////////////////////////////////////////
1563 
////                                                              ////
1564 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1565 
////                                                              ////
1566 
//// This source file may be used and distributed without         ////
1567 
//// restriction provided that this copyright statement is not    ////
1568 
//// removed from the file and that any derivative work contains  ////
1569 
//// the original copyright notice and the associated disclaimer. ////
1570 
////                                                              ////
1571 
//// This source file is free software; you can redistribute it   ////
1572 
//// and/or modify it under the terms of the GNU Lesser General   ////
1573 
//// Public License as published by the Free Software Foundation; ////
1574 
//// either version 2.1 of the License, or (at your option) any   ////
1575 
//// later version.                                               ////
1576 
////                                                              ////
1577 
//// This source is distributed in the hope that it will be       ////
1578 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1579 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1580 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1581 
//// details.                                                     ////
1582 
////                                                              ////
1583 
//// You should have received a copy of the GNU Lesser General    ////
1584 
//// Public License along with this source; if not, download it   ////
1585 
//// from http://www.opencores.org/lgpl.shtml                     ////
1586 
////                                                              ////
1587 
//////////////////////////////////////////////////////////////////////
1588 
 
1589 
// binary counter
1590 
 
1591 40 unneback 
`define MODULE cnt_bin_ce_clear
1592 
module `BASE`MODULE (
1593 
`undef MODULE
1594 
 clear, cke, q, rst, clk);
1595 
 
1596 6 unneback 
   parameter length = 4;
1597 
   input clear;
1598 
   input cke;
1599 
   output [length:1] q;
1600 
   input rst;
1601 
   input clk;
1602 
 
1603 
   parameter clear_value = 0;
1604 
   parameter set_value = 1;
1605 
   parameter wrap_value = 0;
1606 
   parameter level1_value = 15;
1607 
 
1608 
   reg  [length:1] qi;
1609 
   wire [length:1] q_next;
1610 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1611 
 
1612 
   always @ (posedge clk or posedge rst)
1613 
     if (rst)
1614 
       qi <= {length{1'b0}};
1615 
     else
1616 
     if (cke)
1617 
       qi <= q_next;
1618 
 
1619 
   assign q = qi;
1620 
 
1621 
endmodule
1622 40 unneback 
`endif
1623 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1624 6 unneback 
//////////////////////////////////////////////////////////////////////
1625 
////                                                              ////
1626 
////  Versatile counter                                           ////
1627 
////                                                              ////
1628 
////  Description                                                 ////
1629 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1630 
////  counter                                                     ////
1631 
////                                                              ////
1632 
////  To Do:                                                      ////
1633 
////   - add LFSR with more taps                                  ////
1634 
////                                                              ////
1635 
////  Author(s):                                                  ////
1636 
////      - Michael Unneback, unneback@opencores.org              ////
1637 
////        ORSoC AB                                              ////
1638 
////                                                              ////
1639 
//////////////////////////////////////////////////////////////////////
1640 
////                                                              ////
1641 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1642 
////                                                              ////
1643 
//// This source file may be used and distributed without         ////
1644 
//// restriction provided that this copyright statement is not    ////
1645 
//// removed from the file and that any derivative work contains  ////
1646 
//// the original copyright notice and the associated disclaimer. ////
1647 
////                                                              ////
1648 
//// This source file is free software; you can redistribute it   ////
1649 
//// and/or modify it under the terms of the GNU Lesser General   ////
1650 
//// Public License as published by the Free Software Foundation; ////
1651 
//// either version 2.1 of the License, or (at your option) any   ////
1652 
//// later version.                                               ////
1653 
////                                                              ////
1654 
//// This source is distributed in the hope that it will be       ////
1655 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1656 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1657 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1658 
//// details.                                                     ////
1659 
////                                                              ////
1660 
//// You should have received a copy of the GNU Lesser General    ////
1661 
//// Public License along with this source; if not, download it   ////
1662 
//// from http://www.opencores.org/lgpl.shtml                     ////
1663 
////                                                              ////
1664 
//////////////////////////////////////////////////////////////////////
1665 
 
1666 
// binary counter
1667 29 unneback 
 
1668 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1669 
module `BASE`MODULE (
1670 
`undef MODULE
1671 
 clear, cke, q, level1, level2, rst, clk);
1672 
 
1673 29 unneback 
   parameter length = 4;
1674 
   input clear;
1675 
   input cke;
1676 
   output [length:1] q;
1677 
   output reg level1;
1678 
   output reg level2;
1679 
   input rst;
1680 
   input clk;
1681 
 
1682 
   parameter clear_value = 0;
1683 
   parameter set_value = 1;
1684 30 unneback 
   parameter wrap_value = 15;
1685 
   parameter level1_value = 8;
1686 
   parameter level2_value = 15;
1687 29 unneback 
 
1688 
   wire rew;
1689 30 unneback 
   assign rew = 1'b0;
1690 29 unneback 
   reg  [length:1] qi;
1691 
   wire [length:1] q_next;
1692 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1693 
 
1694 
   always @ (posedge clk or posedge rst)
1695 
     if (rst)
1696 
       qi <= {length{1'b0}};
1697 
     else
1698 
     if (cke)
1699 
       qi <= q_next;
1700 
 
1701 
   assign q = qi;
1702 
 
1703 
 
1704 
    always @ (posedge clk or posedge rst)
1705 
    if (rst)
1706 
        level1 <= 1'b0;
1707 
    else
1708 
    if (cke)
1709 
    if (clear)
1710 
        level1 <= 1'b0;
1711 
    else if (q_next == level1_value)
1712 
        level1 <= 1'b1;
1713 
    else if (qi == level1_value & rew)
1714 
        level1 <= 1'b0;
1715 
 
1716 
    always @ (posedge clk or posedge rst)
1717 
    if (rst)
1718 
        level2 <= 1'b0;
1719 
    else
1720 
    if (cke)
1721 
    if (clear)
1722 
        level2 <= 1'b0;
1723 
    else if (q_next == level2_value)
1724 
        level2 <= 1'b1;
1725 
    else if (qi == level2_value & rew)
1726 
        level2 <= 1'b0;
1727 
endmodule
1728 40 unneback 
`endif
1729 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1730 29 unneback 
//////////////////////////////////////////////////////////////////////
1731 
////                                                              ////
1732 
////  Versatile counter                                           ////
1733 
////                                                              ////
1734 
////  Description                                                 ////
1735 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1736 
////  counter                                                     ////
1737 
////                                                              ////
1738 
////  To Do:                                                      ////
1739 
////   - add LFSR with more taps                                  ////
1740 
////                                                              ////
1741 
////  Author(s):                                                  ////
1742 
////      - Michael Unneback, unneback@opencores.org              ////
1743 
////        ORSoC AB                                              ////
1744 
////                                                              ////
1745 
//////////////////////////////////////////////////////////////////////
1746 
////                                                              ////
1747 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1748 
////                                                              ////
1749 
//// This source file may be used and distributed without         ////
1750 
//// restriction provided that this copyright statement is not    ////
1751 
//// removed from the file and that any derivative work contains  ////
1752 
//// the original copyright notice and the associated disclaimer. ////
1753 
////                                                              ////
1754 
//// This source file is free software; you can redistribute it   ////
1755 
//// and/or modify it under the terms of the GNU Lesser General   ////
1756 
//// Public License as published by the Free Software Foundation; ////
1757 
//// either version 2.1 of the License, or (at your option) any   ////
1758 
//// later version.                                               ////
1759 
////                                                              ////
1760 
//// This source is distributed in the hope that it will be       ////
1761 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1762 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1763 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1764 
//// details.                                                     ////
1765 
////                                                              ////
1766 
//// You should have received a copy of the GNU Lesser General    ////
1767 
//// Public License along with this source; if not, download it   ////
1768 
//// from http://www.opencores.org/lgpl.shtml                     ////
1769 
////                                                              ////
1770 
//////////////////////////////////////////////////////////////////////
1771 
 
1772 
// binary counter
1773 6 unneback 
 
1774 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
1775 
module `BASE`MODULE (
1776 
`undef MODULE
1777 
 clear, set, cke, rew, q, rst, clk);
1778 
 
1779 6 unneback 
   parameter length = 4;
1780 
   input clear;
1781 
   input set;
1782 
   input cke;
1783 
   input rew;
1784 
   output [length:1] q;
1785 
   input rst;
1786 
   input clk;
1787 
 
1788 
   parameter clear_value = 0;
1789 
   parameter set_value = 1;
1790 
   parameter wrap_value = 0;
1791 
   parameter level1_value = 15;
1792 
 
1793 
   reg  [length:1] qi;
1794 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1795 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1796 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1797 
   assign q_next = rew ? q_next_rew : q_next_fw;
1798 
 
1799 
   always @ (posedge clk or posedge rst)
1800 
     if (rst)
1801 
       qi <= {length{1'b0}};
1802 
     else
1803 
     if (cke)
1804 
       qi <= q_next;
1805 
 
1806 
   assign q = qi;
1807 
 
1808 
endmodule
1809 40 unneback 
`endif
1810 
`ifdef CNT_BIN_CE_REW_L1
1811 6 unneback 
//////////////////////////////////////////////////////////////////////
1812 
////                                                              ////
1813 
////  Versatile counter                                           ////
1814 
////                                                              ////
1815 
////  Description                                                 ////
1816 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1817 
////  counter                                                     ////
1818 
////                                                              ////
1819 
////  To Do:                                                      ////
1820 
////   - add LFSR with more taps                                  ////
1821 
////                                                              ////
1822 
////  Author(s):                                                  ////
1823 
////      - Michael Unneback, unneback@opencores.org              ////
1824 
////        ORSoC AB                                              ////
1825 
////                                                              ////
1826 
//////////////////////////////////////////////////////////////////////
1827 
////                                                              ////
1828 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1829 
////                                                              ////
1830 
//// This source file may be used and distributed without         ////
1831 
//// restriction provided that this copyright statement is not    ////
1832 
//// removed from the file and that any derivative work contains  ////
1833 
//// the original copyright notice and the associated disclaimer. ////
1834 
////                                                              ////
1835 
//// This source file is free software; you can redistribute it   ////
1836 
//// and/or modify it under the terms of the GNU Lesser General   ////
1837 
//// Public License as published by the Free Software Foundation; ////
1838 
//// either version 2.1 of the License, or (at your option) any   ////
1839 
//// later version.                                               ////
1840 
////                                                              ////
1841 
//// This source is distributed in the hope that it will be       ////
1842 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1843 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1844 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1845 
//// details.                                                     ////
1846 
////                                                              ////
1847 
//// You should have received a copy of the GNU Lesser General    ////
1848 
//// Public License along with this source; if not, download it   ////
1849 
//// from http://www.opencores.org/lgpl.shtml                     ////
1850 
////                                                              ////
1851 
//////////////////////////////////////////////////////////////////////
1852 
 
1853 
// binary counter
1854 
 
1855 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
1856 
module `BASE`MODULE (
1857 
`undef MODULE
1858 
 cke, rew, level1, rst, clk);
1859 
 
1860 6 unneback 
   parameter length = 4;
1861 
   input cke;
1862 
   input rew;
1863 
   output reg level1;
1864 
   input rst;
1865 
   input clk;
1866 
 
1867 
   parameter clear_value = 0;
1868 
   parameter set_value = 1;
1869 
   parameter wrap_value = 1;
1870 
   parameter level1_value = 15;
1871 
 
1872 29 unneback 
   wire clear;
1873 30 unneback 
   assign clear = 1'b0;
1874 6 unneback 
   reg  [length:1] qi;
1875 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1876 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1877 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1878 
   assign q_next = rew ? q_next_rew : q_next_fw;
1879 
 
1880 
   always @ (posedge clk or posedge rst)
1881 
     if (rst)
1882 
       qi <= {length{1'b0}};
1883 
     else
1884 
     if (cke)
1885 
       qi <= q_next;
1886 
 
1887 
 
1888 
 
1889 
    always @ (posedge clk or posedge rst)
1890 
    if (rst)
1891 
        level1 <= 1'b0;
1892 
    else
1893 
    if (cke)
1894 29 unneback 
    if (clear)
1895 
        level1 <= 1'b0;
1896 
    else if (q_next == level1_value)
1897 6 unneback 
        level1 <= 1'b1;
1898 
    else if (qi == level1_value & rew)
1899 
        level1 <= 1'b0;
1900 
endmodule
1901 40 unneback 
`endif
1902 
`ifdef CNT_BIN_CE_REW_ZQ_L1
1903 6 unneback 
//////////////////////////////////////////////////////////////////////
1904 
////                                                              ////
1905 
////  Versatile counter                                           ////
1906 
////                                                              ////
1907 
////  Description                                                 ////
1908 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1909 
////  counter                                                     ////
1910 
////                                                              ////
1911 
////  To Do:                                                      ////
1912 
////   - add LFSR with more taps                                  ////
1913 
////                                                              ////
1914 
////  Author(s):                                                  ////
1915 
////      - Michael Unneback, unneback@opencores.org              ////
1916 
////        ORSoC AB                                              ////
1917 
////                                                              ////
1918 
//////////////////////////////////////////////////////////////////////
1919 
////                                                              ////
1920 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1921 
////                                                              ////
1922 
//// This source file may be used and distributed without         ////
1923 
//// restriction provided that this copyright statement is not    ////
1924 
//// removed from the file and that any derivative work contains  ////
1925 
//// the original copyright notice and the associated disclaimer. ////
1926 
////                                                              ////
1927 
//// This source file is free software; you can redistribute it   ////
1928 
//// and/or modify it under the terms of the GNU Lesser General   ////
1929 
//// Public License as published by the Free Software Foundation; ////
1930 
//// either version 2.1 of the License, or (at your option) any   ////
1931 
//// later version.                                               ////
1932 
////                                                              ////
1933 
//// This source is distributed in the hope that it will be       ////
1934 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1935 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1936 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1937 
//// details.                                                     ////
1938 
////                                                              ////
1939 
//// You should have received a copy of the GNU Lesser General    ////
1940 
//// Public License along with this source; if not, download it   ////
1941 
//// from http://www.opencores.org/lgpl.shtml                     ////
1942 
////                                                              ////
1943 
//////////////////////////////////////////////////////////////////////
1944 
 
1945 25 unneback 
// binary counter
1946 
 
1947 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
1948 
module `BASE`MODULE (
1949 
`undef MODULE
1950 
 cke, rew, zq, level1, rst, clk);
1951 
 
1952 25 unneback 
   parameter length = 4;
1953 
   input cke;
1954 
   input rew;
1955 
   output reg zq;
1956 
   output reg level1;
1957 
   input rst;
1958 
   input clk;
1959 
 
1960 
   parameter clear_value = 0;
1961 
   parameter set_value = 1;
1962 
   parameter wrap_value = 1;
1963 
   parameter level1_value = 15;
1964 
 
1965 29 unneback 
   wire clear;
1966 30 unneback 
   assign clear = 1'b0;
1967 25 unneback 
   reg  [length:1] qi;
1968 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1969 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1970 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1971 
   assign q_next = rew ? q_next_rew : q_next_fw;
1972 
 
1973 
   always @ (posedge clk or posedge rst)
1974 
     if (rst)
1975 
       qi <= {length{1'b0}};
1976 
     else
1977 
     if (cke)
1978 
       qi <= q_next;
1979 
 
1980 
 
1981 
 
1982 
   always @ (posedge clk or posedge rst)
1983 
     if (rst)
1984 
       zq <= 1'b1;
1985 
     else
1986 
     if (cke)
1987 
       zq <= q_next == {length{1'b0}};
1988 
 
1989 
    always @ (posedge clk or posedge rst)
1990 
    if (rst)
1991 
        level1 <= 1'b0;
1992 
    else
1993 
    if (cke)
1994 29 unneback 
    if (clear)
1995 
        level1 <= 1'b0;
1996 
    else if (q_next == level1_value)
1997 25 unneback 
        level1 <= 1'b1;
1998 
    else if (qi == level1_value & rew)
1999 
        level1 <= 1'b0;
2000 
endmodule
2001 40 unneback 
`endif
2002 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2003 25 unneback 
//////////////////////////////////////////////////////////////////////
2004 
////                                                              ////
2005 
////  Versatile counter                                           ////
2006 
////                                                              ////
2007 
////  Description                                                 ////
2008 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2009 
////  counter                                                     ////
2010 
////                                                              ////
2011 
////  To Do:                                                      ////
2012 
////   - add LFSR with more taps                                  ////
2013 
////                                                              ////
2014 
////  Author(s):                                                  ////
2015 
////      - Michael Unneback, unneback@opencores.org              ////
2016 
////        ORSoC AB                                              ////
2017 
////                                                              ////
2018 
//////////////////////////////////////////////////////////////////////
2019 
////                                                              ////
2020 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2021 
////                                                              ////
2022 
//// This source file may be used and distributed without         ////
2023 
//// restriction provided that this copyright statement is not    ////
2024 
//// removed from the file and that any derivative work contains  ////
2025 
//// the original copyright notice and the associated disclaimer. ////
2026 
////                                                              ////
2027 
//// This source file is free software; you can redistribute it   ////
2028 
//// and/or modify it under the terms of the GNU Lesser General   ////
2029 
//// Public License as published by the Free Software Foundation; ////
2030 
//// either version 2.1 of the License, or (at your option) any   ////
2031 
//// later version.                                               ////
2032 
////                                                              ////
2033 
//// This source is distributed in the hope that it will be       ////
2034 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2035 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2036 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2037 
//// details.                                                     ////
2038 
////                                                              ////
2039 
//// You should have received a copy of the GNU Lesser General    ////
2040 
//// Public License along with this source; if not, download it   ////
2041 
//// from http://www.opencores.org/lgpl.shtml                     ////
2042 
////                                                              ////
2043 
//////////////////////////////////////////////////////////////////////
2044 
 
2045 
// binary counter
2046 
 
2047 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2048 
module `BASE`MODULE (
2049 
`undef MODULE
2050 
 cke, rew, q, zq, level1, rst, clk);
2051 
 
2052 25 unneback 
   parameter length = 4;
2053 
   input cke;
2054 
   input rew;
2055 
   output [length:1] q;
2056 
   output reg zq;
2057 
   output reg level1;
2058 
   input rst;
2059 
   input clk;
2060 
 
2061 
   parameter clear_value = 0;
2062 
   parameter set_value = 1;
2063 
   parameter wrap_value = 1;
2064 
   parameter level1_value = 15;
2065 
 
2066 29 unneback 
   wire clear;
2067 30 unneback 
   assign clear = 1'b0;
2068 25 unneback 
   reg  [length:1] qi;
2069 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2070 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2071 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2072 
   assign q_next = rew ? q_next_rew : q_next_fw;
2073 
 
2074 
   always @ (posedge clk or posedge rst)
2075 
     if (rst)
2076 
       qi <= {length{1'b0}};
2077 
     else
2078 
     if (cke)
2079 
       qi <= q_next;
2080 
 
2081 
   assign q = qi;
2082 
 
2083 
 
2084 
   always @ (posedge clk or posedge rst)
2085 
     if (rst)
2086 
       zq <= 1'b1;
2087 
     else
2088 
     if (cke)
2089 
       zq <= q_next == {length{1'b0}};
2090 
 
2091 
    always @ (posedge clk or posedge rst)
2092 
    if (rst)
2093 
        level1 <= 1'b0;
2094 
    else
2095 
    if (cke)
2096 29 unneback 
    if (clear)
2097 
        level1 <= 1'b0;
2098 
    else if (q_next == level1_value)
2099 25 unneback 
        level1 <= 1'b1;
2100 
    else if (qi == level1_value & rew)
2101 
        level1 <= 1'b0;
2102 
endmodule
2103 40 unneback 
`endif
2104 
`ifdef CNT_LFSR_ZQ
2105 25 unneback 
//////////////////////////////////////////////////////////////////////
2106 
////                                                              ////
2107 
////  Versatile counter                                           ////
2108 
////                                                              ////
2109 
////  Description                                                 ////
2110 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2111 
////  counter                                                     ////
2112 
////                                                              ////
2113 
////  To Do:                                                      ////
2114 
////   - add LFSR with more taps                                  ////
2115 
////                                                              ////
2116 
////  Author(s):                                                  ////
2117 
////      - Michael Unneback, unneback@opencores.org              ////
2118 
////        ORSoC AB                                              ////
2119 
////                                                              ////
2120 
//////////////////////////////////////////////////////////////////////
2121 
////                                                              ////
2122 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2123 
////                                                              ////
2124 
//// This source file may be used and distributed without         ////
2125 
//// restriction provided that this copyright statement is not    ////
2126 
//// removed from the file and that any derivative work contains  ////
2127 
//// the original copyright notice and the associated disclaimer. ////
2128 
////                                                              ////
2129 
//// This source file is free software; you can redistribute it   ////
2130 
//// and/or modify it under the terms of the GNU Lesser General   ////
2131 
//// Public License as published by the Free Software Foundation; ////
2132 
//// either version 2.1 of the License, or (at your option) any   ////
2133 
//// later version.                                               ////
2134 
////                                                              ////
2135 
//// This source is distributed in the hope that it will be       ////
2136 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2137 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2138 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2139 
//// details.                                                     ////
2140 
////                                                              ////
2141 
//// You should have received a copy of the GNU Lesser General    ////
2142 
//// Public License along with this source; if not, download it   ////
2143 
//// from http://www.opencores.org/lgpl.shtml                     ////
2144 
////                                                              ////
2145 
//////////////////////////////////////////////////////////////////////
2146 
 
2147 6 unneback 
// LFSR counter
2148 
 
2149 40 unneback 
`define MODULE cnt_lfsr_zq
2150 
module `BASE`MODULE (
2151 
`undef MODULE
2152 
 zq, rst, clk);
2153 
 
2154 6 unneback 
   parameter length = 4;
2155 
   output reg zq;
2156 
   input rst;
2157 
   input clk;
2158 
 
2159 
   parameter clear_value = 0;
2160 
   parameter set_value = 1;
2161 
   parameter wrap_value = 8;
2162 
   parameter level1_value = 15;
2163 
 
2164 
   reg  [length:1] qi;
2165 
   reg lfsr_fb;
2166 
   wire [length:1] q_next;
2167 
   reg [32:1] polynom;
2168 
   integer i;
2169 
 
2170 
   always @ (qi)
2171 
   begin
2172 
        case (length)
2173 
         2: polynom = 32'b11;                               // 0x3
2174 
         3: polynom = 32'b110;                              // 0x6
2175 
         4: polynom = 32'b1100;                             // 0xC
2176 
         5: polynom = 32'b10100;                            // 0x14
2177 
         6: polynom = 32'b110000;                           // 0x30
2178 
         7: polynom = 32'b1100000;                          // 0x60
2179 
         8: polynom = 32'b10111000;                         // 0xb8
2180 
         9: polynom = 32'b100010000;                        // 0x110
2181 
        10: polynom = 32'b1001000000;                       // 0x240
2182 
        11: polynom = 32'b10100000000;                      // 0x500
2183 
        12: polynom = 32'b100000101001;                     // 0x829
2184 
        13: polynom = 32'b1000000001100;                    // 0x100C
2185 
        14: polynom = 32'b10000000010101;                   // 0x2015
2186 
        15: polynom = 32'b110000000000000;                  // 0x6000
2187 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2188 
        17: polynom = 32'b10010000000000000;                // 0x12000
2189 
        18: polynom = 32'b100000010000000000;               // 0x20400
2190 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2191 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2192 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2193 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2194 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2195 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2196 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2197 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2198 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2199 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2200 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2201 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2202 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2203 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2204 
        default: polynom = 32'b0;
2205 
        endcase
2206 
        lfsr_fb = qi[length];
2207 
        for (i=length-1; i>=1; i=i-1) begin
2208 
            if (polynom[i])
2209 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2210 
        end
2211 
    end
2212 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2213 
 
2214 
   always @ (posedge clk or posedge rst)
2215 
     if (rst)
2216 
       qi <= {length{1'b0}};
2217 
     else
2218 
       qi <= q_next;
2219 
 
2220 
 
2221 
 
2222 
   always @ (posedge clk or posedge rst)
2223 
     if (rst)
2224 
       zq <= 1'b1;
2225 
     else
2226 
       zq <= q_next == {length{1'b0}};
2227 
endmodule
2228 40 unneback 
`endif
2229 
`ifdef CNT_LFSR_CE_ZQ
2230 6 unneback 
//////////////////////////////////////////////////////////////////////
2231 
////                                                              ////
2232 
////  Versatile counter                                           ////
2233 
////                                                              ////
2234 
////  Description                                                 ////
2235 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2236 
////  counter                                                     ////
2237 
////                                                              ////
2238 
////  To Do:                                                      ////
2239 
////   - add LFSR with more taps                                  ////
2240 
////                                                              ////
2241 
////  Author(s):                                                  ////
2242 
////      - Michael Unneback, unneback@opencores.org              ////
2243 
////        ORSoC AB                                              ////
2244 
////                                                              ////
2245 
//////////////////////////////////////////////////////////////////////
2246 
////                                                              ////
2247 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2248 
////                                                              ////
2249 
//// This source file may be used and distributed without         ////
2250 
//// restriction provided that this copyright statement is not    ////
2251 
//// removed from the file and that any derivative work contains  ////
2252 
//// the original copyright notice and the associated disclaimer. ////
2253 
////                                                              ////
2254 
//// This source file is free software; you can redistribute it   ////
2255 
//// and/or modify it under the terms of the GNU Lesser General   ////
2256 
//// Public License as published by the Free Software Foundation; ////
2257 
//// either version 2.1 of the License, or (at your option) any   ////
2258 
//// later version.                                               ////
2259 
////                                                              ////
2260 
//// This source is distributed in the hope that it will be       ////
2261 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2262 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2263 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2264 
//// details.                                                     ////
2265 
////                                                              ////
2266 
//// You should have received a copy of the GNU Lesser General    ////
2267 
//// Public License along with this source; if not, download it   ////
2268 
//// from http://www.opencores.org/lgpl.shtml                     ////
2269 
////                                                              ////
2270 
//////////////////////////////////////////////////////////////////////
2271 
 
2272 
// LFSR counter
2273 
 
2274 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2275 
module `BASE`MODULE (
2276 
`undef MODULE
2277 
 cke, zq, rst, clk);
2278 
 
2279 6 unneback 
   parameter length = 4;
2280 
   input cke;
2281 
   output reg zq;
2282 
   input rst;
2283 
   input clk;
2284 
 
2285 
   parameter clear_value = 0;
2286 
   parameter set_value = 1;
2287 
   parameter wrap_value = 8;
2288 
   parameter level1_value = 15;
2289 
 
2290 
   reg  [length:1] qi;
2291 
   reg lfsr_fb;
2292 
   wire [length:1] q_next;
2293 
   reg [32:1] polynom;
2294 
   integer i;
2295 
 
2296 
   always @ (qi)
2297 
   begin
2298 
        case (length)
2299 
         2: polynom = 32'b11;                               // 0x3
2300 
         3: polynom = 32'b110;                              // 0x6
2301 
         4: polynom = 32'b1100;                             // 0xC
2302 
         5: polynom = 32'b10100;                            // 0x14
2303 
         6: polynom = 32'b110000;                           // 0x30
2304 
         7: polynom = 32'b1100000;                          // 0x60
2305 
         8: polynom = 32'b10111000;                         // 0xb8
2306 
         9: polynom = 32'b100010000;                        // 0x110
2307 
        10: polynom = 32'b1001000000;                       // 0x240
2308 
        11: polynom = 32'b10100000000;                      // 0x500
2309 
        12: polynom = 32'b100000101001;                     // 0x829
2310 
        13: polynom = 32'b1000000001100;                    // 0x100C
2311 
        14: polynom = 32'b10000000010101;                   // 0x2015
2312 
        15: polynom = 32'b110000000000000;                  // 0x6000
2313 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2314 
        17: polynom = 32'b10010000000000000;                // 0x12000
2315 
        18: polynom = 32'b100000010000000000;               // 0x20400
2316 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2317 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2318 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2319 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2320 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2321 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2322 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2323 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2324 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2325 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2326 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2327 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2328 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2329 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2330 
        default: polynom = 32'b0;
2331 
        endcase
2332 
        lfsr_fb = qi[length];
2333 
        for (i=length-1; i>=1; i=i-1) begin
2334 
            if (polynom[i])
2335 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2336 
        end
2337 
    end
2338 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2339 
 
2340 
   always @ (posedge clk or posedge rst)
2341 
     if (rst)
2342 
       qi <= {length{1'b0}};
2343 
     else
2344 
     if (cke)
2345 
       qi <= q_next;
2346 
 
2347 
 
2348 
 
2349 
   always @ (posedge clk or posedge rst)
2350 
     if (rst)
2351 
       zq <= 1'b1;
2352 
     else
2353 
     if (cke)
2354 
       zq <= q_next == {length{1'b0}};
2355 
endmodule
2356 40 unneback 
`endif
2357 
`ifdef CNT_LFSR_CE_Q
2358 6 unneback 
//////////////////////////////////////////////////////////////////////
2359 
////                                                              ////
2360 
////  Versatile counter                                           ////
2361 
////                                                              ////
2362 
////  Description                                                 ////
2363 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2364 
////  counter                                                     ////
2365 
////                                                              ////
2366 
////  To Do:                                                      ////
2367 
////   - add LFSR with more taps                                  ////
2368 
////                                                              ////
2369 
////  Author(s):                                                  ////
2370 
////      - Michael Unneback, unneback@opencores.org              ////
2371 
////        ORSoC AB                                              ////
2372 
////                                                              ////
2373 
//////////////////////////////////////////////////////////////////////
2374 
////                                                              ////
2375 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2376 
////                                                              ////
2377 
//// This source file may be used and distributed without         ////
2378 
//// restriction provided that this copyright statement is not    ////
2379 
//// removed from the file and that any derivative work contains  ////
2380 
//// the original copyright notice and the associated disclaimer. ////
2381 
////                                                              ////
2382 
//// This source file is free software; you can redistribute it   ////
2383 
//// and/or modify it under the terms of the GNU Lesser General   ////
2384 
//// Public License as published by the Free Software Foundation; ////
2385 
//// either version 2.1 of the License, or (at your option) any   ////
2386 
//// later version.                                               ////
2387 
////                                                              ////
2388 
//// This source is distributed in the hope that it will be       ////
2389 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2390 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2391 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2392 
//// details.                                                     ////
2393 
////                                                              ////
2394 
//// You should have received a copy of the GNU Lesser General    ////
2395 
//// Public License along with this source; if not, download it   ////
2396 
//// from http://www.opencores.org/lgpl.shtml                     ////
2397 
////                                                              ////
2398 
//////////////////////////////////////////////////////////////////////
2399 22 unneback 
 
2400 
// LFSR counter
2401 27 unneback 
 
2402 40 unneback 
`define MODULE cnt_lfsr_ce_q
2403 
module `BASE`MODULE (
2404 
`undef MODULE
2405 
 cke, q, rst, clk);
2406 
 
2407 27 unneback 
   parameter length = 4;
2408 
   input cke;
2409 
   output [length:1] q;
2410 
   input rst;
2411 
   input clk;
2412 
 
2413 
   parameter clear_value = 0;
2414 
   parameter set_value = 1;
2415 
   parameter wrap_value = 8;
2416 
   parameter level1_value = 15;
2417 
 
2418 
   reg  [length:1] qi;
2419 
   reg lfsr_fb;
2420 
   wire [length:1] q_next;
2421 
   reg [32:1] polynom;
2422 
   integer i;
2423 
 
2424 
   always @ (qi)
2425 
   begin
2426 
        case (length)
2427 
         2: polynom = 32'b11;                               // 0x3
2428 
         3: polynom = 32'b110;                              // 0x6
2429 
         4: polynom = 32'b1100;                             // 0xC
2430 
         5: polynom = 32'b10100;                            // 0x14
2431 
         6: polynom = 32'b110000;                           // 0x30
2432 
         7: polynom = 32'b1100000;                          // 0x60
2433 
         8: polynom = 32'b10111000;                         // 0xb8
2434 
         9: polynom = 32'b100010000;                        // 0x110
2435 
        10: polynom = 32'b1001000000;                       // 0x240
2436 
        11: polynom = 32'b10100000000;                      // 0x500
2437 
        12: polynom = 32'b100000101001;                     // 0x829
2438 
        13: polynom = 32'b1000000001100;                    // 0x100C
2439 
        14: polynom = 32'b10000000010101;                   // 0x2015
2440 
        15: polynom = 32'b110000000000000;                  // 0x6000
2441 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2442 
        17: polynom = 32'b10010000000000000;                // 0x12000
2443 
        18: polynom = 32'b100000010000000000;               // 0x20400
2444 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2445 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2446 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2447 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2448 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2449 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2450 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2451 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2452 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2453 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2454 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2455 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2456 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2457 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2458 
        default: polynom = 32'b0;
2459 
        endcase
2460 
        lfsr_fb = qi[length];
2461 
        for (i=length-1; i>=1; i=i-1) begin
2462 
            if (polynom[i])
2463 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2464 
        end
2465 
    end
2466 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2467 
 
2468 
   always @ (posedge clk or posedge rst)
2469 
     if (rst)
2470 
       qi <= {length{1'b0}};
2471 
     else
2472 
     if (cke)
2473 
       qi <= q_next;
2474 
 
2475 
   assign q = qi;
2476 
 
2477 
endmodule
2478 40 unneback 
`endif
2479 
`ifdef CNT_LFSR_CE_CLEAR_Q
2480 27 unneback 
//////////////////////////////////////////////////////////////////////
2481 
////                                                              ////
2482 
////  Versatile counter                                           ////
2483 
////                                                              ////
2484 
////  Description                                                 ////
2485 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2486 
////  counter                                                     ////
2487 
////                                                              ////
2488 
////  To Do:                                                      ////
2489 
////   - add LFSR with more taps                                  ////
2490 
////                                                              ////
2491 
////  Author(s):                                                  ////
2492 
////      - Michael Unneback, unneback@opencores.org              ////
2493 
////        ORSoC AB                                              ////
2494 
////                                                              ////
2495 
//////////////////////////////////////////////////////////////////////
2496 
////                                                              ////
2497 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2498 
////                                                              ////
2499 
//// This source file may be used and distributed without         ////
2500 
//// restriction provided that this copyright statement is not    ////
2501 
//// removed from the file and that any derivative work contains  ////
2502 
//// the original copyright notice and the associated disclaimer. ////
2503 
////                                                              ////
2504 
//// This source file is free software; you can redistribute it   ////
2505 
//// and/or modify it under the terms of the GNU Lesser General   ////
2506 
//// Public License as published by the Free Software Foundation; ////
2507 
//// either version 2.1 of the License, or (at your option) any   ////
2508 
//// later version.                                               ////
2509 
////                                                              ////
2510 
//// This source is distributed in the hope that it will be       ////
2511 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2512 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2513 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2514 
//// details.                                                     ////
2515 
////                                                              ////
2516 
//// You should have received a copy of the GNU Lesser General    ////
2517 
//// Public License along with this source; if not, download it   ////
2518 
//// from http://www.opencores.org/lgpl.shtml                     ////
2519 
////                                                              ////
2520 
//////////////////////////////////////////////////////////////////////
2521 
 
2522 
// LFSR counter
2523 
 
2524 40 unneback 
`define MODULE cnt_lfsr_ce_clear_q
2525 
module `BASE`MODULE (
2526 
`undef MODULE
2527 
 clear, cke, q, rst, clk);
2528 
 
2529 27 unneback 
   parameter length = 4;
2530 
   input clear;
2531 
   input cke;
2532 
   output [length:1] q;
2533 
   input rst;
2534 
   input clk;
2535 
 
2536 
   parameter clear_value = 0;
2537 
   parameter set_value = 1;
2538 
   parameter wrap_value = 8;
2539 
   parameter level1_value = 15;
2540 
 
2541 
   reg  [length:1] qi;
2542 
   reg lfsr_fb;
2543 
   wire [length:1] q_next;
2544 
   reg [32:1] polynom;
2545 
   integer i;
2546 
 
2547 
   always @ (qi)
2548 
   begin
2549 
        case (length)
2550 
         2: polynom = 32'b11;                               // 0x3
2551 
         3: polynom = 32'b110;                              // 0x6
2552 
         4: polynom = 32'b1100;                             // 0xC
2553 
         5: polynom = 32'b10100;                            // 0x14
2554 
         6: polynom = 32'b110000;                           // 0x30
2555 
         7: polynom = 32'b1100000;                          // 0x60
2556 
         8: polynom = 32'b10111000;                         // 0xb8
2557 
         9: polynom = 32'b100010000;                        // 0x110
2558 
        10: polynom = 32'b1001000000;                       // 0x240
2559 
        11: polynom = 32'b10100000000;                      // 0x500
2560 
        12: polynom = 32'b100000101001;                     // 0x829
2561 
        13: polynom = 32'b1000000001100;                    // 0x100C
2562 
        14: polynom = 32'b10000000010101;                   // 0x2015
2563 
        15: polynom = 32'b110000000000000;                  // 0x6000
2564 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2565 
        17: polynom = 32'b10010000000000000;                // 0x12000
2566 
        18: polynom = 32'b100000010000000000;               // 0x20400
2567 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2568 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2569 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2570 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2571 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2572 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2573 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2574 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2575 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2576 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2577 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2578 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2579 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2580 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2581 
        default: polynom = 32'b0;
2582 
        endcase
2583 
        lfsr_fb = qi[length];
2584 
        for (i=length-1; i>=1; i=i-1) begin
2585 
            if (polynom[i])
2586 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2587 
        end
2588 
    end
2589 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2590 
 
2591 
   always @ (posedge clk or posedge rst)
2592 
     if (rst)
2593 
       qi <= {length{1'b0}};
2594 
     else
2595 
     if (cke)
2596 
       qi <= q_next;
2597 
 
2598 
   assign q = qi;
2599 
 
2600 
endmodule
2601 40 unneback 
`endif
2602 
`ifdef CNT_LFSR_CE_Q_ZQ
2603 27 unneback 
//////////////////////////////////////////////////////////////////////
2604 
////                                                              ////
2605 
////  Versatile counter                                           ////
2606 
////                                                              ////
2607 
////  Description                                                 ////
2608 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2609 
////  counter                                                     ////
2610 
////                                                              ////
2611 
////  To Do:                                                      ////
2612 
////   - add LFSR with more taps                                  ////
2613 
////                                                              ////
2614 
////  Author(s):                                                  ////
2615 
////      - Michael Unneback, unneback@opencores.org              ////
2616 
////        ORSoC AB                                              ////
2617 
////                                                              ////
2618 
//////////////////////////////////////////////////////////////////////
2619 
////                                                              ////
2620 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2621 
////                                                              ////
2622 
//// This source file may be used and distributed without         ////
2623 
//// restriction provided that this copyright statement is not    ////
2624 
//// removed from the file and that any derivative work contains  ////
2625 
//// the original copyright notice and the associated disclaimer. ////
2626 
////                                                              ////
2627 
//// This source file is free software; you can redistribute it   ////
2628 
//// and/or modify it under the terms of the GNU Lesser General   ////
2629 
//// Public License as published by the Free Software Foundation; ////
2630 
//// either version 2.1 of the License, or (at your option) any   ////
2631 
//// later version.                                               ////
2632 
////                                                              ////
2633 
//// This source is distributed in the hope that it will be       ////
2634 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2635 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2636 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2637 
//// details.                                                     ////
2638 
////                                                              ////
2639 
//// You should have received a copy of the GNU Lesser General    ////
2640 
//// Public License along with this source; if not, download it   ////
2641 
//// from http://www.opencores.org/lgpl.shtml                     ////
2642 
////                                                              ////
2643 
//////////////////////////////////////////////////////////////////////
2644 
 
2645 
// LFSR counter
2646 22 unneback 
 
2647 40 unneback 
`define MODULE cnt_lfsr_ce_q_zq
2648 
module `BASE`MODULE (
2649 
`undef MODULE
2650 
 cke, q, zq, rst, clk);
2651 
 
2652 22 unneback 
   parameter length = 4;
2653 
   input cke;
2654 
   output [length:1] q;
2655 
   output reg zq;
2656 
   input rst;
2657 
   input clk;
2658 
 
2659 
   parameter clear_value = 0;
2660 
   parameter set_value = 1;
2661 
   parameter wrap_value = 8;
2662 
   parameter level1_value = 15;
2663 
 
2664 
   reg  [length:1] qi;
2665 
   reg lfsr_fb;
2666 
   wire [length:1] q_next;
2667 
   reg [32:1] polynom;
2668 
   integer i;
2669 
 
2670 
   always @ (qi)
2671 
   begin
2672 
        case (length)
2673 
         2: polynom = 32'b11;                               // 0x3
2674 
         3: polynom = 32'b110;                              // 0x6
2675 
         4: polynom = 32'b1100;                             // 0xC
2676 
         5: polynom = 32'b10100;                            // 0x14
2677 
         6: polynom = 32'b110000;                           // 0x30
2678 
         7: polynom = 32'b1100000;                          // 0x60
2679 
         8: polynom = 32'b10111000;                         // 0xb8
2680 
         9: polynom = 32'b100010000;                        // 0x110
2681 
        10: polynom = 32'b1001000000;                       // 0x240
2682 
        11: polynom = 32'b10100000000;                      // 0x500
2683 
        12: polynom = 32'b100000101001;                     // 0x829
2684 
        13: polynom = 32'b1000000001100;                    // 0x100C
2685 
        14: polynom = 32'b10000000010101;                   // 0x2015
2686 
        15: polynom = 32'b110000000000000;                  // 0x6000
2687 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2688 
        17: polynom = 32'b10010000000000000;                // 0x12000
2689 
        18: polynom = 32'b100000010000000000;               // 0x20400
2690 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2691 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2692 22 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2693 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2694 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2695 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2696 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2697 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2698 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2699 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2700 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2701 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2702 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2703 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2704 
        default: polynom = 32'b0;
2705 
        endcase
2706 
        lfsr_fb = qi[length];
2707 
        for (i=length-1; i>=1; i=i-1) begin
2708 
            if (polynom[i])
2709 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2710 
        end
2711 
    end
2712 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2713 
 
2714 
   always @ (posedge clk or posedge rst)
2715 
     if (rst)
2716 
       qi <= {length{1'b0}};
2717 
     else
2718 
     if (cke)
2719 
       qi <= q_next;
2720 
 
2721 
   assign q = qi;
2722 
 
2723 
 
2724 
   always @ (posedge clk or posedge rst)
2725 
     if (rst)
2726 
       zq <= 1'b1;
2727 
     else
2728 
     if (cke)
2729 
       zq <= q_next == {length{1'b0}};
2730 
endmodule
2731 40 unneback 
`endif
2732 
`ifdef CNT_LFSR_CE_REW_L1
2733 22 unneback 
//////////////////////////////////////////////////////////////////////
2734 
////                                                              ////
2735 
////  Versatile counter                                           ////
2736 
////                                                              ////
2737 
////  Description                                                 ////
2738 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2739 
////  counter                                                     ////
2740 
////                                                              ////
2741 
////  To Do:                                                      ////
2742 
////   - add LFSR with more taps                                  ////
2743 
////                                                              ////
2744 
////  Author(s):                                                  ////
2745 
////      - Michael Unneback, unneback@opencores.org              ////
2746 
////        ORSoC AB                                              ////
2747 
////                                                              ////
2748 
//////////////////////////////////////////////////////////////////////
2749 
////                                                              ////
2750 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2751 
////                                                              ////
2752 
//// This source file may be used and distributed without         ////
2753 
//// restriction provided that this copyright statement is not    ////
2754 
//// removed from the file and that any derivative work contains  ////
2755 
//// the original copyright notice and the associated disclaimer. ////
2756 
////                                                              ////
2757 
//// This source file is free software; you can redistribute it   ////
2758 
//// and/or modify it under the terms of the GNU Lesser General   ////
2759 
//// Public License as published by the Free Software Foundation; ////
2760 
//// either version 2.1 of the License, or (at your option) any   ////
2761 
//// later version.                                               ////
2762 
////                                                              ////
2763 
//// This source is distributed in the hope that it will be       ////
2764 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2765 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2766 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2767 
//// details.                                                     ////
2768 
////                                                              ////
2769 
//// You should have received a copy of the GNU Lesser General    ////
2770 
//// Public License along with this source; if not, download it   ////
2771 
//// from http://www.opencores.org/lgpl.shtml                     ////
2772 
////                                                              ////
2773 
//////////////////////////////////////////////////////////////////////
2774 6 unneback 
 
2775 
// LFSR counter
2776 
 
2777 40 unneback 
`define MODULE cnt_lfsr_ce_rew_l1
2778 
module `BASE`MODULE (
2779 
`undef MODULE
2780 
 cke, rew, level1, rst, clk);
2781 
 
2782 6 unneback 
   parameter length = 4;
2783 
   input cke;
2784 
   input rew;
2785 
   output reg level1;
2786 
   input rst;
2787 
   input clk;
2788 
 
2789 
   parameter clear_value = 0;
2790 
   parameter set_value = 1;
2791 
   parameter wrap_value = 8;
2792 
   parameter level1_value = 15;
2793 
 
2794 29 unneback 
   wire clear;
2795 30 unneback 
   assign clear = 1'b0;
2796 6 unneback 
   reg  [length:1] qi;
2797 
   reg lfsr_fb, lfsr_fb_rew;
2798 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2799 
   reg [32:1] polynom_rew;
2800 
   integer j;
2801 
   reg [32:1] polynom;
2802 
   integer i;
2803 
 
2804 
   always @ (qi)
2805 
   begin
2806 
        case (length)
2807 
         2: polynom = 32'b11;                               // 0x3
2808 
         3: polynom = 32'b110;                              // 0x6
2809 
         4: polynom = 32'b1100;                             // 0xC
2810 
         5: polynom = 32'b10100;                            // 0x14
2811 
         6: polynom = 32'b110000;                           // 0x30
2812 
         7: polynom = 32'b1100000;                          // 0x60
2813 
         8: polynom = 32'b10111000;                         // 0xb8
2814 
         9: polynom = 32'b100010000;                        // 0x110
2815 
        10: polynom = 32'b1001000000;                       // 0x240
2816 
        11: polynom = 32'b10100000000;                      // 0x500
2817 
        12: polynom = 32'b100000101001;                     // 0x829
2818 
        13: polynom = 32'b1000000001100;                    // 0x100C
2819 
        14: polynom = 32'b10000000010101;                   // 0x2015
2820 
        15: polynom = 32'b110000000000000;                  // 0x6000
2821 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2822 
        17: polynom = 32'b10010000000000000;                // 0x12000
2823 
        18: polynom = 32'b100000010000000000;               // 0x20400
2824 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2825 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2826 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2827 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2828 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2829 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2830 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2831 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2832 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2833 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2834 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2835 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2836 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2837 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2838 
        default: polynom = 32'b0;
2839 
        endcase
2840 
        lfsr_fb = qi[length];
2841 
        for (i=length-1; i>=1; i=i-1) begin
2842 
            if (polynom[i])
2843 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2844 
        end
2845 
    end
2846 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2847 
   always @ (qi)
2848 
   begin
2849 
        case (length)
2850 
         2: polynom_rew = 32'b11;
2851 
         3: polynom_rew = 32'b110;
2852 
         4: polynom_rew = 32'b1100;
2853 
         5: polynom_rew = 32'b10100;
2854 
         6: polynom_rew = 32'b110000;
2855 
         7: polynom_rew = 32'b1100000;
2856 
         8: polynom_rew = 32'b10111000;
2857 
         9: polynom_rew = 32'b100010000;
2858 
        10: polynom_rew = 32'b1001000000;
2859 
        11: polynom_rew = 32'b10100000000;
2860 
        12: polynom_rew = 32'b100000101001;
2861 
        13: polynom_rew = 32'b1000000001100;
2862 
        14: polynom_rew = 32'b10000000010101;
2863 
        15: polynom_rew = 32'b110000000000000;
2864 
        16: polynom_rew = 32'b1101000000001000;
2865 
        17: polynom_rew = 32'b10010000000000000;
2866 
        18: polynom_rew = 32'b100000010000000000;
2867 
        19: polynom_rew = 32'b1000000000000100011;
2868 
        20: polynom_rew = 32'b10000010000000000000;
2869 
        21: polynom_rew = 32'b101000000000000000000;
2870 
        22: polynom_rew = 32'b1100000000000000000000;
2871 
        23: polynom_rew = 32'b10000100000000000000000;
2872 
        24: polynom_rew = 32'b111000010000000000000000;
2873 
        25: polynom_rew = 32'b1001000000000000000000000;
2874 
        26: polynom_rew = 32'b10000000000000000000100011;
2875 
        27: polynom_rew = 32'b100000000000000000000010011;
2876 
        28: polynom_rew = 32'b1100100000000000000000000000;
2877 
        29: polynom_rew = 32'b10100000000000000000000000000;
2878 
        30: polynom_rew = 32'b100000000000000000000000101001;
2879 
        31: polynom_rew = 32'b1001000000000000000000000000000;
2880 
        32: polynom_rew = 32'b10000000001000000000000000000011;
2881 
        default: polynom_rew = 32'b0;
2882 
        endcase
2883 
        // rotate left
2884 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2885 
        lfsr_fb_rew = qi[length];
2886 
        for (i=length-1; i>=1; i=i-1) begin
2887 
            if (polynom_rew[i])
2888 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2889 
        end
2890 
    end
2891 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2892 
   assign q_next = rew ? q_next_rew : q_next_fw;
2893 
 
2894 
   always @ (posedge clk or posedge rst)
2895 
     if (rst)
2896 
       qi <= {length{1'b0}};
2897 
     else
2898 
     if (cke)
2899 
       qi <= q_next;
2900 
 
2901 
 
2902 
 
2903 
    always @ (posedge clk or posedge rst)
2904 
    if (rst)
2905 
        level1 <= 1'b0;
2906 
    else
2907 
    if (cke)
2908 29 unneback 
    if (clear)
2909 
        level1 <= 1'b0;
2910 
    else if (q_next == level1_value)
2911 6 unneback 
        level1 <= 1'b1;
2912 
    else if (qi == level1_value & rew)
2913 
        level1 <= 1'b0;
2914 
endmodule
2915 40 unneback 
`endif
2916 
`ifdef CNT_GRAY
2917 6 unneback 
//////////////////////////////////////////////////////////////////////
2918 
////                                                              ////
2919 
////  Versatile counter                                           ////
2920 
////                                                              ////
2921 
////  Description                                                 ////
2922 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2923 
////  counter                                                     ////
2924 
////                                                              ////
2925 
////  To Do:                                                      ////
2926 
////   - add LFSR with more taps                                  ////
2927 
////                                                              ////
2928 
////  Author(s):                                                  ////
2929 
////      - Michael Unneback, unneback@opencores.org              ////
2930 
////        ORSoC AB                                              ////
2931 
////                                                              ////
2932 
//////////////////////////////////////////////////////////////////////
2933 
////                                                              ////
2934 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2935 
////                                                              ////
2936 
//// This source file may be used and distributed without         ////
2937 
//// restriction provided that this copyright statement is not    ////
2938 
//// removed from the file and that any derivative work contains  ////
2939 
//// the original copyright notice and the associated disclaimer. ////
2940 
////                                                              ////
2941 
//// This source file is free software; you can redistribute it   ////
2942 
//// and/or modify it under the terms of the GNU Lesser General   ////
2943 
//// Public License as published by the Free Software Foundation; ////
2944 
//// either version 2.1 of the License, or (at your option) any   ////
2945 
//// later version.                                               ////
2946 
////                                                              ////
2947 
//// This source is distributed in the hope that it will be       ////
2948 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2949 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2950 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2951 
//// details.                                                     ////
2952 
////                                                              ////
2953 
//// You should have received a copy of the GNU Lesser General    ////
2954 
//// Public License along with this source; if not, download it   ////
2955 
//// from http://www.opencores.org/lgpl.shtml                     ////
2956 
////                                                              ////
2957 
//////////////////////////////////////////////////////////////////////
2958 
 
2959 
// GRAY counter
2960 
 
2961 40 unneback 
`define MODULE cnt_gray
2962 
module `BASE`MODULE (
2963 
`undef MODULE
2964 
 q, rst, clk);
2965 
 
2966 6 unneback 
   parameter length = 4;
2967 
   output reg [length:1] q;
2968 
   input rst;
2969 
   input clk;
2970 
 
2971 
   parameter clear_value = 0;
2972 
   parameter set_value = 1;
2973 
   parameter wrap_value = 8;
2974 
   parameter level1_value = 15;
2975 
 
2976 
   reg  [length:1] qi;
2977 
   wire [length:1] q_next;
2978 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2979 
 
2980 
   always @ (posedge clk or posedge rst)
2981 
     if (rst)
2982 
       qi <= {length{1'b0}};
2983 
     else
2984 
       qi <= q_next;
2985 
 
2986 
   always @ (posedge clk or posedge rst)
2987 
     if (rst)
2988 
       q <= {length{1'b0}};
2989 
     else
2990 
         q <= (q_next>>1) ^ q_next;
2991 
 
2992 
endmodule
2993 40 unneback 
`endif
2994 
`ifdef CNT_GRAY_CE
2995 6 unneback 
//////////////////////////////////////////////////////////////////////
2996 
////                                                              ////
2997 
////  Versatile counter                                           ////
2998 
////                                                              ////
2999 
////  Description                                                 ////
3000 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3001 
////  counter                                                     ////
3002 
////                                                              ////
3003 
////  To Do:                                                      ////
3004 
////   - add LFSR with more taps                                  ////
3005 
////                                                              ////
3006 
////  Author(s):                                                  ////
3007 
////      - Michael Unneback, unneback@opencores.org              ////
3008 
////        ORSoC AB                                              ////
3009 
////                                                              ////
3010 
//////////////////////////////////////////////////////////////////////
3011 
////                                                              ////
3012 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3013 
////                                                              ////
3014 
//// This source file may be used and distributed without         ////
3015 
//// restriction provided that this copyright statement is not    ////
3016 
//// removed from the file and that any derivative work contains  ////
3017 
//// the original copyright notice and the associated disclaimer. ////
3018 
////                                                              ////
3019 
//// This source file is free software; you can redistribute it   ////
3020 
//// and/or modify it under the terms of the GNU Lesser General   ////
3021 
//// Public License as published by the Free Software Foundation; ////
3022 
//// either version 2.1 of the License, or (at your option) any   ////
3023 
//// later version.                                               ////
3024 
////                                                              ////
3025 
//// This source is distributed in the hope that it will be       ////
3026 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3027 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3028 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3029 
//// details.                                                     ////
3030 
////                                                              ////
3031 
//// You should have received a copy of the GNU Lesser General    ////
3032 
//// Public License along with this source; if not, download it   ////
3033 
//// from http://www.opencores.org/lgpl.shtml                     ////
3034 
////                                                              ////
3035 
//////////////////////////////////////////////////////////////////////
3036 
 
3037 
// GRAY counter
3038 
 
3039 40 unneback 
`define MODULE cnt_gray_ce
3040 
module `BASE`MODULE (
3041 
`undef MODULE
3042 
 cke, q, rst, clk);
3043 
 
3044 6 unneback 
   parameter length = 4;
3045 
   input cke;
3046 
   output reg [length:1] q;
3047 
   input rst;
3048 
   input clk;
3049 
 
3050 
   parameter clear_value = 0;
3051 
   parameter set_value = 1;
3052 
   parameter wrap_value = 8;
3053 
   parameter level1_value = 15;
3054 
 
3055 
   reg  [length:1] qi;
3056 
   wire [length:1] q_next;
3057 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3058 
 
3059 
   always @ (posedge clk or posedge rst)
3060 
     if (rst)
3061 
       qi <= {length{1'b0}};
3062 
     else
3063 
     if (cke)
3064 
       qi <= q_next;
3065 
 
3066 
   always @ (posedge clk or posedge rst)
3067 
     if (rst)
3068 
       q <= {length{1'b0}};
3069 
     else
3070 
       if (cke)
3071 
         q <= (q_next>>1) ^ q_next;
3072 
 
3073 
endmodule
3074 40 unneback 
`endif
3075 
`ifdef CNT_GRAY_CE_BIN
3076 6 unneback 
//////////////////////////////////////////////////////////////////////
3077 
////                                                              ////
3078 
////  Versatile counter                                           ////
3079 
////                                                              ////
3080 
////  Description                                                 ////
3081 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3082 
////  counter                                                     ////
3083 
////                                                              ////
3084 
////  To Do:                                                      ////
3085 
////   - add LFSR with more taps                                  ////
3086 
////                                                              ////
3087 
////  Author(s):                                                  ////
3088 
////      - Michael Unneback, unneback@opencores.org              ////
3089 
////        ORSoC AB                                              ////
3090 
////                                                              ////
3091 
//////////////////////////////////////////////////////////////////////
3092 
////                                                              ////
3093 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3094 
////                                                              ////
3095 
//// This source file may be used and distributed without         ////
3096 
//// restriction provided that this copyright statement is not    ////
3097 
//// removed from the file and that any derivative work contains  ////
3098 
//// the original copyright notice and the associated disclaimer. ////
3099 
////                                                              ////
3100 
//// This source file is free software; you can redistribute it   ////
3101 
//// and/or modify it under the terms of the GNU Lesser General   ////
3102 
//// Public License as published by the Free Software Foundation; ////
3103 
//// either version 2.1 of the License, or (at your option) any   ////
3104 
//// later version.                                               ////
3105 
////                                                              ////
3106 
//// This source is distributed in the hope that it will be       ////
3107 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3108 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3109 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3110 
//// details.                                                     ////
3111 
////                                                              ////
3112 
//// You should have received a copy of the GNU Lesser General    ////
3113 
//// Public License along with this source; if not, download it   ////
3114 
//// from http://www.opencores.org/lgpl.shtml                     ////
3115 
////                                                              ////
3116 
//////////////////////////////////////////////////////////////////////
3117 
 
3118 
// GRAY counter
3119 
 
3120 40 unneback 
`define MODULE cnt_gray_ce_bin
3121 
module `BASE`MODULE (
3122 
`undef MODULE
3123 
 cke, q, q_bin, rst, clk);
3124 
 
3125 6 unneback 
   parameter length = 4;
3126 
   input cke;
3127 
   output reg [length:1] q;
3128 
   output [length:1] q_bin;
3129 
   input rst;
3130 
   input clk;
3131 
 
3132 
   parameter clear_value = 0;
3133 
   parameter set_value = 1;
3134 
   parameter wrap_value = 8;
3135 
   parameter level1_value = 15;
3136 
 
3137 
   reg  [length:1] qi;
3138 
   wire [length:1] q_next;
3139 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3140 
 
3141 
   always @ (posedge clk or posedge rst)
3142 
     if (rst)
3143 
       qi <= {length{1'b0}};
3144 
     else
3145 
     if (cke)
3146 
       qi <= q_next;
3147 
 
3148 
   always @ (posedge clk or posedge rst)
3149 
     if (rst)
3150 
       q <= {length{1'b0}};
3151 
     else
3152 
       if (cke)
3153 
         q <= (q_next>>1) ^ q_next;
3154 
 
3155 
   assign q_bin = qi;
3156 
 
3157 
endmodule
3158 40 unneback 
`endif
3159 6 unneback 
//////////////////////////////////////////////////////////////////////
3160 
////                                                              ////
3161 
////  Versatile library, counters                                 ////
3162 
////                                                              ////
3163 
////  Description                                                 ////
3164 
////  counters                                                    ////
3165 
////                                                              ////
3166 
////                                                              ////
3167 
////  To Do:                                                      ////
3168 
////   - add more counters                                        ////
3169 
////                                                              ////
3170 
////  Author(s):                                                  ////
3171 
////      - Michael Unneback, unneback@opencores.org              ////
3172 
////        ORSoC AB                                              ////
3173 
////                                                              ////
3174 
//////////////////////////////////////////////////////////////////////
3175 
////                                                              ////
3176 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3177 
////                                                              ////
3178 
//// This source file may be used and distributed without         ////
3179 
//// restriction provided that this copyright statement is not    ////
3180 
//// removed from the file and that any derivative work contains  ////
3181 
//// the original copyright notice and the associated disclaimer. ////
3182 
////                                                              ////
3183 
//// This source file is free software; you can redistribute it   ////
3184 
//// and/or modify it under the terms of the GNU Lesser General   ////
3185 
//// Public License as published by the Free Software Foundation; ////
3186 
//// either version 2.1 of the License, or (at your option) any   ////
3187 
//// later version.                                               ////
3188 
////                                                              ////
3189 
//// This source is distributed in the hope that it will be       ////
3190 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3191 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3192 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3193 
//// details.                                                     ////
3194 
////                                                              ////
3195 
//// You should have received a copy of the GNU Lesser General    ////
3196 
//// Public License along with this source; if not, download it   ////
3197 
//// from http://www.opencores.org/lgpl.shtml                     ////
3198 
////                                                              ////
3199 
//////////////////////////////////////////////////////////////////////
3200 
 
3201 40 unneback 
`ifdef CNT_SHREG_WRAP
3202 
`define MODULE cnt_shreg_wrap
3203 
module `BASE`MODULE ( q, rst, clk);
3204 
`undef MODULE
3205 6 unneback 
 
3206 
   parameter length = 4;
3207 
   output reg [0:length-1] q;
3208 
   input rst;
3209 
   input clk;
3210 
 
3211 
    always @ (posedge clk or posedge rst)
3212 
    if (rst)
3213 
        q <= {1'b1,{length-1{1'b0}}};
3214 
    else
3215 
        q <= {q[length-1],q[0:length-2]};
3216 
 
3217 
endmodule
3218 40 unneback 
`endif
3219 6 unneback 
 
3220 40 unneback 
`ifdef CNT_SHREG_CE_WRAP
3221 
`define MODULE cnt_shreg_ce_wrap
3222 
module `BASE`MODULE ( cke, q, rst, clk);
3223 
`undef MODULE
3224 6 unneback 
 
3225 
   parameter length = 4;
3226 
   input cke;
3227 
   output reg [0:length-1] q;
3228 
   input rst;
3229 
   input clk;
3230 
 
3231 
    always @ (posedge clk or posedge rst)
3232 
    if (rst)
3233 
        q <= {1'b1,{length-1{1'b0}}};
3234 
    else
3235 
        if (cke)
3236 
            q <= {q[length-1],q[0:length-2]};
3237 
 
3238 
endmodule
3239 40 unneback 
`endif
3240 6 unneback 
 
3241 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR
3242 
`define MODULE cnt_shreg_ce_clear
3243 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3244 
`undef MODULE
3245 6 unneback 
 
3246 
   parameter length = 4;
3247 
   input cke, clear;
3248 
   output reg [0:length-1] q;
3249 
   input rst;
3250 
   input clk;
3251 
 
3252 
    always @ (posedge clk or posedge rst)
3253 
    if (rst)
3254 
        q <= {1'b1,{length-1{1'b0}}};
3255 
    else
3256 
        if (cke)
3257 
            if (clear)
3258 
                q <= {1'b1,{length-1{1'b0}}};
3259 
            else
3260 
                q <= q >> 1;
3261 
 
3262 
endmodule
3263 40 unneback 
`endif
3264 6 unneback 
 
3265 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3266 
`define MODULE cnt_shreg_ce_clear_wrap
3267 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3268 
`undef MODULE
3269 6 unneback 
 
3270 
   parameter length = 4;
3271 
   input cke, clear;
3272 
   output reg [0:length-1] q;
3273 
   input rst;
3274 
   input clk;
3275 
 
3276 
    always @ (posedge clk or posedge rst)
3277 
    if (rst)
3278 
        q <= {1'b1,{length-1{1'b0}}};
3279 
    else
3280 
        if (cke)
3281 
            if (clear)
3282 
                q <= {1'b1,{length-1{1'b0}}};
3283 
            else
3284 
            q <= {q[length-1],q[0:length-2]};
3285 
 
3286 
endmodule
3287 40 unneback 
`endif
3288 6 unneback 
//////////////////////////////////////////////////////////////////////
3289 
////                                                              ////
3290 
////  Versatile library, memories                                 ////
3291 
////                                                              ////
3292 
////  Description                                                 ////
3293 
////  memories                                                    ////
3294 
////                                                              ////
3295 
////                                                              ////
3296 
////  To Do:                                                      ////
3297 
////   - add more memory types                                    ////
3298 
////                                                              ////
3299 
////  Author(s):                                                  ////
3300 
////      - Michael Unneback, unneback@opencores.org              ////
3301 
////        ORSoC AB                                              ////
3302 
////                                                              ////
3303 
//////////////////////////////////////////////////////////////////////
3304 
////                                                              ////
3305 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3306 
////                                                              ////
3307 
//// This source file may be used and distributed without         ////
3308 
//// restriction provided that this copyright statement is not    ////
3309 
//// removed from the file and that any derivative work contains  ////
3310 
//// the original copyright notice and the associated disclaimer. ////
3311 
////                                                              ////
3312 
//// This source file is free software; you can redistribute it   ////
3313 
//// and/or modify it under the terms of the GNU Lesser General   ////
3314 
//// Public License as published by the Free Software Foundation; ////
3315 
//// either version 2.1 of the License, or (at your option) any   ////
3316 
//// later version.                                               ////
3317 
////                                                              ////
3318 
//// This source is distributed in the hope that it will be       ////
3319 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3320 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3321 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3322 
//// details.                                                     ////
3323 
////                                                              ////
3324 
//// You should have received a copy of the GNU Lesser General    ////
3325 
//// Public License along with this source; if not, download it   ////
3326 
//// from http://www.opencores.org/lgpl.shtml                     ////
3327 
////                                                              ////
3328 
//////////////////////////////////////////////////////////////////////
3329 
 
3330 40 unneback 
`ifdef ROM_INIT
3331 6 unneback 
/// ROM
3332 40 unneback 
`define MODULE rom_init
3333 
module `BASE`MODULE ( adr, q, clk);
3334 
`undef MODULE
3335 6 unneback 
 
3336 7 unneback 
   parameter data_width = 32;
3337 
   parameter addr_width = 8;
3338 
   input [(addr_width-1):0]       adr;
3339 
   output reg [(data_width-1):0] q;
3340 
   input                         clk;
3341 
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
3342 
   parameter memory_file = "vl_rom.vmem";
3343 
   initial
3344 
     begin
3345 
        $readmemh(memory_file, rom);
3346 
     end
3347 
 
3348 
   always @ (posedge clk)
3349 
     q <= rom[adr];
3350 6 unneback 
 
3351 7 unneback 
endmodule
3352 40 unneback 
`endif
3353 7 unneback 
 
3354 14 unneback 
/*
3355 7 unneback 
module vl_rom ( adr, q, clk);
3356 
 
3357 6 unneback 
parameter data_width = 32;
3358 
parameter addr_width = 4;
3359 
 
3360 
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
3361 
    {32'h18000000},
3362 
    {32'hA8200000},
3363 
    {32'hA8200000},
3364 
    {32'hA8200000},
3365 
    {32'h44003000},
3366 
    {32'h15000000},
3367 
    {32'h15000000},
3368 
    {32'h15000000},
3369 
    {32'h15000000},
3370 
    {32'h15000000},
3371 
    {32'h15000000},
3372 
    {32'h15000000},
3373 
    {32'h15000000},
3374 
    {32'h15000000},
3375 
    {32'h15000000},
3376 
    {32'h15000000}};
3377 
 
3378 7 unneback 
input [addr_width-1:0] adr;
3379 6 unneback 
output reg [data_width-1:0] q;
3380 
input clk;
3381 
 
3382 
always @ (posedge clk)
3383 7 unneback 
    q <= data[adr];
3384 6 unneback 
 
3385 
endmodule
3386 14 unneback 
*/
3387 40 unneback 
 
3388 
`ifdef RAM
3389 
`define MODULE ram
3390 6 unneback 
// Single port RAM
3391 40 unneback 
module `BASE`MODULE ( d, adr, we, q, clk);
3392 
`undef MODULE
3393 6 unneback 
 
3394 
   parameter data_width = 32;
3395 
   parameter addr_width = 8;
3396 
   input [(data_width-1):0]      d;
3397 
   input [(addr_width-1):0]       adr;
3398 
   input                         we;
3399 7 unneback 
   output reg [(data_width-1):0] q;
3400 6 unneback 
   input                         clk;
3401 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3402 7 unneback 
   parameter init = 0;
3403 
   parameter memory_file = "vl_ram.vmem";
3404 
   generate if (init) begin : init_mem
3405 
   initial
3406 
     begin
3407 
        $readmemh(memory_file, ram);
3408 
     end
3409 
   end
3410 
   endgenerate
3411 
 
3412 6 unneback 
   always @ (posedge clk)
3413 
   begin
3414 
   if (we)
3415 
     ram[adr] <= d;
3416 
   q <= ram[adr];
3417 
   end
3418 
 
3419 
endmodule
3420 40 unneback 
`endif
3421 6 unneback 
 
3422 40 unneback 
`ifdef RAM_BE
3423 
`define MODULE ram_be
3424 
module `BASE`MODULE ( d, adr, be, we, q, clk);
3425 
`undef MODULE
3426 
 
3427 7 unneback 
   parameter data_width = 32;
3428 
   parameter addr_width = 8;
3429 
   input [(data_width-1):0]      d;
3430 
   input [(addr_width-1):0]       adr;
3431 
   input [(addr_width/4)-1:0]    be;
3432 
   input                         we;
3433 
   output reg [(data_width-1):0] q;
3434 
   input                         clk;
3435 
 
3436 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3437 
 
3438 
   parameter init = 0;
3439 
   parameter memory_file = "vl_ram.vmem";
3440 
   generate if (init) begin : init_mem
3441 
   initial
3442 
     begin
3443 
        $readmemh(memory_file, ram);
3444 
     end
3445 
   end
3446 
   endgenerate
3447 
 
3448 
   genvar i;
3449 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
3450 
      always @ (posedge clk)
3451 
      if (we & be[i])
3452 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3453 
   end
3454 
   endgenerate
3455 
 
3456 
   always @ (posedge clk)
3457 
      q <= ram[adr];
3458 
 
3459 
endmodule
3460 40 unneback 
`endif
3461 7 unneback 
 
3462 6 unneback 
// Dual port RAM
3463 
 
3464 
// ACTEL FPGA should not use logic to handle rw collision
3465 
`ifdef ACTEL
3466 
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
3467 
`else
3468 
        `define SYN
3469 
`endif
3470 
 
3471 40 unneback 
`ifdef DPRAM_1R1W
3472 
`define MODULE dpram_1r1w
3473 
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3474 
`undef MODULE
3475 6 unneback 
   parameter data_width = 32;
3476 
   parameter addr_width = 8;
3477 
   input [(data_width-1):0]      d_a;
3478 
   input [(addr_width-1):0]       adr_a;
3479 
   input [(addr_width-1):0]       adr_b;
3480 
   input                         we_a;
3481 
   output [(data_width-1):0]      q_b;
3482 
   input                         clk_a, clk_b;
3483 
   reg [(addr_width-1):0]         adr_b_reg;
3484 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3485 7 unneback 
 
3486 
   parameter init = 0;
3487 
   parameter memory_file = "vl_ram.vmem";
3488 
   generate if (init) begin : init_mem
3489 
   initial
3490 
     begin
3491 
        $readmemh(memory_file, ram);
3492 
     end
3493 
   end
3494 
   endgenerate
3495 
 
3496 6 unneback 
   always @ (posedge clk_a)
3497 
   if (we_a)
3498 
     ram[adr_a] <= d_a;
3499 
   always @ (posedge clk_b)
3500 
   adr_b_reg <= adr_b;
3501 
   assign q_b = ram[adr_b_reg];
3502 40 unneback 
 
3503 6 unneback 
endmodule
3504 40 unneback 
`endif
3505 6 unneback 
 
3506 40 unneback 
`ifdef DPRAM_2R1W
3507 
`define MODULE dpram_2r1w
3508 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3509 
`undef MODULE
3510 
 
3511 6 unneback 
   parameter data_width = 32;
3512 
   parameter addr_width = 8;
3513 
   input [(data_width-1):0]      d_a;
3514 
   input [(addr_width-1):0]       adr_a;
3515 
   input [(addr_width-1):0]       adr_b;
3516 
   input                         we_a;
3517 
   output [(data_width-1):0]      q_b;
3518 
   output reg [(data_width-1):0] q_a;
3519 
   input                         clk_a, clk_b;
3520 
   reg [(data_width-1):0]         q_b;
3521 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3522 7 unneback 
 
3523 
   parameter init = 0;
3524 
   parameter memory_file = "vl_ram.vmem";
3525 
   generate if (init) begin : init_mem
3526 
   initial
3527 
     begin
3528 
        $readmemh(memory_file, ram);
3529 
     end
3530 
   end
3531 
   endgenerate
3532 
 
3533 6 unneback 
   always @ (posedge clk_a)
3534 
     begin
3535 
        q_a <= ram[adr_a];
3536 
        if (we_a)
3537 
             ram[adr_a] <= d_a;
3538 
     end
3539 
   always @ (posedge clk_b)
3540 
          q_b <= ram[adr_b];
3541 
endmodule
3542 40 unneback 
`endif
3543 6 unneback 
 
3544 40 unneback 
`ifdef DPRAM_2R2W
3545 
`define MODULE dpram_2r2w
3546 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3547 
`undef MODULE
3548 
 
3549 6 unneback 
   parameter data_width = 32;
3550 
   parameter addr_width = 8;
3551 
   input [(data_width-1):0]      d_a;
3552 
   input [(addr_width-1):0]       adr_a;
3553 
   input [(addr_width-1):0]       adr_b;
3554 
   input                         we_a;
3555 
   output [(data_width-1):0]      q_b;
3556 
   input [(data_width-1):0]       d_b;
3557 
   output reg [(data_width-1):0] q_a;
3558 
   input                         we_b;
3559 
   input                         clk_a, clk_b;
3560 
   reg [(data_width-1):0]         q_b;
3561 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3562 7 unneback 
 
3563 
   parameter init = 0;
3564 
   parameter memory_file = "vl_ram.vmem";
3565 
   generate if (init) begin : init_mem
3566 
   initial
3567 
     begin
3568 
        $readmemh(memory_file, ram);
3569 
     end
3570 
   end
3571 
   endgenerate
3572 
 
3573 6 unneback 
   always @ (posedge clk_a)
3574 
     begin
3575 
        q_a <= ram[adr_a];
3576 
        if (we_a)
3577 
             ram[adr_a] <= d_a;
3578 
     end
3579 
   always @ (posedge clk_b)
3580 
     begin
3581 
        q_b <= ram[adr_b];
3582 
        if (we_b)
3583 
          ram[adr_b] <= d_b;
3584 
     end
3585 
endmodule
3586 40 unneback 
`endif
3587 6 unneback 
 
3588 
// Content addresable memory, CAM
3589 
 
3590 40 unneback 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
3591 6 unneback 
// FIFO
3592 40 unneback 
`define MODULE fifo_1r1w_fill_level_sync
3593 
module `BASE`MODULE (
3594 
`undef MODULE
3595 25 unneback 
    d, wr, fifo_full,
3596 
    q, rd, fifo_empty,
3597 
    fill_level,
3598 
    clk, rst
3599 
    );
3600 
 
3601 
parameter data_width = 18;
3602 
parameter addr_width = 4;
3603 6 unneback 
 
3604 25 unneback 
// write side
3605 
input  [data_width-1:0] d;
3606 
input                   wr;
3607 
output                  fifo_full;
3608 
// read side
3609 
output [data_width-1:0] q;
3610 
input                   rd;
3611 
output                  fifo_empty;
3612 
// common
3613 
output [addr_width:0]   fill_level;
3614 
input rst, clk;
3615 
 
3616 
wire [addr_width:1] wadr, radr;
3617 
 
3618 40 unneback 
`define MODULE cnt_bin_ce
3619 
`BASE`MODULE
3620 25 unneback 
    # ( .length(addr_width))
3621 
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
3622 40 unneback 
`BASE`MODULE
3623 25 unneback 
    # (.length(addr_width))
3624 
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
3625 40 unneback 
`undef MODULE
3626 25 unneback 
 
3627 40 unneback 
`define MODULE dpram_1r1w
3628 
`BASE`MODULE
3629 25 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
3630 
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
3631 40 unneback 
`undef MODULE
3632 25 unneback 
 
3633 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
3634 
`BASE`MODULE
3635 27 unneback 
    # (.length(addr_width+1), .level1_value(1<<addr_width))
3636 25 unneback 
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
3637 40 unneback 
`undef MODULE
3638 25 unneback 
endmodule
3639 40 unneback 
`endif
3640 25 unneback 
 
3641 40 unneback 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
3642 27 unneback 
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
3643 
// RAM is supposed to be larger than the two FIFOs
3644 
// LFSR counters used adr pointers
3645 40 unneback 
`define MODULE fifo_2r2w_sync_simplex
3646 
module `BASE`MODULE (
3647 
`undef MODULE
3648 27 unneback 
    // a side
3649 
    a_d, a_wr, a_fifo_full,
3650 
    a_q, a_rd, a_fifo_empty,
3651 
    a_fill_level,
3652 
    // b side
3653 
    b_d, b_wr, b_fifo_full,
3654 
    b_q, b_rd, b_fifo_empty,
3655 
    b_fill_level,
3656 
    // common
3657 
    clk, rst
3658 
    );
3659 
parameter data_width = 8;
3660 
parameter addr_width = 5;
3661 
parameter fifo_full_level = (1<<addr_width)-1;
3662 
 
3663 
// a side
3664 
input  [data_width-1:0] a_d;
3665 
input                   a_wr;
3666 
output                  a_fifo_full;
3667 
output [data_width-1:0] a_q;
3668 
input                   a_rd;
3669 
output                  a_fifo_empty;
3670 
output [addr_width-1:0] a_fill_level;
3671 
 
3672 
// b side
3673 
input  [data_width-1:0] b_d;
3674 
input                   b_wr;
3675 
output                  b_fifo_full;
3676 
output [data_width-1:0] b_q;
3677 
input                   b_rd;
3678 
output                  b_fifo_empty;
3679 
output [addr_width-1:0] b_fill_level;
3680 
 
3681 
input                   clk;
3682 
input                   rst;
3683 
 
3684 
// adr_gen
3685 
wire [addr_width:1] a_wadr, a_radr;
3686 
wire [addr_width:1] b_wadr, b_radr;
3687 
// dpram
3688 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3689 
 
3690 40 unneback 
`define MODULE cnt_lfsr_ce
3691 
`BASE`MODULE
3692 27 unneback 
    # ( .length(addr_width))
3693 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
3694 
 
3695 40 unneback 
`BASE`MODULE
3696 27 unneback 
    # (.length(addr_width))
3697 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
3698 
 
3699 40 unneback 
`BASE`MODULE
3700 27 unneback 
    # ( .length(addr_width))
3701 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
3702 
 
3703 40 unneback 
`BASE`MODULE
3704 27 unneback 
    # (.length(addr_width))
3705 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
3706 40 unneback 
`undef MODULE
3707 27 unneback 
 
3708 
// mux read or write adr to DPRAM
3709 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
3710 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
3711 
 
3712 40 unneback 
`define MODULE dpram_2r2w
3713 
`BASE`MODULE
3714 27 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
3715 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3716 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3717 40 unneback 
`undef MODULE
3718 
 
3719 
`define MODULE cnt_bin_ce_rew_zq_l1
3720 
`BASE`MODULE
3721 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
3722 27 unneback 
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
3723 
 
3724 40 unneback 
`BASE`MODULE
3725 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
3726 27 unneback 
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
3727 40 unneback 
`undef MODULE
3728 27 unneback 
 
3729 
endmodule
3730 40 unneback 
`endif
3731 27 unneback 
 
3732 40 unneback 
`ifdef FIFO_CMP_ASYNC
3733 
`define MODULE fifo_cmp_async
3734 
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
3735 
`undef MODULE
3736 6 unneback 
 
3737 11 unneback 
   parameter addr_width = 4;
3738 
   parameter N = addr_width-1;
3739 6 unneback 
 
3740 
   parameter Q1 = 2'b00;
3741 
   parameter Q2 = 2'b01;
3742 
   parameter Q3 = 2'b11;
3743 
   parameter Q4 = 2'b10;
3744 
 
3745 
   parameter going_empty = 1'b0;
3746 
   parameter going_full  = 1'b1;
3747 
 
3748 
   input [N:0]  wptr, rptr;
3749 14 unneback 
   output       fifo_empty;
3750 6 unneback 
   output       fifo_full;
3751 
   input        wclk, rclk, rst;
3752 
 
3753 
`ifndef GENERATE_DIRECTION_AS_LATCH
3754 
   wire direction;
3755 
`endif
3756 
`ifdef GENERATE_DIRECTION_AS_LATCH
3757 
   reg direction;
3758 
`endif
3759 
   reg  direction_set, direction_clr;
3760 
 
3761 
   wire async_empty, async_full;
3762 
   wire fifo_full2;
3763 14 unneback 
   wire fifo_empty2;
3764 6 unneback 
 
3765 
   // direction_set
3766 
   always @ (wptr[N:N-1] or rptr[N:N-1])
3767 
     case ({wptr[N:N-1],rptr[N:N-1]})
3768 
       {Q1,Q2} : direction_set <= 1'b1;
3769 
       {Q2,Q3} : direction_set <= 1'b1;
3770 
       {Q3,Q4} : direction_set <= 1'b1;
3771 
       {Q4,Q1} : direction_set <= 1'b1;
3772 
       default : direction_set <= 1'b0;
3773 
     endcase
3774 
 
3775 
   // direction_clear
3776 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
3777 
     if (rst)
3778 
       direction_clr <= 1'b1;
3779 
     else
3780 
       case ({wptr[N:N-1],rptr[N:N-1]})
3781 
         {Q2,Q1} : direction_clr <= 1'b1;
3782 
         {Q3,Q2} : direction_clr <= 1'b1;
3783 
         {Q4,Q3} : direction_clr <= 1'b1;
3784 
         {Q1,Q4} : direction_clr <= 1'b1;
3785 
         default : direction_clr <= 1'b0;
3786 
       endcase
3787 
 
3788 40 unneback 
`define MODULE dff_sr
3789 6 unneback 
`ifndef GENERATE_DIRECTION_AS_LATCH
3790 40 unneback 
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
3791 6 unneback 
`endif
3792 
 
3793 
`ifdef GENERATE_DIRECTION_AS_LATCH
3794 
   always @ (posedge direction_set or posedge direction_clr)
3795 
     if (direction_clr)
3796 
       direction <= going_empty;
3797 
     else
3798 
       direction <= going_full;
3799 
`endif
3800 
 
3801 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
3802 
   assign async_full  = (wptr == rptr) && (direction==going_full);
3803 
 
3804 40 unneback 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
3805 
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
3806 
`undef MODULE
3807 6 unneback 
 
3808 
/*
3809 
   always @ (posedge wclk or posedge rst or posedge async_full)
3810 
     if (rst)
3811 
       {fifo_full, fifo_full2} <= 2'b00;
3812 
     else if (async_full)
3813 
       {fifo_full, fifo_full2} <= 2'b11;
3814 
     else
3815 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
3816 
*/
3817 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
3818 6 unneback 
     if (async_empty)
3819 
       {fifo_empty, fifo_empty2} <= 2'b11;
3820 
     else
3821 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
3822 40 unneback 
`define MODULE dff
3823 
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
3824 
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
3825 
`undef MODULE
3826 27 unneback 
endmodule // async_compb
3827 40 unneback 
`endif
3828 6 unneback 
 
3829 40 unneback 
`ifdef FIFO_1R1W_ASYNC
3830 
`define MODULE fifo_1r1w_async
3831 
module `BASE`MODULE (
3832 
`undef MODULE
3833 6 unneback 
    d, wr, fifo_full, wr_clk, wr_rst,
3834 
    q, rd, fifo_empty, rd_clk, rd_rst
3835 
    );
3836 
 
3837 
parameter data_width = 18;
3838 
parameter addr_width = 4;
3839 
 
3840 
// write side
3841 
input  [data_width-1:0] d;
3842 
input                   wr;
3843 
output                  fifo_full;
3844 
input                   wr_clk;
3845 
input                   wr_rst;
3846 
// read side
3847 
output [data_width-1:0] q;
3848 
input                   rd;
3849 
output                  fifo_empty;
3850 
input                   rd_clk;
3851 
input                   rd_rst;
3852 
 
3853 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
3854 23 unneback 
 
3855 40 unneback 
`define MODULE cnt_gray_ce_bin
3856 
`BASE`MODULE
3857 6 unneback 
    # ( .length(addr_width))
3858 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
3859 
 
3860 40 unneback 
`BASE`MODULE
3861 6 unneback 
    # (.length(addr_width))
3862 23 unneback 
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
3863 40 unneback 
`undef MODULE
3864 6 unneback 
 
3865 40 unneback 
`define MODULE dpram_1r1w
3866 
`BASE`MODULE
3867 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
3868 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
3869 40 unneback 
`undef MODULE
3870 6 unneback 
 
3871 40 unneback 
`define MODULE fifo_cmp_async
3872 
`BASE`MODULE
3873 6 unneback 
    # (.addr_width(addr_width))
3874 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
3875 40 unneback 
`undef MODULE
3876 6 unneback 
 
3877 
endmodule
3878 40 unneback 
`endif
3879 6 unneback 
 
3880 40 unneback 
`ifdef FIFO_2R2W_ASYNC
3881 
`define MODULE fifo_2r2w_async
3882 
module `BASE`MODULE (
3883 
`undef MODULE
3884 6 unneback 
    // a side
3885 
    a_d, a_wr, a_fifo_full,
3886 
    a_q, a_rd, a_fifo_empty,
3887 
    a_clk, a_rst,
3888 
    // b side
3889 
    b_d, b_wr, b_fifo_full,
3890 
    b_q, b_rd, b_fifo_empty,
3891 
    b_clk, b_rst
3892 
    );
3893 
 
3894 
parameter data_width = 18;
3895 
parameter addr_width = 4;
3896 
 
3897 
// a side
3898 
input  [data_width-1:0] a_d;
3899 
input                   a_wr;
3900 
output                  a_fifo_full;
3901 
output [data_width-1:0] a_q;
3902 
input                   a_rd;
3903 
output                  a_fifo_empty;
3904 
input                   a_clk;
3905 
input                   a_rst;
3906 
 
3907 
// b side
3908 
input  [data_width-1:0] b_d;
3909 
input                   b_wr;
3910 
output                  b_fifo_full;
3911 
output [data_width-1:0] b_q;
3912 
input                   b_rd;
3913 
output                  b_fifo_empty;
3914 
input                   b_clk;
3915 
input                   b_rst;
3916 
 
3917 40 unneback 
`define MODULE fifo_1r1w_async
3918 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
3919 6 unneback 
vl_fifo_1r1w_async_a (
3920 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
3921 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
3922 
    );
3923 
 
3924 40 unneback 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
3925 6 unneback 
vl_fifo_1r1w_async_b (
3926 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
3927 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
3928 
    );
3929 40 unneback 
`undef MODULE
3930 
 
3931 6 unneback 
endmodule
3932 40 unneback 
`endif
3933 6 unneback 
 
3934 40 unneback 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
3935 
`define MODULE fifo_2r2w_async_simplex
3936 
module `BASE`MODULE (
3937 
`undef MODULE
3938 6 unneback 
    // a side
3939 
    a_d, a_wr, a_fifo_full,
3940 
    a_q, a_rd, a_fifo_empty,
3941 
    a_clk, a_rst,
3942 
    // b side
3943 
    b_d, b_wr, b_fifo_full,
3944 
    b_q, b_rd, b_fifo_empty,
3945 
    b_clk, b_rst
3946 
    );
3947 
 
3948 
parameter data_width = 18;
3949 
parameter addr_width = 4;
3950 
 
3951 
// a side
3952 
input  [data_width-1:0] a_d;
3953 
input                   a_wr;
3954 
output                  a_fifo_full;
3955 
output [data_width-1:0] a_q;
3956 
input                   a_rd;
3957 
output                  a_fifo_empty;
3958 
input                   a_clk;
3959 
input                   a_rst;
3960 
 
3961 
// b side
3962 
input  [data_width-1:0] b_d;
3963 
input                   b_wr;
3964 
output                  b_fifo_full;
3965 
output [data_width-1:0] b_q;
3966 
input                   b_rd;
3967 
output                  b_fifo_empty;
3968 
input                   b_clk;
3969 
input                   b_rst;
3970 
 
3971 
// adr_gen
3972 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
3973 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
3974 
// dpram
3975 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3976 
 
3977 40 unneback 
`define MODULE cnt_gray_ce_bin
3978 
`BASE`MODULE
3979 6 unneback 
    # ( .length(addr_width))
3980 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
3981 
 
3982 40 unneback 
`BASE`MODULE
3983 6 unneback 
    # (.length(addr_width))
3984 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
3985 
 
3986 40 unneback 
`BASE`MODULE
3987 6 unneback 
    # ( .length(addr_width))
3988 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
3989 
 
3990 40 unneback 
`BASE`MODULE
3991 6 unneback 
    # (.length(addr_width))
3992 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
3993 40 unneback 
`undef MODULE
3994 6 unneback 
 
3995 
// mux read or write adr to DPRAM
3996 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
3997 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
3998 
 
3999 40 unneback 
`define MODULE dpram_2r2w
4000 
`BASE`MODULE
4001 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4002 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4003 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4004 40 unneback 
`undef MODULE
4005 6 unneback 
 
4006 40 unneback 
`define MODULE fifo_cmp_async
4007 
`BASE`MODULE
4008 6 unneback 
    # (.addr_width(addr_width))
4009 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4010 
 
4011 40 unneback 
`BASE`MODULE
4012 6 unneback 
    # (.addr_width(addr_width))
4013 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4014 40 unneback 
`undef MODULE
4015 6 unneback 
 
4016 
endmodule
4017 40 unneback 
`endif
4018 12 unneback 
//////////////////////////////////////////////////////////////////////
4019 
////                                                              ////
4020 
////  Versatile library, wishbone stuff                           ////
4021 
////                                                              ////
4022 
////  Description                                                 ////
4023 
////  Wishbone compliant modules                                  ////
4024 
////                                                              ////
4025 
////                                                              ////
4026 
////  To Do:                                                      ////
4027 
////   -                                                          ////
4028 
////                                                              ////
4029 
////  Author(s):                                                  ////
4030 
////      - Michael Unneback, unneback@opencores.org              ////
4031 
////        ORSoC AB                                              ////
4032 
////                                                              ////
4033 
//////////////////////////////////////////////////////////////////////
4034 
////                                                              ////
4035 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4036 
////                                                              ////
4037 
//// This source file may be used and distributed without         ////
4038 
//// restriction provided that this copyright statement is not    ////
4039 
//// removed from the file and that any derivative work contains  ////
4040 
//// the original copyright notice and the associated disclaimer. ////
4041 
////                                                              ////
4042 
//// This source file is free software; you can redistribute it   ////
4043 
//// and/or modify it under the terms of the GNU Lesser General   ////
4044 
//// Public License as published by the Free Software Foundation; ////
4045 
//// either version 2.1 of the License, or (at your option) any   ////
4046 
//// later version.                                               ////
4047 
////                                                              ////
4048 
//// This source is distributed in the hope that it will be       ////
4049 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4050 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4051 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4052 
//// details.                                                     ////
4053 
////                                                              ////
4054 
//// You should have received a copy of the GNU Lesser General    ////
4055 
//// Public License along with this source; if not, download it   ////
4056 
//// from http://www.opencores.org/lgpl.shtml                     ////
4057 
////                                                              ////
4058 
//////////////////////////////////////////////////////////////////////
4059 
 
4060 40 unneback 
`ifdef WB3WB3_BRIDGE
4061 12 unneback 
// async wb3 - wb3 bridge
4062 
`timescale 1ns/1ns
4063 40 unneback 
`define MODULE wb3wb3_bridge
4064 
module `BASE`MODULE (
4065 
`undef MODULE
4066 12 unneback 
        // wishbone slave side
4067 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4068 
        // wishbone master side
4069 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4070 
 
4071 
input [31:0] wbs_dat_i;
4072 
input [31:2] wbs_adr_i;
4073 
input [3:0]  wbs_sel_i;
4074 
input [1:0]  wbs_bte_i;
4075 
input [2:0]  wbs_cti_i;
4076 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4077 
output [31:0] wbs_dat_o;
4078 14 unneback 
output wbs_ack_o;
4079 12 unneback 
input wbs_clk, wbs_rst;
4080 
 
4081 
output [31:0] wbm_dat_o;
4082 
output reg [31:2] wbm_adr_o;
4083 
output [3:0]  wbm_sel_o;
4084 
output reg [1:0]  wbm_bte_o;
4085 
output reg [2:0]  wbm_cti_o;
4086 14 unneback 
output reg wbm_we_o;
4087 
output wbm_cyc_o;
4088 12 unneback 
output wbm_stb_o;
4089 
input [31:0]  wbm_dat_i;
4090 
input wbm_ack_i;
4091 
input wbm_clk, wbm_rst;
4092 
 
4093 
parameter addr_width = 4;
4094 
 
4095 
// bte
4096 
parameter linear       = 2'b00;
4097 
parameter wrap4        = 2'b01;
4098 
parameter wrap8        = 2'b10;
4099 
parameter wrap16       = 2'b11;
4100 
// cti
4101 
parameter classic      = 3'b000;
4102 
parameter incburst     = 3'b010;
4103 
parameter endofburst   = 3'b111;
4104 
 
4105 
parameter wbs_adr  = 1'b0;
4106 
parameter wbs_data = 1'b1;
4107 
 
4108 33 unneback 
parameter wbm_adr0      = 2'b00;
4109 
parameter wbm_adr1      = 2'b01;
4110 
parameter wbm_data      = 2'b10;
4111 
parameter wbm_data_wait = 2'b11;
4112 12 unneback 
 
4113 
reg [1:0] wbs_bte_reg;
4114 
reg wbs;
4115 
wire wbs_eoc_alert, wbm_eoc_alert;
4116 
reg wbs_eoc, wbm_eoc;
4117 
reg [1:0] wbm;
4118 
 
4119 14 unneback 
wire [1:16] wbs_count, wbm_count;
4120 12 unneback 
 
4121 
wire [35:0] a_d, a_q, b_d, b_q;
4122 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4123 
reg a_rd_reg;
4124 
wire b_rd_adr, b_rd_data;
4125 14 unneback 
wire b_rd_data_reg;
4126 
wire [35:0] temp;
4127 12 unneback 
 
4128 
`define WE 5
4129 
`define BTE 4:3
4130 
`define CTI 2:0
4131 
 
4132 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4133 
always @ (posedge wbs_clk or posedge wbs_rst)
4134 
if (wbs_rst)
4135 
        wbs_eoc <= 1'b0;
4136 
else
4137 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4138 
                wbs_eoc <= wbs_bte_i==linear;
4139 
        else if (wbs_eoc_alert & (a_rd | a_wr))
4140 
                wbs_eoc <= 1'b1;
4141 
 
4142 40 unneback 
`define MODULE cnt_shreg_ce_clear
4143 
`BASE`MODULE # ( .length(16))
4144 
`undef MODULE
4145 12 unneback 
    cnt0 (
4146 
        .cke(wbs_ack_o),
4147 
        .clear(wbs_eoc),
4148 
        .q(wbs_count),
4149 
        .rst(wbs_rst),
4150 
        .clk(wbs_clk));
4151 
 
4152 
always @ (posedge wbs_clk or posedge wbs_rst)
4153 
if (wbs_rst)
4154 
        wbs <= wbs_adr;
4155 
else
4156 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
4157 
                wbs <= wbs_data;
4158 
        else if (wbs_eoc & wbs_ack_o)
4159 
                wbs <= wbs_adr;
4160 
 
4161 
// wbs FIFO
4162 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
4163 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
4164 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4165 
              1'b0;
4166 
assign a_rd = !a_fifo_empty;
4167 
always @ (posedge wbs_clk or posedge wbs_rst)
4168 
if (wbs_rst)
4169 
        a_rd_reg <= 1'b0;
4170 
else
4171 
        a_rd_reg <= a_rd;
4172 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4173 
 
4174 
assign wbs_dat_o = a_q[35:4];
4175 
 
4176 
always @ (posedge wbs_clk or posedge wbs_rst)
4177 
if (wbs_rst)
4178 13 unneback 
        wbs_bte_reg <= 2'b00;
4179 12 unneback 
else
4180 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
4181 12 unneback 
 
4182 
// wbm FIFO
4183 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4184 
always @ (posedge wbm_clk or posedge wbm_rst)
4185 
if (wbm_rst)
4186 
        wbm_eoc <= 1'b0;
4187 
else
4188 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4189 
                wbm_eoc <= b_q[`BTE] == linear;
4190 
        else if (wbm_eoc_alert & wbm_ack_i)
4191 
                wbm_eoc <= 1'b1;
4192 
 
4193 
always @ (posedge wbm_clk or posedge wbm_rst)
4194 
if (wbm_rst)
4195 
        wbm <= wbm_adr0;
4196 
else
4197 33 unneback 
/*
4198 12 unneback 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
4199 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
4200 
        (wbm==wbm_adr1 & !wbm_we_o) |
4201 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
4202 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
4203 33 unneback 
*/
4204 
    case (wbm)
4205 
    wbm_adr0:
4206 
        if (!b_fifo_empty)
4207 
            wbm <= wbm_adr1;
4208 
    wbm_adr1:
4209 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
4210 
            wbm <= wbm_data;
4211 
    wbm_data:
4212 
        if (wbm_ack_i & wbm_eoc)
4213 
            wbm <= wbm_adr0;
4214 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
4215 
            wbm <= wbm_data_wait;
4216 
    wbm_data_wait:
4217 
        if (!b_fifo_empty)
4218 
            wbm <= wbm_data;
4219 
    endcase
4220 12 unneback 
 
4221 
assign b_d = {wbm_dat_i,4'b1111};
4222 
assign b_wr = !wbm_we_o & wbm_ack_i;
4223 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
4224 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
4225 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
4226 33 unneback 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
4227 12 unneback 
                   1'b0;
4228 
assign b_rd = b_rd_adr | b_rd_data;
4229 
 
4230 40 unneback 
`define MODULE dff
4231 
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
4232 
`undef MODULE
4233 
`define MODULE dff_ce
4234 
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
4235 
`undef MODULE
4236 12 unneback 
 
4237 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
4238 
 
4239 40 unneback 
`define MODULE cnt_shreg_ce_clear
4240 42 unneback 
`BASE`MODULE # ( .length(16))
4241 40 unneback 
`undef MODULE
4242 12 unneback 
    cnt1 (
4243 
        .cke(wbm_ack_i),
4244 
        .clear(wbm_eoc),
4245 
        .q(wbm_count),
4246 
        .rst(wbm_rst),
4247 
        .clk(wbm_clk));
4248 
 
4249 33 unneback 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
4250 
assign wbm_stb_o = (wbm==wbm_data);
4251 12 unneback 
 
4252 
always @ (posedge wbm_clk or posedge wbm_rst)
4253 
if (wbm_rst)
4254 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
4255 
else begin
4256 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4257 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
4258 
        else if (wbm_eoc_alert & wbm_ack_i)
4259 
                wbm_cti_o <= endofburst;
4260 
end
4261 
 
4262 
//async_fifo_dw_simplex_top
4263 40 unneback 
`define MODULE fifo_2r2w_async_simplex
4264 
`BASE`MODULE
4265 
`undef MODULE
4266 12 unneback 
# ( .data_width(36), .addr_width(addr_width))
4267 
fifo (
4268 
    // a side
4269 
    .a_d(a_d),
4270 
    .a_wr(a_wr),
4271 
    .a_fifo_full(a_fifo_full),
4272 
    .a_q(a_q),
4273 
    .a_rd(a_rd),
4274 
    .a_fifo_empty(a_fifo_empty),
4275 
    .a_clk(wbs_clk),
4276 
    .a_rst(wbs_rst),
4277 
    // b side
4278 
    .b_d(b_d),
4279 
    .b_wr(b_wr),
4280 
    .b_fifo_full(b_fifo_full),
4281 
    .b_q(b_q),
4282 
    .b_rd(b_rd),
4283 
    .b_fifo_empty(b_fifo_empty),
4284 
    .b_clk(wbm_clk),
4285 
    .b_rst(wbm_rst)
4286 
    );
4287 
 
4288 
endmodule
4289 40 unneback 
`undef WE
4290 
`undef BTE
4291 
`undef CTI
4292 
`endif
4293 17 unneback 
 
4294 40 unneback 
`ifdef WB3_ARBITER_TYPE1
4295 
`define MODULE wb3_arbiter_type1
4296 42 unneback 
module `BASE`MODULE (
4297 40 unneback 
`undef MODULE
4298 39 unneback 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
4299 
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
4300 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
4301 
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
4302 
    wb_clk, wb_rst
4303 
);
4304 
 
4305 
parameter nr_of_ports = 3;
4306 
parameter adr_size = 26;
4307 
parameter adr_lo   = 2;
4308 
parameter dat_size = 32;
4309 
parameter sel_size = dat_size/8;
4310 
 
4311 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
4312 
localparam dw = dat_size * nr_of_ports;
4313 
localparam sw = sel_size * nr_of_ports;
4314 
localparam cw = 3 * nr_of_ports;
4315 
localparam bw = 2 * nr_of_ports;
4316 
 
4317 
input  [dw-1:0] wbm_dat_o;
4318 
input  [aw-1:0] wbm_adr_o;
4319 
input  [sw-1:0] wbm_sel_o;
4320 
input  [cw-1:0] wbm_cti_o;
4321 
input  [bw-1:0] wbm_bte_o;
4322 
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
4323 
output [dw-1:0] wbm_dat_i;
4324 
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
4325 
 
4326 
output [dat_size-1:0] wbs_dat_i;
4327 
output [adr_size-1:adr_lo] wbs_adr_i;
4328 
output [sel_size-1:0] wbs_sel_i;
4329 
output [2:0] wbs_cti_i;
4330 
output [1:0] wbs_bte_i;
4331 
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
4332 
input  [dat_size-1:0] wbs_dat_o;
4333 
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
4334 
 
4335 
input wb_clk, wb_rst;
4336 
 
4337 
wire [nr_of_ports-1:0] select;
4338 
wire [nr_of_ports-1:0] state;
4339 
wire [nr_of_ports-1:0] eoc; // end-of-cycle
4340 
wire [nr_of_ports-1:0] sel;
4341 
wire idle;
4342 
 
4343 
genvar i;
4344 
 
4345 
assign idle = !(|state);
4346 
 
4347 
generate
4348 
if (nr_of_ports == 2) begin
4349 
 
4350 
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
4351 
 
4352 
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4353 
 
4354 
    assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : 2'b00;
4355 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4356 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4357 
 
4358 
end
4359 
endgenerate
4360 
 
4361 
generate
4362 
if (nr_of_ports == 3) begin
4363 
 
4364 
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4365 
 
4366 
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4367 
 
4368 
    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : 3'b000;
4369 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4370 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4371 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4372 
 
4373 
end
4374 
endgenerate
4375 
 
4376 
generate
4377 
for (i=0;i<nr_of_ports;i=i+1) begin
4378 42 unneback 
`define MODULE spr
4379 
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
4380 
`undef MODULE
4381 39 unneback 
end
4382 
endgenerate
4383 
 
4384 
    assign sel = select | state;
4385 
 
4386 40 unneback 
`define MODULE mux_andor
4387 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
4388 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
4389 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
4390 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
4391 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
4392 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
4393 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
4394 
`undef MODULE
4395 39 unneback 
    assign wbs_cyc_i = |sel;
4396 
 
4397 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
4398 
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
4399 
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
4400 
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
4401 
 
4402 
endmodule
4403 40 unneback 
`endif
4404 39 unneback 
 
4405 40 unneback 
`ifdef WB_BOOT_ROM
4406 17 unneback 
// WB ROM
4407 40 unneback 
`define MODULE wb_boot_rom
4408 
module `BASE`MODULE (
4409 
`undef MODULE
4410 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
4411 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
4412 17 unneback 
 
4413 18 unneback 
    parameter adr_hi = 31;
4414 
    parameter adr_lo = 28;
4415 
    parameter adr_sel = 4'hf;
4416 
    parameter addr_width = 5;
4417 33 unneback 
/*
4418 17 unneback 
`ifndef BOOT_ROM
4419 
`define BOOT_ROM "boot_rom.v"
4420 
`endif
4421 33 unneback 
*/
4422 18 unneback 
    input [adr_hi:2]    wb_adr_i;
4423 
    input               wb_stb_i;
4424 
    input               wb_cyc_i;
4425 
    output [31:0]        wb_dat_o;
4426 
    output              wb_ack_o;
4427 
    output              hit_o;
4428 
    input               wb_clk;
4429 
    input               wb_rst;
4430 
 
4431 
    wire hit;
4432 
    reg [31:0] wb_dat;
4433 
    reg wb_ack;
4434 
 
4435 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
4436 17 unneback 
 
4437 
always @ (posedge wb_clk or posedge wb_rst)
4438 
    if (wb_rst)
4439 18 unneback 
        wb_dat <= 32'h15000000;
4440 17 unneback 
    else
4441 18 unneback 
         case (wb_adr_i[addr_width-1:2])
4442 33 unneback 
`ifdef BOOT_ROM
4443 17 unneback 
`include `BOOT_ROM
4444 33 unneback 
`endif
4445 17 unneback 
           /*
4446 
            // Zero r0 and jump to 0x00000100
4447 18 unneback 
 
4448 
            1 : wb_dat <= 32'hA8200000;
4449 
            2 : wb_dat <= 32'hA8C00100;
4450 
            3 : wb_dat <= 32'h44003000;
4451 
            4 : wb_dat <= 32'h15000000;
4452 17 unneback 
            */
4453 
           default:
4454 18 unneback 
             wb_dat <= 32'h00000000;
4455 17 unneback 
 
4456 
         endcase // case (wb_adr_i)
4457 
 
4458 
 
4459 
always @ (posedge wb_clk or posedge wb_rst)
4460 
    if (wb_rst)
4461 18 unneback 
        wb_ack <= 1'b0;
4462 17 unneback 
    else
4463 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
4464 17 unneback 
 
4465 18 unneback 
assign hit_o = hit;
4466 
assign wb_dat_o = wb_dat & {32{wb_ack}};
4467 
assign wb_ack_o = wb_ack;
4468 
 
4469 17 unneback 
endmodule
4470 40 unneback 
`endif
4471 32 unneback 
 
4472 40 unneback 
`ifdef WB_DPRAM
4473 
`define MODULE wb_dpram
4474 
module `BASE`MODULE (
4475 
`undef MODULE
4476 32 unneback 
        // wishbone slave side a
4477 
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
4478 
        wbsa_clk, wbsa_rst,
4479 
        // wishbone slave side a
4480 
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
4481 
        wbsb_clk, wbsb_rst);
4482 
 
4483 
parameter data_width = 32;
4484 
parameter addr_width = 8;
4485 
 
4486 
parameter dat_o_mask_a = 1;
4487 
parameter dat_o_mask_b = 1;
4488 
 
4489 
input [31:0] wbsa_dat_i;
4490 
input [addr_width-1:2] wbsa_adr_i;
4491 
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
4492 
output [31:0] wbsa_dat_o;
4493 
output wbsa_ack_o;
4494 
input wbsa_clk, wbsa_rst;
4495 
 
4496 
input [31:0] wbsb_dat_i;
4497 
input [addr_width-1:2] wbsb_adr_i;
4498 
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
4499 
output [31:0] wbsb_dat_o;
4500 
output wbsb_ack_o;
4501 
input wbsb_clk, wbsb_rst;
4502 
 
4503 
wire wbsa_dat_tmp, wbsb_dat_tmp;
4504 
 
4505 40 unneback 
`define MODULE dpram_2r2w
4506 
`BASE`MODULE # (
4507 
`undef MODULE
4508 33 unneback 
    .data_width(data_width), .addr_width(addr_width) )
4509 32 unneback 
dpram0(
4510 
    .d_a(wbsa_dat_i),
4511 
    .q_a(wbsa_dat_tmp),
4512 
    .adr_a(wbsa_adr_i),
4513 
    .we_a(wbsa_we_i),
4514 
    .clk_a(wbsa_clk),
4515 
    .d_b(wbsb_dat_i),
4516 
    .q_b(wbsb_dat_tmp),
4517 
    .adr_b(wbsb_adr_i),
4518 
    .we_b(wbsb_we_i),
4519 
    .clk_b(wbsb_clk) );
4520 
 
4521 33 unneback 
generate if (dat_o_mask_a==1)
4522 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
4523 
endgenerate
4524 33 unneback 
generate if (dat_o_mask_a==0)
4525 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp;
4526 
endgenerate
4527 
 
4528 33 unneback 
generate if (dat_o_mask_b==1)
4529 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
4530 
endgenerate
4531 33 unneback 
generate if (dat_o_mask_b==0)
4532 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp;
4533 
endgenerate
4534 
 
4535 40 unneback 
`define MODULE spr
4536 
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
4537 
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
4538 
`undef MODULE
4539 32 unneback 
 
4540 
endmodule
4541 40 unneback 
`endif
4542 18 unneback 
//////////////////////////////////////////////////////////////////////
4543 
////                                                              ////
4544 
////  Arithmetic functions                                        ////
4545 
////                                                              ////
4546 
////  Description                                                 ////
4547 
////  Arithmetic functions for ALU and DSP                        ////
4548 
////                                                              ////
4549 
////                                                              ////
4550 
////  To Do:                                                      ////
4551 
////   -                                                          ////
4552 
////                                                              ////
4553 
////  Author(s):                                                  ////
4554 
////      - Michael Unneback, unneback@opencores.org              ////
4555 
////        ORSoC AB                                              ////
4556 
////                                                              ////
4557 
//////////////////////////////////////////////////////////////////////
4558 
////                                                              ////
4559 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4560 
////                                                              ////
4561 
//// This source file may be used and distributed without         ////
4562 
//// restriction provided that this copyright statement is not    ////
4563 
//// removed from the file and that any derivative work contains  ////
4564 
//// the original copyright notice and the associated disclaimer. ////
4565 
////                                                              ////
4566 
//// This source file is free software; you can redistribute it   ////
4567 
//// and/or modify it under the terms of the GNU Lesser General   ////
4568 
//// Public License as published by the Free Software Foundation; ////
4569 
//// either version 2.1 of the License, or (at your option) any   ////
4570 
//// later version.                                               ////
4571 
////                                                              ////
4572 
//// This source is distributed in the hope that it will be       ////
4573 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4574 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4575 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4576 
//// details.                                                     ////
4577 
////                                                              ////
4578 
//// You should have received a copy of the GNU Lesser General    ////
4579 
//// Public License along with this source; if not, download it   ////
4580 
//// from http://www.opencores.org/lgpl.shtml                     ////
4581 
////                                                              ////
4582 
//////////////////////////////////////////////////////////////////////
4583 
 
4584 40 unneback 
`ifdef MULTS
4585 18 unneback 
// signed multiplication
4586 40 unneback 
`define MODULE mults
4587 
module `BASE`MODULE (a,b,p);
4588 
`undef MODULE
4589 18 unneback 
parameter operand_a_width = 18;
4590 
parameter operand_b_width = 18;
4591 
parameter result_hi = 35;
4592 
parameter result_lo = 0;
4593 
input [operand_a_width-1:0] a;
4594 
input [operand_b_width-1:0] b;
4595 
output [result_hi:result_lo] p;
4596 
wire signed [operand_a_width-1:0] ai;
4597 
wire signed [operand_b_width-1:0] bi;
4598 
wire signed [operand_a_width+operand_b_width-1:0] result;
4599 
 
4600 
    assign ai = a;
4601 
    assign bi = b;
4602 
    assign result = ai * bi;
4603 
    assign p = result[result_hi:result_lo];
4604 
 
4605 
endmodule
4606 40 unneback 
`endif
4607 
`ifdef MULTS18X18
4608 
`define MODULE mults18x18
4609 
module `BASE`MODULE (a,b,p);
4610 
`undef MODULE
4611 18 unneback 
input [17:0] a,b;
4612 
output [35:0] p;
4613 
vl_mult
4614 
    # (.operand_a_width(18), .operand_b_width(18))
4615 
    mult0 (.a(a), .b(b), .p(p));
4616 
endmodule
4617 40 unneback 
`endif
4618 18 unneback 
 
4619 40 unneback 
`ifdef MULT
4620 
`define MODULE mult
4621 18 unneback 
// unsigned multiplication
4622 40 unneback 
module `BASE`MODULE (a,b,p);
4623 
`undef MODULE
4624 18 unneback 
parameter operand_a_width = 18;
4625 
parameter operand_b_width = 18;
4626 
parameter result_hi = 35;
4627 
parameter result_lo = 0;
4628 
input [operand_a_width-1:0] a;
4629 
input [operand_b_width-1:0] b;
4630 
output [result_hi:result_hi] p;
4631 
 
4632 
wire [operand_a_width+operand_b_width-1:0] result;
4633 
 
4634 
    assign result = a * b;
4635 
    assign p = result[result_hi:result_lo];
4636 
 
4637 
endmodule
4638 40 unneback 
`endif
4639 18 unneback 
 
4640 40 unneback 
`ifdef SHIFT_UNIT_32
4641 
`define MODULE shift_unit_32
4642 18 unneback 
// shift unit
4643 
// supporting the following shift functions
4644 
//   SLL
4645 
//   SRL
4646 
//   SRA
4647 
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
4648 40 unneback 
module `BASE`MODULE( din, s, dout, opcode);
4649 
`undef MODULE
4650 18 unneback 
input [31:0] din; // data in operand
4651 
input [4:0] s; // shift operand
4652 
input [1:0] opcode;
4653 
output [31:0] dout;
4654 
 
4655 
parameter opcode_sll = 2'b00;
4656 
//parameter opcode_srl = 2'b01;
4657 
parameter opcode_sra = 2'b10;
4658 
//parameter opcode_ror = 2'b11;
4659 
 
4660 
wire sll, sra;
4661 
assign sll = opcode == opcode_sll;
4662 
assign sra = opcode == opcode_sra;
4663 
 
4664 
wire [15:1] s1;
4665 
wire [3:0] sign;
4666 
wire [7:0] tmp [0:3];
4667 
 
4668 
// first stage is multiplier based
4669 
// shift operand as fractional 8.7
4670 
assign s1[15] = sll & s[2:0]==3'd7;
4671 
assign s1[14] = sll & s[2:0]==3'd6;
4672 
assign s1[13] = sll & s[2:0]==3'd5;
4673 
assign s1[12] = sll & s[2:0]==3'd4;
4674 
assign s1[11] = sll & s[2:0]==3'd3;
4675 
assign s1[10] = sll & s[2:0]==3'd2;
4676 
assign s1[ 9] = sll & s[2:0]==3'd1;
4677 
assign s1[ 8] = s[2:0]==3'd0;
4678 
assign s1[ 7] = !sll & s[2:0]==3'd1;
4679 
assign s1[ 6] = !sll & s[2:0]==3'd2;
4680 
assign s1[ 5] = !sll & s[2:0]==3'd3;
4681 
assign s1[ 4] = !sll & s[2:0]==3'd4;
4682 
assign s1[ 3] = !sll & s[2:0]==3'd5;
4683 
assign s1[ 2] = !sll & s[2:0]==3'd6;
4684 
assign s1[ 1] = !sll & s[2:0]==3'd7;
4685 
 
4686 
assign sign[3] = din[31] & sra;
4687 
assign sign[2] = sign[3] & (&din[31:24]);
4688 
assign sign[1] = sign[2] & (&din[23:16]);
4689 
assign sign[0] = sign[1] & (&din[15:8]);
4690 40 unneback 
`define MODULE mults
4691 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
4692 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
4693 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
4694 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
4695 
`undef MODULE
4696 18 unneback 
// second stage is multiplexer based
4697 
// shift on byte level
4698 
 
4699 
// mux byte 3
4700 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
4701 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
4702 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
4703 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
4704 
                     {8{sign[3]}};
4705 
 
4706 
// mux byte 2
4707 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
4708 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
4709 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
4710 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
4711 
                     (s[4:3]==2'b01) ? tmp[3] :
4712 
                     {8{sign[3]}};
4713 
 
4714 
// mux byte 1
4715 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
4716 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
4717 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
4718 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
4719 
                     (s[4:3]==2'b01) ? tmp[2] :
4720 
                     (s[4:3]==2'b10) ? tmp[3] :
4721 
                     {8{sign[3]}};
4722 
 
4723 
// mux byte 0
4724 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
4725 
                     (sll) ?  {8{1'b0}}:
4726 
                     (s[4:3]==2'b01) ? tmp[1] :
4727 
                     (s[4:3]==2'b10) ? tmp[2] :
4728 
                     tmp[3];
4729 
 
4730 
endmodule
4731 40 unneback 
`endif
4732 18 unneback 
 
4733 40 unneback 
`ifdef LOGIC_UNIT
4734 18 unneback 
// logic unit
4735 
// supporting the following logic functions
4736 
//    a and b
4737 
//    a or  b
4738 
//    a xor b
4739 
//    not b
4740 40 unneback 
`define MODULE logic_unit
4741 
module `BASE`MODULE( a, b, result, opcode);
4742 
`undef MODULE
4743 18 unneback 
parameter width = 32;
4744 
parameter opcode_and = 2'b00;
4745 
parameter opcode_or  = 2'b01;
4746 
parameter opcode_xor = 2'b10;
4747 
input [width-1:0] a,b;
4748 
output [width-1:0] result;
4749 
input [1:0] opcode;
4750 
 
4751 
assign result = (opcode==opcode_and) ? a & b :
4752 
                (opcode==opcode_or)  ? a | b :
4753 
                (opcode==opcode_xor) ? a ^ b :
4754 
                b;
4755 
 
4756 
endmodule
4757 
 
4758 
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
4759 
parameter width = 32;
4760 
parameter opcode_add = 1'b0;
4761 
parameter opcode_sub = 1'b1;
4762 
input [width-1:0] a,b;
4763 
input c_in, add_sub, sign;
4764 
output [width-1:0] result;
4765 
output c_out, z, ovfl;
4766 
 
4767 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
4768 
assign z = (result=={width{1'b0}});
4769 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
4770 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
4771 
endmodule
4772 40 unneback 
`endif

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