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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 43

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5
`ifdef ALL
6
 
7
`define GBUF
8
`define SYNC_RST
9
`define PLL
10
 
11
`define MULTS
12
`define MULTS18X18
13
`define MULT
14
`define SHIFT_UNIT_32
15
`define LOGIC_UNIT
16
 
17
`define CNT_SHREG_WRAP
18
`define CNT_SHREG_CE_WRAP
19
`define CNT_SHREG_CE_CLEAR
20
`define CNT_SHREG_CE_CLEAR_WRAP
21
 
22
`define MUX_ANDOR
23
`define MUX2_ANDOR
24
`define MUX3_ANDOR
25
`define MUX4_ANDOR
26
`define MUX5_ANDOR
27
`define MUX6_ANDOR
28 43 unneback
`define PARITY
29 40 unneback
 
30
`define ROM_INIT
31
`define RAM
32
`define RAM_BE
33
`define DPRAM_1R1W
34
`define DPRAM_2R1W
35
`define DPRAM_2R2W
36
`define FIFO_1R1W_FILL_LEVEL_SYNC
37
`define FIFO_2R2W_SYNC_SIMPLEX
38
`define FIFO_CMP_ASYNC
39
`define FIFO_1R1W_ASYNC
40
`define FIFO_2R2W_ASYNC
41
`define FIFO_2R2W_ASYNC_SIMPLEX
42
 
43
`define DFF
44
`define DFF_ARRAY
45
`define DFF_CE
46
`define DFF_CE_CLEAR
47
`define DF_CE_SET
48
`define SPR
49
`define SRP
50
`define DFF_SR
51
`define LATCH
52
`define SHREG
53
`define SHREG_CE
54
`define DELAY
55
`define DELAY_EMPTYFLAG
56
 
57
`define WB3WB3_BRIDGE
58
`define WB3_ARBITER_TYPE1
59
`define WB_BOOT_ROM
60
`define WB_DPRAM
61
 
62
`endif
63
 
64
`ifdef PLL
65
`ifndef SYNC_RST
66
`define SYNC_RST
67
`endif
68
`endif
69
 
70
`ifdef SYNC_RST
71
`ifndef GBUF
72
`define GBUF
73
`endif
74
`endif
75
 
76
`ifdef WB_DPRAM
77
`ifndef DPRAM_2R2W
78
`define DPRAM_2R2W
79
`endif
80
`ifndef SPR
81
`define SPR
82
`endif
83
`endif
84
 
85
`ifdef WB3_ARBITER_TYPE1
86 42 unneback
`ifndef SPR
87
`define SPR
88
`endif
89 40 unneback
`ifndef MUX_ANDOR
90
`define MUX_ANDOR
91
`endif
92
`endif
93
 
94
`ifdef WB3WB3_BRIDGE
95
`ifndef CNT_SHREG_CE_CLEAR
96
`define CNT_SHREG_CE_CLEAR
97
`endif
98
`ifndef DFF
99
`define DFF
100
`endif
101
`ifndef DFF_CE
102
`define DFF_CE
103
`endif
104
`ifndef CNT_SHREG_CE_CLEAR
105
`define CNT_SHREG_CE_CLEAR
106
`endif
107
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
108
`define FIFO_2R2W_ASYNC_SIMPLEX
109
`endif
110
`endif
111
 
112
`ifdef MULTS18X18
113
`ifndef MULTS
114
`define MULTS
115
`endif
116
`endif
117
 
118
`ifdef SHIFT_UNIT_32
119
`ifndef MULTS
120
`define MULTS
121
`endif
122
`endif
123
 
124
`ifdef MUX2_ANDOR
125
`ifndef MUX_ANDOR
126
`define MUX_ANDOR
127
`endif
128
`endif
129
 
130
`ifdef MUX3_ANDOR
131
`ifndef MUX_ANDOR
132
`define MUX_ANDOR
133
`endif
134
`endif
135
 
136
`ifdef MUX4_ANDOR
137
`ifndef MUX_ANDOR
138
`define MUX_ANDOR
139
`endif
140
`endif
141
 
142
`ifdef MUX5_ANDOR
143
`ifndef MUX_ANDOR
144
`define MUX_ANDOR
145
`endif
146
`endif
147
 
148
`ifdef MUX6_ANDOR
149
`ifndef MUX_ANDOR
150
`define MUX_ANDOR
151
`endif
152
`endif
153
 
154
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
155
`ifndef CNT_BIN_CE
156
`define CNT_BIN_CE
157
`endif
158
`ifndef DPRAM_1R1W
159
`define DPRAM_1R1W
160
`endif
161
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
162
`define CNT_BIN_CE_REW_Q_ZQ_L1
163
`endif
164
`endif
165
 
166
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
167
`ifndef CNT_LFSR_CE
168
`define CNT_LFSR_CE
169
`endif
170
`ifndef DPRAM_2R2W
171
`define DPRAM_2R2W
172
`endif
173
`ifndef CNT_BIN_CE_REW_ZQ_L1
174
`define CNT_BIN_CE_REW_ZQ_L1
175
`endif
176
`endif
177
 
178
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
179
`ifndef CNT_GRAY_CE_BIN
180
`define CNT_GRAY_CE_BIN
181
`endif
182
`ifndef DPRAM_2R2W
183
`define DPRAM_2R2W
184
`endif
185
`ifndef FIFO_CMP_ASYNC
186
`define FIFO_CMP_ASYNC
187
`endif
188
`endif
189
 
190
`ifdef FIFO_2R2W_ASYNC
191
`ifndef FIFO_1R1W_ASYNC
192
`define FIFO_1R1W_ASYNC
193
`endif
194
`endif
195
 
196
`ifdef FIFO_1R1W_ASYNC
197
`ifndef CNT_GRAY_CE_BIN
198
`define CNT_GRAY_CE_BIN
199
`endif
200
`ifndef DPRAM_1R1W
201
`define DPRAM_1R1W
202
`endif
203
`ifndef FIFO_CMP_ASYNC
204
`define FIFO_CMP_ASYNC
205
`endif
206
`endif
207
 
208
`ifdef FIFO_CMP_ASYNC
209
`ifndef DFF_SR
210
`define DFF_SR
211
`endif
212
`ifndef DFF
213
`define DFF
214
`endif
215
`endif
216 6 unneback
//////////////////////////////////////////////////////////////////////
217
////                                                              ////
218
////  Versatile library, clock and reset                          ////
219
////                                                              ////
220
////  Description                                                 ////
221
////  Logic related to clock and reset                            ////
222
////                                                              ////
223
////                                                              ////
224
////  To Do:                                                      ////
225
////   - add more different registers                             ////
226
////                                                              ////
227
////  Author(s):                                                  ////
228
////      - Michael Unneback, unneback@opencores.org              ////
229
////        ORSoC AB                                              ////
230
////                                                              ////
231
//////////////////////////////////////////////////////////////////////
232
////                                                              ////
233
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
234
////                                                              ////
235
//// This source file may be used and distributed without         ////
236
//// restriction provided that this copyright statement is not    ////
237
//// removed from the file and that any derivative work contains  ////
238
//// the original copyright notice and the associated disclaimer. ////
239
////                                                              ////
240
//// This source file is free software; you can redistribute it   ////
241
//// and/or modify it under the terms of the GNU Lesser General   ////
242
//// Public License as published by the Free Software Foundation; ////
243
//// either version 2.1 of the License, or (at your option) any   ////
244
//// later version.                                               ////
245
////                                                              ////
246
//// This source is distributed in the hope that it will be       ////
247
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
248
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
249
//// PURPOSE.  See the GNU Lesser General Public License for more ////
250
//// details.                                                     ////
251
////                                                              ////
252
//// You should have received a copy of the GNU Lesser General    ////
253
//// Public License along with this source; if not, download it   ////
254
//// from http://www.opencores.org/lgpl.shtml                     ////
255
////                                                              ////
256
//////////////////////////////////////////////////////////////////////
257
 
258
// Global buffer
259
// usage:
260
// use to enable global buffers for high fan out signals such as clock and reset
261
 
262
`ifdef ACTEL
263 40 unneback
`ifdef GBUF
264 6 unneback
`timescale 1 ns/100 ps
265
// Version: 8.4 8.4.0.33
266
module gbuf(GL,CLK);
267
output GL;
268
input  CLK;
269
 
270
    wire GND;
271
 
272
    GND GND_1_net(.Y(GND));
273
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
274
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
275
 
276
endmodule
277
`timescale 1 ns/1 ns
278 40 unneback
`define MODULE gbuf
279
module `BASE`MODULE ( i, o);
280
`undef MODULE
281 6 unneback
input i;
282
output o;
283
`ifdef SIM_GBUF
284
assign o=i;
285
`else
286
gbuf gbuf_i0 ( .CLK(i), .GL(o));
287
`endif
288
endmodule
289 40 unneback
`endif
290 33 unneback
 
291 6 unneback
`else
292 33 unneback
 
293 40 unneback
`ifdef ALTERA
294
`ifdef GBUF
295 21 unneback
//altera
296 40 unneback
`define MODULE gbuf
297
module `BASE`MODULE ( i, o);
298
`undef MODULE
299 33 unneback
input i;
300
output o;
301
assign o = i;
302
endmodule
303 40 unneback
`endif
304 33 unneback
 
305 6 unneback
`else
306
 
307 40 unneback
`ifdef GBUF
308 6 unneback
`timescale 1 ns/100 ps
309 40 unneback
`define MODULE
310
module `BASE`MODULE ( i, o);
311
`undef MODULE
312 6 unneback
input i;
313
output o;
314
assign o = i;
315
endmodule
316 40 unneback
`endif
317 6 unneback
`endif // ALTERA
318
`endif //ACTEL
319
 
320 40 unneback
`ifdef SYNC_RST
321 6 unneback
// sync reset
322 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
323 6 unneback
// output active high global reset sync with two DFFs 
324
`timescale 1 ns/100 ps
325 40 unneback
`define MODULE sync_rst
326
module `BASE`MODULE ( rst_n_i, rst_o, clk);
327
`undef MODULE
328 6 unneback
input rst_n_i, clk;
329
output rst_o;
330 18 unneback
reg [1:0] tmp;
331 6 unneback
always @ (posedge clk or negedge rst_n_i)
332
if (!rst_n_i)
333 17 unneback
        tmp <= 2'b11;
334 6 unneback
else
335 33 unneback
        tmp <= {1'b0,tmp[1]};
336 40 unneback
`define MODULE gbuf
337
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
338
`undef MODULE
339 6 unneback
endmodule
340 40 unneback
`endif
341 6 unneback
 
342 40 unneback
`ifdef PLL
343 6 unneback
// vl_pll
344
`ifdef ACTEL
345 32 unneback
///////////////////////////////////////////////////////////////////////////////
346 17 unneback
`timescale 1 ps/1 ps
347 40 unneback
`define MODULE pll
348
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
349
`undef MODULE
350 6 unneback
parameter index = 0;
351
parameter number_of_clk = 1;
352 17 unneback
parameter period_time_0 = 20000;
353
parameter period_time_1 = 20000;
354
parameter period_time_2 = 20000;
355
parameter lock_delay = 2000000;
356 6 unneback
input clk_i, rst_n_i;
357
output lock;
358
output reg [0:number_of_clk-1] clk_o;
359
output [0:number_of_clk-1] rst_o;
360
 
361
`ifdef SIM_PLL
362
 
363
always
364
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
365
 
366
generate if (number_of_clk > 1)
367
always
368
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
369
endgenerate
370
 
371
generate if (number_of_clk > 2)
372
always
373
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
374
endgenerate
375
 
376
genvar i;
377
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
378
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
379
end
380
endgenerate
381
 
382
assign #lock_delay lock = rst_n_i;
383
 
384
endmodule
385
`else
386
generate if (number_of_clk==1 & index==0) begin
387
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
388
end
389
endgenerate // index==0
390
generate if (number_of_clk==1 & index==1) begin
391
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
392
end
393
endgenerate // index==1
394
generate if (number_of_clk==1 & index==2) begin
395
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
396
end
397
endgenerate // index==2
398
generate if (number_of_clk==1 & index==3) begin
399
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
400
end
401
endgenerate // index==0
402
 
403
generate if (number_of_clk==2 & index==0) begin
404
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
405
end
406
endgenerate // index==0
407
generate if (number_of_clk==2 & index==1) begin
408
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
409
end
410
endgenerate // index==1
411
generate if (number_of_clk==2 & index==2) begin
412
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
413
end
414
endgenerate // index==2
415
generate if (number_of_clk==2 & index==3) begin
416
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
417
end
418
endgenerate // index==0
419
 
420
generate if (number_of_clk==3 & index==0) begin
421
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
422
end
423
endgenerate // index==0
424
generate if (number_of_clk==3 & index==1) begin
425
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
426
end
427
endgenerate // index==1
428
generate if (number_of_clk==3 & index==2) begin
429
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
430
end
431
endgenerate // index==2
432
generate if (number_of_clk==3 & index==3) begin
433
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
434
end
435
endgenerate // index==0
436
 
437
genvar i;
438
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
439 40 unneback
`define MODULE sync_rst
440
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
441
`undef MODULE
442 6 unneback
end
443
endgenerate
444
endmodule
445
`endif
446 32 unneback
///////////////////////////////////////////////////////////////////////////////
447 6 unneback
 
448
`else
449
 
450 32 unneback
///////////////////////////////////////////////////////////////////////////////
451 6 unneback
`ifdef ALTERA
452
 
453 32 unneback
`timescale 1 ps/1 ps
454 40 unneback
`define MODULE pll
455
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
456
`undef MODULE
457 32 unneback
parameter index = 0;
458
parameter number_of_clk = 1;
459
parameter period_time_0 = 20000;
460
parameter period_time_1 = 20000;
461
parameter period_time_2 = 20000;
462
parameter period_time_3 = 20000;
463
parameter period_time_4 = 20000;
464
parameter lock_delay = 2000000;
465
input clk_i, rst_n_i;
466
output lock;
467
output reg [0:number_of_clk-1] clk_o;
468
output [0:number_of_clk-1] rst_o;
469
 
470
`ifdef SIM_PLL
471
 
472
always
473
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
474
 
475
generate if (number_of_clk > 1)
476
always
477
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
478
endgenerate
479
 
480
generate if (number_of_clk > 2)
481
always
482
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
483
endgenerate
484
 
485 33 unneback
generate if (number_of_clk > 3)
486 32 unneback
always
487
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
488
endgenerate
489
 
490 33 unneback
generate if (number_of_clk > 4)
491 32 unneback
always
492
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
493
endgenerate
494
 
495
genvar i;
496
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
497
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
498
end
499
endgenerate
500
 
501 33 unneback
//assign #lock_delay lock = rst_n_i;
502
assign lock = rst_n_i;
503 32 unneback
 
504
endmodule
505 6 unneback
`else
506
 
507 33 unneback
`ifdef VL_PLL0
508
`ifdef VL_PLL0_CLK1
509
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
510
`endif
511
`ifdef VL_PLL0_CLK2
512
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
513
`endif
514
`ifdef VL_PLL0_CLK3
515
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
516
`endif
517
`ifdef VL_PLL0_CLK4
518
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
519
`endif
520
`ifdef VL_PLL0_CLK5
521
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
522
`endif
523
`endif
524 32 unneback
 
525 33 unneback
`ifdef VL_PLL1
526
`ifdef VL_PLL1_CLK1
527
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
528
`endif
529
`ifdef VL_PLL1_CLK2
530
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
531
`endif
532
`ifdef VL_PLL1_CLK3
533
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
534
`endif
535
`ifdef VL_PLL1_CLK4
536
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
537
`endif
538
`ifdef VL_PLL1_CLK5
539
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
540
`endif
541
`endif
542 32 unneback
 
543 33 unneback
`ifdef VL_PLL2
544
`ifdef VL_PLL2_CLK1
545
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
546
`endif
547
`ifdef VL_PLL2_CLK2
548
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
549
`endif
550
`ifdef VL_PLL2_CLK3
551
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
552
`endif
553
`ifdef VL_PLL2_CLK4
554
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
555
`endif
556
`ifdef VL_PLL2_CLK5
557
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
558
`endif
559
`endif
560 32 unneback
 
561 33 unneback
`ifdef VL_PLL3
562
`ifdef VL_PLL3_CLK1
563
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
564
`endif
565
`ifdef VL_PLL3_CLK2
566
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
567
`endif
568
`ifdef VL_PLL3_CLK3
569
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
570
`endif
571
`ifdef VL_PLL3_CLK4
572
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
573
`endif
574
`ifdef VL_PLL3_CLK5
575
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
576
`endif
577
`endif
578 32 unneback
 
579
genvar i;
580
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
581 40 unneback
`define MODULE sync_rst
582
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
583
`undef MODULE
584 32 unneback
end
585
endgenerate
586
endmodule
587
`endif
588
///////////////////////////////////////////////////////////////////////////////
589
 
590
`else
591
 
592 6 unneback
// generic PLL
593 17 unneback
`timescale 1 ps/1 ps
594 40 unneback
`define MODULE pll
595
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
596
`undef MODULE
597 6 unneback
parameter index = 0;
598
parameter number_of_clk = 1;
599 17 unneback
parameter period_time_0 = 20000;
600
parameter period_time_1 = 20000;
601
parameter period_time_2 = 20000;
602 6 unneback
parameter lock_delay = 2000;
603
input clk_i, rst_n_i;
604
output lock;
605
output reg [0:number_of_clk-1] clk_o;
606
output [0:number_of_clk-1] rst_o;
607
 
608
always
609
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
610
 
611
generate if (number_of_clk > 1)
612
always
613
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
614
endgenerate
615
 
616
generate if (number_of_clk > 2)
617
always
618
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
619
endgenerate
620
 
621
genvar i;
622
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
623 40 unneback
`define MODULE sync_rst
624
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
625
`undef MODULE
626 6 unneback
end
627
endgenerate
628
 
629
assign #lock_delay lock = rst_n_i;
630
 
631
endmodule
632
 
633
`endif //altera
634 17 unneback
`endif //actel
635 40 unneback
`undef MODULE
636
`endif//////////////////////////////////////////////////////////////////////
637 6 unneback
////                                                              ////
638
////  Versatile library, registers                                ////
639
////                                                              ////
640
////  Description                                                 ////
641
////  Different type of registers                                 ////
642
////                                                              ////
643
////                                                              ////
644
////  To Do:                                                      ////
645
////   - add more different registers                             ////
646
////                                                              ////
647
////  Author(s):                                                  ////
648
////      - Michael Unneback, unneback@opencores.org              ////
649
////        ORSoC AB                                              ////
650
////                                                              ////
651
//////////////////////////////////////////////////////////////////////
652
////                                                              ////
653
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
654
////                                                              ////
655
//// This source file may be used and distributed without         ////
656
//// restriction provided that this copyright statement is not    ////
657
//// removed from the file and that any derivative work contains  ////
658
//// the original copyright notice and the associated disclaimer. ////
659
////                                                              ////
660
//// This source file is free software; you can redistribute it   ////
661
//// and/or modify it under the terms of the GNU Lesser General   ////
662
//// Public License as published by the Free Software Foundation; ////
663
//// either version 2.1 of the License, or (at your option) any   ////
664
//// later version.                                               ////
665
////                                                              ////
666
//// This source is distributed in the hope that it will be       ////
667
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
668
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
669
//// PURPOSE.  See the GNU Lesser General Public License for more ////
670
//// details.                                                     ////
671
////                                                              ////
672
//// You should have received a copy of the GNU Lesser General    ////
673
//// Public License along with this source; if not, download it   ////
674
//// from http://www.opencores.org/lgpl.shtml                     ////
675
////                                                              ////
676
//////////////////////////////////////////////////////////////////////
677
 
678 40 unneback
`ifdef DFF
679
`define MODULE dff
680
module `BASE`MODULE ( d, q, clk, rst);
681
`undef MODULE
682 6 unneback
        parameter width = 1;
683
        parameter reset_value = 0;
684
 
685
        input [width-1:0] d;
686
        input clk, rst;
687
        output reg [width-1:0] q;
688
 
689
        always @ (posedge clk or posedge rst)
690
        if (rst)
691
                q <= reset_value;
692
        else
693
                q <= d;
694
 
695
endmodule
696 40 unneback
`endif
697 6 unneback
 
698 40 unneback
`ifdef DFF_ARRAY
699
`define MODULE dff_array
700
module `BASE`MODULE ( d, q, clk, rst);
701
`undef MODULE
702 6 unneback
 
703
        parameter width = 1;
704
        parameter depth = 2;
705
        parameter reset_value = 1'b0;
706
 
707
        input [width-1:0] d;
708
        input clk, rst;
709
        output [width-1:0] q;
710
        reg  [0:depth-1] q_tmp [width-1:0];
711
        integer i;
712
        always @ (posedge clk or posedge rst)
713
        if (rst) begin
714
            for (i=0;i<depth;i=i+1)
715
                q_tmp[i] <= {width{reset_value}};
716
        end else begin
717
            q_tmp[0] <= d;
718
            for (i=1;i<depth;i=i+1)
719
                q_tmp[i] <= q_tmp[i-1];
720
        end
721
 
722
    assign q = q_tmp[depth-1];
723
 
724
endmodule
725 40 unneback
`endif
726 6 unneback
 
727 40 unneback
`ifdef DFF_CE
728
`define MODULE dff_ce
729
module `BASE`MODULE ( d, ce, q, clk, rst);
730
`undef MODULE
731 6 unneback
 
732
        parameter width = 1;
733
        parameter reset_value = 0;
734
 
735
        input [width-1:0] d;
736
        input ce, clk, rst;
737
        output reg [width-1:0] q;
738
 
739
        always @ (posedge clk or posedge rst)
740
        if (rst)
741
                q <= reset_value;
742
        else
743
                if (ce)
744
                        q <= d;
745
 
746
endmodule
747 40 unneback
`endif
748 6 unneback
 
749 40 unneback
`ifdef DFF_CE_CLEAR
750
`define MODULE dff_ce_clear
751
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
752
`undef MODULE
753 8 unneback
 
754
        parameter width = 1;
755
        parameter reset_value = 0;
756
 
757
        input [width-1:0] d;
758 10 unneback
        input ce, clear, clk, rst;
759 8 unneback
        output reg [width-1:0] q;
760
 
761
        always @ (posedge clk or posedge rst)
762
        if (rst)
763
            q <= reset_value;
764
        else
765
            if (ce)
766
                if (clear)
767
                    q <= {width{1'b0}};
768
                else
769
                    q <= d;
770
 
771
endmodule
772 40 unneback
`endif
773 8 unneback
 
774 40 unneback
`ifdef DF_CE_SET
775
`define MODULE dff_ce_set
776
module `BASE`MODULE ( d, ce, set, q, clk, rst);
777
`undef MODULE
778 24 unneback
 
779
        parameter width = 1;
780
        parameter reset_value = 0;
781
 
782
        input [width-1:0] d;
783
        input ce, set, clk, rst;
784
        output reg [width-1:0] q;
785
 
786
        always @ (posedge clk or posedge rst)
787
        if (rst)
788
            q <= reset_value;
789
        else
790
            if (ce)
791
                if (set)
792
                    q <= {width{1'b1}};
793
                else
794
                    q <= d;
795
 
796
endmodule
797 40 unneback
`endif
798 24 unneback
 
799 40 unneback
`ifdef SPR
800
`define MODULE spr
801
module `BASE`MODULE ( sp, r, q, clk, rst);
802
`undef MODULE
803
 
804 29 unneback
        parameter width = 1;
805
        parameter reset_value = 0;
806
 
807
        input sp, r;
808
        output reg q;
809
        input clk, rst;
810
 
811
        always @ (posedge clk or posedge rst)
812
        if (rst)
813
            q <= reset_value;
814
        else
815
            if (sp)
816
                q <= 1'b1;
817
            else if (r)
818
                q <= 1'b0;
819
 
820
endmodule
821 40 unneback
`endif
822 29 unneback
 
823 40 unneback
`ifdef SRP
824
`define MODULE srp
825
module `BASE`MODULE ( s, rp, q, clk, rst);
826
`undef MODULE
827
 
828 29 unneback
        parameter width = 1;
829
        parameter reset_value = 0;
830
 
831
        input s, rp;
832
        output reg q;
833
        input clk, rst;
834
 
835
        always @ (posedge clk or posedge rst)
836
        if (rst)
837
            q <= reset_value;
838
        else
839
            if (rp)
840
                q <= 1'b0;
841
            else if (s)
842
                q <= 1'b1;
843
 
844
endmodule
845 40 unneback
`endif
846 29 unneback
 
847 40 unneback
`ifdef ALTERA
848 29 unneback
 
849 40 unneback
`ifdef DFF_SR
850 6 unneback
// megafunction wizard: %LPM_FF%
851
// GENERATION: STANDARD
852
// VERSION: WM1.0
853
// MODULE: lpm_ff 
854
 
855
// ============================================================
856
// File Name: dff_sr.v
857
// Megafunction Name(s):
858
//                      lpm_ff
859
//
860
// Simulation Library Files(s):
861
//                      lpm
862
// ============================================================
863
// ************************************************************
864
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
865
//
866
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
867
// ************************************************************
868
 
869
 
870
//Copyright (C) 1991-2010 Altera Corporation
871
//Your use of Altera Corporation's design tools, logic functions 
872
//and other software and tools, and its AMPP partner logic 
873
//functions, and any output files from any of the foregoing 
874
//(including device programming or simulation files), and any 
875
//associated documentation or information are expressly subject 
876
//to the terms and conditions of the Altera Program License 
877
//Subscription Agreement, Altera MegaCore Function License 
878
//Agreement, or other applicable license agreement, including, 
879
//without limitation, that your use is for the sole purpose of 
880
//programming logic devices manufactured by Altera and sold by 
881
//Altera or its authorized distributors.  Please refer to the 
882
//applicable agreement for further details.
883
 
884
 
885
// synopsys translate_off
886
`timescale 1 ps / 1 ps
887
// synopsys translate_on
888 40 unneback
`define MODULE dff_sr
889
module `BASE`MODULE (
890
`undef MODULE
891
 
892 6 unneback
        aclr,
893
        aset,
894
        clock,
895
        data,
896
        q);
897
 
898
        input     aclr;
899
        input     aset;
900
        input     clock;
901
        input     data;
902
        output    q;
903
 
904
        wire [0:0] sub_wire0;
905
        wire [0:0] sub_wire1 = sub_wire0[0:0];
906
        wire  q = sub_wire1;
907
        wire  sub_wire2 = data;
908
        wire  sub_wire3 = sub_wire2;
909
 
910
        lpm_ff  lpm_ff_component (
911
                                .aclr (aclr),
912
                                .clock (clock),
913
                                .data (sub_wire3),
914
                                .aset (aset),
915
                                .q (sub_wire0)
916
                                // synopsys translate_off
917
                                ,
918
                                .aload (),
919
                                .enable (),
920
                                .sclr (),
921
                                .sload (),
922
                                .sset ()
923
                                // synopsys translate_on
924
                                );
925
        defparam
926
                lpm_ff_component.lpm_fftype = "DFF",
927
                lpm_ff_component.lpm_type = "LPM_FF",
928
                lpm_ff_component.lpm_width = 1;
929
 
930
 
931
endmodule
932
 
933
// ============================================================
934
// CNX file retrieval info
935
// ============================================================
936
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
937
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
938
// Retrieval info: PRIVATE: ASET NUMERIC "1"
939
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
940
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
941
// Retrieval info: PRIVATE: DFF NUMERIC "1"
942
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
943
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
944
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
945
// Retrieval info: PRIVATE: SSET NUMERIC "0"
946
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
947
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
948
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
949
// Retrieval info: PRIVATE: nBit NUMERIC "1"
950
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
951
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
952
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
953
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
954
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
955
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
956
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
957
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
958
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
959
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
960
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
961
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
962
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
963
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
964
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
965
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
966
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
967
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
968
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
969
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
970
// Retrieval info: LIB_FILE: lpm
971 40 unneback
`endif
972 6 unneback
 
973
`else
974
 
975 40 unneback
`ifdef DFF_SR
976
`define MODULE dff_sr
977
module `BASE`MODULE ( aclr, aset, clock, data, q);
978
`undef MODULE
979 6 unneback
 
980
    input         aclr;
981
    input         aset;
982
    input         clock;
983
    input         data;
984
    output reg    q;
985
 
986
   always @ (posedge clock or posedge aclr or posedge aset)
987
     if (aclr)
988
       q <= 1'b0;
989
     else if (aset)
990
       q <= 1'b1;
991
     else
992
       q <= data;
993
 
994
endmodule
995 40 unneback
`endif
996 6 unneback
 
997
`endif
998
 
999
// LATCH
1000
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1001
`ifdef ALTERA
1002 40 unneback
 
1003
`ifdef LATCH
1004
`define MODULE latch
1005
module `BASE`MODULE ( d, le, q, clk);
1006
`undef MODULE
1007 6 unneback
input d, le;
1008
output q;
1009
input clk;
1010
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1011
endmodule
1012 40 unneback
`endif
1013
 
1014 6 unneback
`else
1015 40 unneback
 
1016
`ifdef LATCH
1017
`define MODULE latch
1018
module `BASE`MODULE ( d, le, q, clk);
1019
`undef MODULE
1020 6 unneback
input d, le;
1021
output q;
1022
input clk;/*
1023
   always @ (posedge direction_set or posedge direction_clr)
1024
     if (direction_clr)
1025
       direction <= going_empty;
1026
     else
1027
       direction <= going_full;*/
1028
endmodule
1029 15 unneback
`endif
1030
 
1031 40 unneback
`endif
1032
 
1033
`ifdef SHREG
1034
`define MODULE shreg
1035
module `BASE`MODULE ( d, q, clk, rst);
1036
`undef MODULE
1037
 
1038 17 unneback
parameter depth = 10;
1039
input d;
1040
output q;
1041
input clk, rst;
1042
 
1043
reg [1:depth] dffs;
1044
 
1045
always @ (posedge clk or posedge rst)
1046
if (rst)
1047
    dffs <= {depth{1'b0}};
1048
else
1049
    dffs <= {d,dffs[1:depth-1]};
1050
assign q = dffs[depth];
1051
endmodule
1052 40 unneback
`endif
1053 17 unneback
 
1054 40 unneback
`ifdef SHREG_CE
1055
`define MODULE shreg_ce
1056
module `BASE`MODULE ( d, ce, q, clk, rst);
1057
`undef MODULE
1058 17 unneback
parameter depth = 10;
1059
input d, ce;
1060
output q;
1061
input clk, rst;
1062
 
1063
reg [1:depth] dffs;
1064
 
1065
always @ (posedge clk or posedge rst)
1066
if (rst)
1067
    dffs <= {depth{1'b0}};
1068
else
1069
    if (ce)
1070
        dffs <= {d,dffs[1:depth-1]};
1071
assign q = dffs[depth];
1072
endmodule
1073 40 unneback
`endif
1074 17 unneback
 
1075 40 unneback
`ifdef DELAY
1076
`define MODULE delay
1077
module `BASE`MODULE ( d, q, clk, rst);
1078
`undef MODULE
1079 15 unneback
parameter depth = 10;
1080
input d;
1081
output q;
1082
input clk, rst;
1083
 
1084
reg [1:depth] dffs;
1085
 
1086
always @ (posedge clk or posedge rst)
1087
if (rst)
1088
    dffs <= {depth{1'b0}};
1089
else
1090
    dffs <= {d,dffs[1:depth-1]};
1091
assign q = dffs[depth];
1092 17 unneback
endmodule
1093 40 unneback
`endif
1094 17 unneback
 
1095 40 unneback
`ifdef DELAY_EMPTYFLAG
1096
`define MODULE delay_emptyflag
1097 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1098 40 unneback
`undef MODULE
1099 17 unneback
parameter depth = 10;
1100
input d;
1101
output q, emptyflag;
1102
input clk, rst;
1103
 
1104
reg [1:depth] dffs;
1105
 
1106
always @ (posedge clk or posedge rst)
1107
if (rst)
1108
    dffs <= {depth{1'b0}};
1109
else
1110
    dffs <= {d,dffs[1:depth-1]};
1111
assign q = dffs[depth];
1112
assign emptyflag = !(|dffs);
1113
endmodule
1114 40 unneback
`endif
1115 17 unneback
//////////////////////////////////////////////////////////////////////
1116 6 unneback
////                                                              ////
1117 18 unneback
////  Logic functions                                             ////
1118
////                                                              ////
1119
////  Description                                                 ////
1120
////  Logic functions such as multiplexers                        ////
1121
////                                                              ////
1122
////                                                              ////
1123
////  To Do:                                                      ////
1124
////   -                                                          ////
1125
////                                                              ////
1126
////  Author(s):                                                  ////
1127
////      - Michael Unneback, unneback@opencores.org              ////
1128
////        ORSoC AB                                              ////
1129
////                                                              ////
1130
//////////////////////////////////////////////////////////////////////
1131
////                                                              ////
1132
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1133
////                                                              ////
1134
//// This source file may be used and distributed without         ////
1135
//// restriction provided that this copyright statement is not    ////
1136
//// removed from the file and that any derivative work contains  ////
1137
//// the original copyright notice and the associated disclaimer. ////
1138
////                                                              ////
1139
//// This source file is free software; you can redistribute it   ////
1140
//// and/or modify it under the terms of the GNU Lesser General   ////
1141
//// Public License as published by the Free Software Foundation; ////
1142
//// either version 2.1 of the License, or (at your option) any   ////
1143
//// later version.                                               ////
1144
////                                                              ////
1145
//// This source is distributed in the hope that it will be       ////
1146
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1147
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1148
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1149
//// details.                                                     ////
1150
////                                                              ////
1151
//// You should have received a copy of the GNU Lesser General    ////
1152
//// Public License along with this source; if not, download it   ////
1153
//// from http://www.opencores.org/lgpl.shtml                     ////
1154
////                                                              ////
1155
//////////////////////////////////////////////////////////////////////
1156 40 unneback
`ifdef MUX_ANDOR
1157
`define MODULE mux_andor
1158
module `BASE`MODULE ( a, sel, dout);
1159
`undef MODULE
1160 36 unneback
 
1161
parameter width = 32;
1162
parameter nr_of_ports = 4;
1163
 
1164
input [nr_of_ports*width-1:0] a;
1165
input [nr_of_ports-1:0] sel;
1166
output reg [width-1:0] dout;
1167
 
1168 38 unneback
integer i,j;
1169
 
1170 36 unneback
always @ (a, sel)
1171
begin
1172
    dout = a[width-1:0] & {width{sel[0]}};
1173 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1174
        for (j=0;j<width;j=j+1)
1175
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1176 36 unneback
end
1177
 
1178
endmodule
1179 40 unneback
`endif
1180 36 unneback
 
1181 40 unneback
`ifdef MUX2_ANDOR
1182
`define MODULE mux2_andor
1183
module `BASE`MODULE ( a1, a0, sel, dout);
1184
`undef MODULE
1185 18 unneback
 
1186 34 unneback
parameter width = 32;
1187 35 unneback
localparam nr_of_ports = 2;
1188 34 unneback
input [width-1:0] a1, a0;
1189
input [nr_of_ports-1:0] sel;
1190
output [width-1:0] dout;
1191
 
1192 40 unneback
`define MODULE mux_andor
1193
`BASE`MODULE
1194 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1195 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1196 40 unneback
`undef MODULE
1197
 
1198 34 unneback
endmodule
1199 40 unneback
`endif
1200 34 unneback
 
1201 40 unneback
`ifdef MUX3_ANDOR
1202
`define MODULE mux3_andor
1203
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1204
`undef MODULE
1205 34 unneback
 
1206
parameter width = 32;
1207 35 unneback
localparam nr_of_ports = 3;
1208 34 unneback
input [width-1:0] a2, a1, a0;
1209
input [nr_of_ports-1:0] sel;
1210
output [width-1:0] dout;
1211
 
1212 40 unneback
`define MODULE mux_andor
1213
`BASE`MODULE
1214 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1215 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1216 40 unneback
`undef MODULE
1217 34 unneback
endmodule
1218 40 unneback
`endif
1219 34 unneback
 
1220 40 unneback
`ifdef MUX4_ANDOR
1221
`define MODULE mux4_andor
1222
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1223
`undef MODULE
1224 18 unneback
 
1225
parameter width = 32;
1226 35 unneback
localparam nr_of_ports = 4;
1227 18 unneback
input [width-1:0] a3, a2, a1, a0;
1228
input [nr_of_ports-1:0] sel;
1229 22 unneback
output [width-1:0] dout;
1230 18 unneback
 
1231 40 unneback
`define MODULE mux_andor
1232
`BASE`MODULE
1233 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1234 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1235 40 unneback
`undef MODULE
1236 18 unneback
 
1237
endmodule
1238 40 unneback
`endif
1239 18 unneback
 
1240 40 unneback
`ifdef MUX5_ANDOR
1241
`define MODULE mux5_andor
1242
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1243
`undef MODULE
1244 18 unneback
 
1245
parameter width = 32;
1246 35 unneback
localparam nr_of_ports = 5;
1247 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1248
input [nr_of_ports-1:0] sel;
1249 22 unneback
output [width-1:0] dout;
1250 18 unneback
 
1251 40 unneback
`define MODULE mux_andor
1252
`BASE`MODULE
1253 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1254 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1255 40 unneback
`undef MODULE
1256 18 unneback
 
1257
endmodule
1258 40 unneback
`endif
1259 18 unneback
 
1260 40 unneback
`ifdef MUX6_ANDOR
1261
`define MODULE mux6_andor
1262
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1263
`undef MODULE
1264 18 unneback
 
1265
parameter width = 32;
1266 35 unneback
localparam nr_of_ports = 6;
1267 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1268
input [nr_of_ports-1:0] sel;
1269 22 unneback
output [width-1:0] dout;
1270 18 unneback
 
1271 40 unneback
`define MODULE mux_andor
1272
`BASE`MODULE
1273 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1274 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1275 40 unneback
`undef MODULE
1276 18 unneback
 
1277
endmodule
1278 40 unneback
`endif
1279 43 unneback
 
1280
`ifdef PARITY
1281
 
1282
`define MODULE parity_generate
1283
module `BASE`MODULE (data, parity);
1284
`undef MODULE
1285
parameter word_size = 32;
1286
parameter chunk_size = 8;
1287
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1288
input [word_size-1:0] data;
1289
output reg [word_size/chunk_size-1:0] parity;
1290
integer i,j;
1291
always @ (data)
1292
for (i=0;i<word_size/chunk_size;i=i+1) begin
1293
    parity[i] = parity_type;
1294
    for (j=0;j<chunk_size;j=j+1) begin
1295
        parity[i] = data[i+j] ^ parity[i];
1296
    end
1297
end
1298
endmodule
1299
 
1300
`define MODULE parity_check
1301
module `BASE`MODULE( data, parity, parity_error);
1302
`undef MODULE
1303
parameter word_size = 32;
1304
parameter chunk_size = 8;
1305
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1306
input [word_size-1:0] data;
1307
input [word_size/chunk_size-1:0] parity;
1308
output parity_error;
1309
reg [chunk_size-1:0] error_flag;
1310
integer i,j;
1311
always @ (data or parity)
1312
for (i=0;i<word_size/chunk_size;i=i+1) begin
1313
    error_flag[i] = parity[i] ^ parity_type;
1314
    for (j=0;j<chunk_size;j=j+1) begin
1315
        error_flag[i] = data[i+j] ^ error_flag[i];
1316
    end
1317
end
1318
assign parity_error = |error_flag;
1319
endmodule
1320
 
1321
`endif`ifdef CNT_BIN
1322 18 unneback
//////////////////////////////////////////////////////////////////////
1323
////                                                              ////
1324 6 unneback
////  Versatile counter                                           ////
1325
////                                                              ////
1326
////  Description                                                 ////
1327
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1328
////  counter                                                     ////
1329
////                                                              ////
1330
////  To Do:                                                      ////
1331
////   - add LFSR with more taps                                  ////
1332
////                                                              ////
1333
////  Author(s):                                                  ////
1334
////      - Michael Unneback, unneback@opencores.org              ////
1335
////        ORSoC AB                                              ////
1336
////                                                              ////
1337
//////////////////////////////////////////////////////////////////////
1338
////                                                              ////
1339
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1340
////                                                              ////
1341
//// This source file may be used and distributed without         ////
1342
//// restriction provided that this copyright statement is not    ////
1343
//// removed from the file and that any derivative work contains  ////
1344
//// the original copyright notice and the associated disclaimer. ////
1345
////                                                              ////
1346
//// This source file is free software; you can redistribute it   ////
1347
//// and/or modify it under the terms of the GNU Lesser General   ////
1348
//// Public License as published by the Free Software Foundation; ////
1349
//// either version 2.1 of the License, or (at your option) any   ////
1350
//// later version.                                               ////
1351
////                                                              ////
1352
//// This source is distributed in the hope that it will be       ////
1353
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1354
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1355
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1356
//// details.                                                     ////
1357
////                                                              ////
1358
//// You should have received a copy of the GNU Lesser General    ////
1359
//// Public License along with this source; if not, download it   ////
1360
//// from http://www.opencores.org/lgpl.shtml                     ////
1361
////                                                              ////
1362
//////////////////////////////////////////////////////////////////////
1363
 
1364
// binary counter
1365 22 unneback
 
1366 40 unneback
`define MODULE cnt_bin
1367
module `BASE`MODULE (
1368
`undef MODULE
1369
 q, rst, clk);
1370
 
1371 22 unneback
   parameter length = 4;
1372
   output [length:1] q;
1373
   input rst;
1374
   input clk;
1375
 
1376
   parameter clear_value = 0;
1377
   parameter set_value = 1;
1378
   parameter wrap_value = 0;
1379
   parameter level1_value = 15;
1380
 
1381
   reg  [length:1] qi;
1382
   wire [length:1] q_next;
1383
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1384
 
1385
   always @ (posedge clk or posedge rst)
1386
     if (rst)
1387
       qi <= {length{1'b0}};
1388
     else
1389
       qi <= q_next;
1390
 
1391
   assign q = qi;
1392
 
1393
endmodule
1394 40 unneback
`endif
1395
`ifdef CNT_BIN_CLEAR
1396 22 unneback
//////////////////////////////////////////////////////////////////////
1397
////                                                              ////
1398
////  Versatile counter                                           ////
1399
////                                                              ////
1400
////  Description                                                 ////
1401
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1402
////  counter                                                     ////
1403
////                                                              ////
1404
////  To Do:                                                      ////
1405
////   - add LFSR with more taps                                  ////
1406
////                                                              ////
1407
////  Author(s):                                                  ////
1408
////      - Michael Unneback, unneback@opencores.org              ////
1409
////        ORSoC AB                                              ////
1410
////                                                              ////
1411
//////////////////////////////////////////////////////////////////////
1412
////                                                              ////
1413
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1414
////                                                              ////
1415
//// This source file may be used and distributed without         ////
1416
//// restriction provided that this copyright statement is not    ////
1417
//// removed from the file and that any derivative work contains  ////
1418
//// the original copyright notice and the associated disclaimer. ////
1419
////                                                              ////
1420
//// This source file is free software; you can redistribute it   ////
1421
//// and/or modify it under the terms of the GNU Lesser General   ////
1422
//// Public License as published by the Free Software Foundation; ////
1423
//// either version 2.1 of the License, or (at your option) any   ////
1424
//// later version.                                               ////
1425
////                                                              ////
1426
//// This source is distributed in the hope that it will be       ////
1427
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1428
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1429
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1430
//// details.                                                     ////
1431
////                                                              ////
1432
//// You should have received a copy of the GNU Lesser General    ////
1433
//// Public License along with this source; if not, download it   ////
1434
//// from http://www.opencores.org/lgpl.shtml                     ////
1435
////                                                              ////
1436
//////////////////////////////////////////////////////////////////////
1437
 
1438
// binary counter
1439
 
1440 40 unneback
`define MODULE cnt_bin_clear
1441
module `BASE`MODULE (
1442
`undef MODULE
1443
 clear, q, rst, clk);
1444
 
1445 22 unneback
   parameter length = 4;
1446
   input clear;
1447
   output [length:1] q;
1448
   input rst;
1449
   input clk;
1450
 
1451
   parameter clear_value = 0;
1452
   parameter set_value = 1;
1453
   parameter wrap_value = 0;
1454
   parameter level1_value = 15;
1455
 
1456
   reg  [length:1] qi;
1457
   wire [length:1] q_next;
1458
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1459
 
1460
   always @ (posedge clk or posedge rst)
1461
     if (rst)
1462
       qi <= {length{1'b0}};
1463
     else
1464
       qi <= q_next;
1465
 
1466
   assign q = qi;
1467
 
1468
endmodule
1469 40 unneback
`endif
1470
`ifdef CNT_BIN_CE
1471 22 unneback
//////////////////////////////////////////////////////////////////////
1472
////                                                              ////
1473
////  Versatile counter                                           ////
1474
////                                                              ////
1475
////  Description                                                 ////
1476
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1477
////  counter                                                     ////
1478
////                                                              ////
1479
////  To Do:                                                      ////
1480
////   - add LFSR with more taps                                  ////
1481
////                                                              ////
1482
////  Author(s):                                                  ////
1483
////      - Michael Unneback, unneback@opencores.org              ////
1484
////        ORSoC AB                                              ////
1485
////                                                              ////
1486
//////////////////////////////////////////////////////////////////////
1487
////                                                              ////
1488
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1489
////                                                              ////
1490
//// This source file may be used and distributed without         ////
1491
//// restriction provided that this copyright statement is not    ////
1492
//// removed from the file and that any derivative work contains  ////
1493
//// the original copyright notice and the associated disclaimer. ////
1494
////                                                              ////
1495
//// This source file is free software; you can redistribute it   ////
1496
//// and/or modify it under the terms of the GNU Lesser General   ////
1497
//// Public License as published by the Free Software Foundation; ////
1498
//// either version 2.1 of the License, or (at your option) any   ////
1499
//// later version.                                               ////
1500
////                                                              ////
1501
//// This source is distributed in the hope that it will be       ////
1502
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1503
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1504
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1505
//// details.                                                     ////
1506
////                                                              ////
1507
//// You should have received a copy of the GNU Lesser General    ////
1508
//// Public License along with this source; if not, download it   ////
1509
//// from http://www.opencores.org/lgpl.shtml                     ////
1510
////                                                              ////
1511
//////////////////////////////////////////////////////////////////////
1512
 
1513
// binary counter
1514 6 unneback
 
1515 40 unneback
`define MODULE cnt_bin_ce
1516
module `BASE`MODULE (
1517
`undef MODULE
1518
 cke, q, rst, clk);
1519
 
1520 6 unneback
   parameter length = 4;
1521
   input cke;
1522
   output [length:1] q;
1523
   input rst;
1524
   input clk;
1525
 
1526
   parameter clear_value = 0;
1527
   parameter set_value = 1;
1528
   parameter wrap_value = 0;
1529
   parameter level1_value = 15;
1530
 
1531
   reg  [length:1] qi;
1532
   wire [length:1] q_next;
1533
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1534
 
1535
   always @ (posedge clk or posedge rst)
1536
     if (rst)
1537
       qi <= {length{1'b0}};
1538
     else
1539
     if (cke)
1540
       qi <= q_next;
1541
 
1542
   assign q = qi;
1543
 
1544
endmodule
1545 40 unneback
`endif
1546
`ifdef CNT_BIN_CE_CLEAR
1547 6 unneback
//////////////////////////////////////////////////////////////////////
1548
////                                                              ////
1549
////  Versatile counter                                           ////
1550
////                                                              ////
1551
////  Description                                                 ////
1552
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1553
////  counter                                                     ////
1554
////                                                              ////
1555
////  To Do:                                                      ////
1556
////   - add LFSR with more taps                                  ////
1557
////                                                              ////
1558
////  Author(s):                                                  ////
1559
////      - Michael Unneback, unneback@opencores.org              ////
1560
////        ORSoC AB                                              ////
1561
////                                                              ////
1562
//////////////////////////////////////////////////////////////////////
1563
////                                                              ////
1564
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1565
////                                                              ////
1566
//// This source file may be used and distributed without         ////
1567
//// restriction provided that this copyright statement is not    ////
1568
//// removed from the file and that any derivative work contains  ////
1569
//// the original copyright notice and the associated disclaimer. ////
1570
////                                                              ////
1571
//// This source file is free software; you can redistribute it   ////
1572
//// and/or modify it under the terms of the GNU Lesser General   ////
1573
//// Public License as published by the Free Software Foundation; ////
1574
//// either version 2.1 of the License, or (at your option) any   ////
1575
//// later version.                                               ////
1576
////                                                              ////
1577
//// This source is distributed in the hope that it will be       ////
1578
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1579
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1580
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1581
//// details.                                                     ////
1582
////                                                              ////
1583
//// You should have received a copy of the GNU Lesser General    ////
1584
//// Public License along with this source; if not, download it   ////
1585
//// from http://www.opencores.org/lgpl.shtml                     ////
1586
////                                                              ////
1587
//////////////////////////////////////////////////////////////////////
1588
 
1589
// binary counter
1590
 
1591 40 unneback
`define MODULE cnt_bin_ce_clear
1592
module `BASE`MODULE (
1593
`undef MODULE
1594
 clear, cke, q, rst, clk);
1595
 
1596 6 unneback
   parameter length = 4;
1597
   input clear;
1598
   input cke;
1599
   output [length:1] q;
1600
   input rst;
1601
   input clk;
1602
 
1603
   parameter clear_value = 0;
1604
   parameter set_value = 1;
1605
   parameter wrap_value = 0;
1606
   parameter level1_value = 15;
1607
 
1608
   reg  [length:1] qi;
1609
   wire [length:1] q_next;
1610
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1611
 
1612
   always @ (posedge clk or posedge rst)
1613
     if (rst)
1614
       qi <= {length{1'b0}};
1615
     else
1616
     if (cke)
1617
       qi <= q_next;
1618
 
1619
   assign q = qi;
1620
 
1621
endmodule
1622 40 unneback
`endif
1623
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1624 6 unneback
//////////////////////////////////////////////////////////////////////
1625
////                                                              ////
1626
////  Versatile counter                                           ////
1627
////                                                              ////
1628
////  Description                                                 ////
1629
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1630
////  counter                                                     ////
1631
////                                                              ////
1632
////  To Do:                                                      ////
1633
////   - add LFSR with more taps                                  ////
1634
////                                                              ////
1635
////  Author(s):                                                  ////
1636
////      - Michael Unneback, unneback@opencores.org              ////
1637
////        ORSoC AB                                              ////
1638
////                                                              ////
1639
//////////////////////////////////////////////////////////////////////
1640
////                                                              ////
1641
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1642
////                                                              ////
1643
//// This source file may be used and distributed without         ////
1644
//// restriction provided that this copyright statement is not    ////
1645
//// removed from the file and that any derivative work contains  ////
1646
//// the original copyright notice and the associated disclaimer. ////
1647
////                                                              ////
1648
//// This source file is free software; you can redistribute it   ////
1649
//// and/or modify it under the terms of the GNU Lesser General   ////
1650
//// Public License as published by the Free Software Foundation; ////
1651
//// either version 2.1 of the License, or (at your option) any   ////
1652
//// later version.                                               ////
1653
////                                                              ////
1654
//// This source is distributed in the hope that it will be       ////
1655
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1656
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1657
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1658
//// details.                                                     ////
1659
////                                                              ////
1660
//// You should have received a copy of the GNU Lesser General    ////
1661
//// Public License along with this source; if not, download it   ////
1662
//// from http://www.opencores.org/lgpl.shtml                     ////
1663
////                                                              ////
1664
//////////////////////////////////////////////////////////////////////
1665
 
1666
// binary counter
1667 29 unneback
 
1668 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1669
module `BASE`MODULE (
1670
`undef MODULE
1671
 clear, cke, q, level1, level2, rst, clk);
1672
 
1673 29 unneback
   parameter length = 4;
1674
   input clear;
1675
   input cke;
1676
   output [length:1] q;
1677
   output reg level1;
1678
   output reg level2;
1679
   input rst;
1680
   input clk;
1681
 
1682
   parameter clear_value = 0;
1683
   parameter set_value = 1;
1684 30 unneback
   parameter wrap_value = 15;
1685
   parameter level1_value = 8;
1686
   parameter level2_value = 15;
1687 29 unneback
 
1688
   wire rew;
1689 30 unneback
   assign rew = 1'b0;
1690 29 unneback
   reg  [length:1] qi;
1691
   wire [length:1] q_next;
1692
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1693
 
1694
   always @ (posedge clk or posedge rst)
1695
     if (rst)
1696
       qi <= {length{1'b0}};
1697
     else
1698
     if (cke)
1699
       qi <= q_next;
1700
 
1701
   assign q = qi;
1702
 
1703
 
1704
    always @ (posedge clk or posedge rst)
1705
    if (rst)
1706
        level1 <= 1'b0;
1707
    else
1708
    if (cke)
1709
    if (clear)
1710
        level1 <= 1'b0;
1711
    else if (q_next == level1_value)
1712
        level1 <= 1'b1;
1713
    else if (qi == level1_value & rew)
1714
        level1 <= 1'b0;
1715
 
1716
    always @ (posedge clk or posedge rst)
1717
    if (rst)
1718
        level2 <= 1'b0;
1719
    else
1720
    if (cke)
1721
    if (clear)
1722
        level2 <= 1'b0;
1723
    else if (q_next == level2_value)
1724
        level2 <= 1'b1;
1725
    else if (qi == level2_value & rew)
1726
        level2 <= 1'b0;
1727
endmodule
1728 40 unneback
`endif
1729
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1730 29 unneback
//////////////////////////////////////////////////////////////////////
1731
////                                                              ////
1732
////  Versatile counter                                           ////
1733
////                                                              ////
1734
////  Description                                                 ////
1735
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1736
////  counter                                                     ////
1737
////                                                              ////
1738
////  To Do:                                                      ////
1739
////   - add LFSR with more taps                                  ////
1740
////                                                              ////
1741
////  Author(s):                                                  ////
1742
////      - Michael Unneback, unneback@opencores.org              ////
1743
////        ORSoC AB                                              ////
1744
////                                                              ////
1745
//////////////////////////////////////////////////////////////////////
1746
////                                                              ////
1747
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1748
////                                                              ////
1749
//// This source file may be used and distributed without         ////
1750
//// restriction provided that this copyright statement is not    ////
1751
//// removed from the file and that any derivative work contains  ////
1752
//// the original copyright notice and the associated disclaimer. ////
1753
////                                                              ////
1754
//// This source file is free software; you can redistribute it   ////
1755
//// and/or modify it under the terms of the GNU Lesser General   ////
1756
//// Public License as published by the Free Software Foundation; ////
1757
//// either version 2.1 of the License, or (at your option) any   ////
1758
//// later version.                                               ////
1759
////                                                              ////
1760
//// This source is distributed in the hope that it will be       ////
1761
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1762
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1763
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1764
//// details.                                                     ////
1765
////                                                              ////
1766
//// You should have received a copy of the GNU Lesser General    ////
1767
//// Public License along with this source; if not, download it   ////
1768
//// from http://www.opencores.org/lgpl.shtml                     ////
1769
////                                                              ////
1770
//////////////////////////////////////////////////////////////////////
1771
 
1772
// binary counter
1773 6 unneback
 
1774 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1775
module `BASE`MODULE (
1776
`undef MODULE
1777
 clear, set, cke, rew, q, rst, clk);
1778
 
1779 6 unneback
   parameter length = 4;
1780
   input clear;
1781
   input set;
1782
   input cke;
1783
   input rew;
1784
   output [length:1] q;
1785
   input rst;
1786
   input clk;
1787
 
1788
   parameter clear_value = 0;
1789
   parameter set_value = 1;
1790
   parameter wrap_value = 0;
1791
   parameter level1_value = 15;
1792
 
1793
   reg  [length:1] qi;
1794
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1795
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1796
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1797
   assign q_next = rew ? q_next_rew : q_next_fw;
1798
 
1799
   always @ (posedge clk or posedge rst)
1800
     if (rst)
1801
       qi <= {length{1'b0}};
1802
     else
1803
     if (cke)
1804
       qi <= q_next;
1805
 
1806
   assign q = qi;
1807
 
1808
endmodule
1809 40 unneback
`endif
1810
`ifdef CNT_BIN_CE_REW_L1
1811 6 unneback
//////////////////////////////////////////////////////////////////////
1812
////                                                              ////
1813
////  Versatile counter                                           ////
1814
////                                                              ////
1815
////  Description                                                 ////
1816
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1817
////  counter                                                     ////
1818
////                                                              ////
1819
////  To Do:                                                      ////
1820
////   - add LFSR with more taps                                  ////
1821
////                                                              ////
1822
////  Author(s):                                                  ////
1823
////      - Michael Unneback, unneback@opencores.org              ////
1824
////        ORSoC AB                                              ////
1825
////                                                              ////
1826
//////////////////////////////////////////////////////////////////////
1827
////                                                              ////
1828
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1829
////                                                              ////
1830
//// This source file may be used and distributed without         ////
1831
//// restriction provided that this copyright statement is not    ////
1832
//// removed from the file and that any derivative work contains  ////
1833
//// the original copyright notice and the associated disclaimer. ////
1834
////                                                              ////
1835
//// This source file is free software; you can redistribute it   ////
1836
//// and/or modify it under the terms of the GNU Lesser General   ////
1837
//// Public License as published by the Free Software Foundation; ////
1838
//// either version 2.1 of the License, or (at your option) any   ////
1839
//// later version.                                               ////
1840
////                                                              ////
1841
//// This source is distributed in the hope that it will be       ////
1842
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1843
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1844
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1845
//// details.                                                     ////
1846
////                                                              ////
1847
//// You should have received a copy of the GNU Lesser General    ////
1848
//// Public License along with this source; if not, download it   ////
1849
//// from http://www.opencores.org/lgpl.shtml                     ////
1850
////                                                              ////
1851
//////////////////////////////////////////////////////////////////////
1852
 
1853
// binary counter
1854
 
1855 40 unneback
`define MODULE cnt_bin_ce_rew_l1
1856
module `BASE`MODULE (
1857
`undef MODULE
1858
 cke, rew, level1, rst, clk);
1859
 
1860 6 unneback
   parameter length = 4;
1861
   input cke;
1862
   input rew;
1863
   output reg level1;
1864
   input rst;
1865
   input clk;
1866
 
1867
   parameter clear_value = 0;
1868
   parameter set_value = 1;
1869
   parameter wrap_value = 1;
1870
   parameter level1_value = 15;
1871
 
1872 29 unneback
   wire clear;
1873 30 unneback
   assign clear = 1'b0;
1874 6 unneback
   reg  [length:1] qi;
1875
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1876
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1877
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1878
   assign q_next = rew ? q_next_rew : q_next_fw;
1879
 
1880
   always @ (posedge clk or posedge rst)
1881
     if (rst)
1882
       qi <= {length{1'b0}};
1883
     else
1884
     if (cke)
1885
       qi <= q_next;
1886
 
1887
 
1888
 
1889
    always @ (posedge clk or posedge rst)
1890
    if (rst)
1891
        level1 <= 1'b0;
1892
    else
1893
    if (cke)
1894 29 unneback
    if (clear)
1895
        level1 <= 1'b0;
1896
    else if (q_next == level1_value)
1897 6 unneback
        level1 <= 1'b1;
1898
    else if (qi == level1_value & rew)
1899
        level1 <= 1'b0;
1900
endmodule
1901 40 unneback
`endif
1902
`ifdef CNT_BIN_CE_REW_ZQ_L1
1903 6 unneback
//////////////////////////////////////////////////////////////////////
1904
////                                                              ////
1905
////  Versatile counter                                           ////
1906
////                                                              ////
1907
////  Description                                                 ////
1908
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1909
////  counter                                                     ////
1910
////                                                              ////
1911
////  To Do:                                                      ////
1912
////   - add LFSR with more taps                                  ////
1913
////                                                              ////
1914
////  Author(s):                                                  ////
1915
////      - Michael Unneback, unneback@opencores.org              ////
1916
////        ORSoC AB                                              ////
1917
////                                                              ////
1918
//////////////////////////////////////////////////////////////////////
1919
////                                                              ////
1920
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1921
////                                                              ////
1922
//// This source file may be used and distributed without         ////
1923
//// restriction provided that this copyright statement is not    ////
1924
//// removed from the file and that any derivative work contains  ////
1925
//// the original copyright notice and the associated disclaimer. ////
1926
////                                                              ////
1927
//// This source file is free software; you can redistribute it   ////
1928
//// and/or modify it under the terms of the GNU Lesser General   ////
1929
//// Public License as published by the Free Software Foundation; ////
1930
//// either version 2.1 of the License, or (at your option) any   ////
1931
//// later version.                                               ////
1932
////                                                              ////
1933
//// This source is distributed in the hope that it will be       ////
1934
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1935
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1936
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1937
//// details.                                                     ////
1938
////                                                              ////
1939
//// You should have received a copy of the GNU Lesser General    ////
1940
//// Public License along with this source; if not, download it   ////
1941
//// from http://www.opencores.org/lgpl.shtml                     ////
1942
////                                                              ////
1943
//////////////////////////////////////////////////////////////////////
1944
 
1945 25 unneback
// binary counter
1946
 
1947 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
1948
module `BASE`MODULE (
1949
`undef MODULE
1950
 cke, rew, zq, level1, rst, clk);
1951
 
1952 25 unneback
   parameter length = 4;
1953
   input cke;
1954
   input rew;
1955
   output reg zq;
1956
   output reg level1;
1957
   input rst;
1958
   input clk;
1959
 
1960
   parameter clear_value = 0;
1961
   parameter set_value = 1;
1962
   parameter wrap_value = 1;
1963
   parameter level1_value = 15;
1964
 
1965 29 unneback
   wire clear;
1966 30 unneback
   assign clear = 1'b0;
1967 25 unneback
   reg  [length:1] qi;
1968
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1969
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1970
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1971
   assign q_next = rew ? q_next_rew : q_next_fw;
1972
 
1973
   always @ (posedge clk or posedge rst)
1974
     if (rst)
1975
       qi <= {length{1'b0}};
1976
     else
1977
     if (cke)
1978
       qi <= q_next;
1979
 
1980
 
1981
 
1982
   always @ (posedge clk or posedge rst)
1983
     if (rst)
1984
       zq <= 1'b1;
1985
     else
1986
     if (cke)
1987
       zq <= q_next == {length{1'b0}};
1988
 
1989
    always @ (posedge clk or posedge rst)
1990
    if (rst)
1991
        level1 <= 1'b0;
1992
    else
1993
    if (cke)
1994 29 unneback
    if (clear)
1995
        level1 <= 1'b0;
1996
    else if (q_next == level1_value)
1997 25 unneback
        level1 <= 1'b1;
1998
    else if (qi == level1_value & rew)
1999
        level1 <= 1'b0;
2000
endmodule
2001 40 unneback
`endif
2002
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2003 25 unneback
//////////////////////////////////////////////////////////////////////
2004
////                                                              ////
2005
////  Versatile counter                                           ////
2006
////                                                              ////
2007
////  Description                                                 ////
2008
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2009
////  counter                                                     ////
2010
////                                                              ////
2011
////  To Do:                                                      ////
2012
////   - add LFSR with more taps                                  ////
2013
////                                                              ////
2014
////  Author(s):                                                  ////
2015
////      - Michael Unneback, unneback@opencores.org              ////
2016
////        ORSoC AB                                              ////
2017
////                                                              ////
2018
//////////////////////////////////////////////////////////////////////
2019
////                                                              ////
2020
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2021
////                                                              ////
2022
//// This source file may be used and distributed without         ////
2023
//// restriction provided that this copyright statement is not    ////
2024
//// removed from the file and that any derivative work contains  ////
2025
//// the original copyright notice and the associated disclaimer. ////
2026
////                                                              ////
2027
//// This source file is free software; you can redistribute it   ////
2028
//// and/or modify it under the terms of the GNU Lesser General   ////
2029
//// Public License as published by the Free Software Foundation; ////
2030
//// either version 2.1 of the License, or (at your option) any   ////
2031
//// later version.                                               ////
2032
////                                                              ////
2033
//// This source is distributed in the hope that it will be       ////
2034
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2035
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2036
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2037
//// details.                                                     ////
2038
////                                                              ////
2039
//// You should have received a copy of the GNU Lesser General    ////
2040
//// Public License along with this source; if not, download it   ////
2041
//// from http://www.opencores.org/lgpl.shtml                     ////
2042
////                                                              ////
2043
//////////////////////////////////////////////////////////////////////
2044
 
2045
// binary counter
2046
 
2047 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2048
module `BASE`MODULE (
2049
`undef MODULE
2050
 cke, rew, q, zq, level1, rst, clk);
2051
 
2052 25 unneback
   parameter length = 4;
2053
   input cke;
2054
   input rew;
2055
   output [length:1] q;
2056
   output reg zq;
2057
   output reg level1;
2058
   input rst;
2059
   input clk;
2060
 
2061
   parameter clear_value = 0;
2062
   parameter set_value = 1;
2063
   parameter wrap_value = 1;
2064
   parameter level1_value = 15;
2065
 
2066 29 unneback
   wire clear;
2067 30 unneback
   assign clear = 1'b0;
2068 25 unneback
   reg  [length:1] qi;
2069
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2070
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2071
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2072
   assign q_next = rew ? q_next_rew : q_next_fw;
2073
 
2074
   always @ (posedge clk or posedge rst)
2075
     if (rst)
2076
       qi <= {length{1'b0}};
2077
     else
2078
     if (cke)
2079
       qi <= q_next;
2080
 
2081
   assign q = qi;
2082
 
2083
 
2084
   always @ (posedge clk or posedge rst)
2085
     if (rst)
2086
       zq <= 1'b1;
2087
     else
2088
     if (cke)
2089
       zq <= q_next == {length{1'b0}};
2090
 
2091
    always @ (posedge clk or posedge rst)
2092
    if (rst)
2093
        level1 <= 1'b0;
2094
    else
2095
    if (cke)
2096 29 unneback
    if (clear)
2097
        level1 <= 1'b0;
2098
    else if (q_next == level1_value)
2099 25 unneback
        level1 <= 1'b1;
2100
    else if (qi == level1_value & rew)
2101
        level1 <= 1'b0;
2102
endmodule
2103 40 unneback
`endif
2104
`ifdef CNT_LFSR_ZQ
2105 25 unneback
//////////////////////////////////////////////////////////////////////
2106
////                                                              ////
2107
////  Versatile counter                                           ////
2108
////                                                              ////
2109
////  Description                                                 ////
2110
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2111
////  counter                                                     ////
2112
////                                                              ////
2113
////  To Do:                                                      ////
2114
////   - add LFSR with more taps                                  ////
2115
////                                                              ////
2116
////  Author(s):                                                  ////
2117
////      - Michael Unneback, unneback@opencores.org              ////
2118
////        ORSoC AB                                              ////
2119
////                                                              ////
2120
//////////////////////////////////////////////////////////////////////
2121
////                                                              ////
2122
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2123
////                                                              ////
2124
//// This source file may be used and distributed without         ////
2125
//// restriction provided that this copyright statement is not    ////
2126
//// removed from the file and that any derivative work contains  ////
2127
//// the original copyright notice and the associated disclaimer. ////
2128
////                                                              ////
2129
//// This source file is free software; you can redistribute it   ////
2130
//// and/or modify it under the terms of the GNU Lesser General   ////
2131
//// Public License as published by the Free Software Foundation; ////
2132
//// either version 2.1 of the License, or (at your option) any   ////
2133
//// later version.                                               ////
2134
////                                                              ////
2135
//// This source is distributed in the hope that it will be       ////
2136
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2137
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2138
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2139
//// details.                                                     ////
2140
////                                                              ////
2141
//// You should have received a copy of the GNU Lesser General    ////
2142
//// Public License along with this source; if not, download it   ////
2143
//// from http://www.opencores.org/lgpl.shtml                     ////
2144
////                                                              ////
2145
//////////////////////////////////////////////////////////////////////
2146
 
2147 6 unneback
// LFSR counter
2148
 
2149 40 unneback
`define MODULE cnt_lfsr_zq
2150
module `BASE`MODULE (
2151
`undef MODULE
2152
 zq, rst, clk);
2153
 
2154 6 unneback
   parameter length = 4;
2155
   output reg zq;
2156
   input rst;
2157
   input clk;
2158
 
2159
   parameter clear_value = 0;
2160
   parameter set_value = 1;
2161
   parameter wrap_value = 8;
2162
   parameter level1_value = 15;
2163
 
2164
   reg  [length:1] qi;
2165
   reg lfsr_fb;
2166
   wire [length:1] q_next;
2167
   reg [32:1] polynom;
2168
   integer i;
2169
 
2170
   always @ (qi)
2171
   begin
2172
        case (length)
2173
         2: polynom = 32'b11;                               // 0x3
2174
         3: polynom = 32'b110;                              // 0x6
2175
         4: polynom = 32'b1100;                             // 0xC
2176
         5: polynom = 32'b10100;                            // 0x14
2177
         6: polynom = 32'b110000;                           // 0x30
2178
         7: polynom = 32'b1100000;                          // 0x60
2179
         8: polynom = 32'b10111000;                         // 0xb8
2180
         9: polynom = 32'b100010000;                        // 0x110
2181
        10: polynom = 32'b1001000000;                       // 0x240
2182
        11: polynom = 32'b10100000000;                      // 0x500
2183
        12: polynom = 32'b100000101001;                     // 0x829
2184
        13: polynom = 32'b1000000001100;                    // 0x100C
2185
        14: polynom = 32'b10000000010101;                   // 0x2015
2186
        15: polynom = 32'b110000000000000;                  // 0x6000
2187
        16: polynom = 32'b1101000000001000;                 // 0xD008
2188
        17: polynom = 32'b10010000000000000;                // 0x12000
2189
        18: polynom = 32'b100000010000000000;               // 0x20400
2190
        19: polynom = 32'b1000000000000100011;              // 0x40023
2191 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2192 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2193
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2194
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2195
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2196
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2197
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2198
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2199
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2200
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2201
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2202
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2203
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2204
        default: polynom = 32'b0;
2205
        endcase
2206
        lfsr_fb = qi[length];
2207
        for (i=length-1; i>=1; i=i-1) begin
2208
            if (polynom[i])
2209
                lfsr_fb = lfsr_fb  ~^ qi[i];
2210
        end
2211
    end
2212
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2213
 
2214
   always @ (posedge clk or posedge rst)
2215
     if (rst)
2216
       qi <= {length{1'b0}};
2217
     else
2218
       qi <= q_next;
2219
 
2220
 
2221
 
2222
   always @ (posedge clk or posedge rst)
2223
     if (rst)
2224
       zq <= 1'b1;
2225
     else
2226
       zq <= q_next == {length{1'b0}};
2227
endmodule
2228 40 unneback
`endif
2229
`ifdef CNT_LFSR_CE_ZQ
2230 6 unneback
//////////////////////////////////////////////////////////////////////
2231
////                                                              ////
2232
////  Versatile counter                                           ////
2233
////                                                              ////
2234
////  Description                                                 ////
2235
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2236
////  counter                                                     ////
2237
////                                                              ////
2238
////  To Do:                                                      ////
2239
////   - add LFSR with more taps                                  ////
2240
////                                                              ////
2241
////  Author(s):                                                  ////
2242
////      - Michael Unneback, unneback@opencores.org              ////
2243
////        ORSoC AB                                              ////
2244
////                                                              ////
2245
//////////////////////////////////////////////////////////////////////
2246
////                                                              ////
2247
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2248
////                                                              ////
2249
//// This source file may be used and distributed without         ////
2250
//// restriction provided that this copyright statement is not    ////
2251
//// removed from the file and that any derivative work contains  ////
2252
//// the original copyright notice and the associated disclaimer. ////
2253
////                                                              ////
2254
//// This source file is free software; you can redistribute it   ////
2255
//// and/or modify it under the terms of the GNU Lesser General   ////
2256
//// Public License as published by the Free Software Foundation; ////
2257
//// either version 2.1 of the License, or (at your option) any   ////
2258
//// later version.                                               ////
2259
////                                                              ////
2260
//// This source is distributed in the hope that it will be       ////
2261
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2262
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2263
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2264
//// details.                                                     ////
2265
////                                                              ////
2266
//// You should have received a copy of the GNU Lesser General    ////
2267
//// Public License along with this source; if not, download it   ////
2268
//// from http://www.opencores.org/lgpl.shtml                     ////
2269
////                                                              ////
2270
//////////////////////////////////////////////////////////////////////
2271
 
2272
// LFSR counter
2273
 
2274 40 unneback
`define MODULE cnt_lfsr_ce_zq
2275
module `BASE`MODULE (
2276
`undef MODULE
2277
 cke, zq, rst, clk);
2278
 
2279 6 unneback
   parameter length = 4;
2280
   input cke;
2281
   output reg zq;
2282
   input rst;
2283
   input clk;
2284
 
2285
   parameter clear_value = 0;
2286
   parameter set_value = 1;
2287
   parameter wrap_value = 8;
2288
   parameter level1_value = 15;
2289
 
2290
   reg  [length:1] qi;
2291
   reg lfsr_fb;
2292
   wire [length:1] q_next;
2293
   reg [32:1] polynom;
2294
   integer i;
2295
 
2296
   always @ (qi)
2297
   begin
2298
        case (length)
2299
         2: polynom = 32'b11;                               // 0x3
2300
         3: polynom = 32'b110;                              // 0x6
2301
         4: polynom = 32'b1100;                             // 0xC
2302
         5: polynom = 32'b10100;                            // 0x14
2303
         6: polynom = 32'b110000;                           // 0x30
2304
         7: polynom = 32'b1100000;                          // 0x60
2305
         8: polynom = 32'b10111000;                         // 0xb8
2306
         9: polynom = 32'b100010000;                        // 0x110
2307
        10: polynom = 32'b1001000000;                       // 0x240
2308
        11: polynom = 32'b10100000000;                      // 0x500
2309
        12: polynom = 32'b100000101001;                     // 0x829
2310
        13: polynom = 32'b1000000001100;                    // 0x100C
2311
        14: polynom = 32'b10000000010101;                   // 0x2015
2312
        15: polynom = 32'b110000000000000;                  // 0x6000
2313
        16: polynom = 32'b1101000000001000;                 // 0xD008
2314
        17: polynom = 32'b10010000000000000;                // 0x12000
2315
        18: polynom = 32'b100000010000000000;               // 0x20400
2316
        19: polynom = 32'b1000000000000100011;              // 0x40023
2317 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2318 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2319
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2320
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2321
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2322
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2323
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2324
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2325
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2326
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2327
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2328
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2329
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2330
        default: polynom = 32'b0;
2331
        endcase
2332
        lfsr_fb = qi[length];
2333
        for (i=length-1; i>=1; i=i-1) begin
2334
            if (polynom[i])
2335
                lfsr_fb = lfsr_fb  ~^ qi[i];
2336
        end
2337
    end
2338
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2339
 
2340
   always @ (posedge clk or posedge rst)
2341
     if (rst)
2342
       qi <= {length{1'b0}};
2343
     else
2344
     if (cke)
2345
       qi <= q_next;
2346
 
2347
 
2348
 
2349
   always @ (posedge clk or posedge rst)
2350
     if (rst)
2351
       zq <= 1'b1;
2352
     else
2353
     if (cke)
2354
       zq <= q_next == {length{1'b0}};
2355
endmodule
2356 40 unneback
`endif
2357
`ifdef CNT_LFSR_CE_Q
2358 6 unneback
//////////////////////////////////////////////////////////////////////
2359
////                                                              ////
2360
////  Versatile counter                                           ////
2361
////                                                              ////
2362
////  Description                                                 ////
2363
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2364
////  counter                                                     ////
2365
////                                                              ////
2366
////  To Do:                                                      ////
2367
////   - add LFSR with more taps                                  ////
2368
////                                                              ////
2369
////  Author(s):                                                  ////
2370
////      - Michael Unneback, unneback@opencores.org              ////
2371
////        ORSoC AB                                              ////
2372
////                                                              ////
2373
//////////////////////////////////////////////////////////////////////
2374
////                                                              ////
2375
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2376
////                                                              ////
2377
//// This source file may be used and distributed without         ////
2378
//// restriction provided that this copyright statement is not    ////
2379
//// removed from the file and that any derivative work contains  ////
2380
//// the original copyright notice and the associated disclaimer. ////
2381
////                                                              ////
2382
//// This source file is free software; you can redistribute it   ////
2383
//// and/or modify it under the terms of the GNU Lesser General   ////
2384
//// Public License as published by the Free Software Foundation; ////
2385
//// either version 2.1 of the License, or (at your option) any   ////
2386
//// later version.                                               ////
2387
////                                                              ////
2388
//// This source is distributed in the hope that it will be       ////
2389
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2390
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2391
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2392
//// details.                                                     ////
2393
////                                                              ////
2394
//// You should have received a copy of the GNU Lesser General    ////
2395
//// Public License along with this source; if not, download it   ////
2396
//// from http://www.opencores.org/lgpl.shtml                     ////
2397
////                                                              ////
2398
//////////////////////////////////////////////////////////////////////
2399 22 unneback
 
2400
// LFSR counter
2401 27 unneback
 
2402 40 unneback
`define MODULE cnt_lfsr_ce_q
2403
module `BASE`MODULE (
2404
`undef MODULE
2405
 cke, q, rst, clk);
2406
 
2407 27 unneback
   parameter length = 4;
2408
   input cke;
2409
   output [length:1] q;
2410
   input rst;
2411
   input clk;
2412
 
2413
   parameter clear_value = 0;
2414
   parameter set_value = 1;
2415
   parameter wrap_value = 8;
2416
   parameter level1_value = 15;
2417
 
2418
   reg  [length:1] qi;
2419
   reg lfsr_fb;
2420
   wire [length:1] q_next;
2421
   reg [32:1] polynom;
2422
   integer i;
2423
 
2424
   always @ (qi)
2425
   begin
2426
        case (length)
2427
         2: polynom = 32'b11;                               // 0x3
2428
         3: polynom = 32'b110;                              // 0x6
2429
         4: polynom = 32'b1100;                             // 0xC
2430
         5: polynom = 32'b10100;                            // 0x14
2431
         6: polynom = 32'b110000;                           // 0x30
2432
         7: polynom = 32'b1100000;                          // 0x60
2433
         8: polynom = 32'b10111000;                         // 0xb8
2434
         9: polynom = 32'b100010000;                        // 0x110
2435
        10: polynom = 32'b1001000000;                       // 0x240
2436
        11: polynom = 32'b10100000000;                      // 0x500
2437
        12: polynom = 32'b100000101001;                     // 0x829
2438
        13: polynom = 32'b1000000001100;                    // 0x100C
2439
        14: polynom = 32'b10000000010101;                   // 0x2015
2440
        15: polynom = 32'b110000000000000;                  // 0x6000
2441
        16: polynom = 32'b1101000000001000;                 // 0xD008
2442
        17: polynom = 32'b10010000000000000;                // 0x12000
2443
        18: polynom = 32'b100000010000000000;               // 0x20400
2444
        19: polynom = 32'b1000000000000100011;              // 0x40023
2445 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2446 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2447
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2448
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2449
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2450
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2451
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2452
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2453
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2454
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2455
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2456
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2457
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2458
        default: polynom = 32'b0;
2459
        endcase
2460
        lfsr_fb = qi[length];
2461
        for (i=length-1; i>=1; i=i-1) begin
2462
            if (polynom[i])
2463
                lfsr_fb = lfsr_fb  ~^ qi[i];
2464
        end
2465
    end
2466
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2467
 
2468
   always @ (posedge clk or posedge rst)
2469
     if (rst)
2470
       qi <= {length{1'b0}};
2471
     else
2472
     if (cke)
2473
       qi <= q_next;
2474
 
2475
   assign q = qi;
2476
 
2477
endmodule
2478 40 unneback
`endif
2479
`ifdef CNT_LFSR_CE_CLEAR_Q
2480 27 unneback
//////////////////////////////////////////////////////////////////////
2481
////                                                              ////
2482
////  Versatile counter                                           ////
2483
////                                                              ////
2484
////  Description                                                 ////
2485
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2486
////  counter                                                     ////
2487
////                                                              ////
2488
////  To Do:                                                      ////
2489
////   - add LFSR with more taps                                  ////
2490
////                                                              ////
2491
////  Author(s):                                                  ////
2492
////      - Michael Unneback, unneback@opencores.org              ////
2493
////        ORSoC AB                                              ////
2494
////                                                              ////
2495
//////////////////////////////////////////////////////////////////////
2496
////                                                              ////
2497
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2498
////                                                              ////
2499
//// This source file may be used and distributed without         ////
2500
//// restriction provided that this copyright statement is not    ////
2501
//// removed from the file and that any derivative work contains  ////
2502
//// the original copyright notice and the associated disclaimer. ////
2503
////                                                              ////
2504
//// This source file is free software; you can redistribute it   ////
2505
//// and/or modify it under the terms of the GNU Lesser General   ////
2506
//// Public License as published by the Free Software Foundation; ////
2507
//// either version 2.1 of the License, or (at your option) any   ////
2508
//// later version.                                               ////
2509
////                                                              ////
2510
//// This source is distributed in the hope that it will be       ////
2511
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2512
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2513
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2514
//// details.                                                     ////
2515
////                                                              ////
2516
//// You should have received a copy of the GNU Lesser General    ////
2517
//// Public License along with this source; if not, download it   ////
2518
//// from http://www.opencores.org/lgpl.shtml                     ////
2519
////                                                              ////
2520
//////////////////////////////////////////////////////////////////////
2521
 
2522
// LFSR counter
2523
 
2524 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2525
module `BASE`MODULE (
2526
`undef MODULE
2527
 clear, cke, q, rst, clk);
2528
 
2529 27 unneback
   parameter length = 4;
2530
   input clear;
2531
   input cke;
2532
   output [length:1] q;
2533
   input rst;
2534
   input clk;
2535
 
2536
   parameter clear_value = 0;
2537
   parameter set_value = 1;
2538
   parameter wrap_value = 8;
2539
   parameter level1_value = 15;
2540
 
2541
   reg  [length:1] qi;
2542
   reg lfsr_fb;
2543
   wire [length:1] q_next;
2544
   reg [32:1] polynom;
2545
   integer i;
2546
 
2547
   always @ (qi)
2548
   begin
2549
        case (length)
2550
         2: polynom = 32'b11;                               // 0x3
2551
         3: polynom = 32'b110;                              // 0x6
2552
         4: polynom = 32'b1100;                             // 0xC
2553
         5: polynom = 32'b10100;                            // 0x14
2554
         6: polynom = 32'b110000;                           // 0x30
2555
         7: polynom = 32'b1100000;                          // 0x60
2556
         8: polynom = 32'b10111000;                         // 0xb8
2557
         9: polynom = 32'b100010000;                        // 0x110
2558
        10: polynom = 32'b1001000000;                       // 0x240
2559
        11: polynom = 32'b10100000000;                      // 0x500
2560
        12: polynom = 32'b100000101001;                     // 0x829
2561
        13: polynom = 32'b1000000001100;                    // 0x100C
2562
        14: polynom = 32'b10000000010101;                   // 0x2015
2563
        15: polynom = 32'b110000000000000;                  // 0x6000
2564
        16: polynom = 32'b1101000000001000;                 // 0xD008
2565
        17: polynom = 32'b10010000000000000;                // 0x12000
2566
        18: polynom = 32'b100000010000000000;               // 0x20400
2567
        19: polynom = 32'b1000000000000100011;              // 0x40023
2568 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2569 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2570
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2571
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2572
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2573
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2574
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2575
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2576
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2577
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2578
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2579
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2580
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2581
        default: polynom = 32'b0;
2582
        endcase
2583
        lfsr_fb = qi[length];
2584
        for (i=length-1; i>=1; i=i-1) begin
2585
            if (polynom[i])
2586
                lfsr_fb = lfsr_fb  ~^ qi[i];
2587
        end
2588
    end
2589
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2590
 
2591
   always @ (posedge clk or posedge rst)
2592
     if (rst)
2593
       qi <= {length{1'b0}};
2594
     else
2595
     if (cke)
2596
       qi <= q_next;
2597
 
2598
   assign q = qi;
2599
 
2600
endmodule
2601 40 unneback
`endif
2602
`ifdef CNT_LFSR_CE_Q_ZQ
2603 27 unneback
//////////////////////////////////////////////////////////////////////
2604
////                                                              ////
2605
////  Versatile counter                                           ////
2606
////                                                              ////
2607
////  Description                                                 ////
2608
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2609
////  counter                                                     ////
2610
////                                                              ////
2611
////  To Do:                                                      ////
2612
////   - add LFSR with more taps                                  ////
2613
////                                                              ////
2614
////  Author(s):                                                  ////
2615
////      - Michael Unneback, unneback@opencores.org              ////
2616
////        ORSoC AB                                              ////
2617
////                                                              ////
2618
//////////////////////////////////////////////////////////////////////
2619
////                                                              ////
2620
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2621
////                                                              ////
2622
//// This source file may be used and distributed without         ////
2623
//// restriction provided that this copyright statement is not    ////
2624
//// removed from the file and that any derivative work contains  ////
2625
//// the original copyright notice and the associated disclaimer. ////
2626
////                                                              ////
2627
//// This source file is free software; you can redistribute it   ////
2628
//// and/or modify it under the terms of the GNU Lesser General   ////
2629
//// Public License as published by the Free Software Foundation; ////
2630
//// either version 2.1 of the License, or (at your option) any   ////
2631
//// later version.                                               ////
2632
////                                                              ////
2633
//// This source is distributed in the hope that it will be       ////
2634
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2635
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2636
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2637
//// details.                                                     ////
2638
////                                                              ////
2639
//// You should have received a copy of the GNU Lesser General    ////
2640
//// Public License along with this source; if not, download it   ////
2641
//// from http://www.opencores.org/lgpl.shtml                     ////
2642
////                                                              ////
2643
//////////////////////////////////////////////////////////////////////
2644
 
2645
// LFSR counter
2646 22 unneback
 
2647 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
2648
module `BASE`MODULE (
2649
`undef MODULE
2650
 cke, q, zq, rst, clk);
2651
 
2652 22 unneback
   parameter length = 4;
2653
   input cke;
2654
   output [length:1] q;
2655
   output reg zq;
2656
   input rst;
2657
   input clk;
2658
 
2659
   parameter clear_value = 0;
2660
   parameter set_value = 1;
2661
   parameter wrap_value = 8;
2662
   parameter level1_value = 15;
2663
 
2664
   reg  [length:1] qi;
2665
   reg lfsr_fb;
2666
   wire [length:1] q_next;
2667
   reg [32:1] polynom;
2668
   integer i;
2669
 
2670
   always @ (qi)
2671
   begin
2672
        case (length)
2673
         2: polynom = 32'b11;                               // 0x3
2674
         3: polynom = 32'b110;                              // 0x6
2675
         4: polynom = 32'b1100;                             // 0xC
2676
         5: polynom = 32'b10100;                            // 0x14
2677
         6: polynom = 32'b110000;                           // 0x30
2678
         7: polynom = 32'b1100000;                          // 0x60
2679
         8: polynom = 32'b10111000;                         // 0xb8
2680
         9: polynom = 32'b100010000;                        // 0x110
2681
        10: polynom = 32'b1001000000;                       // 0x240
2682
        11: polynom = 32'b10100000000;                      // 0x500
2683
        12: polynom = 32'b100000101001;                     // 0x829
2684
        13: polynom = 32'b1000000001100;                    // 0x100C
2685
        14: polynom = 32'b10000000010101;                   // 0x2015
2686
        15: polynom = 32'b110000000000000;                  // 0x6000
2687
        16: polynom = 32'b1101000000001000;                 // 0xD008
2688
        17: polynom = 32'b10010000000000000;                // 0x12000
2689
        18: polynom = 32'b100000010000000000;               // 0x20400
2690
        19: polynom = 32'b1000000000000100011;              // 0x40023
2691 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2692 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2693
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2694
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2695
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2696
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2697
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2698
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2699
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2700
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2701
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2702
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2703
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2704
        default: polynom = 32'b0;
2705
        endcase
2706
        lfsr_fb = qi[length];
2707
        for (i=length-1; i>=1; i=i-1) begin
2708
            if (polynom[i])
2709
                lfsr_fb = lfsr_fb  ~^ qi[i];
2710
        end
2711
    end
2712
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2713
 
2714
   always @ (posedge clk or posedge rst)
2715
     if (rst)
2716
       qi <= {length{1'b0}};
2717
     else
2718
     if (cke)
2719
       qi <= q_next;
2720
 
2721
   assign q = qi;
2722
 
2723
 
2724
   always @ (posedge clk or posedge rst)
2725
     if (rst)
2726
       zq <= 1'b1;
2727
     else
2728
     if (cke)
2729
       zq <= q_next == {length{1'b0}};
2730
endmodule
2731 40 unneback
`endif
2732
`ifdef CNT_LFSR_CE_REW_L1
2733 22 unneback
//////////////////////////////////////////////////////////////////////
2734
////                                                              ////
2735
////  Versatile counter                                           ////
2736
////                                                              ////
2737
////  Description                                                 ////
2738
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2739
////  counter                                                     ////
2740
////                                                              ////
2741
////  To Do:                                                      ////
2742
////   - add LFSR with more taps                                  ////
2743
////                                                              ////
2744
////  Author(s):                                                  ////
2745
////      - Michael Unneback, unneback@opencores.org              ////
2746
////        ORSoC AB                                              ////
2747
////                                                              ////
2748
//////////////////////////////////////////////////////////////////////
2749
////                                                              ////
2750
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2751
////                                                              ////
2752
//// This source file may be used and distributed without         ////
2753
//// restriction provided that this copyright statement is not    ////
2754
//// removed from the file and that any derivative work contains  ////
2755
//// the original copyright notice and the associated disclaimer. ////
2756
////                                                              ////
2757
//// This source file is free software; you can redistribute it   ////
2758
//// and/or modify it under the terms of the GNU Lesser General   ////
2759
//// Public License as published by the Free Software Foundation; ////
2760
//// either version 2.1 of the License, or (at your option) any   ////
2761
//// later version.                                               ////
2762
////                                                              ////
2763
//// This source is distributed in the hope that it will be       ////
2764
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2765
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2766
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2767
//// details.                                                     ////
2768
////                                                              ////
2769
//// You should have received a copy of the GNU Lesser General    ////
2770
//// Public License along with this source; if not, download it   ////
2771
//// from http://www.opencores.org/lgpl.shtml                     ////
2772
////                                                              ////
2773
//////////////////////////////////////////////////////////////////////
2774 6 unneback
 
2775
// LFSR counter
2776
 
2777 40 unneback
`define MODULE cnt_lfsr_ce_rew_l1
2778
module `BASE`MODULE (
2779
`undef MODULE
2780
 cke, rew, level1, rst, clk);
2781
 
2782 6 unneback
   parameter length = 4;
2783
   input cke;
2784
   input rew;
2785
   output reg level1;
2786
   input rst;
2787
   input clk;
2788
 
2789
   parameter clear_value = 0;
2790
   parameter set_value = 1;
2791
   parameter wrap_value = 8;
2792
   parameter level1_value = 15;
2793
 
2794 29 unneback
   wire clear;
2795 30 unneback
   assign clear = 1'b0;
2796 6 unneback
   reg  [length:1] qi;
2797
   reg lfsr_fb, lfsr_fb_rew;
2798
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2799
   reg [32:1] polynom_rew;
2800
   integer j;
2801
   reg [32:1] polynom;
2802
   integer i;
2803
 
2804
   always @ (qi)
2805
   begin
2806
        case (length)
2807
         2: polynom = 32'b11;                               // 0x3
2808
         3: polynom = 32'b110;                              // 0x6
2809
         4: polynom = 32'b1100;                             // 0xC
2810
         5: polynom = 32'b10100;                            // 0x14
2811
         6: polynom = 32'b110000;                           // 0x30
2812
         7: polynom = 32'b1100000;                          // 0x60
2813
         8: polynom = 32'b10111000;                         // 0xb8
2814
         9: polynom = 32'b100010000;                        // 0x110
2815
        10: polynom = 32'b1001000000;                       // 0x240
2816
        11: polynom = 32'b10100000000;                      // 0x500
2817
        12: polynom = 32'b100000101001;                     // 0x829
2818