OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 49

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 44 unneback
`ifdef ACTEL
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
`endif
8
 
9 40 unneback
`ifdef ALL
10
 
11
`define GBUF
12
`define SYNC_RST
13
`define PLL
14
 
15
`define MULTS
16
`define MULTS18X18
17
`define MULT
18
`define SHIFT_UNIT_32
19
`define LOGIC_UNIT
20
 
21
`define CNT_SHREG_WRAP
22
`define CNT_SHREG_CE_WRAP
23
`define CNT_SHREG_CE_CLEAR
24
`define CNT_SHREG_CE_CLEAR_WRAP
25
 
26
`define MUX_ANDOR
27
`define MUX2_ANDOR
28
`define MUX3_ANDOR
29
`define MUX4_ANDOR
30
`define MUX5_ANDOR
31
`define MUX6_ANDOR
32 43 unneback
`define PARITY
33 40 unneback
 
34
`define ROM_INIT
35
`define RAM
36
`define RAM_BE
37
`define DPRAM_1R1W
38
`define DPRAM_2R1W
39
`define DPRAM_2R2W
40
`define FIFO_1R1W_FILL_LEVEL_SYNC
41
`define FIFO_2R2W_SYNC_SIMPLEX
42
`define FIFO_CMP_ASYNC
43
`define FIFO_1R1W_ASYNC
44
`define FIFO_2R2W_ASYNC
45
`define FIFO_2R2W_ASYNC_SIMPLEX
46 48 unneback
`define REG_FILE
47 40 unneback
 
48
`define DFF
49
`define DFF_ARRAY
50
`define DFF_CE
51
`define DFF_CE_CLEAR
52
`define DF_CE_SET
53
`define SPR
54
`define SRP
55
`define DFF_SR
56
`define LATCH
57
`define SHREG
58
`define SHREG_CE
59
`define DELAY
60
`define DELAY_EMPTYFLAG
61
 
62
`define WB3WB3_BRIDGE
63
`define WB3_ARBITER_TYPE1
64 49 unneback
`define WB_B4_RAM_BE
65 48 unneback
`define WB_B4_ROM
66 40 unneback
`define WB_BOOT_ROM
67
`define WB_DPRAM
68
 
69 44 unneback
`define IO_DFF_OE
70
`define O_DFF
71
 
72 40 unneback
`endif
73
 
74
`ifdef PLL
75
`ifndef SYNC_RST
76
`define SYNC_RST
77
`endif
78
`endif
79
 
80
`ifdef SYNC_RST
81
`ifndef GBUF
82
`define GBUF
83
`endif
84
`endif
85
 
86
`ifdef WB_DPRAM
87
`ifndef DPRAM_2R2W
88
`define DPRAM_2R2W
89
`endif
90
`ifndef SPR
91
`define SPR
92
`endif
93
`endif
94
 
95
`ifdef WB3_ARBITER_TYPE1
96 42 unneback
`ifndef SPR
97
`define SPR
98
`endif
99 40 unneback
`ifndef MUX_ANDOR
100
`define MUX_ANDOR
101
`endif
102
`endif
103
 
104
`ifdef WB3WB3_BRIDGE
105
`ifndef CNT_SHREG_CE_CLEAR
106
`define CNT_SHREG_CE_CLEAR
107
`endif
108
`ifndef DFF
109
`define DFF
110
`endif
111
`ifndef DFF_CE
112
`define DFF_CE
113
`endif
114
`ifndef CNT_SHREG_CE_CLEAR
115
`define CNT_SHREG_CE_CLEAR
116
`endif
117
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
118
`define FIFO_2R2W_ASYNC_SIMPLEX
119
`endif
120
`endif
121
 
122
`ifdef MULTS18X18
123
`ifndef MULTS
124
`define MULTS
125
`endif
126
`endif
127
 
128
`ifdef SHIFT_UNIT_32
129
`ifndef MULTS
130
`define MULTS
131
`endif
132
`endif
133
 
134
`ifdef MUX2_ANDOR
135
`ifndef MUX_ANDOR
136
`define MUX_ANDOR
137
`endif
138
`endif
139
 
140
`ifdef MUX3_ANDOR
141
`ifndef MUX_ANDOR
142
`define MUX_ANDOR
143
`endif
144
`endif
145
 
146
`ifdef MUX4_ANDOR
147
`ifndef MUX_ANDOR
148
`define MUX_ANDOR
149
`endif
150
`endif
151
 
152
`ifdef MUX5_ANDOR
153
`ifndef MUX_ANDOR
154
`define MUX_ANDOR
155
`endif
156
`endif
157
 
158
`ifdef MUX6_ANDOR
159
`ifndef MUX_ANDOR
160
`define MUX_ANDOR
161
`endif
162
`endif
163
 
164
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
165
`ifndef CNT_BIN_CE
166
`define CNT_BIN_CE
167
`endif
168
`ifndef DPRAM_1R1W
169
`define DPRAM_1R1W
170
`endif
171
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
172
`define CNT_BIN_CE_REW_Q_ZQ_L1
173
`endif
174
`endif
175
 
176
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
177
`ifndef CNT_LFSR_CE
178
`define CNT_LFSR_CE
179
`endif
180
`ifndef DPRAM_2R2W
181
`define DPRAM_2R2W
182
`endif
183
`ifndef CNT_BIN_CE_REW_ZQ_L1
184
`define CNT_BIN_CE_REW_ZQ_L1
185
`endif
186
`endif
187
 
188
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
189
`ifndef CNT_GRAY_CE_BIN
190
`define CNT_GRAY_CE_BIN
191
`endif
192
`ifndef DPRAM_2R2W
193
`define DPRAM_2R2W
194
`endif
195
`ifndef FIFO_CMP_ASYNC
196
`define FIFO_CMP_ASYNC
197
`endif
198
`endif
199
 
200
`ifdef FIFO_2R2W_ASYNC
201
`ifndef FIFO_1R1W_ASYNC
202
`define FIFO_1R1W_ASYNC
203
`endif
204
`endif
205
 
206
`ifdef FIFO_1R1W_ASYNC
207
`ifndef CNT_GRAY_CE_BIN
208
`define CNT_GRAY_CE_BIN
209
`endif
210
`ifndef DPRAM_1R1W
211
`define DPRAM_1R1W
212
`endif
213
`ifndef FIFO_CMP_ASYNC
214
`define FIFO_CMP_ASYNC
215
`endif
216
`endif
217
 
218
`ifdef FIFO_CMP_ASYNC
219
`ifndef DFF_SR
220
`define DFF_SR
221
`endif
222
`ifndef DFF
223
`define DFF
224
`endif
225
`endif
226 48 unneback
 
227
`ifdef REG_FILE
228
`ifndef DPRAM_1R1W
229
`define DPRAM_1R1W
230
`endif
231
`endif
232 6 unneback
//////////////////////////////////////////////////////////////////////
233
////                                                              ////
234
////  Versatile library, clock and reset                          ////
235
////                                                              ////
236
////  Description                                                 ////
237
////  Logic related to clock and reset                            ////
238
////                                                              ////
239
////                                                              ////
240
////  To Do:                                                      ////
241
////   - add more different registers                             ////
242
////                                                              ////
243
////  Author(s):                                                  ////
244
////      - Michael Unneback, unneback@opencores.org              ////
245
////        ORSoC AB                                              ////
246
////                                                              ////
247
//////////////////////////////////////////////////////////////////////
248
////                                                              ////
249
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
250
////                                                              ////
251
//// This source file may be used and distributed without         ////
252
//// restriction provided that this copyright statement is not    ////
253
//// removed from the file and that any derivative work contains  ////
254
//// the original copyright notice and the associated disclaimer. ////
255
////                                                              ////
256
//// This source file is free software; you can redistribute it   ////
257
//// and/or modify it under the terms of the GNU Lesser General   ////
258
//// Public License as published by the Free Software Foundation; ////
259
//// either version 2.1 of the License, or (at your option) any   ////
260
//// later version.                                               ////
261
////                                                              ////
262
//// This source is distributed in the hope that it will be       ////
263
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
264
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
265
//// PURPOSE.  See the GNU Lesser General Public License for more ////
266
//// details.                                                     ////
267
////                                                              ////
268
//// You should have received a copy of the GNU Lesser General    ////
269
//// Public License along with this source; if not, download it   ////
270
//// from http://www.opencores.org/lgpl.shtml                     ////
271
////                                                              ////
272
//////////////////////////////////////////////////////////////////////
273
 
274 48 unneback
`ifdef ACTEL
275
`ifdef GBUF
276
`timescale 1 ns/100 ps
277 6 unneback
// Global buffer
278
// usage:
279
// use to enable global buffers for high fan out signals such as clock and reset
280
// Version: 8.4 8.4.0.33
281
module gbuf(GL,CLK);
282
output GL;
283
input  CLK;
284
 
285
    wire GND;
286
 
287
    GND GND_1_net(.Y(GND));
288
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
289
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
290
 
291
endmodule
292
`timescale 1 ns/1 ns
293 40 unneback
`define MODULE gbuf
294
module `BASE`MODULE ( i, o);
295
`undef MODULE
296 6 unneback
input i;
297
output o;
298
`ifdef SIM_GBUF
299
assign o=i;
300
`else
301
gbuf gbuf_i0 ( .CLK(i), .GL(o));
302
`endif
303
endmodule
304 40 unneback
`endif
305 33 unneback
 
306 6 unneback
`else
307 33 unneback
 
308 40 unneback
`ifdef ALTERA
309
`ifdef GBUF
310 21 unneback
//altera
311 40 unneback
`define MODULE gbuf
312
module `BASE`MODULE ( i, o);
313
`undef MODULE
314 33 unneback
input i;
315
output o;
316
assign o = i;
317
endmodule
318 40 unneback
`endif
319 33 unneback
 
320 6 unneback
`else
321
 
322 40 unneback
`ifdef GBUF
323 6 unneback
`timescale 1 ns/100 ps
324 40 unneback
`define MODULE
325
module `BASE`MODULE ( i, o);
326
`undef MODULE
327 6 unneback
input i;
328
output o;
329
assign o = i;
330
endmodule
331 40 unneback
`endif
332 6 unneback
`endif // ALTERA
333
`endif //ACTEL
334
 
335 40 unneback
`ifdef SYNC_RST
336 6 unneback
// sync reset
337 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
338 6 unneback
// output active high global reset sync with two DFFs 
339
`timescale 1 ns/100 ps
340 40 unneback
`define MODULE sync_rst
341
module `BASE`MODULE ( rst_n_i, rst_o, clk);
342
`undef MODULE
343 6 unneback
input rst_n_i, clk;
344
output rst_o;
345 18 unneback
reg [1:0] tmp;
346 6 unneback
always @ (posedge clk or negedge rst_n_i)
347
if (!rst_n_i)
348 17 unneback
        tmp <= 2'b11;
349 6 unneback
else
350 33 unneback
        tmp <= {1'b0,tmp[1]};
351 40 unneback
`define MODULE gbuf
352
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
353
`undef MODULE
354 6 unneback
endmodule
355 40 unneback
`endif
356 6 unneback
 
357 40 unneback
`ifdef PLL
358 6 unneback
// vl_pll
359
`ifdef ACTEL
360 32 unneback
///////////////////////////////////////////////////////////////////////////////
361 17 unneback
`timescale 1 ps/1 ps
362 40 unneback
`define MODULE pll
363
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
364
`undef MODULE
365 6 unneback
parameter index = 0;
366
parameter number_of_clk = 1;
367 17 unneback
parameter period_time_0 = 20000;
368
parameter period_time_1 = 20000;
369
parameter period_time_2 = 20000;
370
parameter lock_delay = 2000000;
371 6 unneback
input clk_i, rst_n_i;
372
output lock;
373
output reg [0:number_of_clk-1] clk_o;
374
output [0:number_of_clk-1] rst_o;
375
 
376
`ifdef SIM_PLL
377
 
378
always
379
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
380
 
381
generate if (number_of_clk > 1)
382
always
383
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
384
endgenerate
385
 
386
generate if (number_of_clk > 2)
387
always
388
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
389
endgenerate
390
 
391
genvar i;
392
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
393
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
394
end
395
endgenerate
396
 
397
assign #lock_delay lock = rst_n_i;
398
 
399
endmodule
400
`else
401
generate if (number_of_clk==1 & index==0) begin
402
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
403
end
404
endgenerate // index==0
405
generate if (number_of_clk==1 & index==1) begin
406
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
407
end
408
endgenerate // index==1
409
generate if (number_of_clk==1 & index==2) begin
410
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
411
end
412
endgenerate // index==2
413
generate if (number_of_clk==1 & index==3) begin
414
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
415
end
416
endgenerate // index==0
417
 
418
generate if (number_of_clk==2 & index==0) begin
419
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
420
end
421
endgenerate // index==0
422
generate if (number_of_clk==2 & index==1) begin
423
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
424
end
425
endgenerate // index==1
426
generate if (number_of_clk==2 & index==2) begin
427
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
428
end
429
endgenerate // index==2
430
generate if (number_of_clk==2 & index==3) begin
431
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
432
end
433
endgenerate // index==0
434
 
435
generate if (number_of_clk==3 & index==0) begin
436
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
437
end
438
endgenerate // index==0
439
generate if (number_of_clk==3 & index==1) begin
440
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
441
end
442
endgenerate // index==1
443
generate if (number_of_clk==3 & index==2) begin
444
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
445
end
446
endgenerate // index==2
447
generate if (number_of_clk==3 & index==3) begin
448
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
449
end
450
endgenerate // index==0
451
 
452
genvar i;
453
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
454 40 unneback
`define MODULE sync_rst
455
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
456
`undef MODULE
457 6 unneback
end
458
endgenerate
459
endmodule
460
`endif
461 32 unneback
///////////////////////////////////////////////////////////////////////////////
462 6 unneback
 
463
`else
464
 
465 32 unneback
///////////////////////////////////////////////////////////////////////////////
466 6 unneback
`ifdef ALTERA
467
 
468 32 unneback
`timescale 1 ps/1 ps
469 40 unneback
`define MODULE pll
470
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
471
`undef MODULE
472 32 unneback
parameter index = 0;
473
parameter number_of_clk = 1;
474
parameter period_time_0 = 20000;
475
parameter period_time_1 = 20000;
476
parameter period_time_2 = 20000;
477
parameter period_time_3 = 20000;
478
parameter period_time_4 = 20000;
479
parameter lock_delay = 2000000;
480
input clk_i, rst_n_i;
481
output lock;
482
output reg [0:number_of_clk-1] clk_o;
483
output [0:number_of_clk-1] rst_o;
484
 
485
`ifdef SIM_PLL
486
 
487
always
488
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
489
 
490
generate if (number_of_clk > 1)
491
always
492
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
493
endgenerate
494
 
495
generate if (number_of_clk > 2)
496
always
497
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
498
endgenerate
499
 
500 33 unneback
generate if (number_of_clk > 3)
501 32 unneback
always
502
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
503
endgenerate
504
 
505 33 unneback
generate if (number_of_clk > 4)
506 32 unneback
always
507
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
508
endgenerate
509
 
510
genvar i;
511
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
512
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
513
end
514
endgenerate
515
 
516 33 unneback
//assign #lock_delay lock = rst_n_i;
517
assign lock = rst_n_i;
518 32 unneback
 
519
endmodule
520 6 unneback
`else
521
 
522 33 unneback
`ifdef VL_PLL0
523
`ifdef VL_PLL0_CLK1
524
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
525
`endif
526
`ifdef VL_PLL0_CLK2
527
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
528
`endif
529
`ifdef VL_PLL0_CLK3
530
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
531
`endif
532
`ifdef VL_PLL0_CLK4
533
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
534
`endif
535
`ifdef VL_PLL0_CLK5
536
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
537
`endif
538
`endif
539 32 unneback
 
540 33 unneback
`ifdef VL_PLL1
541
`ifdef VL_PLL1_CLK1
542
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
543
`endif
544
`ifdef VL_PLL1_CLK2
545
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
546
`endif
547
`ifdef VL_PLL1_CLK3
548
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
549
`endif
550
`ifdef VL_PLL1_CLK4
551
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
552
`endif
553
`ifdef VL_PLL1_CLK5
554
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
555
`endif
556
`endif
557 32 unneback
 
558 33 unneback
`ifdef VL_PLL2
559
`ifdef VL_PLL2_CLK1
560
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
561
`endif
562
`ifdef VL_PLL2_CLK2
563
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
564
`endif
565
`ifdef VL_PLL2_CLK3
566
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
567
`endif
568
`ifdef VL_PLL2_CLK4
569
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
570
`endif
571
`ifdef VL_PLL2_CLK5
572
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
573
`endif
574
`endif
575 32 unneback
 
576 33 unneback
`ifdef VL_PLL3
577
`ifdef VL_PLL3_CLK1
578
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
579
`endif
580
`ifdef VL_PLL3_CLK2
581
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
582
`endif
583
`ifdef VL_PLL3_CLK3
584
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
585
`endif
586
`ifdef VL_PLL3_CLK4
587
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
588
`endif
589
`ifdef VL_PLL3_CLK5
590
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
591
`endif
592
`endif
593 32 unneback
 
594
genvar i;
595
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
596 40 unneback
`define MODULE sync_rst
597
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
598
`undef MODULE
599 32 unneback
end
600
endgenerate
601
endmodule
602
`endif
603
///////////////////////////////////////////////////////////////////////////////
604
 
605
`else
606
 
607 6 unneback
// generic PLL
608 17 unneback
`timescale 1 ps/1 ps
609 40 unneback
`define MODULE pll
610
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
611
`undef MODULE
612 6 unneback
parameter index = 0;
613
parameter number_of_clk = 1;
614 17 unneback
parameter period_time_0 = 20000;
615
parameter period_time_1 = 20000;
616
parameter period_time_2 = 20000;
617 6 unneback
parameter lock_delay = 2000;
618
input clk_i, rst_n_i;
619
output lock;
620
output reg [0:number_of_clk-1] clk_o;
621
output [0:number_of_clk-1] rst_o;
622
 
623
always
624
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
625
 
626
generate if (number_of_clk > 1)
627
always
628
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
629
endgenerate
630
 
631
generate if (number_of_clk > 2)
632
always
633
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
634
endgenerate
635
 
636
genvar i;
637
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
638 40 unneback
`define MODULE sync_rst
639
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
640
`undef MODULE
641 6 unneback
end
642
endgenerate
643
 
644
assign #lock_delay lock = rst_n_i;
645
 
646
endmodule
647
 
648
`endif //altera
649 17 unneback
`endif //actel
650 40 unneback
`undef MODULE
651
`endif//////////////////////////////////////////////////////////////////////
652 6 unneback
////                                                              ////
653
////  Versatile library, registers                                ////
654
////                                                              ////
655
////  Description                                                 ////
656
////  Different type of registers                                 ////
657
////                                                              ////
658
////                                                              ////
659
////  To Do:                                                      ////
660
////   - add more different registers                             ////
661
////                                                              ////
662
////  Author(s):                                                  ////
663
////      - Michael Unneback, unneback@opencores.org              ////
664
////        ORSoC AB                                              ////
665
////                                                              ////
666
//////////////////////////////////////////////////////////////////////
667
////                                                              ////
668
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
669
////                                                              ////
670
//// This source file may be used and distributed without         ////
671
//// restriction provided that this copyright statement is not    ////
672
//// removed from the file and that any derivative work contains  ////
673
//// the original copyright notice and the associated disclaimer. ////
674
////                                                              ////
675
//// This source file is free software; you can redistribute it   ////
676
//// and/or modify it under the terms of the GNU Lesser General   ////
677
//// Public License as published by the Free Software Foundation; ////
678
//// either version 2.1 of the License, or (at your option) any   ////
679
//// later version.                                               ////
680
////                                                              ////
681
//// This source is distributed in the hope that it will be       ////
682
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
683
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
684
//// PURPOSE.  See the GNU Lesser General Public License for more ////
685
//// details.                                                     ////
686
////                                                              ////
687
//// You should have received a copy of the GNU Lesser General    ////
688
//// Public License along with this source; if not, download it   ////
689
//// from http://www.opencores.org/lgpl.shtml                     ////
690
////                                                              ////
691
//////////////////////////////////////////////////////////////////////
692
 
693 40 unneback
`ifdef DFF
694
`define MODULE dff
695
module `BASE`MODULE ( d, q, clk, rst);
696
`undef MODULE
697 6 unneback
        parameter width = 1;
698
        parameter reset_value = 0;
699
 
700
        input [width-1:0] d;
701
        input clk, rst;
702
        output reg [width-1:0] q;
703
 
704
        always @ (posedge clk or posedge rst)
705
        if (rst)
706
                q <= reset_value;
707
        else
708
                q <= d;
709
 
710
endmodule
711 40 unneback
`endif
712 6 unneback
 
713 40 unneback
`ifdef DFF_ARRAY
714
`define MODULE dff_array
715
module `BASE`MODULE ( d, q, clk, rst);
716
`undef MODULE
717 6 unneback
 
718
        parameter width = 1;
719
        parameter depth = 2;
720
        parameter reset_value = 1'b0;
721
 
722
        input [width-1:0] d;
723
        input clk, rst;
724
        output [width-1:0] q;
725
        reg  [0:depth-1] q_tmp [width-1:0];
726
        integer i;
727
        always @ (posedge clk or posedge rst)
728
        if (rst) begin
729
            for (i=0;i<depth;i=i+1)
730
                q_tmp[i] <= {width{reset_value}};
731
        end else begin
732
            q_tmp[0] <= d;
733
            for (i=1;i<depth;i=i+1)
734
                q_tmp[i] <= q_tmp[i-1];
735
        end
736
 
737
    assign q = q_tmp[depth-1];
738
 
739
endmodule
740 40 unneback
`endif
741 6 unneback
 
742 40 unneback
`ifdef DFF_CE
743
`define MODULE dff_ce
744
module `BASE`MODULE ( d, ce, q, clk, rst);
745
`undef MODULE
746 6 unneback
 
747
        parameter width = 1;
748
        parameter reset_value = 0;
749
 
750
        input [width-1:0] d;
751
        input ce, clk, rst;
752
        output reg [width-1:0] q;
753
 
754
        always @ (posedge clk or posedge rst)
755
        if (rst)
756
                q <= reset_value;
757
        else
758
                if (ce)
759
                        q <= d;
760
 
761
endmodule
762 40 unneback
`endif
763 6 unneback
 
764 40 unneback
`ifdef DFF_CE_CLEAR
765
`define MODULE dff_ce_clear
766
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
767
`undef MODULE
768 8 unneback
 
769
        parameter width = 1;
770
        parameter reset_value = 0;
771
 
772
        input [width-1:0] d;
773 10 unneback
        input ce, clear, clk, rst;
774 8 unneback
        output reg [width-1:0] q;
775
 
776
        always @ (posedge clk or posedge rst)
777
        if (rst)
778
            q <= reset_value;
779
        else
780
            if (ce)
781
                if (clear)
782
                    q <= {width{1'b0}};
783
                else
784
                    q <= d;
785
 
786
endmodule
787 40 unneback
`endif
788 8 unneback
 
789 40 unneback
`ifdef DF_CE_SET
790
`define MODULE dff_ce_set
791
module `BASE`MODULE ( d, ce, set, q, clk, rst);
792
`undef MODULE
793 24 unneback
 
794
        parameter width = 1;
795
        parameter reset_value = 0;
796
 
797
        input [width-1:0] d;
798
        input ce, set, clk, rst;
799
        output reg [width-1:0] q;
800
 
801
        always @ (posedge clk or posedge rst)
802
        if (rst)
803
            q <= reset_value;
804
        else
805
            if (ce)
806
                if (set)
807
                    q <= {width{1'b1}};
808
                else
809
                    q <= d;
810
 
811
endmodule
812 40 unneback
`endif
813 24 unneback
 
814 40 unneback
`ifdef SPR
815
`define MODULE spr
816
module `BASE`MODULE ( sp, r, q, clk, rst);
817
`undef MODULE
818
 
819 29 unneback
        parameter width = 1;
820
        parameter reset_value = 0;
821
 
822
        input sp, r;
823
        output reg q;
824
        input clk, rst;
825
 
826
        always @ (posedge clk or posedge rst)
827
        if (rst)
828
            q <= reset_value;
829
        else
830
            if (sp)
831
                q <= 1'b1;
832
            else if (r)
833
                q <= 1'b0;
834
 
835
endmodule
836 40 unneback
`endif
837 29 unneback
 
838 40 unneback
`ifdef SRP
839
`define MODULE srp
840
module `BASE`MODULE ( s, rp, q, clk, rst);
841
`undef MODULE
842
 
843 29 unneback
        parameter width = 1;
844
        parameter reset_value = 0;
845
 
846
        input s, rp;
847
        output reg q;
848
        input clk, rst;
849
 
850
        always @ (posedge clk or posedge rst)
851
        if (rst)
852
            q <= reset_value;
853
        else
854
            if (rp)
855
                q <= 1'b0;
856
            else if (s)
857
                q <= 1'b1;
858
 
859
endmodule
860 40 unneback
`endif
861 29 unneback
 
862 40 unneback
`ifdef ALTERA
863 29 unneback
 
864 40 unneback
`ifdef DFF_SR
865 6 unneback
// megafunction wizard: %LPM_FF%
866
// GENERATION: STANDARD
867
// VERSION: WM1.0
868
// MODULE: lpm_ff 
869
 
870
// ============================================================
871
// File Name: dff_sr.v
872
// Megafunction Name(s):
873
//                      lpm_ff
874
//
875
// Simulation Library Files(s):
876
//                      lpm
877
// ============================================================
878
// ************************************************************
879
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
880
//
881
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
882
// ************************************************************
883
 
884
 
885
//Copyright (C) 1991-2010 Altera Corporation
886
//Your use of Altera Corporation's design tools, logic functions 
887
//and other software and tools, and its AMPP partner logic 
888
//functions, and any output files from any of the foregoing 
889
//(including device programming or simulation files), and any 
890
//associated documentation or information are expressly subject 
891
//to the terms and conditions of the Altera Program License 
892
//Subscription Agreement, Altera MegaCore Function License 
893
//Agreement, or other applicable license agreement, including, 
894
//without limitation, that your use is for the sole purpose of 
895
//programming logic devices manufactured by Altera and sold by 
896
//Altera or its authorized distributors.  Please refer to the 
897
//applicable agreement for further details.
898
 
899
 
900
// synopsys translate_off
901
`timescale 1 ps / 1 ps
902
// synopsys translate_on
903 40 unneback
`define MODULE dff_sr
904
module `BASE`MODULE (
905
`undef MODULE
906
 
907 6 unneback
        aclr,
908
        aset,
909
        clock,
910
        data,
911
        q);
912
 
913
        input     aclr;
914
        input     aset;
915
        input     clock;
916
        input     data;
917
        output    q;
918
 
919
        wire [0:0] sub_wire0;
920
        wire [0:0] sub_wire1 = sub_wire0[0:0];
921
        wire  q = sub_wire1;
922
        wire  sub_wire2 = data;
923
        wire  sub_wire3 = sub_wire2;
924
 
925
        lpm_ff  lpm_ff_component (
926
                                .aclr (aclr),
927
                                .clock (clock),
928
                                .data (sub_wire3),
929
                                .aset (aset),
930
                                .q (sub_wire0)
931
                                // synopsys translate_off
932
                                ,
933
                                .aload (),
934
                                .enable (),
935
                                .sclr (),
936
                                .sload (),
937
                                .sset ()
938
                                // synopsys translate_on
939
                                );
940
        defparam
941
                lpm_ff_component.lpm_fftype = "DFF",
942
                lpm_ff_component.lpm_type = "LPM_FF",
943
                lpm_ff_component.lpm_width = 1;
944
 
945
 
946
endmodule
947
 
948
// ============================================================
949
// CNX file retrieval info
950
// ============================================================
951
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
952
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
953
// Retrieval info: PRIVATE: ASET NUMERIC "1"
954
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
955
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
956
// Retrieval info: PRIVATE: DFF NUMERIC "1"
957
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
958
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
959
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
960
// Retrieval info: PRIVATE: SSET NUMERIC "0"
961
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
962
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
963
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
964
// Retrieval info: PRIVATE: nBit NUMERIC "1"
965
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
966
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
967
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
968
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
969
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
970
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
971
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
972
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
973
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
974
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
975
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
976
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
977
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
978
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
979
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
980
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
981
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
982
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
983
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
984
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
985
// Retrieval info: LIB_FILE: lpm
986 40 unneback
`endif
987 6 unneback
 
988
`else
989
 
990 40 unneback
`ifdef DFF_SR
991
`define MODULE dff_sr
992
module `BASE`MODULE ( aclr, aset, clock, data, q);
993
`undef MODULE
994 6 unneback
 
995
    input         aclr;
996
    input         aset;
997
    input         clock;
998
    input         data;
999
    output reg    q;
1000
 
1001
   always @ (posedge clock or posedge aclr or posedge aset)
1002
     if (aclr)
1003
       q <= 1'b0;
1004
     else if (aset)
1005
       q <= 1'b1;
1006
     else
1007
       q <= data;
1008
 
1009
endmodule
1010 40 unneback
`endif
1011 6 unneback
 
1012
`endif
1013
 
1014
// LATCH
1015
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1016
`ifdef ALTERA
1017 40 unneback
 
1018
`ifdef LATCH
1019
`define MODULE latch
1020
module `BASE`MODULE ( d, le, q, clk);
1021
`undef MODULE
1022 6 unneback
input d, le;
1023
output q;
1024
input clk;
1025
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1026
endmodule
1027 40 unneback
`endif
1028
 
1029 6 unneback
`else
1030 40 unneback
 
1031
`ifdef LATCH
1032
`define MODULE latch
1033
module `BASE`MODULE ( d, le, q, clk);
1034
`undef MODULE
1035 6 unneback
input d, le;
1036 48 unneback
input clk;
1037
always @ (le or d)
1038
if le
1039
    d <= q;
1040 6 unneback
endmodule
1041 15 unneback
`endif
1042
 
1043 40 unneback
`endif
1044
 
1045
`ifdef SHREG
1046
`define MODULE shreg
1047
module `BASE`MODULE ( d, q, clk, rst);
1048
`undef MODULE
1049
 
1050 17 unneback
parameter depth = 10;
1051
input d;
1052
output q;
1053
input clk, rst;
1054
 
1055
reg [1:depth] dffs;
1056
 
1057
always @ (posedge clk or posedge rst)
1058
if (rst)
1059
    dffs <= {depth{1'b0}};
1060
else
1061
    dffs <= {d,dffs[1:depth-1]};
1062
assign q = dffs[depth];
1063
endmodule
1064 40 unneback
`endif
1065 17 unneback
 
1066 40 unneback
`ifdef SHREG_CE
1067
`define MODULE shreg_ce
1068
module `BASE`MODULE ( d, ce, q, clk, rst);
1069
`undef MODULE
1070 17 unneback
parameter depth = 10;
1071
input d, ce;
1072
output q;
1073
input clk, rst;
1074
 
1075
reg [1:depth] dffs;
1076
 
1077
always @ (posedge clk or posedge rst)
1078
if (rst)
1079
    dffs <= {depth{1'b0}};
1080
else
1081
    if (ce)
1082
        dffs <= {d,dffs[1:depth-1]};
1083
assign q = dffs[depth];
1084
endmodule
1085 40 unneback
`endif
1086 17 unneback
 
1087 40 unneback
`ifdef DELAY
1088
`define MODULE delay
1089
module `BASE`MODULE ( d, q, clk, rst);
1090
`undef MODULE
1091 15 unneback
parameter depth = 10;
1092
input d;
1093
output q;
1094
input clk, rst;
1095
 
1096
reg [1:depth] dffs;
1097
 
1098
always @ (posedge clk or posedge rst)
1099
if (rst)
1100
    dffs <= {depth{1'b0}};
1101
else
1102
    dffs <= {d,dffs[1:depth-1]};
1103
assign q = dffs[depth];
1104 17 unneback
endmodule
1105 40 unneback
`endif
1106 17 unneback
 
1107 40 unneback
`ifdef DELAY_EMPTYFLAG
1108
`define MODULE delay_emptyflag
1109 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1110 40 unneback
`undef MODULE
1111 17 unneback
parameter depth = 10;
1112
input d;
1113
output q, emptyflag;
1114
input clk, rst;
1115
 
1116
reg [1:depth] dffs;
1117
 
1118
always @ (posedge clk or posedge rst)
1119
if (rst)
1120
    dffs <= {depth{1'b0}};
1121
else
1122
    dffs <= {d,dffs[1:depth-1]};
1123
assign q = dffs[depth];
1124
assign emptyflag = !(|dffs);
1125
endmodule
1126 40 unneback
`endif
1127 17 unneback
//////////////////////////////////////////////////////////////////////
1128 6 unneback
////                                                              ////
1129 18 unneback
////  Logic functions                                             ////
1130
////                                                              ////
1131
////  Description                                                 ////
1132
////  Logic functions such as multiplexers                        ////
1133
////                                                              ////
1134
////                                                              ////
1135
////  To Do:                                                      ////
1136
////   -                                                          ////
1137
////                                                              ////
1138
////  Author(s):                                                  ////
1139
////      - Michael Unneback, unneback@opencores.org              ////
1140
////        ORSoC AB                                              ////
1141
////                                                              ////
1142
//////////////////////////////////////////////////////////////////////
1143
////                                                              ////
1144
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1145
////                                                              ////
1146
//// This source file may be used and distributed without         ////
1147
//// restriction provided that this copyright statement is not    ////
1148
//// removed from the file and that any derivative work contains  ////
1149
//// the original copyright notice and the associated disclaimer. ////
1150
////                                                              ////
1151
//// This source file is free software; you can redistribute it   ////
1152
//// and/or modify it under the terms of the GNU Lesser General   ////
1153
//// Public License as published by the Free Software Foundation; ////
1154
//// either version 2.1 of the License, or (at your option) any   ////
1155
//// later version.                                               ////
1156
////                                                              ////
1157
//// This source is distributed in the hope that it will be       ////
1158
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1159
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1160
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1161
//// details.                                                     ////
1162
////                                                              ////
1163
//// You should have received a copy of the GNU Lesser General    ////
1164
//// Public License along with this source; if not, download it   ////
1165
//// from http://www.opencores.org/lgpl.shtml                     ////
1166
////                                                              ////
1167
//////////////////////////////////////////////////////////////////////
1168 40 unneback
`ifdef MUX_ANDOR
1169
`define MODULE mux_andor
1170
module `BASE`MODULE ( a, sel, dout);
1171
`undef MODULE
1172 36 unneback
 
1173
parameter width = 32;
1174
parameter nr_of_ports = 4;
1175
 
1176
input [nr_of_ports*width-1:0] a;
1177
input [nr_of_ports-1:0] sel;
1178
output reg [width-1:0] dout;
1179
 
1180 38 unneback
integer i,j;
1181
 
1182 36 unneback
always @ (a, sel)
1183
begin
1184
    dout = a[width-1:0] & {width{sel[0]}};
1185 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1186
        for (j=0;j<width;j=j+1)
1187
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1188 36 unneback
end
1189
 
1190
endmodule
1191 40 unneback
`endif
1192 36 unneback
 
1193 40 unneback
`ifdef MUX2_ANDOR
1194
`define MODULE mux2_andor
1195
module `BASE`MODULE ( a1, a0, sel, dout);
1196
`undef MODULE
1197 18 unneback
 
1198 34 unneback
parameter width = 32;
1199 35 unneback
localparam nr_of_ports = 2;
1200 34 unneback
input [width-1:0] a1, a0;
1201
input [nr_of_ports-1:0] sel;
1202
output [width-1:0] dout;
1203
 
1204 40 unneback
`define MODULE mux_andor
1205
`BASE`MODULE
1206 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1207 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1208 40 unneback
`undef MODULE
1209
 
1210 34 unneback
endmodule
1211 40 unneback
`endif
1212 34 unneback
 
1213 40 unneback
`ifdef MUX3_ANDOR
1214
`define MODULE mux3_andor
1215
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1216
`undef MODULE
1217 34 unneback
 
1218
parameter width = 32;
1219 35 unneback
localparam nr_of_ports = 3;
1220 34 unneback
input [width-1:0] a2, a1, a0;
1221
input [nr_of_ports-1:0] sel;
1222
output [width-1:0] dout;
1223
 
1224 40 unneback
`define MODULE mux_andor
1225
`BASE`MODULE
1226 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1227 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1228 40 unneback
`undef MODULE
1229 34 unneback
endmodule
1230 40 unneback
`endif
1231 34 unneback
 
1232 40 unneback
`ifdef MUX4_ANDOR
1233
`define MODULE mux4_andor
1234
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1235
`undef MODULE
1236 18 unneback
 
1237
parameter width = 32;
1238 35 unneback
localparam nr_of_ports = 4;
1239 18 unneback
input [width-1:0] a3, a2, a1, a0;
1240
input [nr_of_ports-1:0] sel;
1241 22 unneback
output [width-1:0] dout;
1242 18 unneback
 
1243 40 unneback
`define MODULE mux_andor
1244
`BASE`MODULE
1245 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1246 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1247 40 unneback
`undef MODULE
1248 18 unneback
 
1249
endmodule
1250 40 unneback
`endif
1251 18 unneback
 
1252 40 unneback
`ifdef MUX5_ANDOR
1253
`define MODULE mux5_andor
1254
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1255
`undef MODULE
1256 18 unneback
 
1257
parameter width = 32;
1258 35 unneback
localparam nr_of_ports = 5;
1259 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1260
input [nr_of_ports-1:0] sel;
1261 22 unneback
output [width-1:0] dout;
1262 18 unneback
 
1263 40 unneback
`define MODULE mux_andor
1264
`BASE`MODULE
1265 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1266 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1267 40 unneback
`undef MODULE
1268 18 unneback
 
1269
endmodule
1270 40 unneback
`endif
1271 18 unneback
 
1272 40 unneback
`ifdef MUX6_ANDOR
1273
`define MODULE mux6_andor
1274
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1275
`undef MODULE
1276 18 unneback
 
1277
parameter width = 32;
1278 35 unneback
localparam nr_of_ports = 6;
1279 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1280
input [nr_of_ports-1:0] sel;
1281 22 unneback
output [width-1:0] dout;
1282 18 unneback
 
1283 40 unneback
`define MODULE mux_andor
1284
`BASE`MODULE
1285 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1286 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1287 40 unneback
`undef MODULE
1288 18 unneback
 
1289
endmodule
1290 40 unneback
`endif
1291 43 unneback
 
1292
`ifdef PARITY
1293
 
1294
`define MODULE parity_generate
1295
module `BASE`MODULE (data, parity);
1296
`undef MODULE
1297
parameter word_size = 32;
1298
parameter chunk_size = 8;
1299
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1300
input [word_size-1:0] data;
1301
output reg [word_size/chunk_size-1:0] parity;
1302
integer i,j;
1303
always @ (data)
1304
for (i=0;i<word_size/chunk_size;i=i+1) begin
1305
    parity[i] = parity_type;
1306
    for (j=0;j<chunk_size;j=j+1) begin
1307 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1308 43 unneback
    end
1309
end
1310
endmodule
1311
 
1312
`define MODULE parity_check
1313
module `BASE`MODULE( data, parity, parity_error);
1314
`undef MODULE
1315
parameter word_size = 32;
1316
parameter chunk_size = 8;
1317
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1318
input [word_size-1:0] data;
1319
input [word_size/chunk_size-1:0] parity;
1320
output parity_error;
1321 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1322 43 unneback
integer i,j;
1323
always @ (data or parity)
1324
for (i=0;i<word_size/chunk_size;i=i+1) begin
1325
    error_flag[i] = parity[i] ^ parity_type;
1326
    for (j=0;j<chunk_size;j=j+1) begin
1327 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1328 43 unneback
    end
1329
end
1330
assign parity_error = |error_flag;
1331
endmodule
1332
 
1333 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1334
////                                                              ////
1335
////  IO functions                                                ////
1336
////                                                              ////
1337
////  Description                                                 ////
1338
////  IO functions such as IOB flip-flops                         ////
1339
////                                                              ////
1340
////                                                              ////
1341
////  To Do:                                                      ////
1342
////   -                                                          ////
1343
////                                                              ////
1344
////  Author(s):                                                  ////
1345
////      - Michael Unneback, unneback@opencores.org              ////
1346
////        ORSoC AB                                              ////
1347
////                                                              ////
1348 18 unneback
//////////////////////////////////////////////////////////////////////
1349
////                                                              ////
1350 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1351
////                                                              ////
1352
//// This source file may be used and distributed without         ////
1353
//// restriction provided that this copyright statement is not    ////
1354
//// removed from the file and that any derivative work contains  ////
1355
//// the original copyright notice and the associated disclaimer. ////
1356
////                                                              ////
1357
//// This source file is free software; you can redistribute it   ////
1358
//// and/or modify it under the terms of the GNU Lesser General   ////
1359
//// Public License as published by the Free Software Foundation; ////
1360
//// either version 2.1 of the License, or (at your option) any   ////
1361
//// later version.                                               ////
1362
////                                                              ////
1363
//// This source is distributed in the hope that it will be       ////
1364
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1365
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1366
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1367
//// details.                                                     ////
1368
////                                                              ////
1369
//// You should have received a copy of the GNU Lesser General    ////
1370
//// Public License along with this source; if not, download it   ////
1371
//// from http://www.opencores.org/lgpl.shtml                     ////
1372
////                                                              ////
1373
//////////////////////////////////////////////////////////////////////
1374 45 unneback
`timescale 1ns/1ns
1375 44 unneback
`ifdef O_DFF
1376
`define MODULE o_dff
1377
module `BASE`MODULE (d_i, o_pad, clk, rst);
1378
`undef MODULE
1379
parameter width = 1;
1380 45 unneback
parameter reset_value = {width{1'b0}};
1381
input  [width-1:0]  d_i;
1382 44 unneback
output [width-1:0] o_pad;
1383
input clk, rst;
1384
wire [width-1:0] d_i_int `SYN_KEEP;
1385 45 unneback
reg  [width-1:0] o_pad_int;
1386 44 unneback
assign d_i_int = d_i;
1387
genvar i;
1388 45 unneback
generate
1389 44 unneback
for (i=0;i<width;i=i+1) begin
1390
    always @ (posedge clk or posedge rst)
1391
    if (rst)
1392 45 unneback
        o_pad_int[i] <= reset_value[i];
1393 44 unneback
    else
1394 45 unneback
        o_pad_int[i] <= d_i_int[i];
1395
    assign #1 o_pad[i] = o_pad_int[i];
1396 44 unneback
end
1397
endgenerate
1398
endmodule
1399
`endif
1400
 
1401 45 unneback
`timescale 1ns/1ns
1402 44 unneback
`ifdef IO_DFF_OE
1403
`define MODULE io_dff_oe
1404
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1405
`undef MODULE
1406
parameter width = 1;
1407
input  [width-1:0] d_o;
1408
output reg [width-1:0] d_i;
1409
input oe;
1410
inout [width-1:0] io_pad;
1411
input clk, rst;
1412
wire [width-1:0] oe_d `SYN_KEEP;
1413
reg [width-1:0] oe_q;
1414
reg [width-1:0] d_o_q;
1415
assign oe_d = {width{oe}};
1416
genvar i;
1417
generate
1418
for (i=0;i<width;i=i+1) begin
1419
    always @ (posedge clk or posedge rst)
1420
    if (rst)
1421
        oe_q[i] <= 1'b0;
1422
    else
1423
        oe_q[i] <= oe_d[i];
1424
    always @ (posedge clk or posedge rst)
1425
    if (rst)
1426
        d_o_q[i] <= 1'b0;
1427
    else
1428
        d_o_q[i] <= d_o[i];
1429
    always @ (posedge clk or posedge rst)
1430
    if (rst)
1431
        d_i[i] <= 1'b0;
1432
    else
1433
        d_i[i] <= io_pad[i];
1434 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1435 44 unneback
end
1436
endgenerate
1437
endmodule
1438
`endif
1439
`ifdef CNT_BIN
1440
//////////////////////////////////////////////////////////////////////
1441
////                                                              ////
1442 6 unneback
////  Versatile counter                                           ////
1443
////                                                              ////
1444
////  Description                                                 ////
1445
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1446
////  counter                                                     ////
1447
////                                                              ////
1448
////  To Do:                                                      ////
1449
////   - add LFSR with more taps                                  ////
1450
////                                                              ////
1451
////  Author(s):                                                  ////
1452
////      - Michael Unneback, unneback@opencores.org              ////
1453
////        ORSoC AB                                              ////
1454
////                                                              ////
1455
//////////////////////////////////////////////////////////////////////
1456
////                                                              ////
1457
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1458
////                                                              ////
1459
//// This source file may be used and distributed without         ////
1460
//// restriction provided that this copyright statement is not    ////
1461
//// removed from the file and that any derivative work contains  ////
1462
//// the original copyright notice and the associated disclaimer. ////
1463
////                                                              ////
1464
//// This source file is free software; you can redistribute it   ////
1465
//// and/or modify it under the terms of the GNU Lesser General   ////
1466
//// Public License as published by the Free Software Foundation; ////
1467
//// either version 2.1 of the License, or (at your option) any   ////
1468
//// later version.                                               ////
1469
////                                                              ////
1470
//// This source is distributed in the hope that it will be       ////
1471
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1472
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1473
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1474
//// details.                                                     ////
1475
////                                                              ////
1476
//// You should have received a copy of the GNU Lesser General    ////
1477
//// Public License along with this source; if not, download it   ////
1478
//// from http://www.opencores.org/lgpl.shtml                     ////
1479
////                                                              ////
1480
//////////////////////////////////////////////////////////////////////
1481
 
1482
// binary counter
1483 22 unneback
 
1484 40 unneback
`define MODULE cnt_bin
1485
module `BASE`MODULE (
1486
`undef MODULE
1487
 q, rst, clk);
1488
 
1489 22 unneback
   parameter length = 4;
1490
   output [length:1] q;
1491
   input rst;
1492
   input clk;
1493
 
1494
   parameter clear_value = 0;
1495
   parameter set_value = 1;
1496
   parameter wrap_value = 0;
1497
   parameter level1_value = 15;
1498
 
1499
   reg  [length:1] qi;
1500
   wire [length:1] q_next;
1501
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1502
 
1503
   always @ (posedge clk or posedge rst)
1504
     if (rst)
1505
       qi <= {length{1'b0}};
1506
     else
1507
       qi <= q_next;
1508
 
1509
   assign q = qi;
1510
 
1511
endmodule
1512 40 unneback
`endif
1513
`ifdef CNT_BIN_CLEAR
1514 22 unneback
//////////////////////////////////////////////////////////////////////
1515
////                                                              ////
1516
////  Versatile counter                                           ////
1517
////                                                              ////
1518
////  Description                                                 ////
1519
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1520
////  counter                                                     ////
1521
////                                                              ////
1522
////  To Do:                                                      ////
1523
////   - add LFSR with more taps                                  ////
1524
////                                                              ////
1525
////  Author(s):                                                  ////
1526
////      - Michael Unneback, unneback@opencores.org              ////
1527
////        ORSoC AB                                              ////
1528
////                                                              ////
1529
//////////////////////////////////////////////////////////////////////
1530
////                                                              ////
1531
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1532
////                                                              ////
1533
//// This source file may be used and distributed without         ////
1534
//// restriction provided that this copyright statement is not    ////
1535
//// removed from the file and that any derivative work contains  ////
1536
//// the original copyright notice and the associated disclaimer. ////
1537
////                                                              ////
1538
//// This source file is free software; you can redistribute it   ////
1539
//// and/or modify it under the terms of the GNU Lesser General   ////
1540
//// Public License as published by the Free Software Foundation; ////
1541
//// either version 2.1 of the License, or (at your option) any   ////
1542
//// later version.                                               ////
1543
////                                                              ////
1544
//// This source is distributed in the hope that it will be       ////
1545
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1546
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1547
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1548
//// details.                                                     ////
1549
////                                                              ////
1550
//// You should have received a copy of the GNU Lesser General    ////
1551
//// Public License along with this source; if not, download it   ////
1552
//// from http://www.opencores.org/lgpl.shtml                     ////
1553
////                                                              ////
1554
//////////////////////////////////////////////////////////////////////
1555
 
1556
// binary counter
1557
 
1558 40 unneback
`define MODULE cnt_bin_clear
1559
module `BASE`MODULE (
1560
`undef MODULE
1561
 clear, q, rst, clk);
1562
 
1563 22 unneback
   parameter length = 4;
1564
   input clear;
1565
   output [length:1] q;
1566
   input rst;
1567
   input clk;
1568
 
1569
   parameter clear_value = 0;
1570
   parameter set_value = 1;
1571
   parameter wrap_value = 0;
1572
   parameter level1_value = 15;
1573
 
1574
   reg  [length:1] qi;
1575
   wire [length:1] q_next;
1576
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1577
 
1578
   always @ (posedge clk or posedge rst)
1579
     if (rst)
1580
       qi <= {length{1'b0}};
1581
     else
1582
       qi <= q_next;
1583
 
1584
   assign q = qi;
1585
 
1586
endmodule
1587 40 unneback
`endif
1588
`ifdef CNT_BIN_CE
1589 22 unneback
//////////////////////////////////////////////////////////////////////
1590
////                                                              ////
1591
////  Versatile counter                                           ////
1592
////                                                              ////
1593
////  Description                                                 ////
1594
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1595
////  counter                                                     ////
1596
////                                                              ////
1597
////  To Do:                                                      ////
1598
////   - add LFSR with more taps                                  ////
1599
////                                                              ////
1600
////  Author(s):                                                  ////
1601
////      - Michael Unneback, unneback@opencores.org              ////
1602
////        ORSoC AB                                              ////
1603
////                                                              ////
1604
//////////////////////////////////////////////////////////////////////
1605
////                                                              ////
1606
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1607
////                                                              ////
1608
//// This source file may be used and distributed without         ////
1609
//// restriction provided that this copyright statement is not    ////
1610
//// removed from the file and that any derivative work contains  ////
1611
//// the original copyright notice and the associated disclaimer. ////
1612
////                                                              ////
1613
//// This source file is free software; you can redistribute it   ////
1614
//// and/or modify it under the terms of the GNU Lesser General   ////
1615
//// Public License as published by the Free Software Foundation; ////
1616
//// either version 2.1 of the License, or (at your option) any   ////
1617
//// later version.                                               ////
1618
////                                                              ////
1619
//// This source is distributed in the hope that it will be       ////
1620
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1621
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1622
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1623
//// details.                                                     ////
1624
////                                                              ////
1625
//// You should have received a copy of the GNU Lesser General    ////
1626
//// Public License along with this source; if not, download it   ////
1627
//// from http://www.opencores.org/lgpl.shtml                     ////
1628
////                                                              ////
1629
//////////////////////////////////////////////////////////////////////
1630
 
1631
// binary counter
1632 6 unneback
 
1633 40 unneback
`define MODULE cnt_bin_ce
1634
module `BASE`MODULE (
1635
`undef MODULE
1636
 cke, q, rst, clk);
1637
 
1638 6 unneback
   parameter length = 4;
1639
   input cke;
1640
   output [length:1] q;
1641
   input rst;
1642
   input clk;
1643
 
1644
   parameter clear_value = 0;
1645
   parameter set_value = 1;
1646
   parameter wrap_value = 0;
1647
   parameter level1_value = 15;
1648
 
1649
   reg  [length:1] qi;
1650
   wire [length:1] q_next;
1651
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1652
 
1653
   always @ (posedge clk or posedge rst)
1654
     if (rst)
1655
       qi <= {length{1'b0}};
1656
     else
1657
     if (cke)
1658
       qi <= q_next;
1659
 
1660
   assign q = qi;
1661
 
1662
endmodule
1663 40 unneback
`endif
1664
`ifdef CNT_BIN_CE_CLEAR
1665 6 unneback
//////////////////////////////////////////////////////////////////////
1666
////                                                              ////
1667
////  Versatile counter                                           ////
1668
////                                                              ////
1669
////  Description                                                 ////
1670
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1671
////  counter                                                     ////
1672
////                                                              ////
1673
////  To Do:                                                      ////
1674
////   - add LFSR with more taps                                  ////
1675
////                                                              ////
1676
////  Author(s):                                                  ////
1677
////      - Michael Unneback, unneback@opencores.org              ////
1678
////        ORSoC AB                                              ////
1679
////                                                              ////
1680
//////////////////////////////////////////////////////////////////////
1681
////                                                              ////
1682
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1683
////                                                              ////
1684
//// This source file may be used and distributed without         ////
1685
//// restriction provided that this copyright statement is not    ////
1686
//// removed from the file and that any derivative work contains  ////
1687
//// the original copyright notice and the associated disclaimer. ////
1688
////                                                              ////
1689
//// This source file is free software; you can redistribute it   ////
1690
//// and/or modify it under the terms of the GNU Lesser General   ////
1691
//// Public License as published by the Free Software Foundation; ////
1692
//// either version 2.1 of the License, or (at your option) any   ////
1693
//// later version.                                               ////
1694
////                                                              ////
1695
//// This source is distributed in the hope that it will be       ////
1696
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1697
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1698
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1699
//// details.                                                     ////
1700
////                                                              ////
1701
//// You should have received a copy of the GNU Lesser General    ////
1702
//// Public License along with this source; if not, download it   ////
1703
//// from http://www.opencores.org/lgpl.shtml                     ////
1704
////                                                              ////
1705
//////////////////////////////////////////////////////////////////////
1706
 
1707
// binary counter
1708
 
1709 40 unneback
`define MODULE cnt_bin_ce_clear
1710
module `BASE`MODULE (
1711
`undef MODULE
1712
 clear, cke, q, rst, clk);
1713
 
1714 6 unneback
   parameter length = 4;
1715
   input clear;
1716
   input cke;
1717
   output [length:1] q;
1718
   input rst;
1719
   input clk;
1720
 
1721
   parameter clear_value = 0;
1722
   parameter set_value = 1;
1723
   parameter wrap_value = 0;
1724
   parameter level1_value = 15;
1725
 
1726
   reg  [length:1] qi;
1727
   wire [length:1] q_next;
1728
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1729
 
1730
   always @ (posedge clk or posedge rst)
1731
     if (rst)
1732
       qi <= {length{1'b0}};
1733
     else
1734
     if (cke)
1735
       qi <= q_next;
1736
 
1737
   assign q = qi;
1738
 
1739
endmodule
1740 40 unneback
`endif
1741
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1742 6 unneback
//////////////////////////////////////////////////////////////////////
1743
////                                                              ////
1744
////  Versatile counter                                           ////
1745
////                                                              ////
1746
////  Description                                                 ////
1747
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1748
////  counter                                                     ////
1749
////                                                              ////
1750
////  To Do:                                                      ////
1751
////   - add LFSR with more taps                                  ////
1752
////                                                              ////
1753
////  Author(s):                                                  ////
1754
////      - Michael Unneback, unneback@opencores.org              ////
1755
////        ORSoC AB                                              ////
1756
////                                                              ////
1757
//////////////////////////////////////////////////////////////////////
1758
////                                                              ////
1759
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1760
////                                                              ////
1761
//// This source file may be used and distributed without         ////
1762
//// restriction provided that this copyright statement is not    ////
1763
//// removed from the file and that any derivative work contains  ////
1764
//// the original copyright notice and the associated disclaimer. ////
1765
////                                                              ////
1766
//// This source file is free software; you can redistribute it   ////
1767
//// and/or modify it under the terms of the GNU Lesser General   ////
1768
//// Public License as published by the Free Software Foundation; ////
1769
//// either version 2.1 of the License, or (at your option) any   ////
1770
//// later version.                                               ////
1771
////                                                              ////
1772
//// This source is distributed in the hope that it will be       ////
1773
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1774
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1775
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1776
//// details.                                                     ////
1777
////                                                              ////
1778
//// You should have received a copy of the GNU Lesser General    ////
1779
//// Public License along with this source; if not, download it   ////
1780
//// from http://www.opencores.org/lgpl.shtml                     ////
1781
////                                                              ////
1782
//////////////////////////////////////////////////////////////////////
1783
 
1784
// binary counter
1785 29 unneback
 
1786 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1787
module `BASE`MODULE (
1788
`undef MODULE
1789
 clear, cke, q, level1, level2, rst, clk);
1790
 
1791 29 unneback
   parameter length = 4;
1792
   input clear;
1793
   input cke;
1794
   output [length:1] q;
1795
   output reg level1;
1796
   output reg level2;
1797
   input rst;
1798
   input clk;
1799
 
1800
   parameter clear_value = 0;
1801
   parameter set_value = 1;
1802 30 unneback
   parameter wrap_value = 15;
1803
   parameter level1_value = 8;
1804
   parameter level2_value = 15;
1805 29 unneback
 
1806
   wire rew;
1807 30 unneback
   assign rew = 1'b0;
1808 29 unneback
   reg  [length:1] qi;
1809
   wire [length:1] q_next;
1810
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1811
 
1812
   always @ (posedge clk or posedge rst)
1813
     if (rst)
1814
       qi <= {length{1'b0}};
1815
     else
1816
     if (cke)
1817
       qi <= q_next;
1818
 
1819
   assign q = qi;
1820
 
1821
 
1822
    always @ (posedge clk or posedge rst)
1823
    if (rst)
1824
        level1 <= 1'b0;
1825
    else
1826
    if (cke)
1827
    if (clear)
1828
        level1 <= 1'b0;
1829
    else if (q_next == level1_value)
1830
        level1 <= 1'b1;
1831
    else if (qi == level1_value & rew)
1832
        level1 <= 1'b0;
1833
 
1834
    always @ (posedge clk or posedge rst)
1835
    if (rst)
1836
        level2 <= 1'b0;
1837
    else
1838
    if (cke)
1839
    if (clear)
1840
        level2 <= 1'b0;
1841
    else if (q_next == level2_value)
1842
        level2 <= 1'b1;
1843
    else if (qi == level2_value & rew)
1844
        level2 <= 1'b0;
1845
endmodule
1846 40 unneback
`endif
1847
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1848 29 unneback
//////////////////////////////////////////////////////////////////////
1849
////                                                              ////
1850
////  Versatile counter                                           ////
1851
////                                                              ////
1852
////  Description                                                 ////
1853
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1854
////  counter                                                     ////
1855
////                                                              ////
1856
////  To Do:                                                      ////
1857
////   - add LFSR with more taps                                  ////
1858
////                                                              ////
1859
////  Author(s):                                                  ////
1860
////      - Michael Unneback, unneback@opencores.org              ////
1861
////        ORSoC AB                                              ////
1862
////                                                              ////
1863
//////////////////////////////////////////////////////////////////////
1864
////                                                              ////
1865
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1866
////                                                              ////
1867
//// This source file may be used and distributed without         ////
1868
//// restriction provided that this copyright statement is not    ////
1869
//// removed from the file and that any derivative work contains  ////
1870
//// the original copyright notice and the associated disclaimer. ////
1871
////                                                              ////
1872
//// This source file is free software; you can redistribute it   ////
1873
//// and/or modify it under the terms of the GNU Lesser General   ////
1874
//// Public License as published by the Free Software Foundation; ////
1875
//// either version 2.1 of the License, or (at your option) any   ////
1876
//// later version.                                               ////
1877
////                                                              ////
1878
//// This source is distributed in the hope that it will be       ////
1879
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1880
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1881
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1882
//// details.                                                     ////
1883
////                                                              ////
1884
//// You should have received a copy of the GNU Lesser General    ////
1885
//// Public License along with this source; if not, download it   ////
1886
//// from http://www.opencores.org/lgpl.shtml                     ////
1887
////                                                              ////
1888
//////////////////////////////////////////////////////////////////////
1889
 
1890
// binary counter
1891 6 unneback
 
1892 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1893
module `BASE`MODULE (
1894
`undef MODULE
1895
 clear, set, cke, rew, q, rst, clk);
1896
 
1897 6 unneback
   parameter length = 4;
1898
   input clear;
1899
   input set;
1900
   input cke;
1901
   input rew;
1902
   output [length:1] q;
1903
   input rst;
1904
   input clk;
1905
 
1906
   parameter clear_value = 0;
1907
   parameter set_value = 1;
1908
   parameter wrap_value = 0;
1909
   parameter level1_value = 15;
1910
 
1911
   reg  [length:1] qi;
1912
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1913
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1914
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1915
   assign q_next = rew ? q_next_rew : q_next_fw;
1916
 
1917
   always @ (posedge clk or posedge rst)
1918
     if (rst)
1919
       qi <= {length{1'b0}};
1920
     else
1921
     if (cke)
1922
       qi <= q_next;
1923
 
1924
   assign q = qi;
1925
 
1926
endmodule
1927 40 unneback
`endif
1928
`ifdef CNT_BIN_CE_REW_L1
1929 6 unneback
//////////////////////////////////////////////////////////////////////
1930
////                                                              ////
1931
////  Versatile counter                                           ////
1932
////                                                              ////
1933
////  Description                                                 ////
1934
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1935
////  counter                                                     ////
1936
////                                                              ////
1937
////  To Do:                                                      ////
1938
////   - add LFSR with more taps                                  ////
1939
////                                                              ////
1940
////  Author(s):                                                  ////
1941
////      - Michael Unneback, unneback@opencores.org              ////
1942
////        ORSoC AB                                              ////
1943
////                                                              ////
1944
//////////////////////////////////////////////////////////////////////
1945
////                                                              ////
1946
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1947
////                                                              ////
1948
//// This source file may be used and distributed without         ////
1949
//// restriction provided that this copyright statement is not    ////
1950
//// removed from the file and that any derivative work contains  ////
1951
//// the original copyright notice and the associated disclaimer. ////
1952
////                                                              ////
1953
//// This source file is free software; you can redistribute it   ////
1954
//// and/or modify it under the terms of the GNU Lesser General   ////
1955
//// Public License as published by the Free Software Foundation; ////
1956
//// either version 2.1 of the License, or (at your option) any   ////
1957
//// later version.                                               ////
1958
////                                                              ////
1959
//// This source is distributed in the hope that it will be       ////
1960
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1961
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1962
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1963
//// details.                                                     ////
1964
////                                                              ////
1965
//// You should have received a copy of the GNU Lesser General    ////
1966
//// Public License along with this source; if not, download it   ////
1967
//// from http://www.opencores.org/lgpl.shtml                     ////
1968
////                                                              ////
1969
//////////////////////////////////////////////////////////////////////
1970
 
1971
// binary counter
1972
 
1973 40 unneback
`define MODULE cnt_bin_ce_rew_l1
1974
module `BASE`MODULE (
1975
`undef MODULE
1976
 cke, rew, level1, rst, clk);
1977
 
1978 6 unneback
   parameter length = 4;
1979
   input cke;
1980
   input rew;
1981
   output reg level1;
1982
   input rst;
1983
   input clk;
1984
 
1985
   parameter clear_value = 0;
1986
   parameter set_value = 1;
1987
   parameter wrap_value = 1;
1988
   parameter level1_value = 15;
1989
 
1990 29 unneback
   wire clear;
1991 30 unneback
   assign clear = 1'b0;
1992 6 unneback
   reg  [length:1] qi;
1993
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1994
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1995
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1996
   assign q_next = rew ? q_next_rew : q_next_fw;
1997
 
1998
   always @ (posedge clk or posedge rst)
1999
     if (rst)
2000
       qi <= {length{1'b0}};
2001
     else
2002
     if (cke)
2003
       qi <= q_next;
2004
 
2005
 
2006
 
2007
    always @ (posedge clk or posedge rst)
2008
    if (rst)
2009
        level1 <= 1'b0;
2010
    else
2011
    if (cke)
2012 29 unneback
    if (clear)
2013
        level1 <= 1'b0;
2014
    else if (q_next == level1_value)
2015 6 unneback
        level1 <= 1'b1;
2016
    else if (qi == level1_value & rew)
2017
        level1 <= 1'b0;
2018
endmodule
2019 40 unneback
`endif
2020
`ifdef CNT_BIN_CE_REW_ZQ_L1
2021 6 unneback
//////////////////////////////////////////////////////////////////////
2022
////                                                              ////
2023
////  Versatile counter                                           ////
2024
////                                                              ////
2025
////  Description                                                 ////
2026
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2027
////  counter                                                     ////
2028
////                                                              ////
2029
////  To Do:                                                      ////
2030
////   - add LFSR with more taps                                  ////
2031
////                                                              ////
2032
////  Author(s):                                                  ////
2033
////      - Michael Unneback, unneback@opencores.org              ////
2034
////        ORSoC AB                                              ////
2035
////                                                              ////
2036
//////////////////////////////////////////////////////////////////////
2037
////                                                              ////
2038
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2039
////                                                              ////
2040
//// This source file may be used and distributed without         ////
2041
//// restriction provided that this copyright statement is not    ////
2042
//// removed from the file and that any derivative work contains  ////
2043
//// the original copyright notice and the associated disclaimer. ////
2044
////                                                              ////
2045
//// This source file is free software; you can redistribute it   ////
2046
//// and/or modify it under the terms of the GNU Lesser General   ////
2047
//// Public License as published by the Free Software Foundation; ////
2048
//// either version 2.1 of the License, or (at your option) any   ////
2049
//// later version.                                               ////
2050
////                                                              ////
2051
//// This source is distributed in the hope that it will be       ////
2052
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2053
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2054
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2055
//// details.                                                     ////
2056
////                                                              ////
2057
//// You should have received a copy of the GNU Lesser General    ////
2058
//// Public License along with this source; if not, download it   ////
2059
//// from http://www.opencores.org/lgpl.shtml                     ////
2060
////                                                              ////
2061
//////////////////////////////////////////////////////////////////////
2062
 
2063 25 unneback
// binary counter
2064
 
2065 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2066
module `BASE`MODULE (
2067
`undef MODULE
2068
 cke, rew, zq, level1, rst, clk);
2069
 
2070 25 unneback
   parameter length = 4;
2071
   input cke;
2072
   input rew;
2073
   output reg zq;
2074
   output reg level1;
2075
   input rst;
2076
   input clk;
2077
 
2078
   parameter clear_value = 0;
2079
   parameter set_value = 1;
2080
   parameter wrap_value = 1;
2081
   parameter level1_value = 15;
2082
 
2083 29 unneback
   wire clear;
2084 30 unneback
   assign clear = 1'b0;
2085 25 unneback
   reg  [length:1] qi;
2086
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2087
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2088
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2089
   assign q_next = rew ? q_next_rew : q_next_fw;
2090
 
2091
   always @ (posedge clk or posedge rst)
2092
     if (rst)
2093
       qi <= {length{1'b0}};
2094
     else
2095
     if (cke)
2096
       qi <= q_next;
2097
 
2098
 
2099
 
2100
   always @ (posedge clk or posedge rst)
2101
     if (rst)
2102
       zq <= 1'b1;
2103
     else
2104
     if (cke)
2105
       zq <= q_next == {length{1'b0}};
2106
 
2107
    always @ (posedge clk or posedge rst)
2108
    if (rst)
2109
        level1 <= 1'b0;
2110
    else
2111
    if (cke)
2112 29 unneback
    if (clear)
2113
        level1 <= 1'b0;
2114
    else if (q_next == level1_value)
2115 25 unneback
        level1 <= 1'b1;
2116
    else if (qi == level1_value & rew)
2117
        level1 <= 1'b0;
2118
endmodule
2119 40 unneback
`endif
2120
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2121 25 unneback
//////////////////////////////////////////////////////////////////////
2122
////                                                              ////
2123
////  Versatile counter                                           ////
2124
////                                                              ////
2125
////  Description                                                 ////
2126
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2127
////  counter                                                     ////
2128
////                                                              ////
2129
////  To Do:                                                      ////
2130
////   - add LFSR with more taps                                  ////
2131
////                                                              ////
2132
////  Author(s):                                                  ////
2133
////      - Michael Unneback, unneback@opencores.org              ////
2134
////        ORSoC AB                                              ////
2135
////                                                              ////
2136
//////////////////////////////////////////////////////////////////////
2137
////                                                              ////
2138
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2139
////                                                              ////
2140
//// This source file may be used and distributed without         ////
2141
//// restriction provided that this copyright statement is not    ////
2142
//// removed from the file and that any derivative work contains  ////
2143
//// the original copyright notice and the associated disclaimer. ////
2144
////                                                              ////
2145
//// This source file is free software; you can redistribute it   ////
2146
//// and/or modify it under the terms of the GNU Lesser General   ////
2147
//// Public License as published by the Free Software Foundation; ////
2148
//// either version 2.1 of the License, or (at your option) any   ////
2149
//// later version.                                               ////
2150
////                                                              ////
2151
//// This source is distributed in the hope that it will be       ////
2152
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2153
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2154
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2155
//// details.                                                     ////
2156
////                                                              ////
2157
//// You should have received a copy of the GNU Lesser General    ////
2158
//// Public License along with this source; if not, download it   ////
2159
//// from http://www.opencores.org/lgpl.shtml                     ////
2160
////                                                              ////
2161
//////////////////////////////////////////////////////////////////////
2162
 
2163
// binary counter
2164
 
2165 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2166
module `BASE`MODULE (
2167
`undef MODULE
2168
 cke, rew, q, zq, level1, rst, clk);
2169
 
2170 25 unneback
   parameter length = 4;
2171
   input cke;
2172
   input rew;
2173
   output [length:1] q;
2174
   output reg zq;
2175
   output reg level1;
2176
   input rst;
2177
   input clk;
2178
 
2179
   parameter clear_value = 0;
2180
   parameter set_value = 1;
2181
   parameter wrap_value = 1;
2182
   parameter level1_value = 15;
2183
 
2184 29 unneback
   wire clear;
2185 30 unneback
   assign clear = 1'b0;
2186 25 unneback
   reg  [length:1] qi;
2187
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2188
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2189
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2190
   assign q_next = rew ? q_next_rew : q_next_fw;
2191
 
2192
   always @ (posedge clk or posedge rst)
2193
     if (rst)
2194
       qi <= {length{1'b0}};
2195
     else
2196
     if (cke)
2197
       qi <= q_next;
2198
 
2199
   assign q = qi;
2200
 
2201
 
2202
   always @ (posedge clk or posedge rst)
2203
     if (rst)
2204
       zq <= 1'b1;
2205
     else
2206
     if (cke)
2207
       zq <= q_next == {length{1'b0}};
2208
 
2209
    always @ (posedge clk or posedge rst)
2210
    if (rst)
2211
        level1 <= 1'b0;
2212
    else
2213
    if (cke)
2214 29 unneback
    if (clear)
2215
        level1 <= 1'b0;
2216
    else if (q_next == level1_value)
2217 25 unneback
        level1 <= 1'b1;
2218
    else if (qi == level1_value & rew)
2219
        level1 <= 1'b0;
2220
endmodule
2221 40 unneback
`endif
2222
`ifdef CNT_LFSR_ZQ
2223 25 unneback
//////////////////////////////////////////////////////////////////////
2224
////                                                              ////
2225
////  Versatile counter                                           ////
2226
////                                                              ////
2227
////  Description                                                 ////
2228
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2229
////  counter                                                     ////
2230
////                                                              ////
2231
////  To Do:                                                      ////
2232
////   - add LFSR with more taps                                  ////
2233
////                                                              ////
2234
////  Author(s):                                                  ////
2235
////      - Michael Unneback, unneback@opencores.org              ////
2236
////        ORSoC AB                                              ////
2237
////                                                              ////
2238
//////////////////////////////////////////////////////////////////////
2239
////                                                              ////
2240
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2241
////                                                              ////
2242
//// This source file may be used and distributed without         ////
2243
//// restriction provided that this copyright statement is not    ////
2244
//// removed from the file and that any derivative work contains  ////
2245
//// the original copyright notice and the associated disclaimer. ////
2246
////                                                              ////
2247
//// This source file is free software; you can redistribute it   ////
2248
//// and/or modify it under the terms of the GNU Lesser General   ////
2249
//// Public License as published by the Free Software Foundation; ////
2250
//// either version 2.1 of the License, or (at your option) any   ////
2251
//// later version.                                               ////
2252
////                                                              ////
2253
//// This source is distributed in the hope that it will be       ////
2254
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2255
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2256
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2257
//// details.                                                     ////
2258
////                                                              ////
2259
//// You should have received a copy of the GNU Lesser General    ////
2260
//// Public License along with this source; if not, download it   ////
2261
//// from http://www.opencores.org/lgpl.shtml                     ////
2262
////                                                              ////
2263
//////////////////////////////////////////////////////////////////////
2264
 
2265 6 unneback
// LFSR counter
2266
 
2267 40 unneback
`define MODULE cnt_lfsr_zq
2268
module `BASE`MODULE (
2269
`undef MODULE
2270
 zq, rst, clk);
2271
 
2272 6 unneback
   parameter length = 4;
2273
   output reg zq;
2274
   input rst;
2275
   input clk;
2276
 
2277
   parameter clear_value = 0;
2278
   parameter set_value = 1;
2279
   parameter wrap_value = 8;
2280
   parameter level1_value = 15;
2281
 
2282
   reg  [length:1] qi;
2283
   reg lfsr_fb;
2284
   wire [length:1] q_next;
2285
   reg [32:1] polynom;
2286
   integer i;
2287
 
2288
   always @ (qi)
2289
   begin
2290
        case (length)
2291
         2: polynom = 32'b11;                               // 0x3
2292
         3: polynom = 32'b110;                              // 0x6
2293
         4: polynom = 32'b1100;                             // 0xC
2294
         5: polynom = 32'b10100;                            // 0x14
2295
         6: polynom = 32'b110000;                           // 0x30
2296
         7: polynom = 32'b1100000;                          // 0x60
2297
         8: polynom = 32'b10111000;                         // 0xb8
2298
         9: polynom = 32'b100010000;                        // 0x110
2299
        10: polynom = 32'b1001000000;                       // 0x240
2300
        11: polynom = 32'b10100000000;                      // 0x500
2301
        12: polynom = 32'b100000101001;                     // 0x829
2302
        13: polynom = 32'b1000000001100;                    // 0x100C
2303
        14: polynom = 32'b10000000010101;                   // 0x2015
2304
        15: polynom = 32'b110000000000000;                  // 0x6000
2305
        16: polynom = 32'b1101000000001000;                 // 0xD008
2306
        17: polynom = 32'b10010000000000000;                // 0x12000
2307
        18: polynom = 32'b100000010000000000;               // 0x20400
2308
        19: polynom = 32'b1000000000000100011;              // 0x40023
2309 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2310 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2311
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2312
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2313
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2314
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2315
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2316
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2317
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2318
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2319
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2320
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2321
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2322
        default: polynom = 32'b0;
2323
        endcase
2324
        lfsr_fb = qi[length];
2325
        for (i=length-1; i>=1; i=i-1) begin
2326
            if (polynom[i])
2327
                lfsr_fb = lfsr_fb  ~^ qi[i];
2328
        end
2329
    end
2330
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2331
 
2332
   always @ (posedge clk or posedge rst)
2333
     if (rst)
2334
       qi <= {length{1'b0}};
2335
     else
2336
       qi <= q_next;
2337
 
2338
 
2339
 
2340
   always @ (posedge clk or posedge rst)
2341
     if (rst)
2342
       zq <= 1'b1;
2343
     else
2344
       zq <= q_next == {length{1'b0}};
2345
endmodule
2346 40 unneback
`endif
2347
`ifdef CNT_LFSR_CE_ZQ
2348 6 unneback
//////////////////////////////////////////////////////////////////////
2349
////                                                              ////
2350
////  Versatile counter                                           ////
2351
////                                                              ////
2352
////  Description                                                 ////
2353
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2354
////  counter                                                     ////
2355
////                                                              ////
2356
////  To Do:                                                      ////
2357
////   - add LFSR with more taps                                  ////
2358
////                                                              ////
2359
////  Author(s):                                                  ////
2360
////      - Michael Unneback, unneback@opencores.org              ////
2361
////        ORSoC AB                                              ////
2362
////                                                              ////
2363
//////////////////////////////////////////////////////////////////////
2364
////                                                              ////
2365
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2366
////                                                              ////
2367
//// This source file may be used and distributed without         ////
2368
//// restriction provided that this copyright statement is not    ////
2369
//// removed from the file and that any derivative work contains  ////
2370
//// the original copyright notice and the associated disclaimer. ////
2371
////                                                              ////
2372
//// This source file is free software; you can redistribute it   ////
2373
//// and/or modify it under the terms of the GNU Lesser General   ////
2374
//// Public License as published by the Free Software Foundation; ////
2375
//// either version 2.1 of the License, or (at your option) any   ////
2376
//// later version.                                               ////
2377
////                                                              ////
2378
//// This source is distributed in the hope that it will be       ////
2379
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2380
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2381
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2382
//// details.                                                     ////
2383
////                                                              ////
2384
//// You should have received a copy of the GNU Lesser General    ////
2385
//// Public License along with this source; if not, download it   ////
2386
//// from http://www.opencores.org/lgpl.shtml                     ////
2387
////                                                              ////
2388
//////////////////////////////////////////////////////////////////////
2389
 
2390
// LFSR counter
2391
 
2392 40 unneback
`define MODULE cnt_lfsr_ce_zq
2393
module `BASE`MODULE (
2394
`undef MODULE
2395
 cke, zq, rst, clk);
2396
 
2397 6 unneback
   parameter length = 4;
2398
   input cke;
2399
   output reg zq;
2400
   input rst;
2401
   input clk;
2402
 
2403
   parameter clear_value = 0;
2404
   parameter set_value = 1;
2405
   parameter wrap_value = 8;
2406
   parameter level1_value = 15;
2407
 
2408
   reg  [length:1] qi;
2409
   reg lfsr_fb;
2410
   wire [length:1] q_next;
2411
   reg [32:1] polynom;
2412
   integer i;
2413
 
2414
   always @ (qi)
2415
   begin
2416
        case (length)
2417
         2: polynom = 32'b11;                               // 0x3
2418
         3: polynom = 32'b110;                              // 0x6
2419
         4: polynom = 32'b1100;                             // 0xC
2420
         5: polynom = 32'b10100;                            // 0x14
2421
         6: polynom = 32'b110000;                           // 0x30
2422
         7: polynom = 32'b1100000;                          // 0x60
2423
         8: polynom = 32'b10111000;                         // 0xb8
2424
         9: polynom = 32'b100010000;                        // 0x110
2425
        10: polynom = 32'b1001000000;                       // 0x240
2426
        11: polynom = 32'b10100000000;                      // 0x500
2427
        12: polynom = 32'b100000101001;                     // 0x829
2428
        13: polynom = 32'b1000000001100;                    // 0x100C
2429
        14: polynom = 32'b10000000010101;                   // 0x2015
2430
        15: polynom = 32'b110000000000000;                  // 0x6000
2431
        16: polynom = 32'b1101000000001000;                 // 0xD008
2432
        17: polynom = 32'b10010000000000000;                // 0x12000
2433
        18: polynom = 32'b100000010000000000;               // 0x20400
2434
        19: polynom = 32'b1000000000000100011;              // 0x40023
2435 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2436 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2437
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2438
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2439
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2440
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2441
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2442
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2443
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2444
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2445
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2446
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2447
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2448
        default: polynom = 32'b0;
2449
        endcase
2450
        lfsr_fb = qi[length];
2451
        for (i=length-1; i>=1; i=i-1) begin
2452
            if (polynom[i])
2453
                lfsr_fb = lfsr_fb  ~^ qi[i];
2454
        end
2455
    end
2456
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2457
 
2458
   always @ (posedge clk or posedge rst)
2459
     if (rst)
2460
       qi <= {length{1'b0}};
2461
     else
2462
     if (cke)
2463
       qi <= q_next;
2464
 
2465
 
2466
 
2467
   always @ (posedge clk or posedge rst)
2468
     if (rst)
2469
       zq <= 1'b1;
2470
     else
2471
     if (cke)
2472
       zq <= q_next == {length{1'b0}};
2473
endmodule
2474 40 unneback
`endif
2475
`ifdef CNT_LFSR_CE_Q
2476 6 unneback
//////////////////////////////////////////////////////////////////////
2477
////                                                              ////
2478
////  Versatile counter                                           ////
2479
////                                                              ////
2480
////  Description                                                 ////
2481
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2482
////  counter                                                     ////
2483
////                                                              ////
2484
////  To Do:                                                      ////
2485
////   - add LFSR with more taps                                  ////
2486
////                                                              ////
2487
////  Author(s):                                                  ////
2488
////      - Michael Unneback, unneback@opencores.org              ////
2489
////        ORSoC AB                                              ////
2490
////                                                              ////
2491
//////////////////////////////////////////////////////////////////////
2492
////                                                              ////
2493
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2494
////                                                              ////
2495
//// This source file may be used and distributed without         ////
2496
//// restriction provided that this copyright statement is not    ////
2497
//// removed from the file and that any derivative work contains  ////
2498
//// the original copyright notice and the associated disclaimer. ////
2499
////                                                              ////
2500
//// This source file is free software; you can redistribute it   ////
2501
//// and/or modify it under the terms of the GNU Lesser General   ////
2502
//// Public License as published by the Free Software Foundation; ////
2503
//// either version 2.1 of the License, or (at your option) any   ////
2504
//// later version.                                               ////
2505
////                                                              ////
2506
//// This source is distributed in the hope that it will be       ////
2507
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2508
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2509
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2510
//// details.                                                     ////
2511
////                                                              ////
2512
//// You should have received a copy of the GNU Lesser General    ////
2513
//// Public License along with this source; if not, download it   ////
2514
//// from http://www.opencores.org/lgpl.shtml                     ////
2515
////                                                              ////
2516
//////////////////////////////////////////////////////////////////////
2517 22 unneback
 
2518
// LFSR counter
2519 27 unneback
 
2520 40 unneback
`define MODULE cnt_lfsr_ce_q
2521
module `BASE`MODULE (
2522
`undef MODULE
2523
 cke, q, rst, clk);
2524
 
2525 27 unneback
   parameter length = 4;
2526
   input cke;
2527
   output [length:1] q;
2528
   input rst;
2529
   input clk;
2530
 
2531
   parameter clear_value = 0;
2532
   parameter set_value = 1;
2533
   parameter wrap_value = 8;
2534
   parameter level1_value = 15;
2535
 
2536
   reg  [length:1] qi;
2537
   reg lfsr_fb;
2538
   wire [length:1] q_next;
2539
   reg [32:1] polynom;
2540
   integer i;
2541
 
2542
   always @ (qi)
2543
   begin
2544
        case (length)
2545
         2: polynom = 32'b11;                               // 0x3
2546
         3: polynom = 32'b110;                              // 0x6
2547
         4: polynom = 32'b1100;                             // 0xC
2548
         5: polynom = 32'b10100;                            // 0x14
2549
         6: polynom = 32'b110000;                           // 0x30
2550
         7: polynom = 32'b1100000;                          // 0x60
2551
         8: polynom = 32'b10111000;                         // 0xb8
2552
         9: polynom = 32'b100010000;                        // 0x110
2553
        10: polynom = 32'b1001000000;                       // 0x240
2554
        11: polynom = 32'b10100000000;                      // 0x500
2555
        12: polynom = 32'b100000101001;                     // 0x829
2556
        13: polynom = 32'b1000000001100;                    // 0x100C
2557
        14: polynom = 32'b10000000010101;                   // 0x2015
2558
        15: polynom = 32'b110000000000000;                  // 0x6000
2559
        16: polynom = 32'b1101000000001000;                 // 0xD008
2560
        17: polynom = 32'b10010000000000000;                // 0x12000
2561
        18: polynom = 32'b100000010000000000;               // 0x20400
2562
        19: polynom = 32'b1000000000000100011;              // 0x40023
2563 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2564 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2565
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2566
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2567
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2568
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2569
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2570
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2571
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2572
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2573
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2574
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2575
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2576
        default: polynom = 32'b0;
2577
        endcase
2578
        lfsr_fb = qi[length];
2579
        for (i=length-1; i>=1; i=i-1) begin
2580
            if (polynom[i])
2581
                lfsr_fb = lfsr_fb  ~^ qi[i];
2582
        end
2583
    end
2584
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2585
 
2586
   always @ (posedge clk or posedge rst)
2587
     if (rst)
2588
       qi <= {length{1'b0}};
2589
     else
2590
     if (cke)
2591
       qi <= q_next;
2592
 
2593
   assign q = qi;
2594
 
2595
endmodule
2596 40 unneback
`endif
2597
`ifdef CNT_LFSR_CE_CLEAR_Q
2598 27 unneback
//////////////////////////////////////////////////////////////////////
2599
////                                                              ////
2600
////  Versatile counter                                           ////
2601
////                                                              ////
2602
////  Description                                                 ////
2603
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2604
////  counter                                                     ////
2605
////                                                              ////
2606
////  To Do:                                                      ////
2607
////   - add LFSR with more taps                                  ////
2608
////                                                              ////
2609
////  Author(s):                                                  ////
2610
////      - Michael Unneback, unneback@opencores.org              ////
2611
////        ORSoC AB                                              ////
2612
////                                                              ////
2613
//////////////////////////////////////////////////////////////////////
2614
////                                                              ////
2615
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2616
////                                                              ////
2617
//// This source file may be used and distributed without         ////
2618
//// restriction provided that this copyright statement is not    ////
2619
//// removed from the file and that any derivative work contains  ////
2620
//// the original copyright notice and the associated disclaimer. ////
2621
////                                                              ////
2622
//// This source file is free software; you can redistribute it   ////
2623
//// and/or modify it under the terms of the GNU Lesser General   ////
2624
//// Public License as published by the Free Software Foundation; ////
2625
//// either version 2.1 of the License, or (at your option) any   ////
2626
//// later version.                                               ////
2627
////                                                              ////
2628
//// This source is distributed in the hope that it will be       ////
2629
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2630
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2631
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2632
//// details.                                                     ////
2633
////                                                              ////
2634
//// You should have received a copy of the GNU Lesser General    ////
2635
//// Public License along with this source; if not, download it   ////
2636
//// from http://www.opencores.org/lgpl.shtml                     ////
2637
////                                                              ////
2638
//////////////////////////////////////////////////////////////////////
2639
 
2640
// LFSR counter
2641
 
2642 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2643
module `BASE`MODULE (
2644
`undef MODULE
2645
 clear, cke, q, rst, clk);
2646
 
2647 27 unneback
   parameter length = 4;
2648
   input clear;
2649
   input cke;
2650
   output [length:1] q;
2651
   input rst;
2652
   input clk;
2653
 
2654
   parameter clear_value = 0;
2655
   parameter set_value = 1;
2656
   parameter wrap_value = 8;
2657
   parameter level1_value = 15;
2658
 
2659
   reg  [length:1] qi;
2660
   reg lfsr_fb;
2661
   wire [length:1] q_next;
2662
   reg [32:1] polynom;
2663
   integer i;
2664
 
2665
   always @ (qi)
2666
   begin
2667
        case (length)
2668
         2: polynom = 32'b11;                               // 0x3
2669
         3: polynom = 32'b110;                              // 0x6
2670
         4: polynom = 32'b1100;                             // 0xC
2671
         5: polynom = 32'b10100;                            // 0x14
2672
         6: polynom = 32'b110000;                           // 0x30
2673
         7: polynom = 32'b1100000;                          // 0x60
2674
         8: polynom = 32'b10111000;                         // 0xb8
2675
         9: polynom = 32'b100010000;                        // 0x110
2676
        10: polynom = 32'b1001000000;                       // 0x240
2677
        11: polynom = 32'b10100000000;                      // 0x500
2678
        12: polynom = 32'b100000101001;                     // 0x829
2679
        13: polynom = 32'b1000000001100;                    // 0x100C
2680
        14: polynom = 32'b10000000010101;                   // 0x2015
2681
        15: polynom = 32'b110000000000000;                  // 0x6000
2682
        16: polynom = 32'b1101000000001000;                 // 0xD008
2683
        17: polynom = 32'b10010000000000000;                // 0x12000
2684
        18: polynom = 32'b100000010000000000;               // 0x20400
2685
        19: polynom = 32'b1000000000000100011;              // 0x40023
2686 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2687 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2688
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2689
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2690
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2691
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2692
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2693
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2694
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2695
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2696
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2697
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2698
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2699
        default: polynom = 32'b0;
2700
        endcase
2701
        lfsr_fb = qi[length];
2702
        for (i=length-1; i>=1; i=i-1) begin
2703
            if (polynom[i])
2704
                lfsr_fb = lfsr_fb  ~^ qi[i];
2705
        end
2706
    end
2707
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2708
 
2709
   always @ (posedge clk or posedge rst)
2710
     if (rst)
2711
       qi <= {length{1'b0}};
2712
     else
2713
     if (cke)
2714
       qi <= q_next;
2715
 
2716
   assign q = qi;
2717
 
2718
endmodule
2719 40 unneback
`endif
2720
`ifdef CNT_LFSR_CE_Q_ZQ
2721 27 unneback
//////////////////////////////////////////////////////////////////////
2722
////                                                              ////
2723
////  Versatile counter                                           ////
2724
////                                                              ////
2725
////  Description                                                 ////
2726
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2727
////  counter                                                     ////
2728
////                                                              ////
2729
////  To Do:                                                      ////
2730
////   - add LFSR with more taps                                  ////
2731
////                                                              ////
2732
////  Author(s):                                                  ////
2733
////      - Michael Unneback, unneback@opencores.org              ////
2734
////        ORSoC AB                                              ////
2735
////                                                              ////
2736
//////////////////////////////////////////////////////////////////////
2737
////                                                              ////
2738
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2739
////                                                              ////
2740
//// This source file may be used and distributed without         ////
2741
//// restriction provided that this copyright statement is not    ////
2742
//// removed from the file and that any derivative work contains  ////
2743
//// the original copyright notice and the associated disclaimer. ////
2744
////                                                              ////
2745
//// This source file is free software; you can redistribute it   ////
2746
//// and/or modify it under the terms of the GNU Lesser General   ////
2747
//// Public License as published by the Free Software Foundation; ////
2748
//// either version 2.1 of the License, or (at your option) any   ////
2749
//// later version.                                               ////
2750
////                                                              ////
2751
//// This source is distributed in the hope that it will be       ////
2752
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2753
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2754
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2755
//// details.                                                     ////
2756
////                                                              ////
2757
//// You should have received a copy of the GNU Lesser General    ////
2758
//// Public License along with this source; if not, download it   ////
2759
//// from http://www.opencores.org/lgpl.shtml                     ////
2760
////                                                              ////
2761
//////////////////////////////////////////////////////////////////////
2762
 
2763
// LFSR counter
2764 22 unneback
 
2765 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
2766
module `BASE`MODULE (
2767
`undef MODULE
2768
 cke, q, zq, rst, clk);
2769
 
2770 22 unneback
   parameter length = 4;
2771
   input cke;
2772
   output [length:1] q;
2773
   output reg zq;
2774
   input rst;
2775
   input clk;
2776
 
2777
   parameter clear_value = 0;
2778
   parameter set_value = 1;
2779
   parameter wrap_value = 8;
2780
   parameter level1_value = 15;
2781
 
2782
   reg  [length:1] qi;
2783
   reg lfsr_fb;
2784
   wire [length:1] q_next;
2785
   reg [32:1] polynom;
2786
   integer i;
2787
 
2788
   always @ (qi)
2789
   begin
2790
        case (length)
2791
         2: polynom = 32'b11;                               // 0x3
2792
         3: polynom = 32'b110;                              // 0x6
2793
         4: polynom = 32'b1100;                             // 0xC
2794
         5: polynom = 32'b10100;                            // 0x14
2795
         6: polynom = 32'b110000;                           // 0x30
2796
         7: polynom = 32'b1100000;                          // 0x60
2797
         8: polynom = 32'b10111000;                         // 0xb8
2798
         9: polynom = 32'b100010000;                        // 0x110
2799
        10: polynom = 32'b1001000000;                       // 0x240
2800
        11: polynom = 32'b10100000000;                      // 0x500
2801
        12: polynom = 32'b100000101001;                     // 0x829
2802
        13: polynom = 32'b1000000001100;                    // 0x100C
2803
        14: polynom = 32'b10000000010101;                   // 0x2015
2804
        15: polynom = 32'b110000000000000;                  // 0x6000
2805
        16: polynom = 32'b1101000000001000;                 // 0xD008
2806
        17: polynom = 32'b10010000000000000;                // 0x12000
2807
        18: polynom = 32'b100000010000000000;               // 0x20400
2808
        19: polynom = 32'b1000000000000100011;              /