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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 59

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 44 unneback 
`ifdef ACTEL
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
`endif
8 
 
9 40 unneback 
`ifdef ALL
10 
 
11 
`define GBUF
12 
`define SYNC_RST
13 
`define PLL
14 
 
15 
`define MULTS
16 
`define MULTS18X18
17 
`define MULT
18 
`define SHIFT_UNIT_32
19 
`define LOGIC_UNIT
20 
 
21 
`define CNT_SHREG_WRAP
22 
`define CNT_SHREG_CE_WRAP
23 
`define CNT_SHREG_CE_CLEAR
24 
`define CNT_SHREG_CE_CLEAR_WRAP
25 
 
26 
`define MUX_ANDOR
27 
`define MUX2_ANDOR
28 
`define MUX3_ANDOR
29 
`define MUX4_ANDOR
30 
`define MUX5_ANDOR
31 
`define MUX6_ANDOR
32 43 unneback 
`define PARITY
33 40 unneback 
 
34 
`define ROM_INIT
35 
`define RAM
36 
`define RAM_BE
37 
`define DPRAM_1R1W
38 
`define DPRAM_2R1W
39 
`define DPRAM_2R2W
40 
`define FIFO_1R1W_FILL_LEVEL_SYNC
41 
`define FIFO_2R2W_SYNC_SIMPLEX
42 
`define FIFO_CMP_ASYNC
43 
`define FIFO_1R1W_ASYNC
44 
`define FIFO_2R2W_ASYNC
45 
`define FIFO_2R2W_ASYNC_SIMPLEX
46 48 unneback 
`define REG_FILE
47 40 unneback 
 
48 
`define DFF
49 
`define DFF_ARRAY
50 
`define DFF_CE
51 
`define DFF_CE_CLEAR
52 
`define DF_CE_SET
53 
`define SPR
54 
`define SRP
55 
`define DFF_SR
56 
`define LATCH
57 
`define SHREG
58 
`define SHREG_CE
59 
`define DELAY
60 
`define DELAY_EMPTYFLAG
61 
 
62 
`define WB3WB3_BRIDGE
63 
`define WB3_ARBITER_TYPE1
64 59 unneback 
`define WB_B3_RAM_BE
65 49 unneback 
`define WB_B4_RAM_BE
66 48 unneback 
`define WB_B4_ROM
67 40 unneback 
`define WB_BOOT_ROM
68 
`define WB_DPRAM
69 
 
70 44 unneback 
`define IO_DFF_OE
71 
`define O_DFF
72 
 
73 40 unneback 
`endif
74 
 
75 
`ifdef PLL
76 
`ifndef SYNC_RST
77 
`define SYNC_RST
78 
`endif
79 
`endif
80 
 
81 
`ifdef SYNC_RST
82 
`ifndef GBUF
83 
`define GBUF
84 
`endif
85 
`endif
86 
 
87 
`ifdef WB_DPRAM
88 
`ifndef DPRAM_2R2W
89 
`define DPRAM_2R2W
90 
`endif
91 
`ifndef SPR
92 
`define SPR
93 
`endif
94 
`endif
95 
 
96 
`ifdef WB3_ARBITER_TYPE1
97 42 unneback 
`ifndef SPR
98 
`define SPR
99 
`endif
100 40 unneback 
`ifndef MUX_ANDOR
101 
`define MUX_ANDOR
102 
`endif
103 
`endif
104 
 
105 
`ifdef WB3WB3_BRIDGE
106 
`ifndef CNT_SHREG_CE_CLEAR
107 
`define CNT_SHREG_CE_CLEAR
108 
`endif
109 
`ifndef DFF
110 
`define DFF
111 
`endif
112 
`ifndef DFF_CE
113 
`define DFF_CE
114 
`endif
115 
`ifndef CNT_SHREG_CE_CLEAR
116 
`define CNT_SHREG_CE_CLEAR
117 
`endif
118 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
119 
`define FIFO_2R2W_ASYNC_SIMPLEX
120 
`endif
121 
`endif
122 
 
123 
`ifdef MULTS18X18
124 
`ifndef MULTS
125 
`define MULTS
126 
`endif
127 
`endif
128 
 
129 
`ifdef SHIFT_UNIT_32
130 
`ifndef MULTS
131 
`define MULTS
132 
`endif
133 
`endif
134 
 
135 
`ifdef MUX2_ANDOR
136 
`ifndef MUX_ANDOR
137 
`define MUX_ANDOR
138 
`endif
139 
`endif
140 
 
141 
`ifdef MUX3_ANDOR
142 
`ifndef MUX_ANDOR
143 
`define MUX_ANDOR
144 
`endif
145 
`endif
146 
 
147 
`ifdef MUX4_ANDOR
148 
`ifndef MUX_ANDOR
149 
`define MUX_ANDOR
150 
`endif
151 
`endif
152 
 
153 
`ifdef MUX5_ANDOR
154 
`ifndef MUX_ANDOR
155 
`define MUX_ANDOR
156 
`endif
157 
`endif
158 
 
159 
`ifdef MUX6_ANDOR
160 
`ifndef MUX_ANDOR
161 
`define MUX_ANDOR
162 
`endif
163 
`endif
164 
 
165 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
166 
`ifndef CNT_BIN_CE
167 
`define CNT_BIN_CE
168 
`endif
169 
`ifndef DPRAM_1R1W
170 
`define DPRAM_1R1W
171 
`endif
172 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
173 
`define CNT_BIN_CE_REW_Q_ZQ_L1
174 
`endif
175 
`endif
176 
 
177 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
178 
`ifndef CNT_LFSR_CE
179 
`define CNT_LFSR_CE
180 
`endif
181 
`ifndef DPRAM_2R2W
182 
`define DPRAM_2R2W
183 
`endif
184 
`ifndef CNT_BIN_CE_REW_ZQ_L1
185 
`define CNT_BIN_CE_REW_ZQ_L1
186 
`endif
187 
`endif
188 
 
189 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
190 
`ifndef CNT_GRAY_CE_BIN
191 
`define CNT_GRAY_CE_BIN
192 
`endif
193 
`ifndef DPRAM_2R2W
194 
`define DPRAM_2R2W
195 
`endif
196 
`ifndef FIFO_CMP_ASYNC
197 
`define FIFO_CMP_ASYNC
198 
`endif
199 
`endif
200 
 
201 
`ifdef FIFO_2R2W_ASYNC
202 
`ifndef FIFO_1R1W_ASYNC
203 
`define FIFO_1R1W_ASYNC
204 
`endif
205 
`endif
206 
 
207 
`ifdef FIFO_1R1W_ASYNC
208 
`ifndef CNT_GRAY_CE_BIN
209 
`define CNT_GRAY_CE_BIN
210 
`endif
211 
`ifndef DPRAM_1R1W
212 
`define DPRAM_1R1W
213 
`endif
214 
`ifndef FIFO_CMP_ASYNC
215 
`define FIFO_CMP_ASYNC
216 
`endif
217 
`endif
218 
 
219 
`ifdef FIFO_CMP_ASYNC
220 
`ifndef DFF_SR
221 
`define DFF_SR
222 
`endif
223 
`ifndef DFF
224 
`define DFF
225 
`endif
226 
`endif
227 48 unneback 
 
228 
`ifdef REG_FILE
229 
`ifndef DPRAM_1R1W
230 
`define DPRAM_1R1W
231 
`endif
232 
`endif
233 6 unneback 
//////////////////////////////////////////////////////////////////////
234 
////                                                              ////
235 
////  Versatile library, clock and reset                          ////
236 
////                                                              ////
237 
////  Description                                                 ////
238 
////  Logic related to clock and reset                            ////
239 
////                                                              ////
240 
////                                                              ////
241 
////  To Do:                                                      ////
242 
////   - add more different registers                             ////
243 
////                                                              ////
244 
////  Author(s):                                                  ////
245 
////      - Michael Unneback, unneback@opencores.org              ////
246 
////        ORSoC AB                                              ////
247 
////                                                              ////
248 
//////////////////////////////////////////////////////////////////////
249 
////                                                              ////
250 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
251 
////                                                              ////
252 
//// This source file may be used and distributed without         ////
253 
//// restriction provided that this copyright statement is not    ////
254 
//// removed from the file and that any derivative work contains  ////
255 
//// the original copyright notice and the associated disclaimer. ////
256 
////                                                              ////
257 
//// This source file is free software; you can redistribute it   ////
258 
//// and/or modify it under the terms of the GNU Lesser General   ////
259 
//// Public License as published by the Free Software Foundation; ////
260 
//// either version 2.1 of the License, or (at your option) any   ////
261 
//// later version.                                               ////
262 
////                                                              ////
263 
//// This source is distributed in the hope that it will be       ////
264 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
265 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
266 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
267 
//// details.                                                     ////
268 
////                                                              ////
269 
//// You should have received a copy of the GNU Lesser General    ////
270 
//// Public License along with this source; if not, download it   ////
271 
//// from http://www.opencores.org/lgpl.shtml                     ////
272 
////                                                              ////
273 
//////////////////////////////////////////////////////////////////////
274 
 
275 48 unneback 
`ifdef ACTEL
276 
`ifdef GBUF
277 
`timescale 1 ns/100 ps
278 6 unneback 
// Global buffer
279 
// usage:
280 
// use to enable global buffers for high fan out signals such as clock and reset
281 
// Version: 8.4 8.4.0.33
282 
module gbuf(GL,CLK);
283 
output GL;
284 
input  CLK;
285 
 
286 
    wire GND;
287 
 
288 
    GND GND_1_net(.Y(GND));
289 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
290 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
291 
 
292 
endmodule
293 
`timescale 1 ns/1 ns
294 40 unneback 
`define MODULE gbuf
295 
module `BASE`MODULE ( i, o);
296 
`undef MODULE
297 6 unneback 
input i;
298 
output o;
299 
`ifdef SIM_GBUF
300 
assign o=i;
301 
`else
302 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
303 
`endif
304 
endmodule
305 40 unneback 
`endif
306 33 unneback 
 
307 6 unneback 
`else
308 33 unneback 
 
309 40 unneback 
`ifdef ALTERA
310 
`ifdef GBUF
311 21 unneback 
//altera
312 40 unneback 
`define MODULE gbuf
313 
module `BASE`MODULE ( i, o);
314 
`undef MODULE
315 33 unneback 
input i;
316 
output o;
317 
assign o = i;
318 
endmodule
319 40 unneback 
`endif
320 33 unneback 
 
321 6 unneback 
`else
322 
 
323 40 unneback 
`ifdef GBUF
324 6 unneback 
`timescale 1 ns/100 ps
325 40 unneback 
`define MODULE
326 
module `BASE`MODULE ( i, o);
327 
`undef MODULE
328 6 unneback 
input i;
329 
output o;
330 
assign o = i;
331 
endmodule
332 40 unneback 
`endif
333 6 unneback 
`endif // ALTERA
334 
`endif //ACTEL
335 
 
336 40 unneback 
`ifdef SYNC_RST
337 6 unneback 
// sync reset
338 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
339 6 unneback 
// output active high global reset sync with two DFFs
340 
`timescale 1 ns/100 ps
341 40 unneback 
`define MODULE sync_rst
342 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
343 
`undef MODULE
344 6 unneback 
input rst_n_i, clk;
345 
output rst_o;
346 18 unneback 
reg [1:0] tmp;
347 6 unneback 
always @ (posedge clk or negedge rst_n_i)
348 
if (!rst_n_i)
349 17 unneback 
        tmp <= 2'b11;
350 6 unneback 
else
351 33 unneback 
        tmp <= {1'b0,tmp[1]};
352 40 unneback 
`define MODULE gbuf
353 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
354 
`undef MODULE
355 6 unneback 
endmodule
356 40 unneback 
`endif
357 6 unneback 
 
358 40 unneback 
`ifdef PLL
359 6 unneback 
// vl_pll
360 
`ifdef ACTEL
361 32 unneback 
///////////////////////////////////////////////////////////////////////////////
362 17 unneback 
`timescale 1 ps/1 ps
363 40 unneback 
`define MODULE pll
364 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
365 
`undef MODULE
366 6 unneback 
parameter index = 0;
367 
parameter number_of_clk = 1;
368 17 unneback 
parameter period_time_0 = 20000;
369 
parameter period_time_1 = 20000;
370 
parameter period_time_2 = 20000;
371 
parameter lock_delay = 2000000;
372 6 unneback 
input clk_i, rst_n_i;
373 
output lock;
374 
output reg [0:number_of_clk-1] clk_o;
375 
output [0:number_of_clk-1] rst_o;
376 
 
377 
`ifdef SIM_PLL
378 
 
379 
always
380 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
381 
 
382 
generate if (number_of_clk > 1)
383 
always
384 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
385 
endgenerate
386 
 
387 
generate if (number_of_clk > 2)
388 
always
389 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
390 
endgenerate
391 
 
392 
genvar i;
393 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
394 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
395 
end
396 
endgenerate
397 
 
398 
assign #lock_delay lock = rst_n_i;
399 
 
400 
endmodule
401 
`else
402 
generate if (number_of_clk==1 & index==0) begin
403 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
404 
end
405 
endgenerate // index==0
406 
generate if (number_of_clk==1 & index==1) begin
407 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
408 
end
409 
endgenerate // index==1
410 
generate if (number_of_clk==1 & index==2) begin
411 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
412 
end
413 
endgenerate // index==2
414 
generate if (number_of_clk==1 & index==3) begin
415 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
416 
end
417 
endgenerate // index==0
418 
 
419 
generate if (number_of_clk==2 & index==0) begin
420 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
421 
end
422 
endgenerate // index==0
423 
generate if (number_of_clk==2 & index==1) begin
424 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
425 
end
426 
endgenerate // index==1
427 
generate if (number_of_clk==2 & index==2) begin
428 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
429 
end
430 
endgenerate // index==2
431 
generate if (number_of_clk==2 & index==3) begin
432 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
433 
end
434 
endgenerate // index==0
435 
 
436 
generate if (number_of_clk==3 & index==0) begin
437 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
438 
end
439 
endgenerate // index==0
440 
generate if (number_of_clk==3 & index==1) begin
441 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
442 
end
443 
endgenerate // index==1
444 
generate if (number_of_clk==3 & index==2) begin
445 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
446 
end
447 
endgenerate // index==2
448 
generate if (number_of_clk==3 & index==3) begin
449 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
450 
end
451 
endgenerate // index==0
452 
 
453 
genvar i;
454 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
455 40 unneback 
`define MODULE sync_rst
456 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
457 
`undef MODULE
458 6 unneback 
end
459 
endgenerate
460 
endmodule
461 
`endif
462 32 unneback 
///////////////////////////////////////////////////////////////////////////////
463 6 unneback 
 
464 
`else
465 
 
466 32 unneback 
///////////////////////////////////////////////////////////////////////////////
467 6 unneback 
`ifdef ALTERA
468 
 
469 32 unneback 
`timescale 1 ps/1 ps
470 40 unneback 
`define MODULE pll
471 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
472 
`undef MODULE
473 32 unneback 
parameter index = 0;
474 
parameter number_of_clk = 1;
475 
parameter period_time_0 = 20000;
476 
parameter period_time_1 = 20000;
477 
parameter period_time_2 = 20000;
478 
parameter period_time_3 = 20000;
479 
parameter period_time_4 = 20000;
480 
parameter lock_delay = 2000000;
481 
input clk_i, rst_n_i;
482 
output lock;
483 
output reg [0:number_of_clk-1] clk_o;
484 
output [0:number_of_clk-1] rst_o;
485 
 
486 
`ifdef SIM_PLL
487 
 
488 
always
489 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
490 
 
491 
generate if (number_of_clk > 1)
492 
always
493 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
494 
endgenerate
495 
 
496 
generate if (number_of_clk > 2)
497 
always
498 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
499 
endgenerate
500 
 
501 33 unneback 
generate if (number_of_clk > 3)
502 32 unneback 
always
503 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
504 
endgenerate
505 
 
506 33 unneback 
generate if (number_of_clk > 4)
507 32 unneback 
always
508 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
509 
endgenerate
510 
 
511 
genvar i;
512 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
513 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
514 
end
515 
endgenerate
516 
 
517 33 unneback 
//assign #lock_delay lock = rst_n_i;
518 
assign lock = rst_n_i;
519 32 unneback 
 
520 
endmodule
521 6 unneback 
`else
522 
 
523 33 unneback 
`ifdef VL_PLL0
524 
`ifdef VL_PLL0_CLK1
525 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
526 
`endif
527 
`ifdef VL_PLL0_CLK2
528 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
529 
`endif
530 
`ifdef VL_PLL0_CLK3
531 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
532 
`endif
533 
`ifdef VL_PLL0_CLK4
534 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
535 
`endif
536 
`ifdef VL_PLL0_CLK5
537 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
538 
`endif
539 
`endif
540 32 unneback 
 
541 33 unneback 
`ifdef VL_PLL1
542 
`ifdef VL_PLL1_CLK1
543 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
544 
`endif
545 
`ifdef VL_PLL1_CLK2
546 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
547 
`endif
548 
`ifdef VL_PLL1_CLK3
549 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
550 
`endif
551 
`ifdef VL_PLL1_CLK4
552 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
553 
`endif
554 
`ifdef VL_PLL1_CLK5
555 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
556 
`endif
557 
`endif
558 32 unneback 
 
559 33 unneback 
`ifdef VL_PLL2
560 
`ifdef VL_PLL2_CLK1
561 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
562 
`endif
563 
`ifdef VL_PLL2_CLK2
564 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
565 
`endif
566 
`ifdef VL_PLL2_CLK3
567 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
568 
`endif
569 
`ifdef VL_PLL2_CLK4
570 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
571 
`endif
572 
`ifdef VL_PLL2_CLK5
573 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
574 
`endif
575 
`endif
576 32 unneback 
 
577 33 unneback 
`ifdef VL_PLL3
578 
`ifdef VL_PLL3_CLK1
579 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
580 
`endif
581 
`ifdef VL_PLL3_CLK2
582 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
583 
`endif
584 
`ifdef VL_PLL3_CLK3
585 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
586 
`endif
587 
`ifdef VL_PLL3_CLK4
588 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
589 
`endif
590 
`ifdef VL_PLL3_CLK5
591 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
592 
`endif
593 
`endif
594 32 unneback 
 
595 
genvar i;
596 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
597 40 unneback 
`define MODULE sync_rst
598 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
599 
`undef MODULE
600 32 unneback 
end
601 
endgenerate
602 
endmodule
603 
`endif
604 
///////////////////////////////////////////////////////////////////////////////
605 
 
606 
`else
607 
 
608 6 unneback 
// generic PLL
609 17 unneback 
`timescale 1 ps/1 ps
610 40 unneback 
`define MODULE pll
611 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
612 
`undef MODULE
613 6 unneback 
parameter index = 0;
614 
parameter number_of_clk = 1;
615 17 unneback 
parameter period_time_0 = 20000;
616 
parameter period_time_1 = 20000;
617 
parameter period_time_2 = 20000;
618 6 unneback 
parameter lock_delay = 2000;
619 
input clk_i, rst_n_i;
620 
output lock;
621 
output reg [0:number_of_clk-1] clk_o;
622 
output [0:number_of_clk-1] rst_o;
623 
 
624 
always
625 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
626 
 
627 
generate if (number_of_clk > 1)
628 
always
629 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
630 
endgenerate
631 
 
632 
generate if (number_of_clk > 2)
633 
always
634 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
635 
endgenerate
636 
 
637 
genvar i;
638 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
639 40 unneback 
`define MODULE sync_rst
640 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
641 
`undef MODULE
642 6 unneback 
end
643 
endgenerate
644 
 
645 
assign #lock_delay lock = rst_n_i;
646 
 
647 
endmodule
648 
 
649 
`endif //altera
650 17 unneback 
`endif //actel
651 40 unneback 
`undef MODULE
652 
`endif//////////////////////////////////////////////////////////////////////
653 6 unneback 
////                                                              ////
654 
////  Versatile library, registers                                ////
655 
////                                                              ////
656 
////  Description                                                 ////
657 
////  Different type of registers                                 ////
658 
////                                                              ////
659 
////                                                              ////
660 
////  To Do:                                                      ////
661 
////   - add more different registers                             ////
662 
////                                                              ////
663 
////  Author(s):                                                  ////
664 
////      - Michael Unneback, unneback@opencores.org              ////
665 
////        ORSoC AB                                              ////
666 
////                                                              ////
667 
//////////////////////////////////////////////////////////////////////
668 
////                                                              ////
669 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
670 
////                                                              ////
671 
//// This source file may be used and distributed without         ////
672 
//// restriction provided that this copyright statement is not    ////
673 
//// removed from the file and that any derivative work contains  ////
674 
//// the original copyright notice and the associated disclaimer. ////
675 
////                                                              ////
676 
//// This source file is free software; you can redistribute it   ////
677 
//// and/or modify it under the terms of the GNU Lesser General   ////
678 
//// Public License as published by the Free Software Foundation; ////
679 
//// either version 2.1 of the License, or (at your option) any   ////
680 
//// later version.                                               ////
681 
////                                                              ////
682 
//// This source is distributed in the hope that it will be       ////
683 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
684 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
685 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
686 
//// details.                                                     ////
687 
////                                                              ////
688 
//// You should have received a copy of the GNU Lesser General    ////
689 
//// Public License along with this source; if not, download it   ////
690 
//// from http://www.opencores.org/lgpl.shtml                     ////
691 
////                                                              ////
692 
//////////////////////////////////////////////////////////////////////
693 
 
694 40 unneback 
`ifdef DFF
695 
`define MODULE dff
696 
module `BASE`MODULE ( d, q, clk, rst);
697 
`undef MODULE
698 6 unneback 
        parameter width = 1;
699 
        parameter reset_value = 0;
700 
 
701 
        input [width-1:0] d;
702 
        input clk, rst;
703 
        output reg [width-1:0] q;
704 
 
705 
        always @ (posedge clk or posedge rst)
706 
        if (rst)
707 
                q <= reset_value;
708 
        else
709 
                q <= d;
710 
 
711 
endmodule
712 40 unneback 
`endif
713 6 unneback 
 
714 40 unneback 
`ifdef DFF_ARRAY
715 
`define MODULE dff_array
716 
module `BASE`MODULE ( d, q, clk, rst);
717 
`undef MODULE
718 6 unneback 
 
719 
        parameter width = 1;
720 
        parameter depth = 2;
721 
        parameter reset_value = 1'b0;
722 
 
723 
        input [width-1:0] d;
724 
        input clk, rst;
725 
        output [width-1:0] q;
726 
        reg  [0:depth-1] q_tmp [width-1:0];
727 
        integer i;
728 
        always @ (posedge clk or posedge rst)
729 
        if (rst) begin
730 
            for (i=0;i<depth;i=i+1)
731 
                q_tmp[i] <= {width{reset_value}};
732 
        end else begin
733 
            q_tmp[0] <= d;
734 
            for (i=1;i<depth;i=i+1)
735 
                q_tmp[i] <= q_tmp[i-1];
736 
        end
737 
 
738 
    assign q = q_tmp[depth-1];
739 
 
740 
endmodule
741 40 unneback 
`endif
742 6 unneback 
 
743 40 unneback 
`ifdef DFF_CE
744 
`define MODULE dff_ce
745 
module `BASE`MODULE ( d, ce, q, clk, rst);
746 
`undef MODULE
747 6 unneback 
 
748 
        parameter width = 1;
749 
        parameter reset_value = 0;
750 
 
751 
        input [width-1:0] d;
752 
        input ce, clk, rst;
753 
        output reg [width-1:0] q;
754 
 
755 
        always @ (posedge clk or posedge rst)
756 
        if (rst)
757 
                q <= reset_value;
758 
        else
759 
                if (ce)
760 
                        q <= d;
761 
 
762 
endmodule
763 40 unneback 
`endif
764 6 unneback 
 
765 40 unneback 
`ifdef DFF_CE_CLEAR
766 
`define MODULE dff_ce_clear
767 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
768 
`undef MODULE
769 8 unneback 
 
770 
        parameter width = 1;
771 
        parameter reset_value = 0;
772 
 
773 
        input [width-1:0] d;
774 10 unneback 
        input ce, clear, clk, rst;
775 8 unneback 
        output reg [width-1:0] q;
776 
 
777 
        always @ (posedge clk or posedge rst)
778 
        if (rst)
779 
            q <= reset_value;
780 
        else
781 
            if (ce)
782 
                if (clear)
783 
                    q <= {width{1'b0}};
784 
                else
785 
                    q <= d;
786 
 
787 
endmodule
788 40 unneback 
`endif
789 8 unneback 
 
790 40 unneback 
`ifdef DF_CE_SET
791 
`define MODULE dff_ce_set
792 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
793 
`undef MODULE
794 24 unneback 
 
795 
        parameter width = 1;
796 
        parameter reset_value = 0;
797 
 
798 
        input [width-1:0] d;
799 
        input ce, set, clk, rst;
800 
        output reg [width-1:0] q;
801 
 
802 
        always @ (posedge clk or posedge rst)
803 
        if (rst)
804 
            q <= reset_value;
805 
        else
806 
            if (ce)
807 
                if (set)
808 
                    q <= {width{1'b1}};
809 
                else
810 
                    q <= d;
811 
 
812 
endmodule
813 40 unneback 
`endif
814 24 unneback 
 
815 40 unneback 
`ifdef SPR
816 
`define MODULE spr
817 
module `BASE`MODULE ( sp, r, q, clk, rst);
818 
`undef MODULE
819 
 
820 29 unneback 
        parameter width = 1;
821 
        parameter reset_value = 0;
822 
 
823 
        input sp, r;
824 
        output reg q;
825 
        input clk, rst;
826 
 
827 
        always @ (posedge clk or posedge rst)
828 
        if (rst)
829 
            q <= reset_value;
830 
        else
831 
            if (sp)
832 
                q <= 1'b1;
833 
            else if (r)
834 
                q <= 1'b0;
835 
 
836 
endmodule
837 40 unneback 
`endif
838 29 unneback 
 
839 40 unneback 
`ifdef SRP
840 
`define MODULE srp
841 
module `BASE`MODULE ( s, rp, q, clk, rst);
842 
`undef MODULE
843 
 
844 29 unneback 
        parameter width = 1;
845 
        parameter reset_value = 0;
846 
 
847 
        input s, rp;
848 
        output reg q;
849 
        input clk, rst;
850 
 
851 
        always @ (posedge clk or posedge rst)
852 
        if (rst)
853 
            q <= reset_value;
854 
        else
855 
            if (rp)
856 
                q <= 1'b0;
857 
            else if (s)
858 
                q <= 1'b1;
859 
 
860 
endmodule
861 40 unneback 
`endif
862 29 unneback 
 
863 40 unneback 
`ifdef ALTERA
864 29 unneback 
 
865 40 unneback 
`ifdef DFF_SR
866 6 unneback 
// megafunction wizard: %LPM_FF%
867 
// GENERATION: STANDARD
868 
// VERSION: WM1.0
869 
// MODULE: lpm_ff
870 
 
871 
// ============================================================
872 
// File Name: dff_sr.v
873 
// Megafunction Name(s):
874 
//                      lpm_ff
875 
//
876 
// Simulation Library Files(s):
877 
//                      lpm
878 
// ============================================================
879 
// ************************************************************
880 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
881 
//
882 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
883 
// ************************************************************
884 
 
885 
 
886 
//Copyright (C) 1991-2010 Altera Corporation
887 
//Your use of Altera Corporation's design tools, logic functions
888 
//and other software and tools, and its AMPP partner logic
889 
//functions, and any output files from any of the foregoing
890 
//(including device programming or simulation files), and any
891 
//associated documentation or information are expressly subject
892 
//to the terms and conditions of the Altera Program License
893 
//Subscription Agreement, Altera MegaCore Function License
894 
//Agreement, or other applicable license agreement, including,
895 
//without limitation, that your use is for the sole purpose of
896 
//programming logic devices manufactured by Altera and sold by
897 
//Altera or its authorized distributors.  Please refer to the
898 
//applicable agreement for further details.
899 
 
900 
 
901 
// synopsys translate_off
902 
`timescale 1 ps / 1 ps
903 
// synopsys translate_on
904 40 unneback 
`define MODULE dff_sr
905 
module `BASE`MODULE (
906 
`undef MODULE
907 
 
908 6 unneback 
        aclr,
909 
        aset,
910 
        clock,
911 
        data,
912 
        q);
913 
 
914 
        input     aclr;
915 
        input     aset;
916 
        input     clock;
917 
        input     data;
918 
        output    q;
919 
 
920 
        wire [0:0] sub_wire0;
921 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
922 
        wire  q = sub_wire1;
923 
        wire  sub_wire2 = data;
924 
        wire  sub_wire3 = sub_wire2;
925 
 
926 
        lpm_ff  lpm_ff_component (
927 
                                .aclr (aclr),
928 
                                .clock (clock),
929 
                                .data (sub_wire3),
930 
                                .aset (aset),
931 
                                .q (sub_wire0)
932 
                                // synopsys translate_off
933 
                                ,
934 
                                .aload (),
935 
                                .enable (),
936 
                                .sclr (),
937 
                                .sload (),
938 
                                .sset ()
939 
                                // synopsys translate_on
940 
                                );
941 
        defparam
942 
                lpm_ff_component.lpm_fftype = "DFF",
943 
                lpm_ff_component.lpm_type = "LPM_FF",
944 
                lpm_ff_component.lpm_width = 1;
945 
 
946 
 
947 
endmodule
948 
 
949 
// ============================================================
950 
// CNX file retrieval info
951 
// ============================================================
952 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
953 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
954 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
955 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
956 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
957 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
958 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
959 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
960 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
961 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
962 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
963 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
964 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
965 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
966 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
967 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
968 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
969 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
970 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
971 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
972 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
973 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
974 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
975 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
976 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
977 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
978 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
979 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
980 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
981 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
982 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
983 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
984 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
985 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
986 
// Retrieval info: LIB_FILE: lpm
987 40 unneback 
`endif
988 6 unneback 
 
989 
`else
990 
 
991 40 unneback 
`ifdef DFF_SR
992 
`define MODULE dff_sr
993 
module `BASE`MODULE ( aclr, aset, clock, data, q);
994 
`undef MODULE
995 6 unneback 
 
996 
    input         aclr;
997 
    input         aset;
998 
    input         clock;
999 
    input         data;
1000 
    output reg    q;
1001 
 
1002 
   always @ (posedge clock or posedge aclr or posedge aset)
1003 
     if (aclr)
1004 
       q <= 1'b0;
1005 
     else if (aset)
1006 
       q <= 1'b1;
1007 
     else
1008 
       q <= data;
1009 
 
1010 
endmodule
1011 40 unneback 
`endif
1012 6 unneback 
 
1013 
`endif
1014 
 
1015 
// LATCH
1016 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1017 
`ifdef ALTERA
1018 40 unneback 
 
1019 
`ifdef LATCH
1020 
`define MODULE latch
1021 
module `BASE`MODULE ( d, le, q, clk);
1022 
`undef MODULE
1023 6 unneback 
input d, le;
1024 
output q;
1025 
input clk;
1026 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1027 
endmodule
1028 40 unneback 
`endif
1029 
 
1030 6 unneback 
`else
1031 40 unneback 
 
1032 
`ifdef LATCH
1033 
`define MODULE latch
1034 
module `BASE`MODULE ( d, le, q, clk);
1035 
`undef MODULE
1036 6 unneback 
input d, le;
1037 48 unneback 
input clk;
1038 
always @ (le or d)
1039 
if le
1040 
    d <= q;
1041 6 unneback 
endmodule
1042 15 unneback 
`endif
1043 
 
1044 40 unneback 
`endif
1045 
 
1046 
`ifdef SHREG
1047 
`define MODULE shreg
1048 
module `BASE`MODULE ( d, q, clk, rst);
1049 
`undef MODULE
1050 
 
1051 17 unneback 
parameter depth = 10;
1052 
input d;
1053 
output q;
1054 
input clk, rst;
1055 
 
1056 
reg [1:depth] dffs;
1057 
 
1058 
always @ (posedge clk or posedge rst)
1059 
if (rst)
1060 
    dffs <= {depth{1'b0}};
1061 
else
1062 
    dffs <= {d,dffs[1:depth-1]};
1063 
assign q = dffs[depth];
1064 
endmodule
1065 40 unneback 
`endif
1066 17 unneback 
 
1067 40 unneback 
`ifdef SHREG_CE
1068 
`define MODULE shreg_ce
1069 
module `BASE`MODULE ( d, ce, q, clk, rst);
1070 
`undef MODULE
1071 17 unneback 
parameter depth = 10;
1072 
input d, ce;
1073 
output q;
1074 
input clk, rst;
1075 
 
1076 
reg [1:depth] dffs;
1077 
 
1078 
always @ (posedge clk or posedge rst)
1079 
if (rst)
1080 
    dffs <= {depth{1'b0}};
1081 
else
1082 
    if (ce)
1083 
        dffs <= {d,dffs[1:depth-1]};
1084 
assign q = dffs[depth];
1085 
endmodule
1086 40 unneback 
`endif
1087 17 unneback 
 
1088 40 unneback 
`ifdef DELAY
1089 
`define MODULE delay
1090 
module `BASE`MODULE ( d, q, clk, rst);
1091 
`undef MODULE
1092 15 unneback 
parameter depth = 10;
1093 
input d;
1094 
output q;
1095 
input clk, rst;
1096 
 
1097 
reg [1:depth] dffs;
1098 
 
1099 
always @ (posedge clk or posedge rst)
1100 
if (rst)
1101 
    dffs <= {depth{1'b0}};
1102 
else
1103 
    dffs <= {d,dffs[1:depth-1]};
1104 
assign q = dffs[depth];
1105 17 unneback 
endmodule
1106 40 unneback 
`endif
1107 17 unneback 
 
1108 40 unneback 
`ifdef DELAY_EMPTYFLAG
1109 
`define MODULE delay_emptyflag
1110 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1111 40 unneback 
`undef MODULE
1112 17 unneback 
parameter depth = 10;
1113 
input d;
1114 
output q, emptyflag;
1115 
input clk, rst;
1116 
 
1117 
reg [1:depth] dffs;
1118 
 
1119 
always @ (posedge clk or posedge rst)
1120 
if (rst)
1121 
    dffs <= {depth{1'b0}};
1122 
else
1123 
    dffs <= {d,dffs[1:depth-1]};
1124 
assign q = dffs[depth];
1125 
assign emptyflag = !(|dffs);
1126 
endmodule
1127 40 unneback 
`endif
1128 17 unneback 
//////////////////////////////////////////////////////////////////////
1129 6 unneback 
////                                                              ////
1130 18 unneback 
////  Logic functions                                             ////
1131 
////                                                              ////
1132 
////  Description                                                 ////
1133 
////  Logic functions such as multiplexers                        ////
1134 
////                                                              ////
1135 
////                                                              ////
1136 
////  To Do:                                                      ////
1137 
////   -                                                          ////
1138 
////                                                              ////
1139 
////  Author(s):                                                  ////
1140 
////      - Michael Unneback, unneback@opencores.org              ////
1141 
////        ORSoC AB                                              ////
1142 
////                                                              ////
1143 
//////////////////////////////////////////////////////////////////////
1144 
////                                                              ////
1145 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1146 
////                                                              ////
1147 
//// This source file may be used and distributed without         ////
1148 
//// restriction provided that this copyright statement is not    ////
1149 
//// removed from the file and that any derivative work contains  ////
1150 
//// the original copyright notice and the associated disclaimer. ////
1151 
////                                                              ////
1152 
//// This source file is free software; you can redistribute it   ////
1153 
//// and/or modify it under the terms of the GNU Lesser General   ////
1154 
//// Public License as published by the Free Software Foundation; ////
1155 
//// either version 2.1 of the License, or (at your option) any   ////
1156 
//// later version.                                               ////
1157 
////                                                              ////
1158 
//// This source is distributed in the hope that it will be       ////
1159 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1160 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1161 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1162 
//// details.                                                     ////
1163 
////                                                              ////
1164 
//// You should have received a copy of the GNU Lesser General    ////
1165 
//// Public License along with this source; if not, download it   ////
1166 
//// from http://www.opencores.org/lgpl.shtml                     ////
1167 
////                                                              ////
1168 
//////////////////////////////////////////////////////////////////////
1169 40 unneback 
`ifdef MUX_ANDOR
1170 
`define MODULE mux_andor
1171 
module `BASE`MODULE ( a, sel, dout);
1172 
`undef MODULE
1173 36 unneback 
 
1174 
parameter width = 32;
1175 
parameter nr_of_ports = 4;
1176 
 
1177 
input [nr_of_ports*width-1:0] a;
1178 
input [nr_of_ports-1:0] sel;
1179 
output reg [width-1:0] dout;
1180 
 
1181 38 unneback 
integer i,j;
1182 
 
1183 36 unneback 
always @ (a, sel)
1184 
begin
1185 
    dout = a[width-1:0] & {width{sel[0]}};
1186 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1187 
        for (j=0;j<width;j=j+1)
1188 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1189 36 unneback 
end
1190 
 
1191 
endmodule
1192 40 unneback 
`endif
1193 36 unneback 
 
1194 40 unneback 
`ifdef MUX2_ANDOR
1195 
`define MODULE mux2_andor
1196 
module `BASE`MODULE ( a1, a0, sel, dout);
1197 
`undef MODULE
1198 18 unneback 
 
1199 34 unneback 
parameter width = 32;
1200 35 unneback 
localparam nr_of_ports = 2;
1201 34 unneback 
input [width-1:0] a1, a0;
1202 
input [nr_of_ports-1:0] sel;
1203 
output [width-1:0] dout;
1204 
 
1205 40 unneback 
`define MODULE mux_andor
1206 
`BASE`MODULE
1207 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1208 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1209 40 unneback 
`undef MODULE
1210 
 
1211 34 unneback 
endmodule
1212 40 unneback 
`endif
1213 34 unneback 
 
1214 40 unneback 
`ifdef MUX3_ANDOR
1215 
`define MODULE mux3_andor
1216 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1217 
`undef MODULE
1218 34 unneback 
 
1219 
parameter width = 32;
1220 35 unneback 
localparam nr_of_ports = 3;
1221 34 unneback 
input [width-1:0] a2, a1, a0;
1222 
input [nr_of_ports-1:0] sel;
1223 
output [width-1:0] dout;
1224 
 
1225 40 unneback 
`define MODULE mux_andor
1226 
`BASE`MODULE
1227 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1228 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1229 40 unneback 
`undef MODULE
1230 34 unneback 
endmodule
1231 40 unneback 
`endif
1232 34 unneback 
 
1233 40 unneback 
`ifdef MUX4_ANDOR
1234 
`define MODULE mux4_andor
1235 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1236 
`undef MODULE
1237 18 unneback 
 
1238 
parameter width = 32;
1239 35 unneback 
localparam nr_of_ports = 4;
1240 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1241 
input [nr_of_ports-1:0] sel;
1242 22 unneback 
output [width-1:0] dout;
1243 18 unneback 
 
1244 40 unneback 
`define MODULE mux_andor
1245 
`BASE`MODULE
1246 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1247 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1248 40 unneback 
`undef MODULE
1249 18 unneback 
 
1250 
endmodule
1251 40 unneback 
`endif
1252 18 unneback 
 
1253 40 unneback 
`ifdef MUX5_ANDOR
1254 
`define MODULE mux5_andor
1255 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1256 
`undef MODULE
1257 18 unneback 
 
1258 
parameter width = 32;
1259 35 unneback 
localparam nr_of_ports = 5;
1260 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1261 
input [nr_of_ports-1:0] sel;
1262 22 unneback 
output [width-1:0] dout;
1263 18 unneback 
 
1264 40 unneback 
`define MODULE mux_andor
1265 
`BASE`MODULE
1266 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1267 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1268 40 unneback 
`undef MODULE
1269 18 unneback 
 
1270 
endmodule
1271 40 unneback 
`endif
1272 18 unneback 
 
1273 40 unneback 
`ifdef MUX6_ANDOR
1274 
`define MODULE mux6_andor
1275 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1276 
`undef MODULE
1277 18 unneback 
 
1278 
parameter width = 32;
1279 35 unneback 
localparam nr_of_ports = 6;
1280 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1281 
input [nr_of_ports-1:0] sel;
1282 22 unneback 
output [width-1:0] dout;
1283 18 unneback 
 
1284 40 unneback 
`define MODULE mux_andor
1285 
`BASE`MODULE
1286 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1287 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1288 40 unneback 
`undef MODULE
1289 18 unneback 
 
1290 
endmodule
1291 40 unneback 
`endif
1292 43 unneback 
 
1293 
`ifdef PARITY
1294 
 
1295 
`define MODULE parity_generate
1296 
module `BASE`MODULE (data, parity);
1297 
`undef MODULE
1298 
parameter word_size = 32;
1299 
parameter chunk_size = 8;
1300 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1301 
input [word_size-1:0] data;
1302 
output reg [word_size/chunk_size-1:0] parity;
1303 
integer i,j;
1304 
always @ (data)
1305 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1306 
    parity[i] = parity_type;
1307 
    for (j=0;j<chunk_size;j=j+1) begin
1308 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1309 43 unneback 
    end
1310 
end
1311 
endmodule
1312 
 
1313 
`define MODULE parity_check
1314 
module `BASE`MODULE( data, parity, parity_error);
1315 
`undef MODULE
1316 
parameter word_size = 32;
1317 
parameter chunk_size = 8;
1318 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1319 
input [word_size-1:0] data;
1320 
input [word_size/chunk_size-1:0] parity;
1321 
output parity_error;
1322 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1323 43 unneback 
integer i,j;
1324 
always @ (data or parity)
1325 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1326 
    error_flag[i] = parity[i] ^ parity_type;
1327 
    for (j=0;j<chunk_size;j=j+1) begin
1328 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1329 43 unneback 
    end
1330 
end
1331 
assign parity_error = |error_flag;
1332 
endmodule
1333 
 
1334 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1335 
////                                                              ////
1336 
////  IO functions                                                ////
1337 
////                                                              ////
1338 
////  Description                                                 ////
1339 
////  IO functions such as IOB flip-flops                         ////
1340 
////                                                              ////
1341 
////                                                              ////
1342 
////  To Do:                                                      ////
1343 
////   -                                                          ////
1344 
////                                                              ////
1345 
////  Author(s):                                                  ////
1346 
////      - Michael Unneback, unneback@opencores.org              ////
1347 
////        ORSoC AB                                              ////
1348 
////                                                              ////
1349 18 unneback 
//////////////////////////////////////////////////////////////////////
1350 
////                                                              ////
1351 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1352 
////                                                              ////
1353 
//// This source file may be used and distributed without         ////
1354 
//// restriction provided that this copyright statement is not    ////
1355 
//// removed from the file and that any derivative work contains  ////
1356 
//// the original copyright notice and the associated disclaimer. ////
1357 
////                                                              ////
1358 
//// This source file is free software; you can redistribute it   ////
1359 
//// and/or modify it under the terms of the GNU Lesser General   ////
1360 
//// Public License as published by the Free Software Foundation; ////
1361 
//// either version 2.1 of the License, or (at your option) any   ////
1362 
//// later version.                                               ////
1363 
////                                                              ////
1364 
//// This source is distributed in the hope that it will be       ////
1365 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1366 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1367 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1368 
//// details.                                                     ////
1369 
////                                                              ////
1370 
//// You should have received a copy of the GNU Lesser General    ////
1371 
//// Public License along with this source; if not, download it   ////
1372 
//// from http://www.opencores.org/lgpl.shtml                     ////
1373 
////                                                              ////
1374 
//////////////////////////////////////////////////////////////////////
1375 45 unneback 
`timescale 1ns/1ns
1376 44 unneback 
`ifdef O_DFF
1377 
`define MODULE o_dff
1378 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1379 
`undef MODULE
1380 
parameter width = 1;
1381 45 unneback 
parameter reset_value = {width{1'b0}};
1382 
input  [width-1:0]  d_i;
1383 44 unneback 
output [width-1:0] o_pad;
1384 
input clk, rst;
1385 
wire [width-1:0] d_i_int `SYN_KEEP;
1386 45 unneback 
reg  [width-1:0] o_pad_int;
1387 44 unneback 
assign d_i_int = d_i;
1388 
genvar i;
1389 45 unneback 
generate
1390 44 unneback 
for (i=0;i<width;i=i+1) begin
1391 
    always @ (posedge clk or posedge rst)
1392 
    if (rst)
1393 45 unneback 
        o_pad_int[i] <= reset_value[i];
1394 44 unneback 
    else
1395 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1396 
    assign #1 o_pad[i] = o_pad_int[i];
1397 44 unneback 
end
1398 
endgenerate
1399 
endmodule
1400 
`endif
1401 
 
1402 45 unneback 
`timescale 1ns/1ns
1403 44 unneback 
`ifdef IO_DFF_OE
1404 
`define MODULE io_dff_oe
1405 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1406 
`undef MODULE
1407 
parameter width = 1;
1408 
input  [width-1:0] d_o;
1409 
output reg [width-1:0] d_i;
1410 
input oe;
1411 
inout [width-1:0] io_pad;
1412 
input clk, rst;
1413 
wire [width-1:0] oe_d `SYN_KEEP;
1414 
reg [width-1:0] oe_q;
1415 
reg [width-1:0] d_o_q;
1416 
assign oe_d = {width{oe}};
1417 
genvar i;
1418 
generate
1419 
for (i=0;i<width;i=i+1) begin
1420 
    always @ (posedge clk or posedge rst)
1421 
    if (rst)
1422 
        oe_q[i] <= 1'b0;
1423 
    else
1424 
        oe_q[i] <= oe_d[i];
1425 
    always @ (posedge clk or posedge rst)
1426 
    if (rst)
1427 
        d_o_q[i] <= 1'b0;
1428 
    else
1429 
        d_o_q[i] <= d_o[i];
1430 
    always @ (posedge clk or posedge rst)
1431 
    if (rst)
1432 
        d_i[i] <= 1'b0;
1433 
    else
1434 
        d_i[i] <= io_pad[i];
1435 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1436 44 unneback 
end
1437 
endgenerate
1438 
endmodule
1439 
`endif
1440 
`ifdef CNT_BIN
1441 
//////////////////////////////////////////////////////////////////////
1442 
////                                                              ////
1443 6 unneback 
////  Versatile counter                                           ////
1444 
////                                                              ////
1445 
////  Description                                                 ////
1446 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1447 
////  counter                                                     ////
1448 
////                                                              ////
1449 
////  To Do:                                                      ////
1450 
////   - add LFSR with more taps                                  ////
1451 
////                                                              ////
1452 
////  Author(s):                                                  ////
1453 
////      - Michael Unneback, unneback@opencores.org              ////
1454 
////        ORSoC AB                                              ////
1455 
////                                                              ////
1456 
//////////////////////////////////////////////////////////////////////
1457 
////                                                              ////
1458 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1459 
////                                                              ////
1460 
//// This source file may be used and distributed without         ////
1461 
//// restriction provided that this copyright statement is not    ////
1462 
//// removed from the file and that any derivative work contains  ////
1463 
//// the original copyright notice and the associated disclaimer. ////
1464 
////                                                              ////
1465 
//// This source file is free software; you can redistribute it   ////
1466 
//// and/or modify it under the terms of the GNU Lesser General   ////
1467 
//// Public License as published by the Free Software Foundation; ////
1468 
//// either version 2.1 of the License, or (at your option) any   ////
1469 
//// later version.                                               ////
1470 
////                                                              ////
1471 
//// This source is distributed in the hope that it will be       ////
1472 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1473 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1474 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1475 
//// details.                                                     ////
1476 
////                                                              ////
1477 
//// You should have received a copy of the GNU Lesser General    ////
1478 
//// Public License along with this source; if not, download it   ////
1479 
//// from http://www.opencores.org/lgpl.shtml                     ////
1480 
////                                                              ////
1481 
//////////////////////////////////////////////////////////////////////
1482 
 
1483 
// binary counter
1484 22 unneback 
 
1485 40 unneback 
`define MODULE cnt_bin
1486 
module `BASE`MODULE (
1487 
`undef MODULE
1488 
 q, rst, clk);
1489 
 
1490 22 unneback 
   parameter length = 4;
1491 
   output [length:1] q;
1492 
   input rst;
1493 
   input clk;
1494 
 
1495 
   parameter clear_value = 0;
1496 
   parameter set_value = 1;
1497 
   parameter wrap_value = 0;
1498 
   parameter level1_value = 15;
1499 
 
1500 
   reg  [length:1] qi;
1501 
   wire [length:1] q_next;
1502 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1503 
 
1504 
   always @ (posedge clk or posedge rst)
1505 
     if (rst)
1506 
       qi <= {length{1'b0}};
1507 
     else
1508 
       qi <= q_next;
1509 
 
1510 
   assign q = qi;
1511 
 
1512 
endmodule
1513 40 unneback 
`endif
1514 
`ifdef CNT_BIN_CLEAR
1515 22 unneback 
//////////////////////////////////////////////////////////////////////
1516 
////                                                              ////
1517 
////  Versatile counter                                           ////
1518 
////                                                              ////
1519 
////  Description                                                 ////
1520 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1521 
////  counter                                                     ////
1522 
////                                                              ////
1523 
////  To Do:                                                      ////
1524 
////   - add LFSR with more taps                                  ////
1525 
////                                                              ////
1526 
////  Author(s):                                                  ////
1527 
////      - Michael Unneback, unneback@opencores.org              ////
1528 
////        ORSoC AB                                              ////
1529 
////                                                              ////
1530 
//////////////////////////////////////////////////////////////////////
1531 
////                                                              ////
1532 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1533 
////                                                              ////
1534 
//// This source file may be used and distributed without         ////
1535 
//// restriction provided that this copyright statement is not    ////
1536 
//// removed from the file and that any derivative work contains  ////
1537 
//// the original copyright notice and the associated disclaimer. ////
1538 
////                                                              ////
1539 
//// This source file is free software; you can redistribute it   ////
1540 
//// and/or modify it under the terms of the GNU Lesser General   ////
1541 
//// Public License as published by the Free Software Foundation; ////
1542 
//// either version 2.1 of the License, or (at your option) any   ////
1543 
//// later version.                                               ////
1544 
////                                                              ////
1545 
//// This source is distributed in the hope that it will be       ////
1546 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1547 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1548 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1549 
//// details.                                                     ////
1550 
////                                                              ////
1551 
//// You should have received a copy of the GNU Lesser General    ////
1552 
//// Public License along with this source; if not, download it   ////
1553 
//// from http://www.opencores.org/lgpl.shtml                     ////
1554 
////                                                              ////
1555 
//////////////////////////////////////////////////////////////////////
1556 
 
1557 
// binary counter
1558 
 
1559 40 unneback 
`define MODULE cnt_bin_clear
1560 
module `BASE`MODULE (
1561 
`undef MODULE
1562 
 clear, q, rst, clk);
1563 
 
1564 22 unneback 
   parameter length = 4;
1565 
   input clear;
1566 
   output [length:1] q;
1567 
   input rst;
1568 
   input clk;
1569 
 
1570 
   parameter clear_value = 0;
1571 
   parameter set_value = 1;
1572 
   parameter wrap_value = 0;
1573 
   parameter level1_value = 15;
1574 
 
1575 
   reg  [length:1] qi;
1576 
   wire [length:1] q_next;
1577 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1578 
 
1579 
   always @ (posedge clk or posedge rst)
1580 
     if (rst)
1581 
       qi <= {length{1'b0}};
1582 
     else
1583 
       qi <= q_next;
1584 
 
1585 
   assign q = qi;
1586 
 
1587 
endmodule
1588 40 unneback 
`endif
1589 
`ifdef CNT_BIN_CE
1590 22 unneback 
//////////////////////////////////////////////////////////////////////
1591 
////                                                              ////
1592 
////  Versatile counter                                           ////
1593 
////                                                              ////
1594 
////  Description                                                 ////
1595 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1596 
////  counter                                                     ////
1597 
////                                                              ////
1598 
////  To Do:                                                      ////
1599 
////   - add LFSR with more taps                                  ////
1600 
////                                                              ////
1601 
////  Author(s):                                                  ////
1602 
////      - Michael Unneback, unneback@opencores.org              ////
1603 
////        ORSoC AB                                              ////
1604 
////                                                              ////
1605 
//////////////////////////////////////////////////////////////////////
1606 
////                                                              ////
1607 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1608 
////                                                              ////
1609 
//// This source file may be used and distributed without         ////
1610 
//// restriction provided that this copyright statement is not    ////
1611 
//// removed from the file and that any derivative work contains  ////
1612 
//// the original copyright notice and the associated disclaimer. ////
1613 
////                                                              ////
1614 
//// This source file is free software; you can redistribute it   ////
1615 
//// and/or modify it under the terms of the GNU Lesser General   ////
1616 
//// Public License as published by the Free Software Foundation; ////
1617 
//// either version 2.1 of the License, or (at your option) any   ////
1618 
//// later version.                                               ////
1619 
////                                                              ////
1620 
//// This source is distributed in the hope that it will be       ////
1621 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1622 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1623 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1624 
//// details.                                                     ////
1625 
////                                                              ////
1626 
//// You should have received a copy of the GNU Lesser General    ////
1627 
//// Public License along with this source; if not, download it   ////
1628 
//// from http://www.opencores.org/lgpl.shtml                     ////
1629 
////                                                              ////
1630 
//////////////////////////////////////////////////////////////////////
1631 
 
1632 
// binary counter
1633 6 unneback 
 
1634 40 unneback 
`define MODULE cnt_bin_ce
1635 
module `BASE`MODULE (
1636 
`undef MODULE
1637 
 cke, q, rst, clk);
1638 
 
1639 6 unneback 
   parameter length = 4;
1640 
   input cke;
1641 
   output [length:1] q;
1642 
   input rst;
1643 
   input clk;
1644 
 
1645 
   parameter clear_value = 0;
1646 
   parameter set_value = 1;
1647 
   parameter wrap_value = 0;
1648 
   parameter level1_value = 15;
1649 
 
1650 
   reg  [length:1] qi;
1651 
   wire [length:1] q_next;
1652 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1653 
 
1654 
   always @ (posedge clk or posedge rst)
1655 
     if (rst)
1656 
       qi <= {length{1'b0}};
1657 
     else
1658 
     if (cke)
1659 
       qi <= q_next;
1660 
 
1661 
   assign q = qi;
1662 
 
1663 
endmodule
1664 40 unneback 
`endif
1665 
`ifdef CNT_BIN_CE_CLEAR
1666 6 unneback 
//////////////////////////////////////////////////////////////////////
1667 
////                                                              ////
1668 
////  Versatile counter                                           ////
1669 
////                                                              ////
1670 
////  Description                                                 ////
1671 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1672 
////  counter                                                     ////
1673 
////                                                              ////
1674 
////  To Do:                                                      ////
1675 
////   - add LFSR with more taps                                  ////
1676 
////                                                              ////
1677 
////  Author(s):                                                  ////
1678 
////      - Michael Unneback, unneback@opencores.org              ////
1679 
////        ORSoC AB                                              ////
1680 
////                                                              ////
1681 
//////////////////////////////////////////////////////////////////////
1682 
////                                                              ////
1683 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1684 
////                                                              ////
1685 
//// This source file may be used and distributed without         ////
1686 
//// restriction provided that this copyright statement is not    ////
1687 
//// removed from the file and that any derivative work contains  ////
1688 
//// the original copyright notice and the associated disclaimer. ////
1689 
////                                                              ////
1690 
//// This source file is free software; you can redistribute it   ////
1691 
//// and/or modify it under the terms of the GNU Lesser General   ////
1692 
//// Public License as published by the Free Software Foundation; ////
1693 
//// either version 2.1 of the License, or (at your option) any   ////
1694 
//// later version.                                               ////
1695 
////                                                              ////
1696 
//// This source is distributed in the hope that it will be       ////
1697 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1698 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1699 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1700 
//// details.                                                     ////
1701 
////                                                              ////
1702 
//// You should have received a copy of the GNU Lesser General    ////
1703 
//// Public License along with this source; if not, download it   ////
1704 
//// from http://www.opencores.org/lgpl.shtml                     ////
1705 
////                                                              ////
1706 
//////////////////////////////////////////////////////////////////////
1707 
 
1708 
// binary counter
1709 
 
1710 40 unneback 
`define MODULE cnt_bin_ce_clear
1711 
module `BASE`MODULE (
1712 
`undef MODULE
1713 
 clear, cke, q, rst, clk);
1714 
 
1715 6 unneback 
   parameter length = 4;
1716 
   input clear;
1717 
   input cke;
1718 
   output [length:1] q;
1719 
   input rst;
1720 
   input clk;
1721 
 
1722 
   parameter clear_value = 0;
1723 
   parameter set_value = 1;
1724 
   parameter wrap_value = 0;
1725 
   parameter level1_value = 15;
1726 
 
1727 
   reg  [length:1] qi;
1728 
   wire [length:1] q_next;
1729 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1730 
 
1731 
   always @ (posedge clk or posedge rst)
1732 
     if (rst)
1733 
       qi <= {length{1'b0}};
1734 
     else
1735 
     if (cke)
1736 
       qi <= q_next;
1737 
 
1738 
   assign q = qi;
1739 
 
1740 
endmodule
1741 40 unneback 
`endif
1742 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1743 6 unneback 
//////////////////////////////////////////////////////////////////////
1744 
////                                                              ////
1745 
////  Versatile counter                                           ////
1746 
////                                                              ////
1747 
////  Description                                                 ////
1748 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1749 
////  counter                                                     ////
1750 
////                                                              ////
1751 
////  To Do:                                                      ////
1752 
////   - add LFSR with more taps                                  ////
1753 
////                                                              ////
1754 
////  Author(s):                                                  ////
1755 
////      - Michael Unneback, unneback@opencores.org              ////
1756 
////        ORSoC AB                                              ////
1757 
////                                                              ////
1758 
//////////////////////////////////////////////////////////////////////
1759 
////                                                              ////
1760 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1761 
////                                                              ////
1762 
//// This source file may be used and distributed without         ////
1763 
//// restriction provided that this copyright statement is not    ////
1764 
//// removed from the file and that any derivative work contains  ////
1765 
//// the original copyright notice and the associated disclaimer. ////
1766 
////                                                              ////
1767 
//// This source file is free software; you can redistribute it   ////
1768 
//// and/or modify it under the terms of the GNU Lesser General   ////
1769 
//// Public License as published by the Free Software Foundation; ////
1770 
//// either version 2.1 of the License, or (at your option) any   ////
1771 
//// later version.                                               ////
1772 
////                                                              ////
1773 
//// This source is distributed in the hope that it will be       ////
1774 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1775 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1776 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1777 
//// details.                                                     ////
1778 
////                                                              ////
1779 
//// You should have received a copy of the GNU Lesser General    ////
1780 
//// Public License along with this source; if not, download it   ////
1781 
//// from http://www.opencores.org/lgpl.shtml                     ////
1782 
////                                                              ////
1783 
//////////////////////////////////////////////////////////////////////
1784 
 
1785 
// binary counter
1786 29 unneback 
 
1787 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1788 
module `BASE`MODULE (
1789 
`undef MODULE
1790 
 clear, cke, q, level1, level2, rst, clk);
1791 
 
1792 29 unneback 
   parameter length = 4;
1793 
   input clear;
1794 
   input cke;
1795 
   output [length:1] q;
1796 
   output reg level1;
1797 
   output reg level2;
1798 
   input rst;
1799 
   input clk;
1800 
 
1801 
   parameter clear_value = 0;
1802 
   parameter set_value = 1;
1803 30 unneback 
   parameter wrap_value = 15;
1804 
   parameter level1_value = 8;
1805 
   parameter level2_value = 15;
1806 29 unneback 
 
1807 
   wire rew;
1808 30 unneback 
   assign rew = 1'b0;
1809 29 unneback 
   reg  [length:1] qi;
1810 
   wire [length:1] q_next;
1811 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1812 
 
1813 
   always @ (posedge clk or posedge rst)
1814 
     if (rst)
1815 
       qi <= {length{1'b0}};
1816 
     else
1817 
     if (cke)
1818 
       qi <= q_next;
1819 
 
1820 
   assign q = qi;
1821 
 
1822 
 
1823 
    always @ (posedge clk or posedge rst)
1824 
    if (rst)
1825 
        level1 <= 1'b0;
1826 
    else
1827 
    if (cke)
1828 
    if (clear)
1829 
        level1 <= 1'b0;
1830 
    else if (q_next == level1_value)
1831 
        level1 <= 1'b1;
1832 
    else if (qi == level1_value & rew)
1833 
        level1 <= 1'b0;
1834 
 
1835 
    always @ (posedge clk or posedge rst)
1836 
    if (rst)
1837 
        level2 <= 1'b0;
1838 
    else
1839 
    if (cke)
1840 
    if (clear)
1841 
        level2 <= 1'b0;
1842 
    else if (q_next == level2_value)
1843 
        level2 <= 1'b1;
1844 
    else if (qi == level2_value & rew)
1845 
        level2 <= 1'b0;
1846 
endmodule
1847 40 unneback 
`endif
1848 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1849 29 unneback 
//////////////////////////////////////////////////////////////////////
1850 
////                                                              ////
1851 
////  Versatile counter                                           ////
1852 
////                                                              ////
1853 
////  Description                                                 ////
1854 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1855 
////  counter                                                     ////
1856 
////                                                              ////
1857 
////  To Do:                                                      ////
1858 
////   - add LFSR with more taps                                  ////
1859 
////                                                              ////
1860 
////  Author(s):                                                  ////
1861 
////      - Michael Unneback, unneback@opencores.org              ////
1862 
////        ORSoC AB                                              ////
1863 
////                                                              ////
1864 
//////////////////////////////////////////////////////////////////////
1865 
////                                                              ////
1866 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1867 
////                                                              ////
1868 
//// This source file may be used and distributed without         ////
1869 
//// restriction provided that this copyright statement is not    ////
1870 
//// removed from the file and that any derivative work contains  ////
1871 
//// the original copyright notice and the associated disclaimer. ////
1872 
////                                                              ////
1873 
//// This source file is free software; you can redistribute it   ////
1874 
//// and/or modify it under the terms of the GNU Lesser General   ////
1875 
//// Public License as published by the Free Software Foundation; ////
1876 
//// either version 2.1 of the License, or (at your option) any   ////
1877 
//// later version.                                               ////
1878 
////                                                              ////
1879 
//// This source is distributed in the hope that it will be       ////
1880 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1881 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1882 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1883 
//// details.                                                     ////
1884 
////                                                              ////
1885 
//// You should have received a copy of the GNU Lesser General    ////
1886 
//// Public License along with this source; if not, download it   ////
1887 
//// from http://www.opencores.org/lgpl.shtml                     ////
1888 
////                                                              ////
1889 
//////////////////////////////////////////////////////////////////////
1890 
 
1891 
// binary counter
1892 6 unneback 
 
1893 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
1894 
module `BASE`MODULE (
1895 
`undef MODULE
1896 
 clear, set, cke, rew, q, rst, clk);
1897 
 
1898 6 unneback 
   parameter length = 4;
1899 
   input clear;
1900 
   input set;
1901 
   input cke;
1902 
   input rew;
1903 
   output [length:1] q;
1904 
   input rst;
1905 
   input clk;
1906 
 
1907 
   parameter clear_value = 0;
1908 
   parameter set_value = 1;
1909 
   parameter wrap_value = 0;
1910 
   parameter level1_value = 15;
1911 
 
1912 
   reg  [length:1] qi;
1913 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1914 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1915 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1916 
   assign q_next = rew ? q_next_rew : q_next_fw;
1917 
 
1918 
   always @ (posedge clk or posedge rst)
1919 
     if (rst)
1920 
       qi <= {length{1'b0}};
1921 
     else
1922 
     if (cke)
1923 
       qi <= q_next;
1924 
 
1925 
   assign q = qi;
1926 
 
1927 
endmodule
1928 40 unneback 
`endif
1929 
`ifdef CNT_BIN_CE_REW_L1
1930 6 unneback 
//////////////////////////////////////////////////////////////////////
1931 
////                                                              ////
1932 
////  Versatile counter                                           ////
1933 
////                                                              ////
1934 
////  Description                                                 ////
1935 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1936 
////  counter                                                     ////
1937 
////                                                              ////
1938 
////  To Do:                                                      ////
1939 
////   - add LFSR with more taps                                  ////
1940 
////                                                              ////
1941 
////  Author(s):                                                  ////
1942 
////      - Michael Unneback, unneback@opencores.org              ////
1943 
////        ORSoC AB                                              ////
1944 
////                                                              ////
1945 
//////////////////////////////////////////////////////////////////////
1946 
////                                                              ////
1947 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1948 
////                                                              ////
1949 
//// This source file may be used and distributed without         ////
1950 
//// restriction provided that this copyright statement is not    ////
1951 
//// removed from the file and that any derivative work contains  ////
1952 
//// the original copyright notice and the associated disclaimer. ////
1953 
////                                                              ////
1954 
//// This source file is free software; you can redistribute it   ////
1955 
//// and/or modify it under the terms of the GNU Lesser General   ////
1956 
//// Public License as published by the Free Software Foundation; ////
1957 
//// either version 2.1 of the License, or (at your option) any   ////
1958 
//// later version.                                               ////
1959 
////                                                              ////
1960 
//// This source is distributed in the hope that it will be       ////
1961 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1962 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1963 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1964 
//// details.                                                     ////
1965 
////                                                              ////
1966 
//// You should have received a copy of the GNU Lesser General    ////
1967 
//// Public License along with this source; if not, download it   ////
1968 
//// from http://www.opencores.org/lgpl.shtml                     ////
1969 
////                                                              ////
1970 
//////////////////////////////////////////////////////////////////////
1971 
 
1972 
// binary counter
1973 
 
1974 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
1975 
module `BASE`MODULE (
1976 
`undef MODULE
1977 
 cke, rew, level1, rst, clk);
1978 
 
1979 6 unneback 
   parameter length = 4;
1980 
   input cke;
1981 
   input rew;
1982 
   output reg level1;
1983 
   input rst;
1984 
   input clk;
1985 
 
1986 
   parameter clear_value = 0;
1987 
   parameter set_value = 1;
1988 
   parameter wrap_value = 1;
1989 
   parameter level1_value = 15;
1990 
 
1991 29 unneback 
   wire clear;
1992 30 unneback 
   assign clear = 1'b0;
1993 6 unneback 
   reg  [length:1] qi;
1994 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1995 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1996 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1997 
   assign q_next = rew ? q_next_rew : q_next_fw;
1998 
 
1999 
   always @ (posedge clk or posedge rst)
2000 
     if (rst)
2001 
       qi <= {length{1'b0}};
2002 
     else
2003 
     if (cke)
2004 
       qi <= q_next;
2005 
 
2006 
 
2007 
 
2008 
    always @ (posedge clk or posedge rst)
2009 
    if (rst)
2010 
        level1 <= 1'b0;
2011 
    else
2012 
    if (cke)
2013 29 unneback 
    if (clear)
2014 
        level1 <= 1'b0;
2015 
    else if (q_next == level1_value)
2016 6 unneback 
        level1 <= 1'b1;
2017 
    else if (qi == level1_value & rew)
2018 
        level1 <= 1'b0;
2019 
endmodule
2020 40 unneback 
`endif
2021 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2022 6 unneback 
//////////////////////////////////////////////////////////////////////
2023 
////                                                              ////
2024 
////  Versatile counter                                           ////
2025 
////                                                              ////
2026 
////  Description                                                 ////
2027 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2028 
////  counter                                                     ////
2029 
////                                                              ////
2030 
////  To Do:                                                      ////
2031 
////   - add LFSR with more taps                                  ////
2032 
////                                                              ////
2033 
////  Author(s):                                                  ////
2034 
////      - Michael Unneback, unneback@opencores.org              ////
2035 
////        ORSoC AB                                              ////
2036 
////                                                              ////
2037 
//////////////////////////////////////////////////////////////////////
2038 
////                                                              ////
2039 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2040 
////                                                              ////
2041 
//// This source file may be used and distributed without         ////
2042 
//// restriction provided that this copyright statement is not    ////
2043 
//// removed from the file and that any derivative work contains  ////
2044 
//// the original copyright notice and the associated disclaimer. ////
2045 
////                                                              ////
2046 
//// This source file is free software; you can redistribute it   ////
2047 
//// and/or modify it under the terms of the GNU Lesser General   ////
2048 
//// Public License as published by the Free Software Foundation; ////
2049 
//// either version 2.1 of the License, or (at your option) any   ////
2050 
//// later version.                                               ////
2051 
////                                                              ////
2052 
//// This source is distributed in the hope that it will be       ////
2053 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2054 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2055 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2056 
//// details.                                                     ////
2057 
////                                                              ////
2058 
//// You should have received a copy of the GNU Lesser General    ////
2059 
//// Public License along with this source; if not, download it   ////
2060 
//// from http://www.opencores.org/lgpl.shtml                     ////
2061 
////                                                              ////
2062 
//////////////////////////////////////////////////////////////////////
2063 
 
2064 25 unneback 
// binary counter
2065 
 
2066 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2067 
module `BASE`MODULE (
2068 
`undef MODULE
2069 
 cke, rew, zq, level1, rst, clk);
2070 
 
2071 25 unneback 
   parameter length = 4;
2072 
   input cke;
2073 
   input rew;
2074 
   output reg zq;
2075 
   output reg level1;
2076 
   input rst;
2077 
   input clk;
2078 
 
2079 
   parameter clear_value = 0;
2080 
   parameter set_value = 1;
2081 
   parameter wrap_value = 1;
2082 
   parameter level1_value = 15;
2083 
 
2084 29 unneback 
   wire clear;
2085 30 unneback 
   assign clear = 1'b0;
2086 25 unneback 
   reg  [length:1] qi;
2087 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2088 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2089 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2090 
   assign q_next = rew ? q_next_rew : q_next_fw;
2091 
 
2092 
   always @ (posedge clk or posedge rst)
2093 
     if (rst)
2094 
       qi <= {length{1'b0}};
2095 
     else
2096 
     if (cke)
2097 
       qi <= q_next;
2098 
 
2099 
 
2100 
 
2101 
   always @ (posedge clk or posedge rst)
2102 
     if (rst)
2103 
       zq <= 1'b1;
2104 
     else
2105 
     if (cke)
2106 
       zq <= q_next == {length{1'b0}};
2107 
 
2108 
    always @ (posedge clk or posedge rst)
2109 
    if (rst)
2110 
        level1 <= 1'b0;
2111 
    else
2112 
    if (cke)
2113 29 unneback 
    if (clear)
2114 
        level1 <= 1'b0;
2115 
    else if (q_next == level1_value)
2116 25 unneback 
        level1 <= 1'b1;
2117 
    else if (qi == level1_value & rew)
2118 
        level1 <= 1'b0;
2119 
endmodule
2120 40 unneback 
`endif
2121 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2122 25 unneback 
//////////////////////////////////////////////////////////////////////
2123 
////                                                              ////
2124 
////  Versatile counter                                           ////
2125 
////                                                              ////
2126 
////  Description                                                 ////
2127 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2128 
////  counter                                                     ////
2129 
////                                                              ////
2130 
////  To Do:                                                      ////
2131 
////   - add LFSR with more taps                                  ////
2132 
////                                                              ////
2133 
////  Author(s):                                                  ////
2134 
////      - Michael Unneback, unneback@opencores.org              ////
2135 
////        ORSoC AB                                              ////
2136 
////                                                              ////
2137 
//////////////////////////////////////////////////////////////////////
2138 
////                                                              ////
2139 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2140 
////                                                              ////
2141 
//// This source file may be used and distributed without         ////
2142 
//// restriction provided that this copyright statement is not    ////
2143 
//// removed from the file and that any derivative work contains  ////
2144 
//// the original copyright notice and the associated disclaimer. ////
2145 
////                                                              ////
2146 
//// This source file is free software; you can redistribute it   ////
2147 
//// and/or modify it under the terms of the GNU Lesser General   ////
2148 
//// Public License as published by the Free Software Foundation; ////
2149 
//// either version 2.1 of the License, or (at your option) any   ////
2150 
//// later version.                                               ////
2151 
////                                                              ////
2152 
//// This source is distributed in the hope that it will be       ////
2153 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2154 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2155 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2156 
//// details.                                                     ////
2157 
////                                                              ////
2158 
//// You should have received a copy of the GNU Lesser General    ////
2159 
//// Public License along with this source; if not, download it   ////
2160 
//// from http://www.opencores.org/lgpl.shtml                     ////
2161 
////                                                              ////
2162 
//////////////////////////////////////////////////////////////////////
2163 
 
2164 
// binary counter
2165 
 
2166 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2167 
module `BASE`MODULE (
2168 
`undef MODULE
2169 
 cke, rew, q, zq, level1, rst, clk);
2170 
 
2171 25 unneback 
   parameter length = 4;
2172 
   input cke;
2173 
   input rew;
2174 
   output [length:1] q;
2175 
   output reg zq;
2176 
   output reg level1;
2177 
   input rst;
2178 
   input clk;
2179 
 
2180 
   parameter clear_value = 0;
2181 
   parameter set_value = 1;
2182 
   parameter wrap_value = 1;
2183 
   parameter level1_value = 15;
2184 
 
2185 29 unneback 
   wire clear;
2186 30 unneback 
   assign clear = 1'b0;
2187 25 unneback 
   reg  [length:1] qi;
2188 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2189 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2190 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2191 
   assign q_next = rew ? q_next_rew : q_next_fw;
2192 
 
2193 
   always @ (posedge clk or posedge rst)
2194 
     if (rst)
2195 
       qi <= {length{1'b0}};
2196 
     else
2197 
     if (cke)
2198 
       qi <= q_next;
2199 
 
2200 
   assign q = qi;
2201 
 
2202 
 
2203 
   always @ (posedge clk or posedge rst)
2204 
     if (rst)
2205 
       zq <= 1'b1;
2206 
     else
2207 
     if (cke)
2208 
       zq <= q_next == {length{1'b0}};
2209 
 
2210 
    always @ (posedge clk or posedge rst)
2211 
    if (rst)
2212 
        level1 <= 1'b0;
2213 
    else
2214 
    if (cke)
2215 29 unneback 
    if (clear)
2216 
        level1 <= 1'b0;
2217 
    else if (q_next == level1_value)
2218 25 unneback 
        level1 <= 1'b1;
2219 
    else if (qi == level1_value & rew)
2220 
        level1 <= 1'b0;
2221 
endmodule
2222 40 unneback 
`endif
2223 
`ifdef CNT_LFSR_ZQ
2224 25 unneback 
//////////////////////////////////////////////////////////////////////
2225 
////                                                              ////
2226 
////  Versatile counter                                           ////
2227 
////                                                              ////
2228 
////  Description                                                 ////
2229 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2230 
////  counter                                                     ////
2231 
////                                                              ////
2232 
////  To Do:                                                      ////
2233 
////   - add LFSR with more taps                                  ////
2234 
////                                                              ////
2235 
////  Author(s):                                                  ////
2236 
////      - Michael Unneback, unneback@opencores.org              ////
2237 
////        ORSoC AB                                              ////
2238 
////                                                              ////
2239 
//////////////////////////////////////////////////////////////////////
2240 
////                                                              ////
2241 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2242 
////                                                              ////
2243 
//// This source file may be used and distributed without         ////
2244 
//// restriction provided that this copyright statement is not    ////
2245 
//// removed from the file and that any derivative work contains  ////
2246 
//// the original copyright notice and the associated disclaimer. ////
2247 
////                                                              ////
2248 
//// This source file is free software; you can redistribute it   ////
2249 
//// and/or modify it under the terms of the GNU Lesser General   ////
2250 
//// Public License as published by the Free Software Foundation; ////
2251 
//// either version 2.1 of the License, or (at your option) any   ////
2252 
//// later version.                                               ////
2253 
////                                                              ////
2254 
//// This source is distributed in the hope that it will be       ////
2255 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2256 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2257 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2258 
//// details.                                                     ////
2259 
////                                                              ////
2260 
//// You should have received a copy of the GNU Lesser General    ////
2261 
//// Public License along with this source; if not, download it   ////
2262 
//// from http://www.opencores.org/lgpl.shtml                     ////
2263 
////                                                              ////
2264 
//////////////////////////////////////////////////////////////////////
2265 
 
2266 6 unneback 
// LFSR counter
2267 
 
2268 40 unneback 
`define MODULE cnt_lfsr_zq
2269 
module `BASE`MODULE (
2270 
`undef MODULE
2271 
 zq, rst, clk);
2272 
 
2273 6 unneback 
   parameter length = 4;
2274 
   output reg zq;
2275 
   input rst;
2276 
   input clk;
2277 
 
2278 
   parameter clear_value = 0;
2279 
   parameter set_value = 1;
2280 
   parameter wrap_value = 8;
2281 
   parameter level1_value = 15;
2282 
 
2283 
   reg  [length:1] qi;
2284 
   reg lfsr_fb;
2285 
   wire [length:1] q_next;
2286 
   reg [32:1] polynom;
2287 
   integer i;
2288 
 
2289 
   always @ (qi)
2290 
   begin
2291 
        case (length)
2292 
         2: polynom = 32'b11;                               // 0x3
2293 
         3: polynom = 32'b110;                              // 0x6
2294 
         4: polynom = 32'b1100;                             // 0xC
2295 
         5: polynom = 32'b10100;                            // 0x14
2296 
         6: polynom = 32'b110000;                           // 0x30
2297 
         7: polynom = 32'b1100000;                          // 0x60
2298 
         8: polynom = 32'b10111000;                         // 0xb8
2299 
         9: polynom = 32'b100010000;                        // 0x110
2300 
        10: polynom = 32'b1001000000;                       // 0x240
2301 
        11: polynom = 32'b10100000000;                      // 0x500
2302 
        12: polynom = 32'b100000101001;                     // 0x829
2303 
        13: polynom = 32'b1000000001100;                    // 0x100C
2304 
        14: polynom = 32'b10000000010101;                   // 0x2015
2305 
        15: polynom = 32'b110000000000000;                  // 0x6000
2306 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2307 
        17: polynom = 32'b10010000000000000;                // 0x12000
2308 
        18: polynom = 32'b100000010000000000;               // 0x20400
2309 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2310 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2311 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2312 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2313 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2314 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2315 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2316 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2317 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2318 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2319 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2320 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2321 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2322 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2323 
        default: polynom = 32'b0;
2324 
        endcase
2325 
        lfsr_fb = qi[length];
2326 
        for (i=length-1; i>=1; i=i-1) begin
2327 
            if (polynom[i])
2328 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2329 
        end
2330 
    end
2331 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2332 
 
2333 
   always @ (posedge clk or posedge rst)
2334 
     if (rst)
2335 
       qi <= {length{1'b0}};
2336 
     else
2337 
       qi <= q_next;
2338 
 
2339 
 
2340 
 
2341 
   always @ (posedge clk or posedge rst)
2342 
     if (rst)
2343 
       zq <= 1'b1;
2344 
     else
2345 
       zq <= q_next == {length{1'b0}};
2346 
endmodule
2347 40 unneback 
`endif
2348 
`ifdef CNT_LFSR_CE_ZQ
2349 6 unneback 
//////////////////////////////////////////////////////////////////////
2350 
////                                                              ////
2351 
////  Versatile counter                                           ////
2352 
////                                                              ////
2353 
////  Description                                                 ////
2354 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2355 
////  counter                                                     ////
2356 
////                                                              ////
2357 
////  To Do:                                                      ////
2358 
////   - add LFSR with more taps                                  ////
2359 
////                                                              ////
2360 
////  Author(s):                                                  ////
2361 
////      - Michael Unneback, unneback@opencores.org              ////
2362 
////        ORSoC AB                                              ////
2363 
////                                                              ////
2364 
//////////////////////////////////////////////////////////////////////
2365 
////                                                              ////
2366 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2367 
////                                                              ////
2368 
//// This source file may be used and distributed without         ////
2369 
//// restriction provided that this copyright statement is not    ////
2370 
//// removed from the file and that any derivative work contains  ////
2371 
//// the original copyright notice and the associated disclaimer. ////
2372 
////                                                              ////
2373 
//// This source file is free software; you can redistribute it   ////
2374 
//// and/or modify it under the terms of the GNU Lesser General   ////
2375 
//// Public License as published by the Free Software Foundation; ////
2376 
//// either version 2.1 of the License, or (at your option) any   ////
2377 
//// later version.                                               ////
2378 
////                                                              ////
2379 
//// This source is distributed in the hope that it will be       ////
2380 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2381 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2382 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2383 
//// details.                                                     ////
2384 
////                                                              ////
2385 
//// You should have received a copy of the GNU Lesser General    ////
2386 
//// Public License along with this source; if not, download it   ////
2387 
//// from http://www.opencores.org/lgpl.shtml                     ////
2388 
////                                                              ////
2389 
//////////////////////////////////////////////////////////////////////
2390 
 
2391 
// LFSR counter
2392 
 
2393 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2394 
module `BASE`MODULE (
2395 
`undef MODULE
2396 
 cke, zq, rst, clk);
2397 
 
2398 6 unneback 
   parameter length = 4;
2399 
   input cke;
2400 
   output reg zq;
2401 
   input rst;
2402 
   input clk;
2403 
 
2404 
   parameter clear_value = 0;
2405 
   parameter set_value = 1;
2406 
   parameter wrap_value = 8;
2407 
   parameter level1_value = 15;
2408 
 
2409 
   reg  [length:1] qi;
2410 
   reg lfsr_fb;
2411 
   wire [length:1] q_next;
2412 
   reg [32:1] polynom;
2413 
   integer i;
2414 
 
2415 
   always @ (qi)
2416 
   begin
2417 
        case (length)
2418 
         2: polynom = 32'b11;                               // 0x3
2419 
         3: polynom = 32'b110;                              // 0x6
2420 
         4: polynom = 32'b1100;                             // 0xC
2421 
         5: polynom = 32'b10100;                            // 0x14
2422 
         6: polynom = 32'b110000;                           // 0x30
2423 
         7: polynom = 32'b1100000;                          // 0x60
2424 
         8: polynom = 32'b10111000;                         // 0xb8
2425 
         9: polynom = 32'b100010000;                        // 0x110
2426 
        10: polynom = 32'b1001000000;                       // 0x240
2427 
        11: polynom = 32'b10100000000;                      // 0x500
2428 
        12: polynom = 32'b100000101001;                     // 0x829
2429 
        13: polynom = 32'b1000000001100;                    // 0x100C
2430 
        14: polynom = 32'b10000000010101;                   // 0x2015
2431 
        15: polynom = 32'b110000000000000;                  // 0x6000
2432 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2433 
        17: polynom = 32'b10010000000000000;                // 0x12000
2434 
        18: polynom = 32'b100000010000000000;               // 0x20400
2435 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2436 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2437 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2438 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2439 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2440 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2441 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2442 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2443 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2444 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2445 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2446 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2447 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2448 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2449 
        default: polynom = 32'b0;
2450 
        endcase
2451 
        lfsr_fb = qi[length];
2452 
        for (i=length-1; i>=1; i=i-1) begin
2453 
            if (polynom[i])
2454 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2455 
        end
2456 
    end
2457 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2458 
 
2459 
   always @ (posedge clk or posedge rst)
2460 
     if (rst)
2461 
       qi <= {length{1'b0}};
2462 
     else
2463 
     if (cke)
2464 
       qi <= q_next;
2465 
 
2466 
 
2467 
 
2468 
   always @ (posedge clk or posedge rst)
2469 
     if (rst)
2470 
       zq <= 1'b1;
2471 
     else
2472 
     if (cke)
2473 
       zq <= q_next == {length{1'b0}};
2474 
endmodule
2475 40 unneback 
`endif
2476 
`ifdef CNT_LFSR_CE_Q
2477 6 unneback 
//////////////////////////////////////////////////////////////////////
2478 
////                                                              ////
2479 
////  Versatile counter                                           ////
2480 
////                                                              ////
2481 
////  Description                                                 ////
2482 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2483 
////  counter                                                     ////
2484 
////                                                              ////
2485 
////  To Do:                                                      ////
2486 
////   - add LFSR with more taps                                  ////
2487 
////                                                              ////
2488 
////  Author(s):                                                  ////
2489 
////      - Michael Unneback, unneback@opencores.org              ////
2490 
////        ORSoC AB                                              ////
2491 
////                                                              ////
2492 
//////////////////////////////////////////////////////////////////////
2493 
////                                                              ////
2494 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2495 
////                                                              ////
2496 
//// This source file may be used and distributed without         ////
2497 
//// restriction provided that this copyright statement is not    ////
2498 
//// removed from the file and that any derivative work contains  ////
2499 
//// the original copyright notice and the associated disclaimer. ////
2500 
////                                                              ////
2501 
//// This source file is free software; you can redistribute it   ////
2502 
//// and/or modify it under the terms of the GNU Lesser General   ////
2503 
//// Public License as published by the Free Software Foundation; ////
2504 
//// either version 2.1 of the License, or (at your option) any   ////
2505 
//// later version.                                               ////
2506 
////                                                              ////
2507 
//// This source is distributed in the hope that it will be       ////
2508 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2509 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2510 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2511 
//// details.                                                     ////
2512 
////                                                              ////
2513 
//// You should have received a copy of the GNU Lesser General    ////
2514 
//// Public License along with this source; if not, download it   ////
2515 
//// from http://www.opencores.org/lgpl.shtml                     ////
2516 
////                                                              ////
2517 
//////////////////////////////////////////////////////////////////////
2518 22 unneback 
 
2519 
// LFSR counter
2520 27 unneback 
 
2521 40 unneback 
`define MODULE cnt_lfsr_ce_q
2522 
module `BASE`MODULE (
2523 
`undef MODULE
2524 
 cke, q, rst, clk);
2525 
 
2526 27 unneback 
   parameter length = 4;
2527 
   input cke;
2528 
   output [length:1] q;
2529 
   input rst;
2530 
   input clk;
2531 
 
2532 
   parameter clear_value = 0;
2533 
   parameter set_value = 1;
2534 
   parameter wrap_value = 8;
2535 
   parameter level1_value = 15;
2536 
 
2537 
   reg  [length:1] qi;
2538 
   reg lfsr_fb;
2539 
   wire [length:1] q_next;
2540 
   reg [32:1] polynom;
2541 
   integer i;
2542 
 
2543 
   always @ (qi)
2544 
   begin
2545 
        case (length)
2546 
         2: polynom = 32'b11;                               // 0x3
2547 
         3: polynom = 32'b110;                              // 0x6
2548 
         4: polynom = 32'b1100;                             // 0xC
2549 
         5: polynom = 32'b10100;                            // 0x14
2550 
         6: polynom = 32'b110000;                           // 0x30
2551 
         7: polynom = 32'b1100000;                          // 0x60
2552 
         8: polynom = 32'b10111000;                         // 0xb8
2553 
         9: polynom = 32'b100010000;                        // 0x110
2554 
        10: polynom = 32'b1001000000;                       // 0x240
2555 
        11: polynom = 32'b10100000000;                      // 0x500
2556 
        12: polynom = 32'b100000101001;                     // 0x829
2557 
        13: polynom = 32'b1000000001100;                    // 0x100C
2558 
        14: polynom = 32'b10000000010101;                   // 0x2015
2559 
        15: polynom = 32'b110000000000000;                  // 0x6000
2560 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2561 
        17: polynom = 32'b10010000000000000;                // 0x12000
2562 
        18: polynom = 32'b100000010000000000;               // 0x20400
2563 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2564 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2565 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2566 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2567 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2568 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2569 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2570 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2571 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2572 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2573 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2574 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2575 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2576 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2577 
        default: polynom = 32'b0;
2578 
        endcase
2579 
        lfsr_fb = qi[length];
2580 
        for (i=length-1; i>=1; i=i-1) begin
2581 
            if (polynom[i])
2582 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2583 
        end
2584 
    end
2585 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2586 
 
2587 
   always @ (posedge clk or posedge rst)
2588 
     if (rst)
2589 
       qi <= {length{1'b0}};
2590 
     else
2591 
     if (cke)
2592 
       qi <= q_next;
2593 
 
2594 
   assign q = qi;
2595 
 
2596 
endmodule
2597 40 unneback 
`endif
2598 
`ifdef CNT_LFSR_CE_CLEAR_Q
2599 27 unneback 
//////////////////////////////////////////////////////////////////////
2600 
////                                                              ////
2601 
////  Versatile counter                                           ////
2602 
////                                                              ////
2603 
////  Description                                                 ////
2604 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2605 
////  counter                                                     ////
2606 
////                                                              ////
2607 
////  To Do:                                                      ////
2608 
////   - add LFSR with more taps                                  ////
2609 
////                                                              ////
2610 
////  Author(s):                                                  ////
2611 
////      - Michael Unneback, unneback@opencores.org              ////
2612 
////        ORSoC AB                                              ////
2613 
////                                                              ////
2614 
//////////////////////////////////////////////////////////////////////
2615 
////                                                              ////
2616 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2617 
////                                                              ////
2618 
//// This source file may be used and distributed without         ////
2619 
//// restriction provided that this copyright statement is not    ////
2620 
//// removed from the file and that any derivative work contains  ////
2621 
//// the original copyright notice and the associated disclaimer. ////
2622 
////                                                              ////
2623 
//// This source file is free software; you can redistribute it   ////
2624 
//// and/or modify it under the terms of the GNU Lesser General   ////
2625 
//// Public License as published by the Free Software Foundation; ////
2626 
//// either version 2.1 of the License, or (at your option) any   ////
2627 
//// later version.                                               ////
2628 
////                                                              ////
2629 
//// This source is distributed in the hope that it will be       ////
2630 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2631 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2632 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2633 
//// details.                                                     ////
2634 
////                                                              ////
2635 
//// You should have received a copy of the GNU Lesser General    ////
2636 
//// Public License along with this source; if not, download it   ////
2637 
//// from http://www.opencores.org/lgpl.shtml                     ////
2638 
////                                                              ////
2639 
//////////////////////////////////////////////////////////////////////
2640 
 
2641 
// LFSR counter
2642 
 
2643 40 unneback 
`define MODULE cnt_lfsr_ce_clear_q
2644 
module `BASE`MODULE (
2645 
`undef MODULE
2646 
 clear, cke, q, rst, clk);
2647 
 
2648 27 unneback 
   parameter length = 4;
2649 
   input clear;
2650 
   input cke;
2651 
   output [length:1] q;
2652 
   input rst;
2653 
   input clk;
2654 
 
2655 
   parameter clear_value = 0;
2656 
   parameter set_value = 1;
2657 
   parameter wrap_value = 8;
2658 
   parameter level1_value = 15;
2659 
 
2660 
   reg  [length:1] qi;
2661 
   reg lfsr_fb;
2662 
   wire [length:1] q_next;
2663 
   reg [32:1] polynom;
2664 
   integer i;
2665 
 
2666 
   always @ (qi)
2667 
   begin
2668 
        case (length)
2669 
         2: polynom = 32'b11;                               // 0x3
2670 
         3: polynom = 32'b110;                              // 0x6
2671 
         4: polynom = 32'b1100;                             // 0xC
2672 
         5: polynom = 32'b10100;                            // 0x14
2673 
         6: polynom = 32'b110000;                           // 0x30
2674 
         7: polynom = 32'b1100000;                          // 0x60
2675 
         8: polynom = 32'b10111000;                         // 0xb8
2676 
         9: polynom = 32'b100010000;                        // 0x110
2677 
        10: polynom = 32'b1001000000;                       // 0x240
2678 
        11: polynom = 32'b10100000000;                      // 0x500
2679 
        12: polynom = 32'b100000101001;                     // 0x829
2680 
        13: polynom = 32'b1000000001100;                    // 0x100C
2681 
        14: polynom = 32'b10000000010101;                   // 0x2015
2682 
        15: polynom = 32'b110000000000000;                  // 0x6000
2683 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2684 
        17: polynom = 32'b10010000000000000;                // 0x12000
2685 
        18: polynom = 32'b100000010000000000;               // 0x20400
2686 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2687 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2688 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2689 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2690 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2691 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2692 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2693 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2694 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2695 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2696 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2697 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2698 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2699 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2700 
        default: polynom = 32'b0;
2701 
        endcase
2702 
        lfsr_fb = qi[length];
2703 
        for (i=length-1; i>=1; i=i-1) begin
2704 
            if (polynom[i])
2705 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2706 
        end
2707 
    end
2708 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2709 
 
2710 
   always @ (posedge clk or posedge rst)
2711 
     if (rst)
2712 
       qi <= {length{1'b0}};
2713 
     else
2714 
     if (cke)
2715 
       qi <= q_next;
2716 
 
2717 
   assign q = qi;
2718 
 
2719 
endmodule
2720 40 unneback 
`endif
2721 
`ifdef CNT_LFSR_CE_Q_ZQ
2722 27 unneback 
//////////////////////////////////////////////////////////////////////
2723 
////                                                              ////
2724 
////  Versatile counter                                           ////
2725 
////                                                              ////
2726 
////  Description                                                 ////
2727 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2728 
////  counter                                                     ////
2729 
////                                                              ////
2730 
////  To Do:                                                      ////
2731 
////   - add LFSR with more taps                                  ////
2732 
////                                                              ////
2733 
////  Author(s):                                                  ////
2734 
////      - Michael Unneback, unneback@opencores.org              ////
2735 
////        ORSoC AB                                              ////
2736 
////                                                              ////
2737 
//////////////////////////////////////////////////////////////////////
2738 
////                                                              ////
2739 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2740 
////                                                              ////
2741 
//// This source file may be used and distributed without         ////
2742 
//// restriction provided that this copyright statement is not    ////
2743 
//// removed from the file and that any derivative work contains  ////
2744 
//// the original copyright notice and the associated disclaimer. ////
2745 
////                                                              ////
2746 
//// This source file is free software; you can redistribute it   ////
2747 
//// and/or modify it under the terms of the GNU Lesser General   ////
2748 
//// Public License as published by the Free Software Foundation; ////
2749 
//// either version 2.1 of the License, or (at your option) any   ////
2750 
//// later version.                                               ////
2751 
////                                                              ////
2752 
//// This source is distributed in the hope that it will be       ////
2753 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2754 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2755 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2756 
//// details.                                                     ////
2757 
////                                                              ////
2758 
//// You should have received a copy of the GNU Lesser General    ////
2759 
//// Public License along with this source; if not, download it   ////
2760 
//// from http://www.opencores.org/lgpl.shtml                     ////
2761 
////                                                              ////
2762 
//////////////////////////////////////////////////////////////////////
2763 
 
2764 
// LFSR counter
2765 22 unneback 
 
2766 40 unneback 
`define MODULE cnt_lfsr_ce_q_zq
2767 
module `BASE`MODULE (
2768 
`undef MODULE
2769 
 cke, q, zq, rst, clk);
2770 
 
2771 22 unneback 
   parameter length = 4;
2772 
   input cke;
2773 
   output [length:1] q;
2774 
   output reg zq;
2775 
   input rst;
2776 
   input clk;
2777 
 
2778 
   parameter clear_value = 0;
2779 
   parameter set_value = 1;
2780 
   parameter wrap_value = 8;
2781 
   parameter level1_value = 15;
2782 
 
2783 
   reg  [length:1] qi;
2784 
   reg lfsr_fb;
2785 
   wire [length:1] q_next;
2786 
   reg [32:1] polynom;
2787 
   integer i;
2788 
 
2789 
   always @ (qi)
2790 
   begin
2791 
        case (length)
2792 
         2: polynom = 32'b11;                               // 0x3
2793 
         3: polynom = 32'b110;                              // 0x6
2794 
         4: polynom = 32'b1100;                             // 0xC
2795 
         5: polynom = 32'b10100;                            // 0x14
2796 
         6: polynom = 32'b110000;                           // 0x30
2797 
         7: polynom = 32'b1100000;                          // 0x60
2798 
         8: polynom = 32'b10111000;                         // 0xb8
2799 
         9: polynom = 32'b100010000;                        // 0x110
2800 
        10: polynom = 32'b1001000000;                       // 0x240
2801 
        11: polynom = 32'b10100000000;                      // 0x500
2802 
        12: polynom = 32'b100000101001;                     // 0x829
2803 
        13: polynom = 32'b1000000001100;                    // 0x100C
2804 
        14: polynom = 32'b10000000010101;                   // 0x2015
2805 
        15: polynom = 32'b110000000000000;                  // 0x6000
2806 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2807 
        17: polynom = 32'b10010000000000000;                // 0x12000
2808 
        18: polynom = 32'b100000010000000000;               // 0x20400
2809 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2810 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2811 22 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2812 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2813 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2814 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2815 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2816 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2817 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2818 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2819 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2820 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2821 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2822 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2823 
        default: polynom = 32'b0;
2824 
        endcase
2825 
        lfsr_fb = qi[length];
2826 
        for (i=length-1; i>=1; i=i-1) begin
2827 
            if (polynom[i])
2828 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2829 
        end
2830 
    end
2831 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2832 
 
2833 
   always @ (posedge clk or posedge rst)
2834 
     if (rst)
2835 
       qi <= {length{1'b0}};
2836 
     else
2837 
     if (cke)
2838 
       qi <= q_next;
2839 
 
2840 
   assign q = qi;
2841 
 
2842 
 
2843 
   always @ (posedge clk or posedge rst)
2844 
     if (rst)
2845 
       zq <= 1'b1;
2846 
     else
2847 
     if (cke)
2848 
       zq <= q_next == {length{1'b0}};
2849 
endmodule
2850 40 unneback 
`endif
2851 
`ifdef CNT_LFSR_CE_REW_L1
2852 22 unneback 
//////////////////////////////////////////////////////////////////////
2853 
////                                                              ////
2854 
////  Versatile counter                                           ////
2855 
////                                                              ////
2856 
////  Description                                                 ////
2857 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2858 
////  counter                                                     ////
2859 
////                                                              ////
2860 
////  To Do:                                                      ////
2861 
////   - add LFSR with more taps                                  ////
2862 
////                                                              ////
2863 
////  Author(s):                                                  ////
2864 
////      - Michael Unneback, unneback@opencores.org              ////
2865 
////        ORSoC AB                                              ////
2866 
////                                                              ////
2867 
//////////////////////////////////////////////////////////////////////
2868 
////                                                              ////
2869 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2870 
////                                                              ////
2871 
//// This source file may be used and distributed without         ////
2872 
//// restriction provided that this copyright statement is not    ////
2873 
//// removed from the file and that any derivative work contains  ////
2874 
//// the original copyright notice and the associated disclaimer. ////
2875 
////                                                              ////
2876 
//// This source file is free software; you can redistribute it   ////
2877 
//// and/or modify it under the terms of the GNU Lesser General   ////
2878 
//// Public License as published by the Free Software Foundation; ////
2879 
//// either version 2.1 of the License, or (at your option) any   ////
2880 
//// later version.                                               ////
2881 
////                                                              ////
2882 
//// This source is distributed in the hope that it will be       ////
2883 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2884 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2885 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2886 
//// details.                                                     ////
2887 
////                                                              ////
2888 
//// You should have received a copy of the GNU Lesser General    ////
2889 
//// Public License along with this source; if not, download it   ////
2890 
//// from http://www.opencores.org/lgpl.shtml                     ////
2891 
////                                                              ////
2892 
//////////////////////////////////////////////////////////////////////
2893 6 unneback 
 
2894 
// LFSR counter
2895 
 
2896 40 unneback 
`define MODULE cnt_lfsr_ce_rew_l1
2897 
module `BASE`MODULE (
2898 
`undef MODULE
2899 
 cke, rew, level1, rst, clk);
2900 
 
2901 6 unneback 
   parameter length = 4;
2902 
   input cke;
2903 
   input rew;
2904 
   output reg level1;
2905 
   input rst;
2906 
   input clk;
2907 
 
2908 
   parameter clear_value = 0;
2909 
   parameter set_value = 1;
2910 
   parameter wrap_value = 8;
2911 
   parameter level1_value = 15;
2912 
 
2913 29 unneback 
   wire clear;
2914 30 unneback 
   assign clear = 1'b0;
2915 6 unneback 
   reg  [length:1] qi;
2916 
   reg lfsr_fb, lfsr_fb_rew;
2917 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2918 
   reg [32:1] polynom_rew;
2919 
   integer j;
2920 
   reg [32:1] polynom;
2921 
   integer i;
2922 
 
2923 
   always @ (qi)
2924 
   begin
2925 
        case (length)
2926 
         2: polynom = 32'b11;                               // 0x3
2927 
         3: polynom = 32'b110;                              // 0x6
2928 
         4: polynom = 32'b1100;                             // 0xC
2929 
         5: polynom = 32'b10100;                            // 0x14
2930 
         6: polynom = 32'b110000;                           // 0x30
2931 
         7: polynom = 32'b1100000;                          // 0x60
2932 
         8: polynom = 32'b10111000;                         // 0xb8
2933 
         9: polynom = 32'b100010000;                        // 0x110
2934 
        10: polynom = 32'b1001000000;                       // 0x240
2935 
        11: polynom = 32'b10100000000;                      // 0x500
2936 
        12: polynom = 32'b100000101001;                     // 0x829
2937 
        13: polynom = 32'b1000000001100;                    // 0x100C
2938 
        14: polynom = 32'b10000000010101;                   // 0x2015
2939 
        15: polynom = 32'b110000000000000;                  // 0x6000
2940 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2941 
        17: polynom = 32'b10010000000000000;                // 0x12000
2942 
        18: polynom = 32'b100000010000000000;               // 0x20400
2943 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2944 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2945 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2946 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2947 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2948 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2949 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2950 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2951 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2952 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2953 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2954 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2955 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2956 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2957 
        default: polynom = 32'b0;
2958 
        endcase
2959 
        lfsr_fb = qi[length];
2960 
        for (i=length-1; i>=1; i=i-1) begin
2961 
            if (polynom[i])
2962 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2963 
        end
2964 
    end
2965 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2966 
   always @ (qi)
2967 
   begin
2968 
        case (length)
2969 
         2: polynom_rew = 32'b11;
2970 
         3: polynom_rew = 32'b110;
2971 
         4: polynom_rew = 32'b1100;
2972 
         5: polynom_rew = 32'b10100;
2973 
         6: polynom_rew = 32'b110000;
2974 
         7: polynom_rew = 32'b1100000;
2975 
         8: polynom_rew = 32'b10111000;
2976 
         9: polynom_rew = 32'b100010000;
2977 
        10: polynom_rew = 32'b1001000000;
2978 
        11: polynom_rew = 32'b10100000000;
2979 
        12: polynom_rew = 32'b100000101001;
2980 
        13: polynom_rew = 32'b1000000001100;
2981 
        14: polynom_rew = 32'b10000000010101;
2982 
        15: polynom_rew = 32'b110000000000000;
2983 
        16: polynom_rew = 32'b1101000000001000;
2984 
        17: polynom_rew = 32'b10010000000000000;
2985 
        18: polynom_rew = 32'b100000010000000000;
2986 
        19: polynom_rew = 32'b1000000000000100011;
2987 
        20: polynom_rew = 32'b10000010000000000000;
2988 
        21: polynom_rew = 32'b101000000000000000000;
2989 
        22: polynom_rew = 32'b1100000000000000000000;
2990 
        23: polynom_rew = 32'b10000100000000000000000;
2991 
        24: polynom_rew = 32'b111000010000000000000000;
2992 
        25: polynom_rew = 32'b1001000000000000000000000;
2993 
        26: polynom_rew = 32'b10000000000000000000100011;
2994 
        27: polynom_rew = 32'b100000000000000000000010011;
2995 
        28: polynom_rew = 32'b1100100000000000000000000000;
2996 
        29: polynom_rew = 32'b10100000000000000000000000000;
2997 
        30: polynom_rew = 32'b100000000000000000000000101001;
2998 
        31: polynom_rew = 32'b1001000000000000000000000000000;
2999 
        32: polynom_rew = 32'b10000000001000000000000000000011;
3000 
        default: polynom_rew = 32'b0;
3001 
        endcase
3002 
        // rotate left
3003 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3004 
        lfsr_fb_rew = qi[length];
3005 
        for (i=length-1; i>=1; i=i-1) begin
3006 
            if (polynom_rew[i])
3007 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3008 
        end
3009 
    end
3010 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3011 
   assign q_next = rew ? q_next_rew : q_next_fw;
3012 
 
3013 
   always @ (posedge clk or posedge rst)
3014 
     if (rst)
3015 
       qi <= {length{1'b0}};
3016 
     else
3017 
     if (cke)
3018 
       qi <= q_next;
3019 
 
3020 
 
3021 
 
3022 
    always @ (posedge clk or posedge rst)
3023 
    if (rst)
3024 
        level1 <= 1'b0;
3025 
    else
3026 
    if (cke)
3027 29 unneback 
    if (clear)
3028 
        level1 <= 1'b0;
3029 
    else if (q_next == level1_value)
3030 6 unneback 
        level1 <= 1'b1;
3031 
    else if (qi == level1_value & rew)
3032 
        level1 <= 1'b0;
3033 
endmodule
3034 40 unneback 
`endif
3035 
`ifdef CNT_GRAY
3036 6 unneback 
//////////////////////////////////////////////////////////////////////
3037 
////                                                              ////
3038 
////  Versatile counter                                           ////
3039 
////                                                              ////
3040 
////  Description                                                 ////
3041 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3042 
////  counter                                                     ////
3043 
////                                                              ////
3044 
////  To Do:                                                      ////
3045 
////   - add LFSR with more taps                                  ////
3046 
////                                                              ////
3047 
////  Author(s):                                                  ////
3048 
////      - Michael Unneback, unneback@opencores.org              ////
3049 
////        ORSoC AB                                              ////
3050 
////                                                              ////
3051 
//////////////////////////////////////////////////////////////////////
3052 
////                                                              ////
3053 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3054 
////                                                              ////
3055 
//// This source file may be used and distributed without         ////
3056 
//// restriction provided that this copyright statement is not    ////
3057 
//// removed from the file and that any derivative work contains  ////
3058 
//// the original copyright notice and the associated disclaimer. ////
3059 
////                                                              ////
3060 
//// This source file is free software; you can redistribute it   ////
3061 
//// and/or modify it under the terms of the GNU Lesser General   ////
3062 
//// Public License as published by the Free Software Foundation; ////
3063 
//// either version 2.1 of the License, or (at your option) any   ////
3064 
//// later version.                                               ////
3065 
////                                                              ////
3066 
//// This source is distributed in the hope that it will be       ////
3067 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3068 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3069 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3070 
//// details.                                                     ////
3071 
////                                                              ////
3072 
//// You should have received a copy of the GNU Lesser General    ////
3073 
//// Public License along with this source; if not, download it   ////
3074 
//// from http://www.opencores.org/lgpl.shtml                     ////
3075 
////                                                              ////
3076 
//////////////////////////////////////////////////////////////////////
3077 
 
3078 
// GRAY counter
3079 
 
3080 40 unneback 
`define MODULE cnt_gray
3081 
module `BASE`MODULE (
3082 
`undef MODULE
3083 
 q, rst, clk);
3084 
 
3085 6 unneback 
   parameter length = 4;
3086 
   output reg [length:1] q;
3087 
   input rst;
3088 
   input clk;
3089 
 
3090 
   parameter clear_value = 0;
3091 
   parameter set_value = 1;
3092 
   parameter wrap_value = 8;
3093 
   parameter level1_value = 15;
3094 
 
3095 
   reg  [length:1] qi;
3096 
   wire [length:1] q_next;
3097 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3098 
 
3099 
   always @ (posedge clk or posedge rst)
3100 
     if (rst)
3101 
       qi <= {length{1'b0}};
3102 
     else
3103 
       qi <= q_next;
3104 
 
3105 
   always @ (posedge clk or posedge rst)
3106 
     if (rst)
3107 
       q <= {length{1'b0}};
3108 
     else
3109 
         q <= (q_next>>1) ^ q_next;
3110 
 
3111 
endmodule
3112 40 unneback 
`endif
3113 
`ifdef CNT_GRAY_CE
3114 6 unneback 
//////////////////////////////////////////////////////////////////////
3115 
////                                                              ////
3116 
////  Versatile counter                                           ////
3117 
////                                                              ////
3118 
////  Description                                                 ////
3119 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3120 
////  counter                                                     ////
3121 
////                                                              ////
3122 
////  To Do:                                                      ////
3123 
////   - add LFSR with more taps                                  ////
3124 
////                                                              ////
3125 
////  Author(s):                                                  ////
3126 
////      - Michael Unneback, unneback@opencores.org              ////
3127 
////        ORSoC AB                                              ////
3128 
////                                                              ////
3129 
//////////////////////////////////////////////////////////////////////
3130 
////                                                              ////
3131 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3132 
////                                                              ////
3133 
//// This source file may be used and distributed without         ////
3134 
//// restriction provided that this copyright statement is not    ////
3135 
//// removed from the file and that any derivative work contains  ////
3136 
//// the original copyright notice and the associated disclaimer. ////
3137 
////                                                              ////
3138 
//// This source file is free software; you can redistribute it   ////
3139 
//// and/or modify it under the terms of the GNU Lesser General   ////
3140 
//// Public License as published by the Free Software Foundation; ////
3141 
//// either version 2.1 of the License, or (at your option) any   ////
3142 
//// later version.                                               ////
3143 
////                                                              ////
3144 
//// This source is distributed in the hope that it will be       ////
3145 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3146 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3147 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3148 
//// details.                                                     ////
3149 
////                                                              ////
3150 
//// You should have received a copy of the GNU Lesser General    ////
3151 
//// Public License along with this source; if not, download it   ////
3152 
//// from http://www.opencores.org/lgpl.shtml                     ////
3153 
////                                                              ////
3154 
//////////////////////////////////////////////////////////////////////
3155 
 
3156 
// GRAY counter
3157 
 
3158 40 unneback 
`define MODULE cnt_gray_ce
3159 
module `BASE`MODULE (
3160 
`undef MODULE
3161 
 cke, q, rst, clk);
3162 
 
3163 6 unneback 
   parameter length = 4;
3164 
   input cke;
3165 
   output reg [length:1] q;
3166 
   input rst;
3167 
   input clk;
3168 
 
3169 
   parameter clear_value = 0;
3170 
   parameter set_value = 1;
3171 
   parameter wrap_value = 8;
3172 
   parameter level1_value = 15;
3173 
 
3174 
   reg  [length:1] qi;
3175 
   wire [length:1] q_next;
3176 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3177 
 
3178 
   always @ (posedge clk or posedge rst)
3179 
     if (rst)
3180 
       qi <= {length{1'b0}};
3181 
     else
3182 
     if (cke)
3183 
       qi <= q_next;
3184 
 
3185 
   always @ (posedge clk or posedge rst)
3186 
     if (rst)
3187 
       q <= {length{1'b0}};
3188 
     else
3189 
       if (cke)
3190 
         q <= (q_next>>1) ^ q_next;
3191 
 
3192 
endmodule
3193 40 unneback 
`endif
3194 
`ifdef CNT_GRAY_CE_BIN
3195 6 unneback 
//////////////////////////////////////////////////////////////////////
3196 
////                                                              ////
3197 
////  Versatile counter                                           ////
3198 
////                                                              ////
3199 
////  Description                                                 ////
3200 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3201 
////  counter                                                     ////
3202 
////                                                              ////
3203 
////  To Do:                                                      ////
3204 
////   - add LFSR with more taps                                  ////
3205 
////                                                              ////
3206 
////  Author(s):                                                  ////
3207 
////      - Michael Unneback, unneback@opencores.org              ////
3208 
////        ORSoC AB                                              ////
3209 
////                                                              ////
3210 
//////////////////////////////////////////////////////////////////////
3211 
////                                                              ////
3212 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3213 
////                                                              ////
3214 
//// This source file may be used and distributed without         ////
3215 
//// restriction provided that this copyright statement is not    ////
3216 
//// removed from the file and that any derivative work contains  ////
3217 
//// the original copyright notice and the associated disclaimer. ////
3218 
////                                                              ////
3219 
//// This source file is free software; you can redistribute it   ////
3220 
//// and/or modify it under the terms of the GNU Lesser General   ////
3221 
//// Public License as published by the Free Software Foundation; ////
3222 
//// either version 2.1 of the License, or (at your option) any   ////
3223 
//// later version.                                               ////
3224 
////                                                              ////
3225 
//// This source is distributed in the hope that it will be       ////
3226 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3227 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3228 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3229 
//// details.                                                     ////
3230 
////                                                              ////
3231 
//// You should have received a copy of the GNU Lesser General    ////
3232 
//// Public License along with this source; if not, download it   ////
3233 
//// from http://www.opencores.org/lgpl.shtml                     ////
3234 
////                                                              ////
3235 
//////////////////////////////////////////////////////////////////////
3236 
 
3237 
// GRAY counter
3238 
 
3239 40 unneback 
`define MODULE cnt_gray_ce_bin
3240 
module `BASE`MODULE (
3241 
`undef MODULE
3242 
 cke, q, q_bin, rst, clk);
3243 
 
3244 6 unneback 
   parameter length = 4;
3245 
   input cke;
3246 
   output reg [length:1] q;
3247 
   output [length:1] q_bin;
3248 
   input rst;
3249 
   input clk;
3250 
 
3251 
   parameter clear_value = 0;
3252 
   parameter set_value = 1;
3253 
   parameter wrap_value = 8;
3254 
   parameter level1_value = 15;
3255 
 
3256 
   reg  [length:1] qi;
3257 
   wire [length:1] q_next;
3258 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3259 
 
3260 
   always @ (posedge clk or posedge rst)
3261 
     if (rst)
3262 
       qi <= {length{1'b0}};
3263 
     else
3264 
     if (cke)
3265 
       qi <= q_next;
3266 
 
3267 
   always @ (posedge clk or posedge rst)
3268 
     if (rst)
3269 
       q <= {length{1'b0}};
3270 
     else
3271 
       if (cke)
3272 
         q <= (q_next>>1) ^ q_next;
3273 
 
3274 
   assign q_bin = qi;
3275 
 
3276 
endmodule
3277 40 unneback 
`endif
3278 6 unneback 
//////////////////////////////////////////////////////////////////////
3279 
////                                                              ////
3280 
////  Versatile library, counters                                 ////
3281 
////                                                              ////
3282 
////  Description                                                 ////
3283 
////  counters                                                    ////
3284 
////                                                              ////
3285 
////                                                              ////
3286 
////  To Do:                                                      ////
3287 
////   - add more counters                                        ////
3288 
////                                                              ////
3289 
////  Author(s):                                                  ////
3290 
////      - Michael Unneback, unneback@opencores.org              ////
3291 
////        ORSoC AB                                              ////
3292 
////                                                              ////
3293 
//////////////////////////////////////////////////////////////////////
3294 
////                                                              ////
3295 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3296 
////                                                              ////
3297 
//// This source file may be used and distributed without         ////
3298 
//// restriction provided that this copyright statement is not    ////
3299 
//// removed from the file and that any derivative work contains  ////
3300 
//// the original copyright notice and the associated disclaimer. ////
3301 
////                                                              ////
3302 
//// This source file is free software; you can redistribute it   ////
3303 
//// and/or modify it under the terms of the GNU Lesser General   ////
3304 
//// Public License as published by the Free Software Foundation; ////
3305 
//// either version 2.1 of the License, or (at your option) any   ////
3306 
//// later version.                                               ////
3307 
////                                                              ////
3308 
//// This source is distributed in the hope that it will be       ////
3309 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3310 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3311 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3312 
//// details.                                                     ////
3313 
////                                                              ////
3314 
//// You should have received a copy of the GNU Lesser General    ////
3315 
//// Public License along with this source; if not, download it   ////
3316 
//// from http://www.opencores.org/lgpl.shtml                     ////
3317 
////                                                              ////
3318 
//////////////////////////////////////////////////////////////////////
3319 
 
3320 40 unneback 
`ifdef CNT_SHREG_WRAP
3321 
`define MODULE cnt_shreg_wrap
3322 
module `BASE`MODULE ( q, rst, clk);
3323 
`undef MODULE
3324 6 unneback 
 
3325 
   parameter length = 4;
3326 
   output reg [0:length-1] q;
3327 
   input rst;
3328 
   input clk;
3329 
 
3330 
    always @ (posedge clk or posedge rst)
3331 
    if (rst)
3332 
        q <= {1'b1,{length-1{1'b0}}};
3333 
    else
3334 
        q <= {q[length-1],q[0:length-2]};
3335 
 
3336 
endmodule
3337 40 unneback 
`endif
3338 6 unneback 
 
3339 40 unneback 
`ifdef CNT_SHREG_CE_WRAP
3340 
`define MODULE cnt_shreg_ce_wrap
3341 
module `BASE`MODULE ( cke, q, rst, clk);
3342 
`undef MODULE
3343 6 unneback 
 
3344 
   parameter length = 4;
3345 
   input cke;
3346 
   output reg [0:length-1] q;
3347 
   input rst;
3348 
   input clk;
3349 
 
3350 
    always @ (posedge clk or posedge rst)
3351 
    if (rst)
3352 
        q <= {1'b1,{length-1{1'b0}}};
3353 
    else
3354 
        if (cke)
3355 
            q <= {q[length-1],q[0:length-2]};
3356 
 
3357 
endmodule
3358 40 unneback 
`endif
3359 6 unneback 
 
3360 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR
3361 
`define MODULE cnt_shreg_ce_clear
3362 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3363 
`undef MODULE
3364 6 unneback 
 
3365 
   parameter length = 4;
3366 
   input cke, clear;
3367 
   output reg [0:length-1] q;
3368 
   input rst;
3369 
   input clk;
3370 
 
3371 
    always @ (posedge clk or posedge rst)
3372 
    if (rst)
3373 
        q <= {1'b1,{length-1{1'b0}}};
3374 
    else
3375 
        if (cke)
3376 
            if (clear)
3377 
                q <= {1'b1,{length-1{1'b0}}};
3378 
            else
3379 
                q <= q >> 1;
3380 
 
3381 
endmodule
3382 40 unneback 
`endif
3383 6 unneback 
 
3384 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3385 
`define MODULE cnt_shreg_ce_clear_wrap
3386 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3387 
`undef MODULE
3388 6 unneback 
 
3389 
   parameter length = 4;
3390 
   input cke, clear;
3391 
   output reg [0:length-1] q;
3392 
   input rst;
3393 
   input clk;
3394 
 
3395 
    always @ (posedge clk or posedge rst)
3396 
    if (rst)
3397 
        q <= {1'b1,{length-1{1'b0}}};
3398 
    else
3399 
        if (cke)
3400 
            if (clear)
3401 
                q <= {1'b1,{length-1{1'b0}}};
3402 
            else
3403 
            q <= {q[length-1],q[0:length-2]};
3404 
 
3405 
endmodule
3406 40 unneback 
`endif
3407 6 unneback 
//////////////////////////////////////////////////////////////////////
3408 
////                                                              ////
3409 
////  Versatile library, memories                                 ////
3410 
////                                                              ////
3411 
////  Description                                                 ////
3412 
////  memories                                                    ////
3413 
////                                                              ////
3414 
////                                                              ////
3415 
////  To Do:                                                      ////
3416 
////   - add more memory types                                    ////
3417 
////                                                              ////
3418 
////  Author(s):                                                  ////
3419 
////      - Michael Unneback, unneback@opencores.org              ////
3420 
////        ORSoC AB                                              ////
3421 
////                                                              ////
3422 
//////////////////////////////////////////////////////////////////////
3423 
////                                                              ////
3424 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3425 
////                                                              ////
3426 
//// This source file may be used and distributed without         ////
3427 
//// restriction provided that this copyright statement is not    ////
3428 
//// removed from the file and that any derivative work contains  ////
3429 
//// the original copyright notice and the associated disclaimer. ////
3430 
////                                                              ////
3431 
//// This source file is free software; you can redistribute it   ////
3432 
//// and/or modify it under the terms of the GNU Lesser General   ////
3433 
//// Public License as published by the Free Software Foundation; ////
3434 
//// either version 2.1 of the License, or (at your option) any   ////
3435 
//// later version.                                               ////
3436 
////                                                              ////
3437 
//// This source is distributed in the hope that it will be       ////
3438 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3439 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3440 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3441 
//// details.                                                     ////
3442 
////                                                              ////
3443 
//// You should have received a copy of the GNU Lesser General    ////
3444 
//// Public License along with this source; if not, download it   ////
3445 
//// from http://www.opencores.org/lgpl.shtml                     ////
3446 
////                                                              ////
3447 
//////////////////////////////////////////////////////////////////////
3448 
 
3449 40 unneback 
`ifdef ROM_INIT
3450 6 unneback 
/// ROM
3451 40 unneback 
`define MODULE rom_init
3452 
module `BASE`MODULE ( adr, q, clk);
3453 
`undef MODULE
3454 6 unneback 
 
3455 7 unneback 
   parameter data_width = 32;
3456 
   parameter addr_width = 8;
3457 
   input [(addr_width-1):0]       adr;
3458 
   output reg [(data_width-1):0] q;
3459 
   input                         clk;
3460 
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
3461 
   parameter memory_file = "vl_rom.vmem";
3462 
   initial
3463 
     begin
3464 
        $readmemh(memory_file, rom);
3465 
     end
3466 
 
3467 
   always @ (posedge clk)
3468 
     q <= rom[adr];
3469 6 unneback 
 
3470 7 unneback 
endmodule
3471 40 unneback 
`endif
3472 7 unneback 
 
3473 40 unneback 
`ifdef RAM
3474 
`define MODULE ram
3475 6 unneback 
// Single port RAM
3476 40 unneback 
module `BASE`MODULE ( d, adr, we, q, clk);
3477 
`undef MODULE
3478 6 unneback 
 
3479 
   parameter data_width = 32;
3480 
   parameter addr_width = 8;
3481 
   input [(data_width-1):0]      d;
3482 
   input [(addr_width-1):0]       adr;
3483 
   input                         we;
3484 7 unneback 
   output reg [(data_width-1):0] q;
3485 6 unneback 
   input                         clk;
3486 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3487 7 unneback 
   parameter init = 0;
3488 
   parameter memory_file = "vl_ram.vmem";
3489 
   generate if (init) begin : init_mem
3490 
   initial
3491 
     begin
3492 
        $readmemh(memory_file, ram);
3493 
     end
3494 
   end
3495 
   endgenerate
3496 
 
3497 6 unneback 
   always @ (posedge clk)
3498 
   begin
3499 
   if (we)
3500 
     ram[adr] <= d;
3501 
   q <= ram[adr];
3502 
   end
3503 
 
3504 
endmodule
3505 40 unneback 
`endif
3506 6 unneback 
 
3507 40 unneback 
`ifdef RAM_BE
3508 
`define MODULE ram_be
3509 
module `BASE`MODULE ( d, adr, be, we, q, clk);
3510 
`undef MODULE
3511 
 
3512 7 unneback 
   parameter data_width = 32;
3513 
   parameter addr_width = 8;
3514 
   input [(data_width-1):0]      d;
3515 
   input [(addr_width-1):0]       adr;
3516 
   input [(addr_width/4)-1:0]    be;
3517 
   input                         we;
3518 
   output reg [(data_width-1):0] q;
3519 
   input                         clk;
3520 
 
3521 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3522 
 
3523 
   parameter init = 0;
3524 
   parameter memory_file = "vl_ram.vmem";
3525 
   generate if (init) begin : init_mem
3526 
   initial
3527 
     begin
3528 
        $readmemh(memory_file, ram);
3529 
     end
3530 
   end
3531 
   endgenerate
3532 
 
3533 
   genvar i;
3534 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
3535 
      always @ (posedge clk)
3536 
      if (we & be[i])
3537 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3538 
   end
3539 
   endgenerate
3540 
 
3541 
   always @ (posedge clk)
3542 
      q <= ram[adr];
3543 
 
3544 
endmodule
3545 40 unneback 
`endif
3546 7 unneback 
 
3547 6 unneback 
`ifdef ACTEL
3548 48 unneback 
        // ACTEL FPGA should not use logic to handle rw collision
3549 6 unneback 
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
3550 
`else
3551 
        `define SYN
3552 
`endif
3553 
 
3554 40 unneback 
`ifdef DPRAM_1R1W
3555 
`define MODULE dpram_1r1w
3556 
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3557 
`undef MODULE
3558 6 unneback 
   parameter data_width = 32;
3559 
   parameter addr_width = 8;
3560 
   input [(data_width-1):0]      d_a;
3561 
   input [(addr_width-1):0]       adr_a;
3562 
   input [(addr_width-1):0]       adr_b;
3563 
   input                         we_a;
3564 
   output [(data_width-1):0]      q_b;
3565 
   input                         clk_a, clk_b;
3566 
   reg [(addr_width-1):0]         adr_b_reg;
3567 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3568 7 unneback 
 
3569 
   parameter init = 0;
3570 
   parameter memory_file = "vl_ram.vmem";
3571 
   generate if (init) begin : init_mem
3572 
   initial
3573 
     begin
3574 
        $readmemh(memory_file, ram);
3575 
     end
3576 
   end
3577 
   endgenerate
3578 
 
3579 6 unneback 
   always @ (posedge clk_a)
3580 
   if (we_a)
3581 
     ram[adr_a] <= d_a;
3582 
   always @ (posedge clk_b)
3583 
   adr_b_reg <= adr_b;
3584 
   assign q_b = ram[adr_b_reg];
3585 40 unneback 
 
3586 6 unneback 
endmodule
3587 40 unneback 
`endif
3588 6 unneback 
 
3589 40 unneback 
`ifdef DPRAM_2R1W
3590 
`define MODULE dpram_2r1w
3591 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3592 
`undef MODULE
3593 
 
3594 6 unneback 
   parameter data_width = 32;
3595 
   parameter addr_width = 8;
3596 
   input [(data_width-1):0]      d_a;
3597 
   input [(addr_width-1):0]       adr_a;
3598 
   input [(addr_width-1):0]       adr_b;
3599 
   input                         we_a;
3600 
   output [(data_width-1):0]      q_b;
3601 
   output reg [(data_width-1):0] q_a;
3602 
   input                         clk_a, clk_b;
3603 
   reg [(data_width-1):0]         q_b;
3604 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3605 7 unneback 
 
3606 
   parameter init = 0;
3607 
   parameter memory_file = "vl_ram.vmem";
3608 
   generate if (init) begin : init_mem
3609 
   initial
3610 
     begin
3611 
        $readmemh(memory_file, ram);
3612 
     end
3613 
   end
3614 
   endgenerate
3615 
 
3616 6 unneback 
   always @ (posedge clk_a)
3617 
     begin
3618 
        q_a <= ram[adr_a];
3619 
        if (we_a)
3620 
             ram[adr_a] <= d_a;
3621 
     end
3622 
   always @ (posedge clk_b)
3623 
          q_b <= ram[adr_b];
3624 
endmodule
3625 40 unneback 
`endif
3626 6 unneback 
 
3627 40 unneback 
`ifdef DPRAM_2R2W
3628 
`define MODULE dpram_2r2w
3629 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3630 
`undef MODULE
3631 
 
3632 6 unneback 
   parameter data_width = 32;
3633 
   parameter addr_width = 8;
3634 
   input [(data_width-1):0]      d_a;
3635 
   input [(addr_width-1):0]       adr_a;
3636 
   input [(addr_width-1):0]       adr_b;
3637 
   input                         we_a;
3638 
   output [(data_width-1):0]      q_b;
3639 
   input [(data_width-1):0]       d_b;
3640 
   output reg [(data_width-1):0] q_a;
3641 
   input                         we_b;
3642 
   input                         clk_a, clk_b;
3643 
   reg [(data_width-1):0]         q_b;
3644 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3645 7 unneback 
 
3646 
   parameter init = 0;
3647 
   parameter memory_file = "vl_ram.vmem";
3648 
   generate if (init) begin : init_mem
3649 
   initial
3650 
     begin
3651 
        $readmemh(memory_file, ram);
3652 
     end
3653 
   end
3654 
   endgenerate
3655 
 
3656 6 unneback 
   always @ (posedge clk_a)
3657 
     begin
3658 
        q_a <= ram[adr_a];
3659 
        if (we_a)
3660 
             ram[adr_a] <= d_a;
3661 
     end
3662 
   always @ (posedge clk_b)
3663 
     begin
3664 
        q_b <= ram[adr_b];
3665 
        if (we_b)
3666 
          ram[adr_b] <= d_b;
3667 
     end
3668 
endmodule
3669 40 unneback 
`endif
3670 6 unneback 
 
3671 
// Content addresable memory, CAM
3672 
 
3673 40 unneback 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
3674 6 unneback 
// FIFO
3675 40 unneback 
`define MODULE fifo_1r1w_fill_level_sync
3676 
module `BASE`MODULE (
3677 
`undef MODULE
3678 25 unneback 
    d, wr, fifo_full,
3679 
    q, rd, fifo_empty,
3680 
    fill_level,
3681 
    clk, rst
3682 
    );
3683 
 
3684 
parameter data_width = 18;
3685 
parameter addr_width = 4;
3686 6 unneback 
 
3687 25 unneback 
// write side
3688 
input  [data_width-1:0] d;
3689 
input                   wr;
3690 
output                  fifo_full;
3691 
// read side
3692 
output [data_width-1:0] q;
3693 
input                   rd;
3694 
output                  fifo_empty;
3695 
// common
3696 
output [addr_width:0]   fill_level;
3697 
input rst, clk;
3698 
 
3699 
wire [addr_width:1] wadr, radr;
3700 
 
3701 40 unneback 
`define MODULE cnt_bin_ce
3702 
`BASE`MODULE
3703 25 unneback 
    # ( .length(addr_width))
3704 
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
3705 40 unneback 
`BASE`MODULE
3706 25 unneback 
    # (.length(addr_width))
3707 
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
3708 40 unneback 
`undef MODULE
3709 25 unneback 
 
3710 40 unneback 
`define MODULE dpram_1r1w
3711 
`BASE`MODULE
3712 25 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
3713 
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
3714 40 unneback 
`undef MODULE
3715 25 unneback 
 
3716 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
3717 
`BASE`MODULE
3718 27 unneback 
    # (.length(addr_width+1), .level1_value(1<<addr_width))
3719 25 unneback 
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
3720 40 unneback 
`undef MODULE
3721 25 unneback 
endmodule
3722 40 unneback 
`endif
3723 25 unneback 
 
3724 40 unneback 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
3725 27 unneback 
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
3726 
// RAM is supposed to be larger than the two FIFOs
3727 
// LFSR counters used adr pointers
3728 40 unneback 
`define MODULE fifo_2r2w_sync_simplex
3729 
module `BASE`MODULE (
3730 
`undef MODULE
3731 27 unneback 
    // a side
3732 
    a_d, a_wr, a_fifo_full,
3733 
    a_q, a_rd, a_fifo_empty,
3734 
    a_fill_level,
3735 
    // b side
3736 
    b_d, b_wr, b_fifo_full,
3737 
    b_q, b_rd, b_fifo_empty,
3738 
    b_fill_level,
3739 
    // common
3740 
    clk, rst
3741 
    );
3742 
parameter data_width = 8;
3743 
parameter addr_width = 5;
3744 
parameter fifo_full_level = (1<<addr_width)-1;
3745 
 
3746 
// a side
3747 
input  [data_width-1:0] a_d;
3748 
input                   a_wr;
3749 
output                  a_fifo_full;
3750 
output [data_width-1:0] a_q;
3751 
input                   a_rd;
3752 
output                  a_fifo_empty;
3753 
output [addr_width-1:0] a_fill_level;
3754 
 
3755 
// b side
3756 
input  [data_width-1:0] b_d;
3757 
input                   b_wr;
3758 
output                  b_fifo_full;
3759 
output [data_width-1:0] b_q;
3760 
input                   b_rd;
3761 
output                  b_fifo_empty;
3762 
output [addr_width-1:0] b_fill_level;
3763 
 
3764 
input                   clk;
3765 
input                   rst;
3766 
 
3767 
// adr_gen
3768 
wire [addr_width:1] a_wadr, a_radr;
3769 
wire [addr_width:1] b_wadr, b_radr;
3770 
// dpram
3771 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3772 
 
3773 40 unneback 
`define MODULE cnt_lfsr_ce
3774 
`BASE`MODULE
3775 27 unneback 
    # ( .length(addr_width))
3776 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
3777 
 
3778 40 unneback 
`BASE`MODULE
3779 27 unneback 
    # (.length(addr_width))
3780 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
3781 
 
3782 40 unneback 
`BASE`MODULE
3783 27 unneback 
    # ( .length(addr_width))
3784 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
3785 
 
3786 40 unneback 
`BASE`MODULE
3787 27 unneback 
    # (.length(addr_width))
3788 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
3789 40 unneback 
`undef MODULE
3790 27 unneback 
 
3791 
// mux read or write adr to DPRAM
3792 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
3793 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
3794 
 
3795 40 unneback 
`define MODULE dpram_2r2w
3796 
`BASE`MODULE
3797 27 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
3798 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3799 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3800 40 unneback 
`undef MODULE
3801 
 
3802 
`define MODULE cnt_bin_ce_rew_zq_l1
3803 
`BASE`MODULE
3804 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
3805 27 unneback 
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
3806 
 
3807 40 unneback 
`BASE`MODULE
3808 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
3809 27 unneback 
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
3810 40 unneback 
`undef MODULE
3811 27 unneback 
 
3812 
endmodule
3813 40 unneback 
`endif
3814 27 unneback 
 
3815 40 unneback 
`ifdef FIFO_CMP_ASYNC
3816 
`define MODULE fifo_cmp_async
3817 
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
3818 
`undef MODULE
3819 6 unneback 
 
3820 11 unneback 
   parameter addr_width = 4;
3821 
   parameter N = addr_width-1;
3822 6 unneback 
 
3823 
   parameter Q1 = 2'b00;
3824 
   parameter Q2 = 2'b01;
3825 
   parameter Q3 = 2'b11;
3826 
   parameter Q4 = 2'b10;
3827 
 
3828 
   parameter going_empty = 1'b0;
3829 
   parameter going_full  = 1'b1;
3830 
 
3831 
   input [N:0]  wptr, rptr;
3832 14 unneback 
   output       fifo_empty;
3833 6 unneback 
   output       fifo_full;
3834 
   input        wclk, rclk, rst;
3835 
 
3836 
`ifndef GENERATE_DIRECTION_AS_LATCH
3837 
   wire direction;
3838 
`endif
3839 
`ifdef GENERATE_DIRECTION_AS_LATCH
3840 
   reg direction;
3841 
`endif
3842 
   reg  direction_set, direction_clr;
3843 
 
3844 
   wire async_empty, async_full;
3845 
   wire fifo_full2;
3846 14 unneback 
   wire fifo_empty2;
3847 6 unneback 
 
3848 
   // direction_set
3849 
   always @ (wptr[N:N-1] or rptr[N:N-1])
3850 
     case ({wptr[N:N-1],rptr[N:N-1]})
3851 
       {Q1,Q2} : direction_set <= 1'b1;
3852 
       {Q2,Q3} : direction_set <= 1'b1;
3853 
       {Q3,Q4} : direction_set <= 1'b1;
3854 
       {Q4,Q1} : direction_set <= 1'b1;
3855 
       default : direction_set <= 1'b0;
3856 
     endcase
3857 
 
3858 
   // direction_clear
3859 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
3860 
     if (rst)
3861 
       direction_clr <= 1'b1;
3862 
     else
3863 
       case ({wptr[N:N-1],rptr[N:N-1]})
3864 
         {Q2,Q1} : direction_clr <= 1'b1;
3865 
         {Q3,Q2} : direction_clr <= 1'b1;
3866 
         {Q4,Q3} : direction_clr <= 1'b1;
3867 
         {Q1,Q4} : direction_clr <= 1'b1;
3868 
         default : direction_clr <= 1'b0;
3869 
       endcase
3870 
 
3871 40 unneback 
`define MODULE dff_sr
3872 6 unneback 
`ifndef GENERATE_DIRECTION_AS_LATCH
3873 40 unneback 
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
3874 6 unneback 
`endif
3875 
 
3876 
`ifdef GENERATE_DIRECTION_AS_LATCH
3877 
   always @ (posedge direction_set or posedge direction_clr)
3878 
     if (direction_clr)
3879 
       direction <= going_empty;
3880 
     else
3881 
       direction <= going_full;
3882 
`endif
3883 
 
3884 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
3885 
   assign async_full  = (wptr == rptr) && (direction==going_full);
3886 
 
3887 40 unneback 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
3888 
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
3889 
`undef MODULE
3890 6 unneback 
 
3891 
/*
3892 
   always @ (posedge wclk or posedge rst or posedge async_full)
3893 
     if (rst)
3894 
       {fifo_full, fifo_full2} <= 2'b00;
3895 
     else if (async_full)
3896 
       {fifo_full, fifo_full2} <= 2'b11;
3897 
     else
3898 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
3899 
*/
3900 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
3901 6 unneback 
     if (async_empty)
3902 
       {fifo_empty, fifo_empty2} <= 2'b11;
3903 
     else
3904 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
3905 40 unneback 
`define MODULE dff
3906 
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
3907 
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
3908 
`undef MODULE
3909 27 unneback 
endmodule // async_compb
3910 40 unneback 
`endif
3911 6 unneback 
 
3912 40 unneback 
`ifdef FIFO_1R1W_ASYNC
3913 
`define MODULE fifo_1r1w_async
3914 
module `BASE`MODULE (
3915 
`undef MODULE
3916 6 unneback 
    d, wr, fifo_full, wr_clk, wr_rst,
3917 
    q, rd, fifo_empty, rd_clk, rd_rst
3918 
    );
3919 
 
3920 
parameter data_width = 18;
3921 
parameter addr_width = 4;
3922 
 
3923 
// write side
3924 
input  [data_width-1:0] d;
3925 
input                   wr;
3926 
output                  fifo_full;
3927 
input                   wr_clk;
3928 
input                   wr_rst;
3929 
// read side
3930 
output [data_width-1:0] q;
3931 
input                   rd;
3932 
output                  fifo_empty;
3933 
input                   rd_clk;
3934 
input                   rd_rst;
3935 
 
3936 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
3937 23 unneback 
 
3938 40 unneback 
`define MODULE cnt_gray_ce_bin
3939 
`BASE`MODULE
3940 6 unneback 
    # ( .length(addr_width))
3941 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
3942 
 
3943 40 unneback 
`BASE`MODULE
3944 6 unneback 
    # (.length(addr_width))
3945 23 unneback 
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
3946 40 unneback 
`undef MODULE
3947 6 unneback 
 
3948 40 unneback 
`define MODULE dpram_1r1w
3949 
`BASE`MODULE
3950 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
3951 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
3952 40 unneback 
`undef MODULE
3953 6 unneback 
 
3954 40 unneback 
`define MODULE fifo_cmp_async
3955 
`BASE`MODULE
3956 6 unneback 
    # (.addr_width(addr_width))
3957 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
3958 40 unneback 
`undef MODULE
3959 6 unneback 
 
3960 
endmodule
3961 40 unneback 
`endif
3962 6 unneback 
 
3963 40 unneback 
`ifdef FIFO_2R2W_ASYNC
3964 
`define MODULE fifo_2r2w_async
3965 
module `BASE`MODULE (
3966 
`undef MODULE
3967 6 unneback 
    // a side
3968 
    a_d, a_wr, a_fifo_full,
3969 
    a_q, a_rd, a_fifo_empty,
3970 
    a_clk, a_rst,
3971 
    // b side
3972 
    b_d, b_wr, b_fifo_full,
3973 
    b_q, b_rd, b_fifo_empty,
3974 
    b_clk, b_rst
3975 
    );
3976 
 
3977 
parameter data_width = 18;
3978 
parameter addr_width = 4;
3979 
 
3980 
// a side
3981 
input  [data_width-1:0] a_d;
3982 
input                   a_wr;
3983 
output                  a_fifo_full;
3984 
output [data_width-1:0] a_q;
3985 
input                   a_rd;
3986 
output                  a_fifo_empty;
3987 
input                   a_clk;
3988 
input                   a_rst;
3989 
 
3990 
// b side
3991 
input  [data_width-1:0] b_d;
3992 
input                   b_wr;
3993 
output                  b_fifo_full;
3994 
output [data_width-1:0] b_q;
3995 
input                   b_rd;
3996 
output                  b_fifo_empty;
3997 
input                   b_clk;
3998 
input                   b_rst;
3999 
 
4000 40 unneback 
`define MODULE fifo_1r1w_async
4001 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4002 6 unneback 
vl_fifo_1r1w_async_a (
4003 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4004 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4005 
    );
4006 
 
4007 40 unneback 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4008 6 unneback 
vl_fifo_1r1w_async_b (
4009 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4010 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4011 
    );
4012 40 unneback 
`undef MODULE
4013 
 
4014 6 unneback 
endmodule
4015 40 unneback 
`endif
4016 6 unneback 
 
4017 40 unneback 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4018 
`define MODULE fifo_2r2w_async_simplex
4019 
module `BASE`MODULE (
4020 
`undef MODULE
4021 6 unneback 
    // a side
4022 
    a_d, a_wr, a_fifo_full,
4023 
    a_q, a_rd, a_fifo_empty,
4024 
    a_clk, a_rst,
4025 
    // b side
4026 
    b_d, b_wr, b_fifo_full,
4027 
    b_q, b_rd, b_fifo_empty,
4028 
    b_clk, b_rst
4029 
    );
4030 
 
4031 
parameter data_width = 18;
4032 
parameter addr_width = 4;
4033 
 
4034 
// a side
4035 
input  [data_width-1:0] a_d;
4036 
input                   a_wr;
4037 
output                  a_fifo_full;
4038 
output [data_width-1:0] a_q;
4039 
input                   a_rd;
4040 
output                  a_fifo_empty;
4041 
input                   a_clk;
4042 
input                   a_rst;
4043 
 
4044 
// b side
4045 
input  [data_width-1:0] b_d;
4046 
input                   b_wr;
4047 
output                  b_fifo_full;
4048 
output [data_width-1:0] b_q;
4049 
input                   b_rd;
4050 
output                  b_fifo_empty;
4051 
input                   b_clk;
4052 
input                   b_rst;
4053 
 
4054 
// adr_gen
4055 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4056 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4057 
// dpram
4058 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4059 
 
4060 40 unneback 
`define MODULE cnt_gray_ce_bin
4061 
`BASE`MODULE
4062 6 unneback 
    # ( .length(addr_width))
4063 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4064 
 
4065 40 unneback 
`BASE`MODULE
4066 6 unneback 
    # (.length(addr_width))
4067 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4068 
 
4069 40 unneback 
`BASE`MODULE
4070 6 unneback 
    # ( .length(addr_width))
4071 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4072 
 
4073 40 unneback 
`BASE`MODULE
4074 6 unneback 
    # (.length(addr_width))
4075 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4076 40 unneback 
`undef MODULE
4077 6 unneback 
 
4078 
// mux read or write adr to DPRAM
4079 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4080 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4081 
 
4082 40 unneback 
`define MODULE dpram_2r2w
4083 
`BASE`MODULE
4084 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4085 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4086 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4087 40 unneback 
`undef MODULE
4088 6 unneback 
 
4089 40 unneback 
`define MODULE fifo_cmp_async
4090 
`BASE`MODULE
4091 6 unneback 
    # (.addr_width(addr_width))
4092 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4093 
 
4094 40 unneback 
`BASE`MODULE
4095 6 unneback 
    # (.addr_width(addr_width))
4096 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4097 40 unneback 
`undef MODULE
4098 6 unneback 
 
4099 
endmodule
4100 40 unneback 
`endif
4101 48 unneback 
 
4102 
`ifdef REG_FILE
4103 
`define MODULE reg_file
4104 
module `BASE`MODULE (
4105 
`undef MODULE
4106 
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4107 
);
4108 
parameter data_width = 32;
4109 
parameter addr_width = 5;
4110 
input [addr_width-1:0] a1, a2, a3;
4111 
input [data_width-1:0] wd3;
4112 
input we3;
4113 
output [data_width-1:0] rd1, rd2;
4114 
input clk;
4115 
 
4116 
`ifdef ACTEL
4117 
reg [data_width-1:0] wd3_reg;
4118 
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4119 
reg we3_reg;
4120 
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
4121 
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
4122 
always @ (posedge clk or posedge rst)
4123 
if (rst)
4124 
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4125 
else
4126 
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4127 
 
4128 
    always @ (negedge clk)
4129 
    if (we3_reg)
4130 
        ram1[a3_reg] <= wd3;
4131 
    always @ (posedge clk)
4132 
        a1_reg <= a1;
4133 
    assign rd1 = ram1[a1_reg];
4134 
 
4135 
    always @ (negedge clk)
4136 
    if (we3_reg)
4137 
        ram2[a3_reg] <= wd3;
4138 
    always @ (posedge clk)
4139 
        a2_reg <= a2;
4140 
    assign rd2 = ram2[a2_reg];
4141 
 
4142 
`else
4143 
 
4144 
`define MODULE dpram_1r1w
4145 
`BASE`MODULE
4146 
    # ( .data_width(data_width), .addr_width(addr_width))
4147 
    ram1 (
4148 
        .d_a(wd3),
4149 
        .adr_a(a3),
4150 
        .we_a(we3),
4151 
        .clk_a(clk),
4152 
        .q_b(rd1),
4153 
        .adr_b(a1),
4154 
        .clk_b(clk) );
4155 
 
4156 
`BASE`MODULE
4157 
    # ( .data_width(data_width), .addr_width(addr_width))
4158 
    ram2 (
4159 
        .d_a(wd3),
4160 
        .adr_a(a3),
4161 
        .we_a(we3),
4162 
        .clk_a(clk),
4163 
        .q_b(rd2),
4164 
        .adr_b(a2),
4165 
        .clk_b(clk) );
4166 
`undef MODULE
4167 
 
4168 
`endif
4169 
 
4170 
endmodule
4171 
`endif
4172 12 unneback 
//////////////////////////////////////////////////////////////////////
4173 
////                                                              ////
4174 
////  Versatile library, wishbone stuff                           ////
4175 
////                                                              ////
4176 
////  Description                                                 ////
4177 
////  Wishbone compliant modules                                  ////
4178 
////                                                              ////
4179 
////                                                              ////
4180 
////  To Do:                                                      ////
4181 
////   -                                                          ////
4182 
////                                                              ////
4183 
////  Author(s):                                                  ////
4184 
////      - Michael Unneback, unneback@opencores.org              ////
4185 
////        ORSoC AB                                              ////
4186 
////                                                              ////
4187 
//////////////////////////////////////////////////////////////////////
4188 
////                                                              ////
4189 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4190 
////                                                              ////
4191 
//// This source file may be used and distributed without         ////
4192 
//// restriction provided that this copyright statement is not    ////
4193 
//// removed from the file and that any derivative work contains  ////
4194 
//// the original copyright notice and the associated disclaimer. ////
4195 
////                                                              ////
4196 
//// This source file is free software; you can redistribute it   ////
4197 
//// and/or modify it under the terms of the GNU Lesser General   ////
4198 
//// Public License as published by the Free Software Foundation; ////
4199 
//// either version 2.1 of the License, or (at your option) any   ////
4200 
//// later version.                                               ////
4201 
////                                                              ////
4202 
//// This source is distributed in the hope that it will be       ////
4203 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4204 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4205 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4206 
//// details.                                                     ////
4207 
////                                                              ////
4208 
//// You should have received a copy of the GNU Lesser General    ////
4209 
//// Public License along with this source; if not, download it   ////
4210 
//// from http://www.opencores.org/lgpl.shtml                     ////
4211 
////                                                              ////
4212 
//////////////////////////////////////////////////////////////////////
4213 
 
4214 40 unneback 
`ifdef WB3WB3_BRIDGE
4215 12 unneback 
// async wb3 - wb3 bridge
4216 
`timescale 1ns/1ns
4217 40 unneback 
`define MODULE wb3wb3_bridge
4218 
module `BASE`MODULE (
4219 
`undef MODULE
4220 12 unneback 
        // wishbone slave side
4221 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4222 
        // wishbone master side
4223 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4224 
 
4225 
input [31:0] wbs_dat_i;
4226 
input [31:2] wbs_adr_i;
4227 
input [3:0]  wbs_sel_i;
4228 
input [1:0]  wbs_bte_i;
4229 
input [2:0]  wbs_cti_i;
4230 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4231 
output [31:0] wbs_dat_o;
4232 14 unneback 
output wbs_ack_o;
4233 12 unneback 
input wbs_clk, wbs_rst;
4234 
 
4235 
output [31:0] wbm_dat_o;
4236 
output reg [31:2] wbm_adr_o;
4237 
output [3:0]  wbm_sel_o;
4238 
output reg [1:0]  wbm_bte_o;
4239 
output reg [2:0]  wbm_cti_o;
4240 14 unneback 
output reg wbm_we_o;
4241 
output wbm_cyc_o;
4242 12 unneback 
output wbm_stb_o;
4243 
input [31:0]  wbm_dat_i;
4244 
input wbm_ack_i;
4245 
input wbm_clk, wbm_rst;
4246 
 
4247 
parameter addr_width = 4;
4248 
 
4249 
// bte
4250 
parameter linear       = 2'b00;
4251 
parameter wrap4        = 2'b01;
4252 
parameter wrap8        = 2'b10;
4253 
parameter wrap16       = 2'b11;
4254 
// cti
4255 
parameter classic      = 3'b000;
4256 
parameter incburst     = 3'b010;
4257 
parameter endofburst   = 3'b111;
4258 
 
4259 
parameter wbs_adr  = 1'b0;
4260 
parameter wbs_data = 1'b1;
4261 
 
4262 33 unneback 
parameter wbm_adr0      = 2'b00;
4263 
parameter wbm_adr1      = 2'b01;
4264 
parameter wbm_data      = 2'b10;
4265 
parameter wbm_data_wait = 2'b11;
4266 12 unneback 
 
4267 
reg [1:0] wbs_bte_reg;
4268 
reg wbs;
4269 
wire wbs_eoc_alert, wbm_eoc_alert;
4270 
reg wbs_eoc, wbm_eoc;
4271 
reg [1:0] wbm;
4272 
 
4273 14 unneback 
wire [1:16] wbs_count, wbm_count;
4274 12 unneback 
 
4275 
wire [35:0] a_d, a_q, b_d, b_q;
4276 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4277 
reg a_rd_reg;
4278 
wire b_rd_adr, b_rd_data;
4279 14 unneback 
wire b_rd_data_reg;
4280 
wire [35:0] temp;
4281 12 unneback 
 
4282 
`define WE 5
4283 
`define BTE 4:3
4284 
`define CTI 2:0
4285 
 
4286 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4287 
always @ (posedge wbs_clk or posedge wbs_rst)
4288 
if (wbs_rst)
4289 
        wbs_eoc <= 1'b0;
4290 
else
4291 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4292 
                wbs_eoc <= wbs_bte_i==linear;
4293 
        else if (wbs_eoc_alert & (a_rd | a_wr))
4294 
                wbs_eoc <= 1'b1;
4295 
 
4296 40 unneback 
`define MODULE cnt_shreg_ce_clear
4297 
`BASE`MODULE # ( .length(16))
4298 
`undef MODULE
4299 12 unneback 
    cnt0 (
4300 
        .cke(wbs_ack_o),
4301 
        .clear(wbs_eoc),
4302 
        .q(wbs_count),
4303 
        .rst(wbs_rst),
4304 
        .clk(wbs_clk));
4305 
 
4306 
always @ (posedge wbs_clk or posedge wbs_rst)
4307 
if (wbs_rst)
4308 
        wbs <= wbs_adr;
4309 
else
4310 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
4311 
                wbs <= wbs_data;
4312 
        else if (wbs_eoc & wbs_ack_o)
4313 
                wbs <= wbs_adr;
4314 
 
4315 
// wbs FIFO
4316 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
4317 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
4318 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4319 
              1'b0;
4320 
assign a_rd = !a_fifo_empty;
4321 
always @ (posedge wbs_clk or posedge wbs_rst)
4322 
if (wbs_rst)
4323 
        a_rd_reg <= 1'b0;
4324 
else
4325 
        a_rd_reg <= a_rd;
4326 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4327 
 
4328 
assign wbs_dat_o = a_q[35:4];
4329 
 
4330 
always @ (posedge wbs_clk or posedge wbs_rst)
4331 
if (wbs_rst)
4332 13 unneback 
        wbs_bte_reg <= 2'b00;
4333 12 unneback 
else
4334 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
4335 12 unneback 
 
4336 
// wbm FIFO
4337 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4338 
always @ (posedge wbm_clk or posedge wbm_rst)
4339 
if (wbm_rst)
4340 
        wbm_eoc <= 1'b0;
4341 
else
4342 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4343 
                wbm_eoc <= b_q[`BTE] == linear;
4344 
        else if (wbm_eoc_alert & wbm_ack_i)
4345 
                wbm_eoc <= 1'b1;
4346 
 
4347 
always @ (posedge wbm_clk or posedge wbm_rst)
4348 
if (wbm_rst)
4349 
        wbm <= wbm_adr0;
4350 
else
4351 33 unneback 
/*
4352 12 unneback 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
4353 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
4354 
        (wbm==wbm_adr1 & !wbm_we_o) |
4355 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
4356 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
4357 33 unneback 
*/
4358 
    case (wbm)
4359 
    wbm_adr0:
4360 
        if (!b_fifo_empty)
4361 
            wbm <= wbm_adr1;
4362 
    wbm_adr1:
4363 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
4364 
            wbm <= wbm_data;
4365 
    wbm_data:
4366 
        if (wbm_ack_i & wbm_eoc)
4367 
            wbm <= wbm_adr0;
4368 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
4369 
            wbm <= wbm_data_wait;
4370 
    wbm_data_wait:
4371 
        if (!b_fifo_empty)
4372 
            wbm <= wbm_data;
4373 
    endcase
4374 12 unneback 
 
4375 
assign b_d = {wbm_dat_i,4'b1111};
4376 
assign b_wr = !wbm_we_o & wbm_ack_i;
4377 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
4378 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
4379 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
4380 33 unneback 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
4381 12 unneback 
                   1'b0;
4382 
assign b_rd = b_rd_adr | b_rd_data;
4383 
 
4384 40 unneback 
`define MODULE dff
4385 
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
4386 
`undef MODULE
4387 
`define MODULE dff_ce
4388 
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
4389 
`undef MODULE
4390 12 unneback 
 
4391 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
4392 
 
4393 40 unneback 
`define MODULE cnt_shreg_ce_clear
4394 42 unneback 
`BASE`MODULE # ( .length(16))
4395 40 unneback 
`undef MODULE
4396 12 unneback 
    cnt1 (
4397 
        .cke(wbm_ack_i),
4398 
        .clear(wbm_eoc),
4399 
        .q(wbm_count),
4400 
        .rst(wbm_rst),
4401 
        .clk(wbm_clk));
4402 
 
4403 33 unneback 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
4404 
assign wbm_stb_o = (wbm==wbm_data);
4405 12 unneback 
 
4406 
always @ (posedge wbm_clk or posedge wbm_rst)
4407 
if (wbm_rst)
4408 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
4409 
else begin
4410 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4411 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
4412 
        else if (wbm_eoc_alert & wbm_ack_i)
4413 
                wbm_cti_o <= endofburst;
4414 
end
4415 
 
4416 
//async_fifo_dw_simplex_top
4417 40 unneback 
`define MODULE fifo_2r2w_async_simplex
4418 
`BASE`MODULE
4419 
`undef MODULE
4420 12 unneback 
# ( .data_width(36), .addr_width(addr_width))
4421 
fifo (
4422 
    // a side
4423 
    .a_d(a_d),
4424 
    .a_wr(a_wr),
4425 
    .a_fifo_full(a_fifo_full),
4426 
    .a_q(a_q),
4427 
    .a_rd(a_rd),
4428 
    .a_fifo_empty(a_fifo_empty),
4429 
    .a_clk(wbs_clk),
4430 
    .a_rst(wbs_rst),
4431 
    // b side
4432 
    .b_d(b_d),
4433 
    .b_wr(b_wr),
4434 
    .b_fifo_full(b_fifo_full),
4435 
    .b_q(b_q),
4436 
    .b_rd(b_rd),
4437 
    .b_fifo_empty(b_fifo_empty),
4438 
    .b_clk(wbm_clk),
4439 
    .b_rst(wbm_rst)
4440 
    );
4441 
 
4442 
endmodule
4443 40 unneback 
`undef WE
4444 
`undef BTE
4445 
`undef CTI
4446 
`endif
4447 17 unneback 
 
4448 40 unneback 
`ifdef WB3_ARBITER_TYPE1
4449 
`define MODULE wb3_arbiter_type1
4450 42 unneback 
module `BASE`MODULE (
4451 40 unneback 
`undef MODULE
4452 39 unneback 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
4453 
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
4454 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
4455 
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
4456 
    wb_clk, wb_rst
4457 
);
4458 
 
4459 
parameter nr_of_ports = 3;
4460 
parameter adr_size = 26;
4461 
parameter adr_lo   = 2;
4462 
parameter dat_size = 32;
4463 
parameter sel_size = dat_size/8;
4464 
 
4465 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
4466 
localparam dw = dat_size * nr_of_ports;
4467 
localparam sw = sel_size * nr_of_ports;
4468 
localparam cw = 3 * nr_of_ports;
4469 
localparam bw = 2 * nr_of_ports;
4470 
 
4471 
input  [dw-1:0] wbm_dat_o;
4472 
input  [aw-1:0] wbm_adr_o;
4473 
input  [sw-1:0] wbm_sel_o;
4474 
input  [cw-1:0] wbm_cti_o;
4475 
input  [bw-1:0] wbm_bte_o;
4476 
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
4477 
output [dw-1:0] wbm_dat_i;
4478 
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
4479 
 
4480 
output [dat_size-1:0] wbs_dat_i;
4481 
output [adr_size-1:adr_lo] wbs_adr_i;
4482 
output [sel_size-1:0] wbs_sel_i;
4483 
output [2:0] wbs_cti_i;
4484 
output [1:0] wbs_bte_i;
4485 
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
4486 
input  [dat_size-1:0] wbs_dat_o;
4487 
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
4488 
 
4489 
input wb_clk, wb_rst;
4490 
 
4491 44 unneback 
reg  [nr_of_ports-1:0] select;
4492 39 unneback 
wire [nr_of_ports-1:0] state;
4493 
wire [nr_of_ports-1:0] eoc; // end-of-cycle
4494 
wire [nr_of_ports-1:0] sel;
4495 
wire idle;
4496 
 
4497 
genvar i;
4498 
 
4499 
assign idle = !(|state);
4500 
 
4501 
generate
4502 
if (nr_of_ports == 2) begin
4503 
 
4504 
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
4505 
 
4506 
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4507 
 
4508 44 unneback 
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4509 
 
4510 
    always @ (idle or wbm_cyc_o)
4511 
    if (idle)
4512 
        casex (wbm_cyc_o)
4513 
        2'b1x : select = 2'b10;
4514 
        2'b01 : select = 2'b01;
4515 
        default : select = {nr_of_ports{1'b0}};
4516 
        endcase
4517 
    else
4518 
        select = {nr_of_ports{1'b0}};
4519 
 
4520 39 unneback 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4521 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4522 
 
4523 
end
4524 
endgenerate
4525 
 
4526 
generate
4527 
if (nr_of_ports == 3) begin
4528 
 
4529 
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4530 
 
4531 
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4532 
 
4533 44 unneback 
    always @ (idle or wbm_cyc_o)
4534 
    if (idle)
4535 
        casex (wbm_cyc_o)
4536 
        3'b1xx : select = 3'b100;
4537 
        3'b01x : select = 3'b010;
4538 
        3'b001 : select = 3'b001;
4539 
        default : select = {nr_of_ports{1'b0}};
4540 
        endcase
4541 
    else
4542 
        select = {nr_of_ports{1'b0}};
4543 
 
4544 
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4545 39 unneback 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4546 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4547 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4548 
 
4549 
end
4550 
endgenerate
4551 
 
4552 
generate
4553 44 unneback 
if (nr_of_ports == 4) begin
4554 
 
4555 
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4556 
 
4557 
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4558 
 
4559 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4560 
 
4561 
    always @ (idle or wbm_cyc_o)
4562 
    if (idle)
4563 
        casex (wbm_cyc_o)
4564 
        4'b1xxx : select = 4'b1000;
4565 
        4'b01xx : select = 4'b0100;
4566 
        4'b001x : select = 4'b0010;
4567 
        4'b0001 : select = 4'b0001;
4568 
        default : select = {nr_of_ports{1'b0}};
4569 
        endcase
4570 
    else
4571 
        select = {nr_of_ports{1'b0}};
4572 
 
4573 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4574 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4575 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4576 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4577 
 
4578 
end
4579 
endgenerate
4580 
 
4581 
generate
4582 
if (nr_of_ports == 5) begin
4583 
 
4584 
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4585 
 
4586 
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4587 
 
4588 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4589 
 
4590 
    always @ (idle or wbm_cyc_o)
4591 
    if (idle)
4592 
        casex (wbm_cyc_o)
4593 
        5'b1xxxx : select = 5'b10000;
4594 
        5'b01xxx : select = 5'b01000;
4595 
        5'b001xx : select = 5'b00100;
4596 
        5'b0001x : select = 5'b00010;
4597 
        5'b00001 : select = 5'b00001;
4598 
        default : select = {nr_of_ports{1'b0}};
4599 
        endcase
4600 
    else
4601 
        select = {nr_of_ports{1'b0}};
4602 
 
4603 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
4604 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4605 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4606 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4607 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4608 
 
4609 
end
4610 
endgenerate
4611 
 
4612 
generate
4613 39 unneback 
for (i=0;i<nr_of_ports;i=i+1) begin
4614 42 unneback 
`define MODULE spr
4615 
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
4616 
`undef MODULE
4617 39 unneback 
end
4618 
endgenerate
4619 
 
4620 
    assign sel = select | state;
4621 
 
4622 40 unneback 
`define MODULE mux_andor
4623 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
4624 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
4625 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
4626 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
4627 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
4628 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
4629 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
4630 
`undef MODULE
4631 39 unneback 
    assign wbs_cyc_i = |sel;
4632 
 
4633 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
4634 
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
4635 
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
4636 
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
4637 
 
4638 
endmodule
4639 40 unneback 
`endif
4640 39 unneback 
 
4641 49 unneback 
`ifdef WB_B4_RAM_BE
4642 
// WB RAM with byte enable
4643 59 unneback 
`define MODULE wb_b3_ram_be
4644 
module `BASE`MODULE (
4645 
`undef MODULE
4646 
    wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
4647 
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
4648 
 
4649 
    parameter dat_width = 32;
4650 
    parameter adr_width = 8;
4651 
 
4652 
input [dat_width-1:0] wb_dat_i;
4653 
input [adr_width-1:0] wb_adr_i;
4654 
input [2:0] wb_cti_i;
4655 
input [dat_width/8-1:0] wb_sel_i;
4656 
input wb_we_i, wb_stb_i, wb_cyc_i;
4657 
output [dat_width-1:0] wb_dat_o;
4658 
reg [dat_width-1:0] wb_dat_o;
4659 
output wb_stall_o;
4660 
output wb_ack_o;
4661 
reg wb_ack_o;
4662 
input wb_clk, wb_rst;
4663 
 
4664 
wire [dat_width/8-1:0] cke;
4665 
 
4666 
generate
4667 
if (dat_width==32) begin
4668 
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
4669 
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
4670 
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
4671 
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
4672 
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
4673 
    always @ (posedge wb_clk)
4674 
    begin
4675 
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
4676 
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
4677 
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
4678 
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
4679 
    end
4680 
    always @ (posedge wb_clk or posedge wb_rst)
4681 
    begin
4682 
        if (wb_rst)
4683 
            wb_dat_o <= 32'h0;
4684 
        else
4685 
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
4686 
    end
4687 
end
4688 
endgenerate
4689 
 
4690 
always @ (posedge wb_clk or posedge wb_rst)
4691 
if (wb_rst)
4692 
    wb_ack_o <= 1'b0;
4693 
else
4694 
    if (wb_cti_i=3'b000 | wb_cti_i=3'b111)
4695 
        wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
4696 
    else
4697 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
4698 
endmodule
4699 
`endif
4700 
 
4701 
`ifdef WB_B4_RAM_BE
4702 
// WB RAM with byte enable
4703 49 unneback 
`define MODULE wb_b4_ram_be
4704 
module `BASE`MODULE (
4705 
`undef MODULE
4706 
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
4707 52 unneback 
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
4708 49 unneback 
 
4709 
    parameter dat_width = 32;
4710 
    parameter adr_width = 8;
4711 
 
4712 
input [dat_width-1:0] wb_dat_i;
4713 
input [adr_width-1:0] wb_adr_i;
4714 
input [dat_width/8-1:0] wb_sel_i;
4715 
input wb_we_i, wb_stb_i, wb_cyc_i;
4716 
output [dat_width-1:0] wb_dat_o;
4717 51 unneback 
reg [dat_width-1:0] wb_dat_o;
4718 52 unneback 
output wb_stall_o;
4719 49 unneback 
output wb_ack_o;
4720 
reg wb_ack_o;
4721 
input wb_clk, wb_rst;
4722 
 
4723 56 unneback 
wire [dat_width/8-1:0] cke;
4724 
 
4725 49 unneback 
generate
4726 
if (dat_width==32) begin
4727 51 unneback 
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
4728 
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
4729 
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
4730 
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
4731 56 unneback 
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
4732 49 unneback 
    always @ (posedge wb_clk)
4733 
    begin
4734 56 unneback 
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
4735 
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
4736 
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
4737 
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
4738 49 unneback 
    end
4739 59 unneback 
    always @ (posedge wb_clk or posedge wb_rst)
4740 
    begin
4741 
        if (wb_rst)
4742 
            wb_dat_o <= 32'h0;
4743 
        else
4744 
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
4745 
    end
4746 49 unneback 
end
4747 
endgenerate
4748 
 
4749 52 unneback 
always @ (posedge wb_clk or posedge wb_rst)
4750 55 unneback 
if (wb_rst)
4751 52 unneback 
    wb_ack_o <= 1'b0;
4752 
else
4753 54 unneback 
    wb_ack_o <= wb_stb_i & wb_cyc_i;
4754 52 unneback 
 
4755 
assign wb_stall_o = 1'b0;
4756 
 
4757 49 unneback 
endmodule
4758 
`endif
4759 
 
4760 48 unneback 
`ifdef WB_B4_ROM
4761 
// WB ROM
4762 
`define MODULE wb_b4_rom
4763 
module `BASE`MODULE (
4764 
`undef MODULE
4765 
    wb_adr_i, wb_stb_i, wb_cyc_i,
4766 
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
4767 
 
4768 
    parameter dat_width = 32;
4769 
    parameter dat_default = 32'h15000000;
4770 
    parameter adr_width = 32;
4771 
 
4772 
/*
4773 
`ifndef ROM
4774 
`define ROM "rom.v"
4775 
`endif
4776 
*/
4777 
    input [adr_width-1:2]   wb_adr_i;
4778 
    input                   wb_stb_i;
4779 
    input                   wb_cyc_i;
4780 
    output [dat_width-1:0]  wb_dat_o;
4781 
    reg [dat_width-1:0]     wb_dat_o;
4782 
    output                  wb_ack_o;
4783 
    reg                     wb_ack_o;
4784 
    output                  stall_o;
4785 
    input                   wb_clk;
4786 
    input                   wb_rst;
4787 
 
4788 
always @ (posedge wb_clk or posedge wb_rst)
4789 
    if (wb_rst)
4790 
        wb_dat_o <= {dat_width{1'b0}};
4791 
    else
4792 
         case (wb_adr_i[adr_width-1:2])
4793 
`ifdef ROM
4794 
`include `ROM
4795 
`endif
4796 
           default:
4797 
             wb_dat_o <= dat_default;
4798 
 
4799 
         endcase // case (wb_adr_i)
4800 
 
4801 
 
4802 
always @ (posedge wb_clk or posedge wb_rst)
4803 
    if (wb_rst)
4804 
        wb_ack_o <= 1'b0;
4805 
    else
4806 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
4807 
 
4808 
assign stall_o = 1'b0;
4809 
 
4810 
endmodule
4811 
`endif
4812 
 
4813 
 
4814 40 unneback 
`ifdef WB_BOOT_ROM
4815 17 unneback 
// WB ROM
4816 40 unneback 
`define MODULE wb_boot_rom
4817 
module `BASE`MODULE (
4818 
`undef MODULE
4819 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
4820 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
4821 17 unneback 
 
4822 18 unneback 
    parameter adr_hi = 31;
4823 
    parameter adr_lo = 28;
4824 
    parameter adr_sel = 4'hf;
4825 
    parameter addr_width = 5;
4826 33 unneback 
/*
4827 17 unneback 
`ifndef BOOT_ROM
4828 
`define BOOT_ROM "boot_rom.v"
4829 
`endif
4830 33 unneback 
*/
4831 18 unneback 
    input [adr_hi:2]    wb_adr_i;
4832 
    input               wb_stb_i;
4833 
    input               wb_cyc_i;
4834 
    output [31:0]        wb_dat_o;
4835 
    output              wb_ack_o;
4836 
    output              hit_o;
4837 
    input               wb_clk;
4838 
    input               wb_rst;
4839 
 
4840 
    wire hit;
4841 
    reg [31:0] wb_dat;
4842 
    reg wb_ack;
4843 
 
4844 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
4845 17 unneback 
 
4846 
always @ (posedge wb_clk or posedge wb_rst)
4847 
    if (wb_rst)
4848 18 unneback 
        wb_dat <= 32'h15000000;
4849 17 unneback 
    else
4850 18 unneback 
         case (wb_adr_i[addr_width-1:2])
4851 33 unneback 
`ifdef BOOT_ROM
4852 17 unneback 
`include `BOOT_ROM
4853 33 unneback 
`endif
4854 17 unneback 
           /*
4855 
            // Zero r0 and jump to 0x00000100
4856 18 unneback 
 
4857 
            1 : wb_dat <= 32'hA8200000;
4858 
            2 : wb_dat <= 32'hA8C00100;
4859 
            3 : wb_dat <= 32'h44003000;
4860 
            4 : wb_dat <= 32'h15000000;
4861 17 unneback 
            */
4862 
           default:
4863 18 unneback 
             wb_dat <= 32'h00000000;
4864 17 unneback 
 
4865 
         endcase // case (wb_adr_i)
4866 
 
4867 
 
4868 
always @ (posedge wb_clk or posedge wb_rst)
4869 
    if (wb_rst)
4870 18 unneback 
        wb_ack <= 1'b0;
4871 17 unneback 
    else
4872 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
4873 17 unneback 
 
4874 18 unneback 
assign hit_o = hit;
4875 
assign wb_dat_o = wb_dat & {32{wb_ack}};
4876 
assign wb_ack_o = wb_ack;
4877 
 
4878 17 unneback 
endmodule
4879 40 unneback 
`endif
4880 32 unneback 
 
4881 40 unneback 
`ifdef WB_DPRAM
4882 
`define MODULE wb_dpram
4883 
module `BASE`MODULE (
4884 
`undef MODULE
4885 32 unneback 
        // wishbone slave side a
4886 
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
4887 
        wbsa_clk, wbsa_rst,
4888 
        // wishbone slave side a
4889 
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
4890 
        wbsb_clk, wbsb_rst);
4891 
 
4892 
parameter data_width = 32;
4893 
parameter addr_width = 8;
4894 
 
4895 
parameter dat_o_mask_a = 1;
4896 
parameter dat_o_mask_b = 1;
4897 
 
4898 
input [31:0] wbsa_dat_i;
4899 
input [addr_width-1:2] wbsa_adr_i;
4900 
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
4901 
output [31:0] wbsa_dat_o;
4902 
output wbsa_ack_o;
4903 
input wbsa_clk, wbsa_rst;
4904 
 
4905 
input [31:0] wbsb_dat_i;
4906 
input [addr_width-1:2] wbsb_adr_i;
4907 
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
4908 
output [31:0] wbsb_dat_o;
4909 
output wbsb_ack_o;
4910 
input wbsb_clk, wbsb_rst;
4911 
 
4912 
wire wbsa_dat_tmp, wbsb_dat_tmp;
4913 
 
4914 40 unneback 
`define MODULE dpram_2r2w
4915 
`BASE`MODULE # (
4916 
`undef MODULE
4917 33 unneback 
    .data_width(data_width), .addr_width(addr_width) )
4918 32 unneback 
dpram0(
4919 
    .d_a(wbsa_dat_i),
4920 
    .q_a(wbsa_dat_tmp),
4921 
    .adr_a(wbsa_adr_i),
4922 
    .we_a(wbsa_we_i),
4923 
    .clk_a(wbsa_clk),
4924 
    .d_b(wbsb_dat_i),
4925 
    .q_b(wbsb_dat_tmp),
4926 
    .adr_b(wbsb_adr_i),
4927 
    .we_b(wbsb_we_i),
4928 
    .clk_b(wbsb_clk) );
4929 
 
4930 33 unneback 
generate if (dat_o_mask_a==1)
4931 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
4932 
endgenerate
4933 33 unneback 
generate if (dat_o_mask_a==0)
4934 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp;
4935 
endgenerate
4936 
 
4937 33 unneback 
generate if (dat_o_mask_b==1)
4938 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
4939 
endgenerate
4940 33 unneback 
generate if (dat_o_mask_b==0)
4941 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp;
4942 
endgenerate
4943 
 
4944 40 unneback 
`define MODULE spr
4945 
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
4946 
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
4947 
`undef MODULE
4948 32 unneback 
 
4949 
endmodule
4950 40 unneback 
`endif
4951 18 unneback 
//////////////////////////////////////////////////////////////////////
4952 
////                                                              ////
4953 
////  Arithmetic functions                                        ////
4954 
////                                                              ////
4955 
////  Description                                                 ////
4956 
////  Arithmetic functions for ALU and DSP                        ////
4957 
////                                                              ////
4958 
////                                                              ////
4959 
////  To Do:                                                      ////
4960 
////   -                                                          ////
4961 
////                                                              ////
4962 
////  Author(s):                                                  ////
4963 
////      - Michael Unneback, unneback@opencores.org              ////
4964 
////        ORSoC AB                                              ////
4965 
////                                                              ////
4966 
//////////////////////////////////////////////////////////////////////
4967 
////                                                              ////
4968 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4969 
////                                                              ////
4970 
//// This source file may be used and distributed without         ////
4971 
//// restriction provided that this copyright statement is not    ////
4972 
//// removed from the file and that any derivative work contains  ////
4973 
//// the original copyright notice and the associated disclaimer. ////
4974 
////                                                              ////
4975 
//// This source file is free software; you can redistribute it   ////
4976 
//// and/or modify it under the terms of the GNU Lesser General   ////
4977 
//// Public License as published by the Free Software Foundation; ////
4978 
//// either version 2.1 of the License, or (at your option) any   ////
4979 
//// later version.                                               ////
4980 
////                                                              ////
4981 
//// This source is distributed in the hope that it will be       ////
4982 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4983 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4984 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4985 
//// details.                                                     ////
4986 
////                                                              ////
4987 
//// You should have received a copy of the GNU Lesser General    ////
4988 
//// Public License along with this source; if not, download it   ////
4989 
//// from http://www.opencores.org/lgpl.shtml                     ////
4990 
////                                                              ////
4991 
//////////////////////////////////////////////////////////////////////
4992 
 
4993 40 unneback 
`ifdef MULTS
4994 18 unneback 
// signed multiplication
4995 40 unneback 
`define MODULE mults
4996 
module `BASE`MODULE (a,b,p);
4997 
`undef MODULE
4998 18 unneback 
parameter operand_a_width = 18;
4999 
parameter operand_b_width = 18;
5000 
parameter result_hi = 35;
5001 
parameter result_lo = 0;
5002 
input [operand_a_width-1:0] a;
5003 
input [operand_b_width-1:0] b;
5004 
output [result_hi:result_lo] p;
5005 
wire signed [operand_a_width-1:0] ai;
5006 
wire signed [operand_b_width-1:0] bi;
5007 
wire signed [operand_a_width+operand_b_width-1:0] result;
5008 
 
5009 
    assign ai = a;
5010 
    assign bi = b;
5011 
    assign result = ai * bi;
5012 
    assign p = result[result_hi:result_lo];
5013 
 
5014 
endmodule
5015 40 unneback 
`endif
5016 
`ifdef MULTS18X18
5017 
`define MODULE mults18x18
5018 
module `BASE`MODULE (a,b,p);
5019 
`undef MODULE
5020 18 unneback 
input [17:0] a,b;
5021 
output [35:0] p;
5022 
vl_mult
5023 
    # (.operand_a_width(18), .operand_b_width(18))
5024 
    mult0 (.a(a), .b(b), .p(p));
5025 
endmodule
5026 40 unneback 
`endif
5027 18 unneback 
 
5028 40 unneback 
`ifdef MULT
5029 
`define MODULE mult
5030 18 unneback 
// unsigned multiplication
5031 40 unneback 
module `BASE`MODULE (a,b,p);
5032 
`undef MODULE
5033 18 unneback 
parameter operand_a_width = 18;
5034 
parameter operand_b_width = 18;
5035 
parameter result_hi = 35;
5036 
parameter result_lo = 0;
5037 
input [operand_a_width-1:0] a;
5038 
input [operand_b_width-1:0] b;
5039 
output [result_hi:result_hi] p;
5040 
 
5041 
wire [operand_a_width+operand_b_width-1:0] result;
5042 
 
5043 
    assign result = a * b;
5044 
    assign p = result[result_hi:result_lo];
5045 
 
5046 
endmodule
5047 40 unneback 
`endif
5048 18 unneback 
 
5049 40 unneback 
`ifdef SHIFT_UNIT_32
5050 
`define MODULE shift_unit_32
5051 18 unneback 
// shift unit
5052 
// supporting the following shift functions
5053 
//   SLL
5054 
//   SRL
5055 
//   SRA
5056 
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
5057 40 unneback 
module `BASE`MODULE( din, s, dout, opcode);
5058 
`undef MODULE
5059 18 unneback 
input [31:0] din; // data in operand
5060 
input [4:0] s; // shift operand
5061 
input [1:0] opcode;
5062 
output [31:0] dout;
5063 
 
5064 
parameter opcode_sll = 2'b00;
5065 
//parameter opcode_srl = 2'b01;
5066 
parameter opcode_sra = 2'b10;
5067 
//parameter opcode_ror = 2'b11;
5068 
 
5069 
wire sll, sra;
5070 
assign sll = opcode == opcode_sll;
5071 
assign sra = opcode == opcode_sra;
5072 
 
5073 
wire [15:1] s1;
5074 
wire [3:0] sign;
5075 
wire [7:0] tmp [0:3];
5076 
 
5077 
// first stage is multiplier based
5078 
// shift operand as fractional 8.7
5079 
assign s1[15] = sll & s[2:0]==3'd7;
5080 
assign s1[14] = sll & s[2:0]==3'd6;
5081 
assign s1[13] = sll & s[2:0]==3'd5;
5082 
assign s1[12] = sll & s[2:0]==3'd4;
5083 
assign s1[11] = sll & s[2:0]==3'd3;
5084 
assign s1[10] = sll & s[2:0]==3'd2;
5085 
assign s1[ 9] = sll & s[2:0]==3'd1;
5086 
assign s1[ 8] = s[2:0]==3'd0;
5087 
assign s1[ 7] = !sll & s[2:0]==3'd1;
5088 
assign s1[ 6] = !sll & s[2:0]==3'd2;
5089 
assign s1[ 5] = !sll & s[2:0]==3'd3;
5090 
assign s1[ 4] = !sll & s[2:0]==3'd4;
5091 
assign s1[ 3] = !sll & s[2:0]==3'd5;
5092 
assign s1[ 2] = !sll & s[2:0]==3'd6;
5093 
assign s1[ 1] = !sll & s[2:0]==3'd7;
5094 
 
5095 
assign sign[3] = din[31] & sra;
5096 
assign sign[2] = sign[3] & (&din[31:24]);
5097 
assign sign[1] = sign[2] & (&din[23:16]);
5098 
assign sign[0] = sign[1] & (&din[15:8]);
5099 40 unneback 
`define MODULE mults
5100 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
5101 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
5102 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
5103 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
5104 
`undef MODULE
5105 18 unneback 
// second stage is multiplexer based
5106 
// shift on byte level
5107 
 
5108 
// mux byte 3
5109 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
5110 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
5111 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
5112 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
5113 
                     {8{sign[3]}};
5114 
 
5115 
// mux byte 2
5116 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
5117 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
5118 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
5119 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5120 
                     (s[4:3]==2'b01) ? tmp[3] :
5121 
                     {8{sign[3]}};
5122 
 
5123 
// mux byte 1
5124 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
5125 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
5126 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
5127 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5128 
                     (s[4:3]==2'b01) ? tmp[2] :
5129 
                     (s[4:3]==2'b10) ? tmp[3] :
5130 
                     {8{sign[3]}};
5131 
 
5132 
// mux byte 0
5133 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
5134 
                     (sll) ?  {8{1'b0}}:
5135 
                     (s[4:3]==2'b01) ? tmp[1] :
5136 
                     (s[4:3]==2'b10) ? tmp[2] :
5137 
                     tmp[3];
5138 
 
5139 
endmodule
5140 40 unneback 
`endif
5141 18 unneback 
 
5142 40 unneback 
`ifdef LOGIC_UNIT
5143 18 unneback 
// logic unit
5144 
// supporting the following logic functions
5145 
//    a and b
5146 
//    a or  b
5147 
//    a xor b
5148 
//    not b
5149 40 unneback 
`define MODULE logic_unit
5150 
module `BASE`MODULE( a, b, result, opcode);
5151 
`undef MODULE
5152 18 unneback 
parameter width = 32;
5153 
parameter opcode_and = 2'b00;
5154 
parameter opcode_or  = 2'b01;
5155 
parameter opcode_xor = 2'b10;
5156 
input [width-1:0] a,b;
5157 
output [width-1:0] result;
5158 
input [1:0] opcode;
5159 
 
5160 
assign result = (opcode==opcode_and) ? a & b :
5161 
                (opcode==opcode_or)  ? a | b :
5162 
                (opcode==opcode_xor) ? a ^ b :
5163 
                b;
5164 
 
5165 
endmodule
5166 48 unneback 
`endif
5167 18 unneback 
 
5168 48 unneback 
`ifdef ARITH_UNIT
5169 
`define MODULE arith_unit
5170 
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
5171 
`undef MODULE
5172 18 unneback 
parameter width = 32;
5173 
parameter opcode_add = 1'b0;
5174 
parameter opcode_sub = 1'b1;
5175 
input [width-1:0] a,b;
5176 
input c_in, add_sub, sign;
5177 
output [width-1:0] result;
5178 
output c_out, z, ovfl;
5179 
 
5180 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
5181 
assign z = (result=={width{1'b0}});
5182 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
5183 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
5184 
endmodule
5185 40 unneback 
`endif
5186 48 unneback 
 
5187 
`ifdef COUNT_UNIT
5188 
`define MODULE count_unit
5189 
module `BASE`MODULE (din, dout, opcode);
5190 
`undef MODULE
5191 
parameter width = 32;
5192 
input [width-1:0] din;
5193 
output [width-1:0] dout;
5194 
input opcode;
5195 
 
5196 
integer i;
5197 58 unneback 
wire [width/32+4:0] ff1, fl1;
5198 48 unneback 
 
5199 57 unneback 
/*
5200 48 unneback 
always @(din) begin
5201 
    ff1 = 0; i = 0;
5202 
    while (din[i] == 0 && i < width) begin // complex condition
5203 
        ff1 = ff1 + 1;
5204 
        i = i + 1;
5205 
    end
5206 
end
5207 
 
5208 
always @(din) begin
5209 
    fl1 = width; i = width-1;
5210 
    while (din[i] == 0 && i >= width) begin // complex condition
5211 
        fl1 = fl1 - 1;
5212 
        i = i - 1;
5213 
    end
5214 
end
5215 57 unneback 
*/
5216 48 unneback 
 
5217 
generate
5218 
if (width==32) begin
5219 57 unneback 
 
5220 
    assign ff1 = din[0] ? 6'd1 :
5221 
                 din[1] ? 6'd2 :
5222 
                 din[2] ? 6'd3 :
5223 
                 din[3] ? 6'd4 :
5224 
                 din[4] ? 6'd5 :
5225 
                 din[5] ? 6'd6 :
5226 
                 din[6] ? 6'd7 :
5227 
                 din[7] ? 6'd8 :
5228 
                 din[8] ? 6'd9 :
5229 
                 din[9] ? 6'd10 :
5230 
                 din[10] ? 6'd11 :
5231 
                 din[11] ? 6'd12 :
5232 
                 din[12] ? 6'd13 :
5233 
                 din[13] ? 6'd14 :
5234 
                 din[14] ? 6'd15 :
5235 
                 din[15] ? 6'd16 :
5236 
                 din[16] ? 6'd17 :
5237 
                 din[17] ? 6'd18 :
5238 
                 din[18] ? 6'd19 :
5239 
                 din[19] ? 6'd20 :
5240 
                 din[20] ? 6'd21 :
5241 
                 din[21] ? 6'd22 :
5242 
                 din[22] ? 6'd23 :
5243 
                 din[23] ? 6'd24 :
5244 
                 din[24] ? 6'd25 :
5245 
                 din[25] ? 6'd26 :
5246 
                 din[26] ? 6'd27 :
5247 
                 din[27] ? 6'd28 :
5248 
                 din[28] ? 6'd29 :
5249 
                 din[29] ? 6'd30 :
5250 
                 din[30] ? 6'd31 :
5251 
                 din[31] ? 6'd32 :
5252 
                 6'd0;
5253 
 
5254 
    assign fl1 = din[31] ? 6'd32 :
5255 
                 din[30] ? 6'd31 :
5256 
                 din[29] ? 6'd30 :
5257 
                 din[28] ? 6'd29 :
5258 
                 din[27] ? 6'd28 :
5259 
                 din[26] ? 6'd27 :
5260 
                 din[25] ? 6'd26 :
5261 
                 din[24] ? 6'd25 :
5262 
                 din[23] ? 6'd24 :
5263 
                 din[22] ? 6'd23 :
5264 
                 din[21] ? 6'd22 :
5265 
                 din[20] ? 6'd21 :
5266 
                 din[19] ? 6'd20 :
5267 
                 din[18] ? 6'd19 :
5268 
                 din[17] ? 6'd18 :
5269 
                 din[16] ? 6'd17 :
5270 
                 din[15] ? 6'd16 :
5271 
                 din[14] ? 6'd15 :
5272 
                 din[13] ? 6'd14 :
5273 
                 din[12] ? 6'd13 :
5274 
                 din[11] ? 6'd12 :
5275 
                 din[10] ? 6'd11 :
5276 
                 din[9] ? 6'd10 :
5277 
                 din[8] ? 6'd9 :
5278 
                 din[7] ? 6'd8 :
5279 
                 din[6] ? 6'd7 :
5280 
                 din[5] ? 6'd6 :
5281 
                 din[4] ? 6'd5 :
5282 
                 din[3] ? 6'd4 :
5283 
                 din[2] ? 6'd3 :
5284 
                 din[1] ? 6'd2 :
5285 
                 din[0] ? 6'd1 :
5286 
                 6'd0;
5287 
 
5288 
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
5289 48 unneback 
end
5290 
endgenerate
5291 57 unneback 
 
5292 48 unneback 
generate
5293 
if (width==64) begin
5294 57 unneback 
    assign ff1 = 7'd0;
5295 
    assign fl1 = 7'd0;
5296 
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
5297 48 unneback 
end
5298 
endgenerate
5299 
 
5300 
endmodule
5301 
`endif
5302 
 
5303 
`ifdef EXT_UNIT
5304 
`define MODULE ext_unit
5305 
module `BASE`MODULE ( a, b, F, result, opcode);
5306 
`undef MODULE
5307 
parameter width = 32;
5308 
input [width-1:0] a, b;
5309 
input F;
5310 
output reg [width-1:0] result;
5311 
input [2:0] opcode;
5312 
 
5313 
generate
5314 
if (width==32) begin
5315 
always @ (a or b or F or opcode)
5316 
begin
5317 
    case (opcode)
5318 
    3'b000: result = {{24{1'b0}},a[7:0]};
5319 
    3'b001: result = {{24{a[7]}},a[7:0]};
5320 
    3'b010: result = {{16{1'b0}},a[7:0]};
5321 
    3'b011: result = {{16{a[15]}},a[15:0]};
5322 
    3'b110: result = (F) ? a : b;
5323 
    default: result = {b[15:0],16'h0000};
5324 
    endcase
5325 
end
5326 
end
5327 
endgenerate
5328 
 
5329 
generate
5330 
if (width==64) begin
5331 
always @ (a or b or F or opcode)
5332 
begin
5333 
    case (opcode)
5334 
    3'b000: result = {{56{1'b0}},a[7:0]};
5335 
    3'b001: result = {{56{a[7]}},a[7:0]};
5336 
    3'b010: result = {{48{1'b0}},a[7:0]};
5337 
    3'b011: result = {{48{a[15]}},a[15:0]};
5338 57 unneback 
    3'b110: result = (F) ? a : b;
5339 48 unneback 
    default: result = {32'h00000000,b[15:0],16'h0000};
5340 
    endcase
5341 
end
5342 
end
5343 
endgenerate
5344 
endmodule
5345 
`endif

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