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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 59

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 44 unneback
`ifdef ACTEL
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
`endif
8
 
9 40 unneback
`ifdef ALL
10
 
11
`define GBUF
12
`define SYNC_RST
13
`define PLL
14
 
15
`define MULTS
16
`define MULTS18X18
17
`define MULT
18
`define SHIFT_UNIT_32
19
`define LOGIC_UNIT
20
 
21
`define CNT_SHREG_WRAP
22
`define CNT_SHREG_CE_WRAP
23
`define CNT_SHREG_CE_CLEAR
24
`define CNT_SHREG_CE_CLEAR_WRAP
25
 
26
`define MUX_ANDOR
27
`define MUX2_ANDOR
28
`define MUX3_ANDOR
29
`define MUX4_ANDOR
30
`define MUX5_ANDOR
31
`define MUX6_ANDOR
32 43 unneback
`define PARITY
33 40 unneback
 
34
`define ROM_INIT
35
`define RAM
36
`define RAM_BE
37
`define DPRAM_1R1W
38
`define DPRAM_2R1W
39
`define DPRAM_2R2W
40
`define FIFO_1R1W_FILL_LEVEL_SYNC
41
`define FIFO_2R2W_SYNC_SIMPLEX
42
`define FIFO_CMP_ASYNC
43
`define FIFO_1R1W_ASYNC
44
`define FIFO_2R2W_ASYNC
45
`define FIFO_2R2W_ASYNC_SIMPLEX
46 48 unneback
`define REG_FILE
47 40 unneback
 
48
`define DFF
49
`define DFF_ARRAY
50
`define DFF_CE
51
`define DFF_CE_CLEAR
52
`define DF_CE_SET
53
`define SPR
54
`define SRP
55
`define DFF_SR
56
`define LATCH
57
`define SHREG
58
`define SHREG_CE
59
`define DELAY
60
`define DELAY_EMPTYFLAG
61
 
62
`define WB3WB3_BRIDGE
63
`define WB3_ARBITER_TYPE1
64 59 unneback
`define WB_B3_RAM_BE
65 49 unneback
`define WB_B4_RAM_BE
66 48 unneback
`define WB_B4_ROM
67 40 unneback
`define WB_BOOT_ROM
68
`define WB_DPRAM
69
 
70 44 unneback
`define IO_DFF_OE
71
`define O_DFF
72
 
73 40 unneback
`endif
74
 
75
`ifdef PLL
76
`ifndef SYNC_RST
77
`define SYNC_RST
78
`endif
79
`endif
80
 
81
`ifdef SYNC_RST
82
`ifndef GBUF
83
`define GBUF
84
`endif
85
`endif
86
 
87
`ifdef WB_DPRAM
88
`ifndef DPRAM_2R2W
89
`define DPRAM_2R2W
90
`endif
91
`ifndef SPR
92
`define SPR
93
`endif
94
`endif
95
 
96
`ifdef WB3_ARBITER_TYPE1
97 42 unneback
`ifndef SPR
98
`define SPR
99
`endif
100 40 unneback
`ifndef MUX_ANDOR
101
`define MUX_ANDOR
102
`endif
103
`endif
104
 
105
`ifdef WB3WB3_BRIDGE
106
`ifndef CNT_SHREG_CE_CLEAR
107
`define CNT_SHREG_CE_CLEAR
108
`endif
109
`ifndef DFF
110
`define DFF
111
`endif
112
`ifndef DFF_CE
113
`define DFF_CE
114
`endif
115
`ifndef CNT_SHREG_CE_CLEAR
116
`define CNT_SHREG_CE_CLEAR
117
`endif
118
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
119
`define FIFO_2R2W_ASYNC_SIMPLEX
120
`endif
121
`endif
122
 
123
`ifdef MULTS18X18
124
`ifndef MULTS
125
`define MULTS
126
`endif
127
`endif
128
 
129
`ifdef SHIFT_UNIT_32
130
`ifndef MULTS
131
`define MULTS
132
`endif
133
`endif
134
 
135
`ifdef MUX2_ANDOR
136
`ifndef MUX_ANDOR
137
`define MUX_ANDOR
138
`endif
139
`endif
140
 
141
`ifdef MUX3_ANDOR
142
`ifndef MUX_ANDOR
143
`define MUX_ANDOR
144
`endif
145
`endif
146
 
147
`ifdef MUX4_ANDOR
148
`ifndef MUX_ANDOR
149
`define MUX_ANDOR
150
`endif
151
`endif
152
 
153
`ifdef MUX5_ANDOR
154
`ifndef MUX_ANDOR
155
`define MUX_ANDOR
156
`endif
157
`endif
158
 
159
`ifdef MUX6_ANDOR
160
`ifndef MUX_ANDOR
161
`define MUX_ANDOR
162
`endif
163
`endif
164
 
165
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
166
`ifndef CNT_BIN_CE
167
`define CNT_BIN_CE
168
`endif
169
`ifndef DPRAM_1R1W
170
`define DPRAM_1R1W
171
`endif
172
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
173
`define CNT_BIN_CE_REW_Q_ZQ_L1
174
`endif
175
`endif
176
 
177
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
178
`ifndef CNT_LFSR_CE
179
`define CNT_LFSR_CE
180
`endif
181
`ifndef DPRAM_2R2W
182
`define DPRAM_2R2W
183
`endif
184
`ifndef CNT_BIN_CE_REW_ZQ_L1
185
`define CNT_BIN_CE_REW_ZQ_L1
186
`endif
187
`endif
188
 
189
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
190
`ifndef CNT_GRAY_CE_BIN
191
`define CNT_GRAY_CE_BIN
192
`endif
193
`ifndef DPRAM_2R2W
194
`define DPRAM_2R2W
195
`endif
196
`ifndef FIFO_CMP_ASYNC
197
`define FIFO_CMP_ASYNC
198
`endif
199
`endif
200
 
201
`ifdef FIFO_2R2W_ASYNC
202
`ifndef FIFO_1R1W_ASYNC
203
`define FIFO_1R1W_ASYNC
204
`endif
205
`endif
206
 
207
`ifdef FIFO_1R1W_ASYNC
208
`ifndef CNT_GRAY_CE_BIN
209
`define CNT_GRAY_CE_BIN
210
`endif
211
`ifndef DPRAM_1R1W
212
`define DPRAM_1R1W
213
`endif
214
`ifndef FIFO_CMP_ASYNC
215
`define FIFO_CMP_ASYNC
216
`endif
217
`endif
218
 
219
`ifdef FIFO_CMP_ASYNC
220
`ifndef DFF_SR
221
`define DFF_SR
222
`endif
223
`ifndef DFF
224
`define DFF
225
`endif
226
`endif
227 48 unneback
 
228
`ifdef REG_FILE
229
`ifndef DPRAM_1R1W
230
`define DPRAM_1R1W
231
`endif
232
`endif
233 6 unneback
//////////////////////////////////////////////////////////////////////
234
////                                                              ////
235
////  Versatile library, clock and reset                          ////
236
////                                                              ////
237
////  Description                                                 ////
238
////  Logic related to clock and reset                            ////
239
////                                                              ////
240
////                                                              ////
241
////  To Do:                                                      ////
242
////   - add more different registers                             ////
243
////                                                              ////
244
////  Author(s):                                                  ////
245
////      - Michael Unneback, unneback@opencores.org              ////
246
////        ORSoC AB                                              ////
247
////                                                              ////
248
//////////////////////////////////////////////////////////////////////
249
////                                                              ////
250
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
251
////                                                              ////
252
//// This source file may be used and distributed without         ////
253
//// restriction provided that this copyright statement is not    ////
254
//// removed from the file and that any derivative work contains  ////
255
//// the original copyright notice and the associated disclaimer. ////
256
////                                                              ////
257
//// This source file is free software; you can redistribute it   ////
258
//// and/or modify it under the terms of the GNU Lesser General   ////
259
//// Public License as published by the Free Software Foundation; ////
260
//// either version 2.1 of the License, or (at your option) any   ////
261
//// later version.                                               ////
262
////                                                              ////
263
//// This source is distributed in the hope that it will be       ////
264
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
265
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
266
//// PURPOSE.  See the GNU Lesser General Public License for more ////
267
//// details.                                                     ////
268
////                                                              ////
269
//// You should have received a copy of the GNU Lesser General    ////
270
//// Public License along with this source; if not, download it   ////
271
//// from http://www.opencores.org/lgpl.shtml                     ////
272
////                                                              ////
273
//////////////////////////////////////////////////////////////////////
274
 
275 48 unneback
`ifdef ACTEL
276
`ifdef GBUF
277
`timescale 1 ns/100 ps
278 6 unneback
// Global buffer
279
// usage:
280
// use to enable global buffers for high fan out signals such as clock and reset
281
// Version: 8.4 8.4.0.33
282
module gbuf(GL,CLK);
283
output GL;
284
input  CLK;
285
 
286
    wire GND;
287
 
288
    GND GND_1_net(.Y(GND));
289
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
290
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
291
 
292
endmodule
293
`timescale 1 ns/1 ns
294 40 unneback
`define MODULE gbuf
295
module `BASE`MODULE ( i, o);
296
`undef MODULE
297 6 unneback
input i;
298
output o;
299
`ifdef SIM_GBUF
300
assign o=i;
301
`else
302
gbuf gbuf_i0 ( .CLK(i), .GL(o));
303
`endif
304
endmodule
305 40 unneback
`endif
306 33 unneback
 
307 6 unneback
`else
308 33 unneback
 
309 40 unneback
`ifdef ALTERA
310
`ifdef GBUF
311 21 unneback
//altera
312 40 unneback
`define MODULE gbuf
313
module `BASE`MODULE ( i, o);
314
`undef MODULE
315 33 unneback
input i;
316
output o;
317
assign o = i;
318
endmodule
319 40 unneback
`endif
320 33 unneback
 
321 6 unneback
`else
322
 
323 40 unneback
`ifdef GBUF
324 6 unneback
`timescale 1 ns/100 ps
325 40 unneback
`define MODULE
326
module `BASE`MODULE ( i, o);
327
`undef MODULE
328 6 unneback
input i;
329
output o;
330
assign o = i;
331
endmodule
332 40 unneback
`endif
333 6 unneback
`endif // ALTERA
334
`endif //ACTEL
335
 
336 40 unneback
`ifdef SYNC_RST
337 6 unneback
// sync reset
338 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
339 6 unneback
// output active high global reset sync with two DFFs 
340
`timescale 1 ns/100 ps
341 40 unneback
`define MODULE sync_rst
342
module `BASE`MODULE ( rst_n_i, rst_o, clk);
343
`undef MODULE
344 6 unneback
input rst_n_i, clk;
345
output rst_o;
346 18 unneback
reg [1:0] tmp;
347 6 unneback
always @ (posedge clk or negedge rst_n_i)
348
if (!rst_n_i)
349 17 unneback
        tmp <= 2'b11;
350 6 unneback
else
351 33 unneback
        tmp <= {1'b0,tmp[1]};
352 40 unneback
`define MODULE gbuf
353
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
354
`undef MODULE
355 6 unneback
endmodule
356 40 unneback
`endif
357 6 unneback
 
358 40 unneback
`ifdef PLL
359 6 unneback
// vl_pll
360
`ifdef ACTEL
361 32 unneback
///////////////////////////////////////////////////////////////////////////////
362 17 unneback
`timescale 1 ps/1 ps
363 40 unneback
`define MODULE pll
364
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
365
`undef MODULE
366 6 unneback
parameter index = 0;
367
parameter number_of_clk = 1;
368 17 unneback
parameter period_time_0 = 20000;
369
parameter period_time_1 = 20000;
370
parameter period_time_2 = 20000;
371
parameter lock_delay = 2000000;
372 6 unneback
input clk_i, rst_n_i;
373
output lock;
374
output reg [0:number_of_clk-1] clk_o;
375
output [0:number_of_clk-1] rst_o;
376
 
377
`ifdef SIM_PLL
378
 
379
always
380
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
381
 
382
generate if (number_of_clk > 1)
383
always
384
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
385
endgenerate
386
 
387
generate if (number_of_clk > 2)
388
always
389
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
390
endgenerate
391
 
392
genvar i;
393
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
394
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
395
end
396
endgenerate
397
 
398
assign #lock_delay lock = rst_n_i;
399
 
400
endmodule
401
`else
402
generate if (number_of_clk==1 & index==0) begin
403
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
404
end
405
endgenerate // index==0
406
generate if (number_of_clk==1 & index==1) begin
407
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
408
end
409
endgenerate // index==1
410
generate if (number_of_clk==1 & index==2) begin
411
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
412
end
413
endgenerate // index==2
414
generate if (number_of_clk==1 & index==3) begin
415
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
416
end
417
endgenerate // index==0
418
 
419
generate if (number_of_clk==2 & index==0) begin
420
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
421
end
422
endgenerate // index==0
423
generate if (number_of_clk==2 & index==1) begin
424
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
425
end
426
endgenerate // index==1
427
generate if (number_of_clk==2 & index==2) begin
428
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
429
end
430
endgenerate // index==2
431
generate if (number_of_clk==2 & index==3) begin
432
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
433
end
434
endgenerate // index==0
435
 
436
generate if (number_of_clk==3 & index==0) begin
437
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
438
end
439
endgenerate // index==0
440
generate if (number_of_clk==3 & index==1) begin
441
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
442
end
443
endgenerate // index==1
444
generate if (number_of_clk==3 & index==2) begin
445
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
446
end
447
endgenerate // index==2
448
generate if (number_of_clk==3 & index==3) begin
449
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
450
end
451
endgenerate // index==0
452
 
453
genvar i;
454
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
455 40 unneback
`define MODULE sync_rst
456
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
457
`undef MODULE
458 6 unneback
end
459
endgenerate
460
endmodule
461
`endif
462 32 unneback
///////////////////////////////////////////////////////////////////////////////
463 6 unneback
 
464
`else
465
 
466 32 unneback
///////////////////////////////////////////////////////////////////////////////
467 6 unneback
`ifdef ALTERA
468
 
469 32 unneback
`timescale 1 ps/1 ps
470 40 unneback
`define MODULE pll
471
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
472
`undef MODULE
473 32 unneback
parameter index = 0;
474
parameter number_of_clk = 1;
475
parameter period_time_0 = 20000;
476
parameter period_time_1 = 20000;
477
parameter period_time_2 = 20000;
478
parameter period_time_3 = 20000;
479
parameter period_time_4 = 20000;
480
parameter lock_delay = 2000000;
481
input clk_i, rst_n_i;
482
output lock;
483
output reg [0:number_of_clk-1] clk_o;
484
output [0:number_of_clk-1] rst_o;
485
 
486
`ifdef SIM_PLL
487
 
488
always
489
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
490
 
491
generate if (number_of_clk > 1)
492
always
493
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
494
endgenerate
495
 
496
generate if (number_of_clk > 2)
497
always
498
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
499
endgenerate
500
 
501 33 unneback
generate if (number_of_clk > 3)
502 32 unneback
always
503
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
504
endgenerate
505
 
506 33 unneback
generate if (number_of_clk > 4)
507 32 unneback
always
508
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
509
endgenerate
510
 
511
genvar i;
512
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
513
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
514
end
515
endgenerate
516
 
517 33 unneback
//assign #lock_delay lock = rst_n_i;
518
assign lock = rst_n_i;
519 32 unneback
 
520
endmodule
521 6 unneback
`else
522
 
523 33 unneback
`ifdef VL_PLL0
524
`ifdef VL_PLL0_CLK1
525
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
526
`endif
527
`ifdef VL_PLL0_CLK2
528
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
529
`endif
530
`ifdef VL_PLL0_CLK3
531
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
532
`endif
533
`ifdef VL_PLL0_CLK4
534
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
535
`endif
536
`ifdef VL_PLL0_CLK5
537
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
538
`endif
539
`endif
540 32 unneback
 
541 33 unneback
`ifdef VL_PLL1
542
`ifdef VL_PLL1_CLK1
543
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
544
`endif
545
`ifdef VL_PLL1_CLK2
546
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
547
`endif
548
`ifdef VL_PLL1_CLK3
549
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
550
`endif
551
`ifdef VL_PLL1_CLK4
552
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
553
`endif
554
`ifdef VL_PLL1_CLK5
555
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
556
`endif
557
`endif
558 32 unneback
 
559 33 unneback
`ifdef VL_PLL2
560
`ifdef VL_PLL2_CLK1
561
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
562
`endif
563
`ifdef VL_PLL2_CLK2
564
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
565
`endif
566
`ifdef VL_PLL2_CLK3
567
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
568
`endif
569
`ifdef VL_PLL2_CLK4
570
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
571
`endif
572
`ifdef VL_PLL2_CLK5
573
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
574
`endif
575
`endif
576 32 unneback
 
577 33 unneback
`ifdef VL_PLL3
578
`ifdef VL_PLL3_CLK1
579
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
580
`endif
581
`ifdef VL_PLL3_CLK2
582
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
583
`endif
584
`ifdef VL_PLL3_CLK3
585
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
586
`endif
587
`ifdef VL_PLL3_CLK4
588
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
589
`endif
590
`ifdef VL_PLL3_CLK5
591
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
592
`endif
593
`endif
594 32 unneback
 
595
genvar i;
596
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
597 40 unneback
`define MODULE sync_rst
598
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
599
`undef MODULE
600 32 unneback
end
601
endgenerate
602
endmodule
603
`endif
604
///////////////////////////////////////////////////////////////////////////////
605
 
606
`else
607
 
608 6 unneback
// generic PLL
609 17 unneback
`timescale 1 ps/1 ps
610 40 unneback
`define MODULE pll
611
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
612
`undef MODULE
613 6 unneback
parameter index = 0;
614
parameter number_of_clk = 1;
615 17 unneback
parameter period_time_0 = 20000;
616
parameter period_time_1 = 20000;
617
parameter period_time_2 = 20000;
618 6 unneback
parameter lock_delay = 2000;
619
input clk_i, rst_n_i;
620
output lock;
621
output reg [0:number_of_clk-1] clk_o;
622
output [0:number_of_clk-1] rst_o;
623
 
624
always
625
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
626
 
627
generate if (number_of_clk > 1)
628
always
629
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
630
endgenerate
631
 
632
generate if (number_of_clk > 2)
633
always
634
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
635
endgenerate
636
 
637
genvar i;
638
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
639 40 unneback
`define MODULE sync_rst
640
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
641
`undef MODULE
642 6 unneback
end
643
endgenerate
644
 
645
assign #lock_delay lock = rst_n_i;
646
 
647
endmodule
648
 
649
`endif //altera
650 17 unneback
`endif //actel
651 40 unneback
`undef MODULE
652
`endif//////////////////////////////////////////////////////////////////////
653 6 unneback
////                                                              ////
654
////  Versatile library, registers                                ////
655
////                                                              ////
656
////  Description                                                 ////
657
////  Different type of registers                                 ////
658
////                                                              ////
659
////                                                              ////
660
////  To Do:                                                      ////
661
////   - add more different registers                             ////
662
////                                                              ////
663
////  Author(s):                                                  ////
664
////      - Michael Unneback, unneback@opencores.org              ////
665
////        ORSoC AB                                              ////
666
////                                                              ////
667
//////////////////////////////////////////////////////////////////////
668
////                                                              ////
669
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
670
////                                                              ////
671
//// This source file may be used and distributed without         ////
672
//// restriction provided that this copyright statement is not    ////
673
//// removed from the file and that any derivative work contains  ////
674
//// the original copyright notice and the associated disclaimer. ////
675
////                                                              ////
676
//// This source file is free software; you can redistribute it   ////
677
//// and/or modify it under the terms of the GNU Lesser General   ////
678
//// Public License as published by the Free Software Foundation; ////
679
//// either version 2.1 of the License, or (at your option) any   ////
680
//// later version.                                               ////
681
////                                                              ////
682
//// This source is distributed in the hope that it will be       ////
683
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
684
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
685
//// PURPOSE.  See the GNU Lesser General Public License for more ////
686
//// details.                                                     ////
687
////                                                              ////
688
//// You should have received a copy of the GNU Lesser General    ////
689
//// Public License along with this source; if not, download it   ////
690
//// from http://www.opencores.org/lgpl.shtml                     ////
691
////                                                              ////
692
//////////////////////////////////////////////////////////////////////
693
 
694 40 unneback
`ifdef DFF
695
`define MODULE dff
696
module `BASE`MODULE ( d, q, clk, rst);
697
`undef MODULE
698 6 unneback
        parameter width = 1;
699
        parameter reset_value = 0;
700
 
701
        input [width-1:0] d;
702
        input clk, rst;
703
        output reg [width-1:0] q;
704
 
705
        always @ (posedge clk or posedge rst)
706
        if (rst)
707
                q <= reset_value;
708
        else
709
                q <= d;
710
 
711
endmodule
712 40 unneback
`endif
713 6 unneback
 
714 40 unneback
`ifdef DFF_ARRAY
715
`define MODULE dff_array
716
module `BASE`MODULE ( d, q, clk, rst);
717
`undef MODULE
718 6 unneback
 
719
        parameter width = 1;
720
        parameter depth = 2;
721
        parameter reset_value = 1'b0;
722
 
723
        input [width-1:0] d;
724
        input clk, rst;
725
        output [width-1:0] q;
726
        reg  [0:depth-1] q_tmp [width-1:0];
727
        integer i;
728
        always @ (posedge clk or posedge rst)
729
        if (rst) begin
730
            for (i=0;i<depth;i=i+1)
731
                q_tmp[i] <= {width{reset_value}};
732
        end else begin
733
            q_tmp[0] <= d;
734
            for (i=1;i<depth;i=i+1)
735
                q_tmp[i] <= q_tmp[i-1];
736
        end
737
 
738
    assign q = q_tmp[depth-1];
739
 
740
endmodule
741 40 unneback
`endif
742 6 unneback
 
743 40 unneback
`ifdef DFF_CE
744
`define MODULE dff_ce
745
module `BASE`MODULE ( d, ce, q, clk, rst);
746
`undef MODULE
747 6 unneback
 
748
        parameter width = 1;
749
        parameter reset_value = 0;
750
 
751
        input [width-1:0] d;
752
        input ce, clk, rst;
753
        output reg [width-1:0] q;
754
 
755
        always @ (posedge clk or posedge rst)
756
        if (rst)
757
                q <= reset_value;
758
        else
759
                if (ce)
760
                        q <= d;
761
 
762
endmodule
763 40 unneback
`endif
764 6 unneback
 
765 40 unneback
`ifdef DFF_CE_CLEAR
766
`define MODULE dff_ce_clear
767
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
768
`undef MODULE
769 8 unneback
 
770
        parameter width = 1;
771
        parameter reset_value = 0;
772
 
773
        input [width-1:0] d;
774 10 unneback
        input ce, clear, clk, rst;
775 8 unneback
        output reg [width-1:0] q;
776
 
777
        always @ (posedge clk or posedge rst)
778
        if (rst)
779
            q <= reset_value;
780
        else
781
            if (ce)
782
                if (clear)
783
                    q <= {width{1'b0}};
784
                else
785
                    q <= d;
786
 
787
endmodule
788 40 unneback
`endif
789 8 unneback
 
790 40 unneback
`ifdef DF_CE_SET
791
`define MODULE dff_ce_set
792
module `BASE`MODULE ( d, ce, set, q, clk, rst);
793
`undef MODULE
794 24 unneback
 
795
        parameter width = 1;
796
        parameter reset_value = 0;
797
 
798
        input [width-1:0] d;
799
        input ce, set, clk, rst;
800
        output reg [width-1:0] q;
801
 
802
        always @ (posedge clk or posedge rst)
803
        if (rst)
804
            q <= reset_value;
805
        else
806
            if (ce)
807
                if (set)
808
                    q <= {width{1'b1}};
809
                else
810
                    q <= d;
811
 
812
endmodule
813 40 unneback
`endif
814 24 unneback
 
815 40 unneback
`ifdef SPR
816
`define MODULE spr
817
module `BASE`MODULE ( sp, r, q, clk, rst);
818
`undef MODULE
819
 
820 29 unneback
        parameter width = 1;
821
        parameter reset_value = 0;
822
 
823
        input sp, r;
824
        output reg q;
825
        input clk, rst;
826
 
827
        always @ (posedge clk or posedge rst)
828
        if (rst)
829
            q <= reset_value;
830
        else
831
            if (sp)
832
                q <= 1'b1;
833
            else if (r)
834
                q <= 1'b0;
835
 
836
endmodule
837 40 unneback
`endif
838 29 unneback
 
839 40 unneback
`ifdef SRP
840
`define MODULE srp
841
module `BASE`MODULE ( s, rp, q, clk, rst);
842
`undef MODULE
843
 
844 29 unneback
        parameter width = 1;
845
        parameter reset_value = 0;
846
 
847
        input s, rp;
848
        output reg q;
849
        input clk, rst;
850
 
851
        always @ (posedge clk or posedge rst)
852
        if (rst)
853
            q <= reset_value;
854
        else
855
            if (rp)
856
                q <= 1'b0;
857
            else if (s)
858
                q <= 1'b1;
859
 
860
endmodule
861 40 unneback
`endif
862 29 unneback
 
863 40 unneback
`ifdef ALTERA
864 29 unneback
 
865 40 unneback
`ifdef DFF_SR
866 6 unneback
// megafunction wizard: %LPM_FF%
867
// GENERATION: STANDARD
868
// VERSION: WM1.0
869
// MODULE: lpm_ff 
870
 
871
// ============================================================
872
// File Name: dff_sr.v
873
// Megafunction Name(s):
874
//                      lpm_ff
875
//
876
// Simulation Library Files(s):
877
//                      lpm
878
// ============================================================
879
// ************************************************************
880
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
881
//
882
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
883
// ************************************************************
884
 
885
 
886
//Copyright (C) 1991-2010 Altera Corporation
887
//Your use of Altera Corporation's design tools, logic functions 
888
//and other software and tools, and its AMPP partner logic 
889
//functions, and any output files from any of the foregoing 
890
//(including device programming or simulation files), and any 
891
//associated documentation or information are expressly subject 
892
//to the terms and conditions of the Altera Program License 
893
//Subscription Agreement, Altera MegaCore Function License 
894
//Agreement, or other applicable license agreement, including, 
895
//without limitation, that your use is for the sole purpose of 
896
//programming logic devices manufactured by Altera and sold by 
897
//Altera or its authorized distributors.  Please refer to the 
898
//applicable agreement for further details.
899
 
900
 
901
// synopsys translate_off
902
`timescale 1 ps / 1 ps
903
// synopsys translate_on
904 40 unneback
`define MODULE dff_sr
905
module `BASE`MODULE (
906
`undef MODULE
907
 
908 6 unneback
        aclr,
909
        aset,
910
        clock,
911
        data,
912
        q);
913
 
914
        input     aclr;
915
        input     aset;
916
        input     clock;
917
        input     data;
918
        output    q;
919
 
920
        wire [0:0] sub_wire0;
921
        wire [0:0] sub_wire1 = sub_wire0[0:0];
922
        wire  q = sub_wire1;
923
        wire  sub_wire2 = data;
924
        wire  sub_wire3 = sub_wire2;
925
 
926
        lpm_ff  lpm_ff_component (
927
                                .aclr (aclr),
928
                                .clock (clock),
929
                                .data (sub_wire3),
930
                                .aset (aset),
931
                                .q (sub_wire0)
932
                                // synopsys translate_off
933
                                ,
934
                                .aload (),
935
                                .enable (),
936
                                .sclr (),
937
                                .sload (),
938
                                .sset ()
939
                                // synopsys translate_on
940
                                );
941
        defparam
942
                lpm_ff_component.lpm_fftype = "DFF",
943
                lpm_ff_component.lpm_type = "LPM_FF",
944
                lpm_ff_component.lpm_width = 1;
945
 
946
 
947
endmodule
948
 
949
// ============================================================
950
// CNX file retrieval info
951
// ============================================================
952
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
953
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
954
// Retrieval info: PRIVATE: ASET NUMERIC "1"
955
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
956
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
957
// Retrieval info: PRIVATE: DFF NUMERIC "1"
958
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
959
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
960
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
961
// Retrieval info: PRIVATE: SSET NUMERIC "0"
962
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
963
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
964
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
965
// Retrieval info: PRIVATE: nBit NUMERIC "1"
966
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
967
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
968
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
969
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
970
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
971
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
972
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
973
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
974
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
975
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
976
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
977
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
978
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
979
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
980
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
981
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
982
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
983
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
984
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
985
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
986
// Retrieval info: LIB_FILE: lpm
987 40 unneback
`endif
988 6 unneback
 
989
`else
990
 
991 40 unneback
`ifdef DFF_SR
992
`define MODULE dff_sr
993
module `BASE`MODULE ( aclr, aset, clock, data, q);
994
`undef MODULE
995 6 unneback
 
996
    input         aclr;
997
    input         aset;
998
    input         clock;
999
    input         data;
1000
    output reg    q;
1001
 
1002
   always @ (posedge clock or posedge aclr or posedge aset)
1003
     if (aclr)
1004
       q <= 1'b0;
1005
     else if (aset)
1006
       q <= 1'b1;
1007
     else
1008
       q <= data;
1009
 
1010
endmodule
1011 40 unneback
`endif
1012 6 unneback
 
1013
`endif
1014
 
1015
// LATCH
1016
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1017
`ifdef ALTERA
1018 40 unneback
 
1019
`ifdef LATCH
1020
`define MODULE latch
1021
module `BASE`MODULE ( d, le, q, clk);
1022
`undef MODULE
1023 6 unneback
input d, le;
1024
output q;
1025
input clk;
1026
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1027
endmodule
1028 40 unneback
`endif
1029
 
1030 6 unneback
`else
1031 40 unneback
 
1032
`ifdef LATCH
1033
`define MODULE latch
1034
module `BASE`MODULE ( d, le, q, clk);
1035
`undef MODULE
1036 6 unneback
input d, le;
1037 48 unneback
input clk;
1038
always @ (le or d)
1039
if le
1040
    d <= q;
1041 6 unneback
endmodule
1042 15 unneback
`endif
1043
 
1044 40 unneback
`endif
1045
 
1046
`ifdef SHREG
1047
`define MODULE shreg
1048
module `BASE`MODULE ( d, q, clk, rst);
1049
`undef MODULE
1050
 
1051 17 unneback
parameter depth = 10;
1052
input d;
1053
output q;
1054
input clk, rst;
1055
 
1056
reg [1:depth] dffs;
1057
 
1058
always @ (posedge clk or posedge rst)
1059
if (rst)
1060
    dffs <= {depth{1'b0}};
1061
else
1062
    dffs <= {d,dffs[1:depth-1]};
1063
assign q = dffs[depth];
1064
endmodule
1065 40 unneback
`endif
1066 17 unneback
 
1067 40 unneback
`ifdef SHREG_CE
1068
`define MODULE shreg_ce
1069
module `BASE`MODULE ( d, ce, q, clk, rst);
1070
`undef MODULE
1071 17 unneback
parameter depth = 10;
1072
input d, ce;
1073
output q;
1074
input clk, rst;
1075
 
1076
reg [1:depth] dffs;
1077
 
1078
always @ (posedge clk or posedge rst)
1079
if (rst)
1080
    dffs <= {depth{1'b0}};
1081
else
1082
    if (ce)
1083
        dffs <= {d,dffs[1:depth-1]};
1084
assign q = dffs[depth];
1085
endmodule
1086 40 unneback
`endif
1087 17 unneback
 
1088 40 unneback
`ifdef DELAY
1089
`define MODULE delay
1090
module `BASE`MODULE ( d, q, clk, rst);
1091
`undef MODULE
1092 15 unneback
parameter depth = 10;
1093
input d;
1094
output q;
1095
input clk, rst;
1096
 
1097
reg [1:depth] dffs;
1098
 
1099
always @ (posedge clk or posedge rst)
1100
if (rst)
1101
    dffs <= {depth{1'b0}};
1102
else
1103
    dffs <= {d,dffs[1:depth-1]};
1104
assign q = dffs[depth];
1105 17 unneback
endmodule
1106 40 unneback
`endif
1107 17 unneback
 
1108 40 unneback
`ifdef DELAY_EMPTYFLAG
1109
`define MODULE delay_emptyflag
1110 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1111 40 unneback
`undef MODULE
1112 17 unneback
parameter depth = 10;
1113
input d;
1114
output q, emptyflag;
1115
input clk, rst;
1116
 
1117
reg [1:depth] dffs;
1118
 
1119
always @ (posedge clk or posedge rst)
1120
if (rst)
1121
    dffs <= {depth{1'b0}};
1122
else
1123
    dffs <= {d,dffs[1:depth-1]};
1124
assign q = dffs[depth];
1125
assign emptyflag = !(|dffs);
1126
endmodule
1127 40 unneback
`endif
1128 17 unneback
//////////////////////////////////////////////////////////////////////
1129 6 unneback
////                                                              ////
1130 18 unneback
////  Logic functions                                             ////
1131
////                                                              ////
1132
////  Description                                                 ////
1133
////  Logic functions such as multiplexers                        ////
1134
////                                                              ////
1135
////                                                              ////
1136
////  To Do:                                                      ////
1137
////   -                                                          ////
1138
////                                                              ////
1139
////  Author(s):                                                  ////
1140
////      - Michael Unneback, unneback@opencores.org              ////
1141
////        ORSoC AB                                              ////
1142
////                                                              ////
1143
//////////////////////////////////////////////////////////////////////
1144
////                                                              ////
1145
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1146
////                                                              ////
1147
//// This source file may be used and distributed without         ////
1148
//// restriction provided that this copyright statement is not    ////
1149
//// removed from the file and that any derivative work contains  ////
1150
//// the original copyright notice and the associated disclaimer. ////
1151
////                                                              ////
1152
//// This source file is free software; you can redistribute it   ////
1153
//// and/or modify it under the terms of the GNU Lesser General   ////
1154
//// Public License as published by the Free Software Foundation; ////
1155
//// either version 2.1 of the License, or (at your option) any   ////
1156
//// later version.                                               ////
1157
////                                                              ////
1158
//// This source is distributed in the hope that it will be       ////
1159
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1160
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1161
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1162
//// details.                                                     ////
1163
////                                                              ////
1164
//// You should have received a copy of the GNU Lesser General    ////
1165
//// Public License along with this source; if not, download it   ////
1166
//// from http://www.opencores.org/lgpl.shtml                     ////
1167
////                                                              ////
1168
//////////////////////////////////////////////////////////////////////
1169 40 unneback
`ifdef MUX_ANDOR
1170
`define MODULE mux_andor
1171
module `BASE`MODULE ( a, sel, dout);
1172
`undef MODULE
1173 36 unneback
 
1174
parameter width = 32;
1175
parameter nr_of_ports = 4;
1176
 
1177
input [nr_of_ports*width-1:0] a;
1178
input [nr_of_ports-1:0] sel;
1179
output reg [width-1:0] dout;
1180
 
1181 38 unneback
integer i,j;
1182
 
1183 36 unneback
always @ (a, sel)
1184
begin
1185
    dout = a[width-1:0] & {width{sel[0]}};
1186 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1187
        for (j=0;j<width;j=j+1)
1188
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1189 36 unneback
end
1190
 
1191
endmodule
1192 40 unneback
`endif
1193 36 unneback
 
1194 40 unneback
`ifdef MUX2_ANDOR
1195
`define MODULE mux2_andor
1196
module `BASE`MODULE ( a1, a0, sel, dout);
1197
`undef MODULE
1198 18 unneback
 
1199 34 unneback
parameter width = 32;
1200 35 unneback
localparam nr_of_ports = 2;
1201 34 unneback
input [width-1:0] a1, a0;
1202
input [nr_of_ports-1:0] sel;
1203
output [width-1:0] dout;
1204
 
1205 40 unneback
`define MODULE mux_andor
1206
`BASE`MODULE
1207 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1208 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1209 40 unneback
`undef MODULE
1210
 
1211 34 unneback
endmodule
1212 40 unneback
`endif
1213 34 unneback
 
1214 40 unneback
`ifdef MUX3_ANDOR
1215
`define MODULE mux3_andor
1216
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1217
`undef MODULE
1218 34 unneback
 
1219
parameter width = 32;
1220 35 unneback
localparam nr_of_ports = 3;
1221 34 unneback
input [width-1:0] a2, a1, a0;
1222
input [nr_of_ports-1:0] sel;
1223
output [width-1:0] dout;
1224
 
1225 40 unneback
`define MODULE mux_andor
1226
`BASE`MODULE
1227 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1228 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1229 40 unneback
`undef MODULE
1230 34 unneback
endmodule
1231 40 unneback
`endif
1232 34 unneback
 
1233 40 unneback
`ifdef MUX4_ANDOR
1234
`define MODULE mux4_andor
1235
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1236
`undef MODULE
1237 18 unneback
 
1238
parameter width = 32;
1239 35 unneback
localparam nr_of_ports = 4;
1240 18 unneback
input [width-1:0] a3, a2, a1, a0;
1241
input [nr_of_ports-1:0] sel;
1242 22 unneback
output [width-1:0] dout;
1243 18 unneback
 
1244 40 unneback
`define MODULE mux_andor
1245
`BASE`MODULE
1246 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1247 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1248 40 unneback
`undef MODULE
1249 18 unneback
 
1250
endmodule
1251 40 unneback
`endif
1252 18 unneback
 
1253 40 unneback
`ifdef MUX5_ANDOR
1254
`define MODULE mux5_andor
1255
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1256
`undef MODULE
1257 18 unneback
 
1258
parameter width = 32;
1259 35 unneback
localparam nr_of_ports = 5;
1260 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1261
input [nr_of_ports-1:0] sel;
1262 22 unneback
output [width-1:0] dout;
1263 18 unneback
 
1264 40 unneback
`define MODULE mux_andor
1265
`BASE`MODULE
1266 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1267 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1268 40 unneback
`undef MODULE
1269 18 unneback
 
1270
endmodule
1271 40 unneback
`endif
1272 18 unneback
 
1273 40 unneback
`ifdef MUX6_ANDOR
1274
`define MODULE mux6_andor
1275
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1276
`undef MODULE
1277 18 unneback
 
1278
parameter width = 32;
1279 35 unneback
localparam nr_of_ports = 6;
1280 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1281
input [nr_of_ports-1:0] sel;
1282 22 unneback
output [width-1:0] dout;
1283 18 unneback
 
1284 40 unneback
`define MODULE mux_andor
1285
`BASE`MODULE
1286 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1287 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1288 40 unneback
`undef MODULE
1289 18 unneback
 
1290
endmodule
1291 40 unneback
`endif
1292 43 unneback
 
1293
`ifdef PARITY
1294
 
1295
`define MODULE parity_generate
1296
module `BASE`MODULE (data, parity);
1297
`undef MODULE
1298
parameter word_size = 32;
1299
parameter chunk_size = 8;
1300
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1301
input [word_size-1:0] data;
1302
output reg [word_size/chunk_size-1:0] parity;
1303
integer i,j;
1304
always @ (data)
1305
for (i=0;i<word_size/chunk_size;i=i+1) begin
1306
    parity[i] = parity_type;
1307
    for (j=0;j<chunk_size;j=j+1) begin
1308 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1309 43 unneback
    end
1310
end
1311
endmodule
1312
 
1313
`define MODULE parity_check
1314
module `BASE`MODULE( data, parity, parity_error);
1315
`undef MODULE
1316
parameter word_size = 32;
1317
parameter chunk_size = 8;
1318
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1319
input [word_size-1:0] data;
1320
input [word_size/chunk_size-1:0] parity;
1321
output parity_error;
1322 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1323 43 unneback
integer i,j;
1324
always @ (data or parity)
1325
for (i=0;i<word_size/chunk_size;i=i+1) begin
1326
    error_flag[i] = parity[i] ^ parity_type;
1327
    for (j=0;j<chunk_size;j=j+1) begin
1328 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1329 43 unneback
    end
1330
end
1331
assign parity_error = |error_flag;
1332
endmodule
1333
 
1334 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1335
////                                                              ////
1336
////  IO functions                                                ////
1337
////                                                              ////
1338
////  Description                                                 ////
1339
////  IO functions such as IOB flip-flops                         ////
1340
////                                                              ////
1341
////                                                              ////
1342
////  To Do:                                                      ////
1343
////   -                                                          ////
1344
////                                                              ////
1345
////  Author(s):                                                  ////
1346
////      - Michael Unneback, unneback@opencores.org              ////
1347
////        ORSoC AB                                              ////
1348
////                                                              ////
1349 18 unneback
//////////////////////////////////////////////////////////////////////
1350
////                                                              ////
1351 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1352
////                                                              ////
1353
//// This source file may be used and distributed without         ////
1354
//// restriction provided that this copyright statement is not    ////
1355
//// removed from the file and that any derivative work contains  ////
1356
//// the original copyright notice and the associated disclaimer. ////
1357
////                                                              ////
1358
//// This source file is free software; you can redistribute it   ////
1359
//// and/or modify it under the terms of the GNU Lesser General   ////
1360
//// Public License as published by the Free Software Foundation; ////
1361
//// either version 2.1 of the License, or (at your option) any   ////
1362
//// later version.                                               ////
1363
////                                                              ////
1364
//// This source is distributed in the hope that it will be       ////
1365
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1366
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1367
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1368
//// details.                                                     ////
1369
////                                                              ////
1370
//// You should have received a copy of the GNU Lesser General    ////
1371
//// Public License along with this source; if not, download it   ////
1372
//// from http://www.opencores.org/lgpl.shtml                     ////
1373
////                                                              ////
1374
//////////////////////////////////////////////////////////////////////
1375 45 unneback
`timescale 1ns/1ns
1376 44 unneback
`ifdef O_DFF
1377
`define MODULE o_dff
1378
module `BASE`MODULE (d_i, o_pad, clk, rst);
1379
`undef MODULE
1380
parameter width = 1;
1381 45 unneback
parameter reset_value = {width{1'b0}};
1382
input  [width-1:0]  d_i;
1383 44 unneback
output [width-1:0] o_pad;
1384
input clk, rst;
1385
wire [width-1:0] d_i_int `SYN_KEEP;
1386 45 unneback
reg  [width-1:0] o_pad_int;
1387 44 unneback
assign d_i_int = d_i;
1388
genvar i;
1389 45 unneback
generate
1390 44 unneback
for (i=0;i<width;i=i+1) begin
1391
    always @ (posedge clk or posedge rst)
1392
    if (rst)
1393 45 unneback
        o_pad_int[i] <= reset_value[i];
1394 44 unneback
    else
1395 45 unneback
        o_pad_int[i] <= d_i_int[i];
1396
    assign #1 o_pad[i] = o_pad_int[i];
1397 44 unneback
end
1398
endgenerate
1399
endmodule
1400
`endif
1401
 
1402 45 unneback
`timescale 1ns/1ns
1403 44 unneback
`ifdef IO_DFF_OE
1404
`define MODULE io_dff_oe
1405
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1406
`undef MODULE
1407
parameter width = 1;
1408
input  [width-1:0] d_o;
1409
output reg [width-1:0] d_i;
1410
input oe;
1411
inout [width-1:0] io_pad;
1412
input clk, rst;
1413
wire [width-1:0] oe_d `SYN_KEEP;
1414
reg [width-1:0] oe_q;
1415
reg [width-1:0] d_o_q;
1416
assign oe_d = {width{oe}};
1417
genvar i;
1418
generate
1419
for (i=0;i<width;i=i+1) begin
1420
    always @ (posedge clk or posedge rst)
1421
    if (rst)
1422
        oe_q[i] <= 1'b0;
1423
    else
1424
        oe_q[i] <= oe_d[i];
1425
    always @ (posedge clk or posedge rst)
1426
    if (rst)
1427
        d_o_q[i] <= 1'b0;
1428
    else
1429
        d_o_q[i] <= d_o[i];
1430
    always @ (posedge clk or posedge rst)
1431
    if (rst)
1432
        d_i[i] <= 1'b0;
1433
    else
1434
        d_i[i] <= io_pad[i];
1435 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1436 44 unneback
end
1437
endgenerate
1438
endmodule
1439
`endif
1440
`ifdef CNT_BIN
1441
//////////////////////////////////////////////////////////////////////
1442
////                                                              ////
1443 6 unneback
////  Versatile counter                                           ////
1444
////                                                              ////
1445
////  Description                                                 ////
1446
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1447
////  counter                                                     ////
1448
////                                                              ////
1449
////  To Do:                                                      ////
1450
////   - add LFSR with more taps                                  ////
1451
////                                                              ////
1452
////  Author(s):                                                  ////
1453
////      - Michael Unneback, unneback@opencores.org              ////
1454
////        ORSoC AB                                              ////
1455
////                                                              ////
1456
//////////////////////////////////////////////////////////////////////
1457
////                                                              ////
1458
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1459
////                                                              ////
1460
//// This source file may be used and distributed without         ////
1461
//// restriction provided that this copyright statement is not    ////
1462
//// removed from the file and that any derivative work contains  ////
1463
//// the original copyright notice and the associated disclaimer. ////
1464
////                                                              ////
1465
//// This source file is free software; you can redistribute it   ////
1466
//// and/or modify it under the terms of the GNU Lesser General   ////
1467
//// Public License as published by the Free Software Foundation; ////
1468
//// either version 2.1 of the License, or (at your option) any   ////
1469
//// later version.                                               ////
1470
////                                                              ////
1471
//// This source is distributed in the hope that it will be       ////
1472
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1473
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1474
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1475
//// details.                                                     ////
1476
////                                                              ////
1477
//// You should have received a copy of the GNU Lesser General    ////
1478
//// Public License along with this source; if not, download it   ////
1479
//// from http://www.opencores.org/lgpl.shtml                     ////
1480
////                                                              ////
1481
//////////////////////////////////////////////////////////////////////
1482
 
1483
// binary counter
1484 22 unneback
 
1485 40 unneback
`define MODULE cnt_bin
1486
module `BASE`MODULE (
1487
`undef MODULE
1488
 q, rst, clk);
1489
 
1490 22 unneback
   parameter length = 4;
1491
   output [length:1] q;
1492
   input rst;
1493
   input clk;
1494
 
1495
   parameter clear_value = 0;
1496
   parameter set_value = 1;
1497
   parameter wrap_value = 0;
1498
   parameter level1_value = 15;
1499
 
1500
   reg  [length:1] qi;
1501
   wire [length:1] q_next;
1502
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1503
 
1504
   always @ (posedge clk or posedge rst)
1505
     if (rst)
1506
       qi <= {length{1'b0}};
1507
     else
1508
       qi <= q_next;
1509
 
1510
   assign q = qi;
1511
 
1512
endmodule
1513 40 unneback
`endif
1514
`ifdef CNT_BIN_CLEAR
1515 22 unneback
//////////////////////////////////////////////////////////////////////
1516
////                                                              ////
1517
////  Versatile counter                                           ////
1518
////                                                              ////
1519
////  Description                                                 ////
1520
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1521
////  counter                                                     ////
1522
////                                                              ////
1523
////  To Do:                                                      ////
1524
////   - add LFSR with more taps                                  ////
1525
////                                                              ////
1526
////  Author(s):                                                  ////
1527
////      - Michael Unneback, unneback@opencores.org              ////
1528
////        ORSoC AB                                              ////
1529
////                                                              ////
1530
//////////////////////////////////////////////////////////////////////
1531
////                                                              ////
1532
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1533
////                                                              ////
1534
//// This source file may be used and distributed without         ////
1535
//// restriction provided that this copyright statement is not    ////
1536
//// removed from the file and that any derivative work contains  ////
1537
//// the original copyright notice and the associated disclaimer. ////
1538
////                                                              ////
1539
//// This source file is free software; you can redistribute it   ////
1540
//// and/or modify it under the terms of the GNU Lesser General   ////
1541
//// Public License as published by the Free Software Foundation; ////
1542
//// either version 2.1 of the License, or (at your option) any   ////
1543
//// later version.                                               ////
1544
////                                                              ////
1545
//// This source is distributed in the hope that it will be       ////
1546
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1547
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1548
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1549
//// details.                                                     ////
1550
////                                                              ////
1551
//// You should have received a copy of the GNU Lesser General    ////
1552
//// Public License along with this source; if not, download it   ////
1553
//// from http://www.opencores.org/lgpl.shtml                     ////
1554
////                                                              ////
1555
//////////////////////////////////////////////////////////////////////
1556
 
1557
// binary counter
1558
 
1559 40 unneback
`define MODULE cnt_bin_clear
1560
module `BASE`MODULE (
1561
`undef MODULE
1562
 clear, q, rst, clk);
1563
 
1564 22 unneback
   parameter length = 4;
1565
   input clear;
1566
   output [length:1] q;
1567
   input rst;
1568
   input clk;
1569
 
1570
   parameter clear_value = 0;
1571
   parameter set_value = 1;
1572
   parameter wrap_value = 0;
1573
   parameter level1_value = 15;
1574
 
1575
   reg  [length:1] qi;
1576
   wire [length:1] q_next;
1577
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1578
 
1579
   always @ (posedge clk or posedge rst)
1580
     if (rst)
1581
       qi <= {length{1'b0}};
1582
     else
1583
       qi <= q_next;
1584
 
1585
   assign q = qi;
1586
 
1587
endmodule
1588 40 unneback
`endif
1589
`ifdef CNT_BIN_CE
1590 22 unneback
//////////////////////////////////////////////////////////////////////
1591
////                                                              ////
1592
////  Versatile counter                                           ////
1593
////                                                              ////
1594
////  Description                                                 ////
1595
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1596
////  counter                                                     ////
1597
////                                                              ////
1598
////  To Do:                                                      ////
1599
////   - add LFSR with more taps                                  ////
1600
////                                                              ////
1601
////  Author(s):                                                  ////
1602
////      - Michael Unneback, unneback@opencores.org              ////
1603
////        ORSoC AB                                              ////
1604
////                                                              ////
1605
//////////////////////////////////////////////////////////////////////
1606
////                                                              ////
1607
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1608
////                                                              ////
1609
//// This source file may be used and distributed without         ////
1610
//// restriction provided that this copyright statement is not    ////
1611
//// removed from the file and that any derivative work contains  ////
1612
//// the original copyright notice and the associated disclaimer. ////
1613
////                                                              ////
1614
//// This source file is free software; you can redistribute it   ////
1615
//// and/or modify it under the terms of the GNU Lesser General   ////
1616
//// Public License as published by the Free Software Foundation; ////
1617
//// either version 2.1 of the License, or (at your option) any   ////
1618
//// later version.                                               ////
1619
////                                                              ////
1620
//// This source is distributed in the hope that it will be       ////
1621
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1622
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1623
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1624
//// details.                                                     ////
1625
////                                                              ////
1626
//// You should have received a copy of the GNU Lesser General    ////
1627
//// Public License along with this source; if not, download it   ////
1628
//// from http://www.opencores.org/lgpl.shtml                     ////
1629
////                                                              ////
1630
//////////////////////////////////////////////////////////////////////
1631
 
1632
// binary counter
1633 6 unneback
 
1634 40 unneback
`define MODULE cnt_bin_ce
1635
module `BASE`MODULE (
1636
`undef MODULE
1637
 cke, q, rst, clk);
1638
 
1639 6 unneback
   parameter length = 4;
1640
   input cke;
1641
   output [length:1] q;
1642
   input rst;
1643
   input clk;
1644
 
1645
   parameter clear_value = 0;
1646
   parameter set_value = 1;
1647
   parameter wrap_value = 0;
1648
   parameter level1_value = 15;
1649
 
1650
   reg  [length:1] qi;
1651
   wire [length:1] q_next;
1652
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1653
 
1654
   always @ (posedge clk or posedge rst)
1655
     if (rst)
1656
       qi <= {length{1'b0}};
1657
     else
1658
     if (cke)
1659
       qi <= q_next;
1660
 
1661
   assign q = qi;
1662
 
1663
endmodule
1664 40 unneback
`endif
1665
`ifdef CNT_BIN_CE_CLEAR
1666 6 unneback
//////////////////////////////////////////////////////////////////////
1667
////                                                              ////
1668
////  Versatile counter                                           ////
1669
////                                                              ////
1670
////  Description                                                 ////
1671
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1672
////  counter                                                     ////
1673
////                                                              ////
1674
////  To Do:                                                      ////
1675
////   - add LFSR with more taps                                  ////
1676
////                                                              ////
1677
////  Author(s):                                                  ////
1678
////      - Michael Unneback, unneback@opencores.org              ////
1679
////        ORSoC AB                                              ////
1680
////                                                              ////
1681
//////////////////////////////////////////////////////////////////////
1682
////                                                              ////
1683
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1684
////                                                              ////
1685
//// This source file may be used and distributed without         ////
1686
//// restriction provided that this copyright statement is not    ////
1687
//// removed from the file and that any derivative work contains  ////
1688
//// the original copyright notice and the associated disclaimer. ////
1689
////                                                              ////
1690
//// This source file is free software; you can redistribute it   ////
1691
//// and/or modify it under the terms of the GNU Lesser General   ////
1692
//// Public License as published by the Free Software Foundation; ////
1693
//// either version 2.1 of the License, or (at your option) any   ////
1694
//// later version.                                               ////
1695
////                                                              ////
1696
//// This source is distributed in the hope that it will be       ////
1697
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1698
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1699
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1700
//// details.                                                     ////
1701
////                                                              ////
1702
//// You should have received a copy of the GNU Lesser General    ////
1703
//// Public License along with this source; if not, download it   ////
1704
//// from http://www.opencores.org/lgpl.shtml                     ////
1705
////                                                              ////
1706
//////////////////////////////////////////////////////////////////////
1707
 
1708
// binary counter
1709
 
1710 40 unneback
`define MODULE cnt_bin_ce_clear
1711
module `BASE`MODULE (
1712
`undef MODULE
1713
 clear, cke, q, rst, clk);
1714
 
1715 6 unneback
   parameter length = 4;
1716
   input clear;
1717
   input cke;
1718
   output [length:1] q;
1719
   input rst;
1720
   input clk;
1721
 
1722
   parameter clear_value = 0;
1723
   parameter set_value = 1;
1724
   parameter wrap_value = 0;
1725
   parameter level1_value = 15;
1726
 
1727
   reg  [length:1] qi;
1728
   wire [length:1] q_next;
1729
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1730
 
1731
   always @ (posedge clk or posedge rst)
1732
     if (rst)
1733
       qi <= {length{1'b0}};
1734
     else
1735
     if (cke)
1736
       qi <= q_next;
1737
 
1738
   assign q = qi;
1739
 
1740
endmodule
1741 40 unneback
`endif
1742
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1743 6 unneback
//////////////////////////////////////////////////////////////////////
1744
////                                                              ////
1745
////  Versatile counter                                           ////
1746
////                                                              ////
1747
////  Description                                                 ////
1748
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1749
////  counter                                                     ////
1750
////                                                              ////
1751
////  To Do:                                                      ////
1752
////   - add LFSR with more taps                                  ////
1753
////                                                              ////
1754
////  Author(s):                                                  ////
1755
////      - Michael Unneback, unneback@opencores.org              ////
1756
////        ORSoC AB                                              ////
1757
////                                                              ////
1758
//////////////////////////////////////////////////////////////////////
1759
////                                                              ////
1760
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1761
////                                                              ////
1762
//// This source file may be used and distributed without         ////
1763
//// restriction provided that this copyright statement is not    ////
1764
//// removed from the file and that any derivative work contains  ////
1765
//// the original copyright notice and the associated disclaimer. ////
1766
////                                                              ////
1767
//// This source file is free software; you can redistribute it   ////
1768
//// and/or modify it under the terms of the GNU Lesser General   ////
1769
//// Public License as published by the Free Software Foundation; ////
1770
//// either version 2.1 of the License, or (at your option) any   ////
1771
//// later version.                                               ////
1772
////                                                              ////
1773
//// This source is distributed in the hope that it will be       ////
1774
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1775
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1776
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1777
//// details.                                                     ////
1778
////                                                              ////
1779
//// You should have received a copy of the GNU Lesser General    ////
1780
//// Public License along with this source; if not, download it   ////
1781
//// from http://www.opencores.org/lgpl.shtml                     ////
1782
////                                                              ////
1783
//////////////////////////////////////////////////////////////////////
1784
 
1785
// binary counter
1786 29 unneback
 
1787 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1788
module `BASE`MODULE (
1789
`undef MODULE
1790
 clear, cke, q, level1, level2, rst, clk);
1791
 
1792 29 unneback
   parameter length = 4;
1793
   input clear;
1794
   input cke;
1795
   output [length:1] q;
1796
   output reg level1;
1797
   output reg level2;
1798
   input rst;
1799
   input clk;
1800
 
1801
   parameter clear_value = 0;
1802
   parameter set_value = 1;
1803 30 unneback
   parameter wrap_value = 15;
1804
   parameter level1_value = 8;
1805
   parameter level2_value = 15;
1806 29 unneback
 
1807
   wire rew;
1808 30 unneback
   assign rew = 1'b0;
1809 29 unneback
   reg  [length:1] qi;
1810
   wire [length:1] q_next;
1811
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1812
 
1813
   always @ (posedge clk or posedge rst)
1814
     if (rst)
1815
       qi <= {length{1'b0}};
1816
     else
1817
     if (cke)
1818
       qi <= q_next;
1819
 
1820
   assign q = qi;
1821
 
1822
 
1823
    always @ (posedge clk or posedge rst)
1824
    if (rst)
1825
        level1 <= 1'b0;
1826
    else
1827
    if (cke)
1828
    if (clear)
1829
        level1 <= 1'b0;
1830
    else if (q_next == level1_value)
1831
        level1 <= 1'b1;
1832
    else if (qi == level1_value & rew)
1833
        level1 <= 1'b0;
1834
 
1835
    always @ (posedge clk or posedge rst)
1836
    if (rst)
1837
        level2 <= 1'b0;
1838
    else
1839
    if (cke)
1840
    if (clear)
1841
        level2 <= 1'b0;
1842
    else if (q_next == level2_value)
1843
        level2 <= 1'b1;
1844
    else if (qi == level2_value & rew)
1845
        level2 <= 1'b0;
1846
endmodule
1847 40 unneback
`endif
1848
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1849 29 unneback
//////////////////////////////////////////////////////////////////////
1850
////                                                              ////
1851
////  Versatile counter                                           ////
1852
////                                                              ////
1853
////  Description                                                 ////
1854
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1855
////  counter                                                     ////
1856
////                                                              ////
1857
////  To Do:                                                      ////
1858
////   - add LFSR with more taps                                  ////
1859
////                                                              ////
1860
////  Author(s):                                                  ////
1861
////      - Michael Unneback, unneback@opencores.org              ////
1862
////        ORSoC AB                                              ////
1863
////                                                              ////
1864
//////////////////////////////////////////////////////////////////////
1865
////                                                              ////
1866
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1867
////                                                              ////
1868
//// This source file may be used and distributed without         ////
1869
//// restriction provided that this copyright statement is not    ////
1870
//// removed from the file and that any derivative work contains  ////
1871
//// the original copyright notice and the associated disclaimer. ////
1872
////                                                              ////
1873
//// This source file is free software; you can redistribute it   ////
1874
//// and/or modify it under the terms of the GNU Lesser General   ////
1875
//// Public License as published by the Free Software Foundation; ////
1876
//// either version 2.1 of the License, or (at your option) any   ////
1877
//// later version.                                               ////
1878
////                                                              ////
1879
//// This source is distributed in the hope that it will be       ////
1880
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1881
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1882
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1883
//// details.                                                     ////
1884
////                                                              ////
1885
//// You should have received a copy of the GNU Lesser General    ////
1886
//// Public License along with this source; if not, download it   ////
1887
//// from http://www.opencores.org/lgpl.shtml                     ////
1888
////                                                              ////
1889
//////////////////////////////////////////////////////////////////////
1890
 
1891
// binary counter
1892 6 unneback
 
1893 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1894
module `BASE`MODULE (
1895
`undef MODULE
1896
 clear, set, cke, rew, q, rst, clk);
1897
 
1898 6 unneback
   parameter length = 4;
1899
   input clear;
1900
   input set;
1901
   input cke;
1902
   input rew;
1903
   output [length:1] q;
1904
   input rst;
1905
   input clk;
1906
 
1907
   parameter clear_value = 0;
1908
   parameter set_value = 1;
1909
   parameter wrap_value = 0;
1910
   parameter level1_value = 15;
1911
 
1912
   reg  [length:1] qi;
1913
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1914
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1915
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1916
   assign q_next = rew ? q_next_rew : q_next_fw;
1917
 
1918
   always @ (posedge clk or posedge rst)
1919
     if (rst)
1920
       qi <= {length{1'b0}};
1921
     else
1922
     if (cke)
1923
       qi <= q_next;
1924
 
1925
   assign q = qi;
1926
 
1927
endmodule
1928 40 unneback
`endif
1929
`ifdef CNT_BIN_CE_REW_L1
1930 6 unneback
//////////////////////////////////////////////////////////////////////
1931
////                                                              ////
1932
////  Versatile counter                                           ////
1933
////                                                              ////
1934
////  Description                                                 ////
1935
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1936
////  counter                                                     ////
1937
////                                                              ////
1938
////  To Do:                                                      ////
1939
////   - add LFSR with more taps                                  ////
1940
////                                                              ////
1941
////  Author(s):                                                  ////
1942
////      - Michael Unneback, unneback@opencores.org              ////
1943
////        ORSoC AB                                              ////
1944
////                                                              ////
1945
//////////////////////////////////////////////////////////////////////
1946
////                                                              ////
1947
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1948
////                                                              ////
1949
//// This source file may be used and distributed without         ////
1950
//// restriction provided that this copyright statement is not    ////
1951
//// removed from the file and that any derivative work contains  ////
1952
//// the original copyright notice and the associated disclaimer. ////
1953
////                                                              ////
1954
//// This source file is free software; you can redistribute it   ////
1955
//// and/or modify it under the terms of the GNU Lesser General   ////
1956
//// Public License as published by the Free Software Foundation; ////
1957
//// either version 2.1 of the License, or (at your option) any   ////
1958
//// later version.                                               ////
1959
////                                                              ////
1960
//// This source is distributed in the hope that it will be       ////
1961
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1962
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1963
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1964
//// details.                                                     ////
1965
////                                                              ////
1966
//// You should have received a copy of the GNU Lesser General    ////
1967
//// Public License along with this source; if not, download it   ////
1968
//// from http://www.opencores.org/lgpl.shtml                     ////
1969
////                                                              ////
1970
//////////////////////////////////////////////////////////////////////
1971
 
1972
// binary counter
1973
 
1974 40 unneback
`define MODULE cnt_bin_ce_rew_l1
1975
module `BASE`MODULE (
1976
`undef MODULE
1977
 cke, rew, level1, rst, clk);
1978
 
1979 6 unneback
   parameter length = 4;
1980
   input cke;
1981
   input rew;
1982
   output reg level1;
1983
   input rst;
1984
   input clk;
1985
 
1986
   parameter clear_value = 0;
1987
   parameter set_value = 1;
1988
   parameter wrap_value = 1;
1989
   parameter level1_value = 15;
1990
 
1991 29 unneback
   wire clear;
1992 30 unneback
   assign clear = 1'b0;
1993 6 unneback
   reg  [length:1] qi;
1994
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1995
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1996
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1997
   assign q_next = rew ? q_next_rew : q_next_fw;
1998
 
1999
   always @ (posedge clk or posedge rst)
2000
     if (rst)
2001
       qi <= {length{1'b0}};
2002
     else
2003
     if (cke)
2004
       qi <= q_next;
2005
 
2006
 
2007
 
2008
    always @ (posedge clk or posedge rst)
2009
    if (rst)
2010
        level1 <= 1'b0;
2011
    else
2012
    if (cke)
2013 29 unneback
    if (clear)
2014
        level1 <= 1'b0;
2015
    else if (q_next == level1_value)
2016 6 unneback
        level1 <= 1'b1;
2017
    else if (qi == level1_value & rew)
2018
        level1 <= 1'b0;
2019
endmodule
2020 40 unneback
`endif
2021
`ifdef CNT_BIN_CE_REW_ZQ_L1
2022 6 unneback
//////////////////////////////////////////////////////////////////////
2023
////                                                              ////
2024
////  Versatile counter                                           ////
2025
////                                                              ////
2026
////  Description                                                 ////
2027
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2028
////  counter                                                     ////
2029
////                                                              ////
2030
////  To Do:                                                      ////
2031
////   - add LFSR with more taps                                  ////
2032
////                                                              ////
2033
////  Author(s):                                                  ////
2034
////      - Michael Unneback, unneback@opencores.org              ////
2035
////        ORSoC AB                                              ////
2036
////                                                              ////
2037
//////////////////////////////////////////////////////////////////////
2038
////                                                              ////
2039
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2040
////                                                              ////
2041
//// This source file may be used and distributed without         ////
2042
//// restriction provided that this copyright statement is not    ////
2043
//// removed from the file and that any derivative work contains  ////
2044
//// the original copyright notice and the associated disclaimer. ////
2045
////                                                              ////
2046
//// This source file is free software; you can redistribute it   ////
2047
//// and/or modify it under the terms of the GNU Lesser General   ////
2048
//// Public License as published by the Free Software Foundation; ////
2049
//// either version 2.1 of the License, or (at your option) any   ////
2050
//// later version.                                               ////
2051
////                                                              ////
2052
//// This source is distributed in the hope that it will be       ////
2053
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2054
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2055
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2056
//// details.                                                     ////
2057
////                                                              ////
2058
//// You should have received a copy of the GNU Lesser General    ////
2059
//// Public License along with this source; if not, download it   ////
2060
//// from http://www.opencores.org/lgpl.shtml                     ////
2061
////                                                              ////
2062
//////////////////////////////////////////////////////////////////////
2063
 
2064 25 unneback
// binary counter
2065
 
2066 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2067
module `BASE`MODULE (
2068
`undef MODULE
2069
 cke, rew, zq, level1, rst, clk);
2070
 
2071 25 unneback
   parameter length = 4;
2072
   input cke;
2073
   input rew;
2074
   output reg zq;
2075
   output reg level1;
2076
   input rst;
2077
   input clk;
2078
 
2079
   parameter clear_value = 0;
2080
   parameter set_value = 1;
2081
   parameter wrap_value = 1;
2082
   parameter level1_value = 15;
2083
 
2084 29 unneback
   wire clear;
2085 30 unneback
   assign clear = 1'b0;
2086 25 unneback
   reg  [length:1] qi;
2087
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2088
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2089
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2090
   assign q_next = rew ? q_next_rew : q_next_fw;
2091
 
2092
   always @ (posedge clk or posedge rst)
2093
     if (rst)
2094
       qi <= {length{1'b0}};
2095
     else
2096
     if (cke)
2097
       qi <= q_next;
2098
 
2099
 
2100
 
2101
   always @ (posedge clk or posedge rst)
2102
     if (rst)
2103
       zq <= 1'b1;
2104
     else
2105
     if (cke)
2106
       zq <= q_next == {length{1'b0}};
2107
 
2108
    always @ (posedge clk or posedge rst)
2109
    if (rst)
2110
        level1 <= 1'b0;
2111
    else
2112
    if (cke)
2113 29 unneback
    if (clear)
2114
        level1 <= 1'b0;
2115
    else if (q_next == level1_value)
2116 25 unneback
        level1 <= 1'b1;
2117
    else if (qi == level1_value & rew)
2118
        level1 <= 1'b0;
2119
endmodule
2120 40 unneback
`endif
2121
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2122 25 unneback
//////////////////////////////////////////////////////////////////////
2123
////                                                              ////
2124
////  Versatile counter                                           ////
2125
////                                                              ////
2126
////  Description                                                 ////
2127
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2128
////  counter                                                     ////
2129
////                                                              ////
2130
////  To Do:                                                      ////
2131
////   - add LFSR with more taps                                  ////
2132
////                                                              ////
2133
////  Author(s):                                                  ////
2134
////      - Michael Unneback, unneback@opencores.org              ////
2135
////        ORSoC AB                                              ////
2136
////                                                              ////
2137
//////////////////////////////////////////////////////////////////////
2138
////                                                              ////
2139
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2140
////                                                              ////
2141
//// This source file may be used and distributed without         ////
2142
//// restriction provided that this copyright statement is not    ////
2143
//// removed from the file and that any derivative work contains  ////
2144
//// the original copyright notice and the associated disclaimer. ////
2145
////                                                              ////
2146
//// This source file is free software; you can redistribute it   ////
2147
//// and/or modify it under the terms of the GNU Lesser General   ////
2148
//// Public License as published by the Free Software Foundation; ////
2149
//// either version 2.1 of the License, or (at your option) any   ////
2150
//// later version.                                               ////
2151
////                                                              ////
2152
//// This source is distributed in the hope that it will be       ////
2153
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2154
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2155
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2156
//// details.                                                     ////
2157
////                                                              ////
2158
//// You should have received a copy of the GNU Lesser General    ////
2159
//// Public License along with this source; if not, download it   ////
2160
//// from http://www.opencores.org/lgpl.shtml                     ////
2161
////                                                              ////
2162
//////////////////////////////////////////////////////////////////////
2163
 
2164
// binary counter
2165
 
2166 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2167
module `BASE`MODULE (
2168
`undef MODULE
2169
 cke, rew, q, zq, level1, rst, clk);
2170
 
2171 25 unneback
   parameter length = 4;
2172
   input cke;
2173
   input rew;
2174
   output [length:1] q;
2175
   output reg zq;
2176
   output reg level1;
2177
   input rst;
2178
   input clk;
2179
 
2180
   parameter clear_value = 0;
2181
   parameter set_value = 1;
2182
   parameter wrap_value = 1;
2183
   parameter level1_value = 15;
2184
 
2185 29 unneback
   wire clear;
2186 30 unneback
   assign clear = 1'b0;
2187 25 unneback
   reg  [length:1] qi;
2188
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2189
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2190
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2191
   assign q_next = rew ? q_next_rew : q_next_fw;
2192
 
2193
   always @ (posedge clk or posedge rst)
2194
     if (rst)
2195
       qi <= {length{1'b0}};
2196
     else
2197
     if (cke)
2198
       qi <= q_next;
2199
 
2200
   assign q = qi;
2201
 
2202
 
2203
   always @ (posedge clk or posedge rst)
2204
     if (rst)
2205
       zq <= 1'b1;
2206
     else
2207
     if (cke)
2208
       zq <= q_next == {length{1'b0}};
2209
 
2210
    always @ (posedge clk or posedge rst)
2211
    if (rst)
2212
        level1 <= 1'b0;
2213
    else
2214
    if (cke)
2215 29 unneback
    if (clear)
2216
        level1 <= 1'b0;
2217
    else if (q_next == level1_value)
2218 25 unneback
        level1 <= 1'b1;
2219
    else if (qi == level1_value & rew)
2220
        level1 <= 1'b0;
2221
endmodule
2222 40 unneback
`endif
2223
`ifdef CNT_LFSR_ZQ
2224 25 unneback
//////////////////////////////////////////////////////////////////////
2225
////                                                              ////
2226
////  Versatile counter                                           ////
2227
////                                                              ////
2228
////  Description                                                 ////
2229
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2230
////  counter                                                     ////
2231
////                                                              ////
2232
////  To Do:                                                      ////
2233
////   - add LFSR with more taps                                  ////
2234
////                                                              ////
2235
////  Author(s):                                                  ////
2236
////      - Michael Unneback, unneback@opencores.org              ////
2237
////        ORSoC AB                                              ////
2238
////                                                              ////
2239
//////////////////////////////////////////////////////////////////////
2240
////                                                              ////
2241
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2242
////                                                              ////
2243
//// This source file may be used and distributed without         ////
2244
//// restriction provided that this copyright statement is not    ////
2245
//// removed from the file and that any derivative work contains  ////
2246
//// the original copyright notice and the associated disclaimer. ////
2247
////                                                              ////
2248
//// This source file is free software; you can redistribute it   ////
2249
//// and/or modify it under the terms of the GNU Lesser General   ////
2250
//// Public License as published by the Free Software Foundation; ////
2251
//// either version 2.1 of the License, or (at your option) any   ////
2252
//// later version.                                               ////
2253
////                                                              ////
2254
//// This source is distributed in the hope that it will be       ////
2255
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2256
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2257
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2258
//// details.                                                     ////
2259
////                                                              ////
2260
//// You should have received a copy of the GNU Lesser General    ////
2261
//// Public License along with this source; if not, download it   ////
2262
//// from http://www.opencores.org/lgpl.shtml                     ////
2263
////                                                              ////
2264
//////////////////////////////////////////////////////////////////////
2265
 
2266 6 unneback
// LFSR counter
2267
 
2268 40 unneback
`define MODULE cnt_lfsr_zq
2269
module `BASE`MODULE (
2270
`undef MODULE
2271
 zq, rst, clk);
2272
 
2273 6 unneback
   parameter length = 4;
2274
   output reg zq;
2275
   input rst;
2276
   input clk;
2277
 
2278
   parameter clear_value = 0;
2279
   parameter set_value = 1;
2280
   parameter wrap_value = 8;
2281
   parameter level1_value = 15;
2282
 
2283
   reg  [length:1] qi;
2284
   reg lfsr_fb;
2285
   wire [length:1] q_next;
2286
   reg [32:1] polynom;
2287
   integer i;
2288
 
2289
   always @ (qi)
2290
   begin
2291
        case (length)
2292
         2: polynom = 32'b11;                               // 0x3
2293
         3: polynom = 32'b110;                              // 0x6
2294
         4: polynom = 32'b1100;                             // 0xC
2295
         5: polynom = 32'b10100;                            // 0x14
2296
         6: polynom = 32'b110000;                           // 0x30
2297
         7: polynom = 32'b1100000;                          // 0x60
2298
         8: polynom = 32'b10111000;                         // 0xb8
2299
         9: polynom = 32'b100010000;                        // 0x110
2300
        10: polynom = 32'b1001000000;                       // 0x240
2301
        11: polynom = 32'b10100000000;                      // 0x500
2302
        12: polynom = 32'b100000101001;                     // 0x829
2303
        13: polynom = 32'b1000000001100;                    // 0x100C
2304
        14: polynom = 32'b10000000010101;                   // 0x2015
2305
        15: polynom = 32'b110000000000000;                  // 0x6000
2306
        16: polynom = 32'b1101000000001000;                 // 0xD008
2307
        17: polynom = 32'b10010000000000000;                // 0x12000
2308
        18: polynom = 32'b100000010000000000;               // 0x20400
2309
        19: polynom = 32'b1000000000000100011;              // 0x40023
2310 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2311 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2312
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2313
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2314
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2315
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2316
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2317
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2318
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2319
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2320
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2321
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2322
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2323
        default: polynom = 32'b0;
2324
        endcase
2325
        lfsr_fb = qi[length];
2326
        for (i=length-1; i>=1; i=i-1) begin
2327
            if (polynom[i])
2328
                lfsr_fb = lfsr_fb  ~^ qi[i];
2329
        end
2330
    end
2331
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2332
 
2333
   always @ (posedge clk or posedge rst)
2334
     if (rst)
2335
       qi <= {length{1'b0}};
2336
     else
2337
       qi <= q_next;
2338
 
2339
 
2340
 
2341
   always @ (posedge clk or posedge rst)
2342
     if (rst)
2343
       zq <= 1'b1;
2344
     else
2345
       zq <= q_next == {length{1'b0}};
2346
endmodule
2347 40 unneback
`endif
2348
`ifdef CNT_LFSR_CE_ZQ
2349 6 unneback
//////////////////////////////////////////////////////////////////////
2350
////                                                              ////
2351
////  Versatile counter                                           ////
2352
////                                                              ////
2353
////  Description                                                 ////
2354
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2355
////  counter                                                     ////
2356
////                                                              ////
2357
////  To Do:                                                      ////
2358
////   - add LFSR with more taps                                  ////
2359
////                                                              ////
2360
////  Author(s):                                                  ////
2361
////      - Michael Unneback, unneback@opencores.org              ////
2362
////        ORSoC AB                                              ////
2363
////                                                              ////
2364
//////////////////////////////////////////////////////////////////////
2365
////                                                              ////
2366
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2367
////                                                              ////
2368
//// This source file may be used and distributed without         ////
2369
//// restriction provided that this copyright statement is not    ////
2370
//// removed from the file and that any derivative work contains  ////
2371
//// the original copyright notice and the associated disclaimer. ////
2372
////                                                              ////
2373
//// This source file is free software; you can redistribute it   ////
2374
//// and/or modify it under the terms of the GNU Lesser General   ////
2375
//// Public License as published by the Free Software Foundation; ////
2376
//// either version 2.1 of the License, or (at your option) any   ////
2377
//// later version.                                               ////
2378
////                                                              ////
2379
//// This source is distributed in the hope that it will be       ////
2380
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2381
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2382
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2383
//// details.                                                     ////
2384
////                                                              ////
2385
//// You should have received a copy of the GNU Lesser General    ////
2386
//// Public License along with this source; if not, download it   ////
2387
//// from http://www.opencores.org/lgpl.shtml                     ////
2388
////                                                              ////
2389
//////////////////////////////////////////////////////////////////////
2390
 
2391
// LFSR counter
2392
 
2393 40 unneback
`define MODULE cnt_lfsr_ce_zq
2394
module `BASE`MODULE (
2395
`undef MODULE
2396
 cke, zq, rst, clk);
2397
 
2398 6 unneback
   parameter length = 4;
2399
   input cke;
2400
   output reg zq;
2401
   input rst;
2402
   input clk;
2403
 
2404
   parameter clear_value = 0;
2405
   parameter set_value = 1;
2406
   parameter wrap_value = 8;
2407
   parameter level1_value = 15;
2408
 
2409
   reg  [length:1] qi;
2410
   reg lfsr_fb;
2411
   wire [length:1] q_next;
2412
   reg [32:1] polynom;
2413
   integer i;
2414
 
2415
   always @ (qi)
2416
   begin
2417
        case (length)
2418
         2: polynom = 32'b11;                               // 0x3
2419
         3: polynom = 32'b110;                              // 0x6
2420
         4: polynom = 32'b1100;                             // 0xC
2421
         5: polynom = 32'b10100;                            // 0x14
2422
         6: polynom = 32'b110000;                           // 0x30
2423
         7: polynom = 32'b1100000;                          // 0x60
2424
         8: polynom = 32'b10111000;                         // 0xb8
2425
         9: polynom = 32'b100010000;                        // 0x110
2426
        10: polynom = 32'b1001000000;                       // 0x240
2427
        11: polynom = 32'b10100000000;                      // 0x500
2428
        12: polynom = 32'b100000101001;                     // 0x829
2429
        13: polynom = 32'b1000000001100;                    // 0x100C
2430
        14: polynom = 32'b10000000010101;                   // 0x2015
2431
        15: polynom = 32'b110000000000000;                  // 0x6000
2432
        16: polynom = 32'b1101000000001000;                 // 0xD008
2433
        17: polynom = 32'b10010000000000000;                // 0x12000
2434
        18: polynom = 32'b100000010000000000;               // 0x20400
2435
        19: polynom = 32'b1000000000000100011;              // 0x40023
2436 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2437 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2438
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2439
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2440
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2441
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2442
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2443
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2444
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2445
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2446
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2447
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2448
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2449
        default: polynom = 32'b0;
2450
        endcase
2451
        lfsr_fb = qi[length];
2452
        for (i=length-1; i>=1; i=i-1) begin
2453
            if (polynom[i])
2454
                lfsr_fb = lfsr_fb  ~^ qi[i];
2455
        end
2456
    end
2457
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2458
 
2459
   always @ (posedge clk or posedge rst)
2460
     if (rst)
2461
       qi <= {length{1'b0}};
2462
     else
2463
     if (cke)
2464
       qi <= q_next;
2465
 
2466
 
2467
 
2468
   always @ (posedge clk or posedge rst)
2469
     if (rst)
2470
       zq <= 1'b1;
2471
     else
2472
     if (cke)
2473
       zq <= q_next == {length{1'b0}};
2474
endmodule
2475 40 unneback
`endif
2476
`ifdef CNT_LFSR_CE_Q
2477 6 unneback
//////////////////////////////////////////////////////////////////////
2478
////                                                              ////
2479
////  Versatile counter                                           ////
2480
////                                                              ////
2481
////  Description                                                 ////
2482
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2483
////  counter                                                     ////
2484
////                                                              ////
2485
////  To Do:                                                      ////
2486
////   - add LFSR with more taps                                  ////
2487
////                                                              ////
2488
////  Author(s):                                                  ////
2489
////      - Michael Unneback, unneback@opencores.org              ////
2490
////        ORSoC AB                                              ////
2491
////                                                              ////
2492
//////////////////////////////////////////////////////////////////////
2493
////                                                              ////
2494
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2495
////                                                              ////
2496
//// This source file may be used and distributed without         ////
2497
//// restriction provided that this copyright statement is not    ////
2498
//// removed from the file and that any derivative work contains  ////
2499
//// the original copyright notice and the associated disclaimer. ////
2500
////                                                              ////
2501
//// This source file is free software; you can redistribute it   ////
2502
//// and/or modify it under the terms of the GNU Lesser General   ////
2503
//// Public License as published by the Free Software Foundation; ////
2504
//// either version 2.1 of the License, or (at your option) any   ////
2505
//// later version.                                               ////
2506
////                                                              ////
2507
//// This source is distributed in the hope that it will be       ////
2508
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2509
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2510
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2511
//// details.                                                     ////
2512
////                                                              ////
2513
//// You should have received a copy of the GNU Lesser General    ////
2514
//// Public License along with this source; if not, download it   ////
2515
//// from http://www.opencores.org/lgpl.shtml                     ////
2516
////                                                              ////
2517
//////////////////////////////////////////////////////////////////////
2518 22 unneback
 
2519
// LFSR counter
2520 27 unneback
 
2521 40 unneback
`define MODULE cnt_lfsr_ce_q
2522
module `BASE`MODULE (
2523
`undef MODULE
2524
 cke, q, rst, clk);
2525
 
2526 27 unneback
   parameter length = 4;
2527
   input cke;
2528
   output [length:1] q;
2529
   input rst;
2530
   input clk;
2531
 
2532
   parameter clear_value = 0;
2533
   parameter set_value = 1;
2534
   parameter wrap_value = 8;
2535
   parameter level1_value = 15;
2536
 
2537
   reg  [length:1] qi;
2538
   reg lfsr_fb;
2539
   wire [length:1] q_next;
2540
   reg [32:1] polynom;
2541
   integer i;
2542
 
2543
   always @ (qi)
2544
   begin
2545
        case (length)
2546
         2: polynom = 32'b11;                               // 0x3
2547
         3: polynom = 32'b110;                              // 0x6
2548
         4: polynom = 32'b1100;                             // 0xC
2549
         5: polynom = 32'b10100;                            // 0x14
2550
         6: polynom = 32'b110000;                           // 0x30
2551
         7: polynom = 32'b1100000;                          // 0x60
2552
         8: polynom = 32'b10111000;                         // 0xb8
2553
         9: polynom = 32'b100010000;                        // 0x110
2554
        10: polynom = 32'b1001000000;                       // 0x240
2555
        11: polynom = 32'b10100000000;                      // 0x500
2556
        12: polynom = 32'b100000101001;                     // 0x829
2557
        13: polynom = 32'b1000000001100;                    // 0x100C
2558
        14: polynom = 32'b10000000010101;                   // 0x2015
2559
        15: polynom = 32'b110000000000000;                  // 0x6000
2560
        16: polynom = 32'b1101000000001000;                 // 0xD008
2561
        17: polynom = 32'b10010000000000000;                // 0x12000
2562
        18: polynom = 32'b100000010000000000;               // 0x20400
2563
        19: polynom = 32'b1000000000000100011;              // 0x40023
2564 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2565 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2566
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2567
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2568
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2569
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2570
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2571
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2572
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2573
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2574
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2575
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2576
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2577
        default: polynom = 32'b0;
2578
        endcase
2579
        lfsr_fb = qi[length];
2580
        for (i=length-1; i>=1; i=i-1) begin
2581
            if (polynom[i])
2582
                lfsr_fb = lfsr_fb  ~^ qi[i];
2583
        end
2584
    end
2585
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2586
 
2587
   always @ (posedge clk or posedge rst)
2588
     if (rst)
2589
       qi <= {length{1'b0}};
2590
     else
2591
     if (cke)
2592
       qi <= q_next;
2593
 
2594
   assign q = qi;
2595
 
2596
endmodule
2597 40 unneback
`endif
2598
`ifdef CNT_LFSR_CE_CLEAR_Q
2599 27 unneback
//////////////////////////////////////////////////////////////////////
2600
////                                                              ////
2601
////  Versatile counter                                           ////
2602
////                                                              ////
2603
////  Description                                                 ////
2604
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2605
////  counter                                                     ////
2606
////                                                              ////
2607
////  To Do:                                                      ////
2608
////   - add LFSR with more taps                                  ////
2609
////                                                              ////
2610
////  Author(s):                                                  ////
2611
////      - Michael Unneback, unneback@opencores.org              ////
2612
////        ORSoC AB                                              ////
2613
////                                                              ////
2614
//////////////////////////////////////////////////////////////////////
2615
////                                                              ////
2616
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2617
////                                                              ////
2618
//// This source file may be used and distributed without         ////
2619
//// restriction provided that this copyright statement is not    ////
2620
//// removed from the file and that any derivative work contains  ////
2621
//// the original copyright notice and the associated disclaimer. ////
2622
////                                                              ////
2623
//// This source file is free software; you can redistribute it   ////
2624
//// and/or modify it under the terms of the GNU Lesser General   ////
2625
//// Public License as published by the Free Software Foundation; ////
2626
//// either version 2.1 of the License, or (at your option) any   ////
2627
//// later version.                                               ////
2628
////                                                              ////
2629
//// This source is distributed in the hope that it will be       ////
2630
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2631
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2632
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2633
//// details.                                                     ////
2634
////                                                              ////
2635
//// You should have received a copy of the GNU Lesser General    ////
2636
//// Public License along with this source; if not, download it   ////
2637
//// from http://www.opencores.org/lgpl.shtml                     ////
2638
////                                                              ////
2639
//////////////////////////////////////////////////////////////////////
2640
 
2641
// LFSR counter
2642
 
2643 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2644
module `BASE`MODULE (
2645
`undef MODULE
2646
 clear, cke, q, rst, clk);
2647
 
2648 27 unneback
   parameter length = 4;
2649
   input clear;
2650
   input cke;
2651
   output [length:1] q;
2652
   input rst;
2653
   input clk;
2654
 
2655
   parameter clear_value = 0;
2656
   parameter set_value = 1;
2657
   parameter wrap_value = 8;
2658
   parameter level1_value = 15;
2659
 
2660
   reg  [length:1] qi;
2661
   reg lfsr_fb;
2662
   wire [length:1] q_next;
2663
   reg [32:1] polynom;
2664
   integer i;
2665
 
2666
   always @ (qi)
2667
   begin
2668
        case (length)
2669
         2: polynom = 32'b11;                               // 0x3
2670
         3: polynom = 32'b110;                              // 0x6
2671
         4: polynom = 32'b1100;                             // 0xC
2672
         5: polynom = 32'b10100;                            // 0x14
2673
         6: polynom = 32'b110000;                           // 0x30
2674
         7: polynom = 32'b1100000;                          // 0x60
2675
         8: polynom = 32'b10111000;                         // 0xb8
2676
         9: polynom = 32'b100010000;                        // 0x110
2677
        10: polynom = 32'b1001000000;                       // 0x240
2678
        11: polynom = 32'b10100000000;                      // 0x500
2679
        12: polynom = 32'b100000101001;                     // 0x829
2680
        13: polynom = 32'b1000000001100;                    // 0x100C
2681
        14: polynom = 32'b10000000010101;                   // 0x2015
2682
        15: polynom = 32'b110000000000000;                  // 0x6000
2683
        16: polynom = 32'b1101000000001000;                 // 0xD008
2684
        17: polynom = 32'b10010000000000000;                // 0x12000
2685
        18: polynom = 32'b100000010000000000;               // 0x20400
2686
        19: polynom = 32'b1000000000000100011;              // 0x40023
2687 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2688 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2689
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2690
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2691
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2692
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2693
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2694
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2695
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2696
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2697
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2698
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2699
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2700
        default: polynom = 32'b0;
2701
        endcase
2702
        lfsr_fb = qi[length];
2703
        for (i=length-1; i>=1; i=i-1) begin
2704
            if (polynom[i])
2705
                lfsr_fb = lfsr_fb  ~^ qi[i];
2706
        end
2707
    end
2708
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2709
 
2710
   always @ (posedge clk or posedge rst)
2711
     if (rst)
2712
       qi <= {length{1'b0}};
2713
     else
2714
     if (cke)
2715
       qi <= q_next;
2716
 
2717
   assign q = qi;
2718
 
2719
endmodule
2720 40 unneback
`endif
2721
`ifdef CNT_LFSR_CE_Q_ZQ
2722 27 unneback
//////////////////////////////////////////////////////////////////////
2723
////                                                              ////
2724
////  Versatile counter                                           ////
2725
////                                                              ////
2726
////  Description                                                 ////
2727
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2728
////  counter                                                     ////
2729
////                                                              ////
2730
////  To Do:                                                      ////
2731
////   - add LFSR with more taps                                  ////
2732
////                                                              ////
2733
////  Author(s):                                                  ////
2734
////      - Michael Unneback, unneback@opencores.org              ////
2735
////        ORSoC AB                                              ////
2736
////                                                              ////
2737
//////////////////////////////////////////////////////////////////////
2738
////                                                              ////
2739
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2740
////                                                              ////
2741
//// This source file may be used and distributed without         ////
2742
//// restriction provided that this copyright statement is not    ////
2743
//// removed from the file and that any derivative work contains  ////
2744
//// the original copyright notice and the associated disclaimer. ////
2745
////                                                              ////
2746
//// This source file is free software; you can redistribute it   ////
2747
//// and/or modify it under the terms of the GNU Lesser General   ////
2748
//// Public License as published by the Free Software Foundation; ////
2749
//// either version 2.1 of the License, or (at your option) any   ////
2750
//// later version.                                               ////
2751
////                                                              ////
2752
//// This source is distributed in the hope that it will be       ////
2753
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2754
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2755
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2756
//// details.                                                     ////
2757
////                                                              ////
2758
//// You should have received a copy of the GNU Lesser General    ////
2759
//// Public License along with this source; if not, download it   ////
2760
//// from http://www.opencores.org/lgpl.shtml                     ////
2761
////                                                              ////
2762
//////////////////////////////////////////////////////////////////////
2763
 
2764
// LFSR counter
2765 22 unneback
 
2766 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
2767
module `BASE`MODULE (
2768
`undef MODULE
2769
 cke, q, zq, rst, clk);
2770
 
2771 22 unneback
   parameter length = 4;
2772
   input cke;
2773
   output [length:1] q;
2774
   output reg zq;
2775
   input rst;
2776
   input clk;
2777
 
2778
   parameter clear_value = 0;
2779
   parameter set_value = 1;
2780
   parameter wrap_value = 8;
2781
   parameter level1_value = 15;
2782
 
2783
   reg  [length:1] qi;
2784
   reg lfsr_fb;
2785
   wire [length:1] q_next;
2786
   reg [32:1] polynom;
2787
   integer i;
2788
 
2789
   always @ (qi)
2790
   begin
2791
        case (length)
2792
         2: polynom = 32'b11;                               // 0x3
2793
         3: polynom = 32'b110;                              // 0x6
2794
         4: polynom = 32'b1100;                             // 0xC
2795
         5: polynom = 32'b10100;                            // 0x14
2796
         6: polynom = 32'b110000;                           // 0x30
2797
         7: polynom = 32'b1100000;                          // 0x60
2798
         8: polynom = 32'b10111000;                         // 0xb8
2799
         9: polynom = 32'b100010000;                        // 0x110
2800
        10: polynom = 32'b1001000000;                       // 0x240
2801
        11: polynom = 32'b10100000000;                      // 0x500
2802
        12: polynom = 32'b100000101001;                     // 0x829
2803
        13: polynom = 32'b1000000001100;                    // 0x100C
2804
        14: polynom = 32'b10000000010101;                   // 0x2015
2805
        15: polynom = 32'b110000000000000;                  // 0x6000
2806
        16: polynom = 32'b1101000000001000;                 // 0xD008
2807