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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
66
`ifdef SIM_GBUF
67
assign o=i;
68
`else
69
gbuf gbuf_i0 ( .CLK(i), .GL(o));
70
`endif
71
endmodule
72
`else
73
`ifdef ALTERA
74
altera
75
`else
76
 
77
`timescale 1 ns/100 ps
78
module vl_gbuf ( i, o);
79
input i;
80
output o;
81
assign o = i;
82
endmodule
83
`endif // ALTERA
84
`endif //ACTEL
85
 
86
// sync reset
87
// input active lo async reset, normally from external reset generetaor and/or switch
88
// output active high global reset sync with two DFFs 
89
`timescale 1 ns/100 ps
90
module vl_sync_rst ( rst_n_i, rst_o, clk);
91
input rst_n_i, clk;
92
output rst_o;
93
reg [0:1] tmp;
94
always @ (posedge clk or negedge rst_n_i)
95
if (!rst_n_i)
96
        tmp <= 2'b00;
97
else
98
        tmp <= {1'b1,tmp[0]};
99
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
100
endmodule
101
 
102
// vl_pll
103
`ifdef ACTEL
104
`timescale 1 ns/100 ps
105
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
106
parameter index = 0;
107
parameter number_of_clk = 1;
108
parameter period_time_0 = 20;
109
parameter period_time_1 = 20;
110
parameter period_time_2 = 20;
111
parameter lock_delay = 2000;
112
input clk_i, rst_n_i;
113
output lock;
114
output reg [0:number_of_clk-1] clk_o;
115
output [0:number_of_clk-1] rst_o;
116
 
117
`ifdef SIM_PLL
118
 
119
always
120
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
121
 
122
generate if (number_of_clk > 1)
123
always
124
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
125
endgenerate
126
 
127
generate if (number_of_clk > 2)
128
always
129
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
130
endgenerate
131
 
132
genvar i;
133
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
134
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
135
end
136
endgenerate
137
 
138
assign #lock_delay lock = rst_n_i;
139
 
140
endmodule
141
`else
142
generate if (number_of_clk==1 & index==0) begin
143
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==1 & index==1) begin
147
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
148
end
149
endgenerate // index==1
150
generate if (number_of_clk==1 & index==2) begin
151
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
152
end
153
endgenerate // index==2
154
generate if (number_of_clk==1 & index==3) begin
155
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
156
end
157
endgenerate // index==0
158
 
159
generate if (number_of_clk==2 & index==0) begin
160
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
161
end
162
endgenerate // index==0
163
generate if (number_of_clk==2 & index==1) begin
164
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
165
end
166
endgenerate // index==1
167
generate if (number_of_clk==2 & index==2) begin
168
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
169
end
170
endgenerate // index==2
171
generate if (number_of_clk==2 & index==3) begin
172
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
173
end
174
endgenerate // index==0
175
 
176
generate if (number_of_clk==3 & index==0) begin
177
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
178
end
179
endgenerate // index==0
180
generate if (number_of_clk==3 & index==1) begin
181
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
182
end
183
endgenerate // index==1
184
generate if (number_of_clk==3 & index==2) begin
185
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
186
end
187
endgenerate // index==2
188
generate if (number_of_clk==3 & index==3) begin
189
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
190
end
191
endgenerate // index==0
192
 
193
genvar i;
194
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
195
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
196
end
197
endgenerate
198
endmodule
199
`endif
200
 
201
`else
202
 
203
`ifdef ALTERA
204
 
205
`else
206
 
207
// generic PLL
208
`timescale 1 ns/100 ps
209
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
210
parameter index = 0;
211
parameter number_of_clk = 1;
212
parameter period_time_0 = 20;
213
parameter period_time_1 = 20;
214
parameter period_time_2 = 20;
215
parameter lock_delay = 2000;
216
input clk_i, rst_n_i;
217
output lock;
218
output reg [0:number_of_clk-1] clk_o;
219
output [0:number_of_clk-1] rst_o;
220
 
221
always
222
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
223
 
224
generate if (number_of_clk > 1)
225
always
226
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
227
endgenerate
228
 
229
generate if (number_of_clk > 2)
230
always
231
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
232
endgenerate
233
 
234
genvar i;
235
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
236
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
237
end
238
endgenerate
239
 
240
assign #lock_delay lock = rst_n_i;
241
 
242
endmodule
243
 
244
`endif //altera
245
`endif //actel//////////////////////////////////////////////////////////////////////
246
////                                                              ////
247
////  Versatile library, registers                                ////
248
////                                                              ////
249
////  Description                                                 ////
250
////  Different type of registers                                 ////
251
////                                                              ////
252
////                                                              ////
253
////  To Do:                                                      ////
254
////   - add more different registers                             ////
255
////                                                              ////
256
////  Author(s):                                                  ////
257
////      - Michael Unneback, unneback@opencores.org              ////
258
////        ORSoC AB                                              ////
259
////                                                              ////
260
//////////////////////////////////////////////////////////////////////
261
////                                                              ////
262
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
263
////                                                              ////
264
//// This source file may be used and distributed without         ////
265
//// restriction provided that this copyright statement is not    ////
266
//// removed from the file and that any derivative work contains  ////
267
//// the original copyright notice and the associated disclaimer. ////
268
////                                                              ////
269
//// This source file is free software; you can redistribute it   ////
270
//// and/or modify it under the terms of the GNU Lesser General   ////
271
//// Public License as published by the Free Software Foundation; ////
272
//// either version 2.1 of the License, or (at your option) any   ////
273
//// later version.                                               ////
274
////                                                              ////
275
//// This source is distributed in the hope that it will be       ////
276
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
277
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
278
//// PURPOSE.  See the GNU Lesser General Public License for more ////
279
//// details.                                                     ////
280
////                                                              ////
281
//// You should have received a copy of the GNU Lesser General    ////
282
//// Public License along with this source; if not, download it   ////
283
//// from http://www.opencores.org/lgpl.shtml                     ////
284
////                                                              ////
285
//////////////////////////////////////////////////////////////////////
286
 
287
module dff ( d, q, clk, rst);
288
 
289
        parameter width = 1;
290
        parameter reset_value = 0;
291
 
292
        input [width-1:0] d;
293
        input clk, rst;
294
        output reg [width-1:0] q;
295
 
296
        always @ (posedge clk or posedge rst)
297
        if (rst)
298
                q <= reset_value;
299
        else
300
                q <= d;
301
 
302
endmodule
303
 
304
module dff_array ( d, q, clk, rst);
305
 
306
        parameter width = 1;
307
        parameter depth = 2;
308
        parameter reset_value = 1'b0;
309
 
310
        input [width-1:0] d;
311
        input clk, rst;
312
        output [width-1:0] q;
313
        reg  [0:depth-1] q_tmp [width-1:0];
314
        integer i;
315
        always @ (posedge clk or posedge rst)
316
        if (rst) begin
317
            for (i=0;i<depth;i=i+1)
318
                q_tmp[i] <= {width{reset_value}};
319
        end else begin
320
            q_tmp[0] <= d;
321
            for (i=1;i<depth;i=i+1)
322
                q_tmp[i] <= q_tmp[i-1];
323
        end
324
 
325
    assign q = q_tmp[depth-1];
326
 
327
endmodule
328
 
329
module dff_ce ( d, ce, q, clk, rst);
330
 
331
        parameter width = 1;
332
        parameter reset_value = 0;
333
 
334
        input [width-1:0] d;
335
        input ce, clk, rst;
336
        output reg [width-1:0] q;
337
 
338
        always @ (posedge clk or posedge rst)
339
        if (rst)
340
                q <= reset_value;
341
        else
342
                if (ce)
343
                        q <= d;
344
 
345
endmodule
346
 
347
`ifdef ALTERA
348
// megafunction wizard: %LPM_FF%
349
// GENERATION: STANDARD
350
// VERSION: WM1.0
351
// MODULE: lpm_ff 
352
 
353
// ============================================================
354
// File Name: dff_sr.v
355
// Megafunction Name(s):
356
//                      lpm_ff
357
//
358
// Simulation Library Files(s):
359
//                      lpm
360
// ============================================================
361
// ************************************************************
362
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
363
//
364
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
365
// ************************************************************
366
 
367
 
368
//Copyright (C) 1991-2010 Altera Corporation
369
//Your use of Altera Corporation's design tools, logic functions 
370
//and other software and tools, and its AMPP partner logic 
371
//functions, and any output files from any of the foregoing 
372
//(including device programming or simulation files), and any 
373
//associated documentation or information are expressly subject 
374
//to the terms and conditions of the Altera Program License 
375
//Subscription Agreement, Altera MegaCore Function License 
376
//Agreement, or other applicable license agreement, including, 
377
//without limitation, that your use is for the sole purpose of 
378
//programming logic devices manufactured by Altera and sold by 
379
//Altera or its authorized distributors.  Please refer to the 
380
//applicable agreement for further details.
381
 
382
 
383
// synopsys translate_off
384
`timescale 1 ps / 1 ps
385
// synopsys translate_on
386
module dff_sr (
387
        aclr,
388
        aset,
389
        clock,
390
        data,
391
        q);
392
 
393
        input     aclr;
394
        input     aset;
395
        input     clock;
396
        input     data;
397
        output    q;
398
 
399
        wire [0:0] sub_wire0;
400
        wire [0:0] sub_wire1 = sub_wire0[0:0];
401
        wire  q = sub_wire1;
402
        wire  sub_wire2 = data;
403
        wire  sub_wire3 = sub_wire2;
404
 
405
        lpm_ff  lpm_ff_component (
406
                                .aclr (aclr),
407
                                .clock (clock),
408
                                .data (sub_wire3),
409
                                .aset (aset),
410
                                .q (sub_wire0)
411
                                // synopsys translate_off
412
                                ,
413
                                .aload (),
414
                                .enable (),
415
                                .sclr (),
416
                                .sload (),
417
                                .sset ()
418
                                // synopsys translate_on
419
                                );
420
        defparam
421
                lpm_ff_component.lpm_fftype = "DFF",
422
                lpm_ff_component.lpm_type = "LPM_FF",
423
                lpm_ff_component.lpm_width = 1;
424
 
425
 
426
endmodule
427
 
428
// ============================================================
429
// CNX file retrieval info
430
// ============================================================
431
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
432
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
433
// Retrieval info: PRIVATE: ASET NUMERIC "1"
434
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
435
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
436
// Retrieval info: PRIVATE: DFF NUMERIC "1"
437
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
438
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
439
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
440
// Retrieval info: PRIVATE: SSET NUMERIC "0"
441
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
442
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
443
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
444
// Retrieval info: PRIVATE: nBit NUMERIC "1"
445
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
446
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
447
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
448
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
449
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
450
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
451
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
452
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
453
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
454
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
455
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
456
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
457
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
458
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
459
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
460
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
461
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
462
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
463
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
464
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
465
// Retrieval info: LIB_FILE: lpm
466
 
467
 
468
`else
469
 
470
 
471
module dff_sr ( aclr, aset, clock, data, q);
472
 
473
    input         aclr;
474
    input         aset;
475
    input         clock;
476
    input         data;
477
    output reg    q;
478
 
479
   always @ (posedge clock or posedge aclr or posedge aset)
480
     if (aclr)
481
       q <= 1'b0;
482
     else if (aset)
483
       q <= 1'b1;
484
     else
485
       q <= data;
486
 
487
endmodule
488
 
489
`endif
490
 
491
// LATCH
492
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
493
`ifdef ALTERA
494
module latch ( d, le, q, clk);
495
input d, le;
496
output q;
497
input clk;
498
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
499
endmodule
500
`else
501
module latch ( d, le, q, clk);
502
input d, le;
503
output q;
504
input clk;/*
505
   always @ (posedge direction_set or posedge direction_clr)
506
     if (direction_clr)
507
       direction <= going_empty;
508
     else
509
       direction <= going_full;*/
510
endmodule
511
`endif//////////////////////////////////////////////////////////////////////
512
////                                                              ////
513
////  Versatile counter                                           ////
514
////                                                              ////
515
////  Description                                                 ////
516
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
517
////  counter                                                     ////
518
////                                                              ////
519
////  To Do:                                                      ////
520
////   - add LFSR with more taps                                  ////
521
////                                                              ////
522
////  Author(s):                                                  ////
523
////      - Michael Unneback, unneback@opencores.org              ////
524
////        ORSoC AB                                              ////
525
////                                                              ////
526
//////////////////////////////////////////////////////////////////////
527
////                                                              ////
528
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
529
////                                                              ////
530
//// This source file may be used and distributed without         ////
531
//// restriction provided that this copyright statement is not    ////
532
//// removed from the file and that any derivative work contains  ////
533
//// the original copyright notice and the associated disclaimer. ////
534
////                                                              ////
535
//// This source file is free software; you can redistribute it   ////
536
//// and/or modify it under the terms of the GNU Lesser General   ////
537
//// Public License as published by the Free Software Foundation; ////
538
//// either version 2.1 of the License, or (at your option) any   ////
539
//// later version.                                               ////
540
////                                                              ////
541
//// This source is distributed in the hope that it will be       ////
542
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
543
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
544
//// PURPOSE.  See the GNU Lesser General Public License for more ////
545
//// details.                                                     ////
546
////                                                              ////
547
//// You should have received a copy of the GNU Lesser General    ////
548
//// Public License along with this source; if not, download it   ////
549
//// from http://www.opencores.org/lgpl.shtml                     ////
550
////                                                              ////
551
//////////////////////////////////////////////////////////////////////
552
 
553
// binary counter
554
module cnt_bin_ce ( cke, q, rst, clk);
555
 
556
   parameter length = 4;
557
   input cke;
558
   output [length:1] q;
559
   input rst;
560
   input clk;
561
 
562
   parameter clear_value = 0;
563
   parameter set_value = 1;
564
   parameter wrap_value = 0;
565
   parameter level1_value = 15;
566
 
567
   reg  [length:1] qi;
568
   wire [length:1] q_next;
569
   assign q_next = qi + {{length-1{1'b0}},1'b1};
570
 
571
   always @ (posedge clk or posedge rst)
572
     if (rst)
573
       qi <= {length{1'b0}};
574
     else
575
     if (cke)
576
       qi <= q_next;
577
 
578
   assign q = qi;
579
 
580
endmodule
581
//////////////////////////////////////////////////////////////////////
582
////                                                              ////
583
////  Versatile counter                                           ////
584
////                                                              ////
585
////  Description                                                 ////
586
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
587
////  counter                                                     ////
588
////                                                              ////
589
////  To Do:                                                      ////
590
////   - add LFSR with more taps                                  ////
591
////                                                              ////
592
////  Author(s):                                                  ////
593
////      - Michael Unneback, unneback@opencores.org              ////
594
////        ORSoC AB                                              ////
595
////                                                              ////
596
//////////////////////////////////////////////////////////////////////
597
////                                                              ////
598
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
599
////                                                              ////
600
//// This source file may be used and distributed without         ////
601
//// restriction provided that this copyright statement is not    ////
602
//// removed from the file and that any derivative work contains  ////
603
//// the original copyright notice and the associated disclaimer. ////
604
////                                                              ////
605
//// This source file is free software; you can redistribute it   ////
606
//// and/or modify it under the terms of the GNU Lesser General   ////
607
//// Public License as published by the Free Software Foundation; ////
608
//// either version 2.1 of the License, or (at your option) any   ////
609
//// later version.                                               ////
610
////                                                              ////
611
//// This source is distributed in the hope that it will be       ////
612
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
613
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
614
//// PURPOSE.  See the GNU Lesser General Public License for more ////
615
//// details.                                                     ////
616
////                                                              ////
617
//// You should have received a copy of the GNU Lesser General    ////
618
//// Public License along with this source; if not, download it   ////
619
//// from http://www.opencores.org/lgpl.shtml                     ////
620
////                                                              ////
621
//////////////////////////////////////////////////////////////////////
622
 
623
// binary counter
624
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
625
 
626
   parameter length = 4;
627
   input clear;
628
   input cke;
629
   output [length:1] q;
630
   input rst;
631
   input clk;
632
 
633
   parameter clear_value = 0;
634
   parameter set_value = 1;
635
   parameter wrap_value = 0;
636
   parameter level1_value = 15;
637
 
638
   reg  [length:1] qi;
639
   wire [length:1] q_next;
640
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
641
 
642
   always @ (posedge clk or posedge rst)
643
     if (rst)
644
       qi <= {length{1'b0}};
645
     else
646
     if (cke)
647
       qi <= q_next;
648
 
649
   assign q = qi;
650
 
651
endmodule
652
//////////////////////////////////////////////////////////////////////
653
////                                                              ////
654
////  Versatile counter                                           ////
655
////                                                              ////
656
////  Description                                                 ////
657
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
658
////  counter                                                     ////
659
////                                                              ////
660
////  To Do:                                                      ////
661
////   - add LFSR with more taps                                  ////
662
////                                                              ////
663
////  Author(s):                                                  ////
664
////      - Michael Unneback, unneback@opencores.org              ////
665
////        ORSoC AB                                              ////
666
////                                                              ////
667
//////////////////////////////////////////////////////////////////////
668
////                                                              ////
669
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
670
////                                                              ////
671
//// This source file may be used and distributed without         ////
672
//// restriction provided that this copyright statement is not    ////
673
//// removed from the file and that any derivative work contains  ////
674
//// the original copyright notice and the associated disclaimer. ////
675
////                                                              ////
676
//// This source file is free software; you can redistribute it   ////
677
//// and/or modify it under the terms of the GNU Lesser General   ////
678
//// Public License as published by the Free Software Foundation; ////
679
//// either version 2.1 of the License, or (at your option) any   ////
680
//// later version.                                               ////
681
////                                                              ////
682
//// This source is distributed in the hope that it will be       ////
683
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
684
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
685
//// PURPOSE.  See the GNU Lesser General Public License for more ////
686
//// details.                                                     ////
687
////                                                              ////
688
//// You should have received a copy of the GNU Lesser General    ////
689
//// Public License along with this source; if not, download it   ////
690
//// from http://www.opencores.org/lgpl.shtml                     ////
691
////                                                              ////
692
//////////////////////////////////////////////////////////////////////
693
 
694
// binary counter
695
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
696
 
697
   parameter length = 4;
698
   input clear;
699
   input set;
700
   input cke;
701
   input rew;
702
   output [length:1] q;
703
   input rst;
704
   input clk;
705
 
706
   parameter clear_value = 0;
707
   parameter set_value = 1;
708
   parameter wrap_value = 0;
709
   parameter level1_value = 15;
710
 
711
   reg  [length:1] qi;
712
   wire  [length:1] q_next, q_next_fw, q_next_rew;
713
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
714
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
715
   assign q_next = rew ? q_next_rew : q_next_fw;
716
 
717
   always @ (posedge clk or posedge rst)
718
     if (rst)
719
       qi <= {length{1'b0}};
720
     else
721
     if (cke)
722
       qi <= q_next;
723
 
724
   assign q = qi;
725
 
726
endmodule
727
//////////////////////////////////////////////////////////////////////
728
////                                                              ////
729
////  Versatile counter                                           ////
730
////                                                              ////
731
////  Description                                                 ////
732
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
733
////  counter                                                     ////
734
////                                                              ////
735
////  To Do:                                                      ////
736
////   - add LFSR with more taps                                  ////
737
////                                                              ////
738
////  Author(s):                                                  ////
739
////      - Michael Unneback, unneback@opencores.org              ////
740
////        ORSoC AB                                              ////
741
////                                                              ////
742
//////////////////////////////////////////////////////////////////////
743
////                                                              ////
744
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
745
////                                                              ////
746
//// This source file may be used and distributed without         ////
747
//// restriction provided that this copyright statement is not    ////
748
//// removed from the file and that any derivative work contains  ////
749
//// the original copyright notice and the associated disclaimer. ////
750
////                                                              ////
751
//// This source file is free software; you can redistribute it   ////
752
//// and/or modify it under the terms of the GNU Lesser General   ////
753
//// Public License as published by the Free Software Foundation; ////
754
//// either version 2.1 of the License, or (at your option) any   ////
755
//// later version.                                               ////
756
////                                                              ////
757
//// This source is distributed in the hope that it will be       ////
758
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
759
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
760
//// PURPOSE.  See the GNU Lesser General Public License for more ////
761
//// details.                                                     ////
762
////                                                              ////
763
//// You should have received a copy of the GNU Lesser General    ////
764
//// Public License along with this source; if not, download it   ////
765
//// from http://www.opencores.org/lgpl.shtml                     ////
766
////                                                              ////
767
//////////////////////////////////////////////////////////////////////
768
 
769
// binary counter
770
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
771
 
772
   parameter length = 4;
773
   input cke;
774
   input rew;
775
   output reg level1;
776
   input rst;
777
   input clk;
778
 
779
   parameter clear_value = 0;
780
   parameter set_value = 1;
781
   parameter wrap_value = 1;
782
   parameter level1_value = 15;
783
 
784
   reg  [length:1] qi;
785
   wire  [length:1] q_next, q_next_fw, q_next_rew;
786
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
787
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
788
   assign q_next = rew ? q_next_rew : q_next_fw;
789
 
790
   always @ (posedge clk or posedge rst)
791
     if (rst)
792
       qi <= {length{1'b0}};
793
     else
794
     if (cke)
795
       qi <= q_next;
796
 
797
 
798
 
799
    always @ (posedge clk or posedge rst)
800
    if (rst)
801
        level1 <= 1'b0;
802
    else
803
    if (cke)
804
    if (q_next == level1_value)
805
        level1 <= 1'b1;
806
    else if (qi == level1_value & rew)
807
        level1 <= 1'b0;
808
endmodule
809
//////////////////////////////////////////////////////////////////////
810
////                                                              ////
811
////  Versatile counter                                           ////
812
////                                                              ////
813
////  Description                                                 ////
814
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
815
////  counter                                                     ////
816
////                                                              ////
817
////  To Do:                                                      ////
818
////   - add LFSR with more taps                                  ////
819
////                                                              ////
820
////  Author(s):                                                  ////
821
////      - Michael Unneback, unneback@opencores.org              ////
822
////        ORSoC AB                                              ////
823
////                                                              ////
824
//////////////////////////////////////////////////////////////////////
825
////                                                              ////
826
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
827
////                                                              ////
828
//// This source file may be used and distributed without         ////
829
//// restriction provided that this copyright statement is not    ////
830
//// removed from the file and that any derivative work contains  ////
831
//// the original copyright notice and the associated disclaimer. ////
832
////                                                              ////
833
//// This source file is free software; you can redistribute it   ////
834
//// and/or modify it under the terms of the GNU Lesser General   ////
835
//// Public License as published by the Free Software Foundation; ////
836
//// either version 2.1 of the License, or (at your option) any   ////
837
//// later version.                                               ////
838
////                                                              ////
839
//// This source is distributed in the hope that it will be       ////
840
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
841
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
842
//// PURPOSE.  See the GNU Lesser General Public License for more ////
843
//// details.                                                     ////
844
////                                                              ////
845
//// You should have received a copy of the GNU Lesser General    ////
846
//// Public License along with this source; if not, download it   ////
847
//// from http://www.opencores.org/lgpl.shtml                     ////
848
////                                                              ////
849
//////////////////////////////////////////////////////////////////////
850
 
851
// LFSR counter
852
module cnt_lfsr_zq ( zq, rst, clk);
853
 
854
   parameter length = 4;
855
   output reg zq;
856
   input rst;
857
   input clk;
858
 
859
   parameter clear_value = 0;
860
   parameter set_value = 1;
861
   parameter wrap_value = 8;
862
   parameter level1_value = 15;
863
 
864
   reg  [length:1] qi;
865
   reg lfsr_fb;
866
   wire [length:1] q_next;
867
   reg [32:1] polynom;
868
   integer i;
869
 
870
   always @ (qi)
871
   begin
872
        case (length)
873
         2: polynom = 32'b11;                               // 0x3
874
         3: polynom = 32'b110;                              // 0x6
875
         4: polynom = 32'b1100;                             // 0xC
876
         5: polynom = 32'b10100;                            // 0x14
877
         6: polynom = 32'b110000;                           // 0x30
878
         7: polynom = 32'b1100000;                          // 0x60
879
         8: polynom = 32'b10111000;                         // 0xb8
880
         9: polynom = 32'b100010000;                        // 0x110
881
        10: polynom = 32'b1001000000;                       // 0x240
882
        11: polynom = 32'b10100000000;                      // 0x500
883
        12: polynom = 32'b100000101001;                     // 0x829
884
        13: polynom = 32'b1000000001100;                    // 0x100C
885
        14: polynom = 32'b10000000010101;                   // 0x2015
886
        15: polynom = 32'b110000000000000;                  // 0x6000
887
        16: polynom = 32'b1101000000001000;                 // 0xD008
888
        17: polynom = 32'b10010000000000000;                // 0x12000
889
        18: polynom = 32'b100000010000000000;               // 0x20400
890
        19: polynom = 32'b1000000000000100011;              // 0x40023
891
        20: polynom = 32'b10000010000000000000;             // 0x82000
892
        21: polynom = 32'b101000000000000000000;            // 0x140000
893
        22: polynom = 32'b1100000000000000000000;           // 0x300000
894
        23: polynom = 32'b10000100000000000000000;          // 0x420000
895
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
896
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
897
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
898
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
899
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
900
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
901
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
902
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
903
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
904
        default: polynom = 32'b0;
905
        endcase
906
        lfsr_fb = qi[length];
907
        for (i=length-1; i>=1; i=i-1) begin
908
            if (polynom[i])
909
                lfsr_fb = lfsr_fb  ~^ qi[i];
910
        end
911
    end
912
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
913
 
914
   always @ (posedge clk or posedge rst)
915
     if (rst)
916
       qi <= {length{1'b0}};
917
     else
918
       qi <= q_next;
919
 
920
 
921
 
922
   always @ (posedge clk or posedge rst)
923
     if (rst)
924
       zq <= 1'b1;
925
     else
926
       zq <= q_next == {length{1'b0}};
927
endmodule
928
//////////////////////////////////////////////////////////////////////
929
////                                                              ////
930
////  Versatile counter                                           ////
931
////                                                              ////
932
////  Description                                                 ////
933
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
934
////  counter                                                     ////
935
////                                                              ////
936
////  To Do:                                                      ////
937
////   - add LFSR with more taps                                  ////
938
////                                                              ////
939
////  Author(s):                                                  ////
940
////      - Michael Unneback, unneback@opencores.org              ////
941
////        ORSoC AB                                              ////
942
////                                                              ////
943
//////////////////////////////////////////////////////////////////////
944
////                                                              ////
945
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
946
////                                                              ////
947
//// This source file may be used and distributed without         ////
948
//// restriction provided that this copyright statement is not    ////
949
//// removed from the file and that any derivative work contains  ////
950
//// the original copyright notice and the associated disclaimer. ////
951
////                                                              ////
952
//// This source file is free software; you can redistribute it   ////
953
//// and/or modify it under the terms of the GNU Lesser General   ////
954
//// Public License as published by the Free Software Foundation; ////
955
//// either version 2.1 of the License, or (at your option) any   ////
956
//// later version.                                               ////
957
////                                                              ////
958
//// This source is distributed in the hope that it will be       ////
959
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
960
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
961
//// PURPOSE.  See the GNU Lesser General Public License for more ////
962
//// details.                                                     ////
963
////                                                              ////
964
//// You should have received a copy of the GNU Lesser General    ////
965
//// Public License along with this source; if not, download it   ////
966
//// from http://www.opencores.org/lgpl.shtml                     ////
967
////                                                              ////
968
//////////////////////////////////////////////////////////////////////
969
 
970
// LFSR counter
971
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
972
 
973
   parameter length = 4;
974
   input cke;
975
   output reg zq;
976
   input rst;
977
   input clk;
978
 
979
   parameter clear_value = 0;
980
   parameter set_value = 1;
981
   parameter wrap_value = 8;
982
   parameter level1_value = 15;
983
 
984
   reg  [length:1] qi;
985
   reg lfsr_fb;
986
   wire [length:1] q_next;
987
   reg [32:1] polynom;
988
   integer i;
989
 
990
   always @ (qi)
991
   begin
992
        case (length)
993
         2: polynom = 32'b11;                               // 0x3
994
         3: polynom = 32'b110;                              // 0x6
995
         4: polynom = 32'b1100;                             // 0xC
996
         5: polynom = 32'b10100;                            // 0x14
997
         6: polynom = 32'b110000;                           // 0x30
998
         7: polynom = 32'b1100000;                          // 0x60
999
         8: polynom = 32'b10111000;                         // 0xb8
1000
         9: polynom = 32'b100010000;                        // 0x110
1001
        10: polynom = 32'b1001000000;                       // 0x240
1002
        11: polynom = 32'b10100000000;                      // 0x500
1003
        12: polynom = 32'b100000101001;                     // 0x829
1004
        13: polynom = 32'b1000000001100;                    // 0x100C
1005
        14: polynom = 32'b10000000010101;                   // 0x2015
1006
        15: polynom = 32'b110000000000000;                  // 0x6000
1007
        16: polynom = 32'b1101000000001000;                 // 0xD008
1008
        17: polynom = 32'b10010000000000000;                // 0x12000
1009
        18: polynom = 32'b100000010000000000;               // 0x20400
1010
        19: polynom = 32'b1000000000000100011;              // 0x40023
1011
        20: polynom = 32'b10000010000000000000;             // 0x82000
1012
        21: polynom = 32'b101000000000000000000;            // 0x140000
1013
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1014
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1015
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1016
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1017
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1018
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1019
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1020
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1021
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1022
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1023
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1024
        default: polynom = 32'b0;
1025
        endcase
1026
        lfsr_fb = qi[length];
1027
        for (i=length-1; i>=1; i=i-1) begin
1028
            if (polynom[i])
1029
                lfsr_fb = lfsr_fb  ~^ qi[i];
1030
        end
1031
    end
1032
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1033
 
1034
   always @ (posedge clk or posedge rst)
1035
     if (rst)
1036
       qi <= {length{1'b0}};
1037
     else
1038
     if (cke)
1039
       qi <= q_next;
1040
 
1041
 
1042
 
1043
   always @ (posedge clk or posedge rst)
1044
     if (rst)
1045
       zq <= 1'b1;
1046
     else
1047
     if (cke)
1048
       zq <= q_next == {length{1'b0}};
1049
endmodule
1050
//////////////////////////////////////////////////////////////////////
1051
////                                                              ////
1052
////  Versatile counter                                           ////
1053
////                                                              ////
1054
////  Description                                                 ////
1055
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1056
////  counter                                                     ////
1057
////                                                              ////
1058
////  To Do:                                                      ////
1059
////   - add LFSR with more taps                                  ////
1060
////                                                              ////
1061
////  Author(s):                                                  ////
1062
////      - Michael Unneback, unneback@opencores.org              ////
1063
////        ORSoC AB                                              ////
1064
////                                                              ////
1065
//////////////////////////////////////////////////////////////////////
1066
////                                                              ////
1067
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1068
////                                                              ////
1069
//// This source file may be used and distributed without         ////
1070
//// restriction provided that this copyright statement is not    ////
1071
//// removed from the file and that any derivative work contains  ////
1072
//// the original copyright notice and the associated disclaimer. ////
1073
////                                                              ////
1074
//// This source file is free software; you can redistribute it   ////
1075
//// and/or modify it under the terms of the GNU Lesser General   ////
1076
//// Public License as published by the Free Software Foundation; ////
1077
//// either version 2.1 of the License, or (at your option) any   ////
1078
//// later version.                                               ////
1079
////                                                              ////
1080
//// This source is distributed in the hope that it will be       ////
1081
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1082
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1083
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1084
//// details.                                                     ////
1085
////                                                              ////
1086
//// You should have received a copy of the GNU Lesser General    ////
1087
//// Public License along with this source; if not, download it   ////
1088
//// from http://www.opencores.org/lgpl.shtml                     ////
1089
////                                                              ////
1090
//////////////////////////////////////////////////////////////////////
1091
 
1092
// LFSR counter
1093
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1094
 
1095
   parameter length = 4;
1096
   input cke;
1097
   input rew;
1098
   output reg level1;
1099
   input rst;
1100
   input clk;
1101
 
1102
   parameter clear_value = 0;
1103
   parameter set_value = 1;
1104
   parameter wrap_value = 8;
1105
   parameter level1_value = 15;
1106
 
1107
   reg  [length:1] qi;
1108
   reg lfsr_fb, lfsr_fb_rew;
1109
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1110
   reg [32:1] polynom_rew;
1111
   integer j;
1112
   reg [32:1] polynom;
1113
   integer i;
1114
 
1115
   always @ (qi)
1116
   begin
1117
        case (length)
1118
         2: polynom = 32'b11;                               // 0x3
1119
         3: polynom = 32'b110;                              // 0x6
1120
         4: polynom = 32'b1100;                             // 0xC
1121
         5: polynom = 32'b10100;                            // 0x14
1122
         6: polynom = 32'b110000;                           // 0x30
1123
         7: polynom = 32'b1100000;                          // 0x60
1124
         8: polynom = 32'b10111000;                         // 0xb8
1125
         9: polynom = 32'b100010000;                        // 0x110
1126
        10: polynom = 32'b1001000000;                       // 0x240
1127
        11: polynom = 32'b10100000000;                      // 0x500
1128
        12: polynom = 32'b100000101001;                     // 0x829
1129
        13: polynom = 32'b1000000001100;                    // 0x100C
1130
        14: polynom = 32'b10000000010101;                   // 0x2015
1131
        15: polynom = 32'b110000000000000;                  // 0x6000
1132
        16: polynom = 32'b1101000000001000;                 // 0xD008
1133
        17: polynom = 32'b10010000000000000;                // 0x12000
1134
        18: polynom = 32'b100000010000000000;               // 0x20400
1135
        19: polynom = 32'b1000000000000100011;              // 0x40023
1136
        20: polynom = 32'b10000010000000000000;             // 0x82000
1137
        21: polynom = 32'b101000000000000000000;            // 0x140000
1138
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1139
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1140
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1141
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1142
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1143
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1144
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1145
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1146
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1147
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1148
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1149
        default: polynom = 32'b0;
1150
        endcase
1151
        lfsr_fb = qi[length];
1152
        for (i=length-1; i>=1; i=i-1) begin
1153
            if (polynom[i])
1154
                lfsr_fb = lfsr_fb  ~^ qi[i];
1155
        end
1156
    end
1157
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1158
   always @ (qi)
1159
   begin
1160
        case (length)
1161
         2: polynom_rew = 32'b11;
1162
         3: polynom_rew = 32'b110;
1163
         4: polynom_rew = 32'b1100;
1164
         5: polynom_rew = 32'b10100;
1165
         6: polynom_rew = 32'b110000;
1166
         7: polynom_rew = 32'b1100000;
1167
         8: polynom_rew = 32'b10111000;
1168
         9: polynom_rew = 32'b100010000;
1169
        10: polynom_rew = 32'b1001000000;
1170
        11: polynom_rew = 32'b10100000000;
1171
        12: polynom_rew = 32'b100000101001;
1172
        13: polynom_rew = 32'b1000000001100;
1173
        14: polynom_rew = 32'b10000000010101;
1174
        15: polynom_rew = 32'b110000000000000;
1175
        16: polynom_rew = 32'b1101000000001000;
1176
        17: polynom_rew = 32'b10010000000000000;
1177
        18: polynom_rew = 32'b100000010000000000;
1178
        19: polynom_rew = 32'b1000000000000100011;
1179
        20: polynom_rew = 32'b10000010000000000000;
1180
        21: polynom_rew = 32'b101000000000000000000;
1181
        22: polynom_rew = 32'b1100000000000000000000;
1182
        23: polynom_rew = 32'b10000100000000000000000;
1183
        24: polynom_rew = 32'b111000010000000000000000;
1184
        25: polynom_rew = 32'b1001000000000000000000000;
1185
        26: polynom_rew = 32'b10000000000000000000100011;
1186
        27: polynom_rew = 32'b100000000000000000000010011;
1187
        28: polynom_rew = 32'b1100100000000000000000000000;
1188
        29: polynom_rew = 32'b10100000000000000000000000000;
1189
        30: polynom_rew = 32'b100000000000000000000000101001;
1190
        31: polynom_rew = 32'b1001000000000000000000000000000;
1191
        32: polynom_rew = 32'b10000000001000000000000000000011;
1192
        default: polynom_rew = 32'b0;
1193
        endcase
1194
        // rotate left
1195
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1196
        lfsr_fb_rew = qi[length];
1197
        for (i=length-1; i>=1; i=i-1) begin
1198
            if (polynom_rew[i])
1199
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1200
        end
1201
    end
1202
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1203
   assign q_next = rew ? q_next_rew : q_next_fw;
1204
 
1205
   always @ (posedge clk or posedge rst)
1206
     if (rst)
1207
       qi <= {length{1'b0}};
1208
     else
1209
     if (cke)
1210
       qi <= q_next;
1211
 
1212
 
1213
 
1214
    always @ (posedge clk or posedge rst)
1215
    if (rst)
1216
        level1 <= 1'b0;
1217
    else
1218
    if (cke)
1219
    if (q_next == level1_value)
1220
        level1 <= 1'b1;
1221
    else if (qi == level1_value & rew)
1222
        level1 <= 1'b0;
1223
endmodule
1224
//////////////////////////////////////////////////////////////////////
1225
////                                                              ////
1226
////  Versatile counter                                           ////
1227
////                                                              ////
1228
////  Description                                                 ////
1229
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1230
////  counter                                                     ////
1231
////                                                              ////
1232
////  To Do:                                                      ////
1233
////   - add LFSR with more taps                                  ////
1234
////                                                              ////
1235
////  Author(s):                                                  ////
1236
////      - Michael Unneback, unneback@opencores.org              ////
1237
////        ORSoC AB                                              ////
1238
////                                                              ////
1239
//////////////////////////////////////////////////////////////////////
1240
////                                                              ////
1241
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1242
////                                                              ////
1243
//// This source file may be used and distributed without         ////
1244
//// restriction provided that this copyright statement is not    ////
1245
//// removed from the file and that any derivative work contains  ////
1246
//// the original copyright notice and the associated disclaimer. ////
1247
////                                                              ////
1248
//// This source file is free software; you can redistribute it   ////
1249
//// and/or modify it under the terms of the GNU Lesser General   ////
1250
//// Public License as published by the Free Software Foundation; ////
1251
//// either version 2.1 of the License, or (at your option) any   ////
1252
//// later version.                                               ////
1253
////                                                              ////
1254
//// This source is distributed in the hope that it will be       ////
1255
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1256
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1257
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1258
//// details.                                                     ////
1259
////                                                              ////
1260
//// You should have received a copy of the GNU Lesser General    ////
1261
//// Public License along with this source; if not, download it   ////
1262
//// from http://www.opencores.org/lgpl.shtml                     ////
1263
////                                                              ////
1264
//////////////////////////////////////////////////////////////////////
1265
 
1266
// GRAY counter
1267
module cnt_gray ( q, rst, clk);
1268
 
1269
   parameter length = 4;
1270
   output reg [length:1] q;
1271
   input rst;
1272
   input clk;
1273
 
1274
   parameter clear_value = 0;
1275
   parameter set_value = 1;
1276
   parameter wrap_value = 8;
1277
   parameter level1_value = 15;
1278
 
1279
   reg  [length:1] qi;
1280
   wire [length:1] q_next;
1281
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1282
 
1283
   always @ (posedge clk or posedge rst)
1284
     if (rst)
1285
       qi <= {length{1'b0}};
1286
     else
1287
       qi <= q_next;
1288
 
1289
   always @ (posedge clk or posedge rst)
1290
     if (rst)
1291
       q <= {length{1'b0}};
1292
     else
1293
         q <= (q_next>>1) ^ q_next;
1294
 
1295
endmodule
1296
//////////////////////////////////////////////////////////////////////
1297
////                                                              ////
1298
////  Versatile counter                                           ////
1299
////                                                              ////
1300
////  Description                                                 ////
1301
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1302
////  counter                                                     ////
1303
////                                                              ////
1304
////  To Do:                                                      ////
1305
////   - add LFSR with more taps                                  ////
1306
////                                                              ////
1307
////  Author(s):                                                  ////
1308
////      - Michael Unneback, unneback@opencores.org              ////
1309
////        ORSoC AB                                              ////
1310
////                                                              ////
1311
//////////////////////////////////////////////////////////////////////
1312
////                                                              ////
1313
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1314
////                                                              ////
1315
//// This source file may be used and distributed without         ////
1316
//// restriction provided that this copyright statement is not    ////
1317
//// removed from the file and that any derivative work contains  ////
1318
//// the original copyright notice and the associated disclaimer. ////
1319
////                                                              ////
1320
//// This source file is free software; you can redistribute it   ////
1321
//// and/or modify it under the terms of the GNU Lesser General   ////
1322
//// Public License as published by the Free Software Foundation; ////
1323
//// either version 2.1 of the License, or (at your option) any   ////
1324
//// later version.                                               ////
1325
////                                                              ////
1326
//// This source is distributed in the hope that it will be       ////
1327
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1328
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1329
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1330
//// details.                                                     ////
1331
////                                                              ////
1332
//// You should have received a copy of the GNU Lesser General    ////
1333
//// Public License along with this source; if not, download it   ////
1334
//// from http://www.opencores.org/lgpl.shtml                     ////
1335
////                                                              ////
1336
//////////////////////////////////////////////////////////////////////
1337
 
1338
// GRAY counter
1339
module cnt_gray_ce ( cke, q, rst, clk);
1340
 
1341
   parameter length = 4;
1342
   input cke;
1343
   output reg [length:1] q;
1344
   input rst;
1345
   input clk;
1346
 
1347
   parameter clear_value = 0;
1348
   parameter set_value = 1;
1349
   parameter wrap_value = 8;
1350
   parameter level1_value = 15;
1351
 
1352
   reg  [length:1] qi;
1353
   wire [length:1] q_next;
1354
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1355
 
1356
   always @ (posedge clk or posedge rst)
1357
     if (rst)
1358
       qi <= {length{1'b0}};
1359
     else
1360
     if (cke)
1361
       qi <= q_next;
1362
 
1363
   always @ (posedge clk or posedge rst)
1364
     if (rst)
1365
       q <= {length{1'b0}};
1366
     else
1367
       if (cke)
1368
         q <= (q_next>>1) ^ q_next;
1369
 
1370
endmodule
1371
//////////////////////////////////////////////////////////////////////
1372
////                                                              ////
1373
////  Versatile counter                                           ////
1374
////                                                              ////
1375
////  Description                                                 ////
1376
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1377
////  counter                                                     ////
1378
////                                                              ////
1379
////  To Do:                                                      ////
1380
////   - add LFSR with more taps                                  ////
1381
////                                                              ////
1382
////  Author(s):                                                  ////
1383
////      - Michael Unneback, unneback@opencores.org              ////
1384
////        ORSoC AB                                              ////
1385
////                                                              ////
1386
//////////////////////////////////////////////////////////////////////
1387
////                                                              ////
1388
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1389
////                                                              ////
1390
//// This source file may be used and distributed without         ////
1391
//// restriction provided that this copyright statement is not    ////
1392
//// removed from the file and that any derivative work contains  ////
1393
//// the original copyright notice and the associated disclaimer. ////
1394
////                                                              ////
1395
//// This source file is free software; you can redistribute it   ////
1396
//// and/or modify it under the terms of the GNU Lesser General   ////
1397
//// Public License as published by the Free Software Foundation; ////
1398
//// either version 2.1 of the License, or (at your option) any   ////
1399
//// later version.                                               ////
1400
////                                                              ////
1401
//// This source is distributed in the hope that it will be       ////
1402
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1403
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1404
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1405
//// details.                                                     ////
1406
////                                                              ////
1407
//// You should have received a copy of the GNU Lesser General    ////
1408
//// Public License along with this source; if not, download it   ////
1409
//// from http://www.opencores.org/lgpl.shtml                     ////
1410
////                                                              ////
1411
//////////////////////////////////////////////////////////////////////
1412
 
1413
// GRAY counter
1414
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1415
 
1416
   parameter length = 4;
1417
   input cke;
1418
   output reg [length:1] q;
1419
   output [length:1] q_bin;
1420
   input rst;
1421
   input clk;
1422
 
1423
   parameter clear_value = 0;
1424
   parameter set_value = 1;
1425
   parameter wrap_value = 8;
1426
   parameter level1_value = 15;
1427
 
1428
   reg  [length:1] qi;
1429
   wire [length:1] q_next;
1430
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1431
 
1432
   always @ (posedge clk or posedge rst)
1433
     if (rst)
1434
       qi <= {length{1'b0}};
1435
     else
1436
     if (cke)
1437
       qi <= q_next;
1438
 
1439
   always @ (posedge clk or posedge rst)
1440
     if (rst)
1441
       q <= {length{1'b0}};
1442
     else
1443
       if (cke)
1444
         q <= (q_next>>1) ^ q_next;
1445
 
1446
   assign q_bin = qi;
1447
 
1448
endmodule
1449
//////////////////////////////////////////////////////////////////////
1450
////                                                              ////
1451
////  Versatile library, counters                                 ////
1452
////                                                              ////
1453
////  Description                                                 ////
1454
////  counters                                                    ////
1455
////                                                              ////
1456
////                                                              ////
1457
////  To Do:                                                      ////
1458
////   - add more counters                                        ////
1459
////                                                              ////
1460
////  Author(s):                                                  ////
1461
////      - Michael Unneback, unneback@opencores.org              ////
1462
////        ORSoC AB                                              ////
1463
////                                                              ////
1464
//////////////////////////////////////////////////////////////////////
1465
////                                                              ////
1466
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1467
////                                                              ////
1468
//// This source file may be used and distributed without         ////
1469
//// restriction provided that this copyright statement is not    ////
1470
//// removed from the file and that any derivative work contains  ////
1471
//// the original copyright notice and the associated disclaimer. ////
1472
////                                                              ////
1473
//// This source file is free software; you can redistribute it   ////
1474
//// and/or modify it under the terms of the GNU Lesser General   ////
1475
//// Public License as published by the Free Software Foundation; ////
1476
//// either version 2.1 of the License, or (at your option) any   ////
1477
//// later version.                                               ////
1478
////                                                              ////
1479
//// This source is distributed in the hope that it will be       ////
1480
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1481
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1482
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1483
//// details.                                                     ////
1484
////                                                              ////
1485
//// You should have received a copy of the GNU Lesser General    ////
1486
//// Public License along with this source; if not, download it   ////
1487
//// from http://www.opencores.org/lgpl.shtml                     ////
1488
////                                                              ////
1489
//////////////////////////////////////////////////////////////////////
1490
 
1491
module cnt_shreg_wrap ( q, rst, clk);
1492
 
1493
   parameter length = 4;
1494
   output reg [0:length-1] q;
1495
   input rst;
1496
   input clk;
1497
 
1498
    always @ (posedge clk or posedge rst)
1499
    if (rst)
1500
        q <= {1'b1,{length-1{1'b0}}};
1501
    else
1502
        q <= {q[length-1],q[0:length-2]};
1503
 
1504
endmodule
1505
 
1506
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
1507
 
1508
   parameter length = 4;
1509
   input cke;
1510
   output reg [0:length-1] q;
1511
   input rst;
1512
   input clk;
1513
 
1514
    always @ (posedge clk or posedge rst)
1515
    if (rst)
1516
        q <= {1'b1,{length-1{1'b0}}};
1517
    else
1518
        if (cke)
1519
            q <= {q[length-1],q[0:length-2]};
1520
 
1521
endmodule
1522
 
1523
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1524
 
1525
   parameter length = 4;
1526
   input cke, clear;
1527
   output reg [0:length-1] q;
1528
   input rst;
1529
   input clk;
1530
 
1531
    always @ (posedge clk or posedge rst)
1532
    if (rst)
1533
        q <= {1'b1,{length-1{1'b0}}};
1534
    else
1535
        if (cke)
1536
            if (clear)
1537
                q <= {1'b1,{length-1{1'b0}}};
1538
            else
1539
                q <= q >> 1;
1540
 
1541
endmodule
1542
 
1543
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1544
 
1545
   parameter length = 4;
1546
   input cke, clear;
1547
   output reg [0:length-1] q;
1548
   input rst;
1549
   input clk;
1550
 
1551
    always @ (posedge clk or posedge rst)
1552
    if (rst)
1553
        q <= {1'b1,{length-1{1'b0}}};
1554
    else
1555
        if (cke)
1556
            if (clear)
1557
                q <= {1'b1,{length-1{1'b0}}};
1558
            else
1559
            q <= {q[length-1],q[0:length-2]};
1560
 
1561
endmodule
1562
//////////////////////////////////////////////////////////////////////
1563
////                                                              ////
1564
////  Versatile library, memories                                 ////
1565
////                                                              ////
1566
////  Description                                                 ////
1567
////  memories                                                    ////
1568
////                                                              ////
1569
////                                                              ////
1570
////  To Do:                                                      ////
1571
////   - add more memory types                                    ////
1572
////                                                              ////
1573
////  Author(s):                                                  ////
1574
////      - Michael Unneback, unneback@opencores.org              ////
1575
////        ORSoC AB                                              ////
1576
////                                                              ////
1577
//////////////////////////////////////////////////////////////////////
1578
////                                                              ////
1579
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1580
////                                                              ////
1581
//// This source file may be used and distributed without         ////
1582
//// restriction provided that this copyright statement is not    ////
1583
//// removed from the file and that any derivative work contains  ////
1584
//// the original copyright notice and the associated disclaimer. ////
1585
////                                                              ////
1586
//// This source file is free software; you can redistribute it   ////
1587
//// and/or modify it under the terms of the GNU Lesser General   ////
1588
//// Public License as published by the Free Software Foundation; ////
1589
//// either version 2.1 of the License, or (at your option) any   ////
1590
//// later version.                                               ////
1591
////                                                              ////
1592
//// This source is distributed in the hope that it will be       ////
1593
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1594
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1595
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1596
//// details.                                                     ////
1597
////                                                              ////
1598
//// You should have received a copy of the GNU Lesser General    ////
1599
//// Public License along with this source; if not, download it   ////
1600
//// from http://www.opencores.org/lgpl.shtml                     ////
1601
////                                                              ////
1602
//////////////////////////////////////////////////////////////////////
1603
 
1604
/// ROM
1605
 
1606
module vl_rom ( a, q, clk);
1607
 
1608
parameter data_width = 32;
1609
parameter addr_width = 4;
1610
 
1611
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1612
    {32'h18000000},
1613
    {32'hA8200000},
1614
    {32'hA8200000},
1615
    {32'hA8200000},
1616
    {32'h44003000},
1617
    {32'h15000000},
1618
    {32'h15000000},
1619
    {32'h15000000},
1620
    {32'h15000000},
1621
    {32'h15000000},
1622
    {32'h15000000},
1623
    {32'h15000000},
1624
    {32'h15000000},
1625
    {32'h15000000},
1626
    {32'h15000000},
1627
    {32'h15000000}};
1628
 
1629
input [addr_width-1:0] a;
1630
output reg [data_width-1:0] q;
1631
input clk;
1632
 
1633
always @ (posedge clk)
1634
    q <= data[a];
1635
 
1636
endmodule
1637
 
1638
// Single port RAM
1639
 
1640
module vl_ram ( d, adr, we, q, clk);
1641
   parameter data_width = 32;
1642
   parameter addr_width = 8;
1643
   input [(data_width-1):0]      d;
1644
   input [(addr_width-1):0]       adr;
1645
   input                         we;
1646
   output reg [(data_width-1):0]          q;
1647
   input                         clk;
1648
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1649
   always @ (posedge clk)
1650
   begin
1651
   if (we)
1652
     ram[adr] <= d;
1653
   q <= ram[adr];
1654
   end
1655
 
1656
endmodule
1657
 
1658
// Dual port RAM
1659
 
1660
// ACTEL FPGA should not use logic to handle rw collision
1661
`ifdef ACTEL
1662
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
1663
`else
1664
        `define SYN
1665
`endif
1666
 
1667
module vl_dual_port_ram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1668
   parameter data_width = 32;
1669
   parameter addr_width = 8;
1670
   input [(data_width-1):0]      d_a;
1671
   input [(addr_width-1):0]       adr_a;
1672
   input [(addr_width-1):0]       adr_b;
1673
   input                         we_a;
1674
   output [(data_width-1):0]      q_b;
1675
   input                         clk_a, clk_b;
1676
   reg [(addr_width-1):0]         adr_b_reg;
1677
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
1678
   always @ (posedge clk_a)
1679
   if (we_a)
1680
     ram[adr_a] <= d_a;
1681
   always @ (posedge clk_b)
1682
   adr_b_reg <= adr_b;
1683
   assign q_b = ram[adr_b_reg];
1684
endmodule
1685
 
1686
module vl_dual_port_ram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1687
   parameter data_width = 32;
1688
   parameter addr_width = 8;
1689
   input [(data_width-1):0]      d_a;
1690
   input [(addr_width-1):0]       adr_a;
1691
   input [(addr_width-1):0]       adr_b;
1692
   input                         we_a;
1693
   output [(data_width-1):0]      q_b;
1694
   output reg [(data_width-1):0] q_a;
1695
   input                         clk_a, clk_b;
1696
   reg [(data_width-1):0]         q_b;
1697
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
1698
   always @ (posedge clk_a)
1699
     begin
1700
        q_a <= ram[adr_a];
1701
        if (we_a)
1702
             ram[adr_a] <= d_a;
1703
     end
1704
   always @ (posedge clk_b)
1705
          q_b <= ram[adr_b];
1706
endmodule
1707
 
1708
module vl_dual_port_ram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, d_b, we_b, clk_b );
1709
   parameter data_width = 32;
1710
   parameter addr_width = 8;
1711
   input [(data_width-1):0]      d_a;
1712
   input [(addr_width-1):0]       adr_a;
1713
   input [(addr_width-1):0]       adr_b;
1714
   input                         we_a;
1715
   output [(data_width-1):0]      q_b;
1716
   input [(data_width-1):0]       d_b;
1717
   output reg [(data_width-1):0] q_a;
1718
   input                         we_b;
1719
   input                         clk_a, clk_b;
1720
   reg [(data_width-1):0]         q_b;
1721
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
1722
   always @ (posedge clk_a)
1723
     begin
1724
        q_a <= ram[adr_a];
1725
        if (we_a)
1726
             ram[adr_a] <= d_a;
1727
     end
1728
   always @ (posedge clk_b)
1729
     begin
1730
        q_b <= ram[adr_b];
1731
        if (we_b)
1732
          ram[adr_b] <= d_b;
1733
     end
1734
endmodule
1735
 
1736
// Content addresable memory, CAM
1737
 
1738
// FIFO
1739
 
1740
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1741
 
1742
   parameter ADDR_WIDTH = 4;
1743
   parameter N = ADDR_WIDTH-1;
1744
 
1745
   parameter Q1 = 2'b00;
1746
   parameter Q2 = 2'b01;
1747
   parameter Q3 = 2'b11;
1748
   parameter Q4 = 2'b10;
1749
 
1750
   parameter going_empty = 1'b0;
1751
   parameter going_full  = 1'b1;
1752
 
1753
   input [N:0]  wptr, rptr;
1754
   output reg   fifo_empty;
1755
   output       fifo_full;
1756
   input        wclk, rclk, rst;
1757
 
1758
`ifndef GENERATE_DIRECTION_AS_LATCH
1759
   wire direction;
1760
`endif
1761
`ifdef GENERATE_DIRECTION_AS_LATCH
1762
   reg direction;
1763
`endif
1764
   reg  direction_set, direction_clr;
1765
 
1766
   wire async_empty, async_full;
1767
   wire fifo_full2;
1768
   reg  fifo_empty2;
1769
 
1770
   // direction_set
1771
   always @ (wptr[N:N-1] or rptr[N:N-1])
1772
     case ({wptr[N:N-1],rptr[N:N-1]})
1773
       {Q1,Q2} : direction_set <= 1'b1;
1774
       {Q2,Q3} : direction_set <= 1'b1;
1775
       {Q3,Q4} : direction_set <= 1'b1;
1776
       {Q4,Q1} : direction_set <= 1'b1;
1777
       default : direction_set <= 1'b0;
1778
     endcase
1779
 
1780
   // direction_clear
1781
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1782
     if (rst)
1783
       direction_clr <= 1'b1;
1784
     else
1785
       case ({wptr[N:N-1],rptr[N:N-1]})
1786
         {Q2,Q1} : direction_clr <= 1'b1;
1787
         {Q3,Q2} : direction_clr <= 1'b1;
1788
         {Q4,Q3} : direction_clr <= 1'b1;
1789
         {Q1,Q4} : direction_clr <= 1'b1;
1790
         default : direction_clr <= 1'b0;
1791
       endcase
1792
 
1793
`ifndef GENERATE_DIRECTION_AS_LATCH
1794
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1795
`endif
1796
 
1797
`ifdef GENERATE_DIRECTION_AS_LATCH
1798
   always @ (posedge direction_set or posedge direction_clr)
1799
     if (direction_clr)
1800
       direction <= going_empty;
1801
     else
1802
       direction <= going_full;
1803
`endif
1804
 
1805
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1806
   assign async_full  = (wptr == rptr) && (direction==going_full);
1807
 
1808
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1809
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1810
 
1811
/*
1812
   always @ (posedge wclk or posedge rst or posedge async_full)
1813
     if (rst)
1814
       {fifo_full, fifo_full2} <= 2'b00;
1815
     else if (async_full)
1816
       {fifo_full, fifo_full2} <= 2'b11;
1817
     else
1818
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1819
*/
1820
   always @ (posedge rclk or posedge async_empty)
1821
     if (async_empty)
1822
       {fifo_empty, fifo_empty2} <= 2'b11;
1823
     else
1824
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
1825
 
1826
endmodule // async_comp
1827
 
1828
module vl_fifo_1r1w_async (
1829
    d, wr, fifo_full, wr_clk, wr_rst,
1830
    q, rd, fifo_empty, rd_clk, rd_rst
1831
    );
1832
 
1833
parameter data_width = 18;
1834
parameter addr_width = 4;
1835
 
1836
// write side
1837
input  [data_width-1:0] d;
1838
input                   wr;
1839
output                  fifo_full;
1840
input                   wr_clk;
1841
input                   wr_rst;
1842
// read side
1843
output [data_width-1:0] q;
1844
input                   rd;
1845
output                  fifo_empty;
1846
input                   rd_clk;
1847
input                   rd_rst;
1848
 
1849
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1850
 
1851
vl_fifo_1r1w_async (
1852
    d, wr, fifo_full, wr_clk, wr_rst,
1853
    q, rd, fifo_empty, rd_clk, rd_rst
1854
    );
1855
 
1856
adr_gen
1857
    # ( .length(addr_width))
1858
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1859
 
1860
adr_gen
1861
    # (.length(addr_width))
1862
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
1863
 
1864
vl_dual_port_ram_1r1w
1865
    # (.data_width(data_width), .addr_width(addr_width))
1866
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1867
 
1868
vl_fifo_cmp_async
1869
    # (.addr_width(addr_width))
1870
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1871
 
1872
endmodule
1873
 
1874
module vl_fifo_2r2w (
1875
    // a side
1876
    a_d, a_wr, a_fifo_full,
1877
    a_q, a_rd, a_fifo_empty,
1878
    a_clk, a_rst,
1879
    // b side
1880
    b_d, b_wr, b_fifo_full,
1881
    b_q, b_rd, b_fifo_empty,
1882
    b_clk, b_rst
1883
    );
1884
 
1885
parameter data_width = 18;
1886
parameter addr_width = 4;
1887
 
1888
// a side
1889
input  [data_width-1:0] a_d;
1890
input                   a_wr;
1891
output                  a_fifo_full;
1892
output [data_width-1:0] a_q;
1893
input                   a_rd;
1894
output                  a_fifo_empty;
1895
input                   a_clk;
1896
input                   a_rst;
1897
 
1898
// b side
1899
input  [data_width-1:0] b_d;
1900
input                   b_wr;
1901
output                  b_fifo_full;
1902
output [data_width-1:0] b_q;
1903
input                   b_rd;
1904
output                  b_fifo_empty;
1905
input                   b_clk;
1906
input                   b_rst;
1907
 
1908
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1909
vl_fifo_1r1w_async_a (
1910
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1911
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1912
    );
1913
 
1914
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1915
vl_fifo_1r1w_async_b (
1916
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1917
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1918
    );
1919
 
1920
endmodule
1921
 
1922
module vl_fifo_2r2w_simplex (
1923
    // a side
1924
    a_d, a_wr, a_fifo_full,
1925
    a_q, a_rd, a_fifo_empty,
1926
    a_clk, a_rst,
1927
    // b side
1928
    b_d, b_wr, b_fifo_full,
1929
    b_q, b_rd, b_fifo_empty,
1930
    b_clk, b_rst
1931
    );
1932
 
1933
parameter data_width = 18;
1934
parameter addr_width = 4;
1935
 
1936
// a side
1937
input  [data_width-1:0] a_d;
1938
input                   a_wr;
1939
output                  a_fifo_full;
1940
output [data_width-1:0] a_q;
1941
input                   a_rd;
1942
output                  a_fifo_empty;
1943
input                   a_clk;
1944
input                   a_rst;
1945
 
1946
// b side
1947
input  [data_width-1:0] b_d;
1948
input                   b_wr;
1949
output                  b_fifo_full;
1950
output [data_width-1:0] b_q;
1951
input                   b_rd;
1952
output                  b_fifo_empty;
1953
input                   b_clk;
1954
input                   b_rst;
1955
 
1956
// adr_gen
1957
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1958
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1959
// dpram
1960
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1961
 
1962
adr_gen
1963
    # ( .length(addr_width))
1964
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1965
 
1966
adr_gen
1967
    # (.length(addr_width))
1968
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1969
 
1970
adr_gen
1971
    # ( .length(addr_width))
1972
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1973
 
1974
adr_gen
1975
    # (.length(addr_width))
1976
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1977
 
1978
// mux read or write adr to DPRAM
1979
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1980
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1981
 
1982
vfifo_dual_port_ram_dc_dw
1983
    # (.data_width(data_width), .addr_width(addr_width+1))
1984
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1985
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1986
 
1987
vl_fifo_async_cmp
1988
    # (.addr_width(addr_width))
1989
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1990
 
1991
versatile_fifo_async_cmp
1992
    # (.addr_width(addr_width))
1993
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1994
 
1995
endmodule

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