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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 61

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 40 unneback
`ifdef ALL
14
 
15
`define GBUF
16
`define SYNC_RST
17
`define PLL
18
 
19
`define MULTS
20
`define MULTS18X18
21
`define MULT
22
`define SHIFT_UNIT_32
23
`define LOGIC_UNIT
24
 
25
`define CNT_SHREG_WRAP
26
`define CNT_SHREG_CE_WRAP
27
`define CNT_SHREG_CE_CLEAR
28
`define CNT_SHREG_CE_CLEAR_WRAP
29
 
30
`define MUX_ANDOR
31
`define MUX2_ANDOR
32
`define MUX3_ANDOR
33
`define MUX4_ANDOR
34
`define MUX5_ANDOR
35
`define MUX6_ANDOR
36 43 unneback
`define PARITY
37 40 unneback
 
38
`define ROM_INIT
39
`define RAM
40
`define RAM_BE
41
`define DPRAM_1R1W
42
`define DPRAM_2R1W
43
`define DPRAM_2R2W
44
`define FIFO_1R1W_FILL_LEVEL_SYNC
45
`define FIFO_2R2W_SYNC_SIMPLEX
46
`define FIFO_CMP_ASYNC
47
`define FIFO_1R1W_ASYNC
48
`define FIFO_2R2W_ASYNC
49
`define FIFO_2R2W_ASYNC_SIMPLEX
50 48 unneback
`define REG_FILE
51 40 unneback
 
52
`define DFF
53
`define DFF_ARRAY
54
`define DFF_CE
55
`define DFF_CE_CLEAR
56
`define DF_CE_SET
57
`define SPR
58
`define SRP
59
`define DFF_SR
60
`define LATCH
61
`define SHREG
62
`define SHREG_CE
63
`define DELAY
64
`define DELAY_EMPTYFLAG
65
 
66
`define WB3WB3_BRIDGE
67
`define WB3_ARBITER_TYPE1
68 59 unneback
`define WB_B3_RAM_BE
69 49 unneback
`define WB_B4_RAM_BE
70 48 unneback
`define WB_B4_ROM
71 40 unneback
`define WB_BOOT_ROM
72
`define WB_DPRAM
73
 
74 44 unneback
`define IO_DFF_OE
75
`define O_DFF
76
 
77 40 unneback
`endif
78
 
79
`ifdef PLL
80
`ifndef SYNC_RST
81
`define SYNC_RST
82
`endif
83
`endif
84
 
85
`ifdef SYNC_RST
86
`ifndef GBUF
87
`define GBUF
88
`endif
89
`endif
90
 
91
`ifdef WB_DPRAM
92
`ifndef DPRAM_2R2W
93
`define DPRAM_2R2W
94
`endif
95
`ifndef SPR
96
`define SPR
97
`endif
98
`endif
99
 
100
`ifdef WB3_ARBITER_TYPE1
101 42 unneback
`ifndef SPR
102
`define SPR
103
`endif
104 40 unneback
`ifndef MUX_ANDOR
105
`define MUX_ANDOR
106
`endif
107
`endif
108
 
109
`ifdef WB3WB3_BRIDGE
110
`ifndef CNT_SHREG_CE_CLEAR
111
`define CNT_SHREG_CE_CLEAR
112
`endif
113
`ifndef DFF
114
`define DFF
115
`endif
116
`ifndef DFF_CE
117
`define DFF_CE
118
`endif
119
`ifndef CNT_SHREG_CE_CLEAR
120
`define CNT_SHREG_CE_CLEAR
121
`endif
122
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
123
`define FIFO_2R2W_ASYNC_SIMPLEX
124
`endif
125
`endif
126
 
127
`ifdef MULTS18X18
128
`ifndef MULTS
129
`define MULTS
130
`endif
131
`endif
132
 
133
`ifdef SHIFT_UNIT_32
134
`ifndef MULTS
135
`define MULTS
136
`endif
137
`endif
138
 
139
`ifdef MUX2_ANDOR
140
`ifndef MUX_ANDOR
141
`define MUX_ANDOR
142
`endif
143
`endif
144
 
145
`ifdef MUX3_ANDOR
146
`ifndef MUX_ANDOR
147
`define MUX_ANDOR
148
`endif
149
`endif
150
 
151
`ifdef MUX4_ANDOR
152
`ifndef MUX_ANDOR
153
`define MUX_ANDOR
154
`endif
155
`endif
156
 
157
`ifdef MUX5_ANDOR
158
`ifndef MUX_ANDOR
159
`define MUX_ANDOR
160
`endif
161
`endif
162
 
163
`ifdef MUX6_ANDOR
164
`ifndef MUX_ANDOR
165
`define MUX_ANDOR
166
`endif
167
`endif
168
 
169
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
170
`ifndef CNT_BIN_CE
171
`define CNT_BIN_CE
172
`endif
173
`ifndef DPRAM_1R1W
174
`define DPRAM_1R1W
175
`endif
176
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
177
`define CNT_BIN_CE_REW_Q_ZQ_L1
178
`endif
179
`endif
180
 
181
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
182
`ifndef CNT_LFSR_CE
183
`define CNT_LFSR_CE
184
`endif
185
`ifndef DPRAM_2R2W
186
`define DPRAM_2R2W
187
`endif
188
`ifndef CNT_BIN_CE_REW_ZQ_L1
189
`define CNT_BIN_CE_REW_ZQ_L1
190
`endif
191
`endif
192
 
193
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
194
`ifndef CNT_GRAY_CE_BIN
195
`define CNT_GRAY_CE_BIN
196
`endif
197
`ifndef DPRAM_2R2W
198
`define DPRAM_2R2W
199
`endif
200
`ifndef FIFO_CMP_ASYNC
201
`define FIFO_CMP_ASYNC
202
`endif
203
`endif
204
 
205
`ifdef FIFO_2R2W_ASYNC
206
`ifndef FIFO_1R1W_ASYNC
207
`define FIFO_1R1W_ASYNC
208
`endif
209
`endif
210
 
211
`ifdef FIFO_1R1W_ASYNC
212
`ifndef CNT_GRAY_CE_BIN
213
`define CNT_GRAY_CE_BIN
214
`endif
215
`ifndef DPRAM_1R1W
216
`define DPRAM_1R1W
217
`endif
218
`ifndef FIFO_CMP_ASYNC
219
`define FIFO_CMP_ASYNC
220
`endif
221
`endif
222
 
223
`ifdef FIFO_CMP_ASYNC
224
`ifndef DFF_SR
225
`define DFF_SR
226
`endif
227
`ifndef DFF
228
`define DFF
229
`endif
230
`endif
231 48 unneback
 
232
`ifdef REG_FILE
233
`ifndef DPRAM_1R1W
234
`define DPRAM_1R1W
235
`endif
236
`endif
237 61 unneback
 
238
`ifdef WB_B3_RAM_BE
239
`ifndef WB3_ARBITER_TYPE1
240
`define WB3_ARBITER_TYPE1
241
`endif
242
`ifndef RAM_BE
243
`define RAM_BE
244
`endif
245
`endif//////////////////////////////////////////////////////////////////////
246 6 unneback
////                                                              ////
247
////  Versatile library, clock and reset                          ////
248
////                                                              ////
249
////  Description                                                 ////
250
////  Logic related to clock and reset                            ////
251
////                                                              ////
252
////                                                              ////
253
////  To Do:                                                      ////
254
////   - add more different registers                             ////
255
////                                                              ////
256
////  Author(s):                                                  ////
257
////      - Michael Unneback, unneback@opencores.org              ////
258
////        ORSoC AB                                              ////
259
////                                                              ////
260
//////////////////////////////////////////////////////////////////////
261
////                                                              ////
262
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
263
////                                                              ////
264
//// This source file may be used and distributed without         ////
265
//// restriction provided that this copyright statement is not    ////
266
//// removed from the file and that any derivative work contains  ////
267
//// the original copyright notice and the associated disclaimer. ////
268
////                                                              ////
269
//// This source file is free software; you can redistribute it   ////
270
//// and/or modify it under the terms of the GNU Lesser General   ////
271
//// Public License as published by the Free Software Foundation; ////
272
//// either version 2.1 of the License, or (at your option) any   ////
273
//// later version.                                               ////
274
////                                                              ////
275
//// This source is distributed in the hope that it will be       ////
276
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
277
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
278
//// PURPOSE.  See the GNU Lesser General Public License for more ////
279
//// details.                                                     ////
280
////                                                              ////
281
//// You should have received a copy of the GNU Lesser General    ////
282
//// Public License along with this source; if not, download it   ////
283
//// from http://www.opencores.org/lgpl.shtml                     ////
284
////                                                              ////
285
//////////////////////////////////////////////////////////////////////
286
 
287 48 unneback
`ifdef ACTEL
288
`ifdef GBUF
289
`timescale 1 ns/100 ps
290 6 unneback
// Global buffer
291
// usage:
292
// use to enable global buffers for high fan out signals such as clock and reset
293
// Version: 8.4 8.4.0.33
294
module gbuf(GL,CLK);
295
output GL;
296
input  CLK;
297
 
298
    wire GND;
299
 
300
    GND GND_1_net(.Y(GND));
301
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
302
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
303
 
304
endmodule
305
`timescale 1 ns/1 ns
306 40 unneback
`define MODULE gbuf
307
module `BASE`MODULE ( i, o);
308
`undef MODULE
309 6 unneback
input i;
310
output o;
311
`ifdef SIM_GBUF
312
assign o=i;
313
`else
314
gbuf gbuf_i0 ( .CLK(i), .GL(o));
315
`endif
316
endmodule
317 40 unneback
`endif
318 33 unneback
 
319 6 unneback
`else
320 33 unneback
 
321 40 unneback
`ifdef ALTERA
322
`ifdef GBUF
323 21 unneback
//altera
324 40 unneback
`define MODULE gbuf
325
module `BASE`MODULE ( i, o);
326
`undef MODULE
327 33 unneback
input i;
328
output o;
329
assign o = i;
330
endmodule
331 40 unneback
`endif
332 33 unneback
 
333 6 unneback
`else
334
 
335 40 unneback
`ifdef GBUF
336 6 unneback
`timescale 1 ns/100 ps
337 40 unneback
`define MODULE
338
module `BASE`MODULE ( i, o);
339
`undef MODULE
340 6 unneback
input i;
341
output o;
342
assign o = i;
343
endmodule
344 40 unneback
`endif
345 6 unneback
`endif // ALTERA
346
`endif //ACTEL
347
 
348 40 unneback
`ifdef SYNC_RST
349 6 unneback
// sync reset
350 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
351 6 unneback
// output active high global reset sync with two DFFs 
352
`timescale 1 ns/100 ps
353 40 unneback
`define MODULE sync_rst
354
module `BASE`MODULE ( rst_n_i, rst_o, clk);
355
`undef MODULE
356 6 unneback
input rst_n_i, clk;
357
output rst_o;
358 18 unneback
reg [1:0] tmp;
359 6 unneback
always @ (posedge clk or negedge rst_n_i)
360
if (!rst_n_i)
361 17 unneback
        tmp <= 2'b11;
362 6 unneback
else
363 33 unneback
        tmp <= {1'b0,tmp[1]};
364 40 unneback
`define MODULE gbuf
365
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
366
`undef MODULE
367 6 unneback
endmodule
368 40 unneback
`endif
369 6 unneback
 
370 40 unneback
`ifdef PLL
371 6 unneback
// vl_pll
372
`ifdef ACTEL
373 32 unneback
///////////////////////////////////////////////////////////////////////////////
374 17 unneback
`timescale 1 ps/1 ps
375 40 unneback
`define MODULE pll
376
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
377
`undef MODULE
378 6 unneback
parameter index = 0;
379
parameter number_of_clk = 1;
380 17 unneback
parameter period_time_0 = 20000;
381
parameter period_time_1 = 20000;
382
parameter period_time_2 = 20000;
383
parameter lock_delay = 2000000;
384 6 unneback
input clk_i, rst_n_i;
385
output lock;
386
output reg [0:number_of_clk-1] clk_o;
387
output [0:number_of_clk-1] rst_o;
388
 
389
`ifdef SIM_PLL
390
 
391
always
392
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
393
 
394
generate if (number_of_clk > 1)
395
always
396
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
397
endgenerate
398
 
399
generate if (number_of_clk > 2)
400
always
401
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
402
endgenerate
403
 
404
genvar i;
405
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
406
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
407
end
408
endgenerate
409
 
410
assign #lock_delay lock = rst_n_i;
411
 
412
endmodule
413
`else
414
generate if (number_of_clk==1 & index==0) begin
415
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
416
end
417
endgenerate // index==0
418
generate if (number_of_clk==1 & index==1) begin
419
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
420
end
421
endgenerate // index==1
422
generate if (number_of_clk==1 & index==2) begin
423
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
424
end
425
endgenerate // index==2
426
generate if (number_of_clk==1 & index==3) begin
427
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
428
end
429
endgenerate // index==0
430
 
431
generate if (number_of_clk==2 & index==0) begin
432
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
433
end
434
endgenerate // index==0
435
generate if (number_of_clk==2 & index==1) begin
436
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
437
end
438
endgenerate // index==1
439
generate if (number_of_clk==2 & index==2) begin
440
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
441
end
442
endgenerate // index==2
443
generate if (number_of_clk==2 & index==3) begin
444
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
445
end
446
endgenerate // index==0
447
 
448
generate if (number_of_clk==3 & index==0) begin
449
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
450
end
451
endgenerate // index==0
452
generate if (number_of_clk==3 & index==1) begin
453
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
454
end
455
endgenerate // index==1
456
generate if (number_of_clk==3 & index==2) begin
457
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
458
end
459
endgenerate // index==2
460
generate if (number_of_clk==3 & index==3) begin
461
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
462
end
463
endgenerate // index==0
464
 
465
genvar i;
466
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
467 40 unneback
`define MODULE sync_rst
468
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
469
`undef MODULE
470 6 unneback
end
471
endgenerate
472
endmodule
473
`endif
474 32 unneback
///////////////////////////////////////////////////////////////////////////////
475 6 unneback
 
476
`else
477
 
478 32 unneback
///////////////////////////////////////////////////////////////////////////////
479 6 unneback
`ifdef ALTERA
480
 
481 32 unneback
`timescale 1 ps/1 ps
482 40 unneback
`define MODULE pll
483
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
484
`undef MODULE
485 32 unneback
parameter index = 0;
486
parameter number_of_clk = 1;
487
parameter period_time_0 = 20000;
488
parameter period_time_1 = 20000;
489
parameter period_time_2 = 20000;
490
parameter period_time_3 = 20000;
491
parameter period_time_4 = 20000;
492
parameter lock_delay = 2000000;
493
input clk_i, rst_n_i;
494
output lock;
495
output reg [0:number_of_clk-1] clk_o;
496
output [0:number_of_clk-1] rst_o;
497
 
498
`ifdef SIM_PLL
499
 
500
always
501
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
502
 
503
generate if (number_of_clk > 1)
504
always
505
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
506
endgenerate
507
 
508
generate if (number_of_clk > 2)
509
always
510
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
511
endgenerate
512
 
513 33 unneback
generate if (number_of_clk > 3)
514 32 unneback
always
515
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
516
endgenerate
517
 
518 33 unneback
generate if (number_of_clk > 4)
519 32 unneback
always
520
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
521
endgenerate
522
 
523
genvar i;
524
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
525
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
526
end
527
endgenerate
528
 
529 33 unneback
//assign #lock_delay lock = rst_n_i;
530
assign lock = rst_n_i;
531 32 unneback
 
532
endmodule
533 6 unneback
`else
534
 
535 33 unneback
`ifdef VL_PLL0
536
`ifdef VL_PLL0_CLK1
537
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
538
`endif
539
`ifdef VL_PLL0_CLK2
540
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
541
`endif
542
`ifdef VL_PLL0_CLK3
543
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
544
`endif
545
`ifdef VL_PLL0_CLK4
546
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
547
`endif
548
`ifdef VL_PLL0_CLK5
549
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
550
`endif
551
`endif
552 32 unneback
 
553 33 unneback
`ifdef VL_PLL1
554
`ifdef VL_PLL1_CLK1
555
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
556
`endif
557
`ifdef VL_PLL1_CLK2
558
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
559
`endif
560
`ifdef VL_PLL1_CLK3
561
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
562
`endif
563
`ifdef VL_PLL1_CLK4
564
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
565
`endif
566
`ifdef VL_PLL1_CLK5
567
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
568
`endif
569
`endif
570 32 unneback
 
571 33 unneback
`ifdef VL_PLL2
572
`ifdef VL_PLL2_CLK1
573
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
574
`endif
575
`ifdef VL_PLL2_CLK2
576
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
577
`endif
578
`ifdef VL_PLL2_CLK3
579
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
580
`endif
581
`ifdef VL_PLL2_CLK4
582
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
583
`endif
584
`ifdef VL_PLL2_CLK5
585
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
586
`endif
587
`endif
588 32 unneback
 
589 33 unneback
`ifdef VL_PLL3
590
`ifdef VL_PLL3_CLK1
591
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
592
`endif
593
`ifdef VL_PLL3_CLK2
594
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
595
`endif
596
`ifdef VL_PLL3_CLK3
597
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
598
`endif
599
`ifdef VL_PLL3_CLK4
600
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
601
`endif
602
`ifdef VL_PLL3_CLK5
603
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
604
`endif
605
`endif
606 32 unneback
 
607
genvar i;
608
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
609 40 unneback
`define MODULE sync_rst
610
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
611
`undef MODULE
612 32 unneback
end
613
endgenerate
614
endmodule
615
`endif
616
///////////////////////////////////////////////////////////////////////////////
617
 
618
`else
619
 
620 6 unneback
// generic PLL
621 17 unneback
`timescale 1 ps/1 ps
622 40 unneback
`define MODULE pll
623
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
624
`undef MODULE
625 6 unneback
parameter index = 0;
626
parameter number_of_clk = 1;
627 17 unneback
parameter period_time_0 = 20000;
628
parameter period_time_1 = 20000;
629
parameter period_time_2 = 20000;
630 6 unneback
parameter lock_delay = 2000;
631
input clk_i, rst_n_i;
632
output lock;
633
output reg [0:number_of_clk-1] clk_o;
634
output [0:number_of_clk-1] rst_o;
635
 
636
always
637
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
638
 
639
generate if (number_of_clk > 1)
640
always
641
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
642
endgenerate
643
 
644
generate if (number_of_clk > 2)
645
always
646
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
647
endgenerate
648
 
649
genvar i;
650
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
651 40 unneback
`define MODULE sync_rst
652
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
653
`undef MODULE
654 6 unneback
end
655
endgenerate
656
 
657
assign #lock_delay lock = rst_n_i;
658
 
659
endmodule
660
 
661
`endif //altera
662 17 unneback
`endif //actel
663 40 unneback
`undef MODULE
664
`endif//////////////////////////////////////////////////////////////////////
665 6 unneback
////                                                              ////
666
////  Versatile library, registers                                ////
667
////                                                              ////
668
////  Description                                                 ////
669
////  Different type of registers                                 ////
670
////                                                              ////
671
////                                                              ////
672
////  To Do:                                                      ////
673
////   - add more different registers                             ////
674
////                                                              ////
675
////  Author(s):                                                  ////
676
////      - Michael Unneback, unneback@opencores.org              ////
677
////        ORSoC AB                                              ////
678
////                                                              ////
679
//////////////////////////////////////////////////////////////////////
680
////                                                              ////
681
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
682
////                                                              ////
683
//// This source file may be used and distributed without         ////
684
//// restriction provided that this copyright statement is not    ////
685
//// removed from the file and that any derivative work contains  ////
686
//// the original copyright notice and the associated disclaimer. ////
687
////                                                              ////
688
//// This source file is free software; you can redistribute it   ////
689
//// and/or modify it under the terms of the GNU Lesser General   ////
690
//// Public License as published by the Free Software Foundation; ////
691
//// either version 2.1 of the License, or (at your option) any   ////
692
//// later version.                                               ////
693
////                                                              ////
694
//// This source is distributed in the hope that it will be       ////
695
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
696
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
697
//// PURPOSE.  See the GNU Lesser General Public License for more ////
698
//// details.                                                     ////
699
////                                                              ////
700
//// You should have received a copy of the GNU Lesser General    ////
701
//// Public License along with this source; if not, download it   ////
702
//// from http://www.opencores.org/lgpl.shtml                     ////
703
////                                                              ////
704
//////////////////////////////////////////////////////////////////////
705
 
706 40 unneback
`ifdef DFF
707
`define MODULE dff
708
module `BASE`MODULE ( d, q, clk, rst);
709
`undef MODULE
710 6 unneback
        parameter width = 1;
711
        parameter reset_value = 0;
712
 
713
        input [width-1:0] d;
714
        input clk, rst;
715
        output reg [width-1:0] q;
716
 
717
        always @ (posedge clk or posedge rst)
718
        if (rst)
719
                q <= reset_value;
720
        else
721
                q <= d;
722
 
723
endmodule
724 40 unneback
`endif
725 6 unneback
 
726 40 unneback
`ifdef DFF_ARRAY
727
`define MODULE dff_array
728
module `BASE`MODULE ( d, q, clk, rst);
729
`undef MODULE
730 6 unneback
 
731
        parameter width = 1;
732
        parameter depth = 2;
733
        parameter reset_value = 1'b0;
734
 
735
        input [width-1:0] d;
736
        input clk, rst;
737
        output [width-1:0] q;
738
        reg  [0:depth-1] q_tmp [width-1:0];
739
        integer i;
740
        always @ (posedge clk or posedge rst)
741
        if (rst) begin
742
            for (i=0;i<depth;i=i+1)
743
                q_tmp[i] <= {width{reset_value}};
744
        end else begin
745
            q_tmp[0] <= d;
746
            for (i=1;i<depth;i=i+1)
747
                q_tmp[i] <= q_tmp[i-1];
748
        end
749
 
750
    assign q = q_tmp[depth-1];
751
 
752
endmodule
753 40 unneback
`endif
754 6 unneback
 
755 40 unneback
`ifdef DFF_CE
756
`define MODULE dff_ce
757
module `BASE`MODULE ( d, ce, q, clk, rst);
758
`undef MODULE
759 6 unneback
 
760
        parameter width = 1;
761
        parameter reset_value = 0;
762
 
763
        input [width-1:0] d;
764
        input ce, clk, rst;
765
        output reg [width-1:0] q;
766
 
767
        always @ (posedge clk or posedge rst)
768
        if (rst)
769
                q <= reset_value;
770
        else
771
                if (ce)
772
                        q <= d;
773
 
774
endmodule
775 40 unneback
`endif
776 6 unneback
 
777 40 unneback
`ifdef DFF_CE_CLEAR
778
`define MODULE dff_ce_clear
779
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
780
`undef MODULE
781 8 unneback
 
782
        parameter width = 1;
783
        parameter reset_value = 0;
784
 
785
        input [width-1:0] d;
786 10 unneback
        input ce, clear, clk, rst;
787 8 unneback
        output reg [width-1:0] q;
788
 
789
        always @ (posedge clk or posedge rst)
790
        if (rst)
791
            q <= reset_value;
792
        else
793
            if (ce)
794
                if (clear)
795
                    q <= {width{1'b0}};
796
                else
797
                    q <= d;
798
 
799
endmodule
800 40 unneback
`endif
801 8 unneback
 
802 40 unneback
`ifdef DF_CE_SET
803
`define MODULE dff_ce_set
804
module `BASE`MODULE ( d, ce, set, q, clk, rst);
805
`undef MODULE
806 24 unneback
 
807
        parameter width = 1;
808
        parameter reset_value = 0;
809
 
810
        input [width-1:0] d;
811
        input ce, set, clk, rst;
812
        output reg [width-1:0] q;
813
 
814
        always @ (posedge clk or posedge rst)
815
        if (rst)
816
            q <= reset_value;
817
        else
818
            if (ce)
819
                if (set)
820
                    q <= {width{1'b1}};
821
                else
822
                    q <= d;
823
 
824
endmodule
825 40 unneback
`endif
826 24 unneback
 
827 40 unneback
`ifdef SPR
828
`define MODULE spr
829
module `BASE`MODULE ( sp, r, q, clk, rst);
830
`undef MODULE
831
 
832 29 unneback
        parameter width = 1;
833
        parameter reset_value = 0;
834
 
835
        input sp, r;
836
        output reg q;
837
        input clk, rst;
838
 
839
        always @ (posedge clk or posedge rst)
840
        if (rst)
841
            q <= reset_value;
842
        else
843
            if (sp)
844
                q <= 1'b1;
845
            else if (r)
846
                q <= 1'b0;
847
 
848
endmodule
849 40 unneback
`endif
850 29 unneback
 
851 40 unneback
`ifdef SRP
852
`define MODULE srp
853
module `BASE`MODULE ( s, rp, q, clk, rst);
854
`undef MODULE
855
 
856 29 unneback
        parameter width = 1;
857
        parameter reset_value = 0;
858
 
859
        input s, rp;
860
        output reg q;
861
        input clk, rst;
862
 
863
        always @ (posedge clk or posedge rst)
864
        if (rst)
865
            q <= reset_value;
866
        else
867
            if (rp)
868
                q <= 1'b0;
869
            else if (s)
870
                q <= 1'b1;
871
 
872
endmodule
873 40 unneback
`endif
874 29 unneback
 
875 40 unneback
`ifdef ALTERA
876 29 unneback
 
877 40 unneback
`ifdef DFF_SR
878 6 unneback
// megafunction wizard: %LPM_FF%
879
// GENERATION: STANDARD
880
// VERSION: WM1.0
881
// MODULE: lpm_ff 
882
 
883
// ============================================================
884
// File Name: dff_sr.v
885
// Megafunction Name(s):
886
//                      lpm_ff
887
//
888
// Simulation Library Files(s):
889
//                      lpm
890
// ============================================================
891
// ************************************************************
892
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
893
//
894
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
895
// ************************************************************
896
 
897
 
898
//Copyright (C) 1991-2010 Altera Corporation
899
//Your use of Altera Corporation's design tools, logic functions 
900
//and other software and tools, and its AMPP partner logic 
901
//functions, and any output files from any of the foregoing 
902
//(including device programming or simulation files), and any 
903
//associated documentation or information are expressly subject 
904
//to the terms and conditions of the Altera Program License 
905
//Subscription Agreement, Altera MegaCore Function License 
906
//Agreement, or other applicable license agreement, including, 
907
//without limitation, that your use is for the sole purpose of 
908
//programming logic devices manufactured by Altera and sold by 
909
//Altera or its authorized distributors.  Please refer to the 
910
//applicable agreement for further details.
911
 
912
 
913
// synopsys translate_off
914
`timescale 1 ps / 1 ps
915
// synopsys translate_on
916 40 unneback
`define MODULE dff_sr
917
module `BASE`MODULE (
918
`undef MODULE
919
 
920 6 unneback
        aclr,
921
        aset,
922
        clock,
923
        data,
924
        q);
925
 
926
        input     aclr;
927
        input     aset;
928
        input     clock;
929
        input     data;
930
        output    q;
931
 
932
        wire [0:0] sub_wire0;
933
        wire [0:0] sub_wire1 = sub_wire0[0:0];
934
        wire  q = sub_wire1;
935
        wire  sub_wire2 = data;
936
        wire  sub_wire3 = sub_wire2;
937
 
938
        lpm_ff  lpm_ff_component (
939
                                .aclr (aclr),
940
                                .clock (clock),
941
                                .data (sub_wire3),
942
                                .aset (aset),
943
                                .q (sub_wire0)
944
                                // synopsys translate_off
945
                                ,
946
                                .aload (),
947
                                .enable (),
948
                                .sclr (),
949
                                .sload (),
950
                                .sset ()
951
                                // synopsys translate_on
952
                                );
953
        defparam
954
                lpm_ff_component.lpm_fftype = "DFF",
955
                lpm_ff_component.lpm_type = "LPM_FF",
956
                lpm_ff_component.lpm_width = 1;
957
 
958
 
959
endmodule
960
 
961
// ============================================================
962
// CNX file retrieval info
963
// ============================================================
964
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
965
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
966
// Retrieval info: PRIVATE: ASET NUMERIC "1"
967
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
968
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
969
// Retrieval info: PRIVATE: DFF NUMERIC "1"
970
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
971
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
972
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
973
// Retrieval info: PRIVATE: SSET NUMERIC "0"
974
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
975
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
976
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
977
// Retrieval info: PRIVATE: nBit NUMERIC "1"
978
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
979
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
980
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
981
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
982
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
983
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
984
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
985
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
986
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
987
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
988
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
989
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
990
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
991
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
992
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
993
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
994
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
995
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
996
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
997
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
998
// Retrieval info: LIB_FILE: lpm
999 40 unneback
`endif
1000 6 unneback
 
1001
`else
1002
 
1003 40 unneback
`ifdef DFF_SR
1004
`define MODULE dff_sr
1005
module `BASE`MODULE ( aclr, aset, clock, data, q);
1006
`undef MODULE
1007 6 unneback
 
1008
    input         aclr;
1009
    input         aset;
1010
    input         clock;
1011
    input         data;
1012
    output reg    q;
1013
 
1014
   always @ (posedge clock or posedge aclr or posedge aset)
1015
     if (aclr)
1016
       q <= 1'b0;
1017
     else if (aset)
1018
       q <= 1'b1;
1019
     else
1020
       q <= data;
1021
 
1022
endmodule
1023 40 unneback
`endif
1024 6 unneback
 
1025
`endif
1026
 
1027
// LATCH
1028
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1029
`ifdef ALTERA
1030 40 unneback
 
1031
`ifdef LATCH
1032
`define MODULE latch
1033
module `BASE`MODULE ( d, le, q, clk);
1034
`undef MODULE
1035 6 unneback
input d, le;
1036
output q;
1037
input clk;
1038
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1039
endmodule
1040 40 unneback
`endif
1041
 
1042 6 unneback
`else
1043 40 unneback
 
1044
`ifdef LATCH
1045
`define MODULE latch
1046
module `BASE`MODULE ( d, le, q, clk);
1047
`undef MODULE
1048 6 unneback
input d, le;
1049 48 unneback
input clk;
1050
always @ (le or d)
1051 60 unneback
if (le)
1052 48 unneback
    d <= q;
1053 6 unneback
endmodule
1054 15 unneback
`endif
1055
 
1056 40 unneback
`endif
1057
 
1058
`ifdef SHREG
1059
`define MODULE shreg
1060
module `BASE`MODULE ( d, q, clk, rst);
1061
`undef MODULE
1062
 
1063 17 unneback
parameter depth = 10;
1064
input d;
1065
output q;
1066
input clk, rst;
1067
 
1068
reg [1:depth] dffs;
1069
 
1070
always @ (posedge clk or posedge rst)
1071
if (rst)
1072
    dffs <= {depth{1'b0}};
1073
else
1074
    dffs <= {d,dffs[1:depth-1]};
1075
assign q = dffs[depth];
1076
endmodule
1077 40 unneback
`endif
1078 17 unneback
 
1079 40 unneback
`ifdef SHREG_CE
1080
`define MODULE shreg_ce
1081
module `BASE`MODULE ( d, ce, q, clk, rst);
1082
`undef MODULE
1083 17 unneback
parameter depth = 10;
1084
input d, ce;
1085
output q;
1086
input clk, rst;
1087
 
1088
reg [1:depth] dffs;
1089
 
1090
always @ (posedge clk or posedge rst)
1091
if (rst)
1092
    dffs <= {depth{1'b0}};
1093
else
1094
    if (ce)
1095
        dffs <= {d,dffs[1:depth-1]};
1096
assign q = dffs[depth];
1097
endmodule
1098 40 unneback
`endif
1099 17 unneback
 
1100 40 unneback
`ifdef DELAY
1101
`define MODULE delay
1102
module `BASE`MODULE ( d, q, clk, rst);
1103
`undef MODULE
1104 15 unneback
parameter depth = 10;
1105
input d;
1106
output q;
1107
input clk, rst;
1108
 
1109
reg [1:depth] dffs;
1110
 
1111
always @ (posedge clk or posedge rst)
1112
if (rst)
1113
    dffs <= {depth{1'b0}};
1114
else
1115
    dffs <= {d,dffs[1:depth-1]};
1116
assign q = dffs[depth];
1117 17 unneback
endmodule
1118 40 unneback
`endif
1119 17 unneback
 
1120 40 unneback
`ifdef DELAY_EMPTYFLAG
1121
`define MODULE delay_emptyflag
1122 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1123 40 unneback
`undef MODULE
1124 17 unneback
parameter depth = 10;
1125
input d;
1126
output q, emptyflag;
1127
input clk, rst;
1128
 
1129
reg [1:depth] dffs;
1130
 
1131
always @ (posedge clk or posedge rst)
1132
if (rst)
1133
    dffs <= {depth{1'b0}};
1134
else
1135
    dffs <= {d,dffs[1:depth-1]};
1136
assign q = dffs[depth];
1137
assign emptyflag = !(|dffs);
1138
endmodule
1139 40 unneback
`endif
1140 17 unneback
//////////////////////////////////////////////////////////////////////
1141 6 unneback
////                                                              ////
1142 18 unneback
////  Logic functions                                             ////
1143
////                                                              ////
1144
////  Description                                                 ////
1145
////  Logic functions such as multiplexers                        ////
1146
////                                                              ////
1147
////                                                              ////
1148
////  To Do:                                                      ////
1149
////   -                                                          ////
1150
////                                                              ////
1151
////  Author(s):                                                  ////
1152
////      - Michael Unneback, unneback@opencores.org              ////
1153
////        ORSoC AB                                              ////
1154
////                                                              ////
1155
//////////////////////////////////////////////////////////////////////
1156
////                                                              ////
1157
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1158
////                                                              ////
1159
//// This source file may be used and distributed without         ////
1160
//// restriction provided that this copyright statement is not    ////
1161
//// removed from the file and that any derivative work contains  ////
1162
//// the original copyright notice and the associated disclaimer. ////
1163
////                                                              ////
1164
//// This source file is free software; you can redistribute it   ////
1165
//// and/or modify it under the terms of the GNU Lesser General   ////
1166
//// Public License as published by the Free Software Foundation; ////
1167
//// either version 2.1 of the License, or (at your option) any   ////
1168
//// later version.                                               ////
1169
////                                                              ////
1170
//// This source is distributed in the hope that it will be       ////
1171
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1172
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1173
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1174
//// details.                                                     ////
1175
////                                                              ////
1176
//// You should have received a copy of the GNU Lesser General    ////
1177
//// Public License along with this source; if not, download it   ////
1178
//// from http://www.opencores.org/lgpl.shtml                     ////
1179
////                                                              ////
1180
//////////////////////////////////////////////////////////////////////
1181 40 unneback
`ifdef MUX_ANDOR
1182
`define MODULE mux_andor
1183
module `BASE`MODULE ( a, sel, dout);
1184
`undef MODULE
1185 36 unneback
 
1186
parameter width = 32;
1187
parameter nr_of_ports = 4;
1188
 
1189
input [nr_of_ports*width-1:0] a;
1190
input [nr_of_ports-1:0] sel;
1191
output reg [width-1:0] dout;
1192
 
1193 38 unneback
integer i,j;
1194
 
1195 36 unneback
always @ (a, sel)
1196
begin
1197
    dout = a[width-1:0] & {width{sel[0]}};
1198 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1199
        for (j=0;j<width;j=j+1)
1200
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1201 36 unneback
end
1202
 
1203
endmodule
1204 40 unneback
`endif
1205 36 unneback
 
1206 40 unneback
`ifdef MUX2_ANDOR
1207
`define MODULE mux2_andor
1208
module `BASE`MODULE ( a1, a0, sel, dout);
1209
`undef MODULE
1210 18 unneback
 
1211 34 unneback
parameter width = 32;
1212 35 unneback
localparam nr_of_ports = 2;
1213 34 unneback
input [width-1:0] a1, a0;
1214
input [nr_of_ports-1:0] sel;
1215
output [width-1:0] dout;
1216
 
1217 40 unneback
`define MODULE mux_andor
1218
`BASE`MODULE
1219 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1220 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1221 40 unneback
`undef MODULE
1222
 
1223 34 unneback
endmodule
1224 40 unneback
`endif
1225 34 unneback
 
1226 40 unneback
`ifdef MUX3_ANDOR
1227
`define MODULE mux3_andor
1228
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1229
`undef MODULE
1230 34 unneback
 
1231
parameter width = 32;
1232 35 unneback
localparam nr_of_ports = 3;
1233 34 unneback
input [width-1:0] a2, a1, a0;
1234
input [nr_of_ports-1:0] sel;
1235
output [width-1:0] dout;
1236
 
1237 40 unneback
`define MODULE mux_andor
1238
`BASE`MODULE
1239 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1240 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1241 40 unneback
`undef MODULE
1242 34 unneback
endmodule
1243 40 unneback
`endif
1244 34 unneback
 
1245 40 unneback
`ifdef MUX4_ANDOR
1246
`define MODULE mux4_andor
1247
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1248
`undef MODULE
1249 18 unneback
 
1250
parameter width = 32;
1251 35 unneback
localparam nr_of_ports = 4;
1252 18 unneback
input [width-1:0] a3, a2, a1, a0;
1253
input [nr_of_ports-1:0] sel;
1254 22 unneback
output [width-1:0] dout;
1255 18 unneback
 
1256 40 unneback
`define MODULE mux_andor
1257
`BASE`MODULE
1258 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1259 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1260 40 unneback
`undef MODULE
1261 18 unneback
 
1262
endmodule
1263 40 unneback
`endif
1264 18 unneback
 
1265 40 unneback
`ifdef MUX5_ANDOR
1266
`define MODULE mux5_andor
1267
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1268
`undef MODULE
1269 18 unneback
 
1270
parameter width = 32;
1271 35 unneback
localparam nr_of_ports = 5;
1272 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1273
input [nr_of_ports-1:0] sel;
1274 22 unneback
output [width-1:0] dout;
1275 18 unneback
 
1276 40 unneback
`define MODULE mux_andor
1277
`BASE`MODULE
1278 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1279 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1280 40 unneback
`undef MODULE
1281 18 unneback
 
1282
endmodule
1283 40 unneback
`endif
1284 18 unneback
 
1285 40 unneback
`ifdef MUX6_ANDOR
1286
`define MODULE mux6_andor
1287
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1288
`undef MODULE
1289 18 unneback
 
1290
parameter width = 32;
1291 35 unneback
localparam nr_of_ports = 6;
1292 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1293
input [nr_of_ports-1:0] sel;
1294 22 unneback
output [width-1:0] dout;
1295 18 unneback
 
1296 40 unneback
`define MODULE mux_andor
1297
`BASE`MODULE
1298 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1299 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1300 40 unneback
`undef MODULE
1301 18 unneback
 
1302
endmodule
1303 40 unneback
`endif
1304 43 unneback
 
1305
`ifdef PARITY
1306
 
1307
`define MODULE parity_generate
1308
module `BASE`MODULE (data, parity);
1309
`undef MODULE
1310
parameter word_size = 32;
1311
parameter chunk_size = 8;
1312
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1313
input [word_size-1:0] data;
1314
output reg [word_size/chunk_size-1:0] parity;
1315
integer i,j;
1316
always @ (data)
1317
for (i=0;i<word_size/chunk_size;i=i+1) begin
1318
    parity[i] = parity_type;
1319
    for (j=0;j<chunk_size;j=j+1) begin
1320 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1321 43 unneback
    end
1322
end
1323
endmodule
1324
 
1325
`define MODULE parity_check
1326
module `BASE`MODULE( data, parity, parity_error);
1327
`undef MODULE
1328
parameter word_size = 32;
1329
parameter chunk_size = 8;
1330
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1331
input [word_size-1:0] data;
1332
input [word_size/chunk_size-1:0] parity;
1333
output parity_error;
1334 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1335 43 unneback
integer i,j;
1336
always @ (data or parity)
1337
for (i=0;i<word_size/chunk_size;i=i+1) begin
1338
    error_flag[i] = parity[i] ^ parity_type;
1339
    for (j=0;j<chunk_size;j=j+1) begin
1340 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1341 43 unneback
    end
1342
end
1343
assign parity_error = |error_flag;
1344
endmodule
1345
 
1346 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1347
////                                                              ////
1348
////  IO functions                                                ////
1349
////                                                              ////
1350
////  Description                                                 ////
1351
////  IO functions such as IOB flip-flops                         ////
1352
////                                                              ////
1353
////                                                              ////
1354
////  To Do:                                                      ////
1355
////   -                                                          ////
1356
////                                                              ////
1357
////  Author(s):                                                  ////
1358
////      - Michael Unneback, unneback@opencores.org              ////
1359
////        ORSoC AB                                              ////
1360
////                                                              ////
1361 18 unneback
//////////////////////////////////////////////////////////////////////
1362
////                                                              ////
1363 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1364
////                                                              ////
1365
//// This source file may be used and distributed without         ////
1366
//// restriction provided that this copyright statement is not    ////
1367
//// removed from the file and that any derivative work contains  ////
1368
//// the original copyright notice and the associated disclaimer. ////
1369
////                                                              ////
1370
//// This source file is free software; you can redistribute it   ////
1371
//// and/or modify it under the terms of the GNU Lesser General   ////
1372
//// Public License as published by the Free Software Foundation; ////
1373
//// either version 2.1 of the License, or (at your option) any   ////
1374
//// later version.                                               ////
1375
////                                                              ////
1376
//// This source is distributed in the hope that it will be       ////
1377
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1378
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1379
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1380
//// details.                                                     ////
1381
////                                                              ////
1382
//// You should have received a copy of the GNU Lesser General    ////
1383
//// Public License along with this source; if not, download it   ////
1384
//// from http://www.opencores.org/lgpl.shtml                     ////
1385
////                                                              ////
1386
//////////////////////////////////////////////////////////////////////
1387 45 unneback
`timescale 1ns/1ns
1388 44 unneback
`ifdef O_DFF
1389
`define MODULE o_dff
1390
module `BASE`MODULE (d_i, o_pad, clk, rst);
1391
`undef MODULE
1392
parameter width = 1;
1393 45 unneback
parameter reset_value = {width{1'b0}};
1394
input  [width-1:0]  d_i;
1395 44 unneback
output [width-1:0] o_pad;
1396
input clk, rst;
1397
wire [width-1:0] d_i_int `SYN_KEEP;
1398 45 unneback
reg  [width-1:0] o_pad_int;
1399 44 unneback
assign d_i_int = d_i;
1400
genvar i;
1401 45 unneback
generate
1402 44 unneback
for (i=0;i<width;i=i+1) begin
1403
    always @ (posedge clk or posedge rst)
1404
    if (rst)
1405 45 unneback
        o_pad_int[i] <= reset_value[i];
1406 44 unneback
    else
1407 45 unneback
        o_pad_int[i] <= d_i_int[i];
1408
    assign #1 o_pad[i] = o_pad_int[i];
1409 44 unneback
end
1410
endgenerate
1411
endmodule
1412
`endif
1413
 
1414 45 unneback
`timescale 1ns/1ns
1415 44 unneback
`ifdef IO_DFF_OE
1416
`define MODULE io_dff_oe
1417
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1418
`undef MODULE
1419
parameter width = 1;
1420
input  [width-1:0] d_o;
1421
output reg [width-1:0] d_i;
1422
input oe;
1423
inout [width-1:0] io_pad;
1424
input clk, rst;
1425
wire [width-1:0] oe_d `SYN_KEEP;
1426
reg [width-1:0] oe_q;
1427
reg [width-1:0] d_o_q;
1428
assign oe_d = {width{oe}};
1429
genvar i;
1430
generate
1431
for (i=0;i<width;i=i+1) begin
1432
    always @ (posedge clk or posedge rst)
1433
    if (rst)
1434
        oe_q[i] <= 1'b0;
1435
    else
1436
        oe_q[i] <= oe_d[i];
1437
    always @ (posedge clk or posedge rst)
1438
    if (rst)
1439
        d_o_q[i] <= 1'b0;
1440
    else
1441
        d_o_q[i] <= d_o[i];
1442
    always @ (posedge clk or posedge rst)
1443
    if (rst)
1444
        d_i[i] <= 1'b0;
1445
    else
1446
        d_i[i] <= io_pad[i];
1447 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1448 44 unneback
end
1449
endgenerate
1450
endmodule
1451
`endif
1452
`ifdef CNT_BIN
1453
//////////////////////////////////////////////////////////////////////
1454
////                                                              ////
1455 6 unneback
////  Versatile counter                                           ////
1456
////                                                              ////
1457
////  Description                                                 ////
1458
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1459
////  counter                                                     ////
1460
////                                                              ////
1461
////  To Do:                                                      ////
1462
////   - add LFSR with more taps                                  ////
1463
////                                                              ////
1464
////  Author(s):                                                  ////
1465
////      - Michael Unneback, unneback@opencores.org              ////
1466
////        ORSoC AB                                              ////
1467
////                                                              ////
1468
//////////////////////////////////////////////////////////////////////
1469
////                                                              ////
1470
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1471
////                                                              ////
1472
//// This source file may be used and distributed without         ////
1473
//// restriction provided that this copyright statement is not    ////
1474
//// removed from the file and that any derivative work contains  ////
1475
//// the original copyright notice and the associated disclaimer. ////
1476
////                                                              ////
1477
//// This source file is free software; you can redistribute it   ////
1478
//// and/or modify it under the terms of the GNU Lesser General   ////
1479
//// Public License as published by the Free Software Foundation; ////
1480
//// either version 2.1 of the License, or (at your option) any   ////
1481
//// later version.                                               ////
1482
////                                                              ////
1483
//// This source is distributed in the hope that it will be       ////
1484
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1485
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1486
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1487
//// details.                                                     ////
1488
////                                                              ////
1489
//// You should have received a copy of the GNU Lesser General    ////
1490
//// Public License along with this source; if not, download it   ////
1491
//// from http://www.opencores.org/lgpl.shtml                     ////
1492
////                                                              ////
1493
//////////////////////////////////////////////////////////////////////
1494
 
1495
// binary counter
1496 22 unneback
 
1497 40 unneback
`define MODULE cnt_bin
1498
module `BASE`MODULE (
1499
`undef MODULE
1500
 q, rst, clk);
1501
 
1502 22 unneback
   parameter length = 4;
1503
   output [length:1] q;
1504
   input rst;
1505
   input clk;
1506
 
1507
   parameter clear_value = 0;
1508
   parameter set_value = 1;
1509
   parameter wrap_value = 0;
1510
   parameter level1_value = 15;
1511
 
1512
   reg  [length:1] qi;
1513
   wire [length:1] q_next;
1514
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1515
 
1516
   always @ (posedge clk or posedge rst)
1517
     if (rst)
1518
       qi <= {length{1'b0}};
1519
     else
1520
       qi <= q_next;
1521
 
1522
   assign q = qi;
1523
 
1524
endmodule
1525 40 unneback
`endif
1526
`ifdef CNT_BIN_CLEAR
1527 22 unneback
//////////////////////////////////////////////////////////////////////
1528
////                                                              ////
1529
////  Versatile counter                                           ////
1530
////                                                              ////
1531
////  Description                                                 ////
1532
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1533
////  counter                                                     ////
1534
////                                                              ////
1535
////  To Do:                                                      ////
1536
////   - add LFSR with more taps                                  ////
1537
////                                                              ////
1538
////  Author(s):                                                  ////
1539
////      - Michael Unneback, unneback@opencores.org              ////
1540
////        ORSoC AB                                              ////
1541
////                                                              ////
1542
//////////////////////////////////////////////////////////////////////
1543
////                                                              ////
1544
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1545
////                                                              ////
1546
//// This source file may be used and distributed without         ////
1547
//// restriction provided that this copyright statement is not    ////
1548
//// removed from the file and that any derivative work contains  ////
1549
//// the original copyright notice and the associated disclaimer. ////
1550
////                                                              ////
1551
//// This source file is free software; you can redistribute it   ////
1552
//// and/or modify it under the terms of the GNU Lesser General   ////
1553
//// Public License as published by the Free Software Foundation; ////
1554
//// either version 2.1 of the License, or (at your option) any   ////
1555
//// later version.                                               ////
1556
////                                                              ////
1557
//// This source is distributed in the hope that it will be       ////
1558
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1559
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1560
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1561
//// details.                                                     ////
1562
////                                                              ////
1563
//// You should have received a copy of the GNU Lesser General    ////
1564
//// Public License along with this source; if not, download it   ////
1565
//// from http://www.opencores.org/lgpl.shtml                     ////
1566
////                                                              ////
1567
//////////////////////////////////////////////////////////////////////
1568
 
1569
// binary counter
1570
 
1571 40 unneback
`define MODULE cnt_bin_clear
1572
module `BASE`MODULE (
1573
`undef MODULE
1574
 clear, q, rst, clk);
1575
 
1576 22 unneback
   parameter length = 4;
1577
   input clear;
1578
   output [length:1] q;
1579
   input rst;
1580
   input clk;
1581
 
1582
   parameter clear_value = 0;
1583
   parameter set_value = 1;
1584
   parameter wrap_value = 0;
1585
   parameter level1_value = 15;
1586
 
1587
   reg  [length:1] qi;
1588
   wire [length:1] q_next;
1589
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1590
 
1591
   always @ (posedge clk or posedge rst)
1592
     if (rst)
1593
       qi <= {length{1'b0}};
1594
     else
1595
       qi <= q_next;
1596
 
1597
   assign q = qi;
1598
 
1599
endmodule
1600 40 unneback
`endif
1601
`ifdef CNT_BIN_CE
1602 22 unneback
//////////////////////////////////////////////////////////////////////
1603
////                                                              ////
1604
////  Versatile counter                                           ////
1605
////                                                              ////
1606
////  Description                                                 ////
1607
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1608
////  counter                                                     ////
1609
////                                                              ////
1610
////  To Do:                                                      ////
1611
////   - add LFSR with more taps                                  ////
1612
////                                                              ////
1613
////  Author(s):                                                  ////
1614
////      - Michael Unneback, unneback@opencores.org              ////
1615
////        ORSoC AB                                              ////
1616
////                                                              ////
1617
//////////////////////////////////////////////////////////////////////
1618
////                                                              ////
1619
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1620
////                                                              ////
1621
//// This source file may be used and distributed without         ////
1622
//// restriction provided that this copyright statement is not    ////
1623
//// removed from the file and that any derivative work contains  ////
1624
//// the original copyright notice and the associated disclaimer. ////
1625
////                                                              ////
1626
//// This source file is free software; you can redistribute it   ////
1627
//// and/or modify it under the terms of the GNU Lesser General   ////
1628
//// Public License as published by the Free Software Foundation; ////
1629
//// either version 2.1 of the License, or (at your option) any   ////
1630
//// later version.                                               ////
1631
////                                                              ////
1632
//// This source is distributed in the hope that it will be       ////
1633
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1634
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1635
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1636
//// details.                                                     ////
1637
////                                                              ////
1638
//// You should have received a copy of the GNU Lesser General    ////
1639
//// Public License along with this source; if not, download it   ////
1640
//// from http://www.opencores.org/lgpl.shtml                     ////
1641
////                                                              ////
1642
//////////////////////////////////////////////////////////////////////
1643
 
1644
// binary counter
1645 6 unneback
 
1646 40 unneback
`define MODULE cnt_bin_ce
1647
module `BASE`MODULE (
1648
`undef MODULE
1649
 cke, q, rst, clk);
1650
 
1651 6 unneback
   parameter length = 4;
1652
   input cke;
1653
   output [length:1] q;
1654
   input rst;
1655
   input clk;
1656
 
1657
   parameter clear_value = 0;
1658
   parameter set_value = 1;
1659
   parameter wrap_value = 0;
1660
   parameter level1_value = 15;
1661
 
1662
   reg  [length:1] qi;
1663
   wire [length:1] q_next;
1664
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1665
 
1666
   always @ (posedge clk or posedge rst)
1667
     if (rst)
1668
       qi <= {length{1'b0}};
1669
     else
1670
     if (cke)
1671
       qi <= q_next;
1672
 
1673
   assign q = qi;
1674
 
1675
endmodule
1676 40 unneback
`endif
1677
`ifdef CNT_BIN_CE_CLEAR
1678 6 unneback
//////////////////////////////////////////////////////////////////////
1679
////                                                              ////
1680
////  Versatile counter                                           ////
1681
////                                                              ////
1682
////  Description                                                 ////
1683
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1684
////  counter                                                     ////
1685
////                                                              ////
1686
////  To Do:                                                      ////
1687
////   - add LFSR with more taps                                  ////
1688
////                                                              ////
1689
////  Author(s):                                                  ////
1690
////      - Michael Unneback, unneback@opencores.org              ////
1691
////        ORSoC AB                                              ////
1692
////                                                              ////
1693
//////////////////////////////////////////////////////////////////////
1694
////                                                              ////
1695
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1696
////                                                              ////
1697
//// This source file may be used and distributed without         ////
1698
//// restriction provided that this copyright statement is not    ////
1699
//// removed from the file and that any derivative work contains  ////
1700
//// the original copyright notice and the associated disclaimer. ////
1701
////                                                              ////
1702
//// This source file is free software; you can redistribute it   ////
1703
//// and/or modify it under the terms of the GNU Lesser General   ////
1704
//// Public License as published by the Free Software Foundation; ////
1705
//// either version 2.1 of the License, or (at your option) any   ////
1706
//// later version.                                               ////
1707
////                                                              ////
1708
//// This source is distributed in the hope that it will be       ////
1709
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1710
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1711
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1712
//// details.                                                     ////
1713
////                                                              ////
1714
//// You should have received a copy of the GNU Lesser General    ////
1715
//// Public License along with this source; if not, download it   ////
1716
//// from http://www.opencores.org/lgpl.shtml                     ////
1717
////                                                              ////
1718
//////////////////////////////////////////////////////////////////////
1719
 
1720
// binary counter
1721
 
1722 40 unneback
`define MODULE cnt_bin_ce_clear
1723
module `BASE`MODULE (
1724
`undef MODULE
1725
 clear, cke, q, rst, clk);
1726
 
1727 6 unneback
   parameter length = 4;
1728
   input clear;
1729
   input cke;
1730
   output [length:1] q;
1731
   input rst;
1732
   input clk;
1733
 
1734
   parameter clear_value = 0;
1735
   parameter set_value = 1;
1736
   parameter wrap_value = 0;
1737
   parameter level1_value = 15;
1738
 
1739
   reg  [length:1] qi;
1740
   wire [length:1] q_next;
1741
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1742
 
1743
   always @ (posedge clk or posedge rst)
1744
     if (rst)
1745
       qi <= {length{1'b0}};
1746
     else
1747
     if (cke)
1748
       qi <= q_next;
1749
 
1750
   assign q = qi;
1751
 
1752
endmodule
1753 40 unneback
`endif
1754
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1755 6 unneback
//////////////////////////////////////////////////////////////////////
1756
////                                                              ////
1757
////  Versatile counter                                           ////
1758
////                                                              ////
1759
////  Description                                                 ////
1760
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1761
////  counter                                                     ////
1762
////                                                              ////
1763
////  To Do:                                                      ////
1764
////   - add LFSR with more taps                                  ////
1765
////                                                              ////
1766
////  Author(s):                                                  ////
1767
////      - Michael Unneback, unneback@opencores.org              ////
1768
////        ORSoC AB                                              ////
1769
////                                                              ////
1770
//////////////////////////////////////////////////////////////////////
1771
////                                                              ////
1772
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1773
////                                                              ////
1774
//// This source file may be used and distributed without         ////
1775
//// restriction provided that this copyright statement is not    ////
1776
//// removed from the file and that any derivative work contains  ////
1777
//// the original copyright notice and the associated disclaimer. ////
1778
////                                                              ////
1779
//// This source file is free software; you can redistribute it   ////
1780
//// and/or modify it under the terms of the GNU Lesser General   ////
1781
//// Public License as published by the Free Software Foundation; ////
1782
//// either version 2.1 of the License, or (at your option) any   ////
1783
//// later version.                                               ////
1784
////                                                              ////
1785
//// This source is distributed in the hope that it will be       ////
1786
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1787
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1788
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1789
//// details.                                                     ////
1790
////                                                              ////
1791
//// You should have received a copy of the GNU Lesser General    ////
1792
//// Public License along with this source; if not, download it   ////
1793
//// from http://www.opencores.org/lgpl.shtml                     ////
1794
////                                                              ////
1795
//////////////////////////////////////////////////////////////////////
1796
 
1797
// binary counter
1798 29 unneback
 
1799 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1800
module `BASE`MODULE (
1801
`undef MODULE
1802
 clear, cke, q, level1, level2, rst, clk);
1803
 
1804 29 unneback
   parameter length = 4;
1805
   input clear;
1806
   input cke;
1807
   output [length:1] q;
1808
   output reg level1;
1809
   output reg level2;
1810
   input rst;
1811
   input clk;
1812
 
1813
   parameter clear_value = 0;
1814
   parameter set_value = 1;
1815 30 unneback
   parameter wrap_value = 15;
1816
   parameter level1_value = 8;
1817
   parameter level2_value = 15;
1818 29 unneback
 
1819
   wire rew;
1820 30 unneback
   assign rew = 1'b0;
1821 29 unneback
   reg  [length:1] qi;
1822
   wire [length:1] q_next;
1823
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1824
 
1825
   always @ (posedge clk or posedge rst)
1826
     if (rst)
1827
       qi <= {length{1'b0}};
1828
     else
1829
     if (cke)
1830
       qi <= q_next;
1831
 
1832
   assign q = qi;
1833
 
1834
 
1835
    always @ (posedge clk or posedge rst)
1836
    if (rst)
1837
        level1 <= 1'b0;
1838
    else
1839
    if (cke)
1840
    if (clear)
1841
        level1 <= 1'b0;
1842
    else if (q_next == level1_value)
1843
        level1 <= 1'b1;
1844
    else if (qi == level1_value & rew)
1845
        level1 <= 1'b0;
1846
 
1847
    always @ (posedge clk or posedge rst)
1848
    if (rst)
1849
        level2 <= 1'b0;
1850
    else
1851
    if (cke)
1852
    if (clear)
1853
        level2 <= 1'b0;
1854
    else if (q_next == level2_value)
1855
        level2 <= 1'b1;
1856
    else if (qi == level2_value & rew)
1857
        level2 <= 1'b0;
1858
endmodule
1859 40 unneback
`endif
1860
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1861 29 unneback
//////////////////////////////////////////////////////////////////////
1862
////                                                              ////
1863
////  Versatile counter                                           ////
1864
////                                                              ////
1865
////  Description                                                 ////
1866
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1867
////  counter                                                     ////
1868
////                                                              ////
1869
////  To Do:                                                      ////
1870
////   - add LFSR with more taps                                  ////
1871
////                                                              ////
1872
////  Author(s):                                                  ////
1873
////      - Michael Unneback, unneback@opencores.org              ////
1874
////        ORSoC AB                                              ////
1875
////                                                              ////
1876
//////////////////////////////////////////////////////////////////////
1877
////                                                              ////
1878
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1879
////                                                              ////
1880
//// This source file may be used and distributed without         ////
1881
//// restriction provided that this copyright statement is not    ////
1882
//// removed from the file and that any derivative work contains  ////
1883
//// the original copyright notice and the associated disclaimer. ////
1884
////                                                              ////
1885
//// This source file is free software; you can redistribute it   ////
1886
//// and/or modify it under the terms of the GNU Lesser General   ////
1887
//// Public License as published by the Free Software Foundation; ////
1888
//// either version 2.1 of the License, or (at your option) any   ////
1889
//// later version.                                               ////
1890
////                                                              ////
1891
//// This source is distributed in the hope that it will be       ////
1892
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1893
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1894
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1895
//// details.                                                     ////
1896
////                                                              ////
1897
//// You should have received a copy of the GNU Lesser General    ////
1898
//// Public License along with this source; if not, download it   ////
1899
//// from http://www.opencores.org/lgpl.shtml                     ////
1900
////                                                              ////
1901
//////////////////////////////////////////////////////////////////////
1902
 
1903
// binary counter
1904 6 unneback
 
1905 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1906
module `BASE`MODULE (
1907
`undef MODULE
1908
 clear, set, cke, rew, q, rst, clk);
1909
 
1910 6 unneback
   parameter length = 4;
1911
   input clear;
1912
   input set;
1913
   input cke;
1914
   input rew;
1915
   output [length:1] q;
1916
   input rst;
1917
   input clk;
1918
 
1919
   parameter clear_value = 0;
1920
   parameter set_value = 1;
1921
   parameter wrap_value = 0;
1922
   parameter level1_value = 15;
1923
 
1924
   reg  [length:1] qi;
1925
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1926
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1927
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1928
   assign q_next = rew ? q_next_rew : q_next_fw;
1929
 
1930
   always @ (posedge clk or posedge rst)
1931
     if (rst)
1932
       qi <= {length{1'b0}};
1933
     else
1934
     if (cke)
1935
       qi <= q_next;
1936
 
1937
   assign q = qi;
1938
 
1939
endmodule
1940 40 unneback
`endif
1941
`ifdef CNT_BIN_CE_REW_L1
1942 6 unneback
//////////////////////////////////////////////////////////////////////
1943
////                                                              ////
1944
////  Versatile counter                                           ////
1945
////                                                              ////
1946
////  Description                                                 ////
1947
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1948
////  counter                                                     ////
1949
////                                                              ////
1950
////  To Do:                                                      ////
1951
////   - add LFSR with more taps                                  ////
1952
////                                                              ////
1953
////  Author(s):                                                  ////
1954
////      - Michael Unneback, unneback@opencores.org              ////
1955
////        ORSoC AB                                              ////
1956
////                                                              ////
1957
//////////////////////////////////////////////////////////////////////
1958
////                                                              ////
1959
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1960
////                                                              ////
1961
//// This source file may be used and distributed without         ////
1962
//// restriction provided that this copyright statement is not    ////
1963
//// removed from the file and that any derivative work contains  ////
1964
//// the original copyright notice and the associated disclaimer. ////
1965
////                                                              ////
1966
//// This source file is free software; you can redistribute it   ////
1967
//// and/or modify it under the terms of the GNU Lesser General   ////
1968
//// Public License as published by the Free Software Foundation; ////
1969
//// either version 2.1 of the License, or (at your option) any   ////
1970
//// later version.                                               ////
1971
////                                                              ////
1972
//// This source is distributed in the hope that it will be       ////
1973
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1974
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1975
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1976
//// details.                                                     ////
1977
////                                                              ////
1978
//// You should have received a copy of the GNU Lesser General    ////
1979
//// Public License along with this source; if not, download it   ////
1980
//// from http://www.opencores.org/lgpl.shtml                     ////
1981
////                                                              ////
1982
//////////////////////////////////////////////////////////////////////
1983
 
1984
// binary counter
1985
 
1986 40 unneback
`define MODULE cnt_bin_ce_rew_l1
1987
module `BASE`MODULE (
1988
`undef MODULE
1989
 cke, rew, level1, rst, clk);
1990
 
1991 6 unneback
   parameter length = 4;
1992
   input cke;
1993
   input rew;
1994
   output reg level1;
1995
   input rst;
1996
   input clk;
1997
 
1998
   parameter clear_value = 0;
1999
   parameter set_value = 1;
2000
   parameter wrap_value = 1;
2001
   parameter level1_value = 15;
2002
 
2003 29 unneback
   wire clear;
2004 30 unneback
   assign clear = 1'b0;
2005 6 unneback
   reg  [length:1] qi;
2006
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2007
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2008
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2009
   assign q_next = rew ? q_next_rew : q_next_fw;
2010
 
2011
   always @ (posedge clk or posedge rst)
2012
     if (rst)
2013
       qi <= {length{1'b0}};
2014
     else
2015
     if (cke)
2016
       qi <= q_next;
2017
 
2018
 
2019
 
2020
    always @ (posedge clk or posedge rst)
2021
    if (rst)
2022
        level1 <= 1'b0;
2023
    else
2024
    if (cke)
2025 29 unneback
    if (clear)
2026
        level1 <= 1'b0;
2027
    else if (q_next == level1_value)
2028 6 unneback
        level1 <= 1'b1;
2029
    else if (qi == level1_value & rew)
2030
        level1 <= 1'b0;
2031
endmodule
2032 40 unneback
`endif
2033
`ifdef CNT_BIN_CE_REW_ZQ_L1
2034 6 unneback
//////////////////////////////////////////////////////////////////////
2035
////                                                              ////
2036
////  Versatile counter                                           ////
2037
////                                                              ////
2038
////  Description                                                 ////
2039
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2040
////  counter                                                     ////
2041
////                                                              ////
2042
////  To Do:                                                      ////
2043
////   - add LFSR with more taps                                  ////
2044
////                                                              ////
2045
////  Author(s):                                                  ////
2046
////      - Michael Unneback, unneback@opencores.org              ////
2047
////        ORSoC AB                                              ////
2048
////                                                              ////
2049
//////////////////////////////////////////////////////////////////////
2050
////                                                              ////
2051
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2052
////                                                              ////
2053
//// This source file may be used and distributed without         ////
2054
//// restriction provided that this copyright statement is not    ////
2055
//// removed from the file and that any derivative work contains  ////
2056
//// the original copyright notice and the associated disclaimer. ////
2057
////                                                              ////
2058
//// This source file is free software; you can redistribute it   ////
2059
//// and/or modify it under the terms of the GNU Lesser General   ////
2060
//// Public License as published by the Free Software Foundation; ////
2061
//// either version 2.1 of the License, or (at your option) any   ////
2062
//// later version.                                               ////
2063
////                                                              ////
2064
//// This source is distributed in the hope that it will be       ////
2065
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2066
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2067
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2068
//// details.                                                     ////
2069
////                                                              ////
2070
//// You should have received a copy of the GNU Lesser General    ////
2071
//// Public License along with this source; if not, download it   ////
2072
//// from http://www.opencores.org/lgpl.shtml                     ////
2073
////                                                              ////
2074
//////////////////////////////////////////////////////////////////////
2075
 
2076 25 unneback
// binary counter
2077
 
2078 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2079
module `BASE`MODULE (
2080
`undef MODULE
2081
 cke, rew, zq, level1, rst, clk);
2082
 
2083 25 unneback
   parameter length = 4;
2084
   input cke;
2085
   input rew;
2086
   output reg zq;
2087
   output reg level1;
2088
   input rst;
2089
   input clk;
2090
 
2091
   parameter clear_value = 0;
2092
   parameter set_value = 1;
2093
   parameter wrap_value = 1;
2094
   parameter level1_value = 15;
2095
 
2096 29 unneback
   wire clear;
2097 30 unneback
   assign clear = 1'b0;
2098 25 unneback
   reg  [length:1] qi;
2099
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2100
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2101
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2102
   assign q_next = rew ? q_next_rew : q_next_fw;
2103
 
2104
   always @ (posedge clk or posedge rst)
2105
     if (rst)
2106
       qi <= {length{1'b0}};
2107
     else
2108
     if (cke)
2109
       qi <= q_next;
2110
 
2111
 
2112
 
2113
   always @ (posedge clk or posedge rst)
2114
     if (rst)
2115
       zq <= 1'b1;
2116
     else
2117
     if (cke)
2118
       zq <= q_next == {length{1'b0}};
2119
 
2120
    always @ (posedge clk or posedge rst)
2121
    if (rst)
2122
        level1 <= 1'b0;
2123
    else
2124
    if (cke)
2125 29 unneback
    if (clear)
2126
        level1 <= 1'b0;
2127
    else if (q_next == level1_value)
2128 25 unneback
        level1 <= 1'b1;
2129
    else if (qi == level1_value & rew)
2130
        level1 <= 1'b0;
2131
endmodule
2132 40 unneback
`endif
2133
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2134 25 unneback
//////////////////////////////////////////////////////////////////////
2135
////                                                              ////
2136
////  Versatile counter                                           ////
2137
////                                                              ////
2138
////  Description                                                 ////
2139
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2140
////  counter                                                     ////
2141
////                                                              ////
2142
////  To Do:                                                      ////
2143
////   - add LFSR with more taps                                  ////
2144
////                                                              ////
2145
////  Author(s):                                                  ////
2146
////      - Michael Unneback, unneback@opencores.org              ////
2147
////        ORSoC AB                                              ////
2148
////                                                              ////
2149
//////////////////////////////////////////////////////////////////////
2150
////                                                              ////
2151
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2152
////                                                              ////
2153
//// This source file may be used and distributed without         ////
2154
//// restriction provided that this copyright statement is not    ////
2155
//// removed from the file and that any derivative work contains  ////
2156
//// the original copyright notice and the associated disclaimer. ////
2157
////                                                              ////
2158
//// This source file is free software; you can redistribute it   ////
2159
//// and/or modify it under the terms of the GNU Lesser General   ////
2160
//// Public License as published by the Free Software Foundation; ////
2161
//// either version 2.1 of the License, or (at your option) any   ////
2162
//// later version.                                               ////
2163
////                                                              ////
2164
//// This source is distributed in the hope that it will be       ////
2165
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2166
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2167
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2168
//// details.                                                     ////
2169
////                                                              ////
2170
//// You should have received a copy of the GNU Lesser General    ////
2171
//// Public License along with this source; if not, download it   ////
2172
//// from http://www.opencores.org/lgpl.shtml                     ////
2173
////                                                              ////
2174
//////////////////////////////////////////////////////////////////////
2175
 
2176
// binary counter
2177
 
2178 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2179
module `BASE`MODULE (
2180
`undef MODULE
2181
 cke, rew, q, zq, level1, rst, clk);
2182
 
2183 25 unneback
   parameter length = 4;
2184
   input cke;
2185
   input rew;
2186
   output [length:1] q;
2187
   output reg zq;
2188
   output reg level1;
2189
   input rst;
2190
   input clk;
2191
 
2192
   parameter clear_value = 0;
2193
   parameter set_value = 1;
2194
   parameter wrap_value = 1;
2195
   parameter level1_value = 15;
2196
 
2197 29 unneback
   wire clear;
2198 30 unneback
   assign clear = 1'b0;
2199 25 unneback
   reg  [length:1] qi;
2200
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2201
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2202
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2203
   assign q_next = rew ? q_next_rew : q_next_fw;
2204
 
2205
   always @ (posedge clk or posedge rst)
2206
     if (rst)
2207
       qi <= {length{1'b0}};
2208
     else
2209
     if (cke)
2210
       qi <= q_next;
2211
 
2212
   assign q = qi;
2213
 
2214
 
2215
   always @ (posedge clk or posedge rst)
2216
     if (rst)
2217
       zq <= 1'b1;
2218
     else
2219
     if (cke)
2220
       zq <= q_next == {length{1'b0}};
2221
 
2222
    always @ (posedge clk or posedge rst)
2223
    if (rst)
2224
        level1 <= 1'b0;
2225
    else
2226
    if (cke)
2227 29 unneback
    if (clear)
2228
        level1 <= 1'b0;
2229
    else if (q_next == level1_value)
2230 25 unneback
        level1 <= 1'b1;
2231
    else if (qi == level1_value & rew)
2232
        level1 <= 1'b0;
2233
endmodule
2234 40 unneback
`endif
2235
`ifdef CNT_LFSR_ZQ
2236 25 unneback
//////////////////////////////////////////////////////////////////////
2237
////                                                              ////
2238
////  Versatile counter                                           ////
2239
////                                                              ////
2240
////  Description                                                 ////
2241
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2242
////  counter                                                     ////
2243
////                                                              ////
2244
////  To Do:                                                      ////
2245
////   - add LFSR with more taps                                  ////
2246
////                                                              ////
2247
////  Author(s):                                                  ////
2248
////      - Michael Unneback, unneback@opencores.org              ////
2249
////        ORSoC AB                                              ////
2250
////                                                              ////
2251
//////////////////////////////////////////////////////////////////////
2252
////                                                              ////
2253
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2254
////                                                              ////
2255
//// This source file may be used and distributed without         ////
2256
//// restriction provided that this copyright statement is not    ////
2257
//// removed from the file and that any derivative work contains  ////
2258
//// the original copyright notice and the associated disclaimer. ////
2259
////                                                              ////
2260
//// This source file is free software; you can redistribute it   ////
2261
//// and/or modify it under the terms of the GNU Lesser General   ////
2262
//// Public License as published by the Free Software Foundation; ////
2263
//// either version 2.1 of the License, or (at your option) any   ////
2264
//// later version.                                               ////
2265
////                                                              ////
2266
//// This source is distributed in the hope that it will be       ////
2267
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2268
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2269
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2270
//// details.                                                     ////
2271
////                                                              ////
2272
//// You should have received a copy of the GNU Lesser General    ////
2273
//// Public License along with this source; if not, download it   ////
2274
//// from http://www.opencores.org/lgpl.shtml                     ////
2275
////                                                              ////
2276
//////////////////////////////////////////////////////////////////////
2277
 
2278 6 unneback
// LFSR counter
2279
 
2280 40 unneback
`define MODULE cnt_lfsr_zq
2281
module `BASE`MODULE (
2282
`undef MODULE
2283
 zq, rst, clk);
2284
 
2285 6 unneback
   parameter length = 4;
2286
   output reg zq;
2287
   input rst;
2288
   input clk;
2289
 
2290
   parameter clear_value = 0;
2291
   parameter set_value = 1;
2292
   parameter wrap_value = 8;
2293
   parameter level1_value = 15;
2294
 
2295
   reg  [length:1] qi;
2296
   reg lfsr_fb;
2297
   wire [length:1] q_next;
2298
   reg [32:1] polynom;
2299
   integer i;
2300
 
2301
   always @ (qi)
2302
   begin
2303
        case (length)
2304
         2: polynom = 32'b11;                               // 0x3
2305
         3: polynom = 32'b110;                              // 0x6
2306
         4: polynom = 32'b1100;                             // 0xC
2307
         5: polynom = 32'b10100;                            // 0x14
2308
         6: polynom = 32'b110000;                           // 0x30
2309
         7: polynom = 32'b1100000;                          // 0x60
2310
         8: polynom = 32'b10111000;                         // 0xb8
2311
         9: polynom = 32'b100010000;                        // 0x110
2312
        10: polynom = 32'b1001000000;                       // 0x240
2313
        11: polynom = 32'b10100000000;                      // 0x500
2314
        12: polynom = 32'b100000101001;                     // 0x829
2315
        13: polynom = 32'b1000000001100;                    // 0x100C
2316
        14: polynom = 32'b10000000010101;                   // 0x2015
2317
        15: polynom = 32'b110000000000000;                  // 0x6000
2318
        16: polynom = 32'b1101000000001000;                 // 0xD008
2319
        17: polynom = 32'b10010000000000000;                // 0x12000
2320
        18: polynom = 32'b100000010000000000;               // 0x20400
2321
        19: polynom = 32'b1000000000000100011;              // 0x40023
2322 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2323 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2324
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2325
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2326
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2327
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2328
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2329
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2330
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2331
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2332
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2333
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2334
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2335
        default: polynom = 32'b0;
2336
        endcase
2337
        lfsr_fb = qi[length];
2338
        for (i=length-1; i>=1; i=i-1) begin
2339
            if (polynom[i])
2340
                lfsr_fb = lfsr_fb  ~^ qi[i];
2341
        end
2342
    end
2343
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2344
 
2345
   always @ (posedge clk or posedge rst)
2346
     if (rst)
2347
       qi <= {length{1'b0}};
2348
     else
2349
       qi <= q_next;
2350
 
2351
 
2352
 
2353
   always @ (posedge clk or posedge rst)
2354
     if (rst)
2355
       zq <= 1'b1;
2356
     else
2357
       zq <= q_next == {length{1'b0}};
2358
endmodule
2359 40 unneback
`endif
2360
`ifdef CNT_LFSR_CE_ZQ
2361 6 unneback
//////////////////////////////////////////////////////////////////////
2362
////                                                              ////
2363
////  Versatile counter                                           ////
2364
////                                                              ////
2365
////  Description                                                 ////
2366
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2367
////  counter                                                     ////
2368
////                                                              ////
2369
////  To Do:                                                      ////
2370
////   - add LFSR with more taps                                  ////
2371
////                                                              ////
2372
////  Author(s):                                                  ////
2373
////      - Michael Unneback, unneback@opencores.org              ////
2374
////        ORSoC AB                                              ////
2375
////                                                              ////
2376
//////////////////////////////////////////////////////////////////////
2377
////                                                              ////
2378
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2379
////                                                              ////
2380
//// This source file may be used and distributed without         ////
2381
//// restriction provided that this copyright statement is not    ////
2382
//// removed from the file and that any derivative work contains  ////
2383
//// the original copyright notice and the associated disclaimer. ////
2384
////                                                              ////
2385
//// This source file is free software; you can redistribute it   ////
2386
//// and/or modify it under the terms of the GNU Lesser General   ////
2387
//// Public License as published by the Free Software Foundation; ////
2388
//// either version 2.1 of the License, or (at your option) any   ////
2389
//// later version.                                               ////
2390
////                                                              ////
2391
//// This source is distributed in the hope that it will be       ////
2392
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2393
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2394
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2395
//// details.                                                     ////
2396
////                                                              ////
2397
//// You should have received a copy of the GNU Lesser General    ////
2398
//// Public License along with this source; if not, download it   ////
2399
//// from http://www.opencores.org/lgpl.shtml                     ////
2400
////                                                              ////
2401
//////////////////////////////////////////////////////////////////////
2402
 
2403
// LFSR counter
2404
 
2405 40 unneback
`define MODULE cnt_lfsr_ce_zq
2406
module `BASE`MODULE (
2407
`undef MODULE
2408
 cke, zq, rst, clk);
2409
 
2410 6 unneback
   parameter length = 4;
2411
   input cke;
2412
   output reg zq;
2413
   input rst;
2414
   input clk;
2415
 
2416
   parameter clear_value = 0;
2417
   parameter set_value = 1;
2418
   parameter wrap_value = 8;
2419
   parameter level1_value = 15;
2420
 
2421
   reg  [length:1] qi;
2422
   reg lfsr_fb;
2423
   wire [length:1] q_next;
2424
   reg [32:1] polynom;
2425
   integer i;
2426
 
2427
   always @ (qi)
2428
   begin
2429
        case (length)
2430
         2: polynom = 32'b11;                               // 0x3
2431
         3: polynom = 32'b110;                              // 0x6
2432
         4: polynom = 32'b1100;                             // 0xC
2433
         5: polynom = 32'b10100;                            // 0x14
2434
         6: polynom = 32'b110000;                           // 0x30
2435
         7: polynom = 32'b1100000;                          // 0x60
2436
         8: polynom = 32'b10111000;                         // 0xb8
2437
         9: polynom = 32'b100010000;                        // 0x110
2438
        10: polynom = 32'b1001000000;                       // 0x240
2439
        11: polynom = 32'b10100000000;                      // 0x500
2440
        12: polynom = 32'b100000101001;                     // 0x829
2441
        13: polynom = 32'b1000000001100;                    // 0x100C
2442
        14: polynom = 32'b10000000010101;                   // 0x2015
2443
        15: polynom = 32'b110000000000000;                  // 0x6000
2444
        16: polynom = 32'b1101000000001000;                 // 0xD008
2445
        17: polynom = 32'b10010000000000000;                // 0x12000
2446
        18: polynom = 32'b100000010000000000;               // 0x20400
2447
        19: polynom = 32'b1000000000000100011;              // 0x40023
2448 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2449 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2450
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2451
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2452
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2453
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2454
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2455
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2456
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2457
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2458
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2459
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2460
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2461
        default: polynom = 32'b0;
2462
        endcase
2463
        lfsr_fb = qi[length];
2464
        for (i=length-1; i>=1; i=i-1) begin
2465
            if (polynom[i])
2466
                lfsr_fb = lfsr_fb  ~^ qi[i];
2467
        end
2468
    end
2469
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2470
 
2471
   always @ (posedge clk or posedge rst)
2472
     if (rst)
2473
       qi <= {length{1'b0}};
2474
     else
2475
     if (cke)
2476
       qi <= q_next;
2477
 
2478
 
2479
 
2480
   always @ (posedge clk or posedge rst)
2481
     if (rst)
2482
       zq <= 1'b1;
2483
     else
2484
     if (cke)
2485
       zq <= q_next == {length{1'b0}};
2486
endmodule
2487 40 unneback
`endif
2488
`ifdef CNT_LFSR_CE_Q
2489 6 unneback
//////////////////////////////////////////////////////////////////////
2490
////                                                              ////
2491
////  Versatile counter                                           ////
2492
////                                                              ////
2493
////  Description                                                 ////
2494
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2495
////  counter                                                     ////
2496
////                                                              ////
2497
////  To Do:                                                      ////
2498
////   - add LFSR with more taps                                  ////
2499
////                                                              ////
2500
////  Author(s):                                                  ////
2501
////      - Michael Unneback, unneback@opencores.org              ////
2502
////        ORSoC AB                                              ////
2503
////                                                              ////
2504
//////////////////////////////////////////////////////////////////////
2505
////                                                              ////
2506
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2507
////                                                              ////
2508
//// This source file may be used and distributed without         ////
2509
//// restriction provided that this copyright statement is not    ////
2510
//// removed from the file and that any derivative work contains  ////
2511
//// the original copyright notice and the associated disclaimer. ////
2512
////                                                              ////
2513
//// This source file is free software; you can redistribute it   ////
2514
//// and/or modify it under the terms of the GNU Lesser General   ////
2515
//// Public License as published by the Free Software Foundation; ////
2516
//// either version 2.1 of the License, or (at your option) any   ////
2517
//// later version.                                               ////
2518
////                                                              ////
2519
//// This source is distributed in the hope that it will be       ////
2520
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2521
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2522
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2523
//// details.                                                     ////
2524
////                                                              ////
2525
//// You should have received a copy of the GNU Lesser General    ////
2526
//// Public License along with this source; if not, download it   ////
2527
//// from http://www.opencores.org/lgpl.shtml                     ////
2528
////                                                              ////
2529
//////////////////////////////////////////////////////////////////////
2530 22 unneback
 
2531
// LFSR counter
2532 27 unneback
 
2533 40 unneback
`define MODULE cnt_lfsr_ce_q
2534
module `BASE`MODULE (
2535
`undef MODULE
2536
 cke, q, rst, clk);
2537
 
2538 27 unneback
   parameter length = 4;
2539
   input cke;
2540
   output [length:1] q;
2541
   input rst;
2542
   input clk;
2543
 
2544
   parameter clear_value = 0;
2545
   parameter set_value = 1;
2546
   parameter wrap_value = 8;
2547
   parameter level1_value = 15;
2548
 
2549
   reg  [length:1] qi;
2550
   reg lfsr_fb;
2551
   wire [length:1] q_next;
2552
   reg [32:1] polynom;
2553
   integer i;
2554
 
2555
   always @ (qi)
2556
   begin
2557
        case (length)
2558
         2: polynom = 32'b11;                               // 0x3
2559
         3: polynom = 32'b110;                              // 0x6
2560
         4: polynom = 32'b1100;                             // 0xC
2561
         5: polynom = 32'b10100;                            // 0x14
2562
         6: polynom = 32'b110000;                           // 0x30
2563
         7: polynom = 32'b1100000;                          // 0x60
2564
         8: polynom = 32'b10111000;                         // 0xb8
2565
         9: polynom = 32'b100010000;                        // 0x110
2566
        10: polynom = 32'b1001000000;                       // 0x240
2567
        11: polynom = 32'b10100000000;                      // 0x500
2568
        12: polynom = 32'b100000101001;                     // 0x829
2569
        13: polynom = 32'b1000000001100;                    // 0x100C
2570
        14: polynom = 32'b10000000010101;                   // 0x2015
2571
        15: polynom = 32'b110000000000000;                  // 0x6000
2572
        16: polynom = 32'b1101000000001000;                 // 0xD008
2573
        17: polynom = 32'b10010000000000000;                // 0x12000
2574
        18: polynom = 32'b100000010000000000;               // 0x20400
2575
        19: polynom = 32'b1000000000000100011;              // 0x40023
2576 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2577 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2578
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2579
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2580
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2581
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2582
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2583
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2584
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2585
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2586
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2587
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2588
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2589
        default: polynom = 32'b0;
2590
        endcase
2591
        lfsr_fb = qi[length];
2592
        for (i=length-1; i>=1; i=i-1) begin
2593
            if (polynom[i])
2594
                lfsr_fb = lfsr_fb  ~^ qi[i];
2595
        end
2596
    end
2597
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2598
 
2599
   always @ (posedge clk or posedge rst)
2600
     if (rst)
2601
       qi <= {length{1'b0}};
2602
     else
2603
     if (cke)
2604
       qi <= q_next;
2605
 
2606
   assign q = qi;
2607
 
2608
endmodule
2609 40 unneback
`endif
2610
`ifdef CNT_LFSR_CE_CLEAR_Q
2611 27 unneback
//////////////////////////////////////////////////////////////////////
2612
////                                                              ////
2613
////  Versatile counter                                           ////
2614
////                                                              ////
2615
////  Description                                                 ////
2616
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2617
////  counter                                                     ////
2618
////                                                              ////
2619
////  To Do:                                                      ////
2620
////   - add LFSR with more taps                                  ////
2621
////                                                              ////
2622
////  Author(s):                                                  ////
2623
////      - Michael Unneback, unneback@opencores.org              ////
2624
////        ORSoC AB                                              ////
2625
////                                                              ////
2626
//////////////////////////////////////////////////////////////////////
2627
////                                                              ////
2628
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2629
////                                                              ////
2630
//// This source file may be used and distributed without         ////
2631
//// restriction provided that this copyright statement is not    ////
2632
//// removed from the file and that any derivative work contains  ////
2633
//// the original copyright notice and the associated disclaimer. ////
2634
////                                                              ////
2635
//// This source file is free software; you can redistribute it   ////
2636
//// and/or modify it under the terms of the GNU Lesser General   ////
2637
//// Public License as published by the Free Software Foundation; ////
2638
//// either version 2.1 of the License, or (at your option) any   ////
2639
//// later version.                                               ////
2640
////                                                              ////
2641
//// This source is distributed in the hope that it will be       ////
2642
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2643
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2644
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2645
//// details.                                                     ////
2646
////                                                              ////
2647
//// You should have received a copy of the GNU Lesser General    ////
2648
//// Public License along with this source; if not, download it   ////
2649
//// from http://www.opencores.org/lgpl.shtml                     ////
2650
////                                                              ////
2651
//////////////////////////////////////////////////////////////////////
2652
 
2653
// LFSR counter
2654
 
2655 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2656
module `BASE`MODULE (
2657
`undef MODULE
2658
 clear, cke, q, rst, clk);
2659
 
2660 27 unneback
   parameter length = 4;
2661
   input clear;
2662
   input cke;
2663
   output [length:1] q;
2664
   input rst;
2665
   input clk;
2666
 
2667
   parameter clear_value = 0;
2668
   parameter set_value = 1;
2669
   parameter wrap_value = 8;
2670
   parameter level1_value = 15;
2671
 
2672
   reg  [length:1] qi;
2673
   reg lfsr_fb;
2674
   wire [length:1] q_next;
2675
   reg [32:1] polynom;
2676
   integer i;
2677
 
2678
   always @ (qi)
2679
   begin
2680
        case (length)
2681
         2: polynom = 32'b11;                               // 0x3
2682
         3: polynom = 32'b110;                              // 0x6
2683
         4: polynom = 32'b1100;                             // 0xC
2684
         5: polynom = 32'b10100;                            // 0x14
2685
         6: polynom = 32'b110000;                           // 0x30
2686
         7: polynom = 32'b1100000;                          // 0x60
2687
         8: polynom = 32'b10111000;                         // 0xb8
2688
         9: polynom = 32'b100010000;                        // 0x110
2689
        10: polynom = 32'b1001000000;                       // 0x240
2690
        11: polynom = 32'b10100000000;                      // 0x500
2691
        12: polynom = 32'b100000101001;                     // 0x829
2692
        13: polynom = 32'b1000000001100;                    // 0x100C
2693
        14: polynom = 32'b10000000010101;                   // 0x2015
2694
        15: polynom = 32'b110000000000000;                  // 0x6000
2695
        16: polynom = 32'b1101000000001000;                 // 0xD008
2696
        17: polynom = 32'b10010000000000000;                // 0x12000
2697
        18: polynom = 32'b100000010000000000;               // 0x20400
2698
        19: polynom = 32'b1000000000000100011;              // 0x40023
2699 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2700 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2701
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2702
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2703
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2704
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2705
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2706
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2707
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2708
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2709
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2710
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2711
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2712
        default: polynom = 32'b0;
2713
        endcase
2714
        lfsr_fb = qi[length];
2715
        for (i=length-1; i>=1; i=i-1) begin
2716
            if (polynom[i])
2717
                lfsr_fb = lfsr_fb  ~^ qi[i];
2718
        end
2719
    end
2720
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2721
 
2722
   always @ (posedge clk or posedge rst)
2723
     if (rst)
2724
       qi <= {length{1'b0}};
2725
     else
2726
     if (cke)
2727
       qi <= q_next;
2728
 
2729
   assign q = qi;
2730
 
2731
endmodule
2732 40 unneback
`endif
2733
`ifdef CNT_LFSR_CE_Q_ZQ
2734 27 unneback
//////////////////////////////////////////////////////////////////////
2735
////                                                              ////
2736
////  Versatile counter                                           ////
2737
////                                                              ////
2738
////  Description                                                 ////
2739
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2740
////  counter                                                     ////
2741
////                                                              ////
2742
////  To Do:                                                      ////
2743
////   - add LFSR with more taps                                  ////
2744
////                                                              ////
2745
////  Author(s):                                                  ////
2746
////      - Michael Unneback, unneback@opencores.org              ////
2747
////        ORSoC AB                                              ////
2748
////                                                              ////
2749
//////////////////////////////////////////////////////////////////////
2750
////                                                              ////
2751
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2752
////                                                              ////
2753
//// This source file may be used and distributed without         ////
2754
//// restriction provided that this copyright statement is not    ////
2755
//// removed from the file and that any derivative work contains  ////
2756
//// the original copyright notice and the associated disclaimer. ////
2757
////                                                              ////
2758
//// This source file is free software; you can redistribute it   ////
2759
//// and/or modify it under the terms of the GNU Lesser General   ////
2760
//// Public License as published by the Free Software Foundation; ////
2761
//// either version 2.1 of the License, or (at your option) any   ////
2762
//// later version.                                               ////
2763
////                                                              ////
2764
//// This source is distributed in the hope that it will be       ////
2765
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2766
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2767
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2768
//// details.                                                     ////
2769
////                                                              ////
2770
//// You should have received a copy of the GNU Lesser General    ////
2771
//// Public License along with this source; if not, download it   ////
2772
//// from http://www.opencores.org/lgpl.shtml                     ////
2773
////                                                              ////
2774
//////////////////////////////////////////////////////////////////////
2775
 
2776
// LFSR counter
2777 22 unneback
 
2778 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
2779
module `BASE`MODULE (
2780
`undef MODULE
2781
 cke, q, zq, rst, clk);
2782
 
2783 22 unneback
   parameter length = 4;
2784
   input cke;
2785
   output [length:1] q;
2786
   output reg zq;
2787
   input rst;
2788
   input clk;
2789
 
2790
   parameter clear_value = 0;
2791
   parameter set_value = 1;
2792
   parameter wrap_value = 8;
2793
   parameter level1_value = 15;
2794
 
2795
   reg  [length:1] qi;
2796
   reg lfsr_fb;
2797
   wire [length:1] q_next;
2798
   reg [32:1] polynom;
2799
   integer i;
2800
 
2801
   always @ (qi)
2802
   begin
2803
        case (length)
2804
         2: polynom = 32'b11;                               // 0x3
2805
         3: polynom = 32'b110;                              // 0x6
2806
         4: polynom = 32'b1100;                             // 0xC
2807
         5: polynom = 32'b10100;                            // 0x14
2808
         6: polynom = 32'b110000;                           // 0x30
2809
         7: polynom = 32'b1100000;                          // 0x60
2810
         8: polynom = 3