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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 61

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 40 unneback 
`ifdef ALL
14 
 
15 
`define GBUF
16 
`define SYNC_RST
17 
`define PLL
18 
 
19 
`define MULTS
20 
`define MULTS18X18
21 
`define MULT
22 
`define SHIFT_UNIT_32
23 
`define LOGIC_UNIT
24 
 
25 
`define CNT_SHREG_WRAP
26 
`define CNT_SHREG_CE_WRAP
27 
`define CNT_SHREG_CE_CLEAR
28 
`define CNT_SHREG_CE_CLEAR_WRAP
29 
 
30 
`define MUX_ANDOR
31 
`define MUX2_ANDOR
32 
`define MUX3_ANDOR
33 
`define MUX4_ANDOR
34 
`define MUX5_ANDOR
35 
`define MUX6_ANDOR
36 43 unneback 
`define PARITY
37 40 unneback 
 
38 
`define ROM_INIT
39 
`define RAM
40 
`define RAM_BE
41 
`define DPRAM_1R1W
42 
`define DPRAM_2R1W
43 
`define DPRAM_2R2W
44 
`define FIFO_1R1W_FILL_LEVEL_SYNC
45 
`define FIFO_2R2W_SYNC_SIMPLEX
46 
`define FIFO_CMP_ASYNC
47 
`define FIFO_1R1W_ASYNC
48 
`define FIFO_2R2W_ASYNC
49 
`define FIFO_2R2W_ASYNC_SIMPLEX
50 48 unneback 
`define REG_FILE
51 40 unneback 
 
52 
`define DFF
53 
`define DFF_ARRAY
54 
`define DFF_CE
55 
`define DFF_CE_CLEAR
56 
`define DF_CE_SET
57 
`define SPR
58 
`define SRP
59 
`define DFF_SR
60 
`define LATCH
61 
`define SHREG
62 
`define SHREG_CE
63 
`define DELAY
64 
`define DELAY_EMPTYFLAG
65 
 
66 
`define WB3WB3_BRIDGE
67 
`define WB3_ARBITER_TYPE1
68 59 unneback 
`define WB_B3_RAM_BE
69 49 unneback 
`define WB_B4_RAM_BE
70 48 unneback 
`define WB_B4_ROM
71 40 unneback 
`define WB_BOOT_ROM
72 
`define WB_DPRAM
73 
 
74 44 unneback 
`define IO_DFF_OE
75 
`define O_DFF
76 
 
77 40 unneback 
`endif
78 
 
79 
`ifdef PLL
80 
`ifndef SYNC_RST
81 
`define SYNC_RST
82 
`endif
83 
`endif
84 
 
85 
`ifdef SYNC_RST
86 
`ifndef GBUF
87 
`define GBUF
88 
`endif
89 
`endif
90 
 
91 
`ifdef WB_DPRAM
92 
`ifndef DPRAM_2R2W
93 
`define DPRAM_2R2W
94 
`endif
95 
`ifndef SPR
96 
`define SPR
97 
`endif
98 
`endif
99 
 
100 
`ifdef WB3_ARBITER_TYPE1
101 42 unneback 
`ifndef SPR
102 
`define SPR
103 
`endif
104 40 unneback 
`ifndef MUX_ANDOR
105 
`define MUX_ANDOR
106 
`endif
107 
`endif
108 
 
109 
`ifdef WB3WB3_BRIDGE
110 
`ifndef CNT_SHREG_CE_CLEAR
111 
`define CNT_SHREG_CE_CLEAR
112 
`endif
113 
`ifndef DFF
114 
`define DFF
115 
`endif
116 
`ifndef DFF_CE
117 
`define DFF_CE
118 
`endif
119 
`ifndef CNT_SHREG_CE_CLEAR
120 
`define CNT_SHREG_CE_CLEAR
121 
`endif
122 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
123 
`define FIFO_2R2W_ASYNC_SIMPLEX
124 
`endif
125 
`endif
126 
 
127 
`ifdef MULTS18X18
128 
`ifndef MULTS
129 
`define MULTS
130 
`endif
131 
`endif
132 
 
133 
`ifdef SHIFT_UNIT_32
134 
`ifndef MULTS
135 
`define MULTS
136 
`endif
137 
`endif
138 
 
139 
`ifdef MUX2_ANDOR
140 
`ifndef MUX_ANDOR
141 
`define MUX_ANDOR
142 
`endif
143 
`endif
144 
 
145 
`ifdef MUX3_ANDOR
146 
`ifndef MUX_ANDOR
147 
`define MUX_ANDOR
148 
`endif
149 
`endif
150 
 
151 
`ifdef MUX4_ANDOR
152 
`ifndef MUX_ANDOR
153 
`define MUX_ANDOR
154 
`endif
155 
`endif
156 
 
157 
`ifdef MUX5_ANDOR
158 
`ifndef MUX_ANDOR
159 
`define MUX_ANDOR
160 
`endif
161 
`endif
162 
 
163 
`ifdef MUX6_ANDOR
164 
`ifndef MUX_ANDOR
165 
`define MUX_ANDOR
166 
`endif
167 
`endif
168 
 
169 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
170 
`ifndef CNT_BIN_CE
171 
`define CNT_BIN_CE
172 
`endif
173 
`ifndef DPRAM_1R1W
174 
`define DPRAM_1R1W
175 
`endif
176 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
177 
`define CNT_BIN_CE_REW_Q_ZQ_L1
178 
`endif
179 
`endif
180 
 
181 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
182 
`ifndef CNT_LFSR_CE
183 
`define CNT_LFSR_CE
184 
`endif
185 
`ifndef DPRAM_2R2W
186 
`define DPRAM_2R2W
187 
`endif
188 
`ifndef CNT_BIN_CE_REW_ZQ_L1
189 
`define CNT_BIN_CE_REW_ZQ_L1
190 
`endif
191 
`endif
192 
 
193 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
194 
`ifndef CNT_GRAY_CE_BIN
195 
`define CNT_GRAY_CE_BIN
196 
`endif
197 
`ifndef DPRAM_2R2W
198 
`define DPRAM_2R2W
199 
`endif
200 
`ifndef FIFO_CMP_ASYNC
201 
`define FIFO_CMP_ASYNC
202 
`endif
203 
`endif
204 
 
205 
`ifdef FIFO_2R2W_ASYNC
206 
`ifndef FIFO_1R1W_ASYNC
207 
`define FIFO_1R1W_ASYNC
208 
`endif
209 
`endif
210 
 
211 
`ifdef FIFO_1R1W_ASYNC
212 
`ifndef CNT_GRAY_CE_BIN
213 
`define CNT_GRAY_CE_BIN
214 
`endif
215 
`ifndef DPRAM_1R1W
216 
`define DPRAM_1R1W
217 
`endif
218 
`ifndef FIFO_CMP_ASYNC
219 
`define FIFO_CMP_ASYNC
220 
`endif
221 
`endif
222 
 
223 
`ifdef FIFO_CMP_ASYNC
224 
`ifndef DFF_SR
225 
`define DFF_SR
226 
`endif
227 
`ifndef DFF
228 
`define DFF
229 
`endif
230 
`endif
231 48 unneback 
 
232 
`ifdef REG_FILE
233 
`ifndef DPRAM_1R1W
234 
`define DPRAM_1R1W
235 
`endif
236 
`endif
237 61 unneback 
 
238 
`ifdef WB_B3_RAM_BE
239 
`ifndef WB3_ARBITER_TYPE1
240 
`define WB3_ARBITER_TYPE1
241 
`endif
242 
`ifndef RAM_BE
243 
`define RAM_BE
244 
`endif
245 
`endif//////////////////////////////////////////////////////////////////////
246 6 unneback 
////                                                              ////
247 
////  Versatile library, clock and reset                          ////
248 
////                                                              ////
249 
////  Description                                                 ////
250 
////  Logic related to clock and reset                            ////
251 
////                                                              ////
252 
////                                                              ////
253 
////  To Do:                                                      ////
254 
////   - add more different registers                             ////
255 
////                                                              ////
256 
////  Author(s):                                                  ////
257 
////      - Michael Unneback, unneback@opencores.org              ////
258 
////        ORSoC AB                                              ////
259 
////                                                              ////
260 
//////////////////////////////////////////////////////////////////////
261 
////                                                              ////
262 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
263 
////                                                              ////
264 
//// This source file may be used and distributed without         ////
265 
//// restriction provided that this copyright statement is not    ////
266 
//// removed from the file and that any derivative work contains  ////
267 
//// the original copyright notice and the associated disclaimer. ////
268 
////                                                              ////
269 
//// This source file is free software; you can redistribute it   ////
270 
//// and/or modify it under the terms of the GNU Lesser General   ////
271 
//// Public License as published by the Free Software Foundation; ////
272 
//// either version 2.1 of the License, or (at your option) any   ////
273 
//// later version.                                               ////
274 
////                                                              ////
275 
//// This source is distributed in the hope that it will be       ////
276 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
277 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
278 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
279 
//// details.                                                     ////
280 
////                                                              ////
281 
//// You should have received a copy of the GNU Lesser General    ////
282 
//// Public License along with this source; if not, download it   ////
283 
//// from http://www.opencores.org/lgpl.shtml                     ////
284 
////                                                              ////
285 
//////////////////////////////////////////////////////////////////////
286 
 
287 48 unneback 
`ifdef ACTEL
288 
`ifdef GBUF
289 
`timescale 1 ns/100 ps
290 6 unneback 
// Global buffer
291 
// usage:
292 
// use to enable global buffers for high fan out signals such as clock and reset
293 
// Version: 8.4 8.4.0.33
294 
module gbuf(GL,CLK);
295 
output GL;
296 
input  CLK;
297 
 
298 
    wire GND;
299 
 
300 
    GND GND_1_net(.Y(GND));
301 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
302 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
303 
 
304 
endmodule
305 
`timescale 1 ns/1 ns
306 40 unneback 
`define MODULE gbuf
307 
module `BASE`MODULE ( i, o);
308 
`undef MODULE
309 6 unneback 
input i;
310 
output o;
311 
`ifdef SIM_GBUF
312 
assign o=i;
313 
`else
314 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
315 
`endif
316 
endmodule
317 40 unneback 
`endif
318 33 unneback 
 
319 6 unneback 
`else
320 33 unneback 
 
321 40 unneback 
`ifdef ALTERA
322 
`ifdef GBUF
323 21 unneback 
//altera
324 40 unneback 
`define MODULE gbuf
325 
module `BASE`MODULE ( i, o);
326 
`undef MODULE
327 33 unneback 
input i;
328 
output o;
329 
assign o = i;
330 
endmodule
331 40 unneback 
`endif
332 33 unneback 
 
333 6 unneback 
`else
334 
 
335 40 unneback 
`ifdef GBUF
336 6 unneback 
`timescale 1 ns/100 ps
337 40 unneback 
`define MODULE
338 
module `BASE`MODULE ( i, o);
339 
`undef MODULE
340 6 unneback 
input i;
341 
output o;
342 
assign o = i;
343 
endmodule
344 40 unneback 
`endif
345 6 unneback 
`endif // ALTERA
346 
`endif //ACTEL
347 
 
348 40 unneback 
`ifdef SYNC_RST
349 6 unneback 
// sync reset
350 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
351 6 unneback 
// output active high global reset sync with two DFFs
352 
`timescale 1 ns/100 ps
353 40 unneback 
`define MODULE sync_rst
354 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
355 
`undef MODULE
356 6 unneback 
input rst_n_i, clk;
357 
output rst_o;
358 18 unneback 
reg [1:0] tmp;
359 6 unneback 
always @ (posedge clk or negedge rst_n_i)
360 
if (!rst_n_i)
361 17 unneback 
        tmp <= 2'b11;
362 6 unneback 
else
363 33 unneback 
        tmp <= {1'b0,tmp[1]};
364 40 unneback 
`define MODULE gbuf
365 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
366 
`undef MODULE
367 6 unneback 
endmodule
368 40 unneback 
`endif
369 6 unneback 
 
370 40 unneback 
`ifdef PLL
371 6 unneback 
// vl_pll
372 
`ifdef ACTEL
373 32 unneback 
///////////////////////////////////////////////////////////////////////////////
374 17 unneback 
`timescale 1 ps/1 ps
375 40 unneback 
`define MODULE pll
376 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
377 
`undef MODULE
378 6 unneback 
parameter index = 0;
379 
parameter number_of_clk = 1;
380 17 unneback 
parameter period_time_0 = 20000;
381 
parameter period_time_1 = 20000;
382 
parameter period_time_2 = 20000;
383 
parameter lock_delay = 2000000;
384 6 unneback 
input clk_i, rst_n_i;
385 
output lock;
386 
output reg [0:number_of_clk-1] clk_o;
387 
output [0:number_of_clk-1] rst_o;
388 
 
389 
`ifdef SIM_PLL
390 
 
391 
always
392 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
393 
 
394 
generate if (number_of_clk > 1)
395 
always
396 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
397 
endgenerate
398 
 
399 
generate if (number_of_clk > 2)
400 
always
401 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
402 
endgenerate
403 
 
404 
genvar i;
405 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
406 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
407 
end
408 
endgenerate
409 
 
410 
assign #lock_delay lock = rst_n_i;
411 
 
412 
endmodule
413 
`else
414 
generate if (number_of_clk==1 & index==0) begin
415 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
416 
end
417 
endgenerate // index==0
418 
generate if (number_of_clk==1 & index==1) begin
419 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
420 
end
421 
endgenerate // index==1
422 
generate if (number_of_clk==1 & index==2) begin
423 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
424 
end
425 
endgenerate // index==2
426 
generate if (number_of_clk==1 & index==3) begin
427 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
428 
end
429 
endgenerate // index==0
430 
 
431 
generate if (number_of_clk==2 & index==0) begin
432 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
433 
end
434 
endgenerate // index==0
435 
generate if (number_of_clk==2 & index==1) begin
436 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
437 
end
438 
endgenerate // index==1
439 
generate if (number_of_clk==2 & index==2) begin
440 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
441 
end
442 
endgenerate // index==2
443 
generate if (number_of_clk==2 & index==3) begin
444 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
445 
end
446 
endgenerate // index==0
447 
 
448 
generate if (number_of_clk==3 & index==0) begin
449 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
450 
end
451 
endgenerate // index==0
452 
generate if (number_of_clk==3 & index==1) begin
453 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
454 
end
455 
endgenerate // index==1
456 
generate if (number_of_clk==3 & index==2) begin
457 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
458 
end
459 
endgenerate // index==2
460 
generate if (number_of_clk==3 & index==3) begin
461 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
462 
end
463 
endgenerate // index==0
464 
 
465 
genvar i;
466 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
467 40 unneback 
`define MODULE sync_rst
468 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
469 
`undef MODULE
470 6 unneback 
end
471 
endgenerate
472 
endmodule
473 
`endif
474 32 unneback 
///////////////////////////////////////////////////////////////////////////////
475 6 unneback 
 
476 
`else
477 
 
478 32 unneback 
///////////////////////////////////////////////////////////////////////////////
479 6 unneback 
`ifdef ALTERA
480 
 
481 32 unneback 
`timescale 1 ps/1 ps
482 40 unneback 
`define MODULE pll
483 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
484 
`undef MODULE
485 32 unneback 
parameter index = 0;
486 
parameter number_of_clk = 1;
487 
parameter period_time_0 = 20000;
488 
parameter period_time_1 = 20000;
489 
parameter period_time_2 = 20000;
490 
parameter period_time_3 = 20000;
491 
parameter period_time_4 = 20000;
492 
parameter lock_delay = 2000000;
493 
input clk_i, rst_n_i;
494 
output lock;
495 
output reg [0:number_of_clk-1] clk_o;
496 
output [0:number_of_clk-1] rst_o;
497 
 
498 
`ifdef SIM_PLL
499 
 
500 
always
501 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
502 
 
503 
generate if (number_of_clk > 1)
504 
always
505 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
506 
endgenerate
507 
 
508 
generate if (number_of_clk > 2)
509 
always
510 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
511 
endgenerate
512 
 
513 33 unneback 
generate if (number_of_clk > 3)
514 32 unneback 
always
515 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
516 
endgenerate
517 
 
518 33 unneback 
generate if (number_of_clk > 4)
519 32 unneback 
always
520 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
521 
endgenerate
522 
 
523 
genvar i;
524 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
525 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
526 
end
527 
endgenerate
528 
 
529 33 unneback 
//assign #lock_delay lock = rst_n_i;
530 
assign lock = rst_n_i;
531 32 unneback 
 
532 
endmodule
533 6 unneback 
`else
534 
 
535 33 unneback 
`ifdef VL_PLL0
536 
`ifdef VL_PLL0_CLK1
537 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
538 
`endif
539 
`ifdef VL_PLL0_CLK2
540 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
541 
`endif
542 
`ifdef VL_PLL0_CLK3
543 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
544 
`endif
545 
`ifdef VL_PLL0_CLK4
546 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
547 
`endif
548 
`ifdef VL_PLL0_CLK5
549 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
550 
`endif
551 
`endif
552 32 unneback 
 
553 33 unneback 
`ifdef VL_PLL1
554 
`ifdef VL_PLL1_CLK1
555 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
556 
`endif
557 
`ifdef VL_PLL1_CLK2
558 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
559 
`endif
560 
`ifdef VL_PLL1_CLK3
561 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
562 
`endif
563 
`ifdef VL_PLL1_CLK4
564 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
565 
`endif
566 
`ifdef VL_PLL1_CLK5
567 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
568 
`endif
569 
`endif
570 32 unneback 
 
571 33 unneback 
`ifdef VL_PLL2
572 
`ifdef VL_PLL2_CLK1
573 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
574 
`endif
575 
`ifdef VL_PLL2_CLK2
576 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
577 
`endif
578 
`ifdef VL_PLL2_CLK3
579 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
580 
`endif
581 
`ifdef VL_PLL2_CLK4
582 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
583 
`endif
584 
`ifdef VL_PLL2_CLK5
585 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
586 
`endif
587 
`endif
588 32 unneback 
 
589 33 unneback 
`ifdef VL_PLL3
590 
`ifdef VL_PLL3_CLK1
591 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
592 
`endif
593 
`ifdef VL_PLL3_CLK2
594 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
595 
`endif
596 
`ifdef VL_PLL3_CLK3
597 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
598 
`endif
599 
`ifdef VL_PLL3_CLK4
600 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
601 
`endif
602 
`ifdef VL_PLL3_CLK5
603 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
604 
`endif
605 
`endif
606 32 unneback 
 
607 
genvar i;
608 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
609 40 unneback 
`define MODULE sync_rst
610 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
611 
`undef MODULE
612 32 unneback 
end
613 
endgenerate
614 
endmodule
615 
`endif
616 
///////////////////////////////////////////////////////////////////////////////
617 
 
618 
`else
619 
 
620 6 unneback 
// generic PLL
621 17 unneback 
`timescale 1 ps/1 ps
622 40 unneback 
`define MODULE pll
623 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
624 
`undef MODULE
625 6 unneback 
parameter index = 0;
626 
parameter number_of_clk = 1;
627 17 unneback 
parameter period_time_0 = 20000;
628 
parameter period_time_1 = 20000;
629 
parameter period_time_2 = 20000;
630 6 unneback 
parameter lock_delay = 2000;
631 
input clk_i, rst_n_i;
632 
output lock;
633 
output reg [0:number_of_clk-1] clk_o;
634 
output [0:number_of_clk-1] rst_o;
635 
 
636 
always
637 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
638 
 
639 
generate if (number_of_clk > 1)
640 
always
641 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
642 
endgenerate
643 
 
644 
generate if (number_of_clk > 2)
645 
always
646 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
647 
endgenerate
648 
 
649 
genvar i;
650 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
651 40 unneback 
`define MODULE sync_rst
652 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
653 
`undef MODULE
654 6 unneback 
end
655 
endgenerate
656 
 
657 
assign #lock_delay lock = rst_n_i;
658 
 
659 
endmodule
660 
 
661 
`endif //altera
662 17 unneback 
`endif //actel
663 40 unneback 
`undef MODULE
664 
`endif//////////////////////////////////////////////////////////////////////
665 6 unneback 
////                                                              ////
666 
////  Versatile library, registers                                ////
667 
////                                                              ////
668 
////  Description                                                 ////
669 
////  Different type of registers                                 ////
670 
////                                                              ////
671 
////                                                              ////
672 
////  To Do:                                                      ////
673 
////   - add more different registers                             ////
674 
////                                                              ////
675 
////  Author(s):                                                  ////
676 
////      - Michael Unneback, unneback@opencores.org              ////
677 
////        ORSoC AB                                              ////
678 
////                                                              ////
679 
//////////////////////////////////////////////////////////////////////
680 
////                                                              ////
681 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
682 
////                                                              ////
683 
//// This source file may be used and distributed without         ////
684 
//// restriction provided that this copyright statement is not    ////
685 
//// removed from the file and that any derivative work contains  ////
686 
//// the original copyright notice and the associated disclaimer. ////
687 
////                                                              ////
688 
//// This source file is free software; you can redistribute it   ////
689 
//// and/or modify it under the terms of the GNU Lesser General   ////
690 
//// Public License as published by the Free Software Foundation; ////
691 
//// either version 2.1 of the License, or (at your option) any   ////
692 
//// later version.                                               ////
693 
////                                                              ////
694 
//// This source is distributed in the hope that it will be       ////
695 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
696 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
697 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
698 
//// details.                                                     ////
699 
////                                                              ////
700 
//// You should have received a copy of the GNU Lesser General    ////
701 
//// Public License along with this source; if not, download it   ////
702 
//// from http://www.opencores.org/lgpl.shtml                     ////
703 
////                                                              ////
704 
//////////////////////////////////////////////////////////////////////
705 
 
706 40 unneback 
`ifdef DFF
707 
`define MODULE dff
708 
module `BASE`MODULE ( d, q, clk, rst);
709 
`undef MODULE
710 6 unneback 
        parameter width = 1;
711 
        parameter reset_value = 0;
712 
 
713 
        input [width-1:0] d;
714 
        input clk, rst;
715 
        output reg [width-1:0] q;
716 
 
717 
        always @ (posedge clk or posedge rst)
718 
        if (rst)
719 
                q <= reset_value;
720 
        else
721 
                q <= d;
722 
 
723 
endmodule
724 40 unneback 
`endif
725 6 unneback 
 
726 40 unneback 
`ifdef DFF_ARRAY
727 
`define MODULE dff_array
728 
module `BASE`MODULE ( d, q, clk, rst);
729 
`undef MODULE
730 6 unneback 
 
731 
        parameter width = 1;
732 
        parameter depth = 2;
733 
        parameter reset_value = 1'b0;
734 
 
735 
        input [width-1:0] d;
736 
        input clk, rst;
737 
        output [width-1:0] q;
738 
        reg  [0:depth-1] q_tmp [width-1:0];
739 
        integer i;
740 
        always @ (posedge clk or posedge rst)
741 
        if (rst) begin
742 
            for (i=0;i<depth;i=i+1)
743 
                q_tmp[i] <= {width{reset_value}};
744 
        end else begin
745 
            q_tmp[0] <= d;
746 
            for (i=1;i<depth;i=i+1)
747 
                q_tmp[i] <= q_tmp[i-1];
748 
        end
749 
 
750 
    assign q = q_tmp[depth-1];
751 
 
752 
endmodule
753 40 unneback 
`endif
754 6 unneback 
 
755 40 unneback 
`ifdef DFF_CE
756 
`define MODULE dff_ce
757 
module `BASE`MODULE ( d, ce, q, clk, rst);
758 
`undef MODULE
759 6 unneback 
 
760 
        parameter width = 1;
761 
        parameter reset_value = 0;
762 
 
763 
        input [width-1:0] d;
764 
        input ce, clk, rst;
765 
        output reg [width-1:0] q;
766 
 
767 
        always @ (posedge clk or posedge rst)
768 
        if (rst)
769 
                q <= reset_value;
770 
        else
771 
                if (ce)
772 
                        q <= d;
773 
 
774 
endmodule
775 40 unneback 
`endif
776 6 unneback 
 
777 40 unneback 
`ifdef DFF_CE_CLEAR
778 
`define MODULE dff_ce_clear
779 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
780 
`undef MODULE
781 8 unneback 
 
782 
        parameter width = 1;
783 
        parameter reset_value = 0;
784 
 
785 
        input [width-1:0] d;
786 10 unneback 
        input ce, clear, clk, rst;
787 8 unneback 
        output reg [width-1:0] q;
788 
 
789 
        always @ (posedge clk or posedge rst)
790 
        if (rst)
791 
            q <= reset_value;
792 
        else
793 
            if (ce)
794 
                if (clear)
795 
                    q <= {width{1'b0}};
796 
                else
797 
                    q <= d;
798 
 
799 
endmodule
800 40 unneback 
`endif
801 8 unneback 
 
802 40 unneback 
`ifdef DF_CE_SET
803 
`define MODULE dff_ce_set
804 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
805 
`undef MODULE
806 24 unneback 
 
807 
        parameter width = 1;
808 
        parameter reset_value = 0;
809 
 
810 
        input [width-1:0] d;
811 
        input ce, set, clk, rst;
812 
        output reg [width-1:0] q;
813 
 
814 
        always @ (posedge clk or posedge rst)
815 
        if (rst)
816 
            q <= reset_value;
817 
        else
818 
            if (ce)
819 
                if (set)
820 
                    q <= {width{1'b1}};
821 
                else
822 
                    q <= d;
823 
 
824 
endmodule
825 40 unneback 
`endif
826 24 unneback 
 
827 40 unneback 
`ifdef SPR
828 
`define MODULE spr
829 
module `BASE`MODULE ( sp, r, q, clk, rst);
830 
`undef MODULE
831 
 
832 29 unneback 
        parameter width = 1;
833 
        parameter reset_value = 0;
834 
 
835 
        input sp, r;
836 
        output reg q;
837 
        input clk, rst;
838 
 
839 
        always @ (posedge clk or posedge rst)
840 
        if (rst)
841 
            q <= reset_value;
842 
        else
843 
            if (sp)
844 
                q <= 1'b1;
845 
            else if (r)
846 
                q <= 1'b0;
847 
 
848 
endmodule
849 40 unneback 
`endif
850 29 unneback 
 
851 40 unneback 
`ifdef SRP
852 
`define MODULE srp
853 
module `BASE`MODULE ( s, rp, q, clk, rst);
854 
`undef MODULE
855 
 
856 29 unneback 
        parameter width = 1;
857 
        parameter reset_value = 0;
858 
 
859 
        input s, rp;
860 
        output reg q;
861 
        input clk, rst;
862 
 
863 
        always @ (posedge clk or posedge rst)
864 
        if (rst)
865 
            q <= reset_value;
866 
        else
867 
            if (rp)
868 
                q <= 1'b0;
869 
            else if (s)
870 
                q <= 1'b1;
871 
 
872 
endmodule
873 40 unneback 
`endif
874 29 unneback 
 
875 40 unneback 
`ifdef ALTERA
876 29 unneback 
 
877 40 unneback 
`ifdef DFF_SR
878 6 unneback 
// megafunction wizard: %LPM_FF%
879 
// GENERATION: STANDARD
880 
// VERSION: WM1.0
881 
// MODULE: lpm_ff
882 
 
883 
// ============================================================
884 
// File Name: dff_sr.v
885 
// Megafunction Name(s):
886 
//                      lpm_ff
887 
//
888 
// Simulation Library Files(s):
889 
//                      lpm
890 
// ============================================================
891 
// ************************************************************
892 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
893 
//
894 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
895 
// ************************************************************
896 
 
897 
 
898 
//Copyright (C) 1991-2010 Altera Corporation
899 
//Your use of Altera Corporation's design tools, logic functions
900 
//and other software and tools, and its AMPP partner logic
901 
//functions, and any output files from any of the foregoing
902 
//(including device programming or simulation files), and any
903 
//associated documentation or information are expressly subject
904 
//to the terms and conditions of the Altera Program License
905 
//Subscription Agreement, Altera MegaCore Function License
906 
//Agreement, or other applicable license agreement, including,
907 
//without limitation, that your use is for the sole purpose of
908 
//programming logic devices manufactured by Altera and sold by
909 
//Altera or its authorized distributors.  Please refer to the
910 
//applicable agreement for further details.
911 
 
912 
 
913 
// synopsys translate_off
914 
`timescale 1 ps / 1 ps
915 
// synopsys translate_on
916 40 unneback 
`define MODULE dff_sr
917 
module `BASE`MODULE (
918 
`undef MODULE
919 
 
920 6 unneback 
        aclr,
921 
        aset,
922 
        clock,
923 
        data,
924 
        q);
925 
 
926 
        input     aclr;
927 
        input     aset;
928 
        input     clock;
929 
        input     data;
930 
        output    q;
931 
 
932 
        wire [0:0] sub_wire0;
933 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
934 
        wire  q = sub_wire1;
935 
        wire  sub_wire2 = data;
936 
        wire  sub_wire3 = sub_wire2;
937 
 
938 
        lpm_ff  lpm_ff_component (
939 
                                .aclr (aclr),
940 
                                .clock (clock),
941 
                                .data (sub_wire3),
942 
                                .aset (aset),
943 
                                .q (sub_wire0)
944 
                                // synopsys translate_off
945 
                                ,
946 
                                .aload (),
947 
                                .enable (),
948 
                                .sclr (),
949 
                                .sload (),
950 
                                .sset ()
951 
                                // synopsys translate_on
952 
                                );
953 
        defparam
954 
                lpm_ff_component.lpm_fftype = "DFF",
955 
                lpm_ff_component.lpm_type = "LPM_FF",
956 
                lpm_ff_component.lpm_width = 1;
957 
 
958 
 
959 
endmodule
960 
 
961 
// ============================================================
962 
// CNX file retrieval info
963 
// ============================================================
964 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
965 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
966 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
967 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
968 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
969 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
970 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
971 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
972 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
973 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
974 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
975 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
976 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
977 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
978 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
979 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
980 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
981 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
982 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
983 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
984 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
985 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
986 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
987 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
988 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
989 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
990 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
991 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
992 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
993 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
994 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
995 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
996 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
997 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
998 
// Retrieval info: LIB_FILE: lpm
999 40 unneback 
`endif
1000 6 unneback 
 
1001 
`else
1002 
 
1003 40 unneback 
`ifdef DFF_SR
1004 
`define MODULE dff_sr
1005 
module `BASE`MODULE ( aclr, aset, clock, data, q);
1006 
`undef MODULE
1007 6 unneback 
 
1008 
    input         aclr;
1009 
    input         aset;
1010 
    input         clock;
1011 
    input         data;
1012 
    output reg    q;
1013 
 
1014 
   always @ (posedge clock or posedge aclr or posedge aset)
1015 
     if (aclr)
1016 
       q <= 1'b0;
1017 
     else if (aset)
1018 
       q <= 1'b1;
1019 
     else
1020 
       q <= data;
1021 
 
1022 
endmodule
1023 40 unneback 
`endif
1024 6 unneback 
 
1025 
`endif
1026 
 
1027 
// LATCH
1028 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1029 
`ifdef ALTERA
1030 40 unneback 
 
1031 
`ifdef LATCH
1032 
`define MODULE latch
1033 
module `BASE`MODULE ( d, le, q, clk);
1034 
`undef MODULE
1035 6 unneback 
input d, le;
1036 
output q;
1037 
input clk;
1038 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1039 
endmodule
1040 40 unneback 
`endif
1041 
 
1042 6 unneback 
`else
1043 40 unneback 
 
1044 
`ifdef LATCH
1045 
`define MODULE latch
1046 
module `BASE`MODULE ( d, le, q, clk);
1047 
`undef MODULE
1048 6 unneback 
input d, le;
1049 48 unneback 
input clk;
1050 
always @ (le or d)
1051 60 unneback 
if (le)
1052 48 unneback 
    d <= q;
1053 6 unneback 
endmodule
1054 15 unneback 
`endif
1055 
 
1056 40 unneback 
`endif
1057 
 
1058 
`ifdef SHREG
1059 
`define MODULE shreg
1060 
module `BASE`MODULE ( d, q, clk, rst);
1061 
`undef MODULE
1062 
 
1063 17 unneback 
parameter depth = 10;
1064 
input d;
1065 
output q;
1066 
input clk, rst;
1067 
 
1068 
reg [1:depth] dffs;
1069 
 
1070 
always @ (posedge clk or posedge rst)
1071 
if (rst)
1072 
    dffs <= {depth{1'b0}};
1073 
else
1074 
    dffs <= {d,dffs[1:depth-1]};
1075 
assign q = dffs[depth];
1076 
endmodule
1077 40 unneback 
`endif
1078 17 unneback 
 
1079 40 unneback 
`ifdef SHREG_CE
1080 
`define MODULE shreg_ce
1081 
module `BASE`MODULE ( d, ce, q, clk, rst);
1082 
`undef MODULE
1083 17 unneback 
parameter depth = 10;
1084 
input d, ce;
1085 
output q;
1086 
input clk, rst;
1087 
 
1088 
reg [1:depth] dffs;
1089 
 
1090 
always @ (posedge clk or posedge rst)
1091 
if (rst)
1092 
    dffs <= {depth{1'b0}};
1093 
else
1094 
    if (ce)
1095 
        dffs <= {d,dffs[1:depth-1]};
1096 
assign q = dffs[depth];
1097 
endmodule
1098 40 unneback 
`endif
1099 17 unneback 
 
1100 40 unneback 
`ifdef DELAY
1101 
`define MODULE delay
1102 
module `BASE`MODULE ( d, q, clk, rst);
1103 
`undef MODULE
1104 15 unneback 
parameter depth = 10;
1105 
input d;
1106 
output q;
1107 
input clk, rst;
1108 
 
1109 
reg [1:depth] dffs;
1110 
 
1111 
always @ (posedge clk or posedge rst)
1112 
if (rst)
1113 
    dffs <= {depth{1'b0}};
1114 
else
1115 
    dffs <= {d,dffs[1:depth-1]};
1116 
assign q = dffs[depth];
1117 17 unneback 
endmodule
1118 40 unneback 
`endif
1119 17 unneback 
 
1120 40 unneback 
`ifdef DELAY_EMPTYFLAG
1121 
`define MODULE delay_emptyflag
1122 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1123 40 unneback 
`undef MODULE
1124 17 unneback 
parameter depth = 10;
1125 
input d;
1126 
output q, emptyflag;
1127 
input clk, rst;
1128 
 
1129 
reg [1:depth] dffs;
1130 
 
1131 
always @ (posedge clk or posedge rst)
1132 
if (rst)
1133 
    dffs <= {depth{1'b0}};
1134 
else
1135 
    dffs <= {d,dffs[1:depth-1]};
1136 
assign q = dffs[depth];
1137 
assign emptyflag = !(|dffs);
1138 
endmodule
1139 40 unneback 
`endif
1140 17 unneback 
//////////////////////////////////////////////////////////////////////
1141 6 unneback 
////                                                              ////
1142 18 unneback 
////  Logic functions                                             ////
1143 
////                                                              ////
1144 
////  Description                                                 ////
1145 
////  Logic functions such as multiplexers                        ////
1146 
////                                                              ////
1147 
////                                                              ////
1148 
////  To Do:                                                      ////
1149 
////   -                                                          ////
1150 
////                                                              ////
1151 
////  Author(s):                                                  ////
1152 
////      - Michael Unneback, unneback@opencores.org              ////
1153 
////        ORSoC AB                                              ////
1154 
////                                                              ////
1155 
//////////////////////////////////////////////////////////////////////
1156 
////                                                              ////
1157 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1158 
////                                                              ////
1159 
//// This source file may be used and distributed without         ////
1160 
//// restriction provided that this copyright statement is not    ////
1161 
//// removed from the file and that any derivative work contains  ////
1162 
//// the original copyright notice and the associated disclaimer. ////
1163 
////                                                              ////
1164 
//// This source file is free software; you can redistribute it   ////
1165 
//// and/or modify it under the terms of the GNU Lesser General   ////
1166 
//// Public License as published by the Free Software Foundation; ////
1167 
//// either version 2.1 of the License, or (at your option) any   ////
1168 
//// later version.                                               ////
1169 
////                                                              ////
1170 
//// This source is distributed in the hope that it will be       ////
1171 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1172 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1173 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1174 
//// details.                                                     ////
1175 
////                                                              ////
1176 
//// You should have received a copy of the GNU Lesser General    ////
1177 
//// Public License along with this source; if not, download it   ////
1178 
//// from http://www.opencores.org/lgpl.shtml                     ////
1179 
////                                                              ////
1180 
//////////////////////////////////////////////////////////////////////
1181 40 unneback 
`ifdef MUX_ANDOR
1182 
`define MODULE mux_andor
1183 
module `BASE`MODULE ( a, sel, dout);
1184 
`undef MODULE
1185 36 unneback 
 
1186 
parameter width = 32;
1187 
parameter nr_of_ports = 4;
1188 
 
1189 
input [nr_of_ports*width-1:0] a;
1190 
input [nr_of_ports-1:0] sel;
1191 
output reg [width-1:0] dout;
1192 
 
1193 38 unneback 
integer i,j;
1194 
 
1195 36 unneback 
always @ (a, sel)
1196 
begin
1197 
    dout = a[width-1:0] & {width{sel[0]}};
1198 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1199 
        for (j=0;j<width;j=j+1)
1200 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1201 36 unneback 
end
1202 
 
1203 
endmodule
1204 40 unneback 
`endif
1205 36 unneback 
 
1206 40 unneback 
`ifdef MUX2_ANDOR
1207 
`define MODULE mux2_andor
1208 
module `BASE`MODULE ( a1, a0, sel, dout);
1209 
`undef MODULE
1210 18 unneback 
 
1211 34 unneback 
parameter width = 32;
1212 35 unneback 
localparam nr_of_ports = 2;
1213 34 unneback 
input [width-1:0] a1, a0;
1214 
input [nr_of_ports-1:0] sel;
1215 
output [width-1:0] dout;
1216 
 
1217 40 unneback 
`define MODULE mux_andor
1218 
`BASE`MODULE
1219 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1220 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1221 40 unneback 
`undef MODULE
1222 
 
1223 34 unneback 
endmodule
1224 40 unneback 
`endif
1225 34 unneback 
 
1226 40 unneback 
`ifdef MUX3_ANDOR
1227 
`define MODULE mux3_andor
1228 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1229 
`undef MODULE
1230 34 unneback 
 
1231 
parameter width = 32;
1232 35 unneback 
localparam nr_of_ports = 3;
1233 34 unneback 
input [width-1:0] a2, a1, a0;
1234 
input [nr_of_ports-1:0] sel;
1235 
output [width-1:0] dout;
1236 
 
1237 40 unneback 
`define MODULE mux_andor
1238 
`BASE`MODULE
1239 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1240 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1241 40 unneback 
`undef MODULE
1242 34 unneback 
endmodule
1243 40 unneback 
`endif
1244 34 unneback 
 
1245 40 unneback 
`ifdef MUX4_ANDOR
1246 
`define MODULE mux4_andor
1247 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1248 
`undef MODULE
1249 18 unneback 
 
1250 
parameter width = 32;
1251 35 unneback 
localparam nr_of_ports = 4;
1252 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1253 
input [nr_of_ports-1:0] sel;
1254 22 unneback 
output [width-1:0] dout;
1255 18 unneback 
 
1256 40 unneback 
`define MODULE mux_andor
1257 
`BASE`MODULE
1258 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1259 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1260 40 unneback 
`undef MODULE
1261 18 unneback 
 
1262 
endmodule
1263 40 unneback 
`endif
1264 18 unneback 
 
1265 40 unneback 
`ifdef MUX5_ANDOR
1266 
`define MODULE mux5_andor
1267 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1268 
`undef MODULE
1269 18 unneback 
 
1270 
parameter width = 32;
1271 35 unneback 
localparam nr_of_ports = 5;
1272 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1273 
input [nr_of_ports-1:0] sel;
1274 22 unneback 
output [width-1:0] dout;
1275 18 unneback 
 
1276 40 unneback 
`define MODULE mux_andor
1277 
`BASE`MODULE
1278 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1279 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1280 40 unneback 
`undef MODULE
1281 18 unneback 
 
1282 
endmodule
1283 40 unneback 
`endif
1284 18 unneback 
 
1285 40 unneback 
`ifdef MUX6_ANDOR
1286 
`define MODULE mux6_andor
1287 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1288 
`undef MODULE
1289 18 unneback 
 
1290 
parameter width = 32;
1291 35 unneback 
localparam nr_of_ports = 6;
1292 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1293 
input [nr_of_ports-1:0] sel;
1294 22 unneback 
output [width-1:0] dout;
1295 18 unneback 
 
1296 40 unneback 
`define MODULE mux_andor
1297 
`BASE`MODULE
1298 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1299 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1300 40 unneback 
`undef MODULE
1301 18 unneback 
 
1302 
endmodule
1303 40 unneback 
`endif
1304 43 unneback 
 
1305 
`ifdef PARITY
1306 
 
1307 
`define MODULE parity_generate
1308 
module `BASE`MODULE (data, parity);
1309 
`undef MODULE
1310 
parameter word_size = 32;
1311 
parameter chunk_size = 8;
1312 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1313 
input [word_size-1:0] data;
1314 
output reg [word_size/chunk_size-1:0] parity;
1315 
integer i,j;
1316 
always @ (data)
1317 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1318 
    parity[i] = parity_type;
1319 
    for (j=0;j<chunk_size;j=j+1) begin
1320 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1321 43 unneback 
    end
1322 
end
1323 
endmodule
1324 
 
1325 
`define MODULE parity_check
1326 
module `BASE`MODULE( data, parity, parity_error);
1327 
`undef MODULE
1328 
parameter word_size = 32;
1329 
parameter chunk_size = 8;
1330 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1331 
input [word_size-1:0] data;
1332 
input [word_size/chunk_size-1:0] parity;
1333 
output parity_error;
1334 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1335 43 unneback 
integer i,j;
1336 
always @ (data or parity)
1337 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1338 
    error_flag[i] = parity[i] ^ parity_type;
1339 
    for (j=0;j<chunk_size;j=j+1) begin
1340 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1341 43 unneback 
    end
1342 
end
1343 
assign parity_error = |error_flag;
1344 
endmodule
1345 
 
1346 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1347 
////                                                              ////
1348 
////  IO functions                                                ////
1349 
////                                                              ////
1350 
////  Description                                                 ////
1351 
////  IO functions such as IOB flip-flops                         ////
1352 
////                                                              ////
1353 
////                                                              ////
1354 
////  To Do:                                                      ////
1355 
////   -                                                          ////
1356 
////                                                              ////
1357 
////  Author(s):                                                  ////
1358 
////      - Michael Unneback, unneback@opencores.org              ////
1359 
////        ORSoC AB                                              ////
1360 
////                                                              ////
1361 18 unneback 
//////////////////////////////////////////////////////////////////////
1362 
////                                                              ////
1363 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1364 
////                                                              ////
1365 
//// This source file may be used and distributed without         ////
1366 
//// restriction provided that this copyright statement is not    ////
1367 
//// removed from the file and that any derivative work contains  ////
1368 
//// the original copyright notice and the associated disclaimer. ////
1369 
////                                                              ////
1370 
//// This source file is free software; you can redistribute it   ////
1371 
//// and/or modify it under the terms of the GNU Lesser General   ////
1372 
//// Public License as published by the Free Software Foundation; ////
1373 
//// either version 2.1 of the License, or (at your option) any   ////
1374 
//// later version.                                               ////
1375 
////                                                              ////
1376 
//// This source is distributed in the hope that it will be       ////
1377 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1378 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1379 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1380 
//// details.                                                     ////
1381 
////                                                              ////
1382 
//// You should have received a copy of the GNU Lesser General    ////
1383 
//// Public License along with this source; if not, download it   ////
1384 
//// from http://www.opencores.org/lgpl.shtml                     ////
1385 
////                                                              ////
1386 
//////////////////////////////////////////////////////////////////////
1387 45 unneback 
`timescale 1ns/1ns
1388 44 unneback 
`ifdef O_DFF
1389 
`define MODULE o_dff
1390 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1391 
`undef MODULE
1392 
parameter width = 1;
1393 45 unneback 
parameter reset_value = {width{1'b0}};
1394 
input  [width-1:0]  d_i;
1395 44 unneback 
output [width-1:0] o_pad;
1396 
input clk, rst;
1397 
wire [width-1:0] d_i_int `SYN_KEEP;
1398 45 unneback 
reg  [width-1:0] o_pad_int;
1399 44 unneback 
assign d_i_int = d_i;
1400 
genvar i;
1401 45 unneback 
generate
1402 44 unneback 
for (i=0;i<width;i=i+1) begin
1403 
    always @ (posedge clk or posedge rst)
1404 
    if (rst)
1405 45 unneback 
        o_pad_int[i] <= reset_value[i];
1406 44 unneback 
    else
1407 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1408 
    assign #1 o_pad[i] = o_pad_int[i];
1409 44 unneback 
end
1410 
endgenerate
1411 
endmodule
1412 
`endif
1413 
 
1414 45 unneback 
`timescale 1ns/1ns
1415 44 unneback 
`ifdef IO_DFF_OE
1416 
`define MODULE io_dff_oe
1417 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1418 
`undef MODULE
1419 
parameter width = 1;
1420 
input  [width-1:0] d_o;
1421 
output reg [width-1:0] d_i;
1422 
input oe;
1423 
inout [width-1:0] io_pad;
1424 
input clk, rst;
1425 
wire [width-1:0] oe_d `SYN_KEEP;
1426 
reg [width-1:0] oe_q;
1427 
reg [width-1:0] d_o_q;
1428 
assign oe_d = {width{oe}};
1429 
genvar i;
1430 
generate
1431 
for (i=0;i<width;i=i+1) begin
1432 
    always @ (posedge clk or posedge rst)
1433 
    if (rst)
1434 
        oe_q[i] <= 1'b0;
1435 
    else
1436 
        oe_q[i] <= oe_d[i];
1437 
    always @ (posedge clk or posedge rst)
1438 
    if (rst)
1439 
        d_o_q[i] <= 1'b0;
1440 
    else
1441 
        d_o_q[i] <= d_o[i];
1442 
    always @ (posedge clk or posedge rst)
1443 
    if (rst)
1444 
        d_i[i] <= 1'b0;
1445 
    else
1446 
        d_i[i] <= io_pad[i];
1447 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1448 44 unneback 
end
1449 
endgenerate
1450 
endmodule
1451 
`endif
1452 
`ifdef CNT_BIN
1453 
//////////////////////////////////////////////////////////////////////
1454 
////                                                              ////
1455 6 unneback 
////  Versatile counter                                           ////
1456 
////                                                              ////
1457 
////  Description                                                 ////
1458 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1459 
////  counter                                                     ////
1460 
////                                                              ////
1461 
////  To Do:                                                      ////
1462 
////   - add LFSR with more taps                                  ////
1463 
////                                                              ////
1464 
////  Author(s):                                                  ////
1465 
////      - Michael Unneback, unneback@opencores.org              ////
1466 
////        ORSoC AB                                              ////
1467 
////                                                              ////
1468 
//////////////////////////////////////////////////////////////////////
1469 
////                                                              ////
1470 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1471 
////                                                              ////
1472 
//// This source file may be used and distributed without         ////
1473 
//// restriction provided that this copyright statement is not    ////
1474 
//// removed from the file and that any derivative work contains  ////
1475 
//// the original copyright notice and the associated disclaimer. ////
1476 
////                                                              ////
1477 
//// This source file is free software; you can redistribute it   ////
1478 
//// and/or modify it under the terms of the GNU Lesser General   ////
1479 
//// Public License as published by the Free Software Foundation; ////
1480 
//// either version 2.1 of the License, or (at your option) any   ////
1481 
//// later version.                                               ////
1482 
////                                                              ////
1483 
//// This source is distributed in the hope that it will be       ////
1484 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1485 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1486 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1487 
//// details.                                                     ////
1488 
////                                                              ////
1489 
//// You should have received a copy of the GNU Lesser General    ////
1490 
//// Public License along with this source; if not, download it   ////
1491 
//// from http://www.opencores.org/lgpl.shtml                     ////
1492 
////                                                              ////
1493 
//////////////////////////////////////////////////////////////////////
1494 
 
1495 
// binary counter
1496 22 unneback 
 
1497 40 unneback 
`define MODULE cnt_bin
1498 
module `BASE`MODULE (
1499 
`undef MODULE
1500 
 q, rst, clk);
1501 
 
1502 22 unneback 
   parameter length = 4;
1503 
   output [length:1] q;
1504 
   input rst;
1505 
   input clk;
1506 
 
1507 
   parameter clear_value = 0;
1508 
   parameter set_value = 1;
1509 
   parameter wrap_value = 0;
1510 
   parameter level1_value = 15;
1511 
 
1512 
   reg  [length:1] qi;
1513 
   wire [length:1] q_next;
1514 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1515 
 
1516 
   always @ (posedge clk or posedge rst)
1517 
     if (rst)
1518 
       qi <= {length{1'b0}};
1519 
     else
1520 
       qi <= q_next;
1521 
 
1522 
   assign q = qi;
1523 
 
1524 
endmodule
1525 40 unneback 
`endif
1526 
`ifdef CNT_BIN_CLEAR
1527 22 unneback 
//////////////////////////////////////////////////////////////////////
1528 
////                                                              ////
1529 
////  Versatile counter                                           ////
1530 
////                                                              ////
1531 
////  Description                                                 ////
1532 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1533 
////  counter                                                     ////
1534 
////                                                              ////
1535 
////  To Do:                                                      ////
1536 
////   - add LFSR with more taps                                  ////
1537 
////                                                              ////
1538 
////  Author(s):                                                  ////
1539 
////      - Michael Unneback, unneback@opencores.org              ////
1540 
////        ORSoC AB                                              ////
1541 
////                                                              ////
1542 
//////////////////////////////////////////////////////////////////////
1543 
////                                                              ////
1544 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1545 
////                                                              ////
1546 
//// This source file may be used and distributed without         ////
1547 
//// restriction provided that this copyright statement is not    ////
1548 
//// removed from the file and that any derivative work contains  ////
1549 
//// the original copyright notice and the associated disclaimer. ////
1550 
////                                                              ////
1551 
//// This source file is free software; you can redistribute it   ////
1552 
//// and/or modify it under the terms of the GNU Lesser General   ////
1553 
//// Public License as published by the Free Software Foundation; ////
1554 
//// either version 2.1 of the License, or (at your option) any   ////
1555 
//// later version.                                               ////
1556 
////                                                              ////
1557 
//// This source is distributed in the hope that it will be       ////
1558 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1559 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1560 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1561 
//// details.                                                     ////
1562 
////                                                              ////
1563 
//// You should have received a copy of the GNU Lesser General    ////
1564 
//// Public License along with this source; if not, download it   ////
1565 
//// from http://www.opencores.org/lgpl.shtml                     ////
1566 
////                                                              ////
1567 
//////////////////////////////////////////////////////////////////////
1568 
 
1569 
// binary counter
1570 
 
1571 40 unneback 
`define MODULE cnt_bin_clear
1572 
module `BASE`MODULE (
1573 
`undef MODULE
1574 
 clear, q, rst, clk);
1575 
 
1576 22 unneback 
   parameter length = 4;
1577 
   input clear;
1578 
   output [length:1] q;
1579 
   input rst;
1580 
   input clk;
1581 
 
1582 
   parameter clear_value = 0;
1583 
   parameter set_value = 1;
1584 
   parameter wrap_value = 0;
1585 
   parameter level1_value = 15;
1586 
 
1587 
   reg  [length:1] qi;
1588 
   wire [length:1] q_next;
1589 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1590 
 
1591 
   always @ (posedge clk or posedge rst)
1592 
     if (rst)
1593 
       qi <= {length{1'b0}};
1594 
     else
1595 
       qi <= q_next;
1596 
 
1597 
   assign q = qi;
1598 
 
1599 
endmodule
1600 40 unneback 
`endif
1601 
`ifdef CNT_BIN_CE
1602 22 unneback 
//////////////////////////////////////////////////////////////////////
1603 
////                                                              ////
1604 
////  Versatile counter                                           ////
1605 
////                                                              ////
1606 
////  Description                                                 ////
1607 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1608 
////  counter                                                     ////
1609 
////                                                              ////
1610 
////  To Do:                                                      ////
1611 
////   - add LFSR with more taps                                  ////
1612 
////                                                              ////
1613 
////  Author(s):                                                  ////
1614 
////      - Michael Unneback, unneback@opencores.org              ////
1615 
////        ORSoC AB                                              ////
1616 
////                                                              ////
1617 
//////////////////////////////////////////////////////////////////////
1618 
////                                                              ////
1619 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1620 
////                                                              ////
1621 
//// This source file may be used and distributed without         ////
1622 
//// restriction provided that this copyright statement is not    ////
1623 
//// removed from the file and that any derivative work contains  ////
1624 
//// the original copyright notice and the associated disclaimer. ////
1625 
////                                                              ////
1626 
//// This source file is free software; you can redistribute it   ////
1627 
//// and/or modify it under the terms of the GNU Lesser General   ////
1628 
//// Public License as published by the Free Software Foundation; ////
1629 
//// either version 2.1 of the License, or (at your option) any   ////
1630 
//// later version.                                               ////
1631 
////                                                              ////
1632 
//// This source is distributed in the hope that it will be       ////
1633 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1634 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1635 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1636 
//// details.                                                     ////
1637 
////                                                              ////
1638 
//// You should have received a copy of the GNU Lesser General    ////
1639 
//// Public License along with this source; if not, download it   ////
1640 
//// from http://www.opencores.org/lgpl.shtml                     ////
1641 
////                                                              ////
1642 
//////////////////////////////////////////////////////////////////////
1643 
 
1644 
// binary counter
1645 6 unneback 
 
1646 40 unneback 
`define MODULE cnt_bin_ce
1647 
module `BASE`MODULE (
1648 
`undef MODULE
1649 
 cke, q, rst, clk);
1650 
 
1651 6 unneback 
   parameter length = 4;
1652 
   input cke;
1653 
   output [length:1] q;
1654 
   input rst;
1655 
   input clk;
1656 
 
1657 
   parameter clear_value = 0;
1658 
   parameter set_value = 1;
1659 
   parameter wrap_value = 0;
1660 
   parameter level1_value = 15;
1661 
 
1662 
   reg  [length:1] qi;
1663 
   wire [length:1] q_next;
1664 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1665 
 
1666 
   always @ (posedge clk or posedge rst)
1667 
     if (rst)
1668 
       qi <= {length{1'b0}};
1669 
     else
1670 
     if (cke)
1671 
       qi <= q_next;
1672 
 
1673 
   assign q = qi;
1674 
 
1675 
endmodule
1676 40 unneback 
`endif
1677 
`ifdef CNT_BIN_CE_CLEAR
1678 6 unneback 
//////////////////////////////////////////////////////////////////////
1679 
////                                                              ////
1680 
////  Versatile counter                                           ////
1681 
////                                                              ////
1682 
////  Description                                                 ////
1683 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1684 
////  counter                                                     ////
1685 
////                                                              ////
1686 
////  To Do:                                                      ////
1687 
////   - add LFSR with more taps                                  ////
1688 
////                                                              ////
1689 
////  Author(s):                                                  ////
1690 
////      - Michael Unneback, unneback@opencores.org              ////
1691 
////        ORSoC AB                                              ////
1692 
////                                                              ////
1693 
//////////////////////////////////////////////////////////////////////
1694 
////                                                              ////
1695 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1696 
////                                                              ////
1697 
//// This source file may be used and distributed without         ////
1698 
//// restriction provided that this copyright statement is not    ////
1699 
//// removed from the file and that any derivative work contains  ////
1700 
//// the original copyright notice and the associated disclaimer. ////
1701 
////                                                              ////
1702 
//// This source file is free software; you can redistribute it   ////
1703 
//// and/or modify it under the terms of the GNU Lesser General   ////
1704 
//// Public License as published by the Free Software Foundation; ////
1705 
//// either version 2.1 of the License, or (at your option) any   ////
1706 
//// later version.                                               ////
1707 
////                                                              ////
1708 
//// This source is distributed in the hope that it will be       ////
1709 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1710 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1711 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1712 
//// details.                                                     ////
1713 
////                                                              ////
1714 
//// You should have received a copy of the GNU Lesser General    ////
1715 
//// Public License along with this source; if not, download it   ////
1716 
//// from http://www.opencores.org/lgpl.shtml                     ////
1717 
////                                                              ////
1718 
//////////////////////////////////////////////////////////////////////
1719 
 
1720 
// binary counter
1721 
 
1722 40 unneback 
`define MODULE cnt_bin_ce_clear
1723 
module `BASE`MODULE (
1724 
`undef MODULE
1725 
 clear, cke, q, rst, clk);
1726 
 
1727 6 unneback 
   parameter length = 4;
1728 
   input clear;
1729 
   input cke;
1730 
   output [length:1] q;
1731 
   input rst;
1732 
   input clk;
1733 
 
1734 
   parameter clear_value = 0;
1735 
   parameter set_value = 1;
1736 
   parameter wrap_value = 0;
1737 
   parameter level1_value = 15;
1738 
 
1739 
   reg  [length:1] qi;
1740 
   wire [length:1] q_next;
1741 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1742 
 
1743 
   always @ (posedge clk or posedge rst)
1744 
     if (rst)
1745 
       qi <= {length{1'b0}};
1746 
     else
1747 
     if (cke)
1748 
       qi <= q_next;
1749 
 
1750 
   assign q = qi;
1751 
 
1752 
endmodule
1753 40 unneback 
`endif
1754 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1755 6 unneback 
//////////////////////////////////////////////////////////////////////
1756 
////                                                              ////
1757 
////  Versatile counter                                           ////
1758 
////                                                              ////
1759 
////  Description                                                 ////
1760 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1761 
////  counter                                                     ////
1762 
////                                                              ////
1763 
////  To Do:                                                      ////
1764 
////   - add LFSR with more taps                                  ////
1765 
////                                                              ////
1766 
////  Author(s):                                                  ////
1767 
////      - Michael Unneback, unneback@opencores.org              ////
1768 
////        ORSoC AB                                              ////
1769 
////                                                              ////
1770 
//////////////////////////////////////////////////////////////////////
1771 
////                                                              ////
1772 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1773 
////                                                              ////
1774 
//// This source file may be used and distributed without         ////
1775 
//// restriction provided that this copyright statement is not    ////
1776 
//// removed from the file and that any derivative work contains  ////
1777 
//// the original copyright notice and the associated disclaimer. ////
1778 
////                                                              ////
1779 
//// This source file is free software; you can redistribute it   ////
1780 
//// and/or modify it under the terms of the GNU Lesser General   ////
1781 
//// Public License as published by the Free Software Foundation; ////
1782 
//// either version 2.1 of the License, or (at your option) any   ////
1783 
//// later version.                                               ////
1784 
////                                                              ////
1785 
//// This source is distributed in the hope that it will be       ////
1786 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1787 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1788 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1789 
//// details.                                                     ////
1790 
////                                                              ////
1791 
//// You should have received a copy of the GNU Lesser General    ////
1792 
//// Public License along with this source; if not, download it   ////
1793 
//// from http://www.opencores.org/lgpl.shtml                     ////
1794 
////                                                              ////
1795 
//////////////////////////////////////////////////////////////////////
1796 
 
1797 
// binary counter
1798 29 unneback 
 
1799 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1800 
module `BASE`MODULE (
1801 
`undef MODULE
1802 
 clear, cke, q, level1, level2, rst, clk);
1803 
 
1804 29 unneback 
   parameter length = 4;
1805 
   input clear;
1806 
   input cke;
1807 
   output [length:1] q;
1808 
   output reg level1;
1809 
   output reg level2;
1810 
   input rst;
1811 
   input clk;
1812 
 
1813 
   parameter clear_value = 0;
1814 
   parameter set_value = 1;
1815 30 unneback 
   parameter wrap_value = 15;
1816 
   parameter level1_value = 8;
1817 
   parameter level2_value = 15;
1818 29 unneback 
 
1819 
   wire rew;
1820 30 unneback 
   assign rew = 1'b0;
1821 29 unneback 
   reg  [length:1] qi;
1822 
   wire [length:1] q_next;
1823 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1824 
 
1825 
   always @ (posedge clk or posedge rst)
1826 
     if (rst)
1827 
       qi <= {length{1'b0}};
1828 
     else
1829 
     if (cke)
1830 
       qi <= q_next;
1831 
 
1832 
   assign q = qi;
1833 
 
1834 
 
1835 
    always @ (posedge clk or posedge rst)
1836 
    if (rst)
1837 
        level1 <= 1'b0;
1838 
    else
1839 
    if (cke)
1840 
    if (clear)
1841 
        level1 <= 1'b0;
1842 
    else if (q_next == level1_value)
1843 
        level1 <= 1'b1;
1844 
    else if (qi == level1_value & rew)
1845 
        level1 <= 1'b0;
1846 
 
1847 
    always @ (posedge clk or posedge rst)
1848 
    if (rst)
1849 
        level2 <= 1'b0;
1850 
    else
1851 
    if (cke)
1852 
    if (clear)
1853 
        level2 <= 1'b0;
1854 
    else if (q_next == level2_value)
1855 
        level2 <= 1'b1;
1856 
    else if (qi == level2_value & rew)
1857 
        level2 <= 1'b0;
1858 
endmodule
1859 40 unneback 
`endif
1860 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1861 29 unneback 
//////////////////////////////////////////////////////////////////////
1862 
////                                                              ////
1863 
////  Versatile counter                                           ////
1864 
////                                                              ////
1865 
////  Description                                                 ////
1866 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1867 
////  counter                                                     ////
1868 
////                                                              ////
1869 
////  To Do:                                                      ////
1870 
////   - add LFSR with more taps                                  ////
1871 
////                                                              ////
1872 
////  Author(s):                                                  ////
1873 
////      - Michael Unneback, unneback@opencores.org              ////
1874 
////        ORSoC AB                                              ////
1875 
////                                                              ////
1876 
//////////////////////////////////////////////////////////////////////
1877 
////                                                              ////
1878 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1879 
////                                                              ////
1880 
//// This source file may be used and distributed without         ////
1881 
//// restriction provided that this copyright statement is not    ////
1882 
//// removed from the file and that any derivative work contains  ////
1883 
//// the original copyright notice and the associated disclaimer. ////
1884 
////                                                              ////
1885 
//// This source file is free software; you can redistribute it   ////
1886 
//// and/or modify it under the terms of the GNU Lesser General   ////
1887 
//// Public License as published by the Free Software Foundation; ////
1888 
//// either version 2.1 of the License, or (at your option) any   ////
1889 
//// later version.                                               ////
1890 
////                                                              ////
1891 
//// This source is distributed in the hope that it will be       ////
1892 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1893 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1894 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1895 
//// details.                                                     ////
1896 
////                                                              ////
1897 
//// You should have received a copy of the GNU Lesser General    ////
1898 
//// Public License along with this source; if not, download it   ////
1899 
//// from http://www.opencores.org/lgpl.shtml                     ////
1900 
////                                                              ////
1901 
//////////////////////////////////////////////////////////////////////
1902 
 
1903 
// binary counter
1904 6 unneback 
 
1905 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
1906 
module `BASE`MODULE (
1907 
`undef MODULE
1908 
 clear, set, cke, rew, q, rst, clk);
1909 
 
1910 6 unneback 
   parameter length = 4;
1911 
   input clear;
1912 
   input set;
1913 
   input cke;
1914 
   input rew;
1915 
   output [length:1] q;
1916 
   input rst;
1917 
   input clk;
1918 
 
1919 
   parameter clear_value = 0;
1920 
   parameter set_value = 1;
1921 
   parameter wrap_value = 0;
1922 
   parameter level1_value = 15;
1923 
 
1924 
   reg  [length:1] qi;
1925 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1926 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1927 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1928 
   assign q_next = rew ? q_next_rew : q_next_fw;
1929 
 
1930 
   always @ (posedge clk or posedge rst)
1931 
     if (rst)
1932 
       qi <= {length{1'b0}};
1933 
     else
1934 
     if (cke)
1935 
       qi <= q_next;
1936 
 
1937 
   assign q = qi;
1938 
 
1939 
endmodule
1940 40 unneback 
`endif
1941 
`ifdef CNT_BIN_CE_REW_L1
1942 6 unneback 
//////////////////////////////////////////////////////////////////////
1943 
////                                                              ////
1944 
////  Versatile counter                                           ////
1945 
////                                                              ////
1946 
////  Description                                                 ////
1947 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1948 
////  counter                                                     ////
1949 
////                                                              ////
1950 
////  To Do:                                                      ////
1951 
////   - add LFSR with more taps                                  ////
1952 
////                                                              ////
1953 
////  Author(s):                                                  ////
1954 
////      - Michael Unneback, unneback@opencores.org              ////
1955 
////        ORSoC AB                                              ////
1956 
////                                                              ////
1957 
//////////////////////////////////////////////////////////////////////
1958 
////                                                              ////
1959 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1960 
////                                                              ////
1961 
//// This source file may be used and distributed without         ////
1962 
//// restriction provided that this copyright statement is not    ////
1963 
//// removed from the file and that any derivative work contains  ////
1964 
//// the original copyright notice and the associated disclaimer. ////
1965 
////                                                              ////
1966 
//// This source file is free software; you can redistribute it   ////
1967 
//// and/or modify it under the terms of the GNU Lesser General   ////
1968 
//// Public License as published by the Free Software Foundation; ////
1969 
//// either version 2.1 of the License, or (at your option) any   ////
1970 
//// later version.                                               ////
1971 
////                                                              ////
1972 
//// This source is distributed in the hope that it will be       ////
1973 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1974 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1975 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1976 
//// details.                                                     ////
1977 
////                                                              ////
1978 
//// You should have received a copy of the GNU Lesser General    ////
1979 
//// Public License along with this source; if not, download it   ////
1980 
//// from http://www.opencores.org/lgpl.shtml                     ////
1981 
////                                                              ////
1982 
//////////////////////////////////////////////////////////////////////
1983 
 
1984 
// binary counter
1985 
 
1986 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
1987 
module `BASE`MODULE (
1988 
`undef MODULE
1989 
 cke, rew, level1, rst, clk);
1990 
 
1991 6 unneback 
   parameter length = 4;
1992 
   input cke;
1993 
   input rew;
1994 
   output reg level1;
1995 
   input rst;
1996 
   input clk;
1997 
 
1998 
   parameter clear_value = 0;
1999 
   parameter set_value = 1;
2000 
   parameter wrap_value = 1;
2001 
   parameter level1_value = 15;
2002 
 
2003 29 unneback 
   wire clear;
2004 30 unneback 
   assign clear = 1'b0;
2005 6 unneback 
   reg  [length:1] qi;
2006 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2007 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2008 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2009 
   assign q_next = rew ? q_next_rew : q_next_fw;
2010 
 
2011 
   always @ (posedge clk or posedge rst)
2012 
     if (rst)
2013 
       qi <= {length{1'b0}};
2014 
     else
2015 
     if (cke)
2016 
       qi <= q_next;
2017 
 
2018 
 
2019 
 
2020 
    always @ (posedge clk or posedge rst)
2021 
    if (rst)
2022 
        level1 <= 1'b0;
2023 
    else
2024 
    if (cke)
2025 29 unneback 
    if (clear)
2026 
        level1 <= 1'b0;
2027 
    else if (q_next == level1_value)
2028 6 unneback 
        level1 <= 1'b1;
2029 
    else if (qi == level1_value & rew)
2030 
        level1 <= 1'b0;
2031 
endmodule
2032 40 unneback 
`endif
2033 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2034 6 unneback 
//////////////////////////////////////////////////////////////////////
2035 
////                                                              ////
2036 
////  Versatile counter                                           ////
2037 
////                                                              ////
2038 
////  Description                                                 ////
2039 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2040 
////  counter                                                     ////
2041 
////                                                              ////
2042 
////  To Do:                                                      ////
2043 
////   - add LFSR with more taps                                  ////
2044 
////                                                              ////
2045 
////  Author(s):                                                  ////
2046 
////      - Michael Unneback, unneback@opencores.org              ////
2047 
////        ORSoC AB                                              ////
2048 
////                                                              ////
2049 
//////////////////////////////////////////////////////////////////////
2050 
////                                                              ////
2051 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2052 
////                                                              ////
2053 
//// This source file may be used and distributed without         ////
2054 
//// restriction provided that this copyright statement is not    ////
2055 
//// removed from the file and that any derivative work contains  ////
2056 
//// the original copyright notice and the associated disclaimer. ////
2057 
////                                                              ////
2058 
//// This source file is free software; you can redistribute it   ////
2059 
//// and/or modify it under the terms of the GNU Lesser General   ////
2060 
//// Public License as published by the Free Software Foundation; ////
2061 
//// either version 2.1 of the License, or (at your option) any   ////
2062 
//// later version.                                               ////
2063 
////                                                              ////
2064 
//// This source is distributed in the hope that it will be       ////
2065 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2066 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2067 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2068 
//// details.                                                     ////
2069 
////                                                              ////
2070 
//// You should have received a copy of the GNU Lesser General    ////
2071 
//// Public License along with this source; if not, download it   ////
2072 
//// from http://www.opencores.org/lgpl.shtml                     ////
2073 
////                                                              ////
2074 
//////////////////////////////////////////////////////////////////////
2075 
 
2076 25 unneback 
// binary counter
2077 
 
2078 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2079 
module `BASE`MODULE (
2080 
`undef MODULE
2081 
 cke, rew, zq, level1, rst, clk);
2082 
 
2083 25 unneback 
   parameter length = 4;
2084 
   input cke;
2085 
   input rew;
2086 
   output reg zq;
2087 
   output reg level1;
2088 
   input rst;
2089 
   input clk;
2090 
 
2091 
   parameter clear_value = 0;
2092 
   parameter set_value = 1;
2093 
   parameter wrap_value = 1;
2094 
   parameter level1_value = 15;
2095 
 
2096 29 unneback 
   wire clear;
2097 30 unneback 
   assign clear = 1'b0;
2098 25 unneback 
   reg  [length:1] qi;
2099 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2100 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2101 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2102 
   assign q_next = rew ? q_next_rew : q_next_fw;
2103 
 
2104 
   always @ (posedge clk or posedge rst)
2105 
     if (rst)
2106 
       qi <= {length{1'b0}};
2107 
     else
2108 
     if (cke)
2109 
       qi <= q_next;
2110 
 
2111 
 
2112 
 
2113 
   always @ (posedge clk or posedge rst)
2114 
     if (rst)
2115 
       zq <= 1'b1;
2116 
     else
2117 
     if (cke)
2118 
       zq <= q_next == {length{1'b0}};
2119 
 
2120 
    always @ (posedge clk or posedge rst)
2121 
    if (rst)
2122 
        level1 <= 1'b0;
2123 
    else
2124 
    if (cke)
2125 29 unneback 
    if (clear)
2126 
        level1 <= 1'b0;
2127 
    else if (q_next == level1_value)
2128 25 unneback 
        level1 <= 1'b1;
2129 
    else if (qi == level1_value & rew)
2130 
        level1 <= 1'b0;
2131 
endmodule
2132 40 unneback 
`endif
2133 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2134 25 unneback 
//////////////////////////////////////////////////////////////////////
2135 
////                                                              ////
2136 
////  Versatile counter                                           ////
2137 
////                                                              ////
2138 
////  Description                                                 ////
2139 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2140 
////  counter                                                     ////
2141 
////                                                              ////
2142 
////  To Do:                                                      ////
2143 
////   - add LFSR with more taps                                  ////
2144 
////                                                              ////
2145 
////  Author(s):                                                  ////
2146 
////      - Michael Unneback, unneback@opencores.org              ////
2147 
////        ORSoC AB                                              ////
2148 
////                                                              ////
2149 
//////////////////////////////////////////////////////////////////////
2150 
////                                                              ////
2151 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2152 
////                                                              ////
2153 
//// This source file may be used and distributed without         ////
2154 
//// restriction provided that this copyright statement is not    ////
2155 
//// removed from the file and that any derivative work contains  ////
2156 
//// the original copyright notice and the associated disclaimer. ////
2157 
////                                                              ////
2158 
//// This source file is free software; you can redistribute it   ////
2159 
//// and/or modify it under the terms of the GNU Lesser General   ////
2160 
//// Public License as published by the Free Software Foundation; ////
2161 
//// either version 2.1 of the License, or (at your option) any   ////
2162 
//// later version.                                               ////
2163 
////                                                              ////
2164 
//// This source is distributed in the hope that it will be       ////
2165 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2166 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2167 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2168 
//// details.                                                     ////
2169 
////                                                              ////
2170 
//// You should have received a copy of the GNU Lesser General    ////
2171 
//// Public License along with this source; if not, download it   ////
2172 
//// from http://www.opencores.org/lgpl.shtml                     ////
2173 
////                                                              ////
2174 
//////////////////////////////////////////////////////////////////////
2175 
 
2176 
// binary counter
2177 
 
2178 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2179 
module `BASE`MODULE (
2180 
`undef MODULE
2181 
 cke, rew, q, zq, level1, rst, clk);
2182 
 
2183 25 unneback 
   parameter length = 4;
2184 
   input cke;
2185 
   input rew;
2186 
   output [length:1] q;
2187 
   output reg zq;
2188 
   output reg level1;
2189 
   input rst;
2190 
   input clk;
2191 
 
2192 
   parameter clear_value = 0;
2193 
   parameter set_value = 1;
2194 
   parameter wrap_value = 1;
2195 
   parameter level1_value = 15;
2196 
 
2197 29 unneback 
   wire clear;
2198 30 unneback 
   assign clear = 1'b0;
2199 25 unneback 
   reg  [length:1] qi;
2200 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2201 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2202 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2203 
   assign q_next = rew ? q_next_rew : q_next_fw;
2204 
 
2205 
   always @ (posedge clk or posedge rst)
2206 
     if (rst)
2207 
       qi <= {length{1'b0}};
2208 
     else
2209 
     if (cke)
2210 
       qi <= q_next;
2211 
 
2212 
   assign q = qi;
2213 
 
2214 
 
2215 
   always @ (posedge clk or posedge rst)
2216 
     if (rst)
2217 
       zq <= 1'b1;
2218 
     else
2219 
     if (cke)
2220 
       zq <= q_next == {length{1'b0}};
2221 
 
2222 
    always @ (posedge clk or posedge rst)
2223 
    if (rst)
2224 
        level1 <= 1'b0;
2225 
    else
2226 
    if (cke)
2227 29 unneback 
    if (clear)
2228 
        level1 <= 1'b0;
2229 
    else if (q_next == level1_value)
2230 25 unneback 
        level1 <= 1'b1;
2231 
    else if (qi == level1_value & rew)
2232 
        level1 <= 1'b0;
2233 
endmodule
2234 40 unneback 
`endif
2235 
`ifdef CNT_LFSR_ZQ
2236 25 unneback 
//////////////////////////////////////////////////////////////////////
2237 
////                                                              ////
2238 
////  Versatile counter                                           ////
2239 
////                                                              ////
2240 
////  Description                                                 ////
2241 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2242 
////  counter                                                     ////
2243 
////                                                              ////
2244 
////  To Do:                                                      ////
2245 
////   - add LFSR with more taps                                  ////
2246 
////                                                              ////
2247 
////  Author(s):                                                  ////
2248 
////      - Michael Unneback, unneback@opencores.org              ////
2249 
////        ORSoC AB                                              ////
2250 
////                                                              ////
2251 
//////////////////////////////////////////////////////////////////////
2252 
////                                                              ////
2253 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2254 
////                                                              ////
2255 
//// This source file may be used and distributed without         ////
2256 
//// restriction provided that this copyright statement is not    ////
2257 
//// removed from the file and that any derivative work contains  ////
2258 
//// the original copyright notice and the associated disclaimer. ////
2259 
////                                                              ////
2260 
//// This source file is free software; you can redistribute it   ////
2261 
//// and/or modify it under the terms of the GNU Lesser General   ////
2262 
//// Public License as published by the Free Software Foundation; ////
2263 
//// either version 2.1 of the License, or (at your option) any   ////
2264 
//// later version.                                               ////
2265 
////                                                              ////
2266 
//// This source is distributed in the hope that it will be       ////
2267 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2268 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2269 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2270 
//// details.                                                     ////
2271 
////                                                              ////
2272 
//// You should have received a copy of the GNU Lesser General    ////
2273 
//// Public License along with this source; if not, download it   ////
2274 
//// from http://www.opencores.org/lgpl.shtml                     ////
2275 
////                                                              ////
2276 
//////////////////////////////////////////////////////////////////////
2277 
 
2278 6 unneback 
// LFSR counter
2279 
 
2280 40 unneback 
`define MODULE cnt_lfsr_zq
2281 
module `BASE`MODULE (
2282 
`undef MODULE
2283 
 zq, rst, clk);
2284 
 
2285 6 unneback 
   parameter length = 4;
2286 
   output reg zq;
2287 
   input rst;
2288 
   input clk;
2289 
 
2290 
   parameter clear_value = 0;
2291 
   parameter set_value = 1;
2292 
   parameter wrap_value = 8;
2293 
   parameter level1_value = 15;
2294 
 
2295 
   reg  [length:1] qi;
2296 
   reg lfsr_fb;
2297 
   wire [length:1] q_next;
2298 
   reg [32:1] polynom;
2299 
   integer i;
2300 
 
2301 
   always @ (qi)
2302 
   begin
2303 
        case (length)
2304 
         2: polynom = 32'b11;                               // 0x3
2305 
         3: polynom = 32'b110;                              // 0x6
2306 
         4: polynom = 32'b1100;                             // 0xC
2307 
         5: polynom = 32'b10100;                            // 0x14
2308 
         6: polynom = 32'b110000;                           // 0x30
2309 
         7: polynom = 32'b1100000;                          // 0x60
2310 
         8: polynom = 32'b10111000;                         // 0xb8
2311 
         9: polynom = 32'b100010000;                        // 0x110
2312 
        10: polynom = 32'b1001000000;                       // 0x240
2313 
        11: polynom = 32'b10100000000;                      // 0x500
2314 
        12: polynom = 32'b100000101001;                     // 0x829
2315 
        13: polynom = 32'b1000000001100;                    // 0x100C
2316 
        14: polynom = 32'b10000000010101;                   // 0x2015
2317 
        15: polynom = 32'b110000000000000;                  // 0x6000
2318 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2319 
        17: polynom = 32'b10010000000000000;                // 0x12000
2320 
        18: polynom = 32'b100000010000000000;               // 0x20400
2321 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2322 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2323 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2324 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2325 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2326 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2327 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2328 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2329 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2330 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2331 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2332 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2333 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2334 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2335 
        default: polynom = 32'b0;
2336 
        endcase
2337 
        lfsr_fb = qi[length];
2338 
        for (i=length-1; i>=1; i=i-1) begin
2339 
            if (polynom[i])
2340 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2341 
        end
2342 
    end
2343 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2344 
 
2345 
   always @ (posedge clk or posedge rst)
2346 
     if (rst)
2347 
       qi <= {length{1'b0}};
2348 
     else
2349 
       qi <= q_next;
2350 
 
2351 
 
2352 
 
2353 
   always @ (posedge clk or posedge rst)
2354 
     if (rst)
2355 
       zq <= 1'b1;
2356 
     else
2357 
       zq <= q_next == {length{1'b0}};
2358 
endmodule
2359 40 unneback 
`endif
2360 
`ifdef CNT_LFSR_CE_ZQ
2361 6 unneback 
//////////////////////////////////////////////////////////////////////
2362 
////                                                              ////
2363 
////  Versatile counter                                           ////
2364 
////                                                              ////
2365 
////  Description                                                 ////
2366 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2367 
////  counter                                                     ////
2368 
////                                                              ////
2369 
////  To Do:                                                      ////
2370 
////   - add LFSR with more taps                                  ////
2371 
////                                                              ////
2372 
////  Author(s):                                                  ////
2373 
////      - Michael Unneback, unneback@opencores.org              ////
2374 
////        ORSoC AB                                              ////
2375 
////                                                              ////
2376 
//////////////////////////////////////////////////////////////////////
2377 
////                                                              ////
2378 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2379 
////                                                              ////
2380 
//// This source file may be used and distributed without         ////
2381 
//// restriction provided that this copyright statement is not    ////
2382 
//// removed from the file and that any derivative work contains  ////
2383 
//// the original copyright notice and the associated disclaimer. ////
2384 
////                                                              ////
2385 
//// This source file is free software; you can redistribute it   ////
2386 
//// and/or modify it under the terms of the GNU Lesser General   ////
2387 
//// Public License as published by the Free Software Foundation; ////
2388 
//// either version 2.1 of the License, or (at your option) any   ////
2389 
//// later version.                                               ////
2390 
////                                                              ////
2391 
//// This source is distributed in the hope that it will be       ////
2392 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2393 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2394 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2395 
//// details.                                                     ////
2396 
////                                                              ////
2397 
//// You should have received a copy of the GNU Lesser General    ////
2398 
//// Public License along with this source; if not, download it   ////
2399 
//// from http://www.opencores.org/lgpl.shtml                     ////
2400 
////                                                              ////
2401 
//////////////////////////////////////////////////////////////////////
2402 
 
2403 
// LFSR counter
2404 
 
2405 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2406 
module `BASE`MODULE (
2407 
`undef MODULE
2408 
 cke, zq, rst, clk);
2409 
 
2410 6 unneback 
   parameter length = 4;
2411 
   input cke;
2412 
   output reg zq;
2413 
   input rst;
2414 
   input clk;
2415 
 
2416 
   parameter clear_value = 0;
2417 
   parameter set_value = 1;
2418 
   parameter wrap_value = 8;
2419 
   parameter level1_value = 15;
2420 
 
2421 
   reg  [length:1] qi;
2422 
   reg lfsr_fb;
2423 
   wire [length:1] q_next;
2424 
   reg [32:1] polynom;
2425 
   integer i;
2426 
 
2427 
   always @ (qi)
2428 
   begin
2429 
        case (length)
2430 
         2: polynom = 32'b11;                               // 0x3
2431 
         3: polynom = 32'b110;                              // 0x6
2432 
         4: polynom = 32'b1100;                             // 0xC
2433 
         5: polynom = 32'b10100;                            // 0x14
2434 
         6: polynom = 32'b110000;                           // 0x30
2435 
         7: polynom = 32'b1100000;                          // 0x60
2436 
         8: polynom = 32'b10111000;                         // 0xb8
2437 
         9: polynom = 32'b100010000;                        // 0x110
2438 
        10: polynom = 32'b1001000000;                       // 0x240
2439 
        11: polynom = 32'b10100000000;                      // 0x500
2440 
        12: polynom = 32'b100000101001;                     // 0x829
2441 
        13: polynom = 32'b1000000001100;                    // 0x100C
2442 
        14: polynom = 32'b10000000010101;                   // 0x2015
2443 
        15: polynom = 32'b110000000000000;                  // 0x6000
2444 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2445 
        17: polynom = 32'b10010000000000000;                // 0x12000
2446 
        18: polynom = 32'b100000010000000000;               // 0x20400
2447 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2448 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2449 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2450 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2451 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2452 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2453 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2454 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2455 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2456 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2457 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2458 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2459 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2460 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2461 
        default: polynom = 32'b0;
2462 
        endcase
2463 
        lfsr_fb = qi[length];
2464 
        for (i=length-1; i>=1; i=i-1) begin
2465 
            if (polynom[i])
2466 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2467 
        end
2468 
    end
2469 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2470 
 
2471 
   always @ (posedge clk or posedge rst)
2472 
     if (rst)
2473 
       qi <= {length{1'b0}};
2474 
     else
2475 
     if (cke)
2476 
       qi <= q_next;
2477 
 
2478 
 
2479 
 
2480 
   always @ (posedge clk or posedge rst)
2481 
     if (rst)
2482 
       zq <= 1'b1;
2483 
     else
2484 
     if (cke)
2485 
       zq <= q_next == {length{1'b0}};
2486 
endmodule
2487 40 unneback 
`endif
2488 
`ifdef CNT_LFSR_CE_Q
2489 6 unneback 
//////////////////////////////////////////////////////////////////////
2490 
////                                                              ////
2491 
////  Versatile counter                                           ////
2492 
////                                                              ////
2493 
////  Description                                                 ////
2494 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2495 
////  counter                                                     ////
2496 
////                                                              ////
2497 
////  To Do:                                                      ////
2498 
////   - add LFSR with more taps                                  ////
2499 
////                                                              ////
2500 
////  Author(s):                                                  ////
2501 
////      - Michael Unneback, unneback@opencores.org              ////
2502 
////        ORSoC AB                                              ////
2503 
////                                                              ////
2504 
//////////////////////////////////////////////////////////////////////
2505 
////                                                              ////
2506 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2507 
////                                                              ////
2508 
//// This source file may be used and distributed without         ////
2509 
//// restriction provided that this copyright statement is not    ////
2510 
//// removed from the file and that any derivative work contains  ////
2511 
//// the original copyright notice and the associated disclaimer. ////
2512 
////                                                              ////
2513 
//// This source file is free software; you can redistribute it   ////
2514 
//// and/or modify it under the terms of the GNU Lesser General   ////
2515 
//// Public License as published by the Free Software Foundation; ////
2516 
//// either version 2.1 of the License, or (at your option) any   ////
2517 
//// later version.                                               ////
2518 
////                                                              ////
2519 
//// This source is distributed in the hope that it will be       ////
2520 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2521 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2522 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2523 
//// details.                                                     ////
2524 
////                                                              ////
2525 
//// You should have received a copy of the GNU Lesser General    ////
2526 
//// Public License along with this source; if not, download it   ////
2527 
//// from http://www.opencores.org/lgpl.shtml                     ////
2528 
////                                                              ////
2529 
//////////////////////////////////////////////////////////////////////
2530 22 unneback 
 
2531 
// LFSR counter
2532 27 unneback 
 
2533 40 unneback 
`define MODULE cnt_lfsr_ce_q
2534 
module `BASE`MODULE (
2535 
`undef MODULE
2536 
 cke, q, rst, clk);
2537 
 
2538 27 unneback 
   parameter length = 4;
2539 
   input cke;
2540 
   output [length:1] q;
2541 
   input rst;
2542 
   input clk;
2543 
 
2544 
   parameter clear_value = 0;
2545 
   parameter set_value = 1;
2546 
   parameter wrap_value = 8;
2547 
   parameter level1_value = 15;
2548 
 
2549 
   reg  [length:1] qi;
2550 
   reg lfsr_fb;
2551 
   wire [length:1] q_next;
2552 
   reg [32:1] polynom;
2553 
   integer i;
2554 
 
2555 
   always @ (qi)
2556 
   begin
2557 
        case (length)
2558 
         2: polynom = 32'b11;                               // 0x3
2559 
         3: polynom = 32'b110;                              // 0x6
2560 
         4: polynom = 32'b1100;                             // 0xC
2561 
         5: polynom = 32'b10100;                            // 0x14
2562 
         6: polynom = 32'b110000;                           // 0x30
2563 
         7: polynom = 32'b1100000;                          // 0x60
2564 
         8: polynom = 32'b10111000;                         // 0xb8
2565 
         9: polynom = 32'b100010000;                        // 0x110
2566 
        10: polynom = 32'b1001000000;                       // 0x240
2567 
        11: polynom = 32'b10100000000;                      // 0x500
2568 
        12: polynom = 32'b100000101001;                     // 0x829
2569 
        13: polynom = 32'b1000000001100;                    // 0x100C
2570 
        14: polynom = 32'b10000000010101;                   // 0x2015
2571 
        15: polynom = 32'b110000000000000;                  // 0x6000
2572 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2573 
        17: polynom = 32'b10010000000000000;                // 0x12000
2574 
        18: polynom = 32'b100000010000000000;               // 0x20400
2575 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2576 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2577 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2578 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2579 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2580 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2581 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2582 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2583 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2584 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2585 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2586 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2587 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2588 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2589 
        default: polynom = 32'b0;
2590 
        endcase
2591 
        lfsr_fb = qi[length];
2592 
        for (i=length-1; i>=1; i=i-1) begin
2593 
            if (polynom[i])
2594 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2595 
        end
2596 
    end
2597 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2598 
 
2599 
   always @ (posedge clk or posedge rst)
2600 
     if (rst)
2601 
       qi <= {length{1'b0}};
2602 
     else
2603 
     if (cke)
2604 
       qi <= q_next;
2605 
 
2606 
   assign q = qi;
2607 
 
2608 
endmodule
2609 40 unneback 
`endif
2610 
`ifdef CNT_LFSR_CE_CLEAR_Q
2611 27 unneback 
//////////////////////////////////////////////////////////////////////
2612 
////                                                              ////
2613 
////  Versatile counter                                           ////
2614 
////                                                              ////
2615 
////  Description                                                 ////
2616 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2617 
////  counter                                                     ////
2618 
////                                                              ////
2619 
////  To Do:                                                      ////
2620 
////   - add LFSR with more taps                                  ////
2621 
////                                                              ////
2622 
////  Author(s):                                                  ////
2623 
////      - Michael Unneback, unneback@opencores.org              ////
2624 
////        ORSoC AB                                              ////
2625 
////                                                              ////
2626 
//////////////////////////////////////////////////////////////////////
2627 
////                                                              ////
2628 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2629 
////                                                              ////
2630 
//// This source file may be used and distributed without         ////
2631 
//// restriction provided that this copyright statement is not    ////
2632 
//// removed from the file and that any derivative work contains  ////
2633 
//// the original copyright notice and the associated disclaimer. ////
2634 
////                                                              ////
2635 
//// This source file is free software; you can redistribute it   ////
2636 
//// and/or modify it under the terms of the GNU Lesser General   ////
2637 
//// Public License as published by the Free Software Foundation; ////
2638 
//// either version 2.1 of the License, or (at your option) any   ////
2639 
//// later version.                                               ////
2640 
////                                                              ////
2641 
//// This source is distributed in the hope that it will be       ////
2642 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2643 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2644 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2645 
//// details.                                                     ////
2646 
////                                                              ////
2647 
//// You should have received a copy of the GNU Lesser General    ////
2648 
//// Public License along with this source; if not, download it   ////
2649 
//// from http://www.opencores.org/lgpl.shtml                     ////
2650 
////                                                              ////
2651 
//////////////////////////////////////////////////////////////////////
2652 
 
2653 
// LFSR counter
2654 
 
2655 40 unneback 
`define MODULE cnt_lfsr_ce_clear_q
2656 
module `BASE`MODULE (
2657 
`undef MODULE
2658 
 clear, cke, q, rst, clk);
2659 
 
2660 27 unneback 
   parameter length = 4;
2661 
   input clear;
2662 
   input cke;
2663 
   output [length:1] q;
2664 
   input rst;
2665 
   input clk;
2666 
 
2667 
   parameter clear_value = 0;
2668 
   parameter set_value = 1;
2669 
   parameter wrap_value = 8;
2670 
   parameter level1_value = 15;
2671 
 
2672 
   reg  [length:1] qi;
2673 
   reg lfsr_fb;
2674 
   wire [length:1] q_next;
2675 
   reg [32:1] polynom;
2676 
   integer i;
2677 
 
2678 
   always @ (qi)
2679 
   begin
2680 
        case (length)
2681 
         2: polynom = 32'b11;                               // 0x3
2682 
         3: polynom = 32'b110;                              // 0x6
2683 
         4: polynom = 32'b1100;                             // 0xC
2684 
         5: polynom = 32'b10100;                            // 0x14
2685 
         6: polynom = 32'b110000;                           // 0x30
2686 
         7: polynom = 32'b1100000;                          // 0x60
2687 
         8: polynom = 32'b10111000;                         // 0xb8
2688 
         9: polynom = 32'b100010000;                        // 0x110
2689 
        10: polynom = 32'b1001000000;                       // 0x240
2690 
        11: polynom = 32'b10100000000;                      // 0x500
2691 
        12: polynom = 32'b100000101001;                     // 0x829
2692 
        13: polynom = 32'b1000000001100;                    // 0x100C
2693 
        14: polynom = 32'b10000000010101;                   // 0x2015
2694 
        15: polynom = 32'b110000000000000;                  // 0x6000
2695 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2696 
        17: polynom = 32'b10010000000000000;                // 0x12000
2697 
        18: polynom = 32'b100000010000000000;               // 0x20400
2698 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2699 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2700 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2701 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2702 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2703 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2704 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2705 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2706 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2707 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2708 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2709 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2710 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2711 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2712 
        default: polynom = 32'b0;
2713 
        endcase
2714 
        lfsr_fb = qi[length];
2715 
        for (i=length-1; i>=1; i=i-1) begin
2716 
            if (polynom[i])
2717 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2718 
        end
2719 
    end
2720 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2721 
 
2722 
   always @ (posedge clk or posedge rst)
2723 
     if (rst)
2724 
       qi <= {length{1'b0}};
2725 
     else
2726 
     if (cke)
2727 
       qi <= q_next;
2728 
 
2729 
   assign q = qi;
2730 
 
2731 
endmodule
2732 40 unneback 
`endif
2733 
`ifdef CNT_LFSR_CE_Q_ZQ
2734 27 unneback 
//////////////////////////////////////////////////////////////////////
2735 
////                                                              ////
2736 
////  Versatile counter                                           ////
2737 
////                                                              ////
2738 
////  Description                                                 ////
2739 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2740 
////  counter                                                     ////
2741 
////                                                              ////
2742 
////  To Do:                                                      ////
2743 
////   - add LFSR with more taps                                  ////
2744 
////                                                              ////
2745 
////  Author(s):                                                  ////
2746 
////      - Michael Unneback, unneback@opencores.org              ////
2747 
////        ORSoC AB                                              ////
2748 
////                                                              ////
2749 
//////////////////////////////////////////////////////////////////////
2750 
////                                                              ////
2751 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2752 
////                                                              ////
2753 
//// This source file may be used and distributed without         ////
2754 
//// restriction provided that this copyright statement is not    ////
2755 
//// removed from the file and that any derivative work contains  ////
2756 
//// the original copyright notice and the associated disclaimer. ////
2757 
////                                                              ////
2758 
//// This source file is free software; you can redistribute it   ////
2759 
//// and/or modify it under the terms of the GNU Lesser General   ////
2760 
//// Public License as published by the Free Software Foundation; ////
2761 
//// either version 2.1 of the License, or (at your option) any   ////
2762 
//// later version.                                               ////
2763 
////                                                              ////
2764 
//// This source is distributed in the hope that it will be       ////
2765 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2766 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2767 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2768 
//// details.                                                     ////
2769 
////                                                              ////
2770 
//// You should have received a copy of the GNU Lesser General    ////
2771 
//// Public License along with this source; if not, download it   ////
2772 
//// from http://www.opencores.org/lgpl.shtml                     ////
2773 
////                                                              ////
2774 
//////////////////////////////////////////////////////////////////////
2775 
 
2776 
// LFSR counter
2777 22 unneback 
 
2778 40 unneback 
`define MODULE cnt_lfsr_ce_q_zq
2779 
module `BASE`MODULE (
2780 
`undef MODULE
2781 
 cke, q, zq, rst, clk);
2782 
 
2783 22 unneback 
   parameter length = 4;
2784 
   input cke;
2785 
   output [length:1] q;
2786 
   output reg zq;
2787 
   input rst;
2788 
   input clk;
2789 
 
2790 
   parameter clear_value = 0;
2791 
   parameter set_value = 1;
2792 
   parameter wrap_value = 8;
2793 
   parameter level1_value = 15;
2794 
 
2795 
   reg  [length:1] qi;
2796 
   reg lfsr_fb;
2797 
   wire [length:1] q_next;
2798 
   reg [32:1] polynom;
2799 
   integer i;
2800 
 
2801 
   always @ (qi)
2802 
   begin
2803 
        case (length)
2804 
         2: polynom = 32'b11;                               // 0x3
2805 
         3: polynom = 32'b110;                              // 0x6
2806 
         4: polynom = 32'b1100;                             // 0xC
2807 
         5: polynom = 32'b10100;                            // 0x14
2808 
         6: polynom = 32'b110000;                           // 0x30
2809 
         7: polynom = 32'b1100000;                          // 0x60
2810 
         8: polynom = 32'b10111000;                         // 0xb8
2811 
         9: polynom = 32'b100010000;                        // 0x110
2812 
        10: polynom = 32'b1001000000;                       // 0x240
2813 
        11: polynom = 32'b10100000000;                      // 0x500
2814 
        12: polynom = 32'b100000101001;                     // 0x829
2815 
        13: polynom = 32'b1000000001100;                    // 0x100C
2816 
        14: polynom = 32'b10000000010101;                   // 0x2015
2817 
        15: polynom = 32'b110000000000000;                  // 0x6000
2818 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2819 
        17: polynom = 32'b10010000000000000;                // 0x12000
2820 
        18: polynom = 32'b100000010000000000;               // 0x20400
2821 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2822 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2823 22 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2824 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2825 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2826 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2827 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2828 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2829 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2830 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2831 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2832 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2833 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2834 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2835 
        default: polynom = 32'b0;
2836 
        endcase
2837 
        lfsr_fb = qi[length];
2838 
        for (i=length-1; i>=1; i=i-1) begin
2839 
            if (polynom[i])
2840 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2841 
        end
2842 
    end
2843 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2844 
 
2845 
   always @ (posedge clk or posedge rst)
2846 
     if (rst)
2847 
       qi <= {length{1'b0}};
2848 
     else
2849 
     if (cke)
2850 
       qi <= q_next;
2851 
 
2852 
   assign q = qi;
2853 
 
2854 
 
2855 
   always @ (posedge clk or posedge rst)
2856 
     if (rst)
2857 
       zq <= 1'b1;
2858 
     else
2859 
     if (cke)
2860 
       zq <= q_next == {length{1'b0}};
2861 
endmodule
2862 40 unneback 
`endif
2863 
`ifdef CNT_LFSR_CE_REW_L1
2864 22 unneback 
//////////////////////////////////////////////////////////////////////
2865 
////                                                              ////
2866 
////  Versatile counter                                           ////
2867 
////                                                              ////
2868 
////  Description                                                 ////
2869 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2870 
////  counter                                                     ////
2871 
////                                                              ////
2872 
////  To Do:                                                      ////
2873 
////   - add LFSR with more taps                                  ////
2874 
////                                                              ////
2875 
////  Author(s):                                                  ////
2876 
////      - Michael Unneback, unneback@opencores.org              ////
2877 
////        ORSoC AB                                              ////
2878 
////                                                              ////
2879 
//////////////////////////////////////////////////////////////////////
2880 
////                                                              ////
2881 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2882 
////                                                              ////
2883 
//// This source file may be used and distributed without         ////
2884 
//// restriction provided that this copyright statement is not    ////
2885 
//// removed from the file and that any derivative work contains  ////
2886 
//// the original copyright notice and the associated disclaimer. ////
2887 
////                                                              ////
2888 
//// This source file is free software; you can redistribute it   ////
2889 
//// and/or modify it under the terms of the GNU Lesser General   ////
2890 
//// Public License as published by the Free Software Foundation; ////
2891 
//// either version 2.1 of the License, or (at your option) any   ////
2892 
//// later version.                                               ////
2893 
////                                                              ////
2894 
//// This source is distributed in the hope that it will be       ////
2895 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2896 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2897 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2898 
//// details.                                                     ////
2899 
////                                                              ////
2900 
//// You should have received a copy of the GNU Lesser General    ////
2901 
//// Public License along with this source; if not, download it   ////
2902 
//// from http://www.opencores.org/lgpl.shtml                     ////
2903 
////                                                              ////
2904 
//////////////////////////////////////////////////////////////////////
2905 6 unneback 
 
2906 
// LFSR counter
2907 
 
2908 40 unneback 
`define MODULE cnt_lfsr_ce_rew_l1
2909 
module `BASE`MODULE (
2910 
`undef MODULE
2911 
 cke, rew, level1, rst, clk);
2912 
 
2913 6 unneback 
   parameter length = 4;
2914 
   input cke;
2915 
   input rew;
2916 
   output reg level1;
2917 
   input rst;
2918 
   input clk;
2919 
 
2920 
   parameter clear_value = 0;
2921 
   parameter set_value = 1;
2922 
   parameter wrap_value = 8;
2923 
   parameter level1_value = 15;
2924 
 
2925 29 unneback 
   wire clear;
2926 30 unneback 
   assign clear = 1'b0;
2927 6 unneback 
   reg  [length:1] qi;
2928 
   reg lfsr_fb, lfsr_fb_rew;
2929 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2930 
   reg [32:1] polynom_rew;
2931 
   integer j;
2932 
   reg [32:1] polynom;
2933 
   integer i;
2934 
 
2935 
   always @ (qi)
2936 
   begin
2937 
        case (length)
2938 
         2: polynom = 32'b11;                               // 0x3
2939 
         3: polynom = 32'b110;                              // 0x6
2940 
         4: polynom = 32'b1100;                             // 0xC
2941 
         5: polynom = 32'b10100;                            // 0x14
2942 
         6: polynom = 32'b110000;                           // 0x30
2943 
         7: polynom = 32'b1100000;                          // 0x60
2944 
         8: polynom = 32'b10111000;                         // 0xb8
2945 
         9: polynom = 32'b100010000;                        // 0x110
2946 
        10: polynom = 32'b1001000000;                       // 0x240
2947 
        11: polynom = 32'b10100000000;                      // 0x500
2948 
        12: polynom = 32'b100000101001;                     // 0x829
2949 
        13: polynom = 32'b1000000001100;                    // 0x100C
2950 
        14: polynom = 32'b10000000010101;                   // 0x2015
2951 
        15: polynom = 32'b110000000000000;                  // 0x6000
2952 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2953 
        17: polynom = 32'b10010000000000000;                // 0x12000
2954 
        18: polynom = 32'b100000010000000000;               // 0x20400
2955 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2956 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2957 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2958 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2959 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2960 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2961 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2962 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2963 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2964 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2965 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2966 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2967 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2968 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2969 
        default: polynom = 32'b0;
2970 
        endcase
2971 
        lfsr_fb = qi[length];
2972 
        for (i=length-1; i>=1; i=i-1) begin
2973 
            if (polynom[i])
2974 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2975 
        end
2976 
    end
2977 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2978 
   always @ (qi)
2979 
   begin
2980 
        case (length)
2981 
         2: polynom_rew = 32'b11;
2982 
         3: polynom_rew = 32'b110;
2983 
         4: polynom_rew = 32'b1100;
2984 
         5: polynom_rew = 32'b10100;
2985 
         6: polynom_rew = 32'b110000;
2986 
         7: polynom_rew = 32'b1100000;
2987 
         8: polynom_rew = 32'b10111000;
2988 
         9: polynom_rew = 32'b100010000;
2989 
        10: polynom_rew = 32'b1001000000;
2990 
        11: polynom_rew = 32'b10100000000;
2991 
        12: polynom_rew = 32'b100000101001;
2992 
        13: polynom_rew = 32'b1000000001100;
2993 
        14: polynom_rew = 32'b10000000010101;
2994 
        15: polynom_rew = 32'b110000000000000;
2995 
        16: polynom_rew = 32'b1101000000001000;
2996 
        17: polynom_rew = 32'b10010000000000000;
2997 
        18: polynom_rew = 32'b100000010000000000;
2998 
        19: polynom_rew = 32'b1000000000000100011;
2999 
        20: polynom_rew = 32'b10000010000000000000;
3000 
        21: polynom_rew = 32'b101000000000000000000;
3001 
        22: polynom_rew = 32'b1100000000000000000000;
3002 
        23: polynom_rew = 32'b10000100000000000000000;
3003 
        24: polynom_rew = 32'b111000010000000000000000;
3004 
        25: polynom_rew = 32'b1001000000000000000000000;
3005 
        26: polynom_rew = 32'b10000000000000000000100011;
3006 
        27: polynom_rew = 32'b100000000000000000000010011;
3007 
        28: polynom_rew = 32'b1100100000000000000000000000;
3008 
        29: polynom_rew = 32'b10100000000000000000000000000;
3009 
        30: polynom_rew = 32'b100000000000000000000000101001;
3010 
        31: polynom_rew = 32'b1001000000000000000000000000000;
3011 
        32: polynom_rew = 32'b10000000001000000000000000000011;
3012 
        default: polynom_rew = 32'b0;
3013 
        endcase
3014 
        // rotate left
3015 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3016 
        lfsr_fb_rew = qi[length];
3017 
        for (i=length-1; i>=1; i=i-1) begin
3018 
            if (polynom_rew[i])
3019 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3020 
        end
3021 
    end
3022 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3023 
   assign q_next = rew ? q_next_rew : q_next_fw;
3024 
 
3025 
   always @ (posedge clk or posedge rst)
3026 
     if (rst)
3027 
       qi <= {length{1'b0}};
3028 
     else
3029 
     if (cke)
3030 
       qi <= q_next;
3031 
 
3032 
 
3033 
 
3034 
    always @ (posedge clk or posedge rst)
3035 
    if (rst)
3036 
        level1 <= 1'b0;
3037 
    else
3038 
    if (cke)
3039 29 unneback 
    if (clear)
3040 
        level1 <= 1'b0;
3041 
    else if (q_next == level1_value)
3042 6 unneback 
        level1 <= 1'b1;
3043 
    else if (qi == level1_value & rew)
3044 
        level1 <= 1'b0;
3045 
endmodule
3046 40 unneback 
`endif
3047 
`ifdef CNT_GRAY
3048 6 unneback 
//////////////////////////////////////////////////////////////////////
3049 
////                                                              ////
3050 
////  Versatile counter                                           ////
3051 
////                                                              ////
3052 
////  Description                                                 ////
3053 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3054 
////  counter                                                     ////
3055 
////                                                              ////
3056 
////  To Do:                                                      ////
3057 
////   - add LFSR with more taps                                  ////
3058 
////                                                              ////
3059 
////  Author(s):                                                  ////
3060 
////      - Michael Unneback, unneback@opencores.org              ////
3061 
////        ORSoC AB                                              ////
3062 
////                                                              ////
3063 
//////////////////////////////////////////////////////////////////////
3064 
////                                                              ////
3065 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3066 
////                                                              ////
3067 
//// This source file may be used and distributed without         ////
3068 
//// restriction provided that this copyright statement is not    ////
3069 
//// removed from the file and that any derivative work contains  ////
3070 
//// the original copyright notice and the associated disclaimer. ////
3071 
////                                                              ////
3072 
//// This source file is free software; you can redistribute it   ////
3073 
//// and/or modify it under the terms of the GNU Lesser General   ////
3074 
//// Public License as published by the Free Software Foundation; ////
3075 
//// either version 2.1 of the License, or (at your option) any   ////
3076 
//// later version.                                               ////
3077 
////                                                              ////
3078 
//// This source is distributed in the hope that it will be       ////
3079 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3080 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3081 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3082 
//// details.                                                     ////
3083 
////                                                              ////
3084 
//// You should have received a copy of the GNU Lesser General    ////
3085 
//// Public License along with this source; if not, download it   ////
3086 
//// from http://www.opencores.org/lgpl.shtml                     ////
3087 
////                                                              ////
3088 
//////////////////////////////////////////////////////////////////////
3089 
 
3090 
// GRAY counter
3091 
 
3092 40 unneback 
`define MODULE cnt_gray
3093 
module `BASE`MODULE (
3094 
`undef MODULE
3095 
 q, rst, clk);
3096 
 
3097 6 unneback 
   parameter length = 4;
3098 
   output reg [length:1] q;
3099 
   input rst;
3100 
   input clk;
3101 
 
3102 
   parameter clear_value = 0;
3103 
   parameter set_value = 1;
3104 
   parameter wrap_value = 8;
3105 
   parameter level1_value = 15;
3106 
 
3107 
   reg  [length:1] qi;
3108 
   wire [length:1] q_next;
3109 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3110 
 
3111 
   always @ (posedge clk or posedge rst)
3112 
     if (rst)
3113 
       qi <= {length{1'b0}};
3114 
     else
3115 
       qi <= q_next;
3116 
 
3117 
   always @ (posedge clk or posedge rst)
3118 
     if (rst)
3119 
       q <= {length{1'b0}};
3120 
     else
3121 
         q <= (q_next>>1) ^ q_next;
3122 
 
3123 
endmodule
3124 40 unneback 
`endif
3125 
`ifdef CNT_GRAY_CE
3126 6 unneback 
//////////////////////////////////////////////////////////////////////
3127 
////                                                              ////
3128 
////  Versatile counter                                           ////
3129 
////                                                              ////
3130 
////  Description                                                 ////
3131 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3132 
////  counter                                                     ////
3133 
////                                                              ////
3134 
////  To Do:                                                      ////
3135 
////   - add LFSR with more taps                                  ////
3136 
////                                                              ////
3137 
////  Author(s):                                                  ////
3138 
////      - Michael Unneback, unneback@opencores.org              ////
3139 
////        ORSoC AB                                              ////
3140 
////                                                              ////
3141 
//////////////////////////////////////////////////////////////////////
3142 
////                                                              ////
3143 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3144 
////                                                              ////
3145 
//// This source file may be used and distributed without         ////
3146 
//// restriction provided that this copyright statement is not    ////
3147 
//// removed from the file and that any derivative work contains  ////
3148 
//// the original copyright notice and the associated disclaimer. ////
3149 
////                                                              ////
3150 
//// This source file is free software; you can redistribute it   ////
3151 
//// and/or modify it under the terms of the GNU Lesser General   ////
3152 
//// Public License as published by the Free Software Foundation; ////
3153 
//// either version 2.1 of the License, or (at your option) any   ////
3154 
//// later version.                                               ////
3155 
////                                                              ////
3156 
//// This source is distributed in the hope that it will be       ////
3157 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3158 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3159 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3160 
//// details.                                                     ////
3161 
////                                                              ////
3162 
//// You should have received a copy of the GNU Lesser General    ////
3163 
//// Public License along with this source; if not, download it   ////
3164 
//// from http://www.opencores.org/lgpl.shtml                     ////
3165 
////                                                              ////
3166 
//////////////////////////////////////////////////////////////////////
3167 
 
3168 
// GRAY counter
3169 
 
3170 40 unneback 
`define MODULE cnt_gray_ce
3171 
module `BASE`MODULE (
3172 
`undef MODULE
3173 
 cke, q, rst, clk);
3174 
 
3175 6 unneback 
   parameter length = 4;
3176 
   input cke;
3177 
   output reg [length:1] q;
3178 
   input rst;
3179 
   input clk;
3180 
 
3181 
   parameter clear_value = 0;
3182 
   parameter set_value = 1;
3183 
   parameter wrap_value = 8;
3184 
   parameter level1_value = 15;
3185 
 
3186 
   reg  [length:1] qi;
3187 
   wire [length:1] q_next;
3188 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3189 
 
3190 
   always @ (posedge clk or posedge rst)
3191 
     if (rst)
3192 
       qi <= {length{1'b0}};
3193 
     else
3194 
     if (cke)
3195 
       qi <= q_next;
3196 
 
3197 
   always @ (posedge clk or posedge rst)
3198 
     if (rst)
3199 
       q <= {length{1'b0}};
3200 
     else
3201 
       if (cke)
3202 
         q <= (q_next>>1) ^ q_next;
3203 
 
3204 
endmodule
3205 40 unneback 
`endif
3206 
`ifdef CNT_GRAY_CE_BIN
3207 6 unneback 
//////////////////////////////////////////////////////////////////////
3208 
////                                                              ////
3209 
////  Versatile counter                                           ////
3210 
////                                                              ////
3211 
////  Description                                                 ////
3212 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3213 
////  counter                                                     ////
3214 
////                                                              ////
3215 
////  To Do:                                                      ////
3216 
////   - add LFSR with more taps                                  ////
3217 
////                                                              ////
3218 
////  Author(s):                                                  ////
3219 
////      - Michael Unneback, unneback@opencores.org              ////
3220 
////        ORSoC AB                                              ////
3221 
////                                                              ////
3222 
//////////////////////////////////////////////////////////////////////
3223 
////                                                              ////
3224 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3225 
////                                                              ////
3226 
//// This source file may be used and distributed without         ////
3227 
//// restriction provided that this copyright statement is not    ////
3228 
//// removed from the file and that any derivative work contains  ////
3229 
//// the original copyright notice and the associated disclaimer. ////
3230 
////                                                              ////
3231 
//// This source file is free software; you can redistribute it   ////
3232 
//// and/or modify it under the terms of the GNU Lesser General   ////
3233 
//// Public License as published by the Free Software Foundation; ////
3234 
//// either version 2.1 of the License, or (at your option) any   ////
3235 
//// later version.                                               ////
3236 
////                                                              ////
3237 
//// This source is distributed in the hope that it will be       ////
3238 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3239 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3240 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3241 
//// details.                                                     ////
3242 
////                                                              ////
3243 
//// You should have received a copy of the GNU Lesser General    ////
3244 
//// Public License along with this source; if not, download it   ////
3245 
//// from http://www.opencores.org/lgpl.shtml                     ////
3246 
////                                                              ////
3247 
//////////////////////////////////////////////////////////////////////
3248 
 
3249 
// GRAY counter
3250 
 
3251 40 unneback 
`define MODULE cnt_gray_ce_bin
3252 
module `BASE`MODULE (
3253 
`undef MODULE
3254 
 cke, q, q_bin, rst, clk);
3255 
 
3256 6 unneback 
   parameter length = 4;
3257 
   input cke;
3258 
   output reg [length:1] q;
3259 
   output [length:1] q_bin;
3260 
   input rst;
3261 
   input clk;
3262 
 
3263 
   parameter clear_value = 0;
3264 
   parameter set_value = 1;
3265 
   parameter wrap_value = 8;
3266 
   parameter level1_value = 15;
3267 
 
3268 
   reg  [length:1] qi;
3269 
   wire [length:1] q_next;
3270 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3271 
 
3272 
   always @ (posedge clk or posedge rst)
3273 
     if (rst)
3274 
       qi <= {length{1'b0}};
3275 
     else
3276 
     if (cke)
3277 
       qi <= q_next;
3278 
 
3279 
   always @ (posedge clk or posedge rst)
3280 
     if (rst)
3281 
       q <= {length{1'b0}};
3282 
     else
3283 
       if (cke)
3284 
         q <= (q_next>>1) ^ q_next;
3285 
 
3286 
   assign q_bin = qi;
3287 
 
3288 
endmodule
3289 40 unneback 
`endif
3290 6 unneback 
//////////////////////////////////////////////////////////////////////
3291 
////                                                              ////
3292 
////  Versatile library, counters                                 ////
3293 
////                                                              ////
3294 
////  Description                                                 ////
3295 
////  counters                                                    ////
3296 
////                                                              ////
3297 
////                                                              ////
3298 
////  To Do:                                                      ////
3299 
////   - add more counters                                        ////
3300 
////                                                              ////
3301 
////  Author(s):                                                  ////
3302 
////      - Michael Unneback, unneback@opencores.org              ////
3303 
////        ORSoC AB                                              ////
3304 
////                                                              ////
3305 
//////////////////////////////////////////////////////////////////////
3306 
////                                                              ////
3307 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3308 
////                                                              ////
3309 
//// This source file may be used and distributed without         ////
3310 
//// restriction provided that this copyright statement is not    ////
3311 
//// removed from the file and that any derivative work contains  ////
3312 
//// the original copyright notice and the associated disclaimer. ////
3313 
////                                                              ////
3314 
//// This source file is free software; you can redistribute it   ////
3315 
//// and/or modify it under the terms of the GNU Lesser General   ////
3316 
//// Public License as published by the Free Software Foundation; ////
3317 
//// either version 2.1 of the License, or (at your option) any   ////
3318 
//// later version.                                               ////
3319 
////                                                              ////
3320 
//// This source is distributed in the hope that it will be       ////
3321 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3322 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3323 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3324 
//// details.                                                     ////
3325 
////                                                              ////
3326 
//// You should have received a copy of the GNU Lesser General    ////
3327 
//// Public License along with this source; if not, download it   ////
3328 
//// from http://www.opencores.org/lgpl.shtml                     ////
3329 
////                                                              ////
3330 
//////////////////////////////////////////////////////////////////////
3331 
 
3332 40 unneback 
`ifdef CNT_SHREG_WRAP
3333 
`define MODULE cnt_shreg_wrap
3334 
module `BASE`MODULE ( q, rst, clk);
3335 
`undef MODULE
3336 6 unneback 
 
3337 
   parameter length = 4;
3338 
   output reg [0:length-1] q;
3339 
   input rst;
3340 
   input clk;
3341 
 
3342 
    always @ (posedge clk or posedge rst)
3343 
    if (rst)
3344 
        q <= {1'b1,{length-1{1'b0}}};
3345 
    else
3346 
        q <= {q[length-1],q[0:length-2]};
3347 
 
3348 
endmodule
3349 40 unneback 
`endif
3350 6 unneback 
 
3351 40 unneback 
`ifdef CNT_SHREG_CE_WRAP
3352 
`define MODULE cnt_shreg_ce_wrap
3353 
module `BASE`MODULE ( cke, q, rst, clk);
3354 
`undef MODULE
3355 6 unneback 
 
3356 
   parameter length = 4;
3357 
   input cke;
3358 
   output reg [0:length-1] q;
3359 
   input rst;
3360 
   input clk;
3361 
 
3362 
    always @ (posedge clk or posedge rst)
3363 
    if (rst)
3364 
        q <= {1'b1,{length-1{1'b0}}};
3365 
    else
3366 
        if (cke)
3367 
            q <= {q[length-1],q[0:length-2]};
3368 
 
3369 
endmodule
3370 40 unneback 
`endif
3371 6 unneback 
 
3372 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR
3373 
`define MODULE cnt_shreg_ce_clear
3374 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3375 
`undef MODULE
3376 6 unneback 
 
3377 
   parameter length = 4;
3378 
   input cke, clear;
3379 
   output reg [0:length-1] q;
3380 
   input rst;
3381 
   input clk;
3382 
 
3383 
    always @ (posedge clk or posedge rst)
3384 
    if (rst)
3385 
        q <= {1'b1,{length-1{1'b0}}};
3386 
    else
3387 
        if (cke)
3388 
            if (clear)
3389 
                q <= {1'b1,{length-1{1'b0}}};
3390 
            else
3391 
                q <= q >> 1;
3392 
 
3393 
endmodule
3394 40 unneback 
`endif
3395 6 unneback 
 
3396 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3397 
`define MODULE cnt_shreg_ce_clear_wrap
3398 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3399 
`undef MODULE
3400 6 unneback 
 
3401 
   parameter length = 4;
3402 
   input cke, clear;
3403 
   output reg [0:length-1] q;
3404 
   input rst;
3405 
   input clk;
3406 
 
3407 
    always @ (posedge clk or posedge rst)
3408 
    if (rst)
3409 
        q <= {1'b1,{length-1{1'b0}}};
3410 
    else
3411 
        if (cke)
3412 
            if (clear)
3413 
                q <= {1'b1,{length-1{1'b0}}};
3414 
            else
3415 
            q <= {q[length-1],q[0:length-2]};
3416 
 
3417 
endmodule
3418 40 unneback 
`endif
3419 6 unneback 
//////////////////////////////////////////////////////////////////////
3420 
////                                                              ////
3421 
////  Versatile library, memories                                 ////
3422 
////                                                              ////
3423 
////  Description                                                 ////
3424 
////  memories                                                    ////
3425 
////                                                              ////
3426 
////                                                              ////
3427 
////  To Do:                                                      ////
3428 
////   - add more memory types                                    ////
3429 
////                                                              ////
3430 
////  Author(s):                                                  ////
3431 
////      - Michael Unneback, unneback@opencores.org              ////
3432 
////        ORSoC AB                                              ////
3433 
////                                                              ////
3434 
//////////////////////////////////////////////////////////////////////
3435 
////                                                              ////
3436 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3437 
////                                                              ////
3438 
//// This source file may be used and distributed without         ////
3439 
//// restriction provided that this copyright statement is not    ////
3440 
//// removed from the file and that any derivative work contains  ////
3441 
//// the original copyright notice and the associated disclaimer. ////
3442 
////                                                              ////
3443 
//// This source file is free software; you can redistribute it   ////
3444 
//// and/or modify it under the terms of the GNU Lesser General   ////
3445 
//// Public License as published by the Free Software Foundation; ////
3446 
//// either version 2.1 of the License, or (at your option) any   ////
3447 
//// later version.                                               ////
3448 
////                                                              ////
3449 
//// This source is distributed in the hope that it will be       ////
3450 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3451 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3452 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3453 
//// details.                                                     ////
3454 
////                                                              ////
3455 
//// You should have received a copy of the GNU Lesser General    ////
3456 
//// Public License along with this source; if not, download it   ////
3457 
//// from http://www.opencores.org/lgpl.shtml                     ////
3458 
////                                                              ////
3459 
//////////////////////////////////////////////////////////////////////
3460 
 
3461 40 unneback 
`ifdef ROM_INIT
3462 6 unneback 
/// ROM
3463 40 unneback 
`define MODULE rom_init
3464 
module `BASE`MODULE ( adr, q, clk);
3465 
`undef MODULE
3466 6 unneback 
 
3467 7 unneback 
   parameter data_width = 32;
3468 
   parameter addr_width = 8;
3469 
   input [(addr_width-1):0]       adr;
3470 
   output reg [(data_width-1):0] q;
3471 
   input                         clk;
3472 
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
3473 
   parameter memory_file = "vl_rom.vmem";
3474 
   initial
3475 
     begin
3476 
        $readmemh(memory_file, rom);
3477 
     end
3478 
 
3479 
   always @ (posedge clk)
3480 
     q <= rom[adr];
3481 6 unneback 
 
3482 7 unneback 
endmodule
3483 40 unneback 
`endif
3484 7 unneback 
 
3485 40 unneback 
`ifdef RAM
3486 
`define MODULE ram
3487 6 unneback 
// Single port RAM
3488 40 unneback 
module `BASE`MODULE ( d, adr, we, q, clk);
3489 
`undef MODULE
3490 6 unneback 
 
3491 
   parameter data_width = 32;
3492 
   parameter addr_width = 8;
3493 
   input [(data_width-1):0]      d;
3494 
   input [(addr_width-1):0]       adr;
3495 
   input                         we;
3496 7 unneback 
   output reg [(data_width-1):0] q;
3497 6 unneback 
   input                         clk;
3498 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3499 7 unneback 
   parameter init = 0;
3500 
   parameter memory_file = "vl_ram.vmem";
3501 
   generate if (init) begin : init_mem
3502 
   initial
3503 
     begin
3504 
        $readmemh(memory_file, ram);
3505 
     end
3506 
   end
3507 
   endgenerate
3508 
 
3509 6 unneback 
   always @ (posedge clk)
3510 
   begin
3511 
   if (we)
3512 
     ram[adr] <= d;
3513 
   q <= ram[adr];
3514 
   end
3515 
 
3516 
endmodule
3517 40 unneback 
`endif
3518 6 unneback 
 
3519 40 unneback 
`ifdef RAM_BE
3520 
`define MODULE ram_be
3521 
module `BASE`MODULE ( d, adr, be, we, q, clk);
3522 
`undef MODULE
3523 
 
3524 7 unneback 
   parameter data_width = 32;
3525 
   parameter addr_width = 8;
3526 
   input [(data_width-1):0]      d;
3527 
   input [(addr_width-1):0]       adr;
3528 
   input [(addr_width/4)-1:0]    be;
3529 
   input                         we;
3530 
   output reg [(data_width-1):0] q;
3531 
   input                         clk;
3532 
 
3533 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3534 
 
3535 60 unneback 
   parameter memory_init = 0;
3536 7 unneback 
   parameter memory_file = "vl_ram.vmem";
3537 60 unneback 
   generate if (memory_init) begin : init_mem
3538 7 unneback 
   initial
3539 
     begin
3540 
        $readmemh(memory_file, ram);
3541 
     end
3542 
   end
3543 
   endgenerate
3544 
 
3545 60 unneback 
`ifdef SYSTEMVERILOG
3546 
// use a multi-dimensional packed array
3547 
//to model individual bytes within the word
3548 
 
3549 
logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width
3550 
always_ff@(posedge clk)
3551 
begin
3552 
    if(we) begin // note: we should have a for statement to support any bus width
3553 
        if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24];
3554 
        if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16];
3555 
        if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8];
3556 
        if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0];
3557 
    end
3558 
    q <= ram[raddr];
3559 
end
3560 
 
3561 
`else
3562 
 
3563 7 unneback 
   genvar i;
3564 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
3565 
      always @ (posedge clk)
3566 
      if (we & be[i])
3567 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3568 
   end
3569 
   endgenerate
3570 
 
3571 
   always @ (posedge clk)
3572 
      q <= ram[adr];
3573 
 
3574 60 unneback 
`endif
3575 
 
3576 7 unneback 
endmodule
3577 40 unneback 
`endif
3578 7 unneback 
 
3579 6 unneback 
`ifdef ACTEL
3580 48 unneback 
        // ACTEL FPGA should not use logic to handle rw collision
3581 6 unneback 
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
3582 
`else
3583 
        `define SYN
3584 
`endif
3585 
 
3586 40 unneback 
`ifdef DPRAM_1R1W
3587 
`define MODULE dpram_1r1w
3588 
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3589 
`undef MODULE
3590 6 unneback 
   parameter data_width = 32;
3591 
   parameter addr_width = 8;
3592 
   input [(data_width-1):0]      d_a;
3593 
   input [(addr_width-1):0]       adr_a;
3594 
   input [(addr_width-1):0]       adr_b;
3595 
   input                         we_a;
3596 
   output [(data_width-1):0]      q_b;
3597 
   input                         clk_a, clk_b;
3598 
   reg [(addr_width-1):0]         adr_b_reg;
3599 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3600 7 unneback 
 
3601 
   parameter init = 0;
3602 
   parameter memory_file = "vl_ram.vmem";
3603 
   generate if (init) begin : init_mem
3604 
   initial
3605 
     begin
3606 
        $readmemh(memory_file, ram);
3607 
     end
3608 
   end
3609 
   endgenerate
3610 
 
3611 6 unneback 
   always @ (posedge clk_a)
3612 
   if (we_a)
3613 
     ram[adr_a] <= d_a;
3614 
   always @ (posedge clk_b)
3615 
   adr_b_reg <= adr_b;
3616 
   assign q_b = ram[adr_b_reg];
3617 40 unneback 
 
3618 6 unneback 
endmodule
3619 40 unneback 
`endif
3620 6 unneback 
 
3621 40 unneback 
`ifdef DPRAM_2R1W
3622 
`define MODULE dpram_2r1w
3623 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3624 
`undef MODULE
3625 
 
3626 6 unneback 
   parameter data_width = 32;
3627 
   parameter addr_width = 8;
3628 
   input [(data_width-1):0]      d_a;
3629 
   input [(addr_width-1):0]       adr_a;
3630 
   input [(addr_width-1):0]       adr_b;
3631 
   input                         we_a;
3632 
   output [(data_width-1):0]      q_b;
3633 
   output reg [(data_width-1):0] q_a;
3634 
   input                         clk_a, clk_b;
3635 
   reg [(data_width-1):0]         q_b;
3636 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3637 7 unneback 
 
3638 
   parameter init = 0;
3639 
   parameter memory_file = "vl_ram.vmem";
3640 
   generate if (init) begin : init_mem
3641 
   initial
3642 
     begin
3643 
        $readmemh(memory_file, ram);
3644 
     end
3645 
   end
3646 
   endgenerate
3647 
 
3648 6 unneback 
   always @ (posedge clk_a)
3649 
     begin
3650 
        q_a <= ram[adr_a];
3651 
        if (we_a)
3652 
             ram[adr_a] <= d_a;
3653 
     end
3654 
   always @ (posedge clk_b)
3655 
          q_b <= ram[adr_b];
3656 
endmodule
3657 40 unneback 
`endif
3658 6 unneback 
 
3659 40 unneback 
`ifdef DPRAM_2R2W
3660 
`define MODULE dpram_2r2w
3661 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3662 
`undef MODULE
3663 
 
3664 6 unneback 
   parameter data_width = 32;
3665 
   parameter addr_width = 8;
3666 
   input [(data_width-1):0]      d_a;
3667 
   input [(addr_width-1):0]       adr_a;
3668 
   input [(addr_width-1):0]       adr_b;
3669 
   input                         we_a;
3670 
   output [(data_width-1):0]      q_b;
3671 
   input [(data_width-1):0]       d_b;
3672 
   output reg [(data_width-1):0] q_a;
3673 
   input                         we_b;
3674 
   input                         clk_a, clk_b;
3675 
   reg [(data_width-1):0]         q_b;
3676 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3677 7 unneback 
 
3678 
   parameter init = 0;
3679 
   parameter memory_file = "vl_ram.vmem";
3680 
   generate if (init) begin : init_mem
3681 
   initial
3682 
     begin
3683 
        $readmemh(memory_file, ram);
3684 
     end
3685 
   end
3686 
   endgenerate
3687 
 
3688 6 unneback 
   always @ (posedge clk_a)
3689 
     begin
3690 
        q_a <= ram[adr_a];
3691 
        if (we_a)
3692 
             ram[adr_a] <= d_a;
3693 
     end
3694 
   always @ (posedge clk_b)
3695 
     begin
3696 
        q_b <= ram[adr_b];
3697 
        if (we_b)
3698 
          ram[adr_b] <= d_b;
3699 
     end
3700 
endmodule
3701 40 unneback 
`endif
3702 6 unneback 
 
3703 
// Content addresable memory, CAM
3704 
 
3705 40 unneback 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
3706 6 unneback 
// FIFO
3707 40 unneback 
`define MODULE fifo_1r1w_fill_level_sync
3708 
module `BASE`MODULE (
3709 
`undef MODULE
3710 25 unneback 
    d, wr, fifo_full,
3711 
    q, rd, fifo_empty,
3712 
    fill_level,
3713 
    clk, rst
3714 
    );
3715 
 
3716 
parameter data_width = 18;
3717 
parameter addr_width = 4;
3718 6 unneback 
 
3719 25 unneback 
// write side
3720 
input  [data_width-1:0] d;
3721 
input                   wr;
3722 
output                  fifo_full;
3723 
// read side
3724 
output [data_width-1:0] q;
3725 
input                   rd;
3726 
output                  fifo_empty;
3727 
// common
3728 
output [addr_width:0]   fill_level;
3729 
input rst, clk;
3730 
 
3731 
wire [addr_width:1] wadr, radr;
3732 
 
3733 40 unneback 
`define MODULE cnt_bin_ce
3734 
`BASE`MODULE
3735 25 unneback 
    # ( .length(addr_width))
3736 
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
3737 40 unneback 
`BASE`MODULE
3738 25 unneback 
    # (.length(addr_width))
3739 
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
3740 40 unneback 
`undef MODULE
3741 25 unneback 
 
3742 40 unneback 
`define MODULE dpram_1r1w
3743 
`BASE`MODULE
3744 25 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
3745 
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
3746 40 unneback 
`undef MODULE
3747 25 unneback 
 
3748 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
3749 
`BASE`MODULE
3750 27 unneback 
    # (.length(addr_width+1), .level1_value(1<<addr_width))
3751 25 unneback 
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
3752 40 unneback 
`undef MODULE
3753 25 unneback 
endmodule
3754 40 unneback 
`endif
3755 25 unneback 
 
3756 40 unneback 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
3757 27 unneback 
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
3758 
// RAM is supposed to be larger than the two FIFOs
3759 
// LFSR counters used adr pointers
3760 40 unneback 
`define MODULE fifo_2r2w_sync_simplex
3761 
module `BASE`MODULE (
3762 
`undef MODULE
3763 27 unneback 
    // a side
3764 
    a_d, a_wr, a_fifo_full,
3765 
    a_q, a_rd, a_fifo_empty,
3766 
    a_fill_level,
3767 
    // b side
3768 
    b_d, b_wr, b_fifo_full,
3769 
    b_q, b_rd, b_fifo_empty,
3770 
    b_fill_level,
3771 
    // common
3772 
    clk, rst
3773 
    );
3774 
parameter data_width = 8;
3775 
parameter addr_width = 5;
3776 
parameter fifo_full_level = (1<<addr_width)-1;
3777 
 
3778 
// a side
3779 
input  [data_width-1:0] a_d;
3780 
input                   a_wr;
3781 
output                  a_fifo_full;
3782 
output [data_width-1:0] a_q;
3783 
input                   a_rd;
3784 
output                  a_fifo_empty;
3785 
output [addr_width-1:0] a_fill_level;
3786 
 
3787 
// b side
3788 
input  [data_width-1:0] b_d;
3789 
input                   b_wr;
3790 
output                  b_fifo_full;
3791 
output [data_width-1:0] b_q;
3792 
input                   b_rd;
3793 
output                  b_fifo_empty;
3794 
output [addr_width-1:0] b_fill_level;
3795 
 
3796 
input                   clk;
3797 
input                   rst;
3798 
 
3799 
// adr_gen
3800 
wire [addr_width:1] a_wadr, a_radr;
3801 
wire [addr_width:1] b_wadr, b_radr;
3802 
// dpram
3803 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3804 
 
3805 40 unneback 
`define MODULE cnt_lfsr_ce
3806 
`BASE`MODULE
3807 27 unneback 
    # ( .length(addr_width))
3808 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
3809 
 
3810 40 unneback 
`BASE`MODULE
3811 27 unneback 
    # (.length(addr_width))
3812 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
3813 
 
3814 40 unneback 
`BASE`MODULE
3815 27 unneback 
    # ( .length(addr_width))
3816 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
3817 
 
3818 40 unneback 
`BASE`MODULE
3819 27 unneback 
    # (.length(addr_width))
3820 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
3821 40 unneback 
`undef MODULE
3822 27 unneback 
 
3823 
// mux read or write adr to DPRAM
3824 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
3825 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
3826 
 
3827 40 unneback 
`define MODULE dpram_2r2w
3828 
`BASE`MODULE
3829 27 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
3830 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3831 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3832 40 unneback 
`undef MODULE
3833 
 
3834 
`define MODULE cnt_bin_ce_rew_zq_l1
3835 
`BASE`MODULE
3836 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
3837 27 unneback 
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
3838 
 
3839 40 unneback 
`BASE`MODULE
3840 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
3841 27 unneback 
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
3842 40 unneback 
`undef MODULE
3843 27 unneback 
 
3844 
endmodule
3845 40 unneback 
`endif
3846 27 unneback 
 
3847 40 unneback 
`ifdef FIFO_CMP_ASYNC
3848 
`define MODULE fifo_cmp_async
3849 
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
3850 
`undef MODULE
3851 6 unneback 
 
3852 11 unneback 
   parameter addr_width = 4;
3853 
   parameter N = addr_width-1;
3854 6 unneback 
 
3855 
   parameter Q1 = 2'b00;
3856 
   parameter Q2 = 2'b01;
3857 
   parameter Q3 = 2'b11;
3858 
   parameter Q4 = 2'b10;
3859 
 
3860 
   parameter going_empty = 1'b0;
3861 
   parameter going_full  = 1'b1;
3862 
 
3863 
   input [N:0]  wptr, rptr;
3864 14 unneback 
   output       fifo_empty;
3865 6 unneback 
   output       fifo_full;
3866 
   input        wclk, rclk, rst;
3867 
 
3868 
`ifndef GENERATE_DIRECTION_AS_LATCH
3869 
   wire direction;
3870 
`endif
3871 
`ifdef GENERATE_DIRECTION_AS_LATCH
3872 
   reg direction;
3873 
`endif
3874 
   reg  direction_set, direction_clr;
3875 
 
3876 
   wire async_empty, async_full;
3877 
   wire fifo_full2;
3878 14 unneback 
   wire fifo_empty2;
3879 6 unneback 
 
3880 
   // direction_set
3881 
   always @ (wptr[N:N-1] or rptr[N:N-1])
3882 
     case ({wptr[N:N-1],rptr[N:N-1]})
3883 
       {Q1,Q2} : direction_set <= 1'b1;
3884 
       {Q2,Q3} : direction_set <= 1'b1;
3885 
       {Q3,Q4} : direction_set <= 1'b1;
3886 
       {Q4,Q1} : direction_set <= 1'b1;
3887 
       default : direction_set <= 1'b0;
3888 
     endcase
3889 
 
3890 
   // direction_clear
3891 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
3892 
     if (rst)
3893 
       direction_clr <= 1'b1;
3894 
     else
3895 
       case ({wptr[N:N-1],rptr[N:N-1]})
3896 
         {Q2,Q1} : direction_clr <= 1'b1;
3897 
         {Q3,Q2} : direction_clr <= 1'b1;
3898 
         {Q4,Q3} : direction_clr <= 1'b1;
3899 
         {Q1,Q4} : direction_clr <= 1'b1;
3900 
         default : direction_clr <= 1'b0;
3901 
       endcase
3902 
 
3903 40 unneback 
`define MODULE dff_sr
3904 6 unneback 
`ifndef GENERATE_DIRECTION_AS_LATCH
3905 40 unneback 
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
3906 6 unneback 
`endif
3907 
 
3908 
`ifdef GENERATE_DIRECTION_AS_LATCH
3909 
   always @ (posedge direction_set or posedge direction_clr)
3910 
     if (direction_clr)
3911 
       direction <= going_empty;
3912 
     else
3913 
       direction <= going_full;
3914 
`endif
3915 
 
3916 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
3917 
   assign async_full  = (wptr == rptr) && (direction==going_full);
3918 
 
3919 40 unneback 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
3920 
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
3921 
`undef MODULE
3922 6 unneback 
 
3923 
/*
3924 
   always @ (posedge wclk or posedge rst or posedge async_full)
3925 
     if (rst)
3926 
       {fifo_full, fifo_full2} <= 2'b00;
3927 
     else if (async_full)
3928 
       {fifo_full, fifo_full2} <= 2'b11;
3929 
     else
3930 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
3931 
*/
3932 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
3933 6 unneback 
     if (async_empty)
3934 
       {fifo_empty, fifo_empty2} <= 2'b11;
3935 
     else
3936 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
3937 40 unneback 
`define MODULE dff
3938 
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
3939 
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
3940 
`undef MODULE
3941 27 unneback 
endmodule // async_compb
3942 40 unneback 
`endif
3943 6 unneback 
 
3944 40 unneback 
`ifdef FIFO_1R1W_ASYNC
3945 
`define MODULE fifo_1r1w_async
3946 
module `BASE`MODULE (
3947 
`undef MODULE
3948 6 unneback 
    d, wr, fifo_full, wr_clk, wr_rst,
3949 
    q, rd, fifo_empty, rd_clk, rd_rst
3950 
    );
3951 
 
3952 
parameter data_width = 18;
3953 
parameter addr_width = 4;
3954 
 
3955 
// write side
3956 
input  [data_width-1:0] d;
3957 
input                   wr;
3958 
output                  fifo_full;
3959 
input                   wr_clk;
3960 
input                   wr_rst;
3961 
// read side
3962 
output [data_width-1:0] q;
3963 
input                   rd;
3964 
output                  fifo_empty;
3965 
input                   rd_clk;
3966 
input                   rd_rst;
3967 
 
3968 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
3969 23 unneback 
 
3970 40 unneback 
`define MODULE cnt_gray_ce_bin
3971 
`BASE`MODULE
3972 6 unneback 
    # ( .length(addr_width))
3973 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
3974 
 
3975 40 unneback 
`BASE`MODULE
3976 6 unneback 
    # (.length(addr_width))
3977 23 unneback 
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
3978 40 unneback 
`undef MODULE
3979 6 unneback 
 
3980 40 unneback 
`define MODULE dpram_1r1w
3981 
`BASE`MODULE
3982 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
3983 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
3984 40 unneback 
`undef MODULE
3985 6 unneback 
 
3986 40 unneback 
`define MODULE fifo_cmp_async
3987 
`BASE`MODULE
3988 6 unneback 
    # (.addr_width(addr_width))
3989 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
3990 40 unneback 
`undef MODULE
3991 6 unneback 
 
3992 
endmodule
3993 40 unneback 
`endif
3994 6 unneback 
 
3995 40 unneback 
`ifdef FIFO_2R2W_ASYNC
3996 
`define MODULE fifo_2r2w_async
3997 
module `BASE`MODULE (
3998 
`undef MODULE
3999 6 unneback 
    // a side
4000 
    a_d, a_wr, a_fifo_full,
4001 
    a_q, a_rd, a_fifo_empty,
4002 
    a_clk, a_rst,
4003 
    // b side
4004 
    b_d, b_wr, b_fifo_full,
4005 
    b_q, b_rd, b_fifo_empty,
4006 
    b_clk, b_rst
4007 
    );
4008 
 
4009 
parameter data_width = 18;
4010 
parameter addr_width = 4;
4011 
 
4012 
// a side
4013 
input  [data_width-1:0] a_d;
4014 
input                   a_wr;
4015 
output                  a_fifo_full;
4016 
output [data_width-1:0] a_q;
4017 
input                   a_rd;
4018 
output                  a_fifo_empty;
4019 
input                   a_clk;
4020 
input                   a_rst;
4021 
 
4022 
// b side
4023 
input  [data_width-1:0] b_d;
4024 
input                   b_wr;
4025 
output                  b_fifo_full;
4026 
output [data_width-1:0] b_q;
4027 
input                   b_rd;
4028 
output                  b_fifo_empty;
4029 
input                   b_clk;
4030 
input                   b_rst;
4031 
 
4032 40 unneback 
`define MODULE fifo_1r1w_async
4033 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4034 6 unneback 
vl_fifo_1r1w_async_a (
4035 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4036 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4037 
    );
4038 
 
4039 40 unneback 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4040 6 unneback 
vl_fifo_1r1w_async_b (
4041 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4042 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4043 
    );
4044 40 unneback 
`undef MODULE
4045 
 
4046 6 unneback 
endmodule
4047 40 unneback 
`endif
4048 6 unneback 
 
4049 40 unneback 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4050 
`define MODULE fifo_2r2w_async_simplex
4051 
module `BASE`MODULE (
4052 
`undef MODULE
4053 6 unneback 
    // a side
4054 
    a_d, a_wr, a_fifo_full,
4055 
    a_q, a_rd, a_fifo_empty,
4056 
    a_clk, a_rst,
4057 
    // b side
4058 
    b_d, b_wr, b_fifo_full,
4059 
    b_q, b_rd, b_fifo_empty,
4060 
    b_clk, b_rst
4061 
    );
4062 
 
4063 
parameter data_width = 18;
4064 
parameter addr_width = 4;
4065 
 
4066 
// a side
4067 
input  [data_width-1:0] a_d;
4068 
input                   a_wr;
4069 
output                  a_fifo_full;
4070 
output [data_width-1:0] a_q;
4071 
input                   a_rd;
4072 
output                  a_fifo_empty;
4073 
input                   a_clk;
4074 
input                   a_rst;
4075 
 
4076 
// b side
4077 
input  [data_width-1:0] b_d;
4078 
input                   b_wr;
4079 
output                  b_fifo_full;
4080 
output [data_width-1:0] b_q;
4081 
input                   b_rd;
4082 
output                  b_fifo_empty;
4083 
input                   b_clk;
4084 
input                   b_rst;
4085 
 
4086 
// adr_gen
4087 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4088 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4089 
// dpram
4090 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4091 
 
4092 40 unneback 
`define MODULE cnt_gray_ce_bin
4093 
`BASE`MODULE
4094 6 unneback 
    # ( .length(addr_width))
4095 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4096 
 
4097 40 unneback 
`BASE`MODULE
4098 6 unneback 
    # (.length(addr_width))
4099 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4100 
 
4101 40 unneback 
`BASE`MODULE
4102 6 unneback 
    # ( .length(addr_width))
4103 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4104 
 
4105 40 unneback 
`BASE`MODULE
4106 6 unneback 
    # (.length(addr_width))
4107 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4108 40 unneback 
`undef MODULE
4109 6 unneback 
 
4110 
// mux read or write adr to DPRAM
4111 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4112 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4113 
 
4114 40 unneback 
`define MODULE dpram_2r2w
4115 
`BASE`MODULE
4116 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4117 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4118 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4119 40 unneback 
`undef MODULE
4120 6 unneback 
 
4121 40 unneback 
`define MODULE fifo_cmp_async
4122 
`BASE`MODULE
4123 6 unneback 
    # (.addr_width(addr_width))
4124 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4125 
 
4126 40 unneback 
`BASE`MODULE
4127 6 unneback 
    # (.addr_width(addr_width))
4128 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4129 40 unneback 
`undef MODULE
4130 6 unneback 
 
4131 
endmodule
4132 40 unneback 
`endif
4133 48 unneback 
 
4134 
`ifdef REG_FILE
4135 
`define MODULE reg_file
4136 
module `BASE`MODULE (
4137 
`undef MODULE
4138 
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4139 
);
4140 
parameter data_width = 32;
4141 
parameter addr_width = 5;
4142 
input [addr_width-1:0] a1, a2, a3;
4143 
input [data_width-1:0] wd3;
4144 
input we3;
4145 
output [data_width-1:0] rd1, rd2;
4146 
input clk;
4147 
 
4148 
`ifdef ACTEL
4149 
reg [data_width-1:0] wd3_reg;
4150 
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4151 
reg we3_reg;
4152 
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
4153 
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
4154 
always @ (posedge clk or posedge rst)
4155 
if (rst)
4156 
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4157 
else
4158 
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4159 
 
4160 
    always @ (negedge clk)
4161 
    if (we3_reg)
4162 
        ram1[a3_reg] <= wd3;
4163 
    always @ (posedge clk)
4164 
        a1_reg <= a1;
4165 
    assign rd1 = ram1[a1_reg];
4166 
 
4167 
    always @ (negedge clk)
4168 
    if (we3_reg)
4169 
        ram2[a3_reg] <= wd3;
4170 
    always @ (posedge clk)
4171 
        a2_reg <= a2;
4172 
    assign rd2 = ram2[a2_reg];
4173 
 
4174 
`else
4175 
 
4176 
`define MODULE dpram_1r1w
4177 
`BASE`MODULE
4178 
    # ( .data_width(data_width), .addr_width(addr_width))
4179 
    ram1 (
4180 
        .d_a(wd3),
4181 
        .adr_a(a3),
4182 
        .we_a(we3),
4183 
        .clk_a(clk),
4184 
        .q_b(rd1),
4185 
        .adr_b(a1),
4186 
        .clk_b(clk) );
4187 
 
4188 
`BASE`MODULE
4189 
    # ( .data_width(data_width), .addr_width(addr_width))
4190 
    ram2 (
4191 
        .d_a(wd3),
4192 
        .adr_a(a3),
4193 
        .we_a(we3),
4194 
        .clk_a(clk),
4195 
        .q_b(rd2),
4196 
        .adr_b(a2),
4197 
        .clk_b(clk) );
4198 
`undef MODULE
4199 
 
4200 
`endif
4201 
 
4202 
endmodule
4203 
`endif
4204 12 unneback 
//////////////////////////////////////////////////////////////////////
4205 
////                                                              ////
4206 
////  Versatile library, wishbone stuff                           ////
4207 
////                                                              ////
4208 
////  Description                                                 ////
4209 
////  Wishbone compliant modules                                  ////
4210 
////                                                              ////
4211 
////                                                              ////
4212 
////  To Do:                                                      ////
4213 
////   -                                                          ////
4214 
////                                                              ////
4215 
////  Author(s):                                                  ////
4216 
////      - Michael Unneback, unneback@opencores.org              ////
4217 
////        ORSoC AB                                              ////
4218 
////                                                              ////
4219 
//////////////////////////////////////////////////////////////////////
4220 
////                                                              ////
4221 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4222 
////                                                              ////
4223 
//// This source file may be used and distributed without         ////
4224 
//// restriction provided that this copyright statement is not    ////
4225 
//// removed from the file and that any derivative work contains  ////
4226 
//// the original copyright notice and the associated disclaimer. ////
4227 
////                                                              ////
4228 
//// This source file is free software; you can redistribute it   ////
4229 
//// and/or modify it under the terms of the GNU Lesser General   ////
4230 
//// Public License as published by the Free Software Foundation; ////
4231 
//// either version 2.1 of the License, or (at your option) any   ////
4232 
//// later version.                                               ////
4233 
////                                                              ////
4234 
//// This source is distributed in the hope that it will be       ////
4235 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4236 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4237 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4238 
//// details.                                                     ////
4239 
////                                                              ////
4240 
//// You should have received a copy of the GNU Lesser General    ////
4241 
//// Public License along with this source; if not, download it   ////
4242 
//// from http://www.opencores.org/lgpl.shtml                     ////
4243 
////                                                              ////
4244 
//////////////////////////////////////////////////////////////////////
4245 
 
4246 40 unneback 
`ifdef WB3WB3_BRIDGE
4247 12 unneback 
// async wb3 - wb3 bridge
4248 
`timescale 1ns/1ns
4249 40 unneback 
`define MODULE wb3wb3_bridge
4250 
module `BASE`MODULE (
4251 
`undef MODULE
4252 12 unneback 
        // wishbone slave side
4253 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4254 
        // wishbone master side
4255 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4256 
 
4257 
input [31:0] wbs_dat_i;
4258 
input [31:2] wbs_adr_i;
4259 
input [3:0]  wbs_sel_i;
4260 
input [1:0]  wbs_bte_i;
4261 
input [2:0]  wbs_cti_i;
4262 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4263 
output [31:0] wbs_dat_o;
4264 14 unneback 
output wbs_ack_o;
4265 12 unneback 
input wbs_clk, wbs_rst;
4266 
 
4267 
output [31:0] wbm_dat_o;
4268 
output reg [31:2] wbm_adr_o;
4269 
output [3:0]  wbm_sel_o;
4270 
output reg [1:0]  wbm_bte_o;
4271 
output reg [2:0]  wbm_cti_o;
4272 14 unneback 
output reg wbm_we_o;
4273 
output wbm_cyc_o;
4274 12 unneback 
output wbm_stb_o;
4275 
input [31:0]  wbm_dat_i;
4276 
input wbm_ack_i;
4277 
input wbm_clk, wbm_rst;
4278 
 
4279 
parameter addr_width = 4;
4280 
 
4281 
// bte
4282 
parameter linear       = 2'b00;
4283 
parameter wrap4        = 2'b01;
4284 
parameter wrap8        = 2'b10;
4285 
parameter wrap16       = 2'b11;
4286 
// cti
4287 
parameter classic      = 3'b000;
4288 
parameter incburst     = 3'b010;
4289 
parameter endofburst   = 3'b111;
4290 
 
4291 
parameter wbs_adr  = 1'b0;
4292 
parameter wbs_data = 1'b1;
4293 
 
4294 33 unneback 
parameter wbm_adr0      = 2'b00;
4295 
parameter wbm_adr1      = 2'b01;
4296 
parameter wbm_data      = 2'b10;
4297 
parameter wbm_data_wait = 2'b11;
4298 12 unneback 
 
4299 
reg [1:0] wbs_bte_reg;
4300 
reg wbs;
4301 
wire wbs_eoc_alert, wbm_eoc_alert;
4302 
reg wbs_eoc, wbm_eoc;
4303 
reg [1:0] wbm;
4304 
 
4305 14 unneback 
wire [1:16] wbs_count, wbm_count;
4306 12 unneback 
 
4307 
wire [35:0] a_d, a_q, b_d, b_q;
4308 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4309 
reg a_rd_reg;
4310 
wire b_rd_adr, b_rd_data;
4311 14 unneback 
wire b_rd_data_reg;
4312 
wire [35:0] temp;
4313 12 unneback 
 
4314 
`define WE 5
4315 
`define BTE 4:3
4316 
`define CTI 2:0
4317 
 
4318 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4319 
always @ (posedge wbs_clk or posedge wbs_rst)
4320 
if (wbs_rst)
4321 
        wbs_eoc <= 1'b0;
4322 
else
4323 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4324 
                wbs_eoc <= wbs_bte_i==linear;
4325 
        else if (wbs_eoc_alert & (a_rd | a_wr))
4326 
                wbs_eoc <= 1'b1;
4327 
 
4328 40 unneback 
`define MODULE cnt_shreg_ce_clear
4329 
`BASE`MODULE # ( .length(16))
4330 
`undef MODULE
4331 12 unneback 
    cnt0 (
4332 
        .cke(wbs_ack_o),
4333 
        .clear(wbs_eoc),
4334 
        .q(wbs_count),
4335 
        .rst(wbs_rst),
4336 
        .clk(wbs_clk));
4337 
 
4338 
always @ (posedge wbs_clk or posedge wbs_rst)
4339 
if (wbs_rst)
4340 
        wbs <= wbs_adr;
4341 
else
4342 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
4343 
                wbs <= wbs_data;
4344 
        else if (wbs_eoc & wbs_ack_o)
4345 
                wbs <= wbs_adr;
4346 
 
4347 
// wbs FIFO
4348 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
4349 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
4350 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4351 
              1'b0;
4352 
assign a_rd = !a_fifo_empty;
4353 
always @ (posedge wbs_clk or posedge wbs_rst)
4354 
if (wbs_rst)
4355 
        a_rd_reg <= 1'b0;
4356 
else
4357 
        a_rd_reg <= a_rd;
4358 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4359 
 
4360 
assign wbs_dat_o = a_q[35:4];
4361 
 
4362 
always @ (posedge wbs_clk or posedge wbs_rst)
4363 
if (wbs_rst)
4364 13 unneback 
        wbs_bte_reg <= 2'b00;
4365 12 unneback 
else
4366 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
4367 12 unneback 
 
4368 
// wbm FIFO
4369 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4370 
always @ (posedge wbm_clk or posedge wbm_rst)
4371 
if (wbm_rst)
4372 
        wbm_eoc <= 1'b0;
4373 
else
4374 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4375 
                wbm_eoc <= b_q[`BTE] == linear;
4376 
        else if (wbm_eoc_alert & wbm_ack_i)
4377 
                wbm_eoc <= 1'b1;
4378 
 
4379 
always @ (posedge wbm_clk or posedge wbm_rst)
4380 
if (wbm_rst)
4381 
        wbm <= wbm_adr0;
4382 
else
4383 33 unneback 
/*
4384 12 unneback 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
4385 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
4386 
        (wbm==wbm_adr1 & !wbm_we_o) |
4387 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
4388 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
4389 33 unneback 
*/
4390 
    case (wbm)
4391 
    wbm_adr0:
4392 
        if (!b_fifo_empty)
4393 
            wbm <= wbm_adr1;
4394 
    wbm_adr1:
4395 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
4396 
            wbm <= wbm_data;
4397 
    wbm_data:
4398 
        if (wbm_ack_i & wbm_eoc)
4399 
            wbm <= wbm_adr0;
4400 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
4401 
            wbm <= wbm_data_wait;
4402 
    wbm_data_wait:
4403 
        if (!b_fifo_empty)
4404 
            wbm <= wbm_data;
4405 
    endcase
4406 12 unneback 
 
4407 
assign b_d = {wbm_dat_i,4'b1111};
4408 
assign b_wr = !wbm_we_o & wbm_ack_i;
4409 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
4410 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
4411 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
4412 33 unneback 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
4413 12 unneback 
                   1'b0;
4414 
assign b_rd = b_rd_adr | b_rd_data;
4415 
 
4416 40 unneback 
`define MODULE dff
4417 
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
4418 
`undef MODULE
4419 
`define MODULE dff_ce
4420 
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
4421 
`undef MODULE
4422 12 unneback 
 
4423 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
4424 
 
4425 40 unneback 
`define MODULE cnt_shreg_ce_clear
4426 42 unneback 
`BASE`MODULE # ( .length(16))
4427 40 unneback 
`undef MODULE
4428 12 unneback 
    cnt1 (
4429 
        .cke(wbm_ack_i),
4430 
        .clear(wbm_eoc),
4431 
        .q(wbm_count),
4432 
        .rst(wbm_rst),
4433 
        .clk(wbm_clk));
4434 
 
4435 33 unneback 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
4436 
assign wbm_stb_o = (wbm==wbm_data);
4437 12 unneback 
 
4438 
always @ (posedge wbm_clk or posedge wbm_rst)
4439 
if (wbm_rst)
4440 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
4441 
else begin
4442 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4443 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
4444 
        else if (wbm_eoc_alert & wbm_ack_i)
4445 
                wbm_cti_o <= endofburst;
4446 
end
4447 
 
4448 
//async_fifo_dw_simplex_top
4449 40 unneback 
`define MODULE fifo_2r2w_async_simplex
4450 
`BASE`MODULE
4451 
`undef MODULE
4452 12 unneback 
# ( .data_width(36), .addr_width(addr_width))
4453 
fifo (
4454 
    // a side
4455 
    .a_d(a_d),
4456 
    .a_wr(a_wr),
4457 
    .a_fifo_full(a_fifo_full),
4458 
    .a_q(a_q),
4459 
    .a_rd(a_rd),
4460 
    .a_fifo_empty(a_fifo_empty),
4461 
    .a_clk(wbs_clk),
4462 
    .a_rst(wbs_rst),
4463 
    // b side
4464 
    .b_d(b_d),
4465 
    .b_wr(b_wr),
4466 
    .b_fifo_full(b_fifo_full),
4467 
    .b_q(b_q),
4468 
    .b_rd(b_rd),
4469 
    .b_fifo_empty(b_fifo_empty),
4470 
    .b_clk(wbm_clk),
4471 
    .b_rst(wbm_rst)
4472 
    );
4473 
 
4474 
endmodule
4475 40 unneback 
`undef WE
4476 
`undef BTE
4477 
`undef CTI
4478 
`endif
4479 17 unneback 
 
4480 40 unneback 
`ifdef WB3_ARBITER_TYPE1
4481 
`define MODULE wb3_arbiter_type1
4482 42 unneback 
module `BASE`MODULE (
4483 40 unneback 
`undef MODULE
4484 39 unneback 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
4485 
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
4486 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
4487 
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
4488 
    wb_clk, wb_rst
4489 
);
4490 
 
4491 
parameter nr_of_ports = 3;
4492 
parameter adr_size = 26;
4493 
parameter adr_lo   = 2;
4494 
parameter dat_size = 32;
4495 
parameter sel_size = dat_size/8;
4496 
 
4497 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
4498 
localparam dw = dat_size * nr_of_ports;
4499 
localparam sw = sel_size * nr_of_ports;
4500 
localparam cw = 3 * nr_of_ports;
4501 
localparam bw = 2 * nr_of_ports;
4502 
 
4503 
input  [dw-1:0] wbm_dat_o;
4504 
input  [aw-1:0] wbm_adr_o;
4505 
input  [sw-1:0] wbm_sel_o;
4506 
input  [cw-1:0] wbm_cti_o;
4507 
input  [bw-1:0] wbm_bte_o;
4508 
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
4509 
output [dw-1:0] wbm_dat_i;
4510 
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
4511 
 
4512 
output [dat_size-1:0] wbs_dat_i;
4513 
output [adr_size-1:adr_lo] wbs_adr_i;
4514 
output [sel_size-1:0] wbs_sel_i;
4515 
output [2:0] wbs_cti_i;
4516 
output [1:0] wbs_bte_i;
4517 
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
4518 
input  [dat_size-1:0] wbs_dat_o;
4519 
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
4520 
 
4521 
input wb_clk, wb_rst;
4522 
 
4523 44 unneback 
reg  [nr_of_ports-1:0] select;
4524 39 unneback 
wire [nr_of_ports-1:0] state;
4525 
wire [nr_of_ports-1:0] eoc; // end-of-cycle
4526 
wire [nr_of_ports-1:0] sel;
4527 
wire idle;
4528 
 
4529 
genvar i;
4530 
 
4531 
assign idle = !(|state);
4532 
 
4533 
generate
4534 
if (nr_of_ports == 2) begin
4535 
 
4536 
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
4537 
 
4538 
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4539 
 
4540 44 unneback 
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4541 
 
4542 
    always @ (idle or wbm_cyc_o)
4543 
    if (idle)
4544 
        casex (wbm_cyc_o)
4545 
        2'b1x : select = 2'b10;
4546 
        2'b01 : select = 2'b01;
4547 
        default : select = {nr_of_ports{1'b0}};
4548 
        endcase
4549 
    else
4550 
        select = {nr_of_ports{1'b0}};
4551 
 
4552 39 unneback 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4553 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4554 
 
4555 
end
4556 
endgenerate
4557 
 
4558 
generate
4559 
if (nr_of_ports == 3) begin
4560 
 
4561 
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4562 
 
4563 
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4564 
 
4565 44 unneback 
    always @ (idle or wbm_cyc_o)
4566 
    if (idle)
4567 
        casex (wbm_cyc_o)
4568 
        3'b1xx : select = 3'b100;
4569 
        3'b01x : select = 3'b010;
4570 
        3'b001 : select = 3'b001;
4571 
        default : select = {nr_of_ports{1'b0}};
4572 
        endcase
4573 
    else
4574 
        select = {nr_of_ports{1'b0}};
4575 
 
4576 
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4577 39 unneback 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4578 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4579 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4580 
 
4581 
end
4582 
endgenerate
4583 
 
4584 
generate
4585 44 unneback 
if (nr_of_ports == 4) begin
4586 
 
4587 
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4588 
 
4589 
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4590 
 
4591 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4592 
 
4593 
    always @ (idle or wbm_cyc_o)
4594 
    if (idle)
4595 
        casex (wbm_cyc_o)
4596 
        4'b1xxx : select = 4'b1000;
4597 
        4'b01xx : select = 4'b0100;
4598 
        4'b001x : select = 4'b0010;
4599 
        4'b0001 : select = 4'b0001;
4600 
        default : select = {nr_of_ports{1'b0}};
4601 
        endcase
4602 
    else
4603 
        select = {nr_of_ports{1'b0}};
4604 
 
4605 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4606 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4607 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4608 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4609 
 
4610 
end
4611 
endgenerate
4612 
 
4613 
generate
4614 
if (nr_of_ports == 5) begin
4615 
 
4616 
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4617 
 
4618 
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4619 
 
4620 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4621 
 
4622 
    always @ (idle or wbm_cyc_o)
4623 
    if (idle)
4624 
        casex (wbm_cyc_o)
4625 
        5'b1xxxx : select = 5'b10000;
4626 
        5'b01xxx : select = 5'b01000;
4627 
        5'b001xx : select = 5'b00100;
4628 
        5'b0001x : select = 5'b00010;
4629 
        5'b00001 : select = 5'b00001;
4630 
        default : select = {nr_of_ports{1'b0}};
4631 
        endcase
4632 
    else
4633 
        select = {nr_of_ports{1'b0}};
4634 
 
4635 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
4636 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4637 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4638 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4639 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4640 
 
4641 
end
4642 
endgenerate
4643 
 
4644 
generate
4645 39 unneback 
for (i=0;i<nr_of_ports;i=i+1) begin
4646 42 unneback 
`define MODULE spr
4647 
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
4648 
`undef MODULE
4649 39 unneback 
end
4650 
endgenerate
4651 
 
4652 
    assign sel = select | state;
4653 
 
4654 40 unneback 
`define MODULE mux_andor
4655 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
4656 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
4657 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
4658 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
4659 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
4660 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
4661 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
4662 
`undef MODULE
4663 39 unneback 
    assign wbs_cyc_i = |sel;
4664 
 
4665 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
4666 
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
4667 
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
4668 
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
4669 
 
4670 
endmodule
4671 40 unneback 
`endif
4672 39 unneback 
 
4673 60 unneback 
`ifdef WB_B3_RAM_BE
4674 49 unneback 
// WB RAM with byte enable
4675 59 unneback 
`define MODULE wb_b3_ram_be
4676 
module `BASE`MODULE (
4677 
`undef MODULE
4678 61 unneback 
    wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
4679 59 unneback 
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
4680 
 
4681 60 unneback 
parameter nr_of_ports = 3;
4682 
parameter wb_arbiter_type = 1;
4683 
parameter adr_size = 26;
4684 
parameter adr_lo   = 2;
4685 
parameter dat_size = 32;
4686 
parameter memory_init = 1;
4687 
parameter memory_file = "vl_ram.vmem";
4688 59 unneback 
 
4689 60 unneback 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
4690 
localparam dw = dat_size * nr_of_ports;
4691 
localparam sw = dat_size/8 * nr_of_ports;
4692 
localparam cw = 3 * nr_of_ports;
4693 
localparam bw = 2 * nr_of_ports;
4694 
 
4695 
input [dw-1:0] wb_dat_i;
4696 
input [aw-1:0] wb_adr_i;
4697 
input [cw-1:0] wb_cti_i;
4698 61 unneback 
input [bw-1:0] wb_bte_i;
4699 60 unneback 
input [sw-1:0] wb_sel_i;
4700 
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
4701 
output [dw-1:0] wb_dat_o;
4702 
reg [dw-1:0] wb_dat_o;
4703 59 unneback 
output wb_ack_o;
4704 
reg wb_ack_o;
4705 
input wb_clk, wb_rst;
4706 
 
4707 60 unneback 
wire [sw-1:0] cke;
4708 59 unneback 
 
4709 60 unneback 
// local wb slave
4710 
wire [dat_size-1:0] wbs_dat_i;
4711 
wire [adr_size-1:0] wbs_adr_i;
4712 
wire [2:0] wbs_cti_i;
4713 61 unneback 
wire [1:0] wbs_bte_i;
4714 60 unneback 
wire [(dat_size/8)-1:0] wbs_sel_i;
4715 
wire  wbs_we_i, wbs_stb_i, wbs_cyc_i;
4716 
wire [dat_size-1:0] wbs_dat_o;
4717 
reg wbs_ack_o;
4718 
 
4719 59 unneback 
generate
4720 60 unneback 
if (nr_of_ports == 1) begin
4721 
    assign wbs_dat_i = wb_dat_i;
4722 
    assign wbs_adr_i = wb_adr_i;
4723 
    assign wbs_cti_i = wb_cti_i;
4724 
    assign wbs_sel_i = wb_sel_i;
4725 
    assign wbs_we_i  = wb_we_i;
4726 
    assign wbs_stb_i = wb_stb_i;
4727 
    assign wbs_cyc_i = wb_cyc_i;
4728 
    assign wb_dat_o  = wbs_dat_o;
4729 
    assign wb_ack_o  = wbs_ack_o;
4730 59 unneback 
end
4731 
endgenerate
4732 
 
4733 60 unneback 
generate
4734 
if (nr_of_ports > 1 & wb_arbiter_type == 1) begin
4735 
`define MODULE wb3_arbiter_type1
4736 
`BASE`MODULE wb_arbiter0(
4737 
`undef MODULE
4738 
    .wbm_dat_o(wb_dat_i),
4739 
    .wbm_adr_o(wb_adr_i),
4740 
    .wbm_sel_o(wb_sel_i),
4741 
    .wbm_cti_o(wb_cti_i),
4742 
    .wbm_bte_o(wb_bte_i),
4743 
    .wbm_we_o(wb_we_i),
4744 
    .wbm_stb_o(wb_stb_i),
4745 
    .wbm_cyc_o(wb_cyc_i),
4746 
    .wbm_dat_i(wb_dat_o),
4747 
    .wbm_ack_i(wb_ack_o),
4748 
    .wbm_err_i(),
4749 
    .wbm_rty_i(),
4750 
    .wbs_dat_i(wbs_dat_i),
4751 
    .wbs_adr_i(wbs_adr_i),
4752 
    .wbs_sel_i(wbs_sel_i),
4753 
    .wbs_cti_i(wbs_cti_i),
4754 
    .wbs_bte_i(wbs_bte_i),
4755 
    .wbs_we_i(wbs_we_i),
4756 
    .wbs_stb_i(wbs_stb_i),
4757 
    .wbs_cyc_i(wbs_cyc_i),
4758 
    .wbs_dat_o(wbs_dat_o),
4759 
    .wbs_ack_o(wbs_ack_o),
4760 
    .wbs_err_o(1'b0),
4761 
    .wbs_rty_o(1'b0),
4762 
    .wb_clk(wb_clk),
4763 
    .wb_rst(wb_rst)
4764 
);
4765 
end
4766 
endgenerate
4767 
 
4768 
`define MODULE ram_be
4769 
`BASE`MODULE # (
4770 
    .data_width(dat_size),
4771 
    .addr_width(adr_size),
4772 
    .memory_init(1),
4773 
    .memory_file("memory_file"))
4774 
ram0(
4775 
`undef MODULE
4776 
    .d(wbs_dat_i),
4777 
    .adr(wbs_adr_i[adr_size-1:2]),
4778 
    .be(wbs_sel_i),
4779 
    .we(wbs_we_i),
4780 
    .q(wbs_dat_o),
4781 
    .clk(wb_clk)
4782 
);
4783 
 
4784 59 unneback 
always @ (posedge wb_clk or posedge wb_rst)
4785 
if (wb_rst)
4786 60 unneback 
    wbs_ack_o <= 1'b0;
4787 59 unneback 
else
4788 60 unneback 
    if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
4789 
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
4790 59 unneback 
    else
4791 60 unneback 
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
4792 
 
4793 59 unneback 
endmodule
4794 
`endif
4795 
 
4796 
`ifdef WB_B4_RAM_BE
4797 
// WB RAM with byte enable
4798 49 unneback 
`define MODULE wb_b4_ram_be
4799 
module `BASE`MODULE (
4800 
`undef MODULE
4801 
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
4802 52 unneback 
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
4803 49 unneback 
 
4804 
    parameter dat_width = 32;
4805 
    parameter adr_width = 8;
4806 
 
4807 
input [dat_width-1:0] wb_dat_i;
4808 
input [adr_width-1:0] wb_adr_i;
4809 
input [dat_width/8-1:0] wb_sel_i;
4810 
input wb_we_i, wb_stb_i, wb_cyc_i;
4811 
output [dat_width-1:0] wb_dat_o;
4812 51 unneback 
reg [dat_width-1:0] wb_dat_o;
4813 52 unneback 
output wb_stall_o;
4814 49 unneback 
output wb_ack_o;
4815 
reg wb_ack_o;
4816 
input wb_clk, wb_rst;
4817 
 
4818 56 unneback 
wire [dat_width/8-1:0] cke;
4819 
 
4820 49 unneback 
generate
4821 
if (dat_width==32) begin
4822 51 unneback 
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
4823 
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
4824 
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
4825 
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
4826 56 unneback 
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
4827 49 unneback 
    always @ (posedge wb_clk)
4828 
    begin
4829 56 unneback 
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
4830 
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
4831 
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
4832 
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
4833 49 unneback 
    end
4834 59 unneback 
    always @ (posedge wb_clk or posedge wb_rst)
4835 
    begin
4836 
        if (wb_rst)
4837 
            wb_dat_o <= 32'h0;
4838 
        else
4839 
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
4840 
    end
4841 49 unneback 
end
4842 
endgenerate
4843 
 
4844 52 unneback 
always @ (posedge wb_clk or posedge wb_rst)
4845 55 unneback 
if (wb_rst)
4846 52 unneback 
    wb_ack_o <= 1'b0;
4847 
else
4848 54 unneback 
    wb_ack_o <= wb_stb_i & wb_cyc_i;
4849 52 unneback 
 
4850 
assign wb_stall_o = 1'b0;
4851 
 
4852 49 unneback 
endmodule
4853 
`endif
4854 
 
4855 48 unneback 
`ifdef WB_B4_ROM
4856 
// WB ROM
4857 
`define MODULE wb_b4_rom
4858 
module `BASE`MODULE (
4859 
`undef MODULE
4860 
    wb_adr_i, wb_stb_i, wb_cyc_i,
4861 
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
4862 
 
4863 
    parameter dat_width = 32;
4864 
    parameter dat_default = 32'h15000000;
4865 
    parameter adr_width = 32;
4866 
 
4867 
/*
4868 
`ifndef ROM
4869 
`define ROM "rom.v"
4870 
`endif
4871 
*/
4872 
    input [adr_width-1:2]   wb_adr_i;
4873 
    input                   wb_stb_i;
4874 
    input                   wb_cyc_i;
4875 
    output [dat_width-1:0]  wb_dat_o;
4876 
    reg [dat_width-1:0]     wb_dat_o;
4877 
    output                  wb_ack_o;
4878 
    reg                     wb_ack_o;
4879 
    output                  stall_o;
4880 
    input                   wb_clk;
4881 
    input                   wb_rst;
4882 
 
4883 
always @ (posedge wb_clk or posedge wb_rst)
4884 
    if (wb_rst)
4885 
        wb_dat_o <= {dat_width{1'b0}};
4886 
    else
4887 
         case (wb_adr_i[adr_width-1:2])
4888 
`ifdef ROM
4889 
`include `ROM
4890 
`endif
4891 
           default:
4892 
             wb_dat_o <= dat_default;
4893 
 
4894 
         endcase // case (wb_adr_i)
4895 
 
4896 
 
4897 
always @ (posedge wb_clk or posedge wb_rst)
4898 
    if (wb_rst)
4899 
        wb_ack_o <= 1'b0;
4900 
    else
4901 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
4902 
 
4903 
assign stall_o = 1'b0;
4904 
 
4905 
endmodule
4906 
`endif
4907 
 
4908 
 
4909 40 unneback 
`ifdef WB_BOOT_ROM
4910 17 unneback 
// WB ROM
4911 40 unneback 
`define MODULE wb_boot_rom
4912 
module `BASE`MODULE (
4913 
`undef MODULE
4914 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
4915 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
4916 17 unneback 
 
4917 18 unneback 
    parameter adr_hi = 31;
4918 
    parameter adr_lo = 28;
4919 
    parameter adr_sel = 4'hf;
4920 
    parameter addr_width = 5;
4921 33 unneback 
/*
4922 17 unneback 
`ifndef BOOT_ROM
4923 
`define BOOT_ROM "boot_rom.v"
4924 
`endif
4925 33 unneback 
*/
4926 18 unneback 
    input [adr_hi:2]    wb_adr_i;
4927 
    input               wb_stb_i;
4928 
    input               wb_cyc_i;
4929 
    output [31:0]        wb_dat_o;
4930 
    output              wb_ack_o;
4931 
    output              hit_o;
4932 
    input               wb_clk;
4933 
    input               wb_rst;
4934 
 
4935 
    wire hit;
4936 
    reg [31:0] wb_dat;
4937 
    reg wb_ack;
4938 
 
4939 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
4940 17 unneback 
 
4941 
always @ (posedge wb_clk or posedge wb_rst)
4942 
    if (wb_rst)
4943 18 unneback 
        wb_dat <= 32'h15000000;
4944 17 unneback 
    else
4945 18 unneback 
         case (wb_adr_i[addr_width-1:2])
4946 33 unneback 
`ifdef BOOT_ROM
4947 17 unneback 
`include `BOOT_ROM
4948 33 unneback 
`endif
4949 17 unneback 
           /*
4950 
            // Zero r0 and jump to 0x00000100
4951 18 unneback 
 
4952 
            1 : wb_dat <= 32'hA8200000;
4953 
            2 : wb_dat <= 32'hA8C00100;
4954 
            3 : wb_dat <= 32'h44003000;
4955 
            4 : wb_dat <= 32'h15000000;
4956 17 unneback 
            */
4957 
           default:
4958 18 unneback 
             wb_dat <= 32'h00000000;
4959 17 unneback 
 
4960 
         endcase // case (wb_adr_i)
4961 
 
4962 
 
4963 
always @ (posedge wb_clk or posedge wb_rst)
4964 
    if (wb_rst)
4965 18 unneback 
        wb_ack <= 1'b0;
4966 17 unneback 
    else
4967 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
4968 17 unneback 
 
4969 18 unneback 
assign hit_o = hit;
4970 
assign wb_dat_o = wb_dat & {32{wb_ack}};
4971 
assign wb_ack_o = wb_ack;
4972 
 
4973 17 unneback 
endmodule
4974 40 unneback 
`endif
4975 32 unneback 
 
4976 40 unneback 
`ifdef WB_DPRAM
4977 
`define MODULE wb_dpram
4978 
module `BASE`MODULE (
4979 
`undef MODULE
4980 32 unneback 
        // wishbone slave side a
4981 
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
4982 
        wbsa_clk, wbsa_rst,
4983 
        // wishbone slave side a
4984 
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
4985 
        wbsb_clk, wbsb_rst);
4986 
 
4987 
parameter data_width = 32;
4988 
parameter addr_width = 8;
4989 
 
4990 
parameter dat_o_mask_a = 1;
4991 
parameter dat_o_mask_b = 1;
4992 
 
4993 
input [31:0] wbsa_dat_i;
4994 
input [addr_width-1:2] wbsa_adr_i;
4995 
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
4996 
output [31:0] wbsa_dat_o;
4997 
output wbsa_ack_o;
4998 
input wbsa_clk, wbsa_rst;
4999 
 
5000 
input [31:0] wbsb_dat_i;
5001 
input [addr_width-1:2] wbsb_adr_i;
5002 
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
5003 
output [31:0] wbsb_dat_o;
5004 
output wbsb_ack_o;
5005 
input wbsb_clk, wbsb_rst;
5006 
 
5007 
wire wbsa_dat_tmp, wbsb_dat_tmp;
5008 
 
5009 40 unneback 
`define MODULE dpram_2r2w
5010 
`BASE`MODULE # (
5011 
`undef MODULE
5012 33 unneback 
    .data_width(data_width), .addr_width(addr_width) )
5013 32 unneback 
dpram0(
5014 
    .d_a(wbsa_dat_i),
5015 
    .q_a(wbsa_dat_tmp),
5016 
    .adr_a(wbsa_adr_i),
5017 
    .we_a(wbsa_we_i),
5018 
    .clk_a(wbsa_clk),
5019 
    .d_b(wbsb_dat_i),
5020 
    .q_b(wbsb_dat_tmp),
5021 
    .adr_b(wbsb_adr_i),
5022 
    .we_b(wbsb_we_i),
5023 
    .clk_b(wbsb_clk) );
5024 
 
5025 33 unneback 
generate if (dat_o_mask_a==1)
5026 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
5027 
endgenerate
5028 33 unneback 
generate if (dat_o_mask_a==0)
5029 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp;
5030 
endgenerate
5031 
 
5032 33 unneback 
generate if (dat_o_mask_b==1)
5033 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
5034 
endgenerate
5035 33 unneback 
generate if (dat_o_mask_b==0)
5036 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp;
5037 
endgenerate
5038 
 
5039 40 unneback 
`define MODULE spr
5040 
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
5041 
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
5042 
`undef MODULE
5043 32 unneback 
 
5044 
endmodule
5045 40 unneback 
`endif
5046 18 unneback 
//////////////////////////////////////////////////////////////////////
5047 
////                                                              ////
5048 
////  Arithmetic functions                                        ////
5049 
////                                                              ////
5050 
////  Description                                                 ////
5051 
////  Arithmetic functions for ALU and DSP                        ////
5052 
////                                                              ////
5053 
////                                                              ////
5054 
////  To Do:                                                      ////
5055 
////   -                                                          ////
5056 
////                                                              ////
5057 
////  Author(s):                                                  ////
5058 
////      - Michael Unneback, unneback@opencores.org              ////
5059 
////        ORSoC AB                                              ////
5060 
////                                                              ////
5061 
//////////////////////////////////////////////////////////////////////
5062 
////                                                              ////
5063 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
5064 
////                                                              ////
5065 
//// This source file may be used and distributed without         ////
5066 
//// restriction provided that this copyright statement is not    ////
5067 
//// removed from the file and that any derivative work contains  ////
5068 
//// the original copyright notice and the associated disclaimer. ////
5069 
////                                                              ////
5070 
//// This source file is free software; you can redistribute it   ////
5071 
//// and/or modify it under the terms of the GNU Lesser General   ////
5072 
//// Public License as published by the Free Software Foundation; ////
5073 
//// either version 2.1 of the License, or (at your option) any   ////
5074 
//// later version.                                               ////
5075 
////                                                              ////
5076 
//// This source is distributed in the hope that it will be       ////
5077 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
5078 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
5079 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
5080 
//// details.                                                     ////
5081 
////                                                              ////
5082 
//// You should have received a copy of the GNU Lesser General    ////
5083 
//// Public License along with this source; if not, download it   ////
5084 
//// from http://www.opencores.org/lgpl.shtml                     ////
5085 
////                                                              ////
5086 
//////////////////////////////////////////////////////////////////////
5087 
 
5088 40 unneback 
`ifdef MULTS
5089 18 unneback 
// signed multiplication
5090 40 unneback 
`define MODULE mults
5091 
module `BASE`MODULE (a,b,p);
5092 
`undef MODULE
5093 18 unneback 
parameter operand_a_width = 18;
5094 
parameter operand_b_width = 18;
5095 
parameter result_hi = 35;
5096 
parameter result_lo = 0;
5097 
input [operand_a_width-1:0] a;
5098 
input [operand_b_width-1:0] b;
5099 
output [result_hi:result_lo] p;
5100 
wire signed [operand_a_width-1:0] ai;
5101 
wire signed [operand_b_width-1:0] bi;
5102 
wire signed [operand_a_width+operand_b_width-1:0] result;
5103 
 
5104 
    assign ai = a;
5105 
    assign bi = b;
5106 
    assign result = ai * bi;
5107 
    assign p = result[result_hi:result_lo];
5108 
 
5109 
endmodule
5110 40 unneback 
`endif
5111 
`ifdef MULTS18X18
5112 
`define MODULE mults18x18
5113 
module `BASE`MODULE (a,b,p);
5114 
`undef MODULE
5115 18 unneback 
input [17:0] a,b;
5116 
output [35:0] p;
5117 
vl_mult
5118 
    # (.operand_a_width(18), .operand_b_width(18))
5119 
    mult0 (.a(a), .b(b), .p(p));
5120 
endmodule
5121 40 unneback 
`endif
5122 18 unneback 
 
5123 40 unneback 
`ifdef MULT
5124 
`define MODULE mult
5125 18 unneback 
// unsigned multiplication
5126 40 unneback 
module `BASE`MODULE (a,b,p);
5127 
`undef MODULE
5128 18 unneback 
parameter operand_a_width = 18;
5129 
parameter operand_b_width = 18;
5130 
parameter result_hi = 35;
5131 
parameter result_lo = 0;
5132 
input [operand_a_width-1:0] a;
5133 
input [operand_b_width-1:0] b;
5134 
output [result_hi:result_hi] p;
5135 
 
5136 
wire [operand_a_width+operand_b_width-1:0] result;
5137 
 
5138 
    assign result = a * b;
5139 
    assign p = result[result_hi:result_lo];
5140 
 
5141 
endmodule
5142 40 unneback 
`endif
5143 18 unneback 
 
5144 40 unneback 
`ifdef SHIFT_UNIT_32
5145 
`define MODULE shift_unit_32
5146 18 unneback 
// shift unit
5147 
// supporting the following shift functions
5148 
//   SLL
5149 
//   SRL
5150 
//   SRA
5151 
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
5152 40 unneback 
module `BASE`MODULE( din, s, dout, opcode);
5153 
`undef MODULE
5154 18 unneback 
input [31:0] din; // data in operand
5155 
input [4:0] s; // shift operand
5156 
input [1:0] opcode;
5157 
output [31:0] dout;
5158 
 
5159 
parameter opcode_sll = 2'b00;
5160 
//parameter opcode_srl = 2'b01;
5161 
parameter opcode_sra = 2'b10;
5162 
//parameter opcode_ror = 2'b11;
5163 
 
5164 
wire sll, sra;
5165 
assign sll = opcode == opcode_sll;
5166 
assign sra = opcode == opcode_sra;
5167 
 
5168 
wire [15:1] s1;
5169 
wire [3:0] sign;
5170 
wire [7:0] tmp [0:3];
5171 
 
5172 
// first stage is multiplier based
5173 
// shift operand as fractional 8.7
5174 
assign s1[15] = sll & s[2:0]==3'd7;
5175 
assign s1[14] = sll & s[2:0]==3'd6;
5176 
assign s1[13] = sll & s[2:0]==3'd5;
5177 
assign s1[12] = sll & s[2:0]==3'd4;
5178 
assign s1[11] = sll & s[2:0]==3'd3;
5179 
assign s1[10] = sll & s[2:0]==3'd2;
5180 
assign s1[ 9] = sll & s[2:0]==3'd1;
5181 
assign s1[ 8] = s[2:0]==3'd0;
5182 
assign s1[ 7] = !sll & s[2:0]==3'd1;
5183 
assign s1[ 6] = !sll & s[2:0]==3'd2;
5184 
assign s1[ 5] = !sll & s[2:0]==3'd3;
5185 
assign s1[ 4] = !sll & s[2:0]==3'd4;
5186 
assign s1[ 3] = !sll & s[2:0]==3'd5;
5187 
assign s1[ 2] = !sll & s[2:0]==3'd6;
5188 
assign s1[ 1] = !sll & s[2:0]==3'd7;
5189 
 
5190 
assign sign[3] = din[31] & sra;
5191 
assign sign[2] = sign[3] & (&din[31:24]);
5192 
assign sign[1] = sign[2] & (&din[23:16]);
5193 
assign sign[0] = sign[1] & (&din[15:8]);
5194 40 unneback 
`define MODULE mults
5195 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
5196 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
5197 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
5198 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
5199 
`undef MODULE
5200 18 unneback 
// second stage is multiplexer based
5201 
// shift on byte level
5202 
 
5203 
// mux byte 3
5204 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
5205 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
5206 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
5207 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
5208 
                     {8{sign[3]}};
5209 
 
5210 
// mux byte 2
5211 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
5212 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
5213 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
5214 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5215 
                     (s[4:3]==2'b01) ? tmp[3] :
5216 
                     {8{sign[3]}};
5217 
 
5218 
// mux byte 1
5219 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
5220 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
5221 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
5222 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5223 
                     (s[4:3]==2'b01) ? tmp[2] :
5224 
                     (s[4:3]==2'b10) ? tmp[3] :
5225 
                     {8{sign[3]}};
5226 
 
5227 
// mux byte 0
5228 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
5229 
                     (sll) ?  {8{1'b0}}:
5230 
                     (s[4:3]==2'b01) ? tmp[1] :
5231 
                     (s[4:3]==2'b10) ? tmp[2] :
5232 
                     tmp[3];
5233 
 
5234 
endmodule
5235 40 unneback 
`endif
5236 18 unneback 
 
5237 40 unneback 
`ifdef LOGIC_UNIT
5238 18 unneback 
// logic unit
5239 
// supporting the following logic functions
5240 
//    a and b
5241 
//    a or  b
5242 
//    a xor b
5243 
//    not b
5244 40 unneback 
`define MODULE logic_unit
5245 
module `BASE`MODULE( a, b, result, opcode);
5246 
`undef MODULE
5247 18 unneback 
parameter width = 32;
5248 
parameter opcode_and = 2'b00;
5249 
parameter opcode_or  = 2'b01;
5250 
parameter opcode_xor = 2'b10;
5251 
input [width-1:0] a,b;
5252 
output [width-1:0] result;
5253 
input [1:0] opcode;
5254 
 
5255 
assign result = (opcode==opcode_and) ? a & b :
5256 
                (opcode==opcode_or)  ? a | b :
5257 
                (opcode==opcode_xor) ? a ^ b :
5258 
                b;
5259 
 
5260 
endmodule
5261 48 unneback 
`endif
5262 18 unneback 
 
5263 48 unneback 
`ifdef ARITH_UNIT
5264 
`define MODULE arith_unit
5265 
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
5266 
`undef MODULE
5267 18 unneback 
parameter width = 32;
5268 
parameter opcode_add = 1'b0;
5269 
parameter opcode_sub = 1'b1;
5270 
input [width-1:0] a,b;
5271 
input c_in, add_sub, sign;
5272 
output [width-1:0] result;
5273 
output c_out, z, ovfl;
5274 
 
5275 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
5276 
assign z = (result=={width{1'b0}});
5277 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
5278 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
5279 
endmodule
5280 40 unneback 
`endif
5281 48 unneback 
 
5282 
`ifdef COUNT_UNIT
5283 
`define MODULE count_unit
5284 
module `BASE`MODULE (din, dout, opcode);
5285 
`undef MODULE
5286 
parameter width = 32;
5287 
input [width-1:0] din;
5288 
output [width-1:0] dout;
5289 
input opcode;
5290 
 
5291 
integer i;
5292 58 unneback 
wire [width/32+4:0] ff1, fl1;
5293 48 unneback 
 
5294 57 unneback 
/*
5295 48 unneback 
always @(din) begin
5296 
    ff1 = 0; i = 0;
5297 
    while (din[i] == 0 && i < width) begin // complex condition
5298 
        ff1 = ff1 + 1;
5299 
        i = i + 1;
5300 
    end
5301 
end
5302 
 
5303 
always @(din) begin
5304 
    fl1 = width; i = width-1;
5305 
    while (din[i] == 0 && i >= width) begin // complex condition
5306 
        fl1 = fl1 - 1;
5307 
        i = i - 1;
5308 
    end
5309 
end
5310 57 unneback 
*/
5311 48 unneback 
 
5312 
generate
5313 
if (width==32) begin
5314 57 unneback 
 
5315 
    assign ff1 = din[0] ? 6'd1 :
5316 
                 din[1] ? 6'd2 :
5317 
                 din[2] ? 6'd3 :
5318 
                 din[3] ? 6'd4 :
5319 
                 din[4] ? 6'd5 :
5320 
                 din[5] ? 6'd6 :
5321 
                 din[6] ? 6'd7 :
5322 
                 din[7] ? 6'd8 :
5323 
                 din[8] ? 6'd9 :
5324 
                 din[9] ? 6'd10 :
5325 
                 din[10] ? 6'd11 :
5326 
                 din[11] ? 6'd12 :
5327 
                 din[12] ? 6'd13 :
5328 
                 din[13] ? 6'd14 :
5329 
                 din[14] ? 6'd15 :
5330 
                 din[15] ? 6'd16 :
5331 
                 din[16] ? 6'd17 :
5332 
                 din[17] ? 6'd18 :
5333 
                 din[18] ? 6'd19 :
5334 
                 din[19] ? 6'd20 :
5335 
                 din[20] ? 6'd21 :
5336 
                 din[21] ? 6'd22 :
5337 
                 din[22] ? 6'd23 :
5338 
                 din[23] ? 6'd24 :
5339 
                 din[24] ? 6'd25 :
5340 
                 din[25] ? 6'd26 :
5341 
                 din[26] ? 6'd27 :
5342 
                 din[27] ? 6'd28 :
5343 
                 din[28] ? 6'd29 :
5344 
                 din[29] ? 6'd30 :
5345 
                 din[30] ? 6'd31 :
5346 
                 din[31] ? 6'd32 :
5347 
                 6'd0;
5348 
 
5349 
    assign fl1 = din[31] ? 6'd32 :
5350 
                 din[30] ? 6'd31 :
5351 
                 din[29] ? 6'd30 :
5352 
                 din[28] ? 6'd29 :
5353 
                 din[27] ? 6'd28 :
5354 
                 din[26] ? 6'd27 :
5355 
                 din[25] ? 6'd26 :
5356 
                 din[24] ? 6'd25 :
5357 
                 din[23] ? 6'd24 :
5358 
                 din[22] ? 6'd23 :
5359 
                 din[21] ? 6'd22 :
5360 
                 din[20] ? 6'd21 :
5361 
                 din[19] ? 6'd20 :
5362 
                 din[18] ? 6'd19 :
5363 
                 din[17] ? 6'd18 :
5364 
                 din[16] ? 6'd17 :
5365 
                 din[15] ? 6'd16 :
5366 
                 din[14] ? 6'd15 :
5367 
                 din[13] ? 6'd14 :
5368 
                 din[12] ? 6'd13 :
5369 
                 din[11] ? 6'd12 :
5370 
                 din[10] ? 6'd11 :
5371 
                 din[9] ? 6'd10 :
5372 
                 din[8] ? 6'd9 :
5373 
                 din[7] ? 6'd8 :
5374 
                 din[6] ? 6'd7 :
5375 
                 din[5] ? 6'd6 :
5376 
                 din[4] ? 6'd5 :
5377 
                 din[3] ? 6'd4 :
5378 
                 din[2] ? 6'd3 :
5379 
                 din[1] ? 6'd2 :
5380 
                 din[0] ? 6'd1 :
5381 
                 6'd0;
5382 
 
5383 
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
5384 48 unneback 
end
5385 
endgenerate
5386 57 unneback 
 
5387 48 unneback 
generate
5388 
if (width==64) begin
5389 57 unneback 
    assign ff1 = 7'd0;
5390 
    assign fl1 = 7'd0;
5391 
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
5392 48 unneback 
end
5393 
endgenerate
5394 
 
5395 
endmodule
5396 
`endif
5397 
 
5398 
`ifdef EXT_UNIT
5399 
`define MODULE ext_unit
5400 
module `BASE`MODULE ( a, b, F, result, opcode);
5401 
`undef MODULE
5402 
parameter width = 32;
5403 
input [width-1:0] a, b;
5404 
input F;
5405 
output reg [width-1:0] result;
5406 
input [2:0] opcode;
5407 
 
5408 
generate
5409 
if (width==32) begin
5410 
always @ (a or b or F or opcode)
5411 
begin
5412 
    case (opcode)
5413 
    3'b000: result = {{24{1'b0}},a[7:0]};
5414 
    3'b001: result = {{24{a[7]}},a[7:0]};
5415 
    3'b010: result = {{16{1'b0}},a[7:0]};
5416 
    3'b011: result = {{16{a[15]}},a[15:0]};
5417 
    3'b110: result = (F) ? a : b;
5418 
    default: result = {b[15:0],16'h0000};
5419 
    endcase
5420 
end
5421 
end
5422 
endgenerate
5423 
 
5424 
generate
5425 
if (width==64) begin
5426 
always @ (a or b or F or opcode)
5427 
begin
5428 
    case (opcode)
5429 
    3'b000: result = {{56{1'b0}},a[7:0]};
5430 
    3'b001: result = {{56{a[7]}},a[7:0]};
5431 
    3'b010: result = {{48{1'b0}},a[7:0]};
5432 
    3'b011: result = {{48{a[15]}},a[15:0]};
5433 57 unneback 
    3'b110: result = (F) ? a : b;
5434 48 unneback 
    default: result = {32'h00000000,b[15:0],16'h0000};
5435 
    endcase
5436 
end
5437 
end
5438 
endgenerate
5439 
endmodule
5440 
`endif

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