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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 64

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 40 unneback 
`ifdef ALL
14 
 
15 
`define GBUF
16 
`define SYNC_RST
17 
`define PLL
18 
 
19 
`define MULTS
20 
`define MULTS18X18
21 
`define MULT
22 
`define SHIFT_UNIT_32
23 
`define LOGIC_UNIT
24 
 
25 
`define CNT_SHREG_WRAP
26 
`define CNT_SHREG_CE_WRAP
27 
`define CNT_SHREG_CE_CLEAR
28 
`define CNT_SHREG_CE_CLEAR_WRAP
29 
 
30 
`define MUX_ANDOR
31 
`define MUX2_ANDOR
32 
`define MUX3_ANDOR
33 
`define MUX4_ANDOR
34 
`define MUX5_ANDOR
35 
`define MUX6_ANDOR
36 43 unneback 
`define PARITY
37 40 unneback 
 
38 
`define ROM_INIT
39 
`define RAM
40 
`define RAM_BE
41 
`define DPRAM_1R1W
42 
`define DPRAM_2R1W
43 
`define DPRAM_2R2W
44 
`define FIFO_1R1W_FILL_LEVEL_SYNC
45 
`define FIFO_2R2W_SYNC_SIMPLEX
46 
`define FIFO_CMP_ASYNC
47 
`define FIFO_1R1W_ASYNC
48 
`define FIFO_2R2W_ASYNC
49 
`define FIFO_2R2W_ASYNC_SIMPLEX
50 48 unneback 
`define REG_FILE
51 40 unneback 
 
52 
`define DFF
53 
`define DFF_ARRAY
54 
`define DFF_CE
55 
`define DFF_CE_CLEAR
56 
`define DF_CE_SET
57 
`define SPR
58 
`define SRP
59 
`define DFF_SR
60 
`define LATCH
61 
`define SHREG
62 
`define SHREG_CE
63 
`define DELAY
64 
`define DELAY_EMPTYFLAG
65 
 
66 
`define WB3WB3_BRIDGE
67 
`define WB3_ARBITER_TYPE1
68 59 unneback 
`define WB_B3_RAM_BE
69 49 unneback 
`define WB_B4_RAM_BE
70 48 unneback 
`define WB_B4_ROM
71 40 unneback 
`define WB_BOOT_ROM
72 
`define WB_DPRAM
73 
 
74 44 unneback 
`define IO_DFF_OE
75 
`define O_DFF
76 
 
77 40 unneback 
`endif
78 
 
79 
`ifdef PLL
80 
`ifndef SYNC_RST
81 
`define SYNC_RST
82 
`endif
83 
`endif
84 
 
85 
`ifdef SYNC_RST
86 
`ifndef GBUF
87 
`define GBUF
88 
`endif
89 
`endif
90 
 
91 
`ifdef WB_DPRAM
92 
`ifndef DPRAM_2R2W
93 
`define DPRAM_2R2W
94 
`endif
95 
`ifndef SPR
96 
`define SPR
97 
`endif
98 
`endif
99 
 
100 62 unneback 
`ifdef WB_B3_RAM_BE
101 
`ifndef WB3_ARBITER_TYPE1
102 
`define WB3_ARBITER_TYPE1
103 
`endif
104 
`ifndef RAM_BE
105 
`define RAM_BE
106 
`endif
107 
`endif
108 
 
109 40 unneback 
`ifdef WB3_ARBITER_TYPE1
110 42 unneback 
`ifndef SPR
111 
`define SPR
112 
`endif
113 40 unneback 
`ifndef MUX_ANDOR
114 
`define MUX_ANDOR
115 
`endif
116 
`endif
117 
 
118 
`ifdef WB3WB3_BRIDGE
119 
`ifndef CNT_SHREG_CE_CLEAR
120 
`define CNT_SHREG_CE_CLEAR
121 
`endif
122 
`ifndef DFF
123 
`define DFF
124 
`endif
125 
`ifndef DFF_CE
126 
`define DFF_CE
127 
`endif
128 
`ifndef CNT_SHREG_CE_CLEAR
129 
`define CNT_SHREG_CE_CLEAR
130 
`endif
131 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
132 
`define FIFO_2R2W_ASYNC_SIMPLEX
133 
`endif
134 
`endif
135 
 
136 
`ifdef MULTS18X18
137 
`ifndef MULTS
138 
`define MULTS
139 
`endif
140 
`endif
141 
 
142 
`ifdef SHIFT_UNIT_32
143 
`ifndef MULTS
144 
`define MULTS
145 
`endif
146 
`endif
147 
 
148 
`ifdef MUX2_ANDOR
149 
`ifndef MUX_ANDOR
150 
`define MUX_ANDOR
151 
`endif
152 
`endif
153 
 
154 
`ifdef MUX3_ANDOR
155 
`ifndef MUX_ANDOR
156 
`define MUX_ANDOR
157 
`endif
158 
`endif
159 
 
160 
`ifdef MUX4_ANDOR
161 
`ifndef MUX_ANDOR
162 
`define MUX_ANDOR
163 
`endif
164 
`endif
165 
 
166 
`ifdef MUX5_ANDOR
167 
`ifndef MUX_ANDOR
168 
`define MUX_ANDOR
169 
`endif
170 
`endif
171 
 
172 
`ifdef MUX6_ANDOR
173 
`ifndef MUX_ANDOR
174 
`define MUX_ANDOR
175 
`endif
176 
`endif
177 
 
178 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
179 
`ifndef CNT_BIN_CE
180 
`define CNT_BIN_CE
181 
`endif
182 
`ifndef DPRAM_1R1W
183 
`define DPRAM_1R1W
184 
`endif
185 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
186 
`define CNT_BIN_CE_REW_Q_ZQ_L1
187 
`endif
188 
`endif
189 
 
190 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
191 
`ifndef CNT_LFSR_CE
192 
`define CNT_LFSR_CE
193 
`endif
194 
`ifndef DPRAM_2R2W
195 
`define DPRAM_2R2W
196 
`endif
197 
`ifndef CNT_BIN_CE_REW_ZQ_L1
198 
`define CNT_BIN_CE_REW_ZQ_L1
199 
`endif
200 
`endif
201 
 
202 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
203 
`ifndef CNT_GRAY_CE_BIN
204 
`define CNT_GRAY_CE_BIN
205 
`endif
206 
`ifndef DPRAM_2R2W
207 
`define DPRAM_2R2W
208 
`endif
209 
`ifndef FIFO_CMP_ASYNC
210 
`define FIFO_CMP_ASYNC
211 
`endif
212 
`endif
213 
 
214 
`ifdef FIFO_2R2W_ASYNC
215 
`ifndef FIFO_1R1W_ASYNC
216 
`define FIFO_1R1W_ASYNC
217 
`endif
218 
`endif
219 
 
220 
`ifdef FIFO_1R1W_ASYNC
221 
`ifndef CNT_GRAY_CE_BIN
222 
`define CNT_GRAY_CE_BIN
223 
`endif
224 
`ifndef DPRAM_1R1W
225 
`define DPRAM_1R1W
226 
`endif
227 
`ifndef FIFO_CMP_ASYNC
228 
`define FIFO_CMP_ASYNC
229 
`endif
230 
`endif
231 
 
232 
`ifdef FIFO_CMP_ASYNC
233 
`ifndef DFF_SR
234 
`define DFF_SR
235 
`endif
236 
`ifndef DFF
237 
`define DFF
238 
`endif
239 
`endif
240 48 unneback 
 
241 
`ifdef REG_FILE
242 
`ifndef DPRAM_1R1W
243 
`define DPRAM_1R1W
244 
`endif
245 
`endif
246 62 unneback 
//////////////////////////////////////////////////////////////////////
247 6 unneback 
////                                                              ////
248 
////  Versatile library, clock and reset                          ////
249 
////                                                              ////
250 
////  Description                                                 ////
251 
////  Logic related to clock and reset                            ////
252 
////                                                              ////
253 
////                                                              ////
254 
////  To Do:                                                      ////
255 
////   - add more different registers                             ////
256 
////                                                              ////
257 
////  Author(s):                                                  ////
258 
////      - Michael Unneback, unneback@opencores.org              ////
259 
////        ORSoC AB                                              ////
260 
////                                                              ////
261 
//////////////////////////////////////////////////////////////////////
262 
////                                                              ////
263 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
264 
////                                                              ////
265 
//// This source file may be used and distributed without         ////
266 
//// restriction provided that this copyright statement is not    ////
267 
//// removed from the file and that any derivative work contains  ////
268 
//// the original copyright notice and the associated disclaimer. ////
269 
////                                                              ////
270 
//// This source file is free software; you can redistribute it   ////
271 
//// and/or modify it under the terms of the GNU Lesser General   ////
272 
//// Public License as published by the Free Software Foundation; ////
273 
//// either version 2.1 of the License, or (at your option) any   ////
274 
//// later version.                                               ////
275 
////                                                              ////
276 
//// This source is distributed in the hope that it will be       ////
277 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
278 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
279 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
280 
//// details.                                                     ////
281 
////                                                              ////
282 
//// You should have received a copy of the GNU Lesser General    ////
283 
//// Public License along with this source; if not, download it   ////
284 
//// from http://www.opencores.org/lgpl.shtml                     ////
285 
////                                                              ////
286 
//////////////////////////////////////////////////////////////////////
287 
 
288 48 unneback 
`ifdef ACTEL
289 
`ifdef GBUF
290 
`timescale 1 ns/100 ps
291 6 unneback 
// Global buffer
292 
// usage:
293 
// use to enable global buffers for high fan out signals such as clock and reset
294 
// Version: 8.4 8.4.0.33
295 
module gbuf(GL,CLK);
296 
output GL;
297 
input  CLK;
298 
 
299 
    wire GND;
300 
 
301 
    GND GND_1_net(.Y(GND));
302 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
303 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
304 
 
305 
endmodule
306 
`timescale 1 ns/1 ns
307 40 unneback 
`define MODULE gbuf
308 
module `BASE`MODULE ( i, o);
309 
`undef MODULE
310 6 unneback 
input i;
311 
output o;
312 
`ifdef SIM_GBUF
313 
assign o=i;
314 
`else
315 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
316 
`endif
317 
endmodule
318 40 unneback 
`endif
319 33 unneback 
 
320 6 unneback 
`else
321 33 unneback 
 
322 40 unneback 
`ifdef ALTERA
323 
`ifdef GBUF
324 21 unneback 
//altera
325 40 unneback 
`define MODULE gbuf
326 
module `BASE`MODULE ( i, o);
327 
`undef MODULE
328 33 unneback 
input i;
329 
output o;
330 
assign o = i;
331 
endmodule
332 40 unneback 
`endif
333 33 unneback 
 
334 6 unneback 
`else
335 
 
336 40 unneback 
`ifdef GBUF
337 6 unneback 
`timescale 1 ns/100 ps
338 40 unneback 
`define MODULE
339 
module `BASE`MODULE ( i, o);
340 
`undef MODULE
341 6 unneback 
input i;
342 
output o;
343 
assign o = i;
344 
endmodule
345 40 unneback 
`endif
346 6 unneback 
`endif // ALTERA
347 
`endif //ACTEL
348 
 
349 40 unneback 
`ifdef SYNC_RST
350 6 unneback 
// sync reset
351 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
352 6 unneback 
// output active high global reset sync with two DFFs
353 
`timescale 1 ns/100 ps
354 40 unneback 
`define MODULE sync_rst
355 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
356 
`undef MODULE
357 6 unneback 
input rst_n_i, clk;
358 
output rst_o;
359 18 unneback 
reg [1:0] tmp;
360 6 unneback 
always @ (posedge clk or negedge rst_n_i)
361 
if (!rst_n_i)
362 17 unneback 
        tmp <= 2'b11;
363 6 unneback 
else
364 33 unneback 
        tmp <= {1'b0,tmp[1]};
365 40 unneback 
`define MODULE gbuf
366 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
367 
`undef MODULE
368 6 unneback 
endmodule
369 40 unneback 
`endif
370 6 unneback 
 
371 40 unneback 
`ifdef PLL
372 6 unneback 
// vl_pll
373 
`ifdef ACTEL
374 32 unneback 
///////////////////////////////////////////////////////////////////////////////
375 17 unneback 
`timescale 1 ps/1 ps
376 40 unneback 
`define MODULE pll
377 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
378 
`undef MODULE
379 6 unneback 
parameter index = 0;
380 
parameter number_of_clk = 1;
381 17 unneback 
parameter period_time_0 = 20000;
382 
parameter period_time_1 = 20000;
383 
parameter period_time_2 = 20000;
384 
parameter lock_delay = 2000000;
385 6 unneback 
input clk_i, rst_n_i;
386 
output lock;
387 
output reg [0:number_of_clk-1] clk_o;
388 
output [0:number_of_clk-1] rst_o;
389 
 
390 
`ifdef SIM_PLL
391 
 
392 
always
393 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
394 
 
395 
generate if (number_of_clk > 1)
396 
always
397 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
398 
endgenerate
399 
 
400 
generate if (number_of_clk > 2)
401 
always
402 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
403 
endgenerate
404 
 
405 
genvar i;
406 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
407 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
408 
end
409 
endgenerate
410 
 
411 
assign #lock_delay lock = rst_n_i;
412 
 
413 
endmodule
414 
`else
415 
generate if (number_of_clk==1 & index==0) begin
416 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
417 
end
418 
endgenerate // index==0
419 
generate if (number_of_clk==1 & index==1) begin
420 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
421 
end
422 
endgenerate // index==1
423 
generate if (number_of_clk==1 & index==2) begin
424 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
425 
end
426 
endgenerate // index==2
427 
generate if (number_of_clk==1 & index==3) begin
428 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
429 
end
430 
endgenerate // index==0
431 
 
432 
generate if (number_of_clk==2 & index==0) begin
433 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
434 
end
435 
endgenerate // index==0
436 
generate if (number_of_clk==2 & index==1) begin
437 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
438 
end
439 
endgenerate // index==1
440 
generate if (number_of_clk==2 & index==2) begin
441 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
442 
end
443 
endgenerate // index==2
444 
generate if (number_of_clk==2 & index==3) begin
445 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
446 
end
447 
endgenerate // index==0
448 
 
449 
generate if (number_of_clk==3 & index==0) begin
450 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
451 
end
452 
endgenerate // index==0
453 
generate if (number_of_clk==3 & index==1) begin
454 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
455 
end
456 
endgenerate // index==1
457 
generate if (number_of_clk==3 & index==2) begin
458 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
459 
end
460 
endgenerate // index==2
461 
generate if (number_of_clk==3 & index==3) begin
462 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
463 
end
464 
endgenerate // index==0
465 
 
466 
genvar i;
467 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
468 40 unneback 
`define MODULE sync_rst
469 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
470 
`undef MODULE
471 6 unneback 
end
472 
endgenerate
473 
endmodule
474 
`endif
475 32 unneback 
///////////////////////////////////////////////////////////////////////////////
476 6 unneback 
 
477 
`else
478 
 
479 32 unneback 
///////////////////////////////////////////////////////////////////////////////
480 6 unneback 
`ifdef ALTERA
481 
 
482 32 unneback 
`timescale 1 ps/1 ps
483 40 unneback 
`define MODULE pll
484 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
485 
`undef MODULE
486 32 unneback 
parameter index = 0;
487 
parameter number_of_clk = 1;
488 
parameter period_time_0 = 20000;
489 
parameter period_time_1 = 20000;
490 
parameter period_time_2 = 20000;
491 
parameter period_time_3 = 20000;
492 
parameter period_time_4 = 20000;
493 
parameter lock_delay = 2000000;
494 
input clk_i, rst_n_i;
495 
output lock;
496 
output reg [0:number_of_clk-1] clk_o;
497 
output [0:number_of_clk-1] rst_o;
498 
 
499 
`ifdef SIM_PLL
500 
 
501 
always
502 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
503 
 
504 
generate if (number_of_clk > 1)
505 
always
506 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
507 
endgenerate
508 
 
509 
generate if (number_of_clk > 2)
510 
always
511 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
512 
endgenerate
513 
 
514 33 unneback 
generate if (number_of_clk > 3)
515 32 unneback 
always
516 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
517 
endgenerate
518 
 
519 33 unneback 
generate if (number_of_clk > 4)
520 32 unneback 
always
521 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
522 
endgenerate
523 
 
524 
genvar i;
525 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
526 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
527 
end
528 
endgenerate
529 
 
530 33 unneback 
//assign #lock_delay lock = rst_n_i;
531 
assign lock = rst_n_i;
532 32 unneback 
 
533 
endmodule
534 6 unneback 
`else
535 
 
536 33 unneback 
`ifdef VL_PLL0
537 
`ifdef VL_PLL0_CLK1
538 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
539 
`endif
540 
`ifdef VL_PLL0_CLK2
541 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
542 
`endif
543 
`ifdef VL_PLL0_CLK3
544 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
545 
`endif
546 
`ifdef VL_PLL0_CLK4
547 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
548 
`endif
549 
`ifdef VL_PLL0_CLK5
550 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
551 
`endif
552 
`endif
553 32 unneback 
 
554 33 unneback 
`ifdef VL_PLL1
555 
`ifdef VL_PLL1_CLK1
556 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
557 
`endif
558 
`ifdef VL_PLL1_CLK2
559 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
560 
`endif
561 
`ifdef VL_PLL1_CLK3
562 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
563 
`endif
564 
`ifdef VL_PLL1_CLK4
565 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
566 
`endif
567 
`ifdef VL_PLL1_CLK5
568 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
569 
`endif
570 
`endif
571 32 unneback 
 
572 33 unneback 
`ifdef VL_PLL2
573 
`ifdef VL_PLL2_CLK1
574 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
575 
`endif
576 
`ifdef VL_PLL2_CLK2
577 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
578 
`endif
579 
`ifdef VL_PLL2_CLK3
580 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
581 
`endif
582 
`ifdef VL_PLL2_CLK4
583 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
584 
`endif
585 
`ifdef VL_PLL2_CLK5
586 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
587 
`endif
588 
`endif
589 32 unneback 
 
590 33 unneback 
`ifdef VL_PLL3
591 
`ifdef VL_PLL3_CLK1
592 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
593 
`endif
594 
`ifdef VL_PLL3_CLK2
595 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
596 
`endif
597 
`ifdef VL_PLL3_CLK3
598 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
599 
`endif
600 
`ifdef VL_PLL3_CLK4
601 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
602 
`endif
603 
`ifdef VL_PLL3_CLK5
604 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
605 
`endif
606 
`endif
607 32 unneback 
 
608 
genvar i;
609 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
610 40 unneback 
`define MODULE sync_rst
611 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
612 
`undef MODULE
613 32 unneback 
end
614 
endgenerate
615 
endmodule
616 
`endif
617 
///////////////////////////////////////////////////////////////////////////////
618 
 
619 
`else
620 
 
621 6 unneback 
// generic PLL
622 17 unneback 
`timescale 1 ps/1 ps
623 40 unneback 
`define MODULE pll
624 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
625 
`undef MODULE
626 6 unneback 
parameter index = 0;
627 
parameter number_of_clk = 1;
628 17 unneback 
parameter period_time_0 = 20000;
629 
parameter period_time_1 = 20000;
630 
parameter period_time_2 = 20000;
631 6 unneback 
parameter lock_delay = 2000;
632 
input clk_i, rst_n_i;
633 
output lock;
634 
output reg [0:number_of_clk-1] clk_o;
635 
output [0:number_of_clk-1] rst_o;
636 
 
637 
always
638 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
639 
 
640 
generate if (number_of_clk > 1)
641 
always
642 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
643 
endgenerate
644 
 
645 
generate if (number_of_clk > 2)
646 
always
647 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
648 
endgenerate
649 
 
650 
genvar i;
651 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
652 40 unneback 
`define MODULE sync_rst
653 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
654 
`undef MODULE
655 6 unneback 
end
656 
endgenerate
657 
 
658 
assign #lock_delay lock = rst_n_i;
659 
 
660 
endmodule
661 
 
662 
`endif //altera
663 17 unneback 
`endif //actel
664 40 unneback 
`undef MODULE
665 
`endif//////////////////////////////////////////////////////////////////////
666 6 unneback 
////                                                              ////
667 
////  Versatile library, registers                                ////
668 
////                                                              ////
669 
////  Description                                                 ////
670 
////  Different type of registers                                 ////
671 
////                                                              ////
672 
////                                                              ////
673 
////  To Do:                                                      ////
674 
////   - add more different registers                             ////
675 
////                                                              ////
676 
////  Author(s):                                                  ////
677 
////      - Michael Unneback, unneback@opencores.org              ////
678 
////        ORSoC AB                                              ////
679 
////                                                              ////
680 
//////////////////////////////////////////////////////////////////////
681 
////                                                              ////
682 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
683 
////                                                              ////
684 
//// This source file may be used and distributed without         ////
685 
//// restriction provided that this copyright statement is not    ////
686 
//// removed from the file and that any derivative work contains  ////
687 
//// the original copyright notice and the associated disclaimer. ////
688 
////                                                              ////
689 
//// This source file is free software; you can redistribute it   ////
690 
//// and/or modify it under the terms of the GNU Lesser General   ////
691 
//// Public License as published by the Free Software Foundation; ////
692 
//// either version 2.1 of the License, or (at your option) any   ////
693 
//// later version.                                               ////
694 
////                                                              ////
695 
//// This source is distributed in the hope that it will be       ////
696 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
697 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
698 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
699 
//// details.                                                     ////
700 
////                                                              ////
701 
//// You should have received a copy of the GNU Lesser General    ////
702 
//// Public License along with this source; if not, download it   ////
703 
//// from http://www.opencores.org/lgpl.shtml                     ////
704 
////                                                              ////
705 
//////////////////////////////////////////////////////////////////////
706 
 
707 40 unneback 
`ifdef DFF
708 
`define MODULE dff
709 
module `BASE`MODULE ( d, q, clk, rst);
710 
`undef MODULE
711 6 unneback 
        parameter width = 1;
712 
        parameter reset_value = 0;
713 
 
714 
        input [width-1:0] d;
715 
        input clk, rst;
716 
        output reg [width-1:0] q;
717 
 
718 
        always @ (posedge clk or posedge rst)
719 
        if (rst)
720 
                q <= reset_value;
721 
        else
722 
                q <= d;
723 
 
724 
endmodule
725 40 unneback 
`endif
726 6 unneback 
 
727 40 unneback 
`ifdef DFF_ARRAY
728 
`define MODULE dff_array
729 
module `BASE`MODULE ( d, q, clk, rst);
730 
`undef MODULE
731 6 unneback 
 
732 
        parameter width = 1;
733 
        parameter depth = 2;
734 
        parameter reset_value = 1'b0;
735 
 
736 
        input [width-1:0] d;
737 
        input clk, rst;
738 
        output [width-1:0] q;
739 
        reg  [0:depth-1] q_tmp [width-1:0];
740 
        integer i;
741 
        always @ (posedge clk or posedge rst)
742 
        if (rst) begin
743 
            for (i=0;i<depth;i=i+1)
744 
                q_tmp[i] <= {width{reset_value}};
745 
        end else begin
746 
            q_tmp[0] <= d;
747 
            for (i=1;i<depth;i=i+1)
748 
                q_tmp[i] <= q_tmp[i-1];
749 
        end
750 
 
751 
    assign q = q_tmp[depth-1];
752 
 
753 
endmodule
754 40 unneback 
`endif
755 6 unneback 
 
756 40 unneback 
`ifdef DFF_CE
757 
`define MODULE dff_ce
758 
module `BASE`MODULE ( d, ce, q, clk, rst);
759 
`undef MODULE
760 6 unneback 
 
761 
        parameter width = 1;
762 
        parameter reset_value = 0;
763 
 
764 
        input [width-1:0] d;
765 
        input ce, clk, rst;
766 
        output reg [width-1:0] q;
767 
 
768 
        always @ (posedge clk or posedge rst)
769 
        if (rst)
770 
                q <= reset_value;
771 
        else
772 
                if (ce)
773 
                        q <= d;
774 
 
775 
endmodule
776 40 unneback 
`endif
777 6 unneback 
 
778 40 unneback 
`ifdef DFF_CE_CLEAR
779 
`define MODULE dff_ce_clear
780 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
781 
`undef MODULE
782 8 unneback 
 
783 
        parameter width = 1;
784 
        parameter reset_value = 0;
785 
 
786 
        input [width-1:0] d;
787 10 unneback 
        input ce, clear, clk, rst;
788 8 unneback 
        output reg [width-1:0] q;
789 
 
790 
        always @ (posedge clk or posedge rst)
791 
        if (rst)
792 
            q <= reset_value;
793 
        else
794 
            if (ce)
795 
                if (clear)
796 
                    q <= {width{1'b0}};
797 
                else
798 
                    q <= d;
799 
 
800 
endmodule
801 40 unneback 
`endif
802 8 unneback 
 
803 40 unneback 
`ifdef DF_CE_SET
804 
`define MODULE dff_ce_set
805 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
806 
`undef MODULE
807 24 unneback 
 
808 
        parameter width = 1;
809 
        parameter reset_value = 0;
810 
 
811 
        input [width-1:0] d;
812 
        input ce, set, clk, rst;
813 
        output reg [width-1:0] q;
814 
 
815 
        always @ (posedge clk or posedge rst)
816 
        if (rst)
817 
            q <= reset_value;
818 
        else
819 
            if (ce)
820 
                if (set)
821 
                    q <= {width{1'b1}};
822 
                else
823 
                    q <= d;
824 
 
825 
endmodule
826 40 unneback 
`endif
827 24 unneback 
 
828 40 unneback 
`ifdef SPR
829 
`define MODULE spr
830 
module `BASE`MODULE ( sp, r, q, clk, rst);
831 
`undef MODULE
832 
 
833 64 unneback 
        //parameter width = 1;
834 
        parameter reset_value = 1'b0;
835 29 unneback 
 
836 
        input sp, r;
837 
        output reg q;
838 
        input clk, rst;
839 
 
840 
        always @ (posedge clk or posedge rst)
841 
        if (rst)
842 
            q <= reset_value;
843 
        else
844 
            if (sp)
845 
                q <= 1'b1;
846 
            else if (r)
847 
                q <= 1'b0;
848 
 
849 
endmodule
850 40 unneback 
`endif
851 29 unneback 
 
852 40 unneback 
`ifdef SRP
853 
`define MODULE srp
854 
module `BASE`MODULE ( s, rp, q, clk, rst);
855 
`undef MODULE
856 
 
857 29 unneback 
        parameter width = 1;
858 
        parameter reset_value = 0;
859 
 
860 
        input s, rp;
861 
        output reg q;
862 
        input clk, rst;
863 
 
864 
        always @ (posedge clk or posedge rst)
865 
        if (rst)
866 
            q <= reset_value;
867 
        else
868 
            if (rp)
869 
                q <= 1'b0;
870 
            else if (s)
871 
                q <= 1'b1;
872 
 
873 
endmodule
874 40 unneback 
`endif
875 29 unneback 
 
876 40 unneback 
`ifdef ALTERA
877 29 unneback 
 
878 40 unneback 
`ifdef DFF_SR
879 6 unneback 
// megafunction wizard: %LPM_FF%
880 
// GENERATION: STANDARD
881 
// VERSION: WM1.0
882 
// MODULE: lpm_ff
883 
 
884 
// ============================================================
885 
// File Name: dff_sr.v
886 
// Megafunction Name(s):
887 
//                      lpm_ff
888 
//
889 
// Simulation Library Files(s):
890 
//                      lpm
891 
// ============================================================
892 
// ************************************************************
893 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
894 
//
895 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
896 
// ************************************************************
897 
 
898 
 
899 
//Copyright (C) 1991-2010 Altera Corporation
900 
//Your use of Altera Corporation's design tools, logic functions
901 
//and other software and tools, and its AMPP partner logic
902 
//functions, and any output files from any of the foregoing
903 
//(including device programming or simulation files), and any
904 
//associated documentation or information are expressly subject
905 
//to the terms and conditions of the Altera Program License
906 
//Subscription Agreement, Altera MegaCore Function License
907 
//Agreement, or other applicable license agreement, including,
908 
//without limitation, that your use is for the sole purpose of
909 
//programming logic devices manufactured by Altera and sold by
910 
//Altera or its authorized distributors.  Please refer to the
911 
//applicable agreement for further details.
912 
 
913 
 
914 
// synopsys translate_off
915 
`timescale 1 ps / 1 ps
916 
// synopsys translate_on
917 40 unneback 
`define MODULE dff_sr
918 
module `BASE`MODULE (
919 
`undef MODULE
920 
 
921 6 unneback 
        aclr,
922 
        aset,
923 
        clock,
924 
        data,
925 
        q);
926 
 
927 
        input     aclr;
928 
        input     aset;
929 
        input     clock;
930 
        input     data;
931 
        output    q;
932 
 
933 
        wire [0:0] sub_wire0;
934 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
935 
        wire  q = sub_wire1;
936 
        wire  sub_wire2 = data;
937 
        wire  sub_wire3 = sub_wire2;
938 
 
939 
        lpm_ff  lpm_ff_component (
940 
                                .aclr (aclr),
941 
                                .clock (clock),
942 
                                .data (sub_wire3),
943 
                                .aset (aset),
944 
                                .q (sub_wire0)
945 
                                // synopsys translate_off
946 
                                ,
947 
                                .aload (),
948 
                                .enable (),
949 
                                .sclr (),
950 
                                .sload (),
951 
                                .sset ()
952 
                                // synopsys translate_on
953 
                                );
954 
        defparam
955 
                lpm_ff_component.lpm_fftype = "DFF",
956 
                lpm_ff_component.lpm_type = "LPM_FF",
957 
                lpm_ff_component.lpm_width = 1;
958 
 
959 
 
960 
endmodule
961 
 
962 
// ============================================================
963 
// CNX file retrieval info
964 
// ============================================================
965 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
966 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
967 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
968 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
969 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
970 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
971 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
972 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
973 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
974 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
975 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
976 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
977 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
978 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
979 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
980 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
981 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
982 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
983 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
984 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
985 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
986 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
987 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
988 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
989 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
990 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
991 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
992 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
993 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
994 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
995 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
996 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
997 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
998 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
999 
// Retrieval info: LIB_FILE: lpm
1000 40 unneback 
`endif
1001 6 unneback 
 
1002 
`else
1003 
 
1004 40 unneback 
`ifdef DFF_SR
1005 
`define MODULE dff_sr
1006 
module `BASE`MODULE ( aclr, aset, clock, data, q);
1007 
`undef MODULE
1008 6 unneback 
 
1009 
    input         aclr;
1010 
    input         aset;
1011 
    input         clock;
1012 
    input         data;
1013 
    output reg    q;
1014 
 
1015 
   always @ (posedge clock or posedge aclr or posedge aset)
1016 
     if (aclr)
1017 
       q <= 1'b0;
1018 
     else if (aset)
1019 
       q <= 1'b1;
1020 
     else
1021 
       q <= data;
1022 
 
1023 
endmodule
1024 40 unneback 
`endif
1025 6 unneback 
 
1026 
`endif
1027 
 
1028 
// LATCH
1029 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1030 
`ifdef ALTERA
1031 40 unneback 
 
1032 
`ifdef LATCH
1033 
`define MODULE latch
1034 
module `BASE`MODULE ( d, le, q, clk);
1035 
`undef MODULE
1036 6 unneback 
input d, le;
1037 
output q;
1038 
input clk;
1039 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1040 
endmodule
1041 40 unneback 
`endif
1042 
 
1043 6 unneback 
`else
1044 40 unneback 
 
1045 
`ifdef LATCH
1046 
`define MODULE latch
1047 
module `BASE`MODULE ( d, le, q, clk);
1048 
`undef MODULE
1049 6 unneback 
input d, le;
1050 48 unneback 
input clk;
1051 
always @ (le or d)
1052 60 unneback 
if (le)
1053 48 unneback 
    d <= q;
1054 6 unneback 
endmodule
1055 15 unneback 
`endif
1056 
 
1057 40 unneback 
`endif
1058 
 
1059 
`ifdef SHREG
1060 
`define MODULE shreg
1061 
module `BASE`MODULE ( d, q, clk, rst);
1062 
`undef MODULE
1063 
 
1064 17 unneback 
parameter depth = 10;
1065 
input d;
1066 
output q;
1067 
input clk, rst;
1068 
 
1069 
reg [1:depth] dffs;
1070 
 
1071 
always @ (posedge clk or posedge rst)
1072 
if (rst)
1073 
    dffs <= {depth{1'b0}};
1074 
else
1075 
    dffs <= {d,dffs[1:depth-1]};
1076 
assign q = dffs[depth];
1077 
endmodule
1078 40 unneback 
`endif
1079 17 unneback 
 
1080 40 unneback 
`ifdef SHREG_CE
1081 
`define MODULE shreg_ce
1082 
module `BASE`MODULE ( d, ce, q, clk, rst);
1083 
`undef MODULE
1084 17 unneback 
parameter depth = 10;
1085 
input d, ce;
1086 
output q;
1087 
input clk, rst;
1088 
 
1089 
reg [1:depth] dffs;
1090 
 
1091 
always @ (posedge clk or posedge rst)
1092 
if (rst)
1093 
    dffs <= {depth{1'b0}};
1094 
else
1095 
    if (ce)
1096 
        dffs <= {d,dffs[1:depth-1]};
1097 
assign q = dffs[depth];
1098 
endmodule
1099 40 unneback 
`endif
1100 17 unneback 
 
1101 40 unneback 
`ifdef DELAY
1102 
`define MODULE delay
1103 
module `BASE`MODULE ( d, q, clk, rst);
1104 
`undef MODULE
1105 15 unneback 
parameter depth = 10;
1106 
input d;
1107 
output q;
1108 
input clk, rst;
1109 
 
1110 
reg [1:depth] dffs;
1111 
 
1112 
always @ (posedge clk or posedge rst)
1113 
if (rst)
1114 
    dffs <= {depth{1'b0}};
1115 
else
1116 
    dffs <= {d,dffs[1:depth-1]};
1117 
assign q = dffs[depth];
1118 17 unneback 
endmodule
1119 40 unneback 
`endif
1120 17 unneback 
 
1121 40 unneback 
`ifdef DELAY_EMPTYFLAG
1122 
`define MODULE delay_emptyflag
1123 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1124 40 unneback 
`undef MODULE
1125 17 unneback 
parameter depth = 10;
1126 
input d;
1127 
output q, emptyflag;
1128 
input clk, rst;
1129 
 
1130 
reg [1:depth] dffs;
1131 
 
1132 
always @ (posedge clk or posedge rst)
1133 
if (rst)
1134 
    dffs <= {depth{1'b0}};
1135 
else
1136 
    dffs <= {d,dffs[1:depth-1]};
1137 
assign q = dffs[depth];
1138 
assign emptyflag = !(|dffs);
1139 
endmodule
1140 40 unneback 
`endif
1141 17 unneback 
//////////////////////////////////////////////////////////////////////
1142 6 unneback 
////                                                              ////
1143 18 unneback 
////  Logic functions                                             ////
1144 
////                                                              ////
1145 
////  Description                                                 ////
1146 
////  Logic functions such as multiplexers                        ////
1147 
////                                                              ////
1148 
////                                                              ////
1149 
////  To Do:                                                      ////
1150 
////   -                                                          ////
1151 
////                                                              ////
1152 
////  Author(s):                                                  ////
1153 
////      - Michael Unneback, unneback@opencores.org              ////
1154 
////        ORSoC AB                                              ////
1155 
////                                                              ////
1156 
//////////////////////////////////////////////////////////////////////
1157 
////                                                              ////
1158 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1159 
////                                                              ////
1160 
//// This source file may be used and distributed without         ////
1161 
//// restriction provided that this copyright statement is not    ////
1162 
//// removed from the file and that any derivative work contains  ////
1163 
//// the original copyright notice and the associated disclaimer. ////
1164 
////                                                              ////
1165 
//// This source file is free software; you can redistribute it   ////
1166 
//// and/or modify it under the terms of the GNU Lesser General   ////
1167 
//// Public License as published by the Free Software Foundation; ////
1168 
//// either version 2.1 of the License, or (at your option) any   ////
1169 
//// later version.                                               ////
1170 
////                                                              ////
1171 
//// This source is distributed in the hope that it will be       ////
1172 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1173 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1174 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1175 
//// details.                                                     ////
1176 
////                                                              ////
1177 
//// You should have received a copy of the GNU Lesser General    ////
1178 
//// Public License along with this source; if not, download it   ////
1179 
//// from http://www.opencores.org/lgpl.shtml                     ////
1180 
////                                                              ////
1181 
//////////////////////////////////////////////////////////////////////
1182 40 unneback 
`ifdef MUX_ANDOR
1183 
`define MODULE mux_andor
1184 
module `BASE`MODULE ( a, sel, dout);
1185 
`undef MODULE
1186 36 unneback 
 
1187 
parameter width = 32;
1188 
parameter nr_of_ports = 4;
1189 
 
1190 
input [nr_of_ports*width-1:0] a;
1191 
input [nr_of_ports-1:0] sel;
1192 
output reg [width-1:0] dout;
1193 
 
1194 38 unneback 
integer i,j;
1195 
 
1196 36 unneback 
always @ (a, sel)
1197 
begin
1198 
    dout = a[width-1:0] & {width{sel[0]}};
1199 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1200 
        for (j=0;j<width;j=j+1)
1201 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1202 36 unneback 
end
1203 
 
1204 
endmodule
1205 40 unneback 
`endif
1206 36 unneback 
 
1207 40 unneback 
`ifdef MUX2_ANDOR
1208 
`define MODULE mux2_andor
1209 
module `BASE`MODULE ( a1, a0, sel, dout);
1210 
`undef MODULE
1211 18 unneback 
 
1212 34 unneback 
parameter width = 32;
1213 35 unneback 
localparam nr_of_ports = 2;
1214 34 unneback 
input [width-1:0] a1, a0;
1215 
input [nr_of_ports-1:0] sel;
1216 
output [width-1:0] dout;
1217 
 
1218 40 unneback 
`define MODULE mux_andor
1219 
`BASE`MODULE
1220 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1221 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1222 40 unneback 
`undef MODULE
1223 
 
1224 34 unneback 
endmodule
1225 40 unneback 
`endif
1226 34 unneback 
 
1227 40 unneback 
`ifdef MUX3_ANDOR
1228 
`define MODULE mux3_andor
1229 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1230 
`undef MODULE
1231 34 unneback 
 
1232 
parameter width = 32;
1233 35 unneback 
localparam nr_of_ports = 3;
1234 34 unneback 
input [width-1:0] a2, a1, a0;
1235 
input [nr_of_ports-1:0] sel;
1236 
output [width-1:0] dout;
1237 
 
1238 40 unneback 
`define MODULE mux_andor
1239 
`BASE`MODULE
1240 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1241 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1242 40 unneback 
`undef MODULE
1243 34 unneback 
endmodule
1244 40 unneback 
`endif
1245 34 unneback 
 
1246 40 unneback 
`ifdef MUX4_ANDOR
1247 
`define MODULE mux4_andor
1248 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1249 
`undef MODULE
1250 18 unneback 
 
1251 
parameter width = 32;
1252 35 unneback 
localparam nr_of_ports = 4;
1253 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1254 
input [nr_of_ports-1:0] sel;
1255 22 unneback 
output [width-1:0] dout;
1256 18 unneback 
 
1257 40 unneback 
`define MODULE mux_andor
1258 
`BASE`MODULE
1259 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1260 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1261 40 unneback 
`undef MODULE
1262 18 unneback 
 
1263 
endmodule
1264 40 unneback 
`endif
1265 18 unneback 
 
1266 40 unneback 
`ifdef MUX5_ANDOR
1267 
`define MODULE mux5_andor
1268 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1269 
`undef MODULE
1270 18 unneback 
 
1271 
parameter width = 32;
1272 35 unneback 
localparam nr_of_ports = 5;
1273 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1274 
input [nr_of_ports-1:0] sel;
1275 22 unneback 
output [width-1:0] dout;
1276 18 unneback 
 
1277 40 unneback 
`define MODULE mux_andor
1278 
`BASE`MODULE
1279 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1280 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1281 40 unneback 
`undef MODULE
1282 18 unneback 
 
1283 
endmodule
1284 40 unneback 
`endif
1285 18 unneback 
 
1286 40 unneback 
`ifdef MUX6_ANDOR
1287 
`define MODULE mux6_andor
1288 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1289 
`undef MODULE
1290 18 unneback 
 
1291 
parameter width = 32;
1292 35 unneback 
localparam nr_of_ports = 6;
1293 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1294 
input [nr_of_ports-1:0] sel;
1295 22 unneback 
output [width-1:0] dout;
1296 18 unneback 
 
1297 40 unneback 
`define MODULE mux_andor
1298 
`BASE`MODULE
1299 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1300 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1301 40 unneback 
`undef MODULE
1302 18 unneback 
 
1303 
endmodule
1304 40 unneback 
`endif
1305 43 unneback 
 
1306 
`ifdef PARITY
1307 
 
1308 
`define MODULE parity_generate
1309 
module `BASE`MODULE (data, parity);
1310 
`undef MODULE
1311 
parameter word_size = 32;
1312 
parameter chunk_size = 8;
1313 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1314 
input [word_size-1:0] data;
1315 
output reg [word_size/chunk_size-1:0] parity;
1316 
integer i,j;
1317 
always @ (data)
1318 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1319 
    parity[i] = parity_type;
1320 
    for (j=0;j<chunk_size;j=j+1) begin
1321 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1322 43 unneback 
    end
1323 
end
1324 
endmodule
1325 
 
1326 
`define MODULE parity_check
1327 
module `BASE`MODULE( data, parity, parity_error);
1328 
`undef MODULE
1329 
parameter word_size = 32;
1330 
parameter chunk_size = 8;
1331 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1332 
input [word_size-1:0] data;
1333 
input [word_size/chunk_size-1:0] parity;
1334 
output parity_error;
1335 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1336 43 unneback 
integer i,j;
1337 
always @ (data or parity)
1338 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1339 
    error_flag[i] = parity[i] ^ parity_type;
1340 
    for (j=0;j<chunk_size;j=j+1) begin
1341 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1342 43 unneback 
    end
1343 
end
1344 
assign parity_error = |error_flag;
1345 
endmodule
1346 
 
1347 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1348 
////                                                              ////
1349 
////  IO functions                                                ////
1350 
////                                                              ////
1351 
////  Description                                                 ////
1352 
////  IO functions such as IOB flip-flops                         ////
1353 
////                                                              ////
1354 
////                                                              ////
1355 
////  To Do:                                                      ////
1356 
////   -                                                          ////
1357 
////                                                              ////
1358 
////  Author(s):                                                  ////
1359 
////      - Michael Unneback, unneback@opencores.org              ////
1360 
////        ORSoC AB                                              ////
1361 
////                                                              ////
1362 18 unneback 
//////////////////////////////////////////////////////////////////////
1363 
////                                                              ////
1364 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1365 
////                                                              ////
1366 
//// This source file may be used and distributed without         ////
1367 
//// restriction provided that this copyright statement is not    ////
1368 
//// removed from the file and that any derivative work contains  ////
1369 
//// the original copyright notice and the associated disclaimer. ////
1370 
////                                                              ////
1371 
//// This source file is free software; you can redistribute it   ////
1372 
//// and/or modify it under the terms of the GNU Lesser General   ////
1373 
//// Public License as published by the Free Software Foundation; ////
1374 
//// either version 2.1 of the License, or (at your option) any   ////
1375 
//// later version.                                               ////
1376 
////                                                              ////
1377 
//// This source is distributed in the hope that it will be       ////
1378 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1379 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1380 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1381 
//// details.                                                     ////
1382 
////                                                              ////
1383 
//// You should have received a copy of the GNU Lesser General    ////
1384 
//// Public License along with this source; if not, download it   ////
1385 
//// from http://www.opencores.org/lgpl.shtml                     ////
1386 
////                                                              ////
1387 
//////////////////////////////////////////////////////////////////////
1388 45 unneback 
`timescale 1ns/1ns
1389 44 unneback 
`ifdef O_DFF
1390 
`define MODULE o_dff
1391 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1392 
`undef MODULE
1393 
parameter width = 1;
1394 45 unneback 
parameter reset_value = {width{1'b0}};
1395 
input  [width-1:0]  d_i;
1396 44 unneback 
output [width-1:0] o_pad;
1397 
input clk, rst;
1398 
wire [width-1:0] d_i_int `SYN_KEEP;
1399 45 unneback 
reg  [width-1:0] o_pad_int;
1400 44 unneback 
assign d_i_int = d_i;
1401 
genvar i;
1402 45 unneback 
generate
1403 44 unneback 
for (i=0;i<width;i=i+1) begin
1404 
    always @ (posedge clk or posedge rst)
1405 
    if (rst)
1406 45 unneback 
        o_pad_int[i] <= reset_value[i];
1407 44 unneback 
    else
1408 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1409 
    assign #1 o_pad[i] = o_pad_int[i];
1410 44 unneback 
end
1411 
endgenerate
1412 
endmodule
1413 
`endif
1414 
 
1415 45 unneback 
`timescale 1ns/1ns
1416 44 unneback 
`ifdef IO_DFF_OE
1417 
`define MODULE io_dff_oe
1418 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1419 
`undef MODULE
1420 
parameter width = 1;
1421 
input  [width-1:0] d_o;
1422 
output reg [width-1:0] d_i;
1423 
input oe;
1424 
inout [width-1:0] io_pad;
1425 
input clk, rst;
1426 
wire [width-1:0] oe_d `SYN_KEEP;
1427 
reg [width-1:0] oe_q;
1428 
reg [width-1:0] d_o_q;
1429 
assign oe_d = {width{oe}};
1430 
genvar i;
1431 
generate
1432 
for (i=0;i<width;i=i+1) begin
1433 
    always @ (posedge clk or posedge rst)
1434 
    if (rst)
1435 
        oe_q[i] <= 1'b0;
1436 
    else
1437 
        oe_q[i] <= oe_d[i];
1438 
    always @ (posedge clk or posedge rst)
1439 
    if (rst)
1440 
        d_o_q[i] <= 1'b0;
1441 
    else
1442 
        d_o_q[i] <= d_o[i];
1443 
    always @ (posedge clk or posedge rst)
1444 
    if (rst)
1445 
        d_i[i] <= 1'b0;
1446 
    else
1447 
        d_i[i] <= io_pad[i];
1448 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1449 44 unneback 
end
1450 
endgenerate
1451 
endmodule
1452 
`endif
1453 
`ifdef CNT_BIN
1454 
//////////////////////////////////////////////////////////////////////
1455 
////                                                              ////
1456 6 unneback 
////  Versatile counter                                           ////
1457 
////                                                              ////
1458 
////  Description                                                 ////
1459 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1460 
////  counter                                                     ////
1461 
////                                                              ////
1462 
////  To Do:                                                      ////
1463 
////   - add LFSR with more taps                                  ////
1464 
////                                                              ////
1465 
////  Author(s):                                                  ////
1466 
////      - Michael Unneback, unneback@opencores.org              ////
1467 
////        ORSoC AB                                              ////
1468 
////                                                              ////
1469 
//////////////////////////////////////////////////////////////////////
1470 
////                                                              ////
1471 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1472 
////                                                              ////
1473 
//// This source file may be used and distributed without         ////
1474 
//// restriction provided that this copyright statement is not    ////
1475 
//// removed from the file and that any derivative work contains  ////
1476 
//// the original copyright notice and the associated disclaimer. ////
1477 
////                                                              ////
1478 
//// This source file is free software; you can redistribute it   ////
1479 
//// and/or modify it under the terms of the GNU Lesser General   ////
1480 
//// Public License as published by the Free Software Foundation; ////
1481 
//// either version 2.1 of the License, or (at your option) any   ////
1482 
//// later version.                                               ////
1483 
////                                                              ////
1484 
//// This source is distributed in the hope that it will be       ////
1485 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1486 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1487 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1488 
//// details.                                                     ////
1489 
////                                                              ////
1490 
//// You should have received a copy of the GNU Lesser General    ////
1491 
//// Public License along with this source; if not, download it   ////
1492 
//// from http://www.opencores.org/lgpl.shtml                     ////
1493 
////                                                              ////
1494 
//////////////////////////////////////////////////////////////////////
1495 
 
1496 
// binary counter
1497 22 unneback 
 
1498 40 unneback 
`define MODULE cnt_bin
1499 
module `BASE`MODULE (
1500 
`undef MODULE
1501 
 q, rst, clk);
1502 
 
1503 22 unneback 
   parameter length = 4;
1504 
   output [length:1] q;
1505 
   input rst;
1506 
   input clk;
1507 
 
1508 
   parameter clear_value = 0;
1509 
   parameter set_value = 1;
1510 
   parameter wrap_value = 0;
1511 
   parameter level1_value = 15;
1512 
 
1513 
   reg  [length:1] qi;
1514 
   wire [length:1] q_next;
1515 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1516 
 
1517 
   always @ (posedge clk or posedge rst)
1518 
     if (rst)
1519 
       qi <= {length{1'b0}};
1520 
     else
1521 
       qi <= q_next;
1522 
 
1523 
   assign q = qi;
1524 
 
1525 
endmodule
1526 40 unneback 
`endif
1527 
`ifdef CNT_BIN_CLEAR
1528 22 unneback 
//////////////////////////////////////////////////////////////////////
1529 
////                                                              ////
1530 
////  Versatile counter                                           ////
1531 
////                                                              ////
1532 
////  Description                                                 ////
1533 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1534 
////  counter                                                     ////
1535 
////                                                              ////
1536 
////  To Do:                                                      ////
1537 
////   - add LFSR with more taps                                  ////
1538 
////                                                              ////
1539 
////  Author(s):                                                  ////
1540 
////      - Michael Unneback, unneback@opencores.org              ////
1541 
////        ORSoC AB                                              ////
1542 
////                                                              ////
1543 
//////////////////////////////////////////////////////////////////////
1544 
////                                                              ////
1545 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1546 
////                                                              ////
1547 
//// This source file may be used and distributed without         ////
1548 
//// restriction provided that this copyright statement is not    ////
1549 
//// removed from the file and that any derivative work contains  ////
1550 
//// the original copyright notice and the associated disclaimer. ////
1551 
////                                                              ////
1552 
//// This source file is free software; you can redistribute it   ////
1553 
//// and/or modify it under the terms of the GNU Lesser General   ////
1554 
//// Public License as published by the Free Software Foundation; ////
1555 
//// either version 2.1 of the License, or (at your option) any   ////
1556 
//// later version.                                               ////
1557 
////                                                              ////
1558 
//// This source is distributed in the hope that it will be       ////
1559 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1560 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1561 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1562 
//// details.                                                     ////
1563 
////                                                              ////
1564 
//// You should have received a copy of the GNU Lesser General    ////
1565 
//// Public License along with this source; if not, download it   ////
1566 
//// from http://www.opencores.org/lgpl.shtml                     ////
1567 
////                                                              ////
1568 
//////////////////////////////////////////////////////////////////////
1569 
 
1570 
// binary counter
1571 
 
1572 40 unneback 
`define MODULE cnt_bin_clear
1573 
module `BASE`MODULE (
1574 
`undef MODULE
1575 
 clear, q, rst, clk);
1576 
 
1577 22 unneback 
   parameter length = 4;
1578 
   input clear;
1579 
   output [length:1] q;
1580 
   input rst;
1581 
   input clk;
1582 
 
1583 
   parameter clear_value = 0;
1584 
   parameter set_value = 1;
1585 
   parameter wrap_value = 0;
1586 
   parameter level1_value = 15;
1587 
 
1588 
   reg  [length:1] qi;
1589 
   wire [length:1] q_next;
1590 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1591 
 
1592 
   always @ (posedge clk or posedge rst)
1593 
     if (rst)
1594 
       qi <= {length{1'b0}};
1595 
     else
1596 
       qi <= q_next;
1597 
 
1598 
   assign q = qi;
1599 
 
1600 
endmodule
1601 40 unneback 
`endif
1602 
`ifdef CNT_BIN_CE
1603 22 unneback 
//////////////////////////////////////////////////////////////////////
1604 
////                                                              ////
1605 
////  Versatile counter                                           ////
1606 
////                                                              ////
1607 
////  Description                                                 ////
1608 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1609 
////  counter                                                     ////
1610 
////                                                              ////
1611 
////  To Do:                                                      ////
1612 
////   - add LFSR with more taps                                  ////
1613 
////                                                              ////
1614 
////  Author(s):                                                  ////
1615 
////      - Michael Unneback, unneback@opencores.org              ////
1616 
////        ORSoC AB                                              ////
1617 
////                                                              ////
1618 
//////////////////////////////////////////////////////////////////////
1619 
////                                                              ////
1620 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1621 
////                                                              ////
1622 
//// This source file may be used and distributed without         ////
1623 
//// restriction provided that this copyright statement is not    ////
1624 
//// removed from the file and that any derivative work contains  ////
1625 
//// the original copyright notice and the associated disclaimer. ////
1626 
////                                                              ////
1627 
//// This source file is free software; you can redistribute it   ////
1628 
//// and/or modify it under the terms of the GNU Lesser General   ////
1629 
//// Public License as published by the Free Software Foundation; ////
1630 
//// either version 2.1 of the License, or (at your option) any   ////
1631 
//// later version.                                               ////
1632 
////                                                              ////
1633 
//// This source is distributed in the hope that it will be       ////
1634 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1635 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1636 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1637 
//// details.                                                     ////
1638 
////                                                              ////
1639 
//// You should have received a copy of the GNU Lesser General    ////
1640 
//// Public License along with this source; if not, download it   ////
1641 
//// from http://www.opencores.org/lgpl.shtml                     ////
1642 
////                                                              ////
1643 
//////////////////////////////////////////////////////////////////////
1644 
 
1645 
// binary counter
1646 6 unneback 
 
1647 40 unneback 
`define MODULE cnt_bin_ce
1648 
module `BASE`MODULE (
1649 
`undef MODULE
1650 
 cke, q, rst, clk);
1651 
 
1652 6 unneback 
   parameter length = 4;
1653 
   input cke;
1654 
   output [length:1] q;
1655 
   input rst;
1656 
   input clk;
1657 
 
1658 
   parameter clear_value = 0;
1659 
   parameter set_value = 1;
1660 
   parameter wrap_value = 0;
1661 
   parameter level1_value = 15;
1662 
 
1663 
   reg  [length:1] qi;
1664 
   wire [length:1] q_next;
1665 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1666 
 
1667 
   always @ (posedge clk or posedge rst)
1668 
     if (rst)
1669 
       qi <= {length{1'b0}};
1670 
     else
1671 
     if (cke)
1672 
       qi <= q_next;
1673 
 
1674 
   assign q = qi;
1675 
 
1676 
endmodule
1677 40 unneback 
`endif
1678 
`ifdef CNT_BIN_CE_CLEAR
1679 6 unneback 
//////////////////////////////////////////////////////////////////////
1680 
////                                                              ////
1681 
////  Versatile counter                                           ////
1682 
////                                                              ////
1683 
////  Description                                                 ////
1684 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1685 
////  counter                                                     ////
1686 
////                                                              ////
1687 
////  To Do:                                                      ////
1688 
////   - add LFSR with more taps                                  ////
1689 
////                                                              ////
1690 
////  Author(s):                                                  ////
1691 
////      - Michael Unneback, unneback@opencores.org              ////
1692 
////        ORSoC AB                                              ////
1693 
////                                                              ////
1694 
//////////////////////////////////////////////////////////////////////
1695 
////                                                              ////
1696 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1697 
////                                                              ////
1698 
//// This source file may be used and distributed without         ////
1699 
//// restriction provided that this copyright statement is not    ////
1700 
//// removed from the file and that any derivative work contains  ////
1701 
//// the original copyright notice and the associated disclaimer. ////
1702 
////                                                              ////
1703 
//// This source file is free software; you can redistribute it   ////
1704 
//// and/or modify it under the terms of the GNU Lesser General   ////
1705 
//// Public License as published by the Free Software Foundation; ////
1706 
//// either version 2.1 of the License, or (at your option) any   ////
1707 
//// later version.                                               ////
1708 
////                                                              ////
1709 
//// This source is distributed in the hope that it will be       ////
1710 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1711 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1712 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1713 
//// details.                                                     ////
1714 
////                                                              ////
1715 
//// You should have received a copy of the GNU Lesser General    ////
1716 
//// Public License along with this source; if not, download it   ////
1717 
//// from http://www.opencores.org/lgpl.shtml                     ////
1718 
////                                                              ////
1719 
//////////////////////////////////////////////////////////////////////
1720 
 
1721 
// binary counter
1722 
 
1723 40 unneback 
`define MODULE cnt_bin_ce_clear
1724 
module `BASE`MODULE (
1725 
`undef MODULE
1726 
 clear, cke, q, rst, clk);
1727 
 
1728 6 unneback 
   parameter length = 4;
1729 
   input clear;
1730 
   input cke;
1731 
   output [length:1] q;
1732 
   input rst;
1733 
   input clk;
1734 
 
1735 
   parameter clear_value = 0;
1736 
   parameter set_value = 1;
1737 
   parameter wrap_value = 0;
1738 
   parameter level1_value = 15;
1739 
 
1740 
   reg  [length:1] qi;
1741 
   wire [length:1] q_next;
1742 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1743 
 
1744 
   always @ (posedge clk or posedge rst)
1745 
     if (rst)
1746 
       qi <= {length{1'b0}};
1747 
     else
1748 
     if (cke)
1749 
       qi <= q_next;
1750 
 
1751 
   assign q = qi;
1752 
 
1753 
endmodule
1754 40 unneback 
`endif
1755 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1756 6 unneback 
//////////////////////////////////////////////////////////////////////
1757 
////                                                              ////
1758 
////  Versatile counter                                           ////
1759 
////                                                              ////
1760 
////  Description                                                 ////
1761 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1762 
////  counter                                                     ////
1763 
////                                                              ////
1764 
////  To Do:                                                      ////
1765 
////   - add LFSR with more taps                                  ////
1766 
////                                                              ////
1767 
////  Author(s):                                                  ////
1768 
////      - Michael Unneback, unneback@opencores.org              ////
1769 
////        ORSoC AB                                              ////
1770 
////                                                              ////
1771 
//////////////////////////////////////////////////////////////////////
1772 
////                                                              ////
1773 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1774 
////                                                              ////
1775 
//// This source file may be used and distributed without         ////
1776 
//// restriction provided that this copyright statement is not    ////
1777 
//// removed from the file and that any derivative work contains  ////
1778 
//// the original copyright notice and the associated disclaimer. ////
1779 
////                                                              ////
1780 
//// This source file is free software; you can redistribute it   ////
1781 
//// and/or modify it under the terms of the GNU Lesser General   ////
1782 
//// Public License as published by the Free Software Foundation; ////
1783 
//// either version 2.1 of the License, or (at your option) any   ////
1784 
//// later version.                                               ////
1785 
////                                                              ////
1786 
//// This source is distributed in the hope that it will be       ////
1787 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1788 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1789 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1790 
//// details.                                                     ////
1791 
////                                                              ////
1792 
//// You should have received a copy of the GNU Lesser General    ////
1793 
//// Public License along with this source; if not, download it   ////
1794 
//// from http://www.opencores.org/lgpl.shtml                     ////
1795 
////                                                              ////
1796 
//////////////////////////////////////////////////////////////////////
1797 
 
1798 
// binary counter
1799 29 unneback 
 
1800 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1801 
module `BASE`MODULE (
1802 
`undef MODULE
1803 
 clear, cke, q, level1, level2, rst, clk);
1804 
 
1805 29 unneback 
   parameter length = 4;
1806 
   input clear;
1807 
   input cke;
1808 
   output [length:1] q;
1809 
   output reg level1;
1810 
   output reg level2;
1811 
   input rst;
1812 
   input clk;
1813 
 
1814 
   parameter clear_value = 0;
1815 
   parameter set_value = 1;
1816 30 unneback 
   parameter wrap_value = 15;
1817 
   parameter level1_value = 8;
1818 
   parameter level2_value = 15;
1819 29 unneback 
 
1820 
   wire rew;
1821 30 unneback 
   assign rew = 1'b0;
1822 29 unneback 
   reg  [length:1] qi;
1823 
   wire [length:1] q_next;
1824 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1825 
 
1826 
   always @ (posedge clk or posedge rst)
1827 
     if (rst)
1828 
       qi <= {length{1'b0}};
1829 
     else
1830 
     if (cke)
1831 
       qi <= q_next;
1832 
 
1833 
   assign q = qi;
1834 
 
1835 
 
1836 
    always @ (posedge clk or posedge rst)
1837 
    if (rst)
1838 
        level1 <= 1'b0;
1839 
    else
1840 
    if (cke)
1841 
    if (clear)
1842 
        level1 <= 1'b0;
1843 
    else if (q_next == level1_value)
1844 
        level1 <= 1'b1;
1845 
    else if (qi == level1_value & rew)
1846 
        level1 <= 1'b0;
1847 
 
1848 
    always @ (posedge clk or posedge rst)
1849 
    if (rst)
1850 
        level2 <= 1'b0;
1851 
    else
1852 
    if (cke)
1853 
    if (clear)
1854 
        level2 <= 1'b0;
1855 
    else if (q_next == level2_value)
1856 
        level2 <= 1'b1;
1857 
    else if (qi == level2_value & rew)
1858 
        level2 <= 1'b0;
1859 
endmodule
1860 40 unneback 
`endif
1861 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1862 29 unneback 
//////////////////////////////////////////////////////////////////////
1863 
////                                                              ////
1864 
////  Versatile counter                                           ////
1865 
////                                                              ////
1866 
////  Description                                                 ////
1867 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1868 
////  counter                                                     ////
1869 
////                                                              ////
1870 
////  To Do:                                                      ////
1871 
////   - add LFSR with more taps                                  ////
1872 
////                                                              ////
1873 
////  Author(s):                                                  ////
1874 
////      - Michael Unneback, unneback@opencores.org              ////
1875 
////        ORSoC AB                                              ////
1876 
////                                                              ////
1877 
//////////////////////////////////////////////////////////////////////
1878 
////                                                              ////
1879 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1880 
////                                                              ////
1881 
//// This source file may be used and distributed without         ////
1882 
//// restriction provided that this copyright statement is not    ////
1883 
//// removed from the file and that any derivative work contains  ////
1884 
//// the original copyright notice and the associated disclaimer. ////
1885 
////                                                              ////
1886 
//// This source file is free software; you can redistribute it   ////
1887 
//// and/or modify it under the terms of the GNU Lesser General   ////
1888 
//// Public License as published by the Free Software Foundation; ////
1889 
//// either version 2.1 of the License, or (at your option) any   ////
1890 
//// later version.                                               ////
1891 
////                                                              ////
1892 
//// This source is distributed in the hope that it will be       ////
1893 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1894 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1895 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1896 
//// details.                                                     ////
1897 
////                                                              ////
1898 
//// You should have received a copy of the GNU Lesser General    ////
1899 
//// Public License along with this source; if not, download it   ////
1900 
//// from http://www.opencores.org/lgpl.shtml                     ////
1901 
////                                                              ////
1902 
//////////////////////////////////////////////////////////////////////
1903 
 
1904 
// binary counter
1905 6 unneback 
 
1906 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
1907 
module `BASE`MODULE (
1908 
`undef MODULE
1909 
 clear, set, cke, rew, q, rst, clk);
1910 
 
1911 6 unneback 
   parameter length = 4;
1912 
   input clear;
1913 
   input set;
1914 
   input cke;
1915 
   input rew;
1916 
   output [length:1] q;
1917 
   input rst;
1918 
   input clk;
1919 
 
1920 
   parameter clear_value = 0;
1921 
   parameter set_value = 1;
1922 
   parameter wrap_value = 0;
1923 
   parameter level1_value = 15;
1924 
 
1925 
   reg  [length:1] qi;
1926 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1927 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1928 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1929 
   assign q_next = rew ? q_next_rew : q_next_fw;
1930 
 
1931 
   always @ (posedge clk or posedge rst)
1932 
     if (rst)
1933 
       qi <= {length{1'b0}};
1934 
     else
1935 
     if (cke)
1936 
       qi <= q_next;
1937 
 
1938 
   assign q = qi;
1939 
 
1940 
endmodule
1941 40 unneback 
`endif
1942 
`ifdef CNT_BIN_CE_REW_L1
1943 6 unneback 
//////////////////////////////////////////////////////////////////////
1944 
////                                                              ////
1945 
////  Versatile counter                                           ////
1946 
////                                                              ////
1947 
////  Description                                                 ////
1948 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1949 
////  counter                                                     ////
1950 
////                                                              ////
1951 
////  To Do:                                                      ////
1952 
////   - add LFSR with more taps                                  ////
1953 
////                                                              ////
1954 
////  Author(s):                                                  ////
1955 
////      - Michael Unneback, unneback@opencores.org              ////
1956 
////        ORSoC AB                                              ////
1957 
////                                                              ////
1958 
//////////////////////////////////////////////////////////////////////
1959 
////                                                              ////
1960 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1961 
////                                                              ////
1962 
//// This source file may be used and distributed without         ////
1963 
//// restriction provided that this copyright statement is not    ////
1964 
//// removed from the file and that any derivative work contains  ////
1965 
//// the original copyright notice and the associated disclaimer. ////
1966 
////                                                              ////
1967 
//// This source file is free software; you can redistribute it   ////
1968 
//// and/or modify it under the terms of the GNU Lesser General   ////
1969 
//// Public License as published by the Free Software Foundation; ////
1970 
//// either version 2.1 of the License, or (at your option) any   ////
1971 
//// later version.                                               ////
1972 
////                                                              ////
1973 
//// This source is distributed in the hope that it will be       ////
1974 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1975 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1976 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1977 
//// details.                                                     ////
1978 
////                                                              ////
1979 
//// You should have received a copy of the GNU Lesser General    ////
1980 
//// Public License along with this source; if not, download it   ////
1981 
//// from http://www.opencores.org/lgpl.shtml                     ////
1982 
////                                                              ////
1983 
//////////////////////////////////////////////////////////////////////
1984 
 
1985 
// binary counter
1986 
 
1987 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
1988 
module `BASE`MODULE (
1989 
`undef MODULE
1990 
 cke, rew, level1, rst, clk);
1991 
 
1992 6 unneback 
   parameter length = 4;
1993 
   input cke;
1994 
   input rew;
1995 
   output reg level1;
1996 
   input rst;
1997 
   input clk;
1998 
 
1999 
   parameter clear_value = 0;
2000 
   parameter set_value = 1;
2001 
   parameter wrap_value = 1;
2002 
   parameter level1_value = 15;
2003 
 
2004 29 unneback 
   wire clear;
2005 30 unneback 
   assign clear = 1'b0;
2006 6 unneback 
   reg  [length:1] qi;
2007 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2008 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2009 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2010 
   assign q_next = rew ? q_next_rew : q_next_fw;
2011 
 
2012 
   always @ (posedge clk or posedge rst)
2013 
     if (rst)
2014 
       qi <= {length{1'b0}};
2015 
     else
2016 
     if (cke)
2017 
       qi <= q_next;
2018 
 
2019 
 
2020 
 
2021 
    always @ (posedge clk or posedge rst)
2022 
    if (rst)
2023 
        level1 <= 1'b0;
2024 
    else
2025 
    if (cke)
2026 29 unneback 
    if (clear)
2027 
        level1 <= 1'b0;
2028 
    else if (q_next == level1_value)
2029 6 unneback 
        level1 <= 1'b1;
2030 
    else if (qi == level1_value & rew)
2031 
        level1 <= 1'b0;
2032 
endmodule
2033 40 unneback 
`endif
2034 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2035 6 unneback 
//////////////////////////////////////////////////////////////////////
2036 
////                                                              ////
2037 
////  Versatile counter                                           ////
2038 
////                                                              ////
2039 
////  Description                                                 ////
2040 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2041 
////  counter                                                     ////
2042 
////                                                              ////
2043 
////  To Do:                                                      ////
2044 
////   - add LFSR with more taps                                  ////
2045 
////                                                              ////
2046 
////  Author(s):                                                  ////
2047 
////      - Michael Unneback, unneback@opencores.org              ////
2048 
////        ORSoC AB                                              ////
2049 
////                                                              ////
2050 
//////////////////////////////////////////////////////////////////////
2051 
////                                                              ////
2052 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2053 
////                                                              ////
2054 
//// This source file may be used and distributed without         ////
2055 
//// restriction provided that this copyright statement is not    ////
2056 
//// removed from the file and that any derivative work contains  ////
2057 
//// the original copyright notice and the associated disclaimer. ////
2058 
////                                                              ////
2059 
//// This source file is free software; you can redistribute it   ////
2060 
//// and/or modify it under the terms of the GNU Lesser General   ////
2061 
//// Public License as published by the Free Software Foundation; ////
2062 
//// either version 2.1 of the License, or (at your option) any   ////
2063 
//// later version.                                               ////
2064 
////                                                              ////
2065 
//// This source is distributed in the hope that it will be       ////
2066 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2067 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2068 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2069 
//// details.                                                     ////
2070 
////                                                              ////
2071 
//// You should have received a copy of the GNU Lesser General    ////
2072 
//// Public License along with this source; if not, download it   ////
2073 
//// from http://www.opencores.org/lgpl.shtml                     ////
2074 
////                                                              ////
2075 
//////////////////////////////////////////////////////////////////////
2076 
 
2077 25 unneback 
// binary counter
2078 
 
2079 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2080 
module `BASE`MODULE (
2081 
`undef MODULE
2082 
 cke, rew, zq, level1, rst, clk);
2083 
 
2084 25 unneback 
   parameter length = 4;
2085 
   input cke;
2086 
   input rew;
2087 
   output reg zq;
2088 
   output reg level1;
2089 
   input rst;
2090 
   input clk;
2091 
 
2092 
   parameter clear_value = 0;
2093 
   parameter set_value = 1;
2094 
   parameter wrap_value = 1;
2095 
   parameter level1_value = 15;
2096 
 
2097 29 unneback 
   wire clear;
2098 30 unneback 
   assign clear = 1'b0;
2099 25 unneback 
   reg  [length:1] qi;
2100 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2101 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2102 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2103 
   assign q_next = rew ? q_next_rew : q_next_fw;
2104 
 
2105 
   always @ (posedge clk or posedge rst)
2106 
     if (rst)
2107 
       qi <= {length{1'b0}};
2108 
     else
2109 
     if (cke)
2110 
       qi <= q_next;
2111 
 
2112 
 
2113 
 
2114 
   always @ (posedge clk or posedge rst)
2115 
     if (rst)
2116 
       zq <= 1'b1;
2117 
     else
2118 
     if (cke)
2119 
       zq <= q_next == {length{1'b0}};
2120 
 
2121 
    always @ (posedge clk or posedge rst)
2122 
    if (rst)
2123 
        level1 <= 1'b0;
2124 
    else
2125 
    if (cke)
2126 29 unneback 
    if (clear)
2127 
        level1 <= 1'b0;
2128 
    else if (q_next == level1_value)
2129 25 unneback 
        level1 <= 1'b1;
2130 
    else if (qi == level1_value & rew)
2131 
        level1 <= 1'b0;
2132 
endmodule
2133 40 unneback 
`endif
2134 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2135 25 unneback 
//////////////////////////////////////////////////////////////////////
2136 
////                                                              ////
2137 
////  Versatile counter                                           ////
2138 
////                                                              ////
2139 
////  Description                                                 ////
2140 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2141 
////  counter                                                     ////
2142 
////                                                              ////
2143 
////  To Do:                                                      ////
2144 
////   - add LFSR with more taps                                  ////
2145 
////                                                              ////
2146 
////  Author(s):                                                  ////
2147 
////      - Michael Unneback, unneback@opencores.org              ////
2148 
////        ORSoC AB                                              ////
2149 
////                                                              ////
2150 
//////////////////////////////////////////////////////////////////////
2151 
////                                                              ////
2152 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2153 
////                                                              ////
2154 
//// This source file may be used and distributed without         ////
2155 
//// restriction provided that this copyright statement is not    ////
2156 
//// removed from the file and that any derivative work contains  ////
2157 
//// the original copyright notice and the associated disclaimer. ////
2158 
////                                                              ////
2159 
//// This source file is free software; you can redistribute it   ////
2160 
//// and/or modify it under the terms of the GNU Lesser General   ////
2161 
//// Public License as published by the Free Software Foundation; ////
2162 
//// either version 2.1 of the License, or (at your option) any   ////
2163 
//// later version.                                               ////
2164 
////                                                              ////
2165 
//// This source is distributed in the hope that it will be       ////
2166 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2167 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2168 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2169 
//// details.                                                     ////
2170 
////                                                              ////
2171 
//// You should have received a copy of the GNU Lesser General    ////
2172 
//// Public License along with this source; if not, download it   ////
2173 
//// from http://www.opencores.org/lgpl.shtml                     ////
2174 
////                                                              ////
2175 
//////////////////////////////////////////////////////////////////////
2176 
 
2177 
// binary counter
2178 
 
2179 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2180 
module `BASE`MODULE (
2181 
`undef MODULE
2182 
 cke, rew, q, zq, level1, rst, clk);
2183 
 
2184 25 unneback 
   parameter length = 4;
2185 
   input cke;
2186 
   input rew;
2187 
   output [length:1] q;
2188 
   output reg zq;
2189 
   output reg level1;
2190 
   input rst;
2191 
   input clk;
2192 
 
2193 
   parameter clear_value = 0;
2194 
   parameter set_value = 1;
2195 
   parameter wrap_value = 1;
2196 
   parameter level1_value = 15;
2197 
 
2198 29 unneback 
   wire clear;
2199 30 unneback 
   assign clear = 1'b0;
2200 25 unneback 
   reg  [length:1] qi;
2201 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2202 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2203 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2204 
   assign q_next = rew ? q_next_rew : q_next_fw;
2205 
 
2206 
   always @ (posedge clk or posedge rst)
2207 
     if (rst)
2208 
       qi <= {length{1'b0}};
2209 
     else
2210 
     if (cke)
2211 
       qi <= q_next;
2212 
 
2213 
   assign q = qi;
2214 
 
2215 
 
2216 
   always @ (posedge clk or posedge rst)
2217 
     if (rst)
2218 
       zq <= 1'b1;
2219 
     else
2220 
     if (cke)
2221 
       zq <= q_next == {length{1'b0}};
2222 
 
2223 
    always @ (posedge clk or posedge rst)
2224 
    if (rst)
2225 
        level1 <= 1'b0;
2226 
    else
2227 
    if (cke)
2228 29 unneback 
    if (clear)
2229 
        level1 <= 1'b0;
2230 
    else if (q_next == level1_value)
2231 25 unneback 
        level1 <= 1'b1;
2232 
    else if (qi == level1_value & rew)
2233 
        level1 <= 1'b0;
2234 
endmodule
2235 40 unneback 
`endif
2236 
`ifdef CNT_LFSR_ZQ
2237 25 unneback 
//////////////////////////////////////////////////////////////////////
2238 
////                                                              ////
2239 
////  Versatile counter                                           ////
2240 
////                                                              ////
2241 
////  Description                                                 ////
2242 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2243 
////  counter                                                     ////
2244 
////                                                              ////
2245 
////  To Do:                                                      ////
2246 
////   - add LFSR with more taps                                  ////
2247 
////                                                              ////
2248 
////  Author(s):                                                  ////
2249 
////      - Michael Unneback, unneback@opencores.org              ////
2250 
////        ORSoC AB                                              ////
2251 
////                                                              ////
2252 
//////////////////////////////////////////////////////////////////////
2253 
////                                                              ////
2254 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2255 
////                                                              ////
2256 
//// This source file may be used and distributed without         ////
2257 
//// restriction provided that this copyright statement is not    ////
2258 
//// removed from the file and that any derivative work contains  ////
2259 
//// the original copyright notice and the associated disclaimer. ////
2260 
////                                                              ////
2261 
//// This source file is free software; you can redistribute it   ////
2262 
//// and/or modify it under the terms of the GNU Lesser General   ////
2263 
//// Public License as published by the Free Software Foundation; ////
2264 
//// either version 2.1 of the License, or (at your option) any   ////
2265 
//// later version.                                               ////
2266 
////                                                              ////
2267 
//// This source is distributed in the hope that it will be       ////
2268 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2269 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2270 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2271 
//// details.                                                     ////
2272 
////                                                              ////
2273 
//// You should have received a copy of the GNU Lesser General    ////
2274 
//// Public License along with this source; if not, download it   ////
2275 
//// from http://www.opencores.org/lgpl.shtml                     ////
2276 
////                                                              ////
2277 
//////////////////////////////////////////////////////////////////////
2278 
 
2279 6 unneback 
// LFSR counter
2280 
 
2281 40 unneback 
`define MODULE cnt_lfsr_zq
2282 
module `BASE`MODULE (
2283 
`undef MODULE
2284 
 zq, rst, clk);
2285 
 
2286 6 unneback 
   parameter length = 4;
2287 
   output reg zq;
2288 
   input rst;
2289 
   input clk;
2290 
 
2291 
   parameter clear_value = 0;
2292 
   parameter set_value = 1;
2293 
   parameter wrap_value = 8;
2294 
   parameter level1_value = 15;
2295 
 
2296 
   reg  [length:1] qi;
2297 
   reg lfsr_fb;
2298 
   wire [length:1] q_next;
2299 
   reg [32:1] polynom;
2300 
   integer i;
2301 
 
2302 
   always @ (qi)
2303 
   begin
2304 
        case (length)
2305 
         2: polynom = 32'b11;                               // 0x3
2306 
         3: polynom = 32'b110;                              // 0x6
2307 
         4: polynom = 32'b1100;                             // 0xC
2308 
         5: polynom = 32'b10100;                            // 0x14
2309 
         6: polynom = 32'b110000;                           // 0x30
2310 
         7: polynom = 32'b1100000;                          // 0x60
2311 
         8: polynom = 32'b10111000;                         // 0xb8
2312 
         9: polynom = 32'b100010000;                        // 0x110
2313 
        10: polynom = 32'b1001000000;                       // 0x240
2314 
        11: polynom = 32'b10100000000;                      // 0x500
2315 
        12: polynom = 32'b100000101001;                     // 0x829
2316 
        13: polynom = 32'b1000000001100;                    // 0x100C
2317 
        14: polynom = 32'b10000000010101;                   // 0x2015
2318 
        15: polynom = 32'b110000000000000;                  // 0x6000
2319 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2320 
        17: polynom = 32'b10010000000000000;                // 0x12000
2321 
        18: polynom = 32'b100000010000000000;               // 0x20400
2322 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2323 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2324 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2325 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2326 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2327 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2328 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2329 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2330 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2331 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2332 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2333 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2334 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2335 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2336 
        default: polynom = 32'b0;
2337 
        endcase
2338 
        lfsr_fb = qi[length];
2339 
        for (i=length-1; i>=1; i=i-1) begin
2340 
            if (polynom[i])
2341 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2342 
        end
2343 
    end
2344 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2345 
 
2346 
   always @ (posedge clk or posedge rst)
2347 
     if (rst)
2348 
       qi <= {length{1'b0}};
2349 
     else
2350 
       qi <= q_next;
2351 
 
2352 
 
2353 
 
2354 
   always @ (posedge clk or posedge rst)
2355 
     if (rst)
2356 
       zq <= 1'b1;
2357 
     else
2358 
       zq <= q_next == {length{1'b0}};
2359 
endmodule
2360 40 unneback 
`endif
2361 
`ifdef CNT_LFSR_CE_ZQ
2362 6 unneback 
//////////////////////////////////////////////////////////////////////
2363 
////                                                              ////
2364 
////  Versatile counter                                           ////
2365 
////                                                              ////
2366 
////  Description                                                 ////
2367 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2368 
////  counter                                                     ////
2369 
////                                                              ////
2370 
////  To Do:                                                      ////
2371 
////   - add LFSR with more taps                                  ////
2372 
////                                                              ////
2373 
////  Author(s):                                                  ////
2374 
////      - Michael Unneback, unneback@opencores.org              ////
2375 
////        ORSoC AB                                              ////
2376 
////                                                              ////
2377 
//////////////////////////////////////////////////////////////////////
2378 
////                                                              ////
2379 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2380 
////                                                              ////
2381 
//// This source file may be used and distributed without         ////
2382 
//// restriction provided that this copyright statement is not    ////
2383 
//// removed from the file and that any derivative work contains  ////
2384 
//// the original copyright notice and the associated disclaimer. ////
2385 
////                                                              ////
2386 
//// This source file is free software; you can redistribute it   ////
2387 
//// and/or modify it under the terms of the GNU Lesser General   ////
2388 
//// Public License as published by the Free Software Foundation; ////
2389 
//// either version 2.1 of the License, or (at your option) any   ////
2390 
//// later version.                                               ////
2391 
////                                                              ////
2392 
//// This source is distributed in the hope that it will be       ////
2393 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2394 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2395 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2396 
//// details.                                                     ////
2397 
////                                                              ////
2398 
//// You should have received a copy of the GNU Lesser General    ////
2399 
//// Public License along with this source; if not, download it   ////
2400 
//// from http://www.opencores.org/lgpl.shtml                     ////
2401 
////                                                              ////
2402 
//////////////////////////////////////////////////////////////////////
2403 
 
2404 
// LFSR counter
2405 
 
2406 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2407 
module `BASE`MODULE (
2408 
`undef MODULE
2409 
 cke, zq, rst, clk);
2410 
 
2411 6 unneback 
   parameter length = 4;
2412 
   input cke;
2413 
   output reg zq;
2414 
   input rst;
2415 
   input clk;
2416 
 
2417 
   parameter clear_value = 0;
2418 
   parameter set_value = 1;
2419 
   parameter wrap_value = 8;
2420 
   parameter level1_value = 15;
2421 
 
2422 
   reg  [length:1] qi;
2423 
   reg lfsr_fb;
2424 
   wire [length:1] q_next;
2425 
   reg [32:1] polynom;
2426 
   integer i;
2427 
 
2428 
   always @ (qi)
2429 
   begin
2430 
        case (length)
2431 
         2: polynom = 32'b11;                               // 0x3
2432 
         3: polynom = 32'b110;                              // 0x6
2433 
         4: polynom = 32'b1100;                             // 0xC
2434 
         5: polynom = 32'b10100;                            // 0x14
2435 
         6: polynom = 32'b110000;                           // 0x30
2436 
         7: polynom = 32'b1100000;                          // 0x60
2437 
         8: polynom = 32'b10111000;                         // 0xb8
2438 
         9: polynom = 32'b100010000;                        // 0x110
2439 
        10: polynom = 32'b1001000000;                       // 0x240
2440 
        11: polynom = 32'b10100000000;                      // 0x500
2441 
        12: polynom = 32'b100000101001;                     // 0x829
2442 
        13: polynom = 32'b1000000001100;                    // 0x100C
2443 
        14: polynom = 32'b10000000010101;                   // 0x2015
2444 
        15: polynom = 32'b110000000000000;                  // 0x6000
2445 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2446 
        17: polynom = 32'b10010000000000000;                // 0x12000
2447 
        18: polynom = 32'b100000010000000000;               // 0x20400
2448 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2449 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2450 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2451 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2452 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2453 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2454 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2455 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2456 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2457 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2458 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2459 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2460 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2461 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2462 
        default: polynom = 32'b0;
2463 
        endcase
2464 
        lfsr_fb = qi[length];
2465 
        for (i=length-1; i>=1; i=i-1) begin
2466 
            if (polynom[i])
2467 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2468 
        end
2469 
    end
2470 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2471 
 
2472 
   always @ (posedge clk or posedge rst)
2473 
     if (rst)
2474 
       qi <= {length{1'b0}};
2475 
     else
2476 
     if (cke)
2477 
       qi <= q_next;
2478 
 
2479 
 
2480 
 
2481 
   always @ (posedge clk or posedge rst)
2482 
     if (rst)
2483 
       zq <= 1'b1;
2484 
     else
2485 
     if (cke)
2486 
       zq <= q_next == {length{1'b0}};
2487 
endmodule
2488 40 unneback 
`endif
2489 
`ifdef CNT_LFSR_CE_Q
2490 6 unneback 
//////////////////////////////////////////////////////////////////////
2491 
////                                                              ////
2492 
////  Versatile counter                                           ////
2493 
////                                                              ////
2494 
////  Description                                                 ////
2495 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2496 
////  counter                                                     ////
2497 
////                                                              ////
2498 
////  To Do:                                                      ////
2499 
////   - add LFSR with more taps                                  ////
2500 
////                                                              ////
2501 
////  Author(s):                                                  ////
2502 
////      - Michael Unneback, unneback@opencores.org              ////
2503 
////        ORSoC AB                                              ////
2504 
////                                                              ////
2505 
//////////////////////////////////////////////////////////////////////
2506 
////                                                              ////
2507 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2508 
////                                                              ////
2509 
//// This source file may be used and distributed without         ////
2510 
//// restriction provided that this copyright statement is not    ////
2511 
//// removed from the file and that any derivative work contains  ////
2512 
//// the original copyright notice and the associated disclaimer. ////
2513 
////                                                              ////
2514 
//// This source file is free software; you can redistribute it   ////
2515 
//// and/or modify it under the terms of the GNU Lesser General   ////
2516 
//// Public License as published by the Free Software Foundation; ////
2517 
//// either version 2.1 of the License, or (at your option) any   ////
2518 
//// later version.                                               ////
2519 
////                                                              ////
2520 
//// This source is distributed in the hope that it will be       ////
2521 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2522 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2523 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2524 
//// details.                                                     ////
2525 
////                                                              ////
2526 
//// You should have received a copy of the GNU Lesser General    ////
2527 
//// Public License along with this source; if not, download it   ////
2528 
//// from http://www.opencores.org/lgpl.shtml                     ////
2529 
////                                                              ////
2530 
//////////////////////////////////////////////////////////////////////
2531 22 unneback 
 
2532 
// LFSR counter
2533 27 unneback 
 
2534 40 unneback 
`define MODULE cnt_lfsr_ce_q
2535 
module `BASE`MODULE (
2536 
`undef MODULE
2537 
 cke, q, rst, clk);
2538 
 
2539 27 unneback 
   parameter length = 4;
2540 
   input cke;
2541 
   output [length:1] q;
2542 
   input rst;
2543 
   input clk;
2544 
 
2545 
   parameter clear_value = 0;
2546 
   parameter set_value = 1;
2547 
   parameter wrap_value = 8;
2548 
   parameter level1_value = 15;
2549 
 
2550 
   reg  [length:1] qi;
2551 
   reg lfsr_fb;
2552 
   wire [length:1] q_next;
2553 
   reg [32:1] polynom;
2554 
   integer i;
2555 
 
2556 
   always @ (qi)
2557 
   begin
2558 
        case (length)
2559 
         2: polynom = 32'b11;                               // 0x3
2560 
         3: polynom = 32'b110;                              // 0x6
2561 
         4: polynom = 32'b1100;                             // 0xC
2562 
         5: polynom = 32'b10100;                            // 0x14
2563 
         6: polynom = 32'b110000;                           // 0x30
2564 
         7: polynom = 32'b1100000;                          // 0x60
2565 
         8: polynom = 32'b10111000;                         // 0xb8
2566 
         9: polynom = 32'b100010000;                        // 0x110
2567 
        10: polynom = 32'b1001000000;                       // 0x240
2568 
        11: polynom = 32'b10100000000;                      // 0x500
2569 
        12: polynom = 32'b100000101001;                     // 0x829
2570 
        13: polynom = 32'b1000000001100;                    // 0x100C
2571 
        14: polynom = 32'b10000000010101;                   // 0x2015
2572 
        15: polynom = 32'b110000000000000;                  // 0x6000
2573 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2574 
        17: polynom = 32'b10010000000000000;                // 0x12000
2575 
        18: polynom = 32'b100000010000000000;               // 0x20400
2576 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2577 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2578 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2579 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2580 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2581 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2582 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2583 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2584 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2585 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2586 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2587 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2588 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2589 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2590 
        default: polynom = 32'b0;
2591 
        endcase
2592 
        lfsr_fb = qi[length];
2593 
        for (i=length-1; i>=1; i=i-1) begin
2594 
            if (polynom[i])
2595 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2596 
        end
2597 
    end
2598 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2599 
 
2600 
   always @ (posedge clk or posedge rst)
2601 
     if (rst)
2602 
       qi <= {length{1'b0}};
2603 
     else
2604 
     if (cke)
2605 
       qi <= q_next;
2606 
 
2607 
   assign q = qi;
2608 
 
2609 
endmodule
2610 40 unneback 
`endif
2611 
`ifdef CNT_LFSR_CE_CLEAR_Q
2612 27 unneback 
//////////////////////////////////////////////////////////////////////
2613 
////                                                              ////
2614 
////  Versatile counter                                           ////
2615 
////                                                              ////
2616 
////  Description                                                 ////
2617 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2618 
////  counter                                                     ////
2619 
////                                                              ////
2620 
////  To Do:                                                      ////
2621 
////   - add LFSR with more taps                                  ////
2622 
////                                                              ////
2623 
////  Author(s):                                                  ////
2624 
////      - Michael Unneback, unneback@opencores.org              ////
2625 
////        ORSoC AB                                              ////
2626 
////                                                              ////
2627 
//////////////////////////////////////////////////////////////////////
2628 
////                                                              ////
2629 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2630 
////                                                              ////
2631 
//// This source file may be used and distributed without         ////
2632 
//// restriction provided that this copyright statement is not    ////
2633 
//// removed from the file and that any derivative work contains  ////
2634 
//// the original copyright notice and the associated disclaimer. ////
2635 
////                                                              ////
2636 
//// This source file is free software; you can redistribute it   ////
2637 
//// and/or modify it under the terms of the GNU Lesser General   ////
2638 
//// Public License as published by the Free Software Foundation; ////
2639 
//// either version 2.1 of the License, or (at your option) any   ////
2640 
//// later version.                                               ////
2641 
////                                                              ////
2642 
//// This source is distributed in the hope that it will be       ////
2643 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2644 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2645 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2646 
//// details.                                                     ////
2647 
////                                                              ////
2648 
//// You should have received a copy of the GNU Lesser General    ////
2649 
//// Public License along with this source; if not, download it   ////
2650 
//// from http://www.opencores.org/lgpl.shtml                     ////
2651 
////                                                              ////
2652 
//////////////////////////////////////////////////////////////////////
2653 
 
2654 
// LFSR counter
2655 
 
2656 40 unneback 
`define MODULE cnt_lfsr_ce_clear_q
2657 
module `BASE`MODULE (
2658 
`undef MODULE
2659 
 clear, cke, q, rst, clk);
2660 
 
2661 27 unneback 
   parameter length = 4;
2662 
   input clear;
2663 
   input cke;
2664 
   output [length:1] q;
2665 
   input rst;
2666 
   input clk;
2667 
 
2668 
   parameter clear_value = 0;
2669 
   parameter set_value = 1;
2670 
   parameter wrap_value = 8;
2671 
   parameter level1_value = 15;
2672 
 
2673 
   reg  [length:1] qi;
2674 
   reg lfsr_fb;
2675 
   wire [length:1] q_next;
2676 
   reg [32:1] polynom;
2677 
   integer i;
2678 
 
2679 
   always @ (qi)
2680 
   begin
2681 
        case (length)
2682 
         2: polynom = 32'b11;                               // 0x3
2683 
         3: polynom = 32'b110;                              // 0x6
2684 
         4: polynom = 32'b1100;                             // 0xC
2685 
         5: polynom = 32'b10100;                            // 0x14
2686 
         6: polynom = 32'b110000;                           // 0x30
2687 
         7: polynom = 32'b1100000;                          // 0x60
2688 
         8: polynom = 32'b10111000;                         // 0xb8
2689 
         9: polynom = 32'b100010000;                        // 0x110
2690 
        10: polynom = 32'b1001000000;                       // 0x240
2691 
        11: polynom = 32'b10100000000;                      // 0x500
2692 
        12: polynom = 32'b100000101001;                     // 0x829
2693 
        13: polynom = 32'b1000000001100;                    // 0x100C
2694 
        14: polynom = 32'b10000000010101;                   // 0x2015
2695 
        15: polynom = 32'b110000000000000;                  // 0x6000
2696 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2697 
        17: polynom = 32'b10010000000000000;                // 0x12000
2698 
        18: polynom = 32'b100000010000000000;               // 0x20400
2699 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2700 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2701 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2702 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2703 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2704 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2705 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2706 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2707 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2708 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2709 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2710 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2711 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2712 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2713 
        default: polynom = 32'b0;
2714 
        endcase
2715 
        lfsr_fb = qi[length];
2716 
        for (i=length-1; i>=1; i=i-1) begin
2717 
            if (polynom[i])
2718 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2719 
        end
2720 
    end
2721 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2722 
 
2723 
   always @ (posedge clk or posedge rst)
2724 
     if (rst)
2725 
       qi <= {length{1'b0}};
2726 
     else
2727 
     if (cke)
2728 
       qi <= q_next;
2729 
 
2730 
   assign q = qi;
2731 
 
2732 
endmodule
2733 40 unneback 
`endif
2734 
`ifdef CNT_LFSR_CE_Q_ZQ
2735 27 unneback 
//////////////////////////////////////////////////////////////////////
2736 
////                                                              ////
2737 
////  Versatile counter                                           ////
2738 
////                                                              ////
2739 
////  Description                                                 ////
2740 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2741 
////  counter                                                     ////
2742 
////                                                              ////
2743 
////  To Do:                                                      ////
2744 
////   - add LFSR with more taps                                  ////
2745 
////                                                              ////
2746 
////  Author(s):                                                  ////
2747 
////      - Michael Unneback, unneback@opencores.org              ////
2748 
////        ORSoC AB                                              ////
2749 
////                                                              ////
2750 
//////////////////////////////////////////////////////////////////////
2751 
////                                                              ////
2752 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2753 
////                                                              ////
2754 
//// This source file may be used and distributed without         ////
2755 
//// restriction provided that this copyright statement is not    ////
2756 
//// removed from the file and that any derivative work contains  ////
2757 
//// the original copyright notice and the associated disclaimer. ////
2758 
////                                                              ////
2759 
//// This source file is free software; you can redistribute it   ////
2760 
//// and/or modify it under the terms of the GNU Lesser General   ////
2761 
//// Public License as published by the Free Software Foundation; ////
2762 
//// either version 2.1 of the License, or (at your option) any   ////
2763 
//// later version.                                               ////
2764 
////                                                              ////
2765 
//// This source is distributed in the hope that it will be       ////
2766 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2767 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2768 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2769 
//// details.                                                     ////
2770 
////                                                              ////
2771 
//// You should have received a copy of the GNU Lesser General    ////
2772 
//// Public License along with this source; if not, download it   ////
2773 
//// from http://www.opencores.org/lgpl.shtml                     ////
2774 
////                                                              ////
2775 
//////////////////////////////////////////////////////////////////////
2776 
 
2777 
// LFSR counter
2778 22 unneback 
 
2779 40 unneback 
`define MODULE cnt_lfsr_ce_q_zq
2780 
module `BASE`MODULE (
2781 
`undef MODULE
2782 
 cke, q, zq, rst, clk);
2783 
 
2784 22 unneback 
   parameter length = 4;
2785 
   input cke;
2786 
   output [length:1] q;
2787 
   output reg zq;
2788 
   input rst;
2789 
   input clk;
2790 
 
2791 
   parameter clear_value = 0;
2792 
   parameter set_value = 1;
2793 
   parameter wrap_value = 8;
2794 
   parameter level1_value = 15;
2795 
 
2796 
   reg  [length:1] qi;
2797 
   reg lfsr_fb;
2798 
   wire [length:1] q_next;
2799 
   reg [32:1] polynom;
2800 
   integer i;
2801 
 
2802 
   always @ (qi)
2803 
   begin
2804 
        case (length)
2805 
         2: polynom = 32'b11;                               // 0x3
2806 
         3: polynom = 3