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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 67

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 40 unneback
`ifdef ALL
14
 
15
`define GBUF
16
`define SYNC_RST
17
`define PLL
18
 
19
`define MULTS
20
`define MULTS18X18
21
`define MULT
22
`define SHIFT_UNIT_32
23
`define LOGIC_UNIT
24
 
25
`define CNT_SHREG_WRAP
26
`define CNT_SHREG_CE_WRAP
27
`define CNT_SHREG_CE_CLEAR
28
`define CNT_SHREG_CE_CLEAR_WRAP
29
 
30
`define MUX_ANDOR
31
`define MUX2_ANDOR
32
`define MUX3_ANDOR
33
`define MUX4_ANDOR
34
`define MUX5_ANDOR
35
`define MUX6_ANDOR
36 43 unneback
`define PARITY
37 40 unneback
 
38
`define ROM_INIT
39
`define RAM
40
`define RAM_BE
41
`define DPRAM_1R1W
42
`define DPRAM_2R1W
43
`define DPRAM_2R2W
44
`define FIFO_1R1W_FILL_LEVEL_SYNC
45
`define FIFO_2R2W_SYNC_SIMPLEX
46
`define FIFO_CMP_ASYNC
47
`define FIFO_1R1W_ASYNC
48
`define FIFO_2R2W_ASYNC
49
`define FIFO_2R2W_ASYNC_SIMPLEX
50 48 unneback
`define REG_FILE
51 40 unneback
 
52
`define DFF
53
`define DFF_ARRAY
54
`define DFF_CE
55
`define DFF_CE_CLEAR
56
`define DF_CE_SET
57
`define SPR
58
`define SRP
59
`define DFF_SR
60
`define LATCH
61
`define SHREG
62
`define SHREG_CE
63
`define DELAY
64
`define DELAY_EMPTYFLAG
65
 
66
`define WB3WB3_BRIDGE
67
`define WB3_ARBITER_TYPE1
68 59 unneback
`define WB_B3_RAM_BE
69 49 unneback
`define WB_B4_RAM_BE
70 48 unneback
`define WB_B4_ROM
71 40 unneback
`define WB_BOOT_ROM
72
`define WB_DPRAM
73
 
74 44 unneback
`define IO_DFF_OE
75
`define O_DFF
76
 
77 40 unneback
`endif
78
 
79
`ifdef PLL
80
`ifndef SYNC_RST
81
`define SYNC_RST
82
`endif
83
`endif
84
 
85
`ifdef SYNC_RST
86
`ifndef GBUF
87
`define GBUF
88
`endif
89
`endif
90
 
91
`ifdef WB_DPRAM
92
`ifndef DPRAM_2R2W
93
`define DPRAM_2R2W
94
`endif
95
`ifndef SPR
96
`define SPR
97
`endif
98
`endif
99
 
100 62 unneback
`ifdef WB_B3_RAM_BE
101
`ifndef WB3_ARBITER_TYPE1
102
`define WB3_ARBITER_TYPE1
103
`endif
104
`ifndef RAM_BE
105
`define RAM_BE
106
`endif
107
`endif
108
 
109 40 unneback
`ifdef WB3_ARBITER_TYPE1
110 42 unneback
`ifndef SPR
111
`define SPR
112
`endif
113 40 unneback
`ifndef MUX_ANDOR
114
`define MUX_ANDOR
115
`endif
116
`endif
117
 
118
`ifdef WB3WB3_BRIDGE
119
`ifndef CNT_SHREG_CE_CLEAR
120
`define CNT_SHREG_CE_CLEAR
121
`endif
122
`ifndef DFF
123
`define DFF
124
`endif
125
`ifndef DFF_CE
126
`define DFF_CE
127
`endif
128
`ifndef CNT_SHREG_CE_CLEAR
129
`define CNT_SHREG_CE_CLEAR
130
`endif
131
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
132
`define FIFO_2R2W_ASYNC_SIMPLEX
133
`endif
134
`endif
135
 
136
`ifdef MULTS18X18
137
`ifndef MULTS
138
`define MULTS
139
`endif
140
`endif
141
 
142
`ifdef SHIFT_UNIT_32
143
`ifndef MULTS
144
`define MULTS
145
`endif
146
`endif
147
 
148
`ifdef MUX2_ANDOR
149
`ifndef MUX_ANDOR
150
`define MUX_ANDOR
151
`endif
152
`endif
153
 
154
`ifdef MUX3_ANDOR
155
`ifndef MUX_ANDOR
156
`define MUX_ANDOR
157
`endif
158
`endif
159
 
160
`ifdef MUX4_ANDOR
161
`ifndef MUX_ANDOR
162
`define MUX_ANDOR
163
`endif
164
`endif
165
 
166
`ifdef MUX5_ANDOR
167
`ifndef MUX_ANDOR
168
`define MUX_ANDOR
169
`endif
170
`endif
171
 
172
`ifdef MUX6_ANDOR
173
`ifndef MUX_ANDOR
174
`define MUX_ANDOR
175
`endif
176
`endif
177
 
178
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
179
`ifndef CNT_BIN_CE
180
`define CNT_BIN_CE
181
`endif
182
`ifndef DPRAM_1R1W
183
`define DPRAM_1R1W
184
`endif
185
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
186
`define CNT_BIN_CE_REW_Q_ZQ_L1
187
`endif
188
`endif
189
 
190
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
191
`ifndef CNT_LFSR_CE
192
`define CNT_LFSR_CE
193
`endif
194
`ifndef DPRAM_2R2W
195
`define DPRAM_2R2W
196
`endif
197
`ifndef CNT_BIN_CE_REW_ZQ_L1
198
`define CNT_BIN_CE_REW_ZQ_L1
199
`endif
200
`endif
201
 
202
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
203
`ifndef CNT_GRAY_CE_BIN
204
`define CNT_GRAY_CE_BIN
205
`endif
206
`ifndef DPRAM_2R2W
207
`define DPRAM_2R2W
208
`endif
209
`ifndef FIFO_CMP_ASYNC
210
`define FIFO_CMP_ASYNC
211
`endif
212
`endif
213
 
214
`ifdef FIFO_2R2W_ASYNC
215
`ifndef FIFO_1R1W_ASYNC
216
`define FIFO_1R1W_ASYNC
217
`endif
218
`endif
219
 
220
`ifdef FIFO_1R1W_ASYNC
221
`ifndef CNT_GRAY_CE_BIN
222
`define CNT_GRAY_CE_BIN
223
`endif
224
`ifndef DPRAM_1R1W
225
`define DPRAM_1R1W
226
`endif
227
`ifndef FIFO_CMP_ASYNC
228
`define FIFO_CMP_ASYNC
229
`endif
230
`endif
231
 
232
`ifdef FIFO_CMP_ASYNC
233
`ifndef DFF_SR
234
`define DFF_SR
235
`endif
236
`ifndef DFF
237
`define DFF
238
`endif
239
`endif
240 48 unneback
 
241
`ifdef REG_FILE
242
`ifndef DPRAM_1R1W
243
`define DPRAM_1R1W
244
`endif
245
`endif
246 62 unneback
//////////////////////////////////////////////////////////////////////
247 6 unneback
////                                                              ////
248
////  Versatile library, clock and reset                          ////
249
////                                                              ////
250
////  Description                                                 ////
251
////  Logic related to clock and reset                            ////
252
////                                                              ////
253
////                                                              ////
254
////  To Do:                                                      ////
255
////   - add more different registers                             ////
256
////                                                              ////
257
////  Author(s):                                                  ////
258
////      - Michael Unneback, unneback@opencores.org              ////
259
////        ORSoC AB                                              ////
260
////                                                              ////
261
//////////////////////////////////////////////////////////////////////
262
////                                                              ////
263
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
264
////                                                              ////
265
//// This source file may be used and distributed without         ////
266
//// restriction provided that this copyright statement is not    ////
267
//// removed from the file and that any derivative work contains  ////
268
//// the original copyright notice and the associated disclaimer. ////
269
////                                                              ////
270
//// This source file is free software; you can redistribute it   ////
271
//// and/or modify it under the terms of the GNU Lesser General   ////
272
//// Public License as published by the Free Software Foundation; ////
273
//// either version 2.1 of the License, or (at your option) any   ////
274
//// later version.                                               ////
275
////                                                              ////
276
//// This source is distributed in the hope that it will be       ////
277
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
278
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
279
//// PURPOSE.  See the GNU Lesser General Public License for more ////
280
//// details.                                                     ////
281
////                                                              ////
282
//// You should have received a copy of the GNU Lesser General    ////
283
//// Public License along with this source; if not, download it   ////
284
//// from http://www.opencores.org/lgpl.shtml                     ////
285
////                                                              ////
286
//////////////////////////////////////////////////////////////////////
287
 
288 48 unneback
`ifdef ACTEL
289
`ifdef GBUF
290
`timescale 1 ns/100 ps
291 6 unneback
// Global buffer
292
// usage:
293
// use to enable global buffers for high fan out signals such as clock and reset
294
// Version: 8.4 8.4.0.33
295
module gbuf(GL,CLK);
296
output GL;
297
input  CLK;
298
 
299
    wire GND;
300
 
301
    GND GND_1_net(.Y(GND));
302
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
303
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
304
 
305
endmodule
306
`timescale 1 ns/1 ns
307 40 unneback
`define MODULE gbuf
308
module `BASE`MODULE ( i, o);
309
`undef MODULE
310 6 unneback
input i;
311
output o;
312
`ifdef SIM_GBUF
313
assign o=i;
314
`else
315
gbuf gbuf_i0 ( .CLK(i), .GL(o));
316
`endif
317
endmodule
318 40 unneback
`endif
319 33 unneback
 
320 6 unneback
`else
321 33 unneback
 
322 40 unneback
`ifdef ALTERA
323
`ifdef GBUF
324 21 unneback
//altera
325 40 unneback
`define MODULE gbuf
326
module `BASE`MODULE ( i, o);
327
`undef MODULE
328 33 unneback
input i;
329
output o;
330
assign o = i;
331
endmodule
332 40 unneback
`endif
333 33 unneback
 
334 6 unneback
`else
335
 
336 40 unneback
`ifdef GBUF
337 6 unneback
`timescale 1 ns/100 ps
338 40 unneback
`define MODULE
339
module `BASE`MODULE ( i, o);
340
`undef MODULE
341 6 unneback
input i;
342
output o;
343
assign o = i;
344
endmodule
345 40 unneback
`endif
346 6 unneback
`endif // ALTERA
347
`endif //ACTEL
348
 
349 40 unneback
`ifdef SYNC_RST
350 6 unneback
// sync reset
351 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
352 6 unneback
// output active high global reset sync with two DFFs 
353
`timescale 1 ns/100 ps
354 40 unneback
`define MODULE sync_rst
355
module `BASE`MODULE ( rst_n_i, rst_o, clk);
356
`undef MODULE
357 6 unneback
input rst_n_i, clk;
358
output rst_o;
359 18 unneback
reg [1:0] tmp;
360 6 unneback
always @ (posedge clk or negedge rst_n_i)
361
if (!rst_n_i)
362 17 unneback
        tmp <= 2'b11;
363 6 unneback
else
364 33 unneback
        tmp <= {1'b0,tmp[1]};
365 40 unneback
`define MODULE gbuf
366
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
367
`undef MODULE
368 6 unneback
endmodule
369 40 unneback
`endif
370 6 unneback
 
371 40 unneback
`ifdef PLL
372 6 unneback
// vl_pll
373
`ifdef ACTEL
374 32 unneback
///////////////////////////////////////////////////////////////////////////////
375 17 unneback
`timescale 1 ps/1 ps
376 40 unneback
`define MODULE pll
377
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
378
`undef MODULE
379 6 unneback
parameter index = 0;
380
parameter number_of_clk = 1;
381 17 unneback
parameter period_time_0 = 20000;
382
parameter period_time_1 = 20000;
383
parameter period_time_2 = 20000;
384
parameter lock_delay = 2000000;
385 6 unneback
input clk_i, rst_n_i;
386
output lock;
387
output reg [0:number_of_clk-1] clk_o;
388
output [0:number_of_clk-1] rst_o;
389
 
390
`ifdef SIM_PLL
391
 
392
always
393
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
394
 
395
generate if (number_of_clk > 1)
396
always
397
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
398
endgenerate
399
 
400
generate if (number_of_clk > 2)
401
always
402
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
403
endgenerate
404
 
405
genvar i;
406
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
407
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
408
end
409
endgenerate
410
 
411
assign #lock_delay lock = rst_n_i;
412
 
413
endmodule
414
`else
415
generate if (number_of_clk==1 & index==0) begin
416
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
417
end
418
endgenerate // index==0
419
generate if (number_of_clk==1 & index==1) begin
420
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
421
end
422
endgenerate // index==1
423
generate if (number_of_clk==1 & index==2) begin
424
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
425
end
426
endgenerate // index==2
427
generate if (number_of_clk==1 & index==3) begin
428
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
429
end
430
endgenerate // index==0
431
 
432
generate if (number_of_clk==2 & index==0) begin
433
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
434
end
435
endgenerate // index==0
436
generate if (number_of_clk==2 & index==1) begin
437
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
438
end
439
endgenerate // index==1
440
generate if (number_of_clk==2 & index==2) begin
441
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
442
end
443
endgenerate // index==2
444
generate if (number_of_clk==2 & index==3) begin
445
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
446
end
447
endgenerate // index==0
448
 
449
generate if (number_of_clk==3 & index==0) begin
450
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
451
end
452
endgenerate // index==0
453
generate if (number_of_clk==3 & index==1) begin
454
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
455
end
456
endgenerate // index==1
457
generate if (number_of_clk==3 & index==2) begin
458
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
459
end
460
endgenerate // index==2
461
generate if (number_of_clk==3 & index==3) begin
462
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
463
end
464
endgenerate // index==0
465
 
466
genvar i;
467
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
468 40 unneback
`define MODULE sync_rst
469
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
470
`undef MODULE
471 6 unneback
end
472
endgenerate
473
endmodule
474
`endif
475 32 unneback
///////////////////////////////////////////////////////////////////////////////
476 6 unneback
 
477
`else
478
 
479 32 unneback
///////////////////////////////////////////////////////////////////////////////
480 6 unneback
`ifdef ALTERA
481
 
482 32 unneback
`timescale 1 ps/1 ps
483 40 unneback
`define MODULE pll
484
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
485
`undef MODULE
486 32 unneback
parameter index = 0;
487
parameter number_of_clk = 1;
488
parameter period_time_0 = 20000;
489
parameter period_time_1 = 20000;
490
parameter period_time_2 = 20000;
491
parameter period_time_3 = 20000;
492
parameter period_time_4 = 20000;
493
parameter lock_delay = 2000000;
494
input clk_i, rst_n_i;
495
output lock;
496
output reg [0:number_of_clk-1] clk_o;
497
output [0:number_of_clk-1] rst_o;
498
 
499
`ifdef SIM_PLL
500
 
501
always
502
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
503
 
504
generate if (number_of_clk > 1)
505
always
506
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
507
endgenerate
508
 
509
generate if (number_of_clk > 2)
510
always
511
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
512
endgenerate
513
 
514 33 unneback
generate if (number_of_clk > 3)
515 32 unneback
always
516
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
517
endgenerate
518
 
519 33 unneback
generate if (number_of_clk > 4)
520 32 unneback
always
521
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
522
endgenerate
523
 
524
genvar i;
525
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
526
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
527
end
528
endgenerate
529
 
530 33 unneback
//assign #lock_delay lock = rst_n_i;
531
assign lock = rst_n_i;
532 32 unneback
 
533
endmodule
534 6 unneback
`else
535
 
536 33 unneback
`ifdef VL_PLL0
537
`ifdef VL_PLL0_CLK1
538
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
539
`endif
540
`ifdef VL_PLL0_CLK2
541
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
542
`endif
543
`ifdef VL_PLL0_CLK3
544
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
545
`endif
546
`ifdef VL_PLL0_CLK4
547
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
548
`endif
549
`ifdef VL_PLL0_CLK5
550
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
551
`endif
552
`endif
553 32 unneback
 
554 33 unneback
`ifdef VL_PLL1
555
`ifdef VL_PLL1_CLK1
556
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
557
`endif
558
`ifdef VL_PLL1_CLK2
559
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
560
`endif
561
`ifdef VL_PLL1_CLK3
562
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
563
`endif
564
`ifdef VL_PLL1_CLK4
565
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
566
`endif
567
`ifdef VL_PLL1_CLK5
568
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
569
`endif
570
`endif
571 32 unneback
 
572 33 unneback
`ifdef VL_PLL2
573
`ifdef VL_PLL2_CLK1
574
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
575
`endif
576
`ifdef VL_PLL2_CLK2
577
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
578
`endif
579
`ifdef VL_PLL2_CLK3
580
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
581
`endif
582
`ifdef VL_PLL2_CLK4
583
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
584
`endif
585
`ifdef VL_PLL2_CLK5
586
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
587
`endif
588
`endif
589 32 unneback
 
590 33 unneback
`ifdef VL_PLL3
591
`ifdef VL_PLL3_CLK1
592
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
593
`endif
594
`ifdef VL_PLL3_CLK2
595
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
596
`endif
597
`ifdef VL_PLL3_CLK3
598
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
599
`endif
600
`ifdef VL_PLL3_CLK4
601
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
602
`endif
603
`ifdef VL_PLL3_CLK5
604
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
605
`endif
606
`endif
607 32 unneback
 
608
genvar i;
609
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
610 40 unneback
`define MODULE sync_rst
611
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
612
`undef MODULE
613 32 unneback
end
614
endgenerate
615
endmodule
616
`endif
617
///////////////////////////////////////////////////////////////////////////////
618
 
619
`else
620
 
621 6 unneback
// generic PLL
622 17 unneback
`timescale 1 ps/1 ps
623 40 unneback
`define MODULE pll
624
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
625
`undef MODULE
626 6 unneback
parameter index = 0;
627
parameter number_of_clk = 1;
628 17 unneback
parameter period_time_0 = 20000;
629
parameter period_time_1 = 20000;
630
parameter period_time_2 = 20000;
631 6 unneback
parameter lock_delay = 2000;
632
input clk_i, rst_n_i;
633
output lock;
634
output reg [0:number_of_clk-1] clk_o;
635
output [0:number_of_clk-1] rst_o;
636
 
637
always
638
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
639
 
640
generate if (number_of_clk > 1)
641
always
642
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
643
endgenerate
644
 
645
generate if (number_of_clk > 2)
646
always
647
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
648
endgenerate
649
 
650
genvar i;
651
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
652 40 unneback
`define MODULE sync_rst
653
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
654
`undef MODULE
655 6 unneback
end
656
endgenerate
657
 
658
assign #lock_delay lock = rst_n_i;
659
 
660
endmodule
661
 
662
`endif //altera
663 17 unneback
`endif //actel
664 40 unneback
`undef MODULE
665
`endif//////////////////////////////////////////////////////////////////////
666 6 unneback
////                                                              ////
667
////  Versatile library, registers                                ////
668
////                                                              ////
669
////  Description                                                 ////
670
////  Different type of registers                                 ////
671
////                                                              ////
672
////                                                              ////
673
////  To Do:                                                      ////
674
////   - add more different registers                             ////
675
////                                                              ////
676
////  Author(s):                                                  ////
677
////      - Michael Unneback, unneback@opencores.org              ////
678
////        ORSoC AB                                              ////
679
////                                                              ////
680
//////////////////////////////////////////////////////////////////////
681
////                                                              ////
682
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
683
////                                                              ////
684
//// This source file may be used and distributed without         ////
685
//// restriction provided that this copyright statement is not    ////
686
//// removed from the file and that any derivative work contains  ////
687
//// the original copyright notice and the associated disclaimer. ////
688
////                                                              ////
689
//// This source file is free software; you can redistribute it   ////
690
//// and/or modify it under the terms of the GNU Lesser General   ////
691
//// Public License as published by the Free Software Foundation; ////
692
//// either version 2.1 of the License, or (at your option) any   ////
693
//// later version.                                               ////
694
////                                                              ////
695
//// This source is distributed in the hope that it will be       ////
696
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
697
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
698
//// PURPOSE.  See the GNU Lesser General Public License for more ////
699
//// details.                                                     ////
700
////                                                              ////
701
//// You should have received a copy of the GNU Lesser General    ////
702
//// Public License along with this source; if not, download it   ////
703
//// from http://www.opencores.org/lgpl.shtml                     ////
704
////                                                              ////
705
//////////////////////////////////////////////////////////////////////
706
 
707 40 unneback
`ifdef DFF
708
`define MODULE dff
709
module `BASE`MODULE ( d, q, clk, rst);
710
`undef MODULE
711 6 unneback
        parameter width = 1;
712
        parameter reset_value = 0;
713
 
714
        input [width-1:0] d;
715
        input clk, rst;
716
        output reg [width-1:0] q;
717
 
718
        always @ (posedge clk or posedge rst)
719
        if (rst)
720
                q <= reset_value;
721
        else
722
                q <= d;
723
 
724
endmodule
725 40 unneback
`endif
726 6 unneback
 
727 40 unneback
`ifdef DFF_ARRAY
728
`define MODULE dff_array
729
module `BASE`MODULE ( d, q, clk, rst);
730
`undef MODULE
731 6 unneback
 
732
        parameter width = 1;
733
        parameter depth = 2;
734
        parameter reset_value = 1'b0;
735
 
736
        input [width-1:0] d;
737
        input clk, rst;
738
        output [width-1:0] q;
739
        reg  [0:depth-1] q_tmp [width-1:0];
740
        integer i;
741
        always @ (posedge clk or posedge rst)
742
        if (rst) begin
743
            for (i=0;i<depth;i=i+1)
744
                q_tmp[i] <= {width{reset_value}};
745
        end else begin
746
            q_tmp[0] <= d;
747
            for (i=1;i<depth;i=i+1)
748
                q_tmp[i] <= q_tmp[i-1];
749
        end
750
 
751
    assign q = q_tmp[depth-1];
752
 
753
endmodule
754 40 unneback
`endif
755 6 unneback
 
756 40 unneback
`ifdef DFF_CE
757
`define MODULE dff_ce
758
module `BASE`MODULE ( d, ce, q, clk, rst);
759
`undef MODULE
760 6 unneback
 
761
        parameter width = 1;
762
        parameter reset_value = 0;
763
 
764
        input [width-1:0] d;
765
        input ce, clk, rst;
766
        output reg [width-1:0] q;
767
 
768
        always @ (posedge clk or posedge rst)
769
        if (rst)
770
                q <= reset_value;
771
        else
772
                if (ce)
773
                        q <= d;
774
 
775
endmodule
776 40 unneback
`endif
777 6 unneback
 
778 40 unneback
`ifdef DFF_CE_CLEAR
779
`define MODULE dff_ce_clear
780
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
781
`undef MODULE
782 8 unneback
 
783
        parameter width = 1;
784
        parameter reset_value = 0;
785
 
786
        input [width-1:0] d;
787 10 unneback
        input ce, clear, clk, rst;
788 8 unneback
        output reg [width-1:0] q;
789
 
790
        always @ (posedge clk or posedge rst)
791
        if (rst)
792
            q <= reset_value;
793
        else
794
            if (ce)
795
                if (clear)
796
                    q <= {width{1'b0}};
797
                else
798
                    q <= d;
799
 
800
endmodule
801 40 unneback
`endif
802 8 unneback
 
803 40 unneback
`ifdef DF_CE_SET
804
`define MODULE dff_ce_set
805
module `BASE`MODULE ( d, ce, set, q, clk, rst);
806
`undef MODULE
807 24 unneback
 
808
        parameter width = 1;
809
        parameter reset_value = 0;
810
 
811
        input [width-1:0] d;
812
        input ce, set, clk, rst;
813
        output reg [width-1:0] q;
814
 
815
        always @ (posedge clk or posedge rst)
816
        if (rst)
817
            q <= reset_value;
818
        else
819
            if (ce)
820
                if (set)
821
                    q <= {width{1'b1}};
822
                else
823
                    q <= d;
824
 
825
endmodule
826 40 unneback
`endif
827 24 unneback
 
828 40 unneback
`ifdef SPR
829
`define MODULE spr
830
module `BASE`MODULE ( sp, r, q, clk, rst);
831
`undef MODULE
832
 
833 64 unneback
        //parameter width = 1;
834
        parameter reset_value = 1'b0;
835 29 unneback
 
836
        input sp, r;
837
        output reg q;
838
        input clk, rst;
839
 
840
        always @ (posedge clk or posedge rst)
841
        if (rst)
842
            q <= reset_value;
843
        else
844
            if (sp)
845
                q <= 1'b1;
846
            else if (r)
847
                q <= 1'b0;
848
 
849
endmodule
850 40 unneback
`endif
851 29 unneback
 
852 40 unneback
`ifdef SRP
853
`define MODULE srp
854
module `BASE`MODULE ( s, rp, q, clk, rst);
855
`undef MODULE
856
 
857 29 unneback
        parameter width = 1;
858
        parameter reset_value = 0;
859
 
860
        input s, rp;
861
        output reg q;
862
        input clk, rst;
863
 
864
        always @ (posedge clk or posedge rst)
865
        if (rst)
866
            q <= reset_value;
867
        else
868
            if (rp)
869
                q <= 1'b0;
870
            else if (s)
871
                q <= 1'b1;
872
 
873
endmodule
874 40 unneback
`endif
875 29 unneback
 
876 40 unneback
`ifdef ALTERA
877 29 unneback
 
878 40 unneback
`ifdef DFF_SR
879 6 unneback
// megafunction wizard: %LPM_FF%
880
// GENERATION: STANDARD
881
// VERSION: WM1.0
882
// MODULE: lpm_ff 
883
 
884
// ============================================================
885
// File Name: dff_sr.v
886
// Megafunction Name(s):
887
//                      lpm_ff
888
//
889
// Simulation Library Files(s):
890
//                      lpm
891
// ============================================================
892
// ************************************************************
893
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
894
//
895
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
896
// ************************************************************
897
 
898
 
899
//Copyright (C) 1991-2010 Altera Corporation
900
//Your use of Altera Corporation's design tools, logic functions 
901
//and other software and tools, and its AMPP partner logic 
902
//functions, and any output files from any of the foregoing 
903
//(including device programming or simulation files), and any 
904
//associated documentation or information are expressly subject 
905
//to the terms and conditions of the Altera Program License 
906
//Subscription Agreement, Altera MegaCore Function License 
907
//Agreement, or other applicable license agreement, including, 
908
//without limitation, that your use is for the sole purpose of 
909
//programming logic devices manufactured by Altera and sold by 
910
//Altera or its authorized distributors.  Please refer to the 
911
//applicable agreement for further details.
912
 
913
 
914
// synopsys translate_off
915
`timescale 1 ps / 1 ps
916
// synopsys translate_on
917 40 unneback
`define MODULE dff_sr
918
module `BASE`MODULE (
919
`undef MODULE
920
 
921 6 unneback
        aclr,
922
        aset,
923
        clock,
924
        data,
925
        q);
926
 
927
        input     aclr;
928
        input     aset;
929
        input     clock;
930
        input     data;
931
        output    q;
932
 
933
        wire [0:0] sub_wire0;
934
        wire [0:0] sub_wire1 = sub_wire0[0:0];
935
        wire  q = sub_wire1;
936
        wire  sub_wire2 = data;
937
        wire  sub_wire3 = sub_wire2;
938
 
939
        lpm_ff  lpm_ff_component (
940
                                .aclr (aclr),
941
                                .clock (clock),
942
                                .data (sub_wire3),
943
                                .aset (aset),
944
                                .q (sub_wire0)
945
                                // synopsys translate_off
946
                                ,
947
                                .aload (),
948
                                .enable (),
949
                                .sclr (),
950
                                .sload (),
951
                                .sset ()
952
                                // synopsys translate_on
953
                                );
954
        defparam
955
                lpm_ff_component.lpm_fftype = "DFF",
956
                lpm_ff_component.lpm_type = "LPM_FF",
957
                lpm_ff_component.lpm_width = 1;
958
 
959
 
960
endmodule
961
 
962
// ============================================================
963
// CNX file retrieval info
964
// ============================================================
965
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
966
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
967
// Retrieval info: PRIVATE: ASET NUMERIC "1"
968
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
969
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
970
// Retrieval info: PRIVATE: DFF NUMERIC "1"
971
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
972
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
973
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
974
// Retrieval info: PRIVATE: SSET NUMERIC "0"
975
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
976
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
977
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
978
// Retrieval info: PRIVATE: nBit NUMERIC "1"
979
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
980
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
981
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
982
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
983
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
984
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
985
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
986
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
987
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
988
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
989
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
990
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
991
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
992
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
993
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
994
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
995
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
996
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
997
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
998
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
999
// Retrieval info: LIB_FILE: lpm
1000 40 unneback
`endif
1001 6 unneback
 
1002
`else
1003
 
1004 40 unneback
`ifdef DFF_SR
1005
`define MODULE dff_sr
1006
module `BASE`MODULE ( aclr, aset, clock, data, q);
1007
`undef MODULE
1008 6 unneback
 
1009
    input         aclr;
1010
    input         aset;
1011
    input         clock;
1012
    input         data;
1013
    output reg    q;
1014
 
1015
   always @ (posedge clock or posedge aclr or posedge aset)
1016
     if (aclr)
1017
       q <= 1'b0;
1018
     else if (aset)
1019
       q <= 1'b1;
1020
     else
1021
       q <= data;
1022
 
1023
endmodule
1024 40 unneback
`endif
1025 6 unneback
 
1026
`endif
1027
 
1028
// LATCH
1029
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1030
`ifdef ALTERA
1031 40 unneback
 
1032
`ifdef LATCH
1033
`define MODULE latch
1034
module `BASE`MODULE ( d, le, q, clk);
1035
`undef MODULE
1036 6 unneback
input d, le;
1037
output q;
1038
input clk;
1039
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1040
endmodule
1041 40 unneback
`endif
1042
 
1043 6 unneback
`else
1044 40 unneback
 
1045
`ifdef LATCH
1046
`define MODULE latch
1047
module `BASE`MODULE ( d, le, q, clk);
1048
`undef MODULE
1049 6 unneback
input d, le;
1050 48 unneback
input clk;
1051
always @ (le or d)
1052 60 unneback
if (le)
1053 48 unneback
    d <= q;
1054 6 unneback
endmodule
1055 15 unneback
`endif
1056
 
1057 40 unneback
`endif
1058
 
1059
`ifdef SHREG
1060
`define MODULE shreg
1061
module `BASE`MODULE ( d, q, clk, rst);
1062
`undef MODULE
1063
 
1064 17 unneback
parameter depth = 10;
1065
input d;
1066
output q;
1067
input clk, rst;
1068
 
1069
reg [1:depth] dffs;
1070
 
1071
always @ (posedge clk or posedge rst)
1072
if (rst)
1073
    dffs <= {depth{1'b0}};
1074
else
1075
    dffs <= {d,dffs[1:depth-1]};
1076
assign q = dffs[depth];
1077
endmodule
1078 40 unneback
`endif
1079 17 unneback
 
1080 40 unneback
`ifdef SHREG_CE
1081
`define MODULE shreg_ce
1082
module `BASE`MODULE ( d, ce, q, clk, rst);
1083
`undef MODULE
1084 17 unneback
parameter depth = 10;
1085
input d, ce;
1086
output q;
1087
input clk, rst;
1088
 
1089
reg [1:depth] dffs;
1090
 
1091
always @ (posedge clk or posedge rst)
1092
if (rst)
1093
    dffs <= {depth{1'b0}};
1094
else
1095
    if (ce)
1096
        dffs <= {d,dffs[1:depth-1]};
1097
assign q = dffs[depth];
1098
endmodule
1099 40 unneback
`endif
1100 17 unneback
 
1101 40 unneback
`ifdef DELAY
1102
`define MODULE delay
1103
module `BASE`MODULE ( d, q, clk, rst);
1104
`undef MODULE
1105 15 unneback
parameter depth = 10;
1106
input d;
1107
output q;
1108
input clk, rst;
1109
 
1110
reg [1:depth] dffs;
1111
 
1112
always @ (posedge clk or posedge rst)
1113
if (rst)
1114
    dffs <= {depth{1'b0}};
1115
else
1116
    dffs <= {d,dffs[1:depth-1]};
1117
assign q = dffs[depth];
1118 17 unneback
endmodule
1119 40 unneback
`endif
1120 17 unneback
 
1121 40 unneback
`ifdef DELAY_EMPTYFLAG
1122
`define MODULE delay_emptyflag
1123 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1124 40 unneback
`undef MODULE
1125 17 unneback
parameter depth = 10;
1126
input d;
1127
output q, emptyflag;
1128
input clk, rst;
1129
 
1130
reg [1:depth] dffs;
1131
 
1132
always @ (posedge clk or posedge rst)
1133
if (rst)
1134
    dffs <= {depth{1'b0}};
1135
else
1136
    dffs <= {d,dffs[1:depth-1]};
1137
assign q = dffs[depth];
1138
assign emptyflag = !(|dffs);
1139
endmodule
1140 40 unneback
`endif
1141 17 unneback
//////////////////////////////////////////////////////////////////////
1142 6 unneback
////                                                              ////
1143 18 unneback
////  Logic functions                                             ////
1144
////                                                              ////
1145
////  Description                                                 ////
1146
////  Logic functions such as multiplexers                        ////
1147
////                                                              ////
1148
////                                                              ////
1149
////  To Do:                                                      ////
1150
////   -                                                          ////
1151
////                                                              ////
1152
////  Author(s):                                                  ////
1153
////      - Michael Unneback, unneback@opencores.org              ////
1154
////        ORSoC AB                                              ////
1155
////                                                              ////
1156
//////////////////////////////////////////////////////////////////////
1157
////                                                              ////
1158
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1159
////                                                              ////
1160
//// This source file may be used and distributed without         ////
1161
//// restriction provided that this copyright statement is not    ////
1162
//// removed from the file and that any derivative work contains  ////
1163
//// the original copyright notice and the associated disclaimer. ////
1164
////                                                              ////
1165
//// This source file is free software; you can redistribute it   ////
1166
//// and/or modify it under the terms of the GNU Lesser General   ////
1167
//// Public License as published by the Free Software Foundation; ////
1168
//// either version 2.1 of the License, or (at your option) any   ////
1169
//// later version.                                               ////
1170
////                                                              ////
1171
//// This source is distributed in the hope that it will be       ////
1172
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1173
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1174
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1175
//// details.                                                     ////
1176
////                                                              ////
1177
//// You should have received a copy of the GNU Lesser General    ////
1178
//// Public License along with this source; if not, download it   ////
1179
//// from http://www.opencores.org/lgpl.shtml                     ////
1180
////                                                              ////
1181
//////////////////////////////////////////////////////////////////////
1182 40 unneback
`ifdef MUX_ANDOR
1183
`define MODULE mux_andor
1184
module `BASE`MODULE ( a, sel, dout);
1185
`undef MODULE
1186 36 unneback
 
1187
parameter width = 32;
1188
parameter nr_of_ports = 4;
1189
 
1190
input [nr_of_ports*width-1:0] a;
1191
input [nr_of_ports-1:0] sel;
1192
output reg [width-1:0] dout;
1193
 
1194 38 unneback
integer i,j;
1195
 
1196 36 unneback
always @ (a, sel)
1197
begin
1198
    dout = a[width-1:0] & {width{sel[0]}};
1199 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1200
        for (j=0;j<width;j=j+1)
1201
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1202 36 unneback
end
1203
 
1204
endmodule
1205 40 unneback
`endif
1206 36 unneback
 
1207 40 unneback
`ifdef MUX2_ANDOR
1208
`define MODULE mux2_andor
1209
module `BASE`MODULE ( a1, a0, sel, dout);
1210
`undef MODULE
1211 18 unneback
 
1212 34 unneback
parameter width = 32;
1213 35 unneback
localparam nr_of_ports = 2;
1214 34 unneback
input [width-1:0] a1, a0;
1215
input [nr_of_ports-1:0] sel;
1216
output [width-1:0] dout;
1217
 
1218 40 unneback
`define MODULE mux_andor
1219
`BASE`MODULE
1220 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1221 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1222 40 unneback
`undef MODULE
1223
 
1224 34 unneback
endmodule
1225 40 unneback
`endif
1226 34 unneback
 
1227 40 unneback
`ifdef MUX3_ANDOR
1228
`define MODULE mux3_andor
1229
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1230
`undef MODULE
1231 34 unneback
 
1232
parameter width = 32;
1233 35 unneback
localparam nr_of_ports = 3;
1234 34 unneback
input [width-1:0] a2, a1, a0;
1235
input [nr_of_ports-1:0] sel;
1236
output [width-1:0] dout;
1237
 
1238 40 unneback
`define MODULE mux_andor
1239
`BASE`MODULE
1240 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1241 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1242 40 unneback
`undef MODULE
1243 34 unneback
endmodule
1244 40 unneback
`endif
1245 34 unneback
 
1246 40 unneback
`ifdef MUX4_ANDOR
1247
`define MODULE mux4_andor
1248
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1249
`undef MODULE
1250 18 unneback
 
1251
parameter width = 32;
1252 35 unneback
localparam nr_of_ports = 4;
1253 18 unneback
input [width-1:0] a3, a2, a1, a0;
1254
input [nr_of_ports-1:0] sel;
1255 22 unneback
output [width-1:0] dout;
1256 18 unneback
 
1257 40 unneback
`define MODULE mux_andor
1258
`BASE`MODULE
1259 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1260 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1261 40 unneback
`undef MODULE
1262 18 unneback
 
1263
endmodule
1264 40 unneback
`endif
1265 18 unneback
 
1266 40 unneback
`ifdef MUX5_ANDOR
1267
`define MODULE mux5_andor
1268
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1269
`undef MODULE
1270 18 unneback
 
1271
parameter width = 32;
1272 35 unneback
localparam nr_of_ports = 5;
1273 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1274
input [nr_of_ports-1:0] sel;
1275 22 unneback
output [width-1:0] dout;
1276 18 unneback
 
1277 40 unneback
`define MODULE mux_andor
1278
`BASE`MODULE
1279 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1280 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1281 40 unneback
`undef MODULE
1282 18 unneback
 
1283
endmodule
1284 40 unneback
`endif
1285 18 unneback
 
1286 40 unneback
`ifdef MUX6_ANDOR
1287
`define MODULE mux6_andor
1288
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1289
`undef MODULE
1290 18 unneback
 
1291
parameter width = 32;
1292 35 unneback
localparam nr_of_ports = 6;
1293 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1294
input [nr_of_ports-1:0] sel;
1295 22 unneback
output [width-1:0] dout;
1296 18 unneback
 
1297 40 unneback
`define MODULE mux_andor
1298
`BASE`MODULE
1299 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1300 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1301 40 unneback
`undef MODULE
1302 18 unneback
 
1303
endmodule
1304 40 unneback
`endif
1305 43 unneback
 
1306
`ifdef PARITY
1307
 
1308
`define MODULE parity_generate
1309
module `BASE`MODULE (data, parity);
1310
`undef MODULE
1311
parameter word_size = 32;
1312
parameter chunk_size = 8;
1313
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1314
input [word_size-1:0] data;
1315
output reg [word_size/chunk_size-1:0] parity;
1316
integer i,j;
1317
always @ (data)
1318
for (i=0;i<word_size/chunk_size;i=i+1) begin
1319
    parity[i] = parity_type;
1320
    for (j=0;j<chunk_size;j=j+1) begin
1321 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1322 43 unneback
    end
1323
end
1324
endmodule
1325
 
1326
`define MODULE parity_check
1327
module `BASE`MODULE( data, parity, parity_error);
1328
`undef MODULE
1329
parameter word_size = 32;
1330
parameter chunk_size = 8;
1331
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1332
input [word_size-1:0] data;
1333
input [word_size/chunk_size-1:0] parity;
1334
output parity_error;
1335 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1336 43 unneback
integer i,j;
1337
always @ (data or parity)
1338
for (i=0;i<word_size/chunk_size;i=i+1) begin
1339
    error_flag[i] = parity[i] ^ parity_type;
1340
    for (j=0;j<chunk_size;j=j+1) begin
1341 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1342 43 unneback
    end
1343
end
1344
assign parity_error = |error_flag;
1345
endmodule
1346
 
1347 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1348
////                                                              ////
1349
////  IO functions                                                ////
1350
////                                                              ////
1351
////  Description                                                 ////
1352
////  IO functions such as IOB flip-flops                         ////
1353
////                                                              ////
1354
////                                                              ////
1355
////  To Do:                                                      ////
1356
////   -                                                          ////
1357
////                                                              ////
1358
////  Author(s):                                                  ////
1359
////      - Michael Unneback, unneback@opencores.org              ////
1360
////        ORSoC AB                                              ////
1361
////                                                              ////
1362 18 unneback
//////////////////////////////////////////////////////////////////////
1363
////                                                              ////
1364 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1365
////                                                              ////
1366
//// This source file may be used and distributed without         ////
1367
//// restriction provided that this copyright statement is not    ////
1368
//// removed from the file and that any derivative work contains  ////
1369
//// the original copyright notice and the associated disclaimer. ////
1370
////                                                              ////
1371
//// This source file is free software; you can redistribute it   ////
1372
//// and/or modify it under the terms of the GNU Lesser General   ////
1373
//// Public License as published by the Free Software Foundation; ////
1374
//// either version 2.1 of the License, or (at your option) any   ////
1375
//// later version.                                               ////
1376
////                                                              ////
1377
//// This source is distributed in the hope that it will be       ////
1378
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1379
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1380
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1381
//// details.                                                     ////
1382
////                                                              ////
1383
//// You should have received a copy of the GNU Lesser General    ////
1384
//// Public License along with this source; if not, download it   ////
1385
//// from http://www.opencores.org/lgpl.shtml                     ////
1386
////                                                              ////
1387
//////////////////////////////////////////////////////////////////////
1388 45 unneback
`timescale 1ns/1ns
1389 44 unneback
`ifdef O_DFF
1390
`define MODULE o_dff
1391
module `BASE`MODULE (d_i, o_pad, clk, rst);
1392
`undef MODULE
1393
parameter width = 1;
1394 45 unneback
parameter reset_value = {width{1'b0}};
1395
input  [width-1:0]  d_i;
1396 44 unneback
output [width-1:0] o_pad;
1397
input clk, rst;
1398
wire [width-1:0] d_i_int `SYN_KEEP;
1399 45 unneback
reg  [width-1:0] o_pad_int;
1400 44 unneback
assign d_i_int = d_i;
1401
genvar i;
1402 45 unneback
generate
1403 44 unneback
for (i=0;i<width;i=i+1) begin
1404
    always @ (posedge clk or posedge rst)
1405
    if (rst)
1406 45 unneback
        o_pad_int[i] <= reset_value[i];
1407 44 unneback
    else
1408 45 unneback
        o_pad_int[i] <= d_i_int[i];
1409
    assign #1 o_pad[i] = o_pad_int[i];
1410 44 unneback
end
1411
endgenerate
1412
endmodule
1413
`endif
1414
 
1415 45 unneback
`timescale 1ns/1ns
1416 44 unneback
`ifdef IO_DFF_OE
1417
`define MODULE io_dff_oe
1418
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1419
`undef MODULE
1420
parameter width = 1;
1421
input  [width-1:0] d_o;
1422
output reg [width-1:0] d_i;
1423
input oe;
1424
inout [width-1:0] io_pad;
1425
input clk, rst;
1426
wire [width-1:0] oe_d `SYN_KEEP;
1427
reg [width-1:0] oe_q;
1428
reg [width-1:0] d_o_q;
1429
assign oe_d = {width{oe}};
1430
genvar i;
1431
generate
1432
for (i=0;i<width;i=i+1) begin
1433
    always @ (posedge clk or posedge rst)
1434
    if (rst)
1435
        oe_q[i] <= 1'b0;
1436
    else
1437
        oe_q[i] <= oe_d[i];
1438
    always @ (posedge clk or posedge rst)
1439
    if (rst)
1440
        d_o_q[i] <= 1'b0;
1441
    else
1442
        d_o_q[i] <= d_o[i];
1443
    always @ (posedge clk or posedge rst)
1444
    if (rst)
1445
        d_i[i] <= 1'b0;
1446
    else
1447
        d_i[i] <= io_pad[i];
1448 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1449 44 unneback
end
1450
endgenerate
1451
endmodule
1452
`endif
1453
`ifdef CNT_BIN
1454
//////////////////////////////////////////////////////////////////////
1455
////                                                              ////
1456 6 unneback
////  Versatile counter                                           ////
1457
////                                                              ////
1458
////  Description                                                 ////
1459
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1460
////  counter                                                     ////
1461
////                                                              ////
1462
////  To Do:                                                      ////
1463
////   - add LFSR with more taps                                  ////
1464
////                                                              ////
1465
////  Author(s):                                                  ////
1466
////      - Michael Unneback, unneback@opencores.org              ////
1467
////        ORSoC AB                                              ////
1468
////                                                              ////
1469
//////////////////////////////////////////////////////////////////////
1470
////                                                              ////
1471
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1472
////                                                              ////
1473
//// This source file may be used and distributed without         ////
1474
//// restriction provided that this copyright statement is not    ////
1475
//// removed from the file and that any derivative work contains  ////
1476
//// the original copyright notice and the associated disclaimer. ////
1477
////                                                              ////
1478
//// This source file is free software; you can redistribute it   ////
1479
//// and/or modify it under the terms of the GNU Lesser General   ////
1480
//// Public License as published by the Free Software Foundation; ////
1481
//// either version 2.1 of the License, or (at your option) any   ////
1482
//// later version.                                               ////
1483
////                                                              ////
1484
//// This source is distributed in the hope that it will be       ////
1485
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1486
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1487
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1488
//// details.                                                     ////
1489
////                                                              ////
1490
//// You should have received a copy of the GNU Lesser General    ////
1491
//// Public License along with this source; if not, download it   ////
1492
//// from http://www.opencores.org/lgpl.shtml                     ////
1493
////                                                              ////
1494
//////////////////////////////////////////////////////////////////////
1495
 
1496
// binary counter
1497 22 unneback
 
1498 40 unneback
`define MODULE cnt_bin
1499
module `BASE`MODULE (
1500
`undef MODULE
1501
 q, rst, clk);
1502
 
1503 22 unneback
   parameter length = 4;
1504
   output [length:1] q;
1505
   input rst;
1506
   input clk;
1507
 
1508
   parameter clear_value = 0;
1509
   parameter set_value = 1;
1510
   parameter wrap_value = 0;
1511
   parameter level1_value = 15;
1512
 
1513
   reg  [length:1] qi;
1514
   wire [length:1] q_next;
1515
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1516
 
1517
   always @ (posedge clk or posedge rst)
1518
     if (rst)
1519
       qi <= {length{1'b0}};
1520
     else
1521
       qi <= q_next;
1522
 
1523
   assign q = qi;
1524
 
1525
endmodule
1526 40 unneback
`endif
1527
`ifdef CNT_BIN_CLEAR
1528 22 unneback
//////////////////////////////////////////////////////////////////////
1529
////                                                              ////
1530
////  Versatile counter                                           ////
1531
////                                                              ////
1532
////  Description                                                 ////
1533
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1534
////  counter                                                     ////
1535
////                                                              ////
1536
////  To Do:                                                      ////
1537
////   - add LFSR with more taps                                  ////
1538
////                                                              ////
1539
////  Author(s):                                                  ////
1540
////      - Michael Unneback, unneback@opencores.org              ////
1541
////        ORSoC AB                                              ////
1542
////                                                              ////
1543
//////////////////////////////////////////////////////////////////////
1544
////                                                              ////
1545
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1546
////                                                              ////
1547
//// This source file may be used and distributed without         ////
1548
//// restriction provided that this copyright statement is not    ////
1549
//// removed from the file and that any derivative work contains  ////
1550
//// the original copyright notice and the associated disclaimer. ////
1551
////                                                              ////
1552
//// This source file is free software; you can redistribute it   ////
1553
//// and/or modify it under the terms of the GNU Lesser General   ////
1554
//// Public License as published by the Free Software Foundation; ////
1555
//// either version 2.1 of the License, or (at your option) any   ////
1556
//// later version.                                               ////
1557
////                                                              ////
1558
//// This source is distributed in the hope that it will be       ////
1559
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1560
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1561
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1562
//// details.                                                     ////
1563
////                                                              ////
1564
//// You should have received a copy of the GNU Lesser General    ////
1565
//// Public License along with this source; if not, download it   ////
1566
//// from http://www.opencores.org/lgpl.shtml                     ////
1567
////                                                              ////
1568
//////////////////////////////////////////////////////////////////////
1569
 
1570
// binary counter
1571
 
1572 40 unneback
`define MODULE cnt_bin_clear
1573
module `BASE`MODULE (
1574
`undef MODULE
1575
 clear, q, rst, clk);
1576
 
1577 22 unneback
   parameter length = 4;
1578
   input clear;
1579
   output [length:1] q;
1580
   input rst;
1581
   input clk;
1582
 
1583
   parameter clear_value = 0;
1584
   parameter set_value = 1;
1585
   parameter wrap_value = 0;
1586
   parameter level1_value = 15;
1587
 
1588
   reg  [length:1] qi;
1589
   wire [length:1] q_next;
1590
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1591
 
1592
   always @ (posedge clk or posedge rst)
1593
     if (rst)
1594
       qi <= {length{1'b0}};
1595
     else
1596
       qi <= q_next;
1597
 
1598
   assign q = qi;
1599
 
1600
endmodule
1601 40 unneback
`endif
1602
`ifdef CNT_BIN_CE
1603 22 unneback
//////////////////////////////////////////////////////////////////////
1604
////                                                              ////
1605
////  Versatile counter                                           ////
1606
////                                                              ////
1607
////  Description                                                 ////
1608
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1609
////  counter                                                     ////
1610
////                                                              ////
1611
////  To Do:                                                      ////
1612
////   - add LFSR with more taps                                  ////
1613
////                                                              ////
1614
////  Author(s):                                                  ////
1615
////      - Michael Unneback, unneback@opencores.org              ////
1616
////        ORSoC AB                                              ////
1617
////                                                              ////
1618
//////////////////////////////////////////////////////////////////////
1619
////                                                              ////
1620
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1621
////                                                              ////
1622
//// This source file may be used and distributed without         ////
1623
//// restriction provided that this copyright statement is not    ////
1624
//// removed from the file and that any derivative work contains  ////
1625
//// the original copyright notice and the associated disclaimer. ////
1626
////                                                              ////
1627
//// This source file is free software; you can redistribute it   ////
1628
//// and/or modify it under the terms of the GNU Lesser General   ////
1629
//// Public License as published by the Free Software Foundation; ////
1630
//// either version 2.1 of the License, or (at your option) any   ////
1631
//// later version.                                               ////
1632
////                                                              ////
1633
//// This source is distributed in the hope that it will be       ////
1634
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1635
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1636
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1637
//// details.                                                     ////
1638
////                                                              ////
1639
//// You should have received a copy of the GNU Lesser General    ////
1640
//// Public License along with this source; if not, download it   ////
1641
//// from http://www.opencores.org/lgpl.shtml                     ////
1642
////                                                              ////
1643
//////////////////////////////////////////////////////////////////////
1644
 
1645
// binary counter
1646 6 unneback
 
1647 40 unneback
`define MODULE cnt_bin_ce
1648
module `BASE`MODULE (
1649
`undef MODULE
1650
 cke, q, rst, clk);
1651
 
1652 6 unneback
   parameter length = 4;
1653
   input cke;
1654
   output [length:1] q;
1655
   input rst;
1656
   input clk;
1657
 
1658
   parameter clear_value = 0;
1659
   parameter set_value = 1;
1660
   parameter wrap_value = 0;
1661
   parameter level1_value = 15;
1662
 
1663
   reg  [length:1] qi;
1664
   wire [length:1] q_next;
1665
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1666
 
1667
   always @ (posedge clk or posedge rst)
1668
     if (rst)
1669
       qi <= {length{1'b0}};
1670
     else
1671
     if (cke)
1672
       qi <= q_next;
1673
 
1674
   assign q = qi;
1675
 
1676
endmodule
1677 40 unneback
`endif
1678
`ifdef CNT_BIN_CE_CLEAR
1679 6 unneback
//////////////////////////////////////////////////////////////////////
1680
////                                                              ////
1681
////  Versatile counter                                           ////
1682
////                                                              ////
1683
////  Description                                                 ////
1684
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1685
////  counter                                                     ////
1686
////                                                              ////
1687
////  To Do:                                                      ////
1688
////   - add LFSR with more taps                                  ////
1689
////                                                              ////
1690
////  Author(s):                                                  ////
1691
////      - Michael Unneback, unneback@opencores.org              ////
1692
////        ORSoC AB                                              ////
1693
////                                                              ////
1694
//////////////////////////////////////////////////////////////////////
1695
////                                                              ////
1696
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1697
////                                                              ////
1698
//// This source file may be used and distributed without         ////
1699
//// restriction provided that this copyright statement is not    ////
1700
//// removed from the file and that any derivative work contains  ////
1701
//// the original copyright notice and the associated disclaimer. ////
1702
////                                                              ////
1703
//// This source file is free software; you can redistribute it   ////
1704
//// and/or modify it under the terms of the GNU Lesser General   ////
1705
//// Public License as published by the Free Software Foundation; ////
1706
//// either version 2.1 of the License, or (at your option) any   ////
1707
//// later version.                                               ////
1708
////                                                              ////
1709
//// This source is distributed in the hope that it will be       ////
1710
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1711
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1712
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1713
//// details.                                                     ////
1714
////                                                              ////
1715
//// You should have received a copy of the GNU Lesser General    ////
1716
//// Public License along with this source; if not, download it   ////
1717
//// from http://www.opencores.org/lgpl.shtml                     ////
1718
////                                                              ////
1719
//////////////////////////////////////////////////////////////////////
1720
 
1721
// binary counter
1722
 
1723 40 unneback
`define MODULE cnt_bin_ce_clear
1724
module `BASE`MODULE (
1725
`undef MODULE
1726
 clear, cke, q, rst, clk);
1727
 
1728 6 unneback
   parameter length = 4;
1729
   input clear;
1730
   input cke;
1731
   output [length:1] q;
1732
   input rst;
1733
   input clk;
1734
 
1735
   parameter clear_value = 0;
1736
   parameter set_value = 1;
1737
   parameter wrap_value = 0;
1738
   parameter level1_value = 15;
1739
 
1740
   reg  [length:1] qi;
1741
   wire [length:1] q_next;
1742
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1743
 
1744
   always @ (posedge clk or posedge rst)
1745
     if (rst)
1746
       qi <= {length{1'b0}};
1747
     else
1748
     if (cke)
1749
       qi <= q_next;
1750
 
1751
   assign q = qi;
1752
 
1753
endmodule
1754 40 unneback
`endif
1755
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1756 6 unneback
//////////////////////////////////////////////////////////////////////
1757
////                                                              ////
1758
////  Versatile counter                                           ////
1759
////                                                              ////
1760
////  Description                                                 ////
1761
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1762
////  counter                                                     ////
1763
////                                                              ////
1764
////  To Do:                                                      ////
1765
////   - add LFSR with more taps                                  ////
1766
////                                                              ////
1767
////  Author(s):                                                  ////
1768
////      - Michael Unneback, unneback@opencores.org              ////
1769
////        ORSoC AB                                              ////
1770
////                                                              ////
1771
//////////////////////////////////////////////////////////////////////
1772
////                                                              ////
1773
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1774
////                                                              ////
1775
//// This source file may be used and distributed without         ////
1776
//// restriction provided that this copyright statement is not    ////
1777
//// removed from the file and that any derivative work contains  ////
1778
//// the original copyright notice and the associated disclaimer. ////
1779
////                                                              ////
1780
//// This source file is free software; you can redistribute it   ////
1781
//// and/or modify it under the terms of the GNU Lesser General   ////
1782
//// Public License as published by the Free Software Foundation; ////
1783
//// either version 2.1 of the License, or (at your option) any   ////
1784
//// later version.                                               ////
1785
////                                                              ////
1786
//// This source is distributed in the hope that it will be       ////
1787
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1788
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1789
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1790
//// details.                                                     ////
1791
////                                                              ////
1792
//// You should have received a copy of the GNU Lesser General    ////
1793
//// Public License along with this source; if not, download it   ////
1794
//// from http://www.opencores.org/lgpl.shtml                     ////
1795
////                                                              ////
1796
//////////////////////////////////////////////////////////////////////
1797
 
1798
// binary counter
1799 29 unneback
 
1800 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1801
module `BASE`MODULE (
1802
`undef MODULE
1803
 clear, cke, q, level1, level2, rst, clk);
1804
 
1805 29 unneback
   parameter length = 4;
1806
   input clear;
1807
   input cke;
1808
   output [length:1] q;
1809
   output reg level1;
1810
   output reg level2;
1811
   input rst;
1812
   input clk;
1813
 
1814
   parameter clear_value = 0;
1815
   parameter set_value = 1;
1816 30 unneback
   parameter wrap_value = 15;
1817
   parameter level1_value = 8;
1818
   parameter level2_value = 15;
1819 29 unneback
 
1820
   wire rew;
1821 30 unneback
   assign rew = 1'b0;
1822 29 unneback
   reg  [length:1] qi;
1823
   wire [length:1] q_next;
1824
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1825
 
1826
   always @ (posedge clk or posedge rst)
1827
     if (rst)
1828
       qi <= {length{1'b0}};
1829
     else
1830
     if (cke)
1831
       qi <= q_next;
1832
 
1833
   assign q = qi;
1834
 
1835
 
1836
    always @ (posedge clk or posedge rst)
1837
    if (rst)
1838
        level1 <= 1'b0;
1839
    else
1840
    if (cke)
1841
    if (clear)
1842
        level1 <= 1'b0;
1843
    else if (q_next == level1_value)
1844
        level1 <= 1'b1;
1845
    else if (qi == level1_value & rew)
1846
        level1 <= 1'b0;
1847
 
1848
    always @ (posedge clk or posedge rst)
1849
    if (rst)
1850
        level2 <= 1'b0;
1851
    else
1852
    if (cke)
1853
    if (clear)
1854
        level2 <= 1'b0;
1855
    else if (q_next == level2_value)
1856
        level2 <= 1'b1;
1857
    else if (qi == level2_value & rew)
1858
        level2 <= 1'b0;
1859
endmodule
1860 40 unneback
`endif
1861
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1862 29 unneback
//////////////////////////////////////////////////////////////////////
1863
////                                                              ////
1864
////  Versatile counter                                           ////
1865
////                                                              ////
1866
////  Description                                                 ////
1867
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1868
////  counter                                                     ////
1869
////                                                              ////
1870
////  To Do:                                                      ////
1871
////   - add LFSR with more taps                                  ////
1872
////                                                              ////
1873
////  Author(s):                                                  ////
1874
////      - Michael Unneback, unneback@opencores.org              ////
1875
////        ORSoC AB                                              ////
1876
////                                                              ////
1877
//////////////////////////////////////////////////////////////////////
1878
////                                                              ////
1879
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1880
////                                                              ////
1881
//// This source file may be used and distributed without         ////
1882
//// restriction provided that this copyright statement is not    ////
1883
//// removed from the file and that any derivative work contains  ////
1884
//// the original copyright notice and the associated disclaimer. ////
1885
////                                                              ////
1886
//// This source file is free software; you can redistribute it   ////
1887
//// and/or modify it under the terms of the GNU Lesser General   ////
1888
//// Public License as published by the Free Software Foundation; ////
1889
//// either version 2.1 of the License, or (at your option) any   ////
1890
//// later version.                                               ////
1891
////                                                              ////
1892
//// This source is distributed in the hope that it will be       ////
1893
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1894
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1895
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1896
//// details.                                                     ////
1897
////                                                              ////
1898
//// You should have received a copy of the GNU Lesser General    ////
1899
//// Public License along with this source; if not, download it   ////
1900
//// from http://www.opencores.org/lgpl.shtml                     ////
1901
////                                                              ////
1902
//////////////////////////////////////////////////////////////////////
1903
 
1904
// binary counter
1905 6 unneback
 
1906 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1907
module `BASE`MODULE (
1908
`undef MODULE
1909
 clear, set, cke, rew, q, rst, clk);
1910
 
1911 6 unneback
   parameter length = 4;
1912
   input clear;
1913
   input set;
1914
   input cke;
1915
   input rew;
1916
   output [length:1] q;
1917
   input rst;
1918
   input clk;
1919
 
1920
   parameter clear_value = 0;
1921
   parameter set_value = 1;
1922
   parameter wrap_value = 0;
1923
   parameter level1_value = 15;
1924
 
1925
   reg  [length:1] qi;
1926
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1927
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1928
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1929
   assign q_next = rew ? q_next_rew : q_next_fw;
1930
 
1931
   always @ (posedge clk or posedge rst)
1932
     if (rst)
1933
       qi <= {length{1'b0}};
1934
     else
1935
     if (cke)
1936
       qi <= q_next;
1937
 
1938
   assign q = qi;
1939
 
1940
endmodule
1941 40 unneback
`endif
1942
`ifdef CNT_BIN_CE_REW_L1
1943 6 unneback
//////////////////////////////////////////////////////////////////////
1944
////                                                              ////
1945
////  Versatile counter                                           ////
1946
////                                                              ////
1947
////  Description                                                 ////
1948
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1949
////  counter                                                     ////
1950
////                                                              ////
1951
////  To Do:                                                      ////
1952
////   - add LFSR with more taps                                  ////
1953
////                                                              ////
1954
////  Author(s):                                                  ////
1955
////      - Michael Unneback, unneback@opencores.org              ////
1956
////        ORSoC AB                                              ////
1957
////                                                              ////
1958
//////////////////////////////////////////////////////////////////////
1959
////                                                              ////
1960
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1961
////                                                              ////
1962
//// This source file may be used and distributed without         ////
1963
//// restriction provided that this copyright statement is not    ////
1964
//// removed from the file and that any derivative work contains  ////
1965
//// the original copyright notice and the associated disclaimer. ////
1966
////                                                              ////
1967
//// This source file is free software; you can redistribute it   ////
1968
//// and/or modify it under the terms of the GNU Lesser General   ////
1969
//// Public License as published by the Free Software Foundation; ////
1970
//// either version 2.1 of the License, or (at your option) any   ////
1971
//// later version.                                               ////
1972
////                                                              ////
1973
//// This source is distributed in the hope that it will be       ////
1974
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1975
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1976
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1977
//// details.                                                     ////
1978
////                                                              ////
1979
//// You should have received a copy of the GNU Lesser General    ////
1980
//// Public License along with this source; if not, download it   ////
1981
//// from http://www.opencores.org/lgpl.shtml                     ////
1982
////                                                              ////
1983
//////////////////////////////////////////////////////////////////////
1984
 
1985
// binary counter
1986
 
1987 40 unneback
`define MODULE cnt_bin_ce_rew_l1
1988
module `BASE`MODULE (
1989
`undef MODULE
1990
 cke, rew, level1, rst, clk);
1991
 
1992 6 unneback
   parameter length = 4;
1993
   input cke;
1994
   input rew;
1995
   output reg level1;
1996
   input rst;
1997
   input clk;
1998
 
1999
   parameter clear_value = 0;
2000
   parameter set_value = 1;
2001
   parameter wrap_value = 1;
2002
   parameter level1_value = 15;
2003
 
2004 29 unneback
   wire clear;
2005 30 unneback
   assign clear = 1'b0;
2006 6 unneback
   reg  [length:1] qi;
2007
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2008
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2009
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2010
   assign q_next = rew ? q_next_rew : q_next_fw;
2011
 
2012
   always @ (posedge clk or posedge rst)
2013
     if (rst)
2014
       qi <= {length{1'b0}};
2015
     else
2016
     if (cke)
2017
       qi <= q_next;
2018
 
2019
 
2020
 
2021
    always @ (posedge clk or posedge rst)
2022
    if (rst)
2023
        level1 <= 1'b0;
2024
    else
2025
    if (cke)
2026 29 unneback
    if (clear)
2027
        level1 <= 1'b0;
2028
    else if (q_next == level1_value)
2029 6 unneback
        level1 <= 1'b1;
2030
    else if (qi == level1_value & rew)
2031
        level1 <= 1'b0;
2032
endmodule
2033 40 unneback
`endif
2034
`ifdef CNT_BIN_CE_REW_ZQ_L1
2035 6 unneback
//////////////////////////////////////////////////////////////////////
2036
////                                                              ////
2037
////  Versatile counter                                           ////
2038
////                                                              ////
2039
////  Description                                                 ////
2040
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2041
////  counter                                                     ////
2042
////                                                              ////
2043
////  To Do:                                                      ////
2044
////   - add LFSR with more taps                                  ////
2045
////                                                              ////
2046
////  Author(s):                                                  ////
2047
////      - Michael Unneback, unneback@opencores.org              ////
2048
////        ORSoC AB                                              ////
2049
////                                                              ////
2050
//////////////////////////////////////////////////////////////////////
2051
////                                                              ////
2052
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2053
////                                                              ////
2054
//// This source file may be used and distributed without         ////
2055
//// restriction provided that this copyright statement is not    ////
2056
//// removed from the file and that any derivative work contains  ////
2057
//// the original copyright notice and the associated disclaimer. ////
2058
////                                                              ////
2059
//// This source file is free software; you can redistribute it   ////
2060
//// and/or modify it under the terms of the GNU Lesser General   ////
2061
//// Public License as published by the Free Software Foundation; ////
2062
//// either version 2.1 of the License, or (at your option) any   ////
2063
//// later version.                                               ////
2064
////                                                              ////
2065
//// This source is distributed in the hope that it will be       ////
2066
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2067
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2068
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2069
//// details.                                                     ////
2070
////                                                              ////
2071
//// You should have received a copy of the GNU Lesser General    ////
2072
//// Public License along with this source; if not, download it   ////
2073
//// from http://www.opencores.org/lgpl.shtml                     ////
2074
////                                                              ////
2075
//////////////////////////////////////////////////////////////////////
2076
 
2077 25 unneback
// binary counter
2078
 
2079 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2080
module `BASE`MODULE (
2081
`undef MODULE
2082
 cke, rew, zq, level1, rst, clk);
2083
 
2084 25 unneback
   parameter length = 4;
2085
   input cke;
2086
   input rew;
2087
   output reg zq;
2088
   output reg level1;
2089
   input rst;
2090
   input clk;
2091
 
2092
   parameter clear_value = 0;
2093
   parameter set_value = 1;
2094
   parameter wrap_value = 1;
2095
   parameter level1_value = 15;
2096
 
2097 29 unneback
   wire clear;
2098 30 unneback
   assign clear = 1'b0;
2099 25 unneback
   reg  [length:1] qi;
2100
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2101
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2102
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2103
   assign q_next = rew ? q_next_rew : q_next_fw;
2104
 
2105
   always @ (posedge clk or posedge rst)
2106
     if (rst)
2107
       qi <= {length{1'b0}};
2108
     else
2109
     if (cke)
2110
       qi <= q_next;
2111
 
2112
 
2113
 
2114
   always @ (posedge clk or posedge rst)
2115
     if (rst)
2116
       zq <= 1'b1;
2117
     else
2118
     if (cke)
2119
       zq <= q_next == {length{1'b0}};
2120
 
2121
    always @ (posedge clk or posedge rst)
2122
    if (rst)
2123
        level1 <= 1'b0;
2124
    else
2125
    if (cke)
2126 29 unneback
    if (clear)
2127
        level1 <= 1'b0;
2128
    else if (q_next == level1_value)
2129 25 unneback
        level1 <= 1'b1;
2130
    else if (qi == level1_value & rew)
2131
        level1 <= 1'b0;
2132
endmodule
2133 40 unneback
`endif
2134
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2135 25 unneback
//////////////////////////////////////////////////////////////////////
2136
////                                                              ////
2137
////  Versatile counter                                           ////
2138
////                                                              ////
2139
////  Description                                                 ////
2140
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2141
////  counter                                                     ////
2142
////                                                              ////
2143
////  To Do:                                                      ////
2144
////   - add LFSR with more taps                                  ////
2145
////                                                              ////
2146
////  Author(s):                                                  ////
2147
////      - Michael Unneback, unneback@opencores.org              ////
2148
////        ORSoC AB                                              ////
2149
////                                                              ////
2150
//////////////////////////////////////////////////////////////////////
2151
////                                                              ////
2152
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2153
////                                                              ////
2154
//// This source file may be used and distributed without         ////
2155
//// restriction provided that this copyright statement is not    ////
2156
//// removed from the file and that any derivative work contains  ////
2157
//// the original copyright notice and the associated disclaimer. ////
2158
////                                                              ////
2159
//// This source file is free software; you can redistribute it   ////
2160
//// and/or modify it under the terms of the GNU Lesser General   ////
2161
//// Public License as published by the Free Software Foundation; ////
2162
//// either version 2.1 of the License, or (at your option) any   ////
2163
//// later version.                                               ////
2164
////                                                              ////
2165
//// This source is distributed in the hope that it will be       ////
2166
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2167
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2168
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2169
//// details.                                                     ////
2170
////                                                              ////
2171
//// You should have received a copy of the GNU Lesser General    ////
2172
//// Public License along with this source; if not, download it   ////
2173
//// from http://www.opencores.org/lgpl.shtml                     ////
2174
////                                                              ////
2175
//////////////////////////////////////////////////////////////////////
2176
 
2177
// binary counter
2178
 
2179 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2180
module `BASE`MODULE (
2181
`undef MODULE
2182
 cke, rew, q, zq, level1, rst, clk);
2183
 
2184 25 unneback
   parameter length = 4;
2185
   input cke;
2186
   input rew;
2187
   output [length:1] q;
2188
   output reg zq;
2189
   output reg level1;
2190
   input rst;
2191
   input clk;
2192
 
2193
   parameter clear_value = 0;
2194
   parameter set_value = 1;
2195
   parameter wrap_value = 1;
2196
   parameter level1_value = 15;
2197
 
2198 29 unneback
   wire clear;
2199 30 unneback
   assign clear = 1'b0;
2200 25 unneback
   reg  [length:1] qi;
2201
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2202
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2203
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2204
   assign q_next = rew ? q_next_rew : q_next_fw;
2205
 
2206
   always @ (posedge clk or posedge rst)
2207
     if (rst)
2208
       qi <= {length{1'b0}};
2209
     else
2210
     if (cke)
2211
       qi <= q_next;
2212
 
2213
   assign q = qi;
2214
 
2215
 
2216
   always @ (posedge clk or posedge rst)
2217
     if (rst)
2218
       zq <= 1'b1;
2219
     else
2220
     if (cke)
2221
       zq <= q_next == {length{1'b0}};
2222
 
2223
    always @ (posedge clk or posedge rst)
2224
    if (rst)
2225
        level1 <= 1'b0;
2226
    else
2227
    if (cke)
2228 29 unneback
    if (clear)
2229
        level1 <= 1'b0;
2230
    else if (q_next == level1_value)
2231 25 unneback
        level1 <= 1'b1;
2232
    else if (qi == level1_value & rew)
2233
        level1 <= 1'b0;
2234
endmodule
2235 40 unneback
`endif
2236
`ifdef CNT_LFSR_ZQ
2237 25 unneback
//////////////////////////////////////////////////////////////////////
2238
////                                                              ////
2239
////  Versatile counter                                           ////
2240
////                                                              ////
2241
////  Description                                                 ////
2242
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2243
////  counter                                                     ////
2244
////                                                              ////
2245
////  To Do:                                                      ////
2246
////   - add LFSR with more taps                                  ////
2247
////                                                              ////
2248
////  Author(s):                                                  ////
2249
////      - Michael Unneback, unneback@opencores.org              ////
2250
////        ORSoC AB                                              ////
2251
////                                                              ////
2252
//////////////////////////////////////////////////////////////////////
2253
////                                                              ////
2254
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2255
////                                                              ////
2256
//// This source file may be used and distributed without         ////
2257
//// restriction provided that this copyright statement is not    ////
2258
//// removed from the file and that any derivative work contains  ////
2259
//// the original copyright notice and the associated disclaimer. ////
2260
////                                                              ////
2261
//// This source file is free software; you can redistribute it   ////
2262
//// and/or modify it under the terms of the GNU Lesser General   ////
2263
//// Public License as published by the Free Software Foundation; ////
2264
//// either version 2.1 of the License, or (at your option) any   ////
2265
//// later version.                                               ////
2266
////                                                              ////
2267
//// This source is distributed in the hope that it will be       ////
2268
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2269
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2270
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2271
//// details.                                                     ////
2272
////                                                              ////
2273
//// You should have received a copy of the GNU Lesser General    ////
2274
//// Public License along with this source; if not, download it   ////
2275
//// from http://www.opencores.org/lgpl.shtml                     ////
2276
////                                                              ////
2277
//////////////////////////////////////////////////////////////////////
2278
 
2279 6 unneback
// LFSR counter
2280
 
2281 40 unneback
`define MODULE cnt_lfsr_zq
2282
module `BASE`MODULE (
2283
`undef MODULE
2284
 zq, rst, clk);
2285
 
2286 6 unneback
   parameter length = 4;
2287
   output reg zq;
2288
   input rst;
2289
   input clk;
2290
 
2291
   parameter clear_value = 0;
2292
   parameter set_value = 1;
2293
   parameter wrap_value = 8;
2294
   parameter level1_value = 15;
2295
 
2296
   reg  [length:1] qi;
2297
   reg lfsr_fb;
2298
   wire [length:1] q_next;
2299
   reg [32:1] polynom;
2300
   integer i;
2301
 
2302
   always @ (qi)
2303
   begin
2304
        case (length)
2305
         2: polynom = 32'b11;                               // 0x3
2306
         3: polynom = 32'b110;                              // 0x6
2307
         4: polynom = 32'b1100;                             // 0xC
2308
         5: polynom = 32'b10100;                            // 0x14
2309
         6: polynom = 32'b110000;                           // 0x30
2310
         7: polynom = 32'b1100000;                          // 0x60
2311
         8: polynom = 32'b10111000;                         // 0xb8
2312
         9: polynom = 32'b100010000;                        // 0x110
2313
        10: polynom = 32'b1001000000;                       // 0x240
2314
        11: polynom = 32'b10100000000;                      // 0x500
2315
        12: polynom = 32'b100000101001;                     // 0x829
2316
        13: polynom = 32'b1000000001100;                    // 0x100C
2317
        14: polynom = 32'b10000000010101;                   // 0x2015
2318
        15: polynom = 32'b110000000000000;                  // 0x6000
2319
        16: polynom = 32'b1101000000001000;                 // 0xD008
2320
        17: polynom = 32'b10010000000000000;                // 0x12000
2321
        18: polynom = 32'b100000010000000000;               // 0x20400
2322
        19: polynom = 32'b1000000000000100011;              // 0x40023
2323 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2324 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2325
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2326
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2327
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2328
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2329
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2330
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2331
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2332
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2333
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2334
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2335
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2336
        default: polynom = 32'b0;
2337
        endcase
2338
        lfsr_fb = qi[length];
2339
        for (i=length-1; i>=1; i=i-1) begin
2340
            if (polynom[i])
2341
                lfsr_fb = lfsr_fb  ~^ qi[i];
2342
        end
2343
    end
2344
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2345
 
2346
   always @ (posedge clk or posedge rst)
2347
     if (rst)
2348
       qi <= {length{1'b0}};
2349
     else
2350
       qi <= q_next;
2351
 
2352
 
2353
 
2354
   always @ (posedge clk or posedge rst)
2355
     if (rst)
2356
       zq <= 1'b1;
2357
     else
2358
       zq <= q_next == {length{1'b0}};
2359
endmodule
2360 40 unneback
`endif
2361
`ifdef CNT_LFSR_CE_ZQ
2362 6 unneback
//////////////////////////////////////////////////////////////////////
2363
////                                                              ////
2364
////  Versatile counter                                           ////
2365
////                                                              ////
2366
////  Description                                                 ////
2367
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2368
////  counter                                                     ////
2369
////                                                              ////
2370
////  To Do:                                                      ////
2371
////   - add LFSR with more taps                                  ////
2372
////                                                              ////
2373
////  Author(s):                                                  ////
2374
////      - Michael Unneback, unneback@opencores.org              ////
2375
////        ORSoC AB                                              ////
2376
////                                                              ////
2377
//////////////////////////////////////////////////////////////////////
2378
////                                                              ////
2379
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2380
////                                                              ////
2381
//// This source file may be used and distributed without         ////
2382
//// restriction provided that this copyright statement is not    ////
2383
//// removed from the file and that any derivative work contains  ////
2384
//// the original copyright notice and the associated disclaimer. ////
2385
////                                                              ////
2386
//// This source file is free software; you can redistribute it   ////
2387
//// and/or modify it under the terms of the GNU Lesser General   ////
2388
//// Public License as published by the Free Software Foundation; ////
2389
//// either version 2.1 of the License, or (at your option) any   ////
2390
//// later version.                                               ////
2391
////                                                              ////
2392
//// This source is distributed in the hope that it will be       ////
2393
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2394
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2395
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2396
//// details.                                                     ////
2397
////                                                              ////
2398
//// You should have received a copy of the GNU Lesser General    ////
2399
//// Public License along with this source; if not, download it   ////
2400
//// from http://www.opencores.org/lgpl.shtml                     ////
2401
////                                                              ////
2402
//////////////////////////////////////////////////////////////////////
2403
 
2404
// LFSR counter
2405
 
2406 40 unneback
`define MODULE cnt_lfsr_ce_zq
2407
module `BASE`MODULE (
2408
`undef MODULE
2409
 cke, zq, rst, clk);
2410
 
2411 6 unneback
   parameter length = 4;
2412
   input cke;
2413
   output reg zq;
2414
   input rst;
2415
   input clk;
2416
 
2417
   parameter clear_value = 0;
2418
   parameter set_value = 1;
2419
   parameter wrap_value = 8;
2420
   parameter level1_value = 15;
2421
 
2422
   reg  [length:1] qi;
2423
   reg lfsr_fb;
2424
   wire [length:1] q_next;
2425
   reg [32:1] polynom;
2426
   integer i;
2427
 
2428
   always @ (qi)
2429
   begin
2430
        case (length)
2431
         2: polynom = 32'b11;                               // 0x3
2432
         3: polynom = 32'b110;                              // 0x6
2433
         4: polynom = 32'b1100;                             // 0xC
2434
         5: polynom = 32'b10100;                            // 0x14
2435
         6: polynom = 32'b110000;                           // 0x30
2436
         7: polynom = 32'b1100000;                          // 0x60
2437
         8: polynom = 32'b10111000;                         // 0xb8
2438
         9: polynom = 32'b100010000;                        // 0x110
2439
        10: polynom = 32'b1001000000;                       // 0x240
2440
        11: polynom = 32'b10100000000;                      // 0x500
2441
        12: polynom = 32'b100000101001;                     // 0x829
2442
        13: polynom = 32'b1000000001100;                    // 0x100C
2443
        14: polynom = 32'b10000000010101;                   // 0x2015
2444
        15: polynom = 32'b110000000000000;                  // 0x6000
2445
        16: polynom = 32'b1101000000001000;                 // 0xD008
2446
        17: polynom = 32'b10010000000000000;                // 0x12000
2447
        18: polynom = 32'b100000010000000000;               // 0x20400
2448
        19: polynom = 32'b1000000000000100011;              // 0x40023
2449 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2450 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2451
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2452
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2453
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2454
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2455
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2456
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2457
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2458
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2459
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2460
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2461
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2462
        default: polynom = 32'b0;
2463
        endcase
2464
        lfsr_fb = qi[length];
2465
        for (i=length-1; i>=1; i=i-1) begin
2466
            if (polynom[i])
2467
                lfsr_fb = lfsr_fb  ~^ qi[i];
2468
        end
2469
    end
2470
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2471
 
2472
   always @ (posedge clk or posedge rst)
2473
     if (rst)
2474
       qi <= {length{1'b0}};
2475
     else
2476
     if (cke)
2477
       qi <= q_next;
2478
 
2479
 
2480
 
2481
   always @ (posedge clk or posedge rst)
2482
     if (rst)
2483
       zq <= 1'b1;
2484
     else
2485
     if (cke)
2486
       zq <= q_next == {length{1'b0}};
2487
endmodule
2488 40 unneback
`endif
2489
`ifdef CNT_LFSR_CE_Q
2490 6 unneback
//////////////////////////////////////////////////////////////////////
2491
////                                                              ////
2492
////  Versatile counter                                           ////
2493
////                                                              ////
2494
////  Description                                                 ////
2495
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2496
////  counter                                                     ////
2497
////                                                              ////
2498
////  To Do:                                                      ////
2499
////   - add LFSR with more taps                                  ////
2500
////                                                              ////
2501
////  Author(s):                                                  ////
2502
////      - Michael Unneback, unneback@opencores.org              ////
2503
////        ORSoC AB                                              ////
2504
////                                                              ////
2505
//////////////////////////////////////////////////////////////////////
2506
////                                                              ////
2507
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2508
////                                                              ////
2509
//// This source file may be used and distributed without         ////
2510
//// restriction provided that this copyright statement is not    ////
2511
//// removed from the file and that any derivative work contains  ////
2512
//// the original copyright notice and the associated disclaimer. ////
2513
////                                                              ////
2514
//// This source file is free software; you can redistribute it   ////
2515
//// and/or modify it under the terms of the GNU Lesser General   ////
2516
//// Public License as published by the Free Software Foundation; ////
2517
//// either version 2.1 of the License, or (at your option) any   ////
2518
//// later version.                                               ////
2519
////                                                              ////
2520
//// This source is distributed in the hope that it will be       ////
2521
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2522
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2523
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2524
//// details.                                                     ////
2525
////                                                              ////
2526
//// You should have received a copy of the GNU Lesser General    ////
2527
//// Public License along with this source; if not, download it   ////
2528
//// from http://www.opencores.org/lgpl.shtml                     ////
2529
////                                                              ////
2530
//////////////////////////////////////////////////////////////////////
2531 22 unneback
 
2532
// LFSR counter
2533 27 unneback
 
2534 40 unneback
`define MODULE cnt_lfsr_ce_q
2535
module `BASE`MODULE (
2536
`undef MODULE
2537
 cke, q, rst, clk);
2538
 
2539 27 unneback
   parameter length = 4;
2540
   input cke;
2541
   output [length:1] q;
2542
   input rst;
2543
   input clk;
2544
 
2545
   parameter clear_value = 0;
2546
   parameter set_value = 1;
2547
   parameter wrap_value = 8;
2548
   parameter level1_value = 15;
2549
 
2550
   reg  [length:1] qi;
2551
   reg lfsr_fb;
2552
   wire [length:1] q_next;
2553
   reg [32:1] polynom;
2554
   integer i;
2555
 
2556
   always @ (qi)
2557
   begin
2558
        case (length)
2559
         2: polynom = 32'b11;                               // 0x3
2560
         3: polynom = 32'b110;                              // 0x6
2561
         4: polynom = 32'b1100;                             // 0xC
2562
         5: polynom = 32'b10100;                            // 0x14
2563
         6: polynom = 32'b110000;                           // 0x30
2564
         7: polynom = 32'b1100000;                          // 0x60
2565
         8: polynom = 32'b10111000;                         // 0xb8
2566
         9: polynom = 32'b100010000;                        // 0x110
2567
        10: polynom = 32'b1001000000;                       // 0x240
2568
        11: polynom = 32'b10100000000;                      // 0x500
2569
        12: polynom = 32'b100000101001;                     // 0x829
2570
        13: polynom = 32'b1000000001100;                    // 0x100C
2571
        14: polynom = 32'b10000000010101;                   // 0x2015
2572
        15: polynom = 32'b110000000000000;                  // 0x6000
2573
        16: polynom = 32'b1101000000001000;                 // 0xD008
2574
        17: polynom = 32'b10010000000000000;                // 0x12000
2575
        18: polynom = 32'b100000010000000000;               // 0x20400
2576
        19: polynom = 32'b1000000000000100011;              // 0x40023
2577 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2578 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2579
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2580
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2581
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2582
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2583
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2584
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2585
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2586
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2587
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2588
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2589
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2590
        default: polynom = 32'b0;
2591
        endcase
2592
        lfsr_fb = qi[length];
2593
        for (i=length-1; i>=1; i=i-1) begin
2594
            if (polynom[i])
2595
                lfsr_fb = lfsr_fb  ~^ qi[i];
2596
        end
2597
    end
2598
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2599
 
2600
   always @ (posedge clk or posedge rst)
2601
     if (rst)
2602
       qi <= {length{1'b0}};
2603
     else
2604
     if (cke)
2605
       qi <= q_next;
2606
 
2607
   assign q = qi;
2608
 
2609
endmodule
2610 40 unneback
`endif
2611
`ifdef CNT_LFSR_CE_CLEAR_Q
2612 27 unneback
//////////////////////////////////////////////////////////////////////
2613
////                                                              ////
2614
////  Versatile counter                                           ////
2615
////                                                              ////
2616
////  Description                                                 ////
2617
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2618
////  counter                                                     ////
2619
////                                                              ////
2620
////  To Do:                                                      ////
2621
////   - add LFSR with more taps                                  ////
2622
////                                                              ////
2623
////  Author(s):                                                  ////
2624
////      - Michael Unneback, unneback@opencores.org              ////
2625
////        ORSoC AB                                              ////
2626
////                                                              ////
2627
//////////////////////////////////////////////////////////////////////
2628
////                                                              ////
2629
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2630
////                                                              ////
2631
//// This source file may be used and distributed without         ////
2632
//// restriction provided that this copyright statement is not    ////
2633
//// removed from the file and that any derivative work contains  ////
2634
//// the original copyright notice and the associated disclaimer. ////
2635
////                                                              ////
2636
//// This source file is free software; you can redistribute it   ////
2637
//// and/or modify it under the terms of the GNU Lesser General   ////
2638
//// Public License as published by the Free Software Foundation; ////
2639
//// either version 2.1 of the License, or (at your option) any   ////
2640
//// later version.                                               ////
2641
////                                                              ////
2642
//// This source is distributed in the hope that it will be       ////
2643
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2644
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2645
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2646
//// details.                                                     ////
2647
////                                                              ////
2648
//// You should have received a copy of the GNU Lesser General    ////
2649
//// Public License along with this source; if not, download it   ////
2650
//// from http://www.opencores.org/lgpl.shtml                     ////
2651
////                                                              ////
2652
//////////////////////////////////////////////////////////////////////
2653
 
2654
// LFSR counter
2655
 
2656 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2657
module `BASE`MODULE (
2658
`undef MODULE
2659
 clear, cke, q, rst, clk);
2660
 
2661 27 unneback
   parameter length = 4;
2662
   input clear;
2663
   input cke;
2664
   output [length:1] q;
2665
   input rst;
2666
   input clk;
2667
 
2668
   parameter clear_value = 0;
2669
   parameter set_value = 1;
2670
   parameter wrap_value = 8;
2671
   parameter level1_value = 15;
2672
 
2673
   reg  [length:1] qi;
2674
   reg lfsr_fb;
2675
   wire [length:1] q_next;
2676
   reg [32:1] polynom;
2677
   integer i;
2678
 
2679
   always @ (qi)
2680
   begin
2681
        case (length)
2682
         2: polynom = 32'b11;                               // 0x3
2683
         3: polynom = 32'b110;                              // 0x6
2684
         4: polynom = 32'b1100;                             // 0xC
2685
         5: polynom = 32'b10100;                            // 0x14
2686
         6: polynom = 32'b110000;                           // 0x30
2687
         7: polynom = 32'b1100000;                          // 0x60
2688
         8: polynom = 32'b10111000;                         // 0xb8
2689
         9: polynom = 32'b100010000;                        // 0x110
2690
        10: polynom = 32'b1001000000;                       // 0x240
2691
        11: polynom = 32'b10100000000;                      // 0x500
2692
        12: polynom = 32'b100000101001;                     // 0x829
2693
        13: polynom = 32'b1000000001100;                    // 0x100C
2694
        14: polynom = 32'b10000000010101;                   // 0x2015
2695
        15: polynom = 32'b110000000000000;                  // 0x6000
2696
        16: polynom = 32'b1101000000001000;                 // 0xD008
2697
        17: polynom = 32'b10010000000000000;                // 0x12000
2698
        18: polynom = 32'b100000010000000000;               // 0x20400
2699
        19: polynom = 32'b1000000000000100011;              // 0x40023
2700 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2701 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2702
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2703
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2704
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2705
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2706
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2707
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2708
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2709
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2710
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2711
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2712
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2713
        default: polynom = 32'b0;
2714
        endcase
2715
        lfsr_fb = qi[length];
2716
        for (i=length-1; i>=1; i=i-1) begin
2717
            if (polynom[i])
2718
                lfsr_fb = lfsr_fb  ~^ qi[i];
2719
        end
2720
    end
2721
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2722
 
2723
   always @ (posedge clk or posedge rst)
2724
     if (rst)
2725
       qi <= {length{1'b0}};
2726
     else
2727
     if (cke)
2728
       qi <= q_next;
2729
 
2730
   assign q = qi;
2731
 
2732
endmodule
2733 40 unneback
`endif
2734
`ifdef CNT_LFSR_CE_Q_ZQ
2735 27 unneback
//////////////////////////////////////////////////////////////////////
2736
////                                                              ////
2737
////  Versatile counter                                           ////
2738
////                                                              ////
2739
////  Description                                                 ////
2740
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2741
////  counter                                                     ////
2742
////                                                              ////
2743
////  To Do:                                                      ////
2744
////   - add LFSR with more taps                                  ////
2745
////                                                              ////
2746
////  Author(s):                                                  ////
2747
////      - Michael Unneback, unneback@opencores.org              ////
2748
////        ORSoC AB                                              ////
2749
////                                                              ////
2750
//////////////////////////////////////////////////////////////////////
2751
////                                                              ////
2752
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2753
////                                                              ////
2754
//// This source file may be used and distributed without         ////
2755
//// restriction provided that this copyright statement is not    ////
2756
//// removed from the file and that any derivative work contains  ////
2757
//// the original copyright notice and the associated disclaimer. ////
2758
////                                                              ////
2759
//// This source file is free software; you can redistribute it   ////
2760
//// and/or modify it under the terms of the GNU Lesser General   ////
2761
//// Public License as published by the Free Software Foundation; ////
2762
//// either version 2.1 of the License, or (at your option) any   ////
2763
//// later version.                                               ////
2764
////                                                              ////
2765
//// This source is distributed in the hope that it will be       ////
2766
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2767
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2768
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2769
//// details.                                                     ////
2770
////                                                              ////
2771
//// You should have received a copy of the GNU Lesser General    ////
2772
//// Public License along with this source; if not, download it   ////
2773
//// from http://www.opencores.org/lgpl.shtml                     ////
2774
////                                                              ////
2775
//////////////////////////////////////////////////////////////////////
2776
 
2777
// LFSR counter
2778 22 unneback
 
2779 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
2780
module `BASE`MODULE (
2781
`undef MODULE
2782
 cke, q, zq, rst, clk);
2783
 
2784 22 unneback
   parameter length = 4;
2785
   input cke;
2786
   output [length:1] q;
2787
   output reg zq;
2788
   input rst;
2789
   input clk;
2790
 
2791
   parameter clear_value = 0;
2792
   parameter set_value = 1;
2793
   parameter wrap_value = 8;
2794
   parameter level1_value = 15;
2795
 
2796
   reg  [length:1] qi;
2797
   reg lfsr_fb;
2798
   wire [length:1] q_next;
2799
   reg [32:1] polynom;
2800
   integer i;
2801
 
2802
   always @ (qi)
2803
   begin
2804
        case (length)
2805
         2: polynom = 32'b11;                               // 0x3
2806
         3: polynom = 32'b110;                              // 0x6
2807
         4: polynom = 32'b1100;                             // 0xC
2808
         5: polynom = 32'b10100;                            // 0x14
2809
         6: polynom = 32'b110000;                           // 0x30
2810
         7: polynom = 32'b1100000;                          // 0x60
2811
         8: polynom = 32'b10111000;                         // 0xb8
2812
         9: polynom = 32'b100010000;                        // 0x110
2813
        10: polynom = 32'b1001000000;                       // 0x240
2814
        11: polynom = 32'b10100000000;                      // 0x500
2815
        12: polynom = 32'b100000101001;                     // 0x829
2816
        13: polynom = 32'b1000000001100;                    // 0x100C
2817
        14: polynom = 32'b10000000010101;                   // 0x2015
2818
        15: polynom = 32'b110000000000000;                  // 0x6000
2819
        16: polynom = 32'b1101000000001000;                 // 0xD008
2820
        17: polynom = 32'b10010000000000000;                // 0x12000
2821
        18: polynom = 32'b100000010000000000;               // 0x20400
2822
        19: polynom = 32'b1000000000000100011;              // 0x40023
2823 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2824 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2825
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2826
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2827
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2828
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2829
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2830
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2831
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2832
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2833
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2834
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2835
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2836
        default: polynom = 32'b0;
2837
        endcase
2838
        lfsr_fb = qi[length];
2839
        for (i=length-1; i>=1; i=i-1) begin
2840
            if (polynom[i])
2841
                lfsr_fb = lfsr_fb  ~^ qi[i];
2842
        end
2843
    end
2844
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2845
 
2846
   always @ (posedge clk or posedge rst)
2847
     if (rst)
2848
       qi <= {length{1'b0}};
2849
     else
2850
     if (cke)
2851
       qi <= q_next;
2852
 
2853
   assign q = qi;
2854
 
2855
 
2856
   always @ (posedge clk or posedge rst)
2857
     if (rst)
2858
       zq <= 1'b1;
2859
     else
2860
     if (cke)
2861
       zq <= q_next == {length{1'b0}};
2862
endmodule
2863 40 unneback
`endif
2864
`ifdef CNT_LFSR_CE_REW_L1
2865 22 unneback
//////////////////////////////////////////////////////////////////////
2866
////                                                              ////
2867
////  Versatile counter                                           ////
2868
////                                                              ////
2869
////  Description                                                 ////
2870
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2871
////  counter                                                     ////
2872
////                                                              ////
2873
////  To Do:                                                      ////
2874
////   - add LFSR with more taps                                  ////
2875
////                                                              ////
2876
////  Author(s):                                                  ////
2877
////      - Michael Unneback, unneback@opencores.org              ////
2878
////        ORSoC AB                                              ////
2879
////                                                              ////
2880
//////////////////////////////////////////////////////////////////////
2881
////                                                              ////
2882
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2883
////                                                              ////
2884
//// This source file may be used and distributed without         ////
2885
//// restriction provided that this copyright statement is not    ////
2886
//// removed from the file and that any derivative work contains  ////
2887
//// the original copyright notice and the associated disclaimer. ////
2888
////                                                              ////
2889
//// This source file is free software; you can redistribute it   ////
2890
//// and/or modify it under the terms of the GNU Lesser General   ////
2891
//// Public License as published by the Free Software Foundation; ////
2892
//// either version 2.1 of the License, or (at your option) any   ////
2893
//// later version.                                               ////
2894
////                                                              ////
2895
//// This source is distributed in the hope that it will be       ////
2896
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2897
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2898
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2899
//// details.                                                     ////
2900
////                                                              ////
2901
//// You should have received a copy of the GNU Lesser General    ////
2902
//// Public License along with this source; if not, download it   ////
2903
//// from http://www.opencores.org/lgpl.shtml                     ////
2904
////                                                              ////
2905
//////////////////////////////////////////////////////////////////////
2906 6 unneback
 
2907
// LFSR counter
2908
 
2909 40 unneback
`define MODULE cnt_lfsr_ce_rew_l1
2910
module `BASE`MODULE (
2911
`undef MODULE
2912
 cke, rew, level1, rst, clk);
2913
 
2914 6 unneback
   parameter length = 4;
2915
   input cke;
2916
   input rew;
2917
   output reg level1;
2918
   input rst;
2919
   input clk;
2920
 
2921
   parameter clear_value = 0;
2922
   parameter set_value = 1;
2923
   parameter wrap_value = 8;
2924
   parameter level1_value = 15;
2925
 
2926 29 unneback
   wire clear;
2927 30 unneback
   assign clear = 1'b0;
2928 6 unneback
   reg  [length:1] qi;
2929
   reg lfsr_fb, lfsr_fb_rew;
2930
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2931
   reg [32:1] polynom_rew;
2932
   integer j;
2933
   reg [32:1] polynom;
2934
   integer i;
2935
 
2936
   always @ (qi)
2937
   begin
2938
        case (length)
2939
         2: polynom = 32'b11;                               // 0x3
2940
         3: polynom = 32'b110;                              // 0x6
2941
         4: polynom = 32'b1100;                             // 0xC
2942
         5: polynom = 32'b10100;                            // 0x14
2943
         6: polynom = 32'b110000;                           // 0x30
2944
         7: polynom = 32'b1100000;                          // 0x60
2945
         8: polynom = 32'b10111000;                         // 0xb8
2946
         9: polynom = 32'b100010000;                        // 0x110
2947
        10: polynom = 32'b1001000000;                       // 0x240
2948
        11: polynom = 32'b10100000000;                      // 0x500
2949
        12: polynom = 32'b100000101001;                     // 0x829
2950
        13: polynom = 32'b1000000001100;                    // 0x100C
2951
        14: polynom = 32'b10000000010101;                   // 0x2015
2952
        15: polynom = 32'b110000000000000;                  // 0x6000
2953
        16: polynom = 32'b1101000000001000;                 // 0xD008
2954
        17: polynom = 32'b10010000000000000;                // 0x12000
2955
        18: polynom = 32'b100000010000000000;               // 0x20400
2956
        19: polynom = 32'b1000000000000100011;              // 0x40023
2957 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2958 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2959
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2960
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2961
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2962
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2963
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2964
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2965
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2966
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2967
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2968
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2969
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2970
        default: polynom = 32'b0;
2971
        endcase
2972
        lfsr_fb = qi[length];
2973
        for (i=length-1; i>=1; i=i-1) begin
2974
            if (polynom[i])
2975
                lfsr_fb = lfsr_fb  ~^ qi[i];
2976
        end
2977
    end
2978
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2979
   always @ (qi)
2980
   begin
2981
        case (length)
2982
         2: polynom_rew = 32'b11;
2983
         3: polynom_rew = 32'b110;
2984
         4: polynom_rew = 32'b1100;
2985
         5: polynom_rew = 32'b10100;
2986
         6: polynom_rew = 32'b110000;
2987
         7: polynom_rew = 32'b1100000;
2988
         8: polynom_rew = 32'b10111000;
2989
         9: polynom_rew = 32'b100010000;
2990
        10: polynom_rew = 32'b1001000000;
2991
        11: polynom_rew = 32'b10100000000;
2992
        12: polynom_rew = 32'b100000101001;
2993
        13: polynom_rew = 32'b1000000001100;
2994
        14: polynom_rew = 32'b10000000010101;
2995
        15: polynom_rew = 32'b110000000000000;
2996
        16: polynom_rew = 32'b1101000000001000;
2997
        17: polynom_rew = 32'b10010000000000000;
2998
        18: polynom_rew = 32'b100000010000000000;
2999
        19: polynom_rew = 32'b1000000000000100011;
3000
        20: polynom_rew = 32'b10000010000000000000;
3001
        21: polynom_rew = 32'b101000000000000000000;
3002
        22: polynom_rew = 32'b1100000000000000000000;
3003
        23: polynom_rew = 32'b10000100000000000000000;
3004
        24: polynom_rew = 32'b111000010000000000000000;
3005
        25: polynom_rew = 32'b1001000000000000000000000;
3006
        26: polynom_rew = 32'b10000000000000000000100011;
3007
        27: polynom_rew = 32'b100000000000000000000010011;
3008
        28: polynom_rew = 32'b1100100000000000000000000000;
3009
        29: polynom_rew = 32'b10100000000000000000000000000;
3010
        30: polynom_rew = 32'b100000000000000000000000101001;
3011
        31: polynom_rew = 32'b1001000000000000000000000000000;
3012
        32: polynom_rew = 32'b10000000001000000000000000000011;
3013
        default: polynom_rew = 32'b0;
3014
        endcase
3015
        // rotate left
3016
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3017
        lfsr_fb_rew = qi[length];
3018
        for (i=length-1; i>=1; i=i-1) begin
3019
            if (polynom_rew[i])
3020
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3021
        end
3022
    end
3023
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3024
   assign q_next = rew ? q_next_rew : q_next_fw;
3025
 
3026
   always @ (posedge clk or posedge rst)
3027
     if (rst)
3028
       qi <= {length{1'b0}};
3029
     else
3030
     if (cke)
3031
       qi <= q_next;
3032
 
3033
 
3034
 
3035
    always @ (posedge clk or posedge rst)
3036
    if (rst)
3037
        level1 <= 1'b0;
3038
    else
3039
    if (cke)
3040 29 unneback
    if (clear)
3041
        level1 <= 1'b0;
3042
    else if (q_next == level1_value)
3043 6 unneback
        level1 <= 1'b1;
3044
    else if (qi == level1_value & rew)
3045
        level1 <= 1'b0;
3046
endmodule
3047 40 unneback
`endif
3048
`ifdef CNT_GRAY
3049 6 unneback
//////////////////////////////////////////////////////////////////////
3050
////                                                              ////
3051
////  Versatile counter                                           ////
3052
////                                                              ////
3053
////  Description                                                 ////
3054
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3055
////  counter                                                     ////
3056
////                                                              ////
3057
////  To Do:                                                      ////
3058
////   - add LFSR with more taps                                  ////
3059
////                                                              ////
3060
////  Author(s):                                                  ////
3061
////      - Michael Unneback, unneback@opencores.org              ////
3062
////        ORSoC AB                                              ////
3063
////                                                              ////
3064
//////////////////////////////////////////////////////////////////////
3065
////                                                              ////
3066
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3067
////                                                              ////
3068
//// This source file may be used and distributed without         ////
3069
//// restriction provided that this copyright statement is not    ////
3070
//// removed from the file and that any derivative work contains  ////
3071
//// the original copyright notice and the associated disclaimer. ////
3072
////                                                              ////
3073
//// This source file is free software; you can redistribute it   ////
3074
//// and/or modify it under the terms of the GNU Lesser General   ////
3075
//// Public License as published by the Free Software Foundation; ////
3076
//// either version 2.1 of the License, or (at your option) any   ////
3077
//// later version.                                               ////
3078
////                                                              ////
3079
//// This source is distributed in the hope that it will be       ////
3080
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3081
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3082
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3083
//// details.                                                     ////
3084
////                                                              ////
3085
//// You should have received a copy of the GNU Lesser General    ////
3086
//// Public License along with this source; if not, download it   ////
3087
//// from http://www.opencores.org/lgpl.shtml                     ////
3088
////                                                              ////
3089
//////////////////////////////////////////////////////////////////////
3090
 
3091
// GRAY counter
3092
 
3093 40 unneback
`define MODULE cnt_gray
3094
module `BASE`MODULE (
3095
`undef MODULE
3096
 q, rst, clk);
3097
 
3098 6 unneback
   parameter length = 4;
3099
   output reg [length:1] q;
3100
   input rst;
3101
   input clk;
3102
 
3103
   parameter clear_value = 0;
3104
   parameter set_value = 1;
3105
   parameter wrap_value = 8;
3106
   parameter level1_value = 15;
3107
 
3108
   reg  [length:1] qi;
3109
   wire [length:1] q_next;
3110
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3111
 
3112
   always @ (posedge clk or posedge rst)
3113
     if (rst)
3114
       qi <= {length{1'b0}};
3115
     else
3116
       qi <= q_next;
3117
 
3118
   always @ (posedge clk or posedge rst)
3119
     if (rst)
3120
       q <= {length{1'b0}};
3121
     else
3122
         q <= (q_next>>1) ^ q_next;
3123
 
3124
endmodule
3125 40 unneback
`endif
3126
`ifdef CNT_GRAY_CE
3127 6 unneback
//////////////////////////////////////////////////////////////////////
3128
////                                                              ////
3129
////  Versatile counter                                           ////
3130
////                                                              ////
3131
////  Description                                                 ////
3132
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3133
////  counter                                                     ////
3134
////                                                              ////
3135
////  To Do:                                                      ////
3136
////   - add LFSR with more taps                                  ////
3137
////                                                              ////
3138
////  Author(s):                                                  ////
3139
////      - Michael Unneback, unneback@opencores.org              ////
3140
////        ORSoC AB                                              ////
3141
////                                                              ////
3142
//////////////////////////////////////////////////////////////////////
3143
////                                                              ////
3144
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3145
////                                                              ////
3146
//// This source file may be used and distributed without         ////
3147
//// restriction provided that this copyright statement is not    ////
3148
//// removed from the file and that any derivative work contains  ////
3149
//// the original copyright notice and the associated disclaimer. ////
3150
////                                                              ////
3151
//// This source file is free software; you can redistribute it   ////
3152
//// and/or modify it under the terms of the GNU Lesser General   ////
3153
//// Public License as published by the Free Software Foundation; ////
3154
//// either version 2.1 of the License, or (at your option) any   ////
3155
//// later version.                                               ////
3156
////                                                              ////
3157
//// This source is distributed in the hope that it will be       ////
3158
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3159
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3160
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3161
//// details.                                                     ////
3162
////                                                              ////
3163
//// You should have received a copy of the GNU Lesser General    ////
3164
//// Public License along with this source; if not, download it   ////
3165
//// from http://www.opencores.org/lgpl.shtml                     ////
3166
////                                                              ////
3167
//////////////////////////////////////////////////////////////////////
3168
 
3169
// GRAY counter
3170
 
3171 40 unneback
`define MODULE cnt_gray_ce
3172
module `BASE`MODULE (
3173
`undef MODULE
3174
 cke, q, rst, clk);
3175
 
3176 6 unneback
   parameter length = 4;
3177
   input cke;
3178
   output reg [length:1] q;
3179
   input rst;
3180
   input clk;
3181
 
3182
   parameter clear_value = 0;
3183
   parameter set_value = 1;
3184
   parameter wrap_value = 8;
3185
   parameter level1_value = 15;
3186
 
3187
   reg  [length:1] qi;
3188
   wire [length:1] q_next;
3189
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3190
 
3191
   always @ (posedge clk or posedge rst)
3192
     if (rst)
3193
       qi <= {length{1'b0}};
3194
     else
3195
     if (cke)
3196
       qi <= q_next;
3197
 
3198
   always @ (posedge clk or posedge rst)
3199
     if (rst)
3200
       q <= {length{1'b0}};
3201
     else
3202
       if (cke)
3203
         q <= (q_next>>1) ^ q_next;
3204
 
3205
endmodule
3206 40 unneback
`endif
3207
`ifdef CNT_GRAY_CE_BIN
3208 6 unneback
//////////////////////////////////////////////////////////////////////
3209
////                                                              ////
3210
////  Versatile counter                                           ////
3211
////                                                              ////
3212
////  Description                                                 ////
3213
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3214
////  counter                                                     ////
3215
////                                                              ////
3216
////  To Do:                                                      ////
3217
////   - add LFSR with more taps                                  ////
3218
////                                                              ////
3219
////  Author(s):                                                  ////
3220
////      - Michael Unneback, unneback@opencores.org              ////
3221
////        ORSoC AB                                              ////
3222
////                                                              ////
3223
//////////////////////////////////////////////////////////////////////
3224
////                                                              ////
3225
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3226
////                                                              ////
3227
//// This source file may be used and distributed without         ////
3228
//// restriction provided that this copyright statement is not    ////
3229
//// removed from the file and that any derivative work contains  ////
3230
//// the original copyright notice and the associated disclaimer. ////
3231
////                                                              ////
3232
//// This source file is free software; you can redistribute it   ////
3233
//// and/or modify it under the terms of the GNU Lesser General   ////
3234
//// Public License as published by the Free Software Foundation; ////
3235
//// either version 2.1 of the License, or (at your option) any   ////
3236
//// later version.                                               ////
3237
////                                                              ////
3238
//// This source is distributed in the hope that it will be       ////
3239
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3240
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3241
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3242
//// details.                                                     ////
3243
////                                                              ////
3244
//// You should have received a copy of the GNU Lesser General    ////
3245
//// Public License along with this source; if not, download it   ////
3246
//// from http://www.opencores.org/lgpl.shtml                     ////
3247
////                                                              ////
3248
//////////////////////////////////////////////////////////////////////
3249
 
3250
// GRAY counter
3251
 
3252 40 unneback
`define MODULE cnt_gray_ce_bin
3253
module `BASE`MODULE (
3254
`undef MODULE
3255
 cke, q, q_bin, rst, clk);
3256
 
3257 6 unneback
   parameter length = 4;
3258
   input cke;
3259
   output reg [length:1] q;
3260
   output [length:1] q_bin;
3261
   input rst;
3262
   input clk;
3263
 
3264
   parameter clear_value = 0;
3265
   parameter set_value = 1;
3266
   parameter wrap_value = 8;
3267
   parameter level1_value = 15;
3268
 
3269
   reg  [length:1] qi;
3270
   wire [length:1] q_next;
3271
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3272
 
3273
   always @ (posedge clk or posedge rst)
3274
     if (rst)
3275
       qi <= {length{1'b0}};
3276
     else
3277
     if (cke)
3278
       qi <= q_next;
3279
 
3280
   always @ (posedge clk or posedge rst)
3281
     if (rst)
3282
       q <= {length{1'b0}};
3283
     else
3284
       if (cke)
3285
         q <= (q_next>>1) ^ q_next;
3286
 
3287
   assign q_bin = qi;
3288
 
3289
endmodule
3290 40 unneback
`endif
3291 6 unneback
//////////////////////////////////////////////////////////////////////
3292
////                                                              ////
3293
////  Versatile library, counters                                 ////
3294
////                                                              ////
3295
////  Description                                                 ////
3296
////  counters                                                    ////
3297
////                                                              ////
3298
////                                                              ////
3299
////  To Do:                                                      ////
3300
////   - add more counters                                        ////
3301
////                                                              ////
3302
////  Author(s):                                                  ////
3303
////      - Michael Unneback, unneback@opencores.org              ////
3304
////        ORSoC AB                                              ////
3305
////                                                              ////
3306
//////////////////////////////////////////////////////////////////////
3307
////                                                              ////
3308
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3309
////                                                              ////
3310
//// This source file may be used and distributed without         ////
3311
//// restriction provided that this copyright statement is not    ////
3312
//// removed from the file and that any derivative work contains  ////
3313
//// the original copyright notice and the associated disclaimer. ////
3314
////                                                              ////
3315
//// This source file is free software; you can redistribute it   ////
3316
//// and/or modify it under the terms of the GNU Lesser General   ////
3317
//// Public License as published by the Free Software Foundation; ////
3318
//// either version 2.1 of the License, or (at your option) any   ////
3319
//// later version.                                               ////
3320
////                                                              ////
3321
//// This source is distributed in the hope that it will be       ////
3322
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3323
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3324
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3325
//// details.                                                     ////
3326
////                                                              ////
3327
//// You should have received a copy of the GNU Lesser General    ////
3328
//// Public License along with this source; if not, download it   ////
3329
//// from http://www.opencores.org/lgpl.shtml                     ////
3330
////                                                              ////
3331
//////////////////////////////////////////////////////////////////////
3332
 
3333 40 unneback
`ifdef CNT_SHREG_WRAP
3334
`define MODULE cnt_shreg_wrap
3335
module `BASE`MODULE ( q, rst, clk);
3336
`undef MODULE
3337 6 unneback
 
3338
   parameter length = 4;
3339
   output reg [0:length-1] q;
3340
   input rst;
3341
   input clk;
3342
 
3343
    always @ (posedge clk or posedge rst)
3344
    if (rst)
3345
        q <= {1'b1,{length-1{1'b0}}};
3346
    else
3347
        q <= {q[length-1],q[0:length-2]};
3348
 
3349
endmodule
3350 40 unneback
`endif
3351 6 unneback
 
3352 40 unneback
`ifdef CNT_SHREG_CE_WRAP
3353
`define MODULE cnt_shreg_ce_wrap
3354
module `BASE`MODULE ( cke, q, rst, clk);
3355
`undef MODULE
3356 6 unneback
 
3357
   parameter length = 4;
3358
   input cke;
3359
   output reg [0:length-1] q;
3360
   input rst;
3361
   input clk;
3362
 
3363
    always @ (posedge clk or posedge rst)
3364
    if (rst)
3365
        q <= {1'b1,{length-1{1'b0}}};
3366
    else
3367
        if (cke)
3368
            q <= {q[length-1],q[0:length-2]};
3369
 
3370
endmodule
3371 40 unneback
`endif
3372 6 unneback
 
3373 40 unneback
`ifdef CNT_SHREG_CE_CLEAR
3374
`define MODULE cnt_shreg_ce_clear
3375
module `BASE`MODULE ( cke, clear, q, rst, clk);
3376
`undef MODULE
3377 6 unneback
 
3378
   parameter length = 4;
3379
   input cke, clear;
3380
   output reg [0:length-1] q;
3381
   input rst;
3382
   input clk;
3383
 
3384
    always @ (posedge clk or posedge rst)
3385
    if (rst)
3386
        q <= {1'b1,{length-1{1'b0}}};
3387
    else
3388
        if (cke)
3389
            if (clear)
3390
                q <= {1'b1,{length-1{1'b0}}};
3391
            else
3392
                q <= q >> 1;
3393
 
3394
endmodule
3395 40 unneback
`endif
3396 6 unneback
 
3397 40 unneback
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3398
`define MODULE cnt_shreg_ce_clear_wrap
3399
module `BASE`MODULE ( cke, clear, q, rst, clk);
3400
`undef MODULE
3401 6 unneback
 
3402
   parameter length = 4;
3403
   input cke, clear;
3404
   output reg [0:length-1] q;
3405
   input rst;
3406
   input clk;
3407
 
3408
    always @ (posedge clk or posedge rst)
3409
    if (rst)
3410
        q <= {1'b1,{length-1{1'b0}}};
3411
    else
3412
        if (cke)
3413
            if (clear)
3414
                q <= {1'b1,{length-1{1'b0}}};
3415
            else
3416
            q <= {q[length-1],q[0:length-2]};
3417
 
3418
endmodule
3419 40 unneback
`endif
3420 6 unneback
//////////////////////////////////////////////////////////////////////
3421
////                                                              ////
3422
////  Versatile library, memories                                 ////
3423
////                                                              ////
3424
////  Description                                                 ////
3425
////  memories                                                    ////
3426
////                                                              ////
3427
////                                                              ////
3428
////  To Do:                                                      ////
3429
////   - add more memory types                                    ////
3430
////                                                              ////
3431
////  Author(s):                                                  ////
3432
////      - Michael Unneback, unneback@opencores.org              ////
3433
////        ORSoC AB                                              ////
3434
////                                                              ////
3435
//////////////////////////////////////////////////////////////////////
3436
////                                                              ////
3437
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3438
////                                                              ////
3439
//// This source file may be used and distributed without         ////
3440
//// restriction provided that this copyright statement is not    ////
3441
//// removed from the file and that any derivative work contains  ////
3442
//// the original copyright notice and the associated disclaimer. ////
3443
////                                                              ////
3444
//// This source file is free software; you can redistribute it   ////
3445
//// and/or modify it under the terms of the GNU Lesser General   ////
3446
//// Public License as published by the Free Software Foundation; ////
3447
//// either version 2.1 of the License, or (at your option) any   ////
3448
//// later version.                                               ////
3449
////                                                              ////
3450
//// This source is distributed in the hope that it will be       ////
3451
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3452
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3453
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3454
//// details.                                                     ////
3455
////                                                              ////
3456
//// You should have received a copy of the GNU Lesser General    ////
3457
//// Public License along with this source; if not, download it   ////
3458
//// from http://www.opencores.org/lgpl.shtml                     ////
3459
////                                                              ////
3460
//////////////////////////////////////////////////////////////////////
3461
 
3462 40 unneback
`ifdef ROM_INIT
3463 6 unneback
/// ROM
3464 40 unneback
`define MODULE rom_init
3465
module `BASE`MODULE ( adr, q, clk);
3466
`undef MODULE
3467 6 unneback
 
3468 7 unneback
   parameter data_width = 32;
3469
   parameter addr_width = 8;
3470
   input [(addr_width-1):0]       adr;
3471
   output reg [(data_width-1):0] q;
3472
   input                         clk;
3473
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
3474
   parameter memory_file = "vl_rom.vmem";
3475
   initial
3476
     begin
3477
        $readmemh(memory_file, rom);
3478
     end
3479
 
3480
   always @ (posedge clk)
3481
     q <= rom[adr];
3482 6 unneback
 
3483 7 unneback
endmodule
3484 40 unneback
`endif
3485 7 unneback
 
3486 40 unneback
`ifdef RAM
3487
`define MODULE ram
3488 6 unneback
// Single port RAM
3489 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
3490
`undef MODULE
3491 6 unneback
 
3492
   parameter data_width = 32;
3493
   parameter addr_width = 8;
3494
   input [(data_width-1):0]      d;
3495
   input [(addr_width-1):0]       adr;
3496
   input                         we;
3497 7 unneback
   output reg [(data_width-1):0] q;
3498 6 unneback
   input                         clk;
3499
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3500 7 unneback
   parameter init = 0;
3501
   parameter memory_file = "vl_ram.vmem";
3502
   generate if (init) begin : init_mem
3503
   initial
3504
     begin
3505
        $readmemh(memory_file, ram);
3506
     end
3507
   end
3508
   endgenerate
3509
 
3510 6 unneback
   always @ (posedge clk)
3511
   begin
3512
   if (we)
3513
     ram[adr] <= d;
3514
   q <= ram[adr];
3515
   end
3516
 
3517
endmodule
3518 40 unneback
`endif
3519 6 unneback
 
3520 40 unneback
`ifdef RAM_BE
3521
`define MODULE ram_be
3522
module `BASE`MODULE ( d, adr, be, we, q, clk);
3523
`undef MODULE
3524
 
3525 7 unneback
   parameter data_width = 32;
3526
   parameter addr_width = 8;
3527
   input [(data_width-1):0]      d;
3528
   input [(addr_width-1):0]       adr;
3529
   input [(addr_width/4)-1:0]    be;
3530
   input                         we;
3531
   output reg [(data_width-1):0] q;
3532
   input                         clk;
3533
 
3534 65 unneback
`ifdef SYSTEMVERILOG
3535
   logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width
3536
`else
3537 7 unneback
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3538 65 unneback
`endif
3539
 
3540 60 unneback
   parameter memory_init = 0;
3541 7 unneback
   parameter memory_file = "vl_ram.vmem";
3542 60 unneback
   generate if (memory_init) begin : init_mem
3543 7 unneback
   initial
3544
     begin
3545
        $readmemh(memory_file, ram);
3546
     end
3547
   end
3548
   endgenerate
3549
 
3550 60 unneback
`ifdef SYSTEMVERILOG
3551
// use a multi-dimensional packed array
3552
//to model individual bytes within the word
3553
 
3554
always_ff@(posedge clk)
3555
begin
3556
    if(we) begin // note: we should have a for statement to support any bus width
3557 65 unneback
        if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
3558
        if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
3559
        if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
3560
        if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
3561 60 unneback
    end
3562 65 unneback
    q <= ram[adr];
3563 60 unneback
end
3564
 
3565
`else
3566
 
3567 7 unneback
   genvar i;
3568
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
3569
      always @ (posedge clk)
3570
      if (we & be[i])
3571
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3572
   end
3573
   endgenerate
3574
 
3575
   always @ (posedge clk)
3576
      q <= ram[adr];
3577
 
3578 60 unneback
`endif
3579
 
3580 7 unneback
endmodule
3581 40 unneback
`endif
3582 7 unneback
 
3583 6 unneback
`ifdef ACTEL
3584 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
3585 6 unneback
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
3586
`else
3587
        `define SYN
3588
`endif
3589
 
3590 40 unneback
`ifdef DPRAM_1R1W
3591
`define MODULE dpram_1r1w
3592
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3593
`undef MODULE
3594 6 unneback
   parameter data_width = 32;
3595
   parameter addr_width = 8;
3596
   input [(data_width-1):0]      d_a;
3597
   input [(addr_width-1):0]       adr_a;
3598
   input [(addr_width-1):0]       adr_b;
3599
   input                         we_a;
3600
   output [(data_width-1):0]      q_b;
3601
   input                         clk_a, clk_b;
3602
   reg [(addr_width-1):0]         adr_b_reg;
3603
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3604 7 unneback
 
3605
   parameter init = 0;
3606
   parameter memory_file = "vl_ram.vmem";
3607
   generate if (init) begin : init_mem
3608
   initial
3609
     begin
3610
        $readmemh(memory_file, ram);
3611
     end
3612
   end
3613
   endgenerate
3614
 
3615 6 unneback
   always @ (posedge clk_a)
3616
   if (we_a)
3617
     ram[adr_a] <= d_a;
3618
   always @ (posedge clk_b)
3619
   adr_b_reg <= adr_b;
3620
   assign q_b = ram[adr_b_reg];
3621 40 unneback
 
3622 6 unneback
endmodule
3623 40 unneback
`endif
3624 6 unneback
 
3625 40 unneback
`ifdef DPRAM_2R1W
3626
`define MODULE dpram_2r1w
3627
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3628
`undef MODULE
3629
 
3630 6 unneback
   parameter data_width = 32;
3631
   parameter addr_width = 8;
3632
   input [(data_width-1):0]      d_a;
3633
   input [(addr_width-1):0]       adr_a;
3634
   input [(addr_width-1):0]       adr_b;
3635
   input                         we_a;
3636
   output [(data_width-1):0]      q_b;
3637
   output reg [(data_width-1):0] q_a;
3638
   input                         clk_a, clk_b;
3639
   reg [(data_width-1):0]         q_b;
3640
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3641 7 unneback
 
3642
   parameter init = 0;
3643
   parameter memory_file = "vl_ram.vmem";
3644
   generate if (init) begin : init_mem
3645
   initial
3646
     begin
3647
        $readmemh(memory_file, ram);
3648
     end
3649
   end
3650
   endgenerate
3651
 
3652 6 unneback
   always @ (posedge clk_a)
3653
     begin
3654
        q_a <= ram[adr_a];
3655
        if (we_a)
3656
             ram[adr_a] <= d_a;
3657
     end
3658
   always @ (posedge clk_b)
3659
          q_b <= ram[adr_b];
3660
endmodule
3661 40 unneback
`endif
3662 6 unneback
 
3663 40 unneback
`ifdef DPRAM_2R2W
3664
`define MODULE dpram_2r2w
3665
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3666
`undef MODULE
3667
 
3668 6 unneback
   parameter data_width = 32;
3669
   parameter addr_width = 8;
3670
   input [(data_width-1):0]      d_a;
3671
   input [(addr_width-1):0]       adr_a;
3672
   input [(addr_width-1):0]       adr_b;
3673
   input                         we_a;
3674
   output [(data_width-1):0]      q_b;
3675
   input [(data_width-1):0]       d_b;
3676
   output reg [(data_width-1):0] q_a;
3677
   input                         we_b;
3678
   input                         clk_a, clk_b;
3679
   reg [(data_width-1):0]         q_b;
3680
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3681 7 unneback
 
3682
   parameter init = 0;
3683
   parameter memory_file = "vl_ram.vmem";
3684
   generate if (init) begin : init_mem
3685
   initial
3686
     begin
3687
        $readmemh(memory_file, ram);
3688
     end
3689
   end
3690
   endgenerate
3691
 
3692 6 unneback
   always @ (posedge clk_a)
3693
     begin
3694
        q_a <= ram[adr_a];
3695
        if (we_a)
3696
             ram[adr_a] <= d_a;
3697
     end
3698
   always @ (posedge clk_b)
3699
     begin
3700
        q_b <= ram[adr_b];
3701
        if (we_b)
3702
          ram[adr_b] <= d_b;
3703
     end
3704
endmodule
3705 40 unneback
`endif
3706 6 unneback
 
3707
// Content addresable memory, CAM
3708
 
3709 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
3710 6 unneback
// FIFO
3711 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
3712
module `BASE`MODULE (
3713
`undef MODULE
3714 25 unneback
    d, wr, fifo_full,
3715
    q, rd, fifo_empty,
3716
    fill_level,
3717
    clk, rst
3718
    );
3719
 
3720
parameter data_width = 18;
3721
parameter addr_width = 4;
3722 6 unneback
 
3723 25 unneback
// write side
3724
input  [data_width-1:0] d;
3725
input                   wr;
3726
output                  fifo_full;
3727
// read side
3728
output [data_width-1:0] q;
3729
input                   rd;
3730
output                  fifo_empty;
3731
// common
3732
output [addr_width:0]   fill_level;
3733
input rst, clk;
3734
 
3735
wire [addr_width:1] wadr, radr;
3736
 
3737 40 unneback
`define MODULE cnt_bin_ce
3738
`BASE`MODULE
3739 25 unneback
    # ( .length(addr_width))
3740
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
3741 40 unneback
`BASE`MODULE
3742 25 unneback
    # (.length(addr_width))
3743
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
3744 40 unneback
`undef MODULE
3745 25 unneback
 
3746 40 unneback
`define MODULE dpram_1r1w
3747
`BASE`MODULE
3748 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
3749
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
3750 40 unneback
`undef MODULE
3751 25 unneback
 
3752 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
3753
`BASE`MODULE
3754 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
3755 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
3756 40 unneback
`undef MODULE
3757 25 unneback
endmodule
3758 40 unneback
`endif
3759 25 unneback
 
3760 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
3761 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
3762
// RAM is supposed to be larger than the two FIFOs
3763
// LFSR counters used adr pointers
3764 40 unneback
`define MODULE fifo_2r2w_sync_simplex
3765
module `BASE`MODULE (
3766
`undef MODULE
3767 27 unneback
    // a side
3768
    a_d, a_wr, a_fifo_full,
3769
    a_q, a_rd, a_fifo_empty,
3770
    a_fill_level,
3771
    // b side
3772
    b_d, b_wr, b_fifo_full,
3773
    b_q, b_rd, b_fifo_empty,
3774
    b_fill_level,
3775
    // common
3776
    clk, rst
3777
    );
3778
parameter data_width = 8;
3779
parameter addr_width = 5;
3780
parameter fifo_full_level = (1<<addr_width)-1;
3781
 
3782
// a side
3783
input  [data_width-1:0] a_d;
3784
input                   a_wr;
3785
output                  a_fifo_full;
3786
output [data_width-1:0] a_q;
3787
input                   a_rd;
3788
output                  a_fifo_empty;
3789
output [addr_width-1:0] a_fill_level;
3790
 
3791
// b side
3792
input  [data_width-1:0] b_d;
3793
input                   b_wr;
3794
output                  b_fifo_full;
3795
output [data_width-1:0] b_q;
3796
input                   b_rd;
3797
output                  b_fifo_empty;
3798
output [addr_width-1:0] b_fill_level;
3799
 
3800
input                   clk;
3801
input                   rst;
3802
 
3803
// adr_gen
3804
wire [addr_width:1] a_wadr, a_radr;
3805
wire [addr_width:1] b_wadr, b_radr;
3806
// dpram
3807
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3808
 
3809 40 unneback
`define MODULE cnt_lfsr_ce
3810
`BASE`MODULE
3811 27 unneback
    # ( .length(addr_width))
3812
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
3813
 
3814 40 unneback
`BASE`MODULE
3815 27 unneback
    # (.length(addr_width))
3816
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
3817
 
3818 40 unneback
`BASE`MODULE
3819 27 unneback
    # ( .length(addr_width))
3820
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
3821
 
3822 40 unneback
`BASE`MODULE
3823 27 unneback
    # (.length(addr_width))
3824
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
3825 40 unneback
`undef MODULE
3826 27 unneback
 
3827
// mux read or write adr to DPRAM
3828
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
3829
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
3830
 
3831 40 unneback
`define MODULE dpram_2r2w
3832
`BASE`MODULE
3833 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
3834
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3835
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3836 40 unneback
`undef MODULE
3837
 
3838
`define MODULE cnt_bin_ce_rew_zq_l1
3839
`BASE`MODULE
3840 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
3841 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
3842
 
3843 40 unneback
`BASE`MODULE
3844 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
3845 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
3846 40 unneback
`undef MODULE
3847 27 unneback
 
3848
endmodule
3849 40 unneback
`endif
3850 27 unneback
 
3851 40 unneback
`ifdef FIFO_CMP_ASYNC
3852
`define MODULE fifo_cmp_async
3853
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
3854
`undef MODULE
3855 6 unneback
 
3856 11 unneback
   parameter addr_width = 4;
3857
   parameter N = addr_width-1;
3858 6 unneback
 
3859
   parameter Q1 = 2'b00;
3860
   parameter Q2 = 2'b01;
3861
   parameter Q3 = 2'b11;
3862
   parameter Q4 = 2'b10;
3863
 
3864
   parameter going_empty = 1'b0;
3865
   parameter going_full  = 1'b1;
3866
 
3867
   input [N:0]  wptr, rptr;
3868 14 unneback
   output       fifo_empty;
3869 6 unneback
   output       fifo_full;
3870
   input        wclk, rclk, rst;
3871
 
3872
`ifndef GENERATE_DIRECTION_AS_LATCH
3873
   wire direction;
3874
`endif
3875
`ifdef GENERATE_DIRECTION_AS_LATCH
3876
   reg direction;
3877
`endif
3878
   reg  direction_set, direction_clr;
3879
 
3880
   wire async_empty, async_full;
3881
   wire fifo_full2;
3882 14 unneback
   wire fifo_empty2;
3883 6 unneback
 
3884
   // direction_set
3885
   always @ (wptr[N:N-1] or rptr[N:N-1])
3886
     case ({wptr[N:N-1],rptr[N:N-1]})
3887
       {Q1,Q2} : direction_set <= 1'b1;
3888
       {Q2,Q3} : direction_set <= 1'b1;
3889
       {Q3,Q4} : direction_set <= 1'b1;
3890
       {Q4,Q1} : direction_set <= 1'b1;
3891
       default : direction_set <= 1'b0;
3892
     endcase
3893
 
3894
   // direction_clear
3895
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
3896
     if (rst)
3897
       direction_clr <= 1'b1;
3898
     else
3899
       case ({wptr[N:N-1],rptr[N:N-1]})
3900
         {Q2,Q1} : direction_clr <= 1'b1;
3901
         {Q3,Q2} : direction_clr <= 1'b1;
3902
         {Q4,Q3} : direction_clr <= 1'b1;
3903
         {Q1,Q4} : direction_clr <= 1'b1;
3904
         default : direction_clr <= 1'b0;
3905
       endcase
3906
 
3907 40 unneback
`define MODULE dff_sr
3908 6 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
3909 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
3910 6 unneback
`endif
3911
 
3912
`ifdef GENERATE_DIRECTION_AS_LATCH
3913
   always @ (posedge direction_set or posedge direction_clr)
3914
     if (direction_clr)
3915
       direction <= going_empty;
3916
     else
3917
       direction <= going_full;
3918
`endif
3919
 
3920
   assign async_empty = (wptr == rptr) && (direction==going_empty);
3921
   assign async_full  = (wptr == rptr) && (direction==going_full);
3922
 
3923 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
3924
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
3925
`undef MODULE
3926 6 unneback
 
3927
/*
3928
   always @ (posedge wclk or posedge rst or posedge async_full)
3929
     if (rst)
3930
       {fifo_full, fifo_full2} <= 2'b00;
3931
     else if (async_full)
3932
       {fifo_full, fifo_full2} <= 2'b11;
3933
     else
3934
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
3935
*/
3936 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
3937 6 unneback
     if (async_empty)
3938
       {fifo_empty, fifo_empty2} <= 2'b11;
3939
     else
3940 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
3941 40 unneback
`define MODULE dff
3942
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
3943
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
3944
`undef MODULE
3945 27 unneback
endmodule // async_compb
3946 40 unneback
`endif
3947 6 unneback
 
3948 40 unneback
`ifdef FIFO_1R1W_ASYNC
3949
`define MODULE fifo_1r1w_async
3950
module `BASE`MODULE (
3951
`undef MODULE
3952 6 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
3953
    q, rd, fifo_empty, rd_clk, rd_rst
3954
    );
3955
 
3956
parameter data_width = 18;
3957
parameter addr_width = 4;
3958
 
3959
// write side
3960
input  [data_width-1:0] d;
3961
input                   wr;
3962
output                  fifo_full;
3963
input                   wr_clk;
3964
input                   wr_rst;
3965
// read side
3966
output [data_width-1:0] q;
3967
input                   rd;
3968
output                  fifo_empty;
3969
input                   rd_clk;
3970
input                   rd_rst;
3971
 
3972
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
3973 23 unneback
 
3974 40 unneback
`define MODULE cnt_gray_ce_bin
3975
`BASE`MODULE
3976 6 unneback
    # ( .length(addr_width))
3977
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
3978
 
3979 40 unneback
`BASE`MODULE
3980 6 unneback
    # (.length(addr_width))
3981 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
3982 40 unneback
`undef MODULE
3983 6 unneback
 
3984 40 unneback
`define MODULE dpram_1r1w
3985
`BASE`MODULE
3986 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
3987
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
3988 40 unneback
`undef MODULE
3989 6 unneback
 
3990 40 unneback
`define MODULE fifo_cmp_async
3991
`BASE`MODULE
3992 6 unneback
    # (.addr_width(addr_width))
3993
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
3994 40 unneback
`undef MODULE
3995 6 unneback
 
3996
endmodule
3997 40 unneback
`endif
3998 6 unneback
 
3999 40 unneback
`ifdef FIFO_2R2W_ASYNC
4000
`define MODULE fifo_2r2w_async
4001
module `BASE`MODULE (
4002
`undef MODULE
4003 6 unneback
    // a side
4004
    a_d, a_wr, a_fifo_full,
4005
    a_q, a_rd, a_fifo_empty,
4006
    a_clk, a_rst,
4007
    // b side
4008
    b_d, b_wr, b_fifo_full,
4009
    b_q, b_rd, b_fifo_empty,
4010
    b_clk, b_rst
4011
    );
4012
 
4013
parameter data_width = 18;
4014
parameter addr_width = 4;
4015
 
4016
// a side
4017
input  [data_width-1:0] a_d;
4018
input                   a_wr;
4019
output                  a_fifo_full;
4020
output [data_width-1:0] a_q;
4021
input                   a_rd;
4022
output                  a_fifo_empty;
4023
input                   a_clk;
4024
input                   a_rst;
4025
 
4026
// b side
4027
input  [data_width-1:0] b_d;
4028
input                   b_wr;
4029
output                  b_fifo_full;
4030
output [data_width-1:0] b_q;
4031
input                   b_rd;
4032
output                  b_fifo_empty;
4033
input                   b_clk;
4034
input                   b_rst;
4035
 
4036 40 unneback
`define MODULE fifo_1r1w_async
4037
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4038 6 unneback
vl_fifo_1r1w_async_a (
4039
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4040
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4041
    );
4042
 
4043 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4044 6 unneback
vl_fifo_1r1w_async_b (
4045
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4046
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4047
    );
4048 40 unneback
`undef MODULE
4049
 
4050 6 unneback
endmodule
4051 40 unneback
`endif
4052 6 unneback
 
4053 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4054
`define MODULE fifo_2r2w_async_simplex
4055
module `BASE`MODULE (
4056
`undef MODULE
4057 6 unneback
    // a side
4058
    a_d, a_wr, a_fifo_full,
4059
    a_q, a_rd, a_fifo_empty,
4060
    a_clk, a_rst,
4061
    // b side
4062
    b_d, b_wr, b_fifo_full,
4063
    b_q, b_rd, b_fifo_empty,
4064
    b_clk, b_rst
4065
    );
4066
 
4067
parameter data_width = 18;
4068
parameter addr_width = 4;
4069
 
4070
// a side
4071
input  [data_width-1:0] a_d;
4072
input                   a_wr;
4073
output                  a_fifo_full;
4074
output [data_width-1:0] a_q;
4075
input                   a_rd;
4076
output                  a_fifo_empty;
4077
input                   a_clk;
4078
input                   a_rst;
4079
 
4080
// b side
4081
input  [data_width-1:0] b_d;
4082
input                   b_wr;
4083
output                  b_fifo_full;
4084
output [data_width-1:0] b_q;
4085
input                   b_rd;
4086
output                  b_fifo_empty;
4087
input                   b_clk;
4088
input                   b_rst;
4089
 
4090
// adr_gen
4091
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4092
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4093
// dpram
4094
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4095
 
4096 40 unneback
`define MODULE cnt_gray_ce_bin
4097
`BASE`MODULE
4098 6 unneback
    # ( .length(addr_width))
4099
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4100
 
4101 40 unneback
`BASE`MODULE
4102 6 unneback
    # (.length(addr_width))
4103
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4104
 
4105 40 unneback
`BASE`MODULE
4106 6 unneback
    # ( .length(addr_width))
4107
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4108
 
4109 40 unneback
`BASE`MODULE
4110 6 unneback
    # (.length(addr_width))
4111
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4112 40 unneback
`undef MODULE
4113 6 unneback
 
4114
// mux read or write adr to DPRAM
4115
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4116
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4117
 
4118 40 unneback
`define MODULE dpram_2r2w
4119
`BASE`MODULE
4120 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
4121
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4122
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4123 40 unneback
`undef MODULE
4124 6 unneback
 
4125 40 unneback
`define MODULE fifo_cmp_async
4126
`BASE`MODULE
4127 6 unneback
    # (.addr_width(addr_width))
4128
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4129
 
4130 40 unneback
`BASE`MODULE
4131 6 unneback
    # (.addr_width(addr_width))
4132
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4133 40 unneback
`undef MODULE
4134 6 unneback
 
4135
endmodule
4136 40 unneback
`endif
4137 48 unneback
 
4138
`ifdef REG_FILE
4139
`define MODULE reg_file
4140
module `BASE`MODULE (
4141
`undef MODULE
4142
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4143
);
4144
parameter data_width = 32;
4145
parameter addr_width = 5;
4146
input [addr_width-1:0] a1, a2, a3;
4147
input [data_width-1:0] wd3;
4148
input we3;
4149
output [data_width-1:0] rd1, rd2;
4150
input clk;
4151
 
4152
`ifdef ACTEL
4153
reg [data_width-1:0] wd3_reg;
4154
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4155
reg we3_reg;
4156
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
4157
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
4158
always @ (posedge clk or posedge rst)
4159
if (rst)
4160
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4161
else
4162
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4163
 
4164
    always @ (negedge clk)
4165
    if (we3_reg)
4166
        ram1[a3_reg] <= wd3;
4167
    always @ (posedge clk)
4168
        a1_reg <= a1;
4169
    assign rd1 = ram1[a1_reg];
4170
 
4171
    always @ (negedge clk)
4172
    if (we3_reg)
4173
        ram2[a3_reg] <= wd3;
4174
    always @ (posedge clk)
4175
        a2_reg <= a2;
4176
    assign rd2 = ram2[a2_reg];
4177
 
4178
`else
4179
 
4180
`define MODULE dpram_1r1w
4181
`BASE`MODULE
4182
    # ( .data_width(data_width), .addr_width(addr_width))
4183
    ram1 (
4184
        .d_a(wd3),
4185
        .adr_a(a3),
4186
        .we_a(we3),
4187
        .clk_a(clk),
4188
        .q_b(rd1),
4189
        .adr_b(a1),
4190
        .clk_b(clk) );
4191
 
4192
`BASE`MODULE
4193
    # ( .data_width(data_width), .addr_width(addr_width))
4194
    ram2 (
4195
        .d_a(wd3),
4196
        .adr_a(a3),
4197
        .we_a(we3),
4198
        .clk_a(clk),
4199
        .q_b(rd2),
4200
        .adr_b(a2),
4201
        .clk_b(clk) );
4202
`undef MODULE
4203
 
4204
`endif
4205
 
4206
endmodule
4207
`endif
4208 12 unneback
//////////////////////////////////////////////////////////////////////
4209
////                                                              ////
4210
////  Versatile library, wishbone stuff                           ////
4211
////                                                              ////
4212
////  Description                                                 ////
4213
////  Wishbone compliant modules                                  ////
4214
////                                                              ////
4215
////                                                              ////
4216
////  To Do:                                                      ////
4217
////   -                                                          ////
4218
////                                                              ////
4219
////  Author(s):                                                  ////
4220
////      - Michael Unneback, unneback@opencores.org              ////
4221
////        ORSoC AB                                              ////
4222
////                                                              ////
4223
//////////////////////////////////////////////////////////////////////
4224
////                                                              ////
4225
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4226
////                                                              ////
4227
//// This source file may be used and distributed without         ////
4228
//// restriction provided that this copyright statement is not    ////
4229
//// removed from the file and that any derivative work contains  ////
4230
//// the original copyright notice and the associated disclaimer. ////
4231
////                                                              ////
4232
//// This source file is free software; you can redistribute it   ////
4233
//// and/or modify it under the terms of the GNU Lesser General   ////
4234
//// Public License as published by the Free Software Foundation; ////
4235
//// either version 2.1 of the License, or (at your option) any   ////
4236
//// later version.                                               ////
4237
////                                                              ////
4238
//// This source is distributed in the hope that it will be       ////
4239
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4240
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4241
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4242
//// details.                                                     ////
4243
////                                                              ////
4244
//// You should have received a copy of the GNU Lesser General    ////
4245
//// Public License along with this source; if not, download it   ////
4246
//// from http://www.opencores.org/lgpl.shtml                     ////
4247
////                                                              ////
4248
//////////////////////////////////////////////////////////////////////
4249
 
4250 40 unneback
`ifdef WB3WB3_BRIDGE
4251 12 unneback
// async wb3 - wb3 bridge
4252
`timescale 1ns/1ns
4253 40 unneback
`define MODULE wb3wb3_bridge
4254
module `BASE`MODULE (
4255
`undef MODULE
4256 12 unneback
        // wishbone slave side
4257
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4258
        // wishbone master side
4259
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4260
 
4261
input [31:0] wbs_dat_i;
4262
input [31:2] wbs_adr_i;
4263
input [3:0]  wbs_sel_i;
4264
input [1:0]  wbs_bte_i;
4265
input [2:0]  wbs_cti_i;
4266
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4267
output [31:0] wbs_dat_o;
4268 14 unneback
output wbs_ack_o;
4269 12 unneback
input wbs_clk, wbs_rst;
4270
 
4271
output [31:0] wbm_dat_o;
4272
output reg [31:2] wbm_adr_o;
4273
output [3:0]  wbm_sel_o;
4274
output reg [1:0]  wbm_bte_o;
4275
output reg [2:0]  wbm_cti_o;
4276 14 unneback
output reg wbm_we_o;
4277
output wbm_cyc_o;
4278 12 unneback
output wbm_stb_o;
4279
input [31:0]  wbm_dat_i;
4280
input wbm_ack_i;
4281
input wbm_clk, wbm_rst;
4282
 
4283
parameter addr_width = 4;
4284
 
4285
// bte
4286
parameter linear       = 2'b00;
4287
parameter wrap4        = 2'b01;
4288
parameter wrap8        = 2'b10;
4289
parameter wrap16       = 2'b11;
4290
// cti
4291
parameter classic      = 3'b000;
4292
parameter incburst     = 3'b010;
4293
parameter endofburst   = 3'b111;
4294
 
4295
parameter wbs_adr  = 1'b0;
4296
parameter wbs_data = 1'b1;
4297
 
4298 33 unneback
parameter wbm_adr0      = 2'b00;
4299
parameter wbm_adr1      = 2'b01;
4300
parameter wbm_data      = 2'b10;
4301
parameter wbm_data_wait = 2'b11;
4302 12 unneback
 
4303
reg [1:0] wbs_bte_reg;
4304
reg wbs;
4305
wire wbs_eoc_alert, wbm_eoc_alert;
4306
reg wbs_eoc, wbm_eoc;
4307
reg [1:0] wbm;
4308
 
4309 14 unneback
wire [1:16] wbs_count, wbm_count;
4310 12 unneback
 
4311
wire [35:0] a_d, a_q, b_d, b_q;
4312
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4313
reg a_rd_reg;
4314
wire b_rd_adr, b_rd_data;
4315 14 unneback
wire b_rd_data_reg;
4316
wire [35:0] temp;
4317 12 unneback
 
4318
`define WE 5
4319
`define BTE 4:3
4320
`define CTI 2:0
4321
 
4322
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4323
always @ (posedge wbs_clk or posedge wbs_rst)
4324
if (wbs_rst)
4325
        wbs_eoc <= 1'b0;
4326
else
4327
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4328
                wbs_eoc <= wbs_bte_i==linear;
4329
        else if (wbs_eoc_alert & (a_rd | a_wr))
4330
                wbs_eoc <= 1'b1;
4331
 
4332 40 unneback
`define MODULE cnt_shreg_ce_clear
4333
`BASE`MODULE # ( .length(16))
4334
`undef MODULE
4335 12 unneback
    cnt0 (
4336
        .cke(wbs_ack_o),
4337
        .clear(wbs_eoc),
4338
        .q(wbs_count),
4339
        .rst(wbs_rst),
4340
        .clk(wbs_clk));
4341
 
4342
always @ (posedge wbs_clk or posedge wbs_rst)
4343
if (wbs_rst)
4344
        wbs <= wbs_adr;
4345
else
4346
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
4347
                wbs <= wbs_data;
4348
        else if (wbs_eoc & wbs_ack_o)
4349
                wbs <= wbs_adr;
4350
 
4351
// wbs FIFO
4352
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
4353
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
4354
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4355
              1'b0;
4356
assign a_rd = !a_fifo_empty;
4357
always @ (posedge wbs_clk or posedge wbs_rst)
4358
if (wbs_rst)
4359
        a_rd_reg <= 1'b0;
4360
else
4361
        a_rd_reg <= a_rd;
4362
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4363
 
4364
assign wbs_dat_o = a_q[35:4];
4365
 
4366
always @ (posedge wbs_clk or posedge wbs_rst)
4367
if (wbs_rst)
4368 13 unneback
        wbs_bte_reg <= 2'b00;
4369 12 unneback
else
4370 13 unneback
        wbs_bte_reg <= wbs_bte_i;
4371 12 unneback
 
4372
// wbm FIFO
4373
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4374
always @ (posedge wbm_clk or posedge wbm_rst)
4375
if (wbm_rst)
4376
        wbm_eoc <= 1'b0;
4377
else
4378
        if (wbm==wbm_adr0 & !b_fifo_empty)
4379
                wbm_eoc <= b_q[`BTE] == linear;
4380
        else if (wbm_eoc_alert & wbm_ack_i)
4381
                wbm_eoc <= 1'b1;
4382
 
4383
always @ (posedge wbm_clk or posedge wbm_rst)
4384
if (wbm_rst)
4385
        wbm <= wbm_adr0;
4386
else
4387 33 unneback
/*
4388 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
4389
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
4390
        (wbm==wbm_adr1 & !wbm_we_o) |
4391
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
4392
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
4393 33 unneback
*/
4394
    case (wbm)
4395
    wbm_adr0:
4396
        if (!b_fifo_empty)
4397
            wbm <= wbm_adr1;
4398
    wbm_adr1:
4399
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
4400
            wbm <= wbm_data;
4401
    wbm_data:
4402
        if (wbm_ack_i & wbm_eoc)
4403
            wbm <= wbm_adr0;
4404
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
4405
            wbm <= wbm_data_wait;
4406
    wbm_data_wait:
4407
        if (!b_fifo_empty)
4408
            wbm <= wbm_data;
4409
    endcase
4410 12 unneback
 
4411
assign b_d = {wbm_dat_i,4'b1111};
4412
assign b_wr = !wbm_we_o & wbm_ack_i;
4413
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
4414
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
4415
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
4416 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
4417 12 unneback
                   1'b0;
4418
assign b_rd = b_rd_adr | b_rd_data;
4419
 
4420 40 unneback
`define MODULE dff
4421
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
4422
`undef MODULE
4423
`define MODULE dff_ce
4424
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
4425
`undef MODULE
4426 12 unneback
 
4427
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
4428
 
4429 40 unneback
`define MODULE cnt_shreg_ce_clear
4430 42 unneback
`BASE`MODULE # ( .length(16))
4431 40 unneback
`undef MODULE
4432 12 unneback
    cnt1 (
4433
        .cke(wbm_ack_i),
4434
        .clear(wbm_eoc),
4435
        .q(wbm_count),
4436
        .rst(wbm_rst),
4437
        .clk(wbm_clk));
4438
 
4439 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
4440
assign wbm_stb_o = (wbm==wbm_data);
4441 12 unneback
 
4442
always @ (posedge wbm_clk or posedge wbm_rst)
4443
if (wbm_rst)
4444
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
4445
else begin
4446
        if (wbm==wbm_adr0 & !b_fifo_empty)
4447
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
4448
        else if (wbm_eoc_alert & wbm_ack_i)
4449
                wbm_cti_o <= endofburst;
4450
end
4451
 
4452
//async_fifo_dw_simplex_top
4453 40 unneback
`define MODULE fifo_2r2w_async_simplex
4454
`BASE`MODULE
4455
`undef MODULE
4456 12 unneback
# ( .data_width(36), .addr_width(addr_width))
4457
fifo (
4458
    // a side
4459
    .a_d(a_d),
4460
    .a_wr(a_wr),
4461
    .a_fifo_full(a_fifo_full),
4462
    .a_q(a_q),
4463
    .a_rd(a_rd),
4464
    .a_fifo_empty(a_fifo_empty),
4465
    .a_clk(wbs_clk),
4466
    .a_rst(wbs_rst),
4467
    // b side
4468
    .b_d(b_d),
4469
    .b_wr(b_wr),
4470
    .b_fifo_full(b_fifo_full),
4471
    .b_q(b_q),
4472
    .b_rd(b_rd),
4473
    .b_fifo_empty(b_fifo_empty),
4474
    .b_clk(wbm_clk),
4475
    .b_rst(wbm_rst)
4476
    );
4477
 
4478
endmodule
4479 40 unneback
`undef WE
4480
`undef BTE
4481
`undef CTI
4482
`endif
4483 17 unneback
 
4484 40 unneback
`ifdef WB3_ARBITER_TYPE1
4485
`define MODULE wb3_arbiter_type1
4486 42 unneback
module `BASE`MODULE (
4487 40 unneback
`undef MODULE
4488 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
4489
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
4490
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
4491
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
4492
    wb_clk, wb_rst
4493
);
4494
 
4495
parameter nr_of_ports = 3;
4496
parameter adr_size = 26;
4497
parameter adr_lo   = 2;
4498
parameter dat_size = 32;
4499
parameter sel_size = dat_size/8;
4500
 
4501
localparam aw = (adr_size - adr_lo) * nr_of_ports;
4502
localparam dw = dat_size * nr_of_ports;
4503
localparam sw = sel_size * nr_of_ports;
4504
localparam cw = 3 * nr_of_ports;
4505
localparam bw = 2 * nr_of_ports;
4506
 
4507
input  [dw-1:0] wbm_dat_o;
4508
input  [aw-1:0] wbm_adr_o;
4509
input  [sw-1:0] wbm_sel_o;
4510
input  [cw-1:0] wbm_cti_o;
4511
input  [bw-1:0] wbm_bte_o;
4512
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
4513
output [dw-1:0] wbm_dat_i;
4514
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
4515
 
4516
output [dat_size-1:0] wbs_dat_i;
4517
output [adr_size-1:adr_lo] wbs_adr_i;
4518
output [sel_size-1:0] wbs_sel_i;
4519
output [2:0] wbs_cti_i;
4520
output [1:0] wbs_bte_i;
4521
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
4522
input  [dat_size-1:0] wbs_dat_o;
4523
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
4524
 
4525
input wb_clk, wb_rst;
4526
 
4527 44 unneback
reg  [nr_of_ports-1:0] select;
4528 39 unneback
wire [nr_of_ports-1:0] state;
4529
wire [nr_of_ports-1:0] eoc; // end-of-cycle
4530
wire [nr_of_ports-1:0] sel;
4531
wire idle;
4532
 
4533
genvar i;
4534
 
4535
assign idle = !(|state);
4536
 
4537
generate
4538
if (nr_of_ports == 2) begin
4539
 
4540
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
4541
 
4542
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4543
 
4544 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4545
 
4546
    always @ (idle or wbm_cyc_o)
4547
    if (idle)
4548
        casex (wbm_cyc_o)
4549
        2'b1x : select = 2'b10;
4550
        2'b01 : select = 2'b01;
4551
        default : select = {nr_of_ports{1'b0}};
4552
        endcase
4553
    else
4554
        select = {nr_of_ports{1'b0}};
4555
 
4556 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4557
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4558
 
4559
end
4560
endgenerate
4561
 
4562
generate
4563
if (nr_of_ports == 3) begin
4564
 
4565
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4566
 
4567
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4568
 
4569 44 unneback
    always @ (idle or wbm_cyc_o)
4570
    if (idle)
4571
        casex (wbm_cyc_o)
4572
        3'b1xx : select = 3'b100;
4573
        3'b01x : select = 3'b010;
4574
        3'b001 : select = 3'b001;
4575
        default : select = {nr_of_ports{1'b0}};
4576
        endcase
4577
    else
4578
        select = {nr_of_ports{1'b0}};
4579
 
4580
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4581 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4582
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4583
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4584
 
4585
end
4586
endgenerate
4587
 
4588
generate
4589 44 unneback
if (nr_of_ports == 4) begin
4590
 
4591
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4592
 
4593
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4594
 
4595
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4596
 
4597
    always @ (idle or wbm_cyc_o)
4598
    if (idle)
4599
        casex (wbm_cyc_o)
4600
        4'b1xxx : select = 4'b1000;
4601
        4'b01xx : select = 4'b0100;
4602
        4'b001x : select = 4'b0010;
4603
        4'b0001 : select = 4'b0001;
4604
        default : select = {nr_of_ports{1'b0}};
4605
        endcase
4606
    else
4607
        select = {nr_of_ports{1'b0}};
4608
 
4609
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4610
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4611
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4612
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4613
 
4614
end
4615
endgenerate
4616
 
4617
generate
4618
if (nr_of_ports == 5) begin
4619
 
4620
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4621
 
4622
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4623
 
4624
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4625
 
4626
    always @ (idle or wbm_cyc_o)
4627
    if (idle)
4628
        casex (wbm_cyc_o)
4629
        5'b1xxxx : select = 5'b10000;
4630
        5'b01xxx : select = 5'b01000;
4631
        5'b001xx : select = 5'b00100;
4632
        5'b0001x : select = 5'b00010;
4633
        5'b00001 : select = 5'b00001;
4634
        default : select = {nr_of_ports{1'b0}};
4635
        endcase
4636
    else
4637
        select = {nr_of_ports{1'b0}};
4638
 
4639
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
4640
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4641
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4642
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4643
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4644
 
4645
end
4646
endgenerate
4647
 
4648
generate
4649 67 unneback
if (nr_of_ports == 6) begin
4650
 
4651
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4652
 
4653
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4654
 
4655
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4656
 
4657
    always @ (idle or wbm_cyc_o)
4658
    if (idle)
4659
        casex (wbm_cyc_o)
4660
        6'b1xxxxx : select = 6'b100000;
4661
        6'b01xxxx : select = 6'b010000;
4662
        6'b001xxx : select = 6'b001000;
4663
        6'b0001xx : select = 6'b000100;
4664
        6'b00001x : select = 6'b000010;
4665
        6'b000001 : select = 6'b000001;
4666
        default : select = {nr_of_ports{1'b0}};
4667
        endcase
4668
    else
4669
        select = {nr_of_ports{1'b0}};
4670
 
4671
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
4672
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
4673
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4674
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4675
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4676
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4677
 
4678
end
4679
endgenerate
4680
 
4681
generate
4682
if (nr_of_ports == 7) begin
4683
 
4684
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4685
 
4686
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4687
 
4688
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4689
 
4690
    always @ (idle or wbm_cyc_o)
4691
    if (idle)
4692
        casex (wbm_cyc_o)
4693
        7'b1xxxxxx : select = 7'b1000000;
4694
        7'b01xxxxx : select = 7'b0100000;
4695
        7'b001xxxx : select = 7'b0010000;
4696
        7'b0001xxx : select = 7'b0001000;
4697
        7'b00001xx : select = 7'b0000100;
4698
        7'b000001x : select = 7'b0000010;
4699
        7'b0000001 : select = 7'b0000001;
4700
        default : select = {nr_of_ports{1'b0}};
4701
        endcase
4702
    else
4703
        select = {nr_of_ports{1'b0}};
4704
 
4705
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
4706
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
4707
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
4708
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4709
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4710
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4711
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4712
 
4713
end
4714
endgenerate
4715
 
4716
generate
4717
if (nr_of_ports == 8) begin
4718
 
4719
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4720
 
4721
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4722
 
4723
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4724
 
4725
    always @ (idle or wbm_cyc_o)
4726
    if (idle)
4727
        casex (wbm_cyc_o)
4728
        8'b1xxxxxxx : select = 8'b10000000;
4729
        8'b01xxxxxx : select = 8'b01000000;
4730
        8'b001xxxxx : select = 8'b00100000;
4731
        8'b0001xxxx : select = 8'b00010000;
4732
        8'b00001xxx : select = 8'b00001000;
4733
        8'b000001xx : select = 8'b00000100;
4734
        8'b0000001x : select = 8'b00000010;
4735
        8'b00000001 : select = 8'b00000001;
4736
        default : select = {nr_of_ports{1'b0}};
4737
        endcase
4738
    else
4739
        select = {nr_of_ports{1'b0}};
4740
 
4741
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
4742
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
4743
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
4744
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
4745
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4746
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4747
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4748
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4749
 
4750
end
4751
endgenerate
4752
 
4753
generate
4754 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
4755 42 unneback
`define MODULE spr
4756
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
4757
`undef MODULE
4758 39 unneback
end
4759
endgenerate
4760
 
4761
    assign sel = select | state;
4762
 
4763 40 unneback
`define MODULE mux_andor
4764
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
4765
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
4766
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
4767
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
4768
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
4769
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
4770
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
4771
`undef MODULE
4772 39 unneback
    assign wbs_cyc_i = |sel;
4773
 
4774
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
4775
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
4776
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
4777
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
4778
 
4779
endmodule
4780 40 unneback
`endif
4781 39 unneback
 
4782 60 unneback
`ifdef WB_B3_RAM_BE
4783 49 unneback
// WB RAM with byte enable
4784 59 unneback
`define MODULE wb_b3_ram_be
4785
module `BASE`MODULE (
4786
`undef MODULE
4787 61 unneback
    wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
4788 59 unneback
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
4789
 
4790 60 unneback
parameter nr_of_ports = 3;
4791
parameter wb_arbiter_type = 1;
4792
parameter adr_size = 26;
4793
parameter adr_lo   = 2;
4794
parameter dat_size = 32;
4795
parameter memory_init = 1;
4796
parameter memory_file = "vl_ram.vmem";
4797 59 unneback
 
4798 60 unneback
localparam aw = (adr_size - adr_lo) * nr_of_ports;
4799
localparam dw = dat_size * nr_of_ports;
4800
localparam sw = dat_size/8 * nr_of_ports;
4801
localparam cw = 3 * nr_of_ports;
4802
localparam bw = 2 * nr_of_ports;
4803
 
4804
input [dw-1:0] wb_dat_i;
4805
input [aw-1:0] wb_adr_i;
4806
input [cw-1:0] wb_cti_i;
4807 61 unneback
input [bw-1:0] wb_bte_i;
4808 60 unneback
input [sw-1:0] wb_sel_i;
4809
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
4810
output [dw-1:0] wb_dat_o;
4811 66 unneback
output [nr_of_ports-1:0] wb_ack_o;
4812 59 unneback
input wb_clk, wb_rst;
4813
 
4814 60 unneback
wire [sw-1:0] cke;
4815 59 unneback
 
4816 60 unneback
// local wb slave
4817
wire [dat_size-1:0] wbs_dat_i;
4818
wire [adr_size-1:0] wbs_adr_i;
4819
wire [2:0] wbs_cti_i;
4820 61 unneback
wire [1:0] wbs_bte_i;
4821 60 unneback
wire [(dat_size/8)-1:0] wbs_sel_i;
4822
wire  wbs_we_i, wbs_stb_i, wbs_cyc_i;
4823
wire [dat_size-1:0] wbs_dat_o;
4824
reg wbs_ack_o;
4825
 
4826 59 unneback
generate
4827 60 unneback
if (nr_of_ports == 1) begin
4828
    assign wbs_dat_i = wb_dat_i;
4829
    assign wbs_adr_i = wb_adr_i;
4830
    assign wbs_cti_i = wb_cti_i;
4831
    assign wbs_sel_i = wb_sel_i;
4832
    assign wbs_we_i  = wb_we_i;
4833
    assign wbs_stb_i = wb_stb_i;
4834
    assign wbs_cyc_i = wb_cyc_i;
4835
    assign wb_dat_o  = wbs_dat_o;
4836
    assign wb_ack_o  = wbs_ack_o;
4837 59 unneback
end
4838
endgenerate
4839
 
4840 60 unneback
generate
4841
if (nr_of_ports > 1 & wb_arbiter_type == 1) begin
4842
`define MODULE wb3_arbiter_type1
4843
`BASE`MODULE wb_arbiter0(
4844
`undef MODULE
4845
    .wbm_dat_o(wb_dat_i),
4846
    .wbm_adr_o(wb_adr_i),
4847
    .wbm_sel_o(wb_sel_i),
4848
    .wbm_cti_o(wb_cti_i),
4849
    .wbm_bte_o(wb_bte_i),
4850
    .wbm_we_o(wb_we_i),
4851
    .wbm_stb_o(wb_stb_i),
4852
    .wbm_cyc_o(wb_cyc_i),
4853
    .wbm_dat_i(wb_dat_o),
4854
    .wbm_ack_i(wb_ack_o),
4855
    .wbm_err_i(),
4856
    .wbm_rty_i(),
4857
    .wbs_dat_i(wbs_dat_i),
4858
    .wbs_adr_i(wbs_adr_i),
4859
    .wbs_sel_i(wbs_sel_i),
4860
    .wbs_cti_i(wbs_cti_i),
4861
    .wbs_bte_i(wbs_bte_i),
4862
    .wbs_we_i(wbs_we_i),
4863
    .wbs_stb_i(wbs_stb_i),
4864
    .wbs_cyc_i(wbs_cyc_i),
4865
    .wbs_dat_o(wbs_dat_o),
4866
    .wbs_ack_o(wbs_ack_o),
4867
    .wbs_err_o(1'b0),
4868
    .wbs_rty_o(1'b0),
4869
    .wb_clk(wb_clk),
4870
    .wb_rst(wb_rst)
4871
);
4872
end
4873
endgenerate
4874
 
4875
`define MODULE ram_be
4876
`BASE`MODULE # (
4877
    .data_width(dat_size),
4878
    .addr_width(adr_size),
4879
    .memory_init(1),
4880
    .memory_file("memory_file"))
4881
ram0(
4882
`undef MODULE
4883
    .d(wbs_dat_i),
4884
    .adr(wbs_adr_i[adr_size-1:2]),
4885
    .be(wbs_sel_i),
4886
    .we(wbs_we_i),
4887
    .q(wbs_dat_o),
4888
    .clk(wb_clk)
4889
);
4890
 
4891 59 unneback
always @ (posedge wb_clk or posedge wb_rst)
4892
if (wb_rst)
4893 60 unneback
    wbs_ack_o <= 1'b0;
4894 59 unneback
else
4895 60 unneback
    if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
4896
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
4897 59 unneback
    else
4898 60 unneback
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
4899
 
4900 59 unneback
endmodule
4901
`endif
4902
 
4903
`ifdef WB_B4_RAM_BE
4904
// WB RAM with byte enable
4905 49 unneback
`define MODULE wb_b4_ram_be
4906
module `BASE`MODULE (
4907
`undef MODULE
4908
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
4909 52 unneback
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
4910 49 unneback
 
4911
    parameter dat_width = 32;
4912
    parameter adr_width = 8;
4913
 
4914
input [dat_width-1:0] wb_dat_i;
4915
input [adr_width-1:0] wb_adr_i;
4916
input [dat_width/8-1:0] wb_sel_i;
4917
input wb_we_i, wb_stb_i, wb_cyc_i;
4918
output [dat_width-1:0] wb_dat_o;
4919 51 unneback
reg [dat_width-1:0] wb_dat_o;
4920 52 unneback
output wb_stall_o;
4921 49 unneback
output wb_ack_o;
4922
reg wb_ack_o;
4923
input wb_clk, wb_rst;
4924
 
4925 56 unneback
wire [dat_width/8-1:0] cke;
4926
 
4927 49 unneback
generate
4928
if (dat_width==32) begin
4929 51 unneback
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
4930
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
4931
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
4932
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
4933 56 unneback
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
4934 49 unneback
    always @ (posedge wb_clk)
4935
    begin
4936 56 unneback
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
4937
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
4938
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
4939
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
4940 49 unneback
    end
4941 59 unneback
    always @ (posedge wb_clk or posedge wb_rst)
4942
    begin
4943
        if (wb_rst)
4944
            wb_dat_o <= 32'h0;
4945
        else
4946
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
4947
    end
4948 49 unneback
end
4949
endgenerate
4950
 
4951 52 unneback
always @ (posedge wb_clk or posedge wb_rst)
4952 55 unneback
if (wb_rst)
4953 52 unneback
    wb_ack_o <= 1'b0;
4954
else
4955 54 unneback
    wb_ack_o <= wb_stb_i & wb_cyc_i;
4956 52 unneback
 
4957
assign wb_stall_o = 1'b0;
4958
 
4959 49 unneback
endmodule
4960
`endif
4961
 
4962 48 unneback
`ifdef WB_B4_ROM
4963
// WB ROM
4964
`define MODULE wb_b4_rom
4965
module `BASE`MODULE (
4966
`undef MODULE
4967
    wb_adr_i, wb_stb_i, wb_cyc_i,
4968
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
4969
 
4970
    parameter dat_width = 32;
4971
    parameter dat_default = 32'h15000000;
4972
    parameter adr_width = 32;
4973
 
4974
/*
4975
`ifndef ROM
4976
`define ROM "rom.v"
4977
`endif
4978
*/
4979
    input [adr_width-1:2]   wb_adr_i;
4980
    input                   wb_stb_i;
4981
    input                   wb_cyc_i;
4982
    output [dat_width-1:0]  wb_dat_o;
4983
    reg [dat_width-1:0]     wb_dat_o;
4984
    output                  wb_ack_o;
4985
    reg                     wb_ack_o;
4986
    output                  stall_o;
4987
    input                   wb_clk;
4988
    input                   wb_rst;
4989
 
4990
always @ (posedge wb_clk or posedge wb_rst)
4991
    if (wb_rst)
4992
        wb_dat_o <= {dat_width{1'b0}};
4993
    else
4994
         case (wb_adr_i[adr_width-1:2])
4995
`ifdef ROM
4996
`include `ROM
4997
`endif
4998
           default:
4999
             wb_dat_o <= dat_default;
5000
 
5001
         endcase // case (wb_adr_i)
5002
 
5003
 
5004
always @ (posedge wb_clk or posedge wb_rst)
5005
    if (wb_rst)
5006
        wb_ack_o <= 1'b0;
5007
    else
5008
        wb_ack_o <= wb_stb_i & wb_cyc_i;
5009
 
5010
assign stall_o = 1'b0;
5011
 
5012
endmodule
5013
`endif
5014
 
5015
 
5016 40 unneback
`ifdef WB_BOOT_ROM
5017 17 unneback
// WB ROM
5018 40 unneback
`define MODULE wb_boot_rom
5019
module `BASE`MODULE (
5020
`undef MODULE
5021 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
5022 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
5023 17 unneback
 
5024 18 unneback
    parameter adr_hi = 31;
5025
    parameter adr_lo = 28;
5026
    parameter adr_sel = 4'hf;
5027
    parameter addr_width = 5;
5028 33 unneback
/*
5029 17 unneback
`ifndef BOOT_ROM
5030
`define BOOT_ROM "boot_rom.v"
5031
`endif
5032 33 unneback
*/
5033 18 unneback
    input [adr_hi:2]    wb_adr_i;
5034
    input               wb_stb_i;
5035
    input               wb_cyc_i;
5036
    output [31:0]        wb_dat_o;
5037
    output              wb_ack_o;
5038
    output              hit_o;
5039
    input               wb_clk;
5040
    input               wb_rst;
5041
 
5042
    wire hit;
5043
    reg [31:0] wb_dat;
5044
    reg wb_ack;
5045
 
5046
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
5047 17 unneback
 
5048
always @ (posedge wb_clk or posedge wb_rst)
5049
    if (wb_rst)
5050 18 unneback
        wb_dat <= 32'h15000000;
5051 17 unneback
    else
5052 18 unneback
         case (wb_adr_i[addr_width-1:2])
5053 33 unneback
`ifdef BOOT_ROM
5054 17 unneback
`include `BOOT_ROM
5055 33 unneback
`endif
5056 17 unneback
           /*
5057
            // Zero r0 and jump to 0x00000100
5058 18 unneback
 
5059
            1 : wb_dat <= 32'hA8200000;
5060
            2 : wb_dat <= 32'hA8C00100;
5061
            3 : wb_dat <= 32'h44003000;
5062
            4 : wb_dat <= 32'h15000000;
5063 17 unneback
            */
5064
           default:
5065 18 unneback
             wb_dat <= 32'h00000000;
5066 17 unneback
 
5067
         endcase // case (wb_adr_i)
5068
 
5069
 
5070
always @ (posedge wb_clk or posedge wb_rst)
5071
    if (wb_rst)
5072 18 unneback
        wb_ack <= 1'b0;
5073 17 unneback
    else
5074 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
5075 17 unneback
 
5076 18 unneback
assign hit_o = hit;
5077
assign wb_dat_o = wb_dat & {32{wb_ack}};
5078
assign wb_ack_o = wb_ack;
5079
 
5080 17 unneback
endmodule
5081 40 unneback
`endif
5082 32 unneback
 
5083 40 unneback
`ifdef WB_DPRAM
5084
`define MODULE wb_dpram
5085
module `BASE`MODULE (
5086
`undef MODULE
5087 32 unneback
        // wishbone slave side a
5088
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
5089
        wbsa_clk, wbsa_rst,
5090
        // wishbone slave side a
5091
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
5092
        wbsb_clk, wbsb_rst);
5093
 
5094
parameter data_width = 32;
5095
parameter addr_width = 8;
5096
 
5097
parameter dat_o_mask_a = 1;
5098
parameter dat_o_mask_b = 1;
5099
 
5100
input [31:0] wbsa_dat_i;
5101
input [addr_width-1:2] wbsa_adr_i;
5102
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
5103
output [31:0] wbsa_dat_o;
5104
output wbsa_ack_o;
5105
input wbsa_clk, wbsa_rst;
5106
 
5107
input [31:0] wbsb_dat_i;
5108
input [addr_width-1:2] wbsb_adr_i;
5109
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
5110
output [31:0] wbsb_dat_o;
5111
output wbsb_ack_o;
5112
input wbsb_clk, wbsb_rst;
5113
 
5114
wire wbsa_dat_tmp, wbsb_dat_tmp;
5115
 
5116 40 unneback
`define MODULE dpram_2r2w
5117
`BASE`MODULE # (
5118
`undef MODULE
5119 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
5120 32 unneback
dpram0(
5121
    .d_a(wbsa_dat_i),
5122
    .q_a(wbsa_dat_tmp),
5123
    .adr_a(wbsa_adr_i),
5124
    .we_a(wbsa_we_i),
5125
    .clk_a(wbsa_clk),
5126
    .d_b(wbsb_dat_i),
5127
    .q_b(wbsb_dat_tmp),
5128
    .adr_b(wbsb_adr_i),
5129
    .we_b(wbsb_we_i),
5130
    .clk_b(wbsb_clk) );
5131
 
5132 33 unneback
generate if (dat_o_mask_a==1)
5133 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
5134
endgenerate
5135 33 unneback
generate if (dat_o_mask_a==0)
5136 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
5137
endgenerate
5138
 
5139 33 unneback
generate if (dat_o_mask_b==1)
5140 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
5141
endgenerate
5142 33 unneback
generate if (dat_o_mask_b==0)
5143 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
5144
endgenerate
5145
 
5146 40 unneback
`define MODULE spr
5147
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
5148
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
5149
`undef MODULE
5150 32 unneback
 
5151
endmodule
5152 40 unneback
`endif
5153 18 unneback
//////////////////////////////////////////////////////////////////////
5154
////                                                              ////
5155
////  Arithmetic functions                                        ////
5156
////                                                              ////
5157
////  Description                                                 ////
5158
////  Arithmetic functions for ALU and DSP                        ////
5159
////                                                              ////
5160
////                                                              ////
5161
////  To Do:                                                      ////
5162
////   -                                                          ////
5163
////                                                              ////
5164
////  Author(s):                                                  ////
5165
////      - Michael Unneback, unneback@opencores.org              ////
5166
////        ORSoC AB                                              ////
5167
////                                                              ////
5168
//////////////////////////////////////////////////////////////////////
5169
////                                                              ////
5170
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
5171
////                                                              ////
5172
//// This source file may be used and distributed without         ////
5173
//// restriction provided that this copyright statement is not    ////
5174
//// removed from the file and that any derivative work contains  ////
5175
//// the original copyright notice and the associated disclaimer. ////
5176
////                                                              ////
5177
//// This source file is free software; you can redistribute it   ////
5178
//// and/or modify it under the terms of the GNU Lesser General   ////
5179
//// Public License as published by the Free Software Foundation; ////
5180
//// either version 2.1 of the License, or (at your option) any   ////
5181
//// later version.                                               ////
5182
////                                                              ////
5183
//// This source is distributed in the hope that it will be       ////
5184
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
5185
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
5186
//// PURPOSE.  See the GNU Lesser General Public License for more ////
5187
//// details.                                                     ////
5188
////                                                              ////
5189
//// You should have received a copy of the GNU Lesser General    ////
5190
//// Public License along with this source; if not, download it   ////
5191
//// from http://www.opencores.org/lgpl.shtml                     ////
5192
////                                                              ////
5193
//////////////////////////////////////////////////////////////////////
5194
 
5195 40 unneback
`ifdef MULTS
5196 18 unneback
// signed multiplication
5197 40 unneback
`define MODULE mults
5198
module `BASE`MODULE (a,b,p);
5199
`undef MODULE
5200 18 unneback
parameter operand_a_width = 18;
5201
parameter operand_b_width = 18;
5202
parameter result_hi = 35;
5203
parameter result_lo = 0;
5204
input [operand_a_width-1:0] a;
5205
input [operand_b_width-1:0] b;
5206
output [result_hi:result_lo] p;
5207
wire signed [operand_a_width-1:0] ai;
5208
wire signed [operand_b_width-1:0] bi;
5209
wire signed [operand_a_width+operand_b_width-1:0] result;
5210
 
5211
    assign ai = a;
5212
    assign bi = b;
5213
    assign result = ai * bi;
5214
    assign p = result[result_hi:result_lo];
5215
 
5216
endmodule
5217 40 unneback
`endif
5218
`ifdef MULTS18X18
5219
`define MODULE mults18x18
5220
module `BASE`MODULE (a,b,p);
5221
`undef MODULE
5222 18 unneback
input [17:0] a,b;
5223
output [35:0] p;
5224
vl_mult
5225
    # (.operand_a_width(18), .operand_b_width(18))
5226
    mult0 (.a(a), .b(b), .p(p));
5227
endmodule
5228 40 unneback
`endif
5229 18 unneback
 
5230 40 unneback
`ifdef MULT
5231
`define MODULE mult
5232 18 unneback
// unsigned multiplication
5233 40 unneback
module `BASE`MODULE (a,b,p);
5234
`undef MODULE
5235 18 unneback
parameter operand_a_width = 18;
5236
parameter operand_b_width = 18;
5237
parameter result_hi = 35;
5238
parameter result_lo = 0;
5239
input [operand_a_width-1:0] a;
5240
input [operand_b_width-1:0] b;
5241
output [result_hi:result_hi] p;
5242
 
5243
wire [operand_a_width+operand_b_width-1:0] result;
5244
 
5245
    assign result = a * b;
5246
    assign p = result[result_hi:result_lo];
5247
 
5248
endmodule
5249 40 unneback
`endif
5250 18 unneback
 
5251 40 unneback
`ifdef SHIFT_UNIT_32
5252
`define MODULE shift_unit_32
5253 18 unneback
// shift unit
5254
// supporting the following shift functions
5255
//   SLL
5256
//   SRL
5257
//   SRA
5258
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
5259 40 unneback
module `BASE`MODULE( din, s, dout, opcode);
5260
`undef MODULE
5261 18 unneback
input [31:0] din; // data in operand
5262
input [4:0] s; // shift operand
5263
input [1:0] opcode;
5264
output [31:0] dout;
5265
 
5266
parameter opcode_sll = 2'b00;
5267
//parameter opcode_srl = 2'b01;
5268
parameter opcode_sra = 2'b10;
5269
//parameter opcode_ror = 2'b11;
5270
 
5271
wire sll, sra;
5272
assign sll = opcode == opcode_sll;
5273
assign sra = opcode == opcode_sra;
5274
 
5275
wire [15:1] s1;
5276
wire [3:0] sign;
5277
wire [7:0] tmp [0:3];
5278
 
5279
// first stage is multiplier based
5280
// shift operand as fractional 8.7
5281
assign s1[15] = sll & s[2:0]==3'd7;
5282
assign s1[14] = sll & s[2:0]==3'd6;
5283
assign s1[13] = sll & s[2:0]==3'd5;
5284
assign s1[12] = sll & s[2:0]==3'd4;
5285
assign s1[11] = sll & s[2:0]==3'd3;
5286
assign s1[10] = sll & s[2:0]==3'd2;
5287
assign s1[ 9] = sll & s[2:0]==3'd1;
5288
assign s1[ 8] = s[2:0]==3'd0;
5289
assign s1[ 7] = !sll & s[2:0]==3'd1;
5290
assign s1[ 6] = !sll & s[2:0]==3'd2;
5291
assign s1[ 5] = !sll & s[2:0]==3'd3;
5292
assign s1[ 4] = !sll & s[2:0]==3'd4;
5293
assign s1[ 3] = !sll & s[2:0]==3'd5;
5294
assign s1[ 2] = !sll & s[2:0]==3'd6;
5295
assign s1[ 1] = !sll & s[2:0]==3'd7;
5296
 
5297
assign sign[3] = din[31] & sra;
5298
assign sign[2] = sign[3] & (&din[31:24]);
5299
assign sign[1] = sign[2] & (&din[23:16]);
5300
assign sign[0] = sign[1] & (&din[15:8]);
5301 40 unneback
`define MODULE mults
5302
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
5303
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
5304
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
5305
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
5306
`undef MODULE
5307 18 unneback
// second stage is multiplexer based
5308
// shift on byte level
5309
 
5310
// mux byte 3
5311
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
5312
                     (sll & s[4:3]==2'b01) ? tmp[2] :
5313
                     (sll & s[4:3]==2'b10) ? tmp[1] :
5314
                     (sll & s[4:3]==2'b11) ? tmp[0] :
5315
                     {8{sign[3]}};
5316
 
5317
// mux byte 2
5318
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
5319
                     (sll & s[4:3]==2'b01) ? tmp[1] :
5320
                     (sll & s[4:3]==2'b10) ? tmp[0] :
5321
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5322
                     (s[4:3]==2'b01) ? tmp[3] :
5323
                     {8{sign[3]}};
5324
 
5325
// mux byte 1
5326
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
5327
                     (sll & s[4:3]==2'b01) ? tmp[0] :
5328
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
5329
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5330
                     (s[4:3]==2'b01) ? tmp[2] :
5331
                     (s[4:3]==2'b10) ? tmp[3] :
5332
                     {8{sign[3]}};
5333
 
5334
// mux byte 0
5335
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
5336
                     (sll) ?  {8{1'b0}}:
5337
                     (s[4:3]==2'b01) ? tmp[1] :
5338
                     (s[4:3]==2'b10) ? tmp[2] :
5339
                     tmp[3];
5340
 
5341
endmodule
5342 40 unneback
`endif
5343 18 unneback
 
5344 40 unneback
`ifdef LOGIC_UNIT
5345 18 unneback
// logic unit
5346
// supporting the following logic functions
5347
//    a and b
5348
//    a or  b
5349
//    a xor b
5350
//    not b
5351 40 unneback
`define MODULE logic_unit
5352
module `BASE`MODULE( a, b, result, opcode);
5353
`undef MODULE
5354 18 unneback
parameter width = 32;
5355
parameter opcode_and = 2'b00;
5356
parameter opcode_or  = 2'b01;
5357
parameter opcode_xor = 2'b10;
5358
input [width-1:0] a,b;
5359
output [width-1:0] result;
5360
input [1:0] opcode;
5361
 
5362
assign result = (opcode==opcode_and) ? a & b :
5363
                (opcode==opcode_or)  ? a | b :
5364
                (opcode==opcode_xor) ? a ^ b :
5365
                b;
5366
 
5367
endmodule
5368 48 unneback
`endif
5369 18 unneback
 
5370 48 unneback
`ifdef ARITH_UNIT
5371
`define MODULE arith_unit
5372
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
5373
`undef MODULE
5374 18 unneback
parameter width = 32;
5375
parameter opcode_add = 1'b0;
5376
parameter opcode_sub = 1'b1;
5377
input [width-1:0] a,b;
5378
input c_in, add_sub, sign;
5379
output [width-1:0] result;
5380
output c_out, z, ovfl;
5381
 
5382
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
5383
assign z = (result=={width{1'b0}});
5384
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
5385
               (~a[width-1] & ~b[width-1] &  result[width-1]);
5386
endmodule
5387 40 unneback
`endif
5388 48 unneback
 
5389
`ifdef COUNT_UNIT
5390
`define MODULE count_unit
5391
module `BASE`MODULE (din, dout, opcode);
5392
`undef MODULE
5393
parameter width = 32;
5394
input [width-1:0] din;
5395
output [width-1:0] dout;
5396
input opcode;
5397
 
5398
integer i;
5399 58 unneback
wire [width/32+4:0] ff1, fl1;
5400 48 unneback
 
5401 57 unneback
/*
5402 48 unneback
always @(din) begin
5403
    ff1 = 0; i = 0;
5404
    while (din[i] == 0 && i < width) begin // complex condition
5405
        ff1 = ff1 + 1;
5406
        i = i + 1;
5407
    end
5408
end
5409
 
5410
always @(din) begin
5411
    fl1 = width; i = width-1;
5412
    while (din[i] == 0 && i >= width) begin // complex condition
5413
        fl1 = fl1 - 1;
5414
        i = i - 1;
5415
    end
5416
end
5417 57 unneback
*/
5418 48 unneback
 
5419
generate
5420
if (width==32) begin
5421 57 unneback
 
5422
    assign ff1 = din[0] ? 6'd1 :
5423
                 din[1] ? 6'd2 :
5424
                 din[2] ? 6'd3 :
5425
                 din[3] ? 6'd4 :
5426
                 din[4] ? 6'd5 :
5427
                 din[5] ? 6'd6 :
5428
                 din[6] ? 6'd7 :
5429
                 din[7] ? 6'd8 :
5430
                 din[8] ? 6'd9 :
5431
                 din[9] ? 6'd10 :
5432
                 din[10] ? 6'd11 :
5433
                 din[11] ? 6'd12 :
5434
                 din[12] ? 6'd13 :
5435
                 din[13] ? 6'd14 :
5436
                 din[14] ? 6'd15 :
5437
                 din[15] ? 6'd16 :
5438
                 din[16] ? 6'd17 :
5439
                 din[17] ? 6'd18 :
5440
                 din[18] ? 6'd19 :
5441
                 din[19] ? 6'd20 :
5442
                 din[20] ? 6'd21 :
5443
                 din[21] ? 6'd22 :
5444
                 din[22] ? 6'd23 :
5445
                 din[23] ? 6'd24 :
5446
                 din[24] ? 6'd25 :
5447
                 din[25] ? 6'd26 :
5448
                 din[26] ? 6'd27 :
5449
                 din[27] ? 6'd28 :
5450
                 din[28] ? 6'd29 :
5451
                 din[29] ? 6'd30 :
5452
                 din[30] ? 6'd31 :
5453
                 din[31] ? 6'd32 :
5454
                 6'd0;
5455
 
5456
    assign fl1 = din[31] ? 6'd32 :
5457
                 din[30] ? 6'd31 :
5458
                 din[29] ? 6'd30 :
5459
                 din[28] ? 6'd29 :
5460
                 din[27] ? 6'd28 :
5461
                 din[26] ? 6'd27 :
5462
                 din[25] ? 6'd26 :
5463
                 din[24] ? 6'd25 :
5464
                 din[23] ? 6'd24 :
5465
                 din[22] ? 6'd23 :
5466
                 din[21] ? 6'd22 :
5467
                 din[20] ? 6'd21 :
5468
                 din[19] ? 6'd20 :
5469
                 din[18] ? 6'd19 :
5470
                 din[17] ? 6'd18 :
5471
                 din[16] ? 6'd17 :
5472
                 din[15] ? 6'd16 :
5473
                 din[14] ? 6'd15 :
5474
                 din[13] ? 6'd14 :
5475
                 din[12] ? 6'd13 :
5476
                 din[11] ? 6'd12 :
5477
                 din[10] ? 6'd11 :
5478
                 din[9] ? 6'd10 :
5479
                 din[8] ? 6'd9 :
5480
                 din[7] ? 6'd8 :
5481
                 din[6] ? 6'd7 :
5482
                 din[5] ? 6'd6 :
5483
                 din[4] ? 6'd5 :
5484
                 din[3] ? 6'd4 :
5485
                 din[2] ? 6'd3 :
5486
                 din[1] ? 6'd2 :
5487
                 din[0] ? 6'd1 :
5488
                 6'd0;
5489
 
5490
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
5491 48 unneback
end
5492
endgenerate
5493 57 unneback
 
5494 48 unneback
generate
5495
if (width==64) begin
5496 57 unneback
    assign ff1 = 7'd0;
5497
    assign fl1 = 7'd0;
5498
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
5499 48 unneback
end
5500
endgenerate
5501
 
5502
endmodule
5503
`endif
5504
 
5505
`ifdef EXT_UNIT
5506
`define MODULE ext_unit
5507
module `BASE`MODULE ( a, b, F, result, opcode);
5508
`undef MODULE
5509
parameter width = 32;
5510
input [width-1:0] a, b;
5511
input F;
5512
output reg [width-1:0] result;
5513
input [2:0] opcode;
5514
 
5515
generate
5516
if (width==32) begin
5517
always @ (a or b or F or opcode)
5518
begin
5519
    case (opcode)
5520
    3'b000: result = {{24{1'b0}},a[7:0]};
5521
    3'b001: result = {{24{a[7]}},a[7:0]};
5522
    3'b010: result = {{16{1'b0}},a[7:0]};
5523
    3'b011: result = {{16{a[15]}},a[15:0]};
5524
    3'b110: result = (F) ? a : b;
5525
    default: result = {b[15:0],16'h0000};
5526
    endcase
5527
end
5528
end
5529
endgenerate
5530
 
5531
generate
5532
if (width==64) begin
5533
always @ (a or b or F or opcode)
5534
begin
5535
    case (opcode)
5536
    3'b000: result = {{56{1'b0}},a[7:0]};
5537
    3'b001: result = {{56{a[7]}},a[7:0]};
5538
    3'b010: result = {{48{1'b0}},a[7:0]};
5539
    3'b011: result = {{48{a[15]}},a[15:0]};
5540 57 unneback
    3'b110: result = (F) ? a : b;
5541 48 unneback
    default: result = {32'h00000000,b[15:0],16'h0000};
5542
    endcase
5543
end
5544
end
5545
endgenerate
5546
endmodule
5547
`endif

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