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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 70

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 40 unneback 
`ifdef ALL
14 
 
15 
`define GBUF
16 
`define SYNC_RST
17 
`define PLL
18 
 
19 
`define MULTS
20 
`define MULTS18X18
21 
`define MULT
22 
`define SHIFT_UNIT_32
23 
`define LOGIC_UNIT
24 
 
25 
`define CNT_SHREG_WRAP
26 
`define CNT_SHREG_CE_WRAP
27 
`define CNT_SHREG_CE_CLEAR
28 
`define CNT_SHREG_CE_CLEAR_WRAP
29 
 
30 
`define MUX_ANDOR
31 
`define MUX2_ANDOR
32 
`define MUX3_ANDOR
33 
`define MUX4_ANDOR
34 
`define MUX5_ANDOR
35 
`define MUX6_ANDOR
36 43 unneback 
`define PARITY
37 40 unneback 
 
38 
`define ROM_INIT
39 
`define RAM
40 
`define RAM_BE
41 
`define DPRAM_1R1W
42 
`define DPRAM_2R1W
43 
`define DPRAM_2R2W
44 
`define FIFO_1R1W_FILL_LEVEL_SYNC
45 
`define FIFO_2R2W_SYNC_SIMPLEX
46 
`define FIFO_CMP_ASYNC
47 
`define FIFO_1R1W_ASYNC
48 
`define FIFO_2R2W_ASYNC
49 
`define FIFO_2R2W_ASYNC_SIMPLEX
50 48 unneback 
`define REG_FILE
51 40 unneback 
 
52 
`define DFF
53 
`define DFF_ARRAY
54 
`define DFF_CE
55 
`define DFF_CE_CLEAR
56 
`define DF_CE_SET
57 
`define SPR
58 
`define SRP
59 
`define DFF_SR
60 
`define LATCH
61 
`define SHREG
62 
`define SHREG_CE
63 
`define DELAY
64 
`define DELAY_EMPTYFLAG
65 
 
66 
`define WB3WB3_BRIDGE
67 
`define WB3_ARBITER_TYPE1
68 59 unneback 
`define WB_B3_RAM_BE
69 49 unneback 
`define WB_B4_RAM_BE
70 48 unneback 
`define WB_B4_ROM
71 40 unneback 
`define WB_BOOT_ROM
72 
`define WB_DPRAM
73 
 
74 44 unneback 
`define IO_DFF_OE
75 
`define O_DFF
76 
 
77 40 unneback 
`endif
78 
 
79 
`ifdef PLL
80 
`ifndef SYNC_RST
81 
`define SYNC_RST
82 
`endif
83 
`endif
84 
 
85 
`ifdef SYNC_RST
86 
`ifndef GBUF
87 
`define GBUF
88 
`endif
89 
`endif
90 
 
91 
`ifdef WB_DPRAM
92 
`ifndef DPRAM_2R2W
93 
`define DPRAM_2R2W
94 
`endif
95 
`ifndef SPR
96 
`define SPR
97 
`endif
98 
`endif
99 
 
100 62 unneback 
`ifdef WB_B3_RAM_BE
101 
`ifndef WB3_ARBITER_TYPE1
102 
`define WB3_ARBITER_TYPE1
103 
`endif
104 
`ifndef RAM_BE
105 
`define RAM_BE
106 
`endif
107 
`endif
108 
 
109 40 unneback 
`ifdef WB3_ARBITER_TYPE1
110 42 unneback 
`ifndef SPR
111 
`define SPR
112 
`endif
113 40 unneback 
`ifndef MUX_ANDOR
114 
`define MUX_ANDOR
115 
`endif
116 
`endif
117 
 
118 
`ifdef WB3WB3_BRIDGE
119 
`ifndef CNT_SHREG_CE_CLEAR
120 
`define CNT_SHREG_CE_CLEAR
121 
`endif
122 
`ifndef DFF
123 
`define DFF
124 
`endif
125 
`ifndef DFF_CE
126 
`define DFF_CE
127 
`endif
128 
`ifndef CNT_SHREG_CE_CLEAR
129 
`define CNT_SHREG_CE_CLEAR
130 
`endif
131 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
132 
`define FIFO_2R2W_ASYNC_SIMPLEX
133 
`endif
134 
`endif
135 
 
136 
`ifdef MULTS18X18
137 
`ifndef MULTS
138 
`define MULTS
139 
`endif
140 
`endif
141 
 
142 
`ifdef SHIFT_UNIT_32
143 
`ifndef MULTS
144 
`define MULTS
145 
`endif
146 
`endif
147 
 
148 
`ifdef MUX2_ANDOR
149 
`ifndef MUX_ANDOR
150 
`define MUX_ANDOR
151 
`endif
152 
`endif
153 
 
154 
`ifdef MUX3_ANDOR
155 
`ifndef MUX_ANDOR
156 
`define MUX_ANDOR
157 
`endif
158 
`endif
159 
 
160 
`ifdef MUX4_ANDOR
161 
`ifndef MUX_ANDOR
162 
`define MUX_ANDOR
163 
`endif
164 
`endif
165 
 
166 
`ifdef MUX5_ANDOR
167 
`ifndef MUX_ANDOR
168 
`define MUX_ANDOR
169 
`endif
170 
`endif
171 
 
172 
`ifdef MUX6_ANDOR
173 
`ifndef MUX_ANDOR
174 
`define MUX_ANDOR
175 
`endif
176 
`endif
177 
 
178 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
179 
`ifndef CNT_BIN_CE
180 
`define CNT_BIN_CE
181 
`endif
182 
`ifndef DPRAM_1R1W
183 
`define DPRAM_1R1W
184 
`endif
185 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
186 
`define CNT_BIN_CE_REW_Q_ZQ_L1
187 
`endif
188 
`endif
189 
 
190 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
191 
`ifndef CNT_LFSR_CE
192 
`define CNT_LFSR_CE
193 
`endif
194 
`ifndef DPRAM_2R2W
195 
`define DPRAM_2R2W
196 
`endif
197 
`ifndef CNT_BIN_CE_REW_ZQ_L1
198 
`define CNT_BIN_CE_REW_ZQ_L1
199 
`endif
200 
`endif
201 
 
202 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
203 
`ifndef CNT_GRAY_CE_BIN
204 
`define CNT_GRAY_CE_BIN
205 
`endif
206 
`ifndef DPRAM_2R2W
207 
`define DPRAM_2R2W
208 
`endif
209 
`ifndef FIFO_CMP_ASYNC
210 
`define FIFO_CMP_ASYNC
211 
`endif
212 
`endif
213 
 
214 
`ifdef FIFO_2R2W_ASYNC
215 
`ifndef FIFO_1R1W_ASYNC
216 
`define FIFO_1R1W_ASYNC
217 
`endif
218 
`endif
219 
 
220 
`ifdef FIFO_1R1W_ASYNC
221 
`ifndef CNT_GRAY_CE_BIN
222 
`define CNT_GRAY_CE_BIN
223 
`endif
224 
`ifndef DPRAM_1R1W
225 
`define DPRAM_1R1W
226 
`endif
227 
`ifndef FIFO_CMP_ASYNC
228 
`define FIFO_CMP_ASYNC
229 
`endif
230 
`endif
231 
 
232 
`ifdef FIFO_CMP_ASYNC
233 
`ifndef DFF_SR
234 
`define DFF_SR
235 
`endif
236 
`ifndef DFF
237 
`define DFF
238 
`endif
239 
`endif
240 48 unneback 
 
241 
`ifdef REG_FILE
242 
`ifndef DPRAM_1R1W
243 
`define DPRAM_1R1W
244 
`endif
245 
`endif
246 62 unneback 
//////////////////////////////////////////////////////////////////////
247 6 unneback 
////                                                              ////
248 
////  Versatile library, clock and reset                          ////
249 
////                                                              ////
250 
////  Description                                                 ////
251 
////  Logic related to clock and reset                            ////
252 
////                                                              ////
253 
////                                                              ////
254 
////  To Do:                                                      ////
255 
////   - add more different registers                             ////
256 
////                                                              ////
257 
////  Author(s):                                                  ////
258 
////      - Michael Unneback, unneback@opencores.org              ////
259 
////        ORSoC AB                                              ////
260 
////                                                              ////
261 
//////////////////////////////////////////////////////////////////////
262 
////                                                              ////
263 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
264 
////                                                              ////
265 
//// This source file may be used and distributed without         ////
266 
//// restriction provided that this copyright statement is not    ////
267 
//// removed from the file and that any derivative work contains  ////
268 
//// the original copyright notice and the associated disclaimer. ////
269 
////                                                              ////
270 
//// This source file is free software; you can redistribute it   ////
271 
//// and/or modify it under the terms of the GNU Lesser General   ////
272 
//// Public License as published by the Free Software Foundation; ////
273 
//// either version 2.1 of the License, or (at your option) any   ////
274 
//// later version.                                               ////
275 
////                                                              ////
276 
//// This source is distributed in the hope that it will be       ////
277 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
278 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
279 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
280 
//// details.                                                     ////
281 
////                                                              ////
282 
//// You should have received a copy of the GNU Lesser General    ////
283 
//// Public License along with this source; if not, download it   ////
284 
//// from http://www.opencores.org/lgpl.shtml                     ////
285 
////                                                              ////
286 
//////////////////////////////////////////////////////////////////////
287 
 
288 48 unneback 
`ifdef ACTEL
289 
`ifdef GBUF
290 
`timescale 1 ns/100 ps
291 6 unneback 
// Global buffer
292 
// usage:
293 
// use to enable global buffers for high fan out signals such as clock and reset
294 
// Version: 8.4 8.4.0.33
295 
module gbuf(GL,CLK);
296 
output GL;
297 
input  CLK;
298 
 
299 
    wire GND;
300 
 
301 
    GND GND_1_net(.Y(GND));
302 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
303 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
304 
 
305 
endmodule
306 
`timescale 1 ns/1 ns
307 40 unneback 
`define MODULE gbuf
308 
module `BASE`MODULE ( i, o);
309 
`undef MODULE
310 6 unneback 
input i;
311 
output o;
312 
`ifdef SIM_GBUF
313 
assign o=i;
314 
`else
315 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
316 
`endif
317 
endmodule
318 40 unneback 
`endif
319 33 unneback 
 
320 6 unneback 
`else
321 33 unneback 
 
322 40 unneback 
`ifdef ALTERA
323 
`ifdef GBUF
324 21 unneback 
//altera
325 40 unneback 
`define MODULE gbuf
326 
module `BASE`MODULE ( i, o);
327 
`undef MODULE
328 33 unneback 
input i;
329 
output o;
330 
assign o = i;
331 
endmodule
332 40 unneback 
`endif
333 33 unneback 
 
334 6 unneback 
`else
335 
 
336 40 unneback 
`ifdef GBUF
337 6 unneback 
`timescale 1 ns/100 ps
338 40 unneback 
`define MODULE
339 
module `BASE`MODULE ( i, o);
340 
`undef MODULE
341 6 unneback 
input i;
342 
output o;
343 
assign o = i;
344 
endmodule
345 40 unneback 
`endif
346 6 unneback 
`endif // ALTERA
347 
`endif //ACTEL
348 
 
349 40 unneback 
`ifdef SYNC_RST
350 6 unneback 
// sync reset
351 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
352 6 unneback 
// output active high global reset sync with two DFFs
353 
`timescale 1 ns/100 ps
354 40 unneback 
`define MODULE sync_rst
355 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
356 
`undef MODULE
357 6 unneback 
input rst_n_i, clk;
358 
output rst_o;
359 18 unneback 
reg [1:0] tmp;
360 6 unneback 
always @ (posedge clk or negedge rst_n_i)
361 
if (!rst_n_i)
362 17 unneback 
        tmp <= 2'b11;
363 6 unneback 
else
364 33 unneback 
        tmp <= {1'b0,tmp[1]};
365 40 unneback 
`define MODULE gbuf
366 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
367 
`undef MODULE
368 6 unneback 
endmodule
369 40 unneback 
`endif
370 6 unneback 
 
371 40 unneback 
`ifdef PLL
372 6 unneback 
// vl_pll
373 
`ifdef ACTEL
374 32 unneback 
///////////////////////////////////////////////////////////////////////////////
375 17 unneback 
`timescale 1 ps/1 ps
376 40 unneback 
`define MODULE pll
377 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
378 
`undef MODULE
379 6 unneback 
parameter index = 0;
380 
parameter number_of_clk = 1;
381 17 unneback 
parameter period_time_0 = 20000;
382 
parameter period_time_1 = 20000;
383 
parameter period_time_2 = 20000;
384 
parameter lock_delay = 2000000;
385 6 unneback 
input clk_i, rst_n_i;
386 
output lock;
387 
output reg [0:number_of_clk-1] clk_o;
388 
output [0:number_of_clk-1] rst_o;
389 
 
390 
`ifdef SIM_PLL
391 
 
392 
always
393 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
394 
 
395 
generate if (number_of_clk > 1)
396 
always
397 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
398 
endgenerate
399 
 
400 
generate if (number_of_clk > 2)
401 
always
402 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
403 
endgenerate
404 
 
405 
genvar i;
406 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
407 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
408 
end
409 
endgenerate
410 
 
411 
assign #lock_delay lock = rst_n_i;
412 
 
413 
endmodule
414 
`else
415 
generate if (number_of_clk==1 & index==0) begin
416 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
417 
end
418 
endgenerate // index==0
419 
generate if (number_of_clk==1 & index==1) begin
420 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
421 
end
422 
endgenerate // index==1
423 
generate if (number_of_clk==1 & index==2) begin
424 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
425 
end
426 
endgenerate // index==2
427 
generate if (number_of_clk==1 & index==3) begin
428 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
429 
end
430 
endgenerate // index==0
431 
 
432 
generate if (number_of_clk==2 & index==0) begin
433 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
434 
end
435 
endgenerate // index==0
436 
generate if (number_of_clk==2 & index==1) begin
437 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
438 
end
439 
endgenerate // index==1
440 
generate if (number_of_clk==2 & index==2) begin
441 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
442 
end
443 
endgenerate // index==2
444 
generate if (number_of_clk==2 & index==3) begin
445 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
446 
end
447 
endgenerate // index==0
448 
 
449 
generate if (number_of_clk==3 & index==0) begin
450 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
451 
end
452 
endgenerate // index==0
453 
generate if (number_of_clk==3 & index==1) begin
454 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
455 
end
456 
endgenerate // index==1
457 
generate if (number_of_clk==3 & index==2) begin
458 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
459 
end
460 
endgenerate // index==2
461 
generate if (number_of_clk==3 & index==3) begin
462 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
463 
end
464 
endgenerate // index==0
465 
 
466 
genvar i;
467 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
468 40 unneback 
`define MODULE sync_rst
469 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
470 
`undef MODULE
471 6 unneback 
end
472 
endgenerate
473 
endmodule
474 
`endif
475 32 unneback 
///////////////////////////////////////////////////////////////////////////////
476 6 unneback 
 
477 
`else
478 
 
479 32 unneback 
///////////////////////////////////////////////////////////////////////////////
480 6 unneback 
`ifdef ALTERA
481 
 
482 32 unneback 
`timescale 1 ps/1 ps
483 40 unneback 
`define MODULE pll
484 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
485 
`undef MODULE
486 32 unneback 
parameter index = 0;
487 
parameter number_of_clk = 1;
488 
parameter period_time_0 = 20000;
489 
parameter period_time_1 = 20000;
490 
parameter period_time_2 = 20000;
491 
parameter period_time_3 = 20000;
492 
parameter period_time_4 = 20000;
493 
parameter lock_delay = 2000000;
494 
input clk_i, rst_n_i;
495 
output lock;
496 
output reg [0:number_of_clk-1] clk_o;
497 
output [0:number_of_clk-1] rst_o;
498 
 
499 
`ifdef SIM_PLL
500 
 
501 
always
502 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
503 
 
504 
generate if (number_of_clk > 1)
505 
always
506 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
507 
endgenerate
508 
 
509 
generate if (number_of_clk > 2)
510 
always
511 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
512 
endgenerate
513 
 
514 33 unneback 
generate if (number_of_clk > 3)
515 32 unneback 
always
516 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
517 
endgenerate
518 
 
519 33 unneback 
generate if (number_of_clk > 4)
520 32 unneback 
always
521 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
522 
endgenerate
523 
 
524 
genvar i;
525 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
526 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
527 
end
528 
endgenerate
529 
 
530 33 unneback 
//assign #lock_delay lock = rst_n_i;
531 
assign lock = rst_n_i;
532 32 unneback 
 
533 
endmodule
534 6 unneback 
`else
535 
 
536 33 unneback 
`ifdef VL_PLL0
537 
`ifdef VL_PLL0_CLK1
538 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
539 
`endif
540 
`ifdef VL_PLL0_CLK2
541 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
542 
`endif
543 
`ifdef VL_PLL0_CLK3
544 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
545 
`endif
546 
`ifdef VL_PLL0_CLK4
547 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
548 
`endif
549 
`ifdef VL_PLL0_CLK5
550 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
551 
`endif
552 
`endif
553 32 unneback 
 
554 33 unneback 
`ifdef VL_PLL1
555 
`ifdef VL_PLL1_CLK1
556 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
557 
`endif
558 
`ifdef VL_PLL1_CLK2
559 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
560 
`endif
561 
`ifdef VL_PLL1_CLK3
562 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
563 
`endif
564 
`ifdef VL_PLL1_CLK4
565 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
566 
`endif
567 
`ifdef VL_PLL1_CLK5
568 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
569 
`endif
570 
`endif
571 32 unneback 
 
572 33 unneback 
`ifdef VL_PLL2
573 
`ifdef VL_PLL2_CLK1
574 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
575 
`endif
576 
`ifdef VL_PLL2_CLK2
577 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
578 
`endif
579 
`ifdef VL_PLL2_CLK3
580 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
581 
`endif
582 
`ifdef VL_PLL2_CLK4
583 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
584 
`endif
585 
`ifdef VL_PLL2_CLK5
586 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
587 
`endif
588 
`endif
589 32 unneback 
 
590 33 unneback 
`ifdef VL_PLL3
591 
`ifdef VL_PLL3_CLK1
592 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
593 
`endif
594 
`ifdef VL_PLL3_CLK2
595 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
596 
`endif
597 
`ifdef VL_PLL3_CLK3
598 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
599 
`endif
600 
`ifdef VL_PLL3_CLK4
601 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
602 
`endif
603 
`ifdef VL_PLL3_CLK5
604 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
605 
`endif
606 
`endif
607 32 unneback 
 
608 
genvar i;
609 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
610 40 unneback 
`define MODULE sync_rst
611 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
612 
`undef MODULE
613 32 unneback 
end
614 
endgenerate
615 
endmodule
616 
`endif
617 
///////////////////////////////////////////////////////////////////////////////
618 
 
619 
`else
620 
 
621 6 unneback 
// generic PLL
622 17 unneback 
`timescale 1 ps/1 ps
623 40 unneback 
`define MODULE pll
624 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
625 
`undef MODULE
626 6 unneback 
parameter index = 0;
627 
parameter number_of_clk = 1;
628 17 unneback 
parameter period_time_0 = 20000;
629 
parameter period_time_1 = 20000;
630 
parameter period_time_2 = 20000;
631 6 unneback 
parameter lock_delay = 2000;
632 
input clk_i, rst_n_i;
633 
output lock;
634 
output reg [0:number_of_clk-1] clk_o;
635 
output [0:number_of_clk-1] rst_o;
636 
 
637 
always
638 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
639 
 
640 
generate if (number_of_clk > 1)
641 
always
642 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
643 
endgenerate
644 
 
645 
generate if (number_of_clk > 2)
646 
always
647 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
648 
endgenerate
649 
 
650 
genvar i;
651 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
652 40 unneback 
`define MODULE sync_rst
653 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
654 
`undef MODULE
655 6 unneback 
end
656 
endgenerate
657 
 
658 
assign #lock_delay lock = rst_n_i;
659 
 
660 
endmodule
661 
 
662 
`endif //altera
663 17 unneback 
`endif //actel
664 40 unneback 
`undef MODULE
665 
`endif//////////////////////////////////////////////////////////////////////
666 6 unneback 
////                                                              ////
667 
////  Versatile library, registers                                ////
668 
////                                                              ////
669 
////  Description                                                 ////
670 
////  Different type of registers                                 ////
671 
////                                                              ////
672 
////                                                              ////
673 
////  To Do:                                                      ////
674 
////   - add more different registers                             ////
675 
////                                                              ////
676 
////  Author(s):                                                  ////
677 
////      - Michael Unneback, unneback@opencores.org              ////
678 
////        ORSoC AB                                              ////
679 
////                                                              ////
680 
//////////////////////////////////////////////////////////////////////
681 
////                                                              ////
682 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
683 
////                                                              ////
684 
//// This source file may be used and distributed without         ////
685 
//// restriction provided that this copyright statement is not    ////
686 
//// removed from the file and that any derivative work contains  ////
687 
//// the original copyright notice and the associated disclaimer. ////
688 
////                                                              ////
689 
//// This source file is free software; you can redistribute it   ////
690 
//// and/or modify it under the terms of the GNU Lesser General   ////
691 
//// Public License as published by the Free Software Foundation; ////
692 
//// either version 2.1 of the License, or (at your option) any   ////
693 
//// later version.                                               ////
694 
////                                                              ////
695 
//// This source is distributed in the hope that it will be       ////
696 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
697 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
698 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
699 
//// details.                                                     ////
700 
////                                                              ////
701 
//// You should have received a copy of the GNU Lesser General    ////
702 
//// Public License along with this source; if not, download it   ////
703 
//// from http://www.opencores.org/lgpl.shtml                     ////
704 
////                                                              ////
705 
//////////////////////////////////////////////////////////////////////
706 
 
707 40 unneback 
`ifdef DFF
708 
`define MODULE dff
709 
module `BASE`MODULE ( d, q, clk, rst);
710 
`undef MODULE
711 6 unneback 
        parameter width = 1;
712 
        parameter reset_value = 0;
713 
 
714 
        input [width-1:0] d;
715 
        input clk, rst;
716 
        output reg [width-1:0] q;
717 
 
718 
        always @ (posedge clk or posedge rst)
719 
        if (rst)
720 
                q <= reset_value;
721 
        else
722 
                q <= d;
723 
 
724 
endmodule
725 40 unneback 
`endif
726 6 unneback 
 
727 40 unneback 
`ifdef DFF_ARRAY
728 
`define MODULE dff_array
729 
module `BASE`MODULE ( d, q, clk, rst);
730 
`undef MODULE
731 6 unneback 
 
732 
        parameter width = 1;
733 
        parameter depth = 2;
734 
        parameter reset_value = 1'b0;
735 
 
736 
        input [width-1:0] d;
737 
        input clk, rst;
738 
        output [width-1:0] q;
739 
        reg  [0:depth-1] q_tmp [width-1:0];
740 
        integer i;
741 
        always @ (posedge clk or posedge rst)
742 
        if (rst) begin
743 
            for (i=0;i<depth;i=i+1)
744 
                q_tmp[i] <= {width{reset_value}};
745 
        end else begin
746 
            q_tmp[0] <= d;
747 
            for (i=1;i<depth;i=i+1)
748 
                q_tmp[i] <= q_tmp[i-1];
749 
        end
750 
 
751 
    assign q = q_tmp[depth-1];
752 
 
753 
endmodule
754 40 unneback 
`endif
755 6 unneback 
 
756 40 unneback 
`ifdef DFF_CE
757 
`define MODULE dff_ce
758 
module `BASE`MODULE ( d, ce, q, clk, rst);
759 
`undef MODULE
760 6 unneback 
 
761 
        parameter width = 1;
762 
        parameter reset_value = 0;
763 
 
764 
        input [width-1:0] d;
765 
        input ce, clk, rst;
766 
        output reg [width-1:0] q;
767 
 
768 
        always @ (posedge clk or posedge rst)
769 
        if (rst)
770 
                q <= reset_value;
771 
        else
772 
                if (ce)
773 
                        q <= d;
774 
 
775 
endmodule
776 40 unneback 
`endif
777 6 unneback 
 
778 40 unneback 
`ifdef DFF_CE_CLEAR
779 
`define MODULE dff_ce_clear
780 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
781 
`undef MODULE
782 8 unneback 
 
783 
        parameter width = 1;
784 
        parameter reset_value = 0;
785 
 
786 
        input [width-1:0] d;
787 10 unneback 
        input ce, clear, clk, rst;
788 8 unneback 
        output reg [width-1:0] q;
789 
 
790 
        always @ (posedge clk or posedge rst)
791 
        if (rst)
792 
            q <= reset_value;
793 
        else
794 
            if (ce)
795 
                if (clear)
796 
                    q <= {width{1'b0}};
797 
                else
798 
                    q <= d;
799 
 
800 
endmodule
801 40 unneback 
`endif
802 8 unneback 
 
803 40 unneback 
`ifdef DF_CE_SET
804 
`define MODULE dff_ce_set
805 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
806 
`undef MODULE
807 24 unneback 
 
808 
        parameter width = 1;
809 
        parameter reset_value = 0;
810 
 
811 
        input [width-1:0] d;
812 
        input ce, set, clk, rst;
813 
        output reg [width-1:0] q;
814 
 
815 
        always @ (posedge clk or posedge rst)
816 
        if (rst)
817 
            q <= reset_value;
818 
        else
819 
            if (ce)
820 
                if (set)
821 
                    q <= {width{1'b1}};
822 
                else
823 
                    q <= d;
824 
 
825 
endmodule
826 40 unneback 
`endif
827 24 unneback 
 
828 40 unneback 
`ifdef SPR
829 
`define MODULE spr
830 
module `BASE`MODULE ( sp, r, q, clk, rst);
831 
`undef MODULE
832 
 
833 64 unneback 
        //parameter width = 1;
834 
        parameter reset_value = 1'b0;
835 29 unneback 
 
836 
        input sp, r;
837 
        output reg q;
838 
        input clk, rst;
839 
 
840 
        always @ (posedge clk or posedge rst)
841 
        if (rst)
842 
            q <= reset_value;
843 
        else
844 
            if (sp)
845 
                q <= 1'b1;
846 
            else if (r)
847 
                q <= 1'b0;
848 
 
849 
endmodule
850 40 unneback 
`endif
851 29 unneback 
 
852 40 unneback 
`ifdef SRP
853 
`define MODULE srp
854 
module `BASE`MODULE ( s, rp, q, clk, rst);
855 
`undef MODULE
856 
 
857 29 unneback 
        parameter width = 1;
858 
        parameter reset_value = 0;
859 
 
860 
        input s, rp;
861 
        output reg q;
862 
        input clk, rst;
863 
 
864 
        always @ (posedge clk or posedge rst)
865 
        if (rst)
866 
            q <= reset_value;
867 
        else
868 
            if (rp)
869 
                q <= 1'b0;
870 
            else if (s)
871 
                q <= 1'b1;
872 
 
873 
endmodule
874 40 unneback 
`endif
875 29 unneback 
 
876 40 unneback 
`ifdef ALTERA
877 29 unneback 
 
878 40 unneback 
`ifdef DFF_SR
879 6 unneback 
// megafunction wizard: %LPM_FF%
880 
// GENERATION: STANDARD
881 
// VERSION: WM1.0
882 
// MODULE: lpm_ff
883 
 
884 
// ============================================================
885 
// File Name: dff_sr.v
886 
// Megafunction Name(s):
887 
//                      lpm_ff
888 
//
889 
// Simulation Library Files(s):
890 
//                      lpm
891 
// ============================================================
892 
// ************************************************************
893 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
894 
//
895 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
896 
// ************************************************************
897 
 
898 
 
899 
//Copyright (C) 1991-2010 Altera Corporation
900 
//Your use of Altera Corporation's design tools, logic functions
901 
//and other software and tools, and its AMPP partner logic
902 
//functions, and any output files from any of the foregoing
903 
//(including device programming or simulation files), and any
904 
//associated documentation or information are expressly subject
905 
//to the terms and conditions of the Altera Program License
906 
//Subscription Agreement, Altera MegaCore Function License
907 
//Agreement, or other applicable license agreement, including,
908 
//without limitation, that your use is for the sole purpose of
909 
//programming logic devices manufactured by Altera and sold by
910 
//Altera or its authorized distributors.  Please refer to the
911 
//applicable agreement for further details.
912 
 
913 
 
914 
// synopsys translate_off
915 
`timescale 1 ps / 1 ps
916 
// synopsys translate_on
917 40 unneback 
`define MODULE dff_sr
918 
module `BASE`MODULE (
919 
`undef MODULE
920 
 
921 6 unneback 
        aclr,
922 
        aset,
923 
        clock,
924 
        data,
925 
        q);
926 
 
927 
        input     aclr;
928 
        input     aset;
929 
        input     clock;
930 
        input     data;
931 
        output    q;
932 
 
933 
        wire [0:0] sub_wire0;
934 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
935 
        wire  q = sub_wire1;
936 
        wire  sub_wire2 = data;
937 
        wire  sub_wire3 = sub_wire2;
938 
 
939 
        lpm_ff  lpm_ff_component (
940 
                                .aclr (aclr),
941 
                                .clock (clock),
942 
                                .data (sub_wire3),
943 
                                .aset (aset),
944 
                                .q (sub_wire0)
945 
                                // synopsys translate_off
946 
                                ,
947 
                                .aload (),
948 
                                .enable (),
949 
                                .sclr (),
950 
                                .sload (),
951 
                                .sset ()
952 
                                // synopsys translate_on
953 
                                );
954 
        defparam
955 
                lpm_ff_component.lpm_fftype = "DFF",
956 
                lpm_ff_component.lpm_type = "LPM_FF",
957 
                lpm_ff_component.lpm_width = 1;
958 
 
959 
 
960 
endmodule
961 
 
962 
// ============================================================
963 
// CNX file retrieval info
964 
// ============================================================
965 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
966 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
967 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
968 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
969 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
970 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
971 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
972 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
973 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
974 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
975 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
976 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
977 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
978 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
979 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
980 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
981 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
982 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
983 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
984 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
985 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
986 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
987 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
988 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
989 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
990 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
991 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
992 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
993 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
994 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
995 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
996 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
997 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
998 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
999 
// Retrieval info: LIB_FILE: lpm
1000 40 unneback 
`endif
1001 6 unneback 
 
1002 
`else
1003 
 
1004 40 unneback 
`ifdef DFF_SR
1005 
`define MODULE dff_sr
1006 
module `BASE`MODULE ( aclr, aset, clock, data, q);
1007 
`undef MODULE
1008 6 unneback 
 
1009 
    input         aclr;
1010 
    input         aset;
1011 
    input         clock;
1012 
    input         data;
1013 
    output reg    q;
1014 
 
1015 
   always @ (posedge clock or posedge aclr or posedge aset)
1016 
     if (aclr)
1017 
       q <= 1'b0;
1018 
     else if (aset)
1019 
       q <= 1'b1;
1020 
     else
1021 
       q <= data;
1022 
 
1023 
endmodule
1024 40 unneback 
`endif
1025 6 unneback 
 
1026 
`endif
1027 
 
1028 
// LATCH
1029 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1030 
`ifdef ALTERA
1031 40 unneback 
 
1032 
`ifdef LATCH
1033 
`define MODULE latch
1034 
module `BASE`MODULE ( d, le, q, clk);
1035 
`undef MODULE
1036 6 unneback 
input d, le;
1037 
output q;
1038 
input clk;
1039 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1040 
endmodule
1041 40 unneback 
`endif
1042 
 
1043 6 unneback 
`else
1044 40 unneback 
 
1045 
`ifdef LATCH
1046 
`define MODULE latch
1047 
module `BASE`MODULE ( d, le, q, clk);
1048 
`undef MODULE
1049 6 unneback 
input d, le;
1050 48 unneback 
input clk;
1051 
always @ (le or d)
1052 60 unneback 
if (le)
1053 48 unneback 
    d <= q;
1054 6 unneback 
endmodule
1055 15 unneback 
`endif
1056 
 
1057 40 unneback 
`endif
1058 
 
1059 
`ifdef SHREG
1060 
`define MODULE shreg
1061 
module `BASE`MODULE ( d, q, clk, rst);
1062 
`undef MODULE
1063 
 
1064 17 unneback 
parameter depth = 10;
1065 
input d;
1066 
output q;
1067 
input clk, rst;
1068 
 
1069 
reg [1:depth] dffs;
1070 
 
1071 
always @ (posedge clk or posedge rst)
1072 
if (rst)
1073 
    dffs <= {depth{1'b0}};
1074 
else
1075 
    dffs <= {d,dffs[1:depth-1]};
1076 
assign q = dffs[depth];
1077 
endmodule
1078 40 unneback 
`endif
1079 17 unneback 
 
1080 40 unneback 
`ifdef SHREG_CE
1081 
`define MODULE shreg_ce
1082 
module `BASE`MODULE ( d, ce, q, clk, rst);
1083 
`undef MODULE
1084 17 unneback 
parameter depth = 10;
1085 
input d, ce;
1086 
output q;
1087 
input clk, rst;
1088 
 
1089 
reg [1:depth] dffs;
1090 
 
1091 
always @ (posedge clk or posedge rst)
1092 
if (rst)
1093 
    dffs <= {depth{1'b0}};
1094 
else
1095 
    if (ce)
1096 
        dffs <= {d,dffs[1:depth-1]};
1097 
assign q = dffs[depth];
1098 
endmodule
1099 40 unneback 
`endif
1100 17 unneback 
 
1101 40 unneback 
`ifdef DELAY
1102 
`define MODULE delay
1103 
module `BASE`MODULE ( d, q, clk, rst);
1104 
`undef MODULE
1105 15 unneback 
parameter depth = 10;
1106 
input d;
1107 
output q;
1108 
input clk, rst;
1109 
 
1110 
reg [1:depth] dffs;
1111 
 
1112 
always @ (posedge clk or posedge rst)
1113 
if (rst)
1114 
    dffs <= {depth{1'b0}};
1115 
else
1116 
    dffs <= {d,dffs[1:depth-1]};
1117 
assign q = dffs[depth];
1118 17 unneback 
endmodule
1119 40 unneback 
`endif
1120 17 unneback 
 
1121 40 unneback 
`ifdef DELAY_EMPTYFLAG
1122 
`define MODULE delay_emptyflag
1123 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1124 40 unneback 
`undef MODULE
1125 17 unneback 
parameter depth = 10;
1126 
input d;
1127 
output q, emptyflag;
1128 
input clk, rst;
1129 
 
1130 
reg [1:depth] dffs;
1131 
 
1132 
always @ (posedge clk or posedge rst)
1133 
if (rst)
1134 
    dffs <= {depth{1'b0}};
1135 
else
1136 
    dffs <= {d,dffs[1:depth-1]};
1137 
assign q = dffs[depth];
1138 
assign emptyflag = !(|dffs);
1139 
endmodule
1140 40 unneback 
`endif
1141 17 unneback 
//////////////////////////////////////////////////////////////////////
1142 6 unneback 
////                                                              ////
1143 18 unneback 
////  Logic functions                                             ////
1144 
////                                                              ////
1145 
////  Description                                                 ////
1146 
////  Logic functions such as multiplexers                        ////
1147 
////                                                              ////
1148 
////                                                              ////
1149 
////  To Do:                                                      ////
1150 
////   -                                                          ////
1151 
////                                                              ////
1152 
////  Author(s):                                                  ////
1153 
////      - Michael Unneback, unneback@opencores.org              ////
1154 
////        ORSoC AB                                              ////
1155 
////                                                              ////
1156 
//////////////////////////////////////////////////////////////////////
1157 
////                                                              ////
1158 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1159 
////                                                              ////
1160 
//// This source file may be used and distributed without         ////
1161 
//// restriction provided that this copyright statement is not    ////
1162 
//// removed from the file and that any derivative work contains  ////
1163 
//// the original copyright notice and the associated disclaimer. ////
1164 
////                                                              ////
1165 
//// This source file is free software; you can redistribute it   ////
1166 
//// and/or modify it under the terms of the GNU Lesser General   ////
1167 
//// Public License as published by the Free Software Foundation; ////
1168 
//// either version 2.1 of the License, or (at your option) any   ////
1169 
//// later version.                                               ////
1170 
////                                                              ////
1171 
//// This source is distributed in the hope that it will be       ////
1172 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1173 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1174 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1175 
//// details.                                                     ////
1176 
////                                                              ////
1177 
//// You should have received a copy of the GNU Lesser General    ////
1178 
//// Public License along with this source; if not, download it   ////
1179 
//// from http://www.opencores.org/lgpl.shtml                     ////
1180 
////                                                              ////
1181 
//////////////////////////////////////////////////////////////////////
1182 40 unneback 
`ifdef MUX_ANDOR
1183 
`define MODULE mux_andor
1184 
module `BASE`MODULE ( a, sel, dout);
1185 
`undef MODULE
1186 36 unneback 
 
1187 
parameter width = 32;
1188 
parameter nr_of_ports = 4;
1189 
 
1190 
input [nr_of_ports*width-1:0] a;
1191 
input [nr_of_ports-1:0] sel;
1192 
output reg [width-1:0] dout;
1193 
 
1194 38 unneback 
integer i,j;
1195 
 
1196 36 unneback 
always @ (a, sel)
1197 
begin
1198 
    dout = a[width-1:0] & {width{sel[0]}};
1199 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1200 
        for (j=0;j<width;j=j+1)
1201 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1202 36 unneback 
end
1203 
 
1204 
endmodule
1205 40 unneback 
`endif
1206 36 unneback 
 
1207 40 unneback 
`ifdef MUX2_ANDOR
1208 
`define MODULE mux2_andor
1209 
module `BASE`MODULE ( a1, a0, sel, dout);
1210 
`undef MODULE
1211 18 unneback 
 
1212 34 unneback 
parameter width = 32;
1213 35 unneback 
localparam nr_of_ports = 2;
1214 34 unneback 
input [width-1:0] a1, a0;
1215 
input [nr_of_ports-1:0] sel;
1216 
output [width-1:0] dout;
1217 
 
1218 40 unneback 
`define MODULE mux_andor
1219 
`BASE`MODULE
1220 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1221 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1222 40 unneback 
`undef MODULE
1223 
 
1224 34 unneback 
endmodule
1225 40 unneback 
`endif
1226 34 unneback 
 
1227 40 unneback 
`ifdef MUX3_ANDOR
1228 
`define MODULE mux3_andor
1229 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1230 
`undef MODULE
1231 34 unneback 
 
1232 
parameter width = 32;
1233 35 unneback 
localparam nr_of_ports = 3;
1234 34 unneback 
input [width-1:0] a2, a1, a0;
1235 
input [nr_of_ports-1:0] sel;
1236 
output [width-1:0] dout;
1237 
 
1238 40 unneback 
`define MODULE mux_andor
1239 
`BASE`MODULE
1240 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1241 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1242 40 unneback 
`undef MODULE
1243 34 unneback 
endmodule
1244 40 unneback 
`endif
1245 34 unneback 
 
1246 40 unneback 
`ifdef MUX4_ANDOR
1247 
`define MODULE mux4_andor
1248 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1249 
`undef MODULE
1250 18 unneback 
 
1251 
parameter width = 32;
1252 35 unneback 
localparam nr_of_ports = 4;
1253 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1254 
input [nr_of_ports-1:0] sel;
1255 22 unneback 
output [width-1:0] dout;
1256 18 unneback 
 
1257 40 unneback 
`define MODULE mux_andor
1258 
`BASE`MODULE
1259 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1260 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1261 40 unneback 
`undef MODULE
1262 18 unneback 
 
1263 
endmodule
1264 40 unneback 
`endif
1265 18 unneback 
 
1266 40 unneback 
`ifdef MUX5_ANDOR
1267 
`define MODULE mux5_andor
1268 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1269 
`undef MODULE
1270 18 unneback 
 
1271 
parameter width = 32;
1272 35 unneback 
localparam nr_of_ports = 5;
1273 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1274 
input [nr_of_ports-1:0] sel;
1275 22 unneback 
output [width-1:0] dout;
1276 18 unneback 
 
1277 40 unneback 
`define MODULE mux_andor
1278 
`BASE`MODULE
1279 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1280 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1281 40 unneback 
`undef MODULE
1282 18 unneback 
 
1283 
endmodule
1284 40 unneback 
`endif
1285 18 unneback 
 
1286 40 unneback 
`ifdef MUX6_ANDOR
1287 
`define MODULE mux6_andor
1288 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1289 
`undef MODULE
1290 18 unneback 
 
1291 
parameter width = 32;
1292 35 unneback 
localparam nr_of_ports = 6;
1293 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1294 
input [nr_of_ports-1:0] sel;
1295 22 unneback 
output [width-1:0] dout;
1296 18 unneback 
 
1297 40 unneback 
`define MODULE mux_andor
1298 
`BASE`MODULE
1299 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1300 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1301 40 unneback 
`undef MODULE
1302 18 unneback 
 
1303 
endmodule
1304 40 unneback 
`endif
1305 43 unneback 
 
1306 
`ifdef PARITY
1307 
 
1308 
`define MODULE parity_generate
1309 
module `BASE`MODULE (data, parity);
1310 
`undef MODULE
1311 
parameter word_size = 32;
1312 
parameter chunk_size = 8;
1313 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1314 
input [word_size-1:0] data;
1315 
output reg [word_size/chunk_size-1:0] parity;
1316 
integer i,j;
1317 
always @ (data)
1318 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1319 
    parity[i] = parity_type;
1320 
    for (j=0;j<chunk_size;j=j+1) begin
1321 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1322 43 unneback 
    end
1323 
end
1324 
endmodule
1325 
 
1326 
`define MODULE parity_check
1327 
module `BASE`MODULE( data, parity, parity_error);
1328 
`undef MODULE
1329 
parameter word_size = 32;
1330 
parameter chunk_size = 8;
1331 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1332 
input [word_size-1:0] data;
1333 
input [word_size/chunk_size-1:0] parity;
1334 
output parity_error;
1335 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1336 43 unneback 
integer i,j;
1337 
always @ (data or parity)
1338 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1339 
    error_flag[i] = parity[i] ^ parity_type;
1340 
    for (j=0;j<chunk_size;j=j+1) begin
1341 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1342 43 unneback 
    end
1343 
end
1344 
assign parity_error = |error_flag;
1345 
endmodule
1346 
 
1347 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1348 
////                                                              ////
1349 
////  IO functions                                                ////
1350 
////                                                              ////
1351 
////  Description                                                 ////
1352 
////  IO functions such as IOB flip-flops                         ////
1353 
////                                                              ////
1354 
////                                                              ////
1355 
////  To Do:                                                      ////
1356 
////   -                                                          ////
1357 
////                                                              ////
1358 
////  Author(s):                                                  ////
1359 
////      - Michael Unneback, unneback@opencores.org              ////
1360 
////        ORSoC AB                                              ////
1361 
////                                                              ////
1362 18 unneback 
//////////////////////////////////////////////////////////////////////
1363 
////                                                              ////
1364 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1365 
////                                                              ////
1366 
//// This source file may be used and distributed without         ////
1367 
//// restriction provided that this copyright statement is not    ////
1368 
//// removed from the file and that any derivative work contains  ////
1369 
//// the original copyright notice and the associated disclaimer. ////
1370 
////                                                              ////
1371 
//// This source file is free software; you can redistribute it   ////
1372 
//// and/or modify it under the terms of the GNU Lesser General   ////
1373 
//// Public License as published by the Free Software Foundation; ////
1374 
//// either version 2.1 of the License, or (at your option) any   ////
1375 
//// later version.                                               ////
1376 
////                                                              ////
1377 
//// This source is distributed in the hope that it will be       ////
1378 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1379