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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 75

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 40 unneback
`ifdef ALL
14
 
15
`define GBUF
16
`define SYNC_RST
17
`define PLL
18
 
19
`define MULTS
20
`define MULTS18X18
21
`define MULT
22
`define SHIFT_UNIT_32
23
`define LOGIC_UNIT
24
 
25
`define CNT_SHREG_WRAP
26
`define CNT_SHREG_CE_WRAP
27
`define CNT_SHREG_CE_CLEAR
28
`define CNT_SHREG_CE_CLEAR_WRAP
29
 
30
`define MUX_ANDOR
31
`define MUX2_ANDOR
32
`define MUX3_ANDOR
33
`define MUX4_ANDOR
34
`define MUX5_ANDOR
35
`define MUX6_ANDOR
36 43 unneback
`define PARITY
37 40 unneback
 
38
`define ROM_INIT
39
`define RAM
40
`define RAM_BE
41
`define DPRAM_1R1W
42
`define DPRAM_2R1W
43
`define DPRAM_2R2W
44 75 unneback
`define DPRAM_BE_2R2W
45 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
46
`define FIFO_2R2W_SYNC_SIMPLEX
47
`define FIFO_CMP_ASYNC
48
`define FIFO_1R1W_ASYNC
49
`define FIFO_2R2W_ASYNC
50
`define FIFO_2R2W_ASYNC_SIMPLEX
51 48 unneback
`define REG_FILE
52 40 unneback
 
53
`define DFF
54
`define DFF_ARRAY
55
`define DFF_CE
56
`define DFF_CE_CLEAR
57
`define DF_CE_SET
58
`define SPR
59
`define SRP
60
`define DFF_SR
61
`define LATCH
62
`define SHREG
63
`define SHREG_CE
64
`define DELAY
65
`define DELAY_EMPTYFLAG
66
 
67 75 unneback
`define WB3AVALON_BRIDGE
68 40 unneback
`define WB3WB3_BRIDGE
69
`define WB3_ARBITER_TYPE1
70 59 unneback
`define WB_B3_RAM_BE
71 49 unneback
`define WB_B4_RAM_BE
72 48 unneback
`define WB_B4_ROM
73 40 unneback
`define WB_BOOT_ROM
74
`define WB_DPRAM
75
 
76 44 unneback
`define IO_DFF_OE
77
`define O_DFF
78
 
79 40 unneback
`endif
80
 
81
`ifdef PLL
82
`ifndef SYNC_RST
83
`define SYNC_RST
84
`endif
85
`endif
86
 
87
`ifdef SYNC_RST
88
`ifndef GBUF
89
`define GBUF
90
`endif
91
`endif
92
 
93
`ifdef WB_DPRAM
94
`ifndef DPRAM_2R2W
95
`define DPRAM_2R2W
96
`endif
97
`ifndef SPR
98
`define SPR
99
`endif
100
`endif
101
 
102 62 unneback
`ifdef WB_B3_RAM_BE
103
`ifndef WB3_ARBITER_TYPE1
104
`define WB3_ARBITER_TYPE1
105
`endif
106
`ifndef RAM_BE
107
`define RAM_BE
108
`endif
109
`endif
110
 
111 40 unneback
`ifdef WB3_ARBITER_TYPE1
112 42 unneback
`ifndef SPR
113
`define SPR
114
`endif
115 40 unneback
`ifndef MUX_ANDOR
116
`define MUX_ANDOR
117
`endif
118
`endif
119
 
120
`ifdef WB3WB3_BRIDGE
121
`ifndef CNT_SHREG_CE_CLEAR
122
`define CNT_SHREG_CE_CLEAR
123
`endif
124
`ifndef DFF
125
`define DFF
126
`endif
127
`ifndef DFF_CE
128
`define DFF_CE
129
`endif
130
`ifndef CNT_SHREG_CE_CLEAR
131
`define CNT_SHREG_CE_CLEAR
132
`endif
133
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
134
`define FIFO_2R2W_ASYNC_SIMPLEX
135
`endif
136
`endif
137
 
138
`ifdef MULTS18X18
139
`ifndef MULTS
140
`define MULTS
141
`endif
142
`endif
143
 
144
`ifdef SHIFT_UNIT_32
145
`ifndef MULTS
146
`define MULTS
147
`endif
148
`endif
149
 
150
`ifdef MUX2_ANDOR
151
`ifndef MUX_ANDOR
152
`define MUX_ANDOR
153
`endif
154
`endif
155
 
156
`ifdef MUX3_ANDOR
157
`ifndef MUX_ANDOR
158
`define MUX_ANDOR
159
`endif
160
`endif
161
 
162
`ifdef MUX4_ANDOR
163
`ifndef MUX_ANDOR
164
`define MUX_ANDOR
165
`endif
166
`endif
167
 
168
`ifdef MUX5_ANDOR
169
`ifndef MUX_ANDOR
170
`define MUX_ANDOR
171
`endif
172
`endif
173
 
174
`ifdef MUX6_ANDOR
175
`ifndef MUX_ANDOR
176
`define MUX_ANDOR
177
`endif
178
`endif
179
 
180
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
181
`ifndef CNT_BIN_CE
182
`define CNT_BIN_CE
183
`endif
184
`ifndef DPRAM_1R1W
185
`define DPRAM_1R1W
186
`endif
187
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
188
`define CNT_BIN_CE_REW_Q_ZQ_L1
189
`endif
190
`endif
191
 
192
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
193
`ifndef CNT_LFSR_CE
194
`define CNT_LFSR_CE
195
`endif
196
`ifndef DPRAM_2R2W
197
`define DPRAM_2R2W
198
`endif
199
`ifndef CNT_BIN_CE_REW_ZQ_L1
200
`define CNT_BIN_CE_REW_ZQ_L1
201
`endif
202
`endif
203
 
204
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
205
`ifndef CNT_GRAY_CE_BIN
206
`define CNT_GRAY_CE_BIN
207
`endif
208
`ifndef DPRAM_2R2W
209
`define DPRAM_2R2W
210
`endif
211
`ifndef FIFO_CMP_ASYNC
212
`define FIFO_CMP_ASYNC
213
`endif
214
`endif
215
 
216
`ifdef FIFO_2R2W_ASYNC
217
`ifndef FIFO_1R1W_ASYNC
218
`define FIFO_1R1W_ASYNC
219
`endif
220
`endif
221
 
222
`ifdef FIFO_1R1W_ASYNC
223
`ifndef CNT_GRAY_CE_BIN
224
`define CNT_GRAY_CE_BIN
225
`endif
226
`ifndef DPRAM_1R1W
227
`define DPRAM_1R1W
228
`endif
229
`ifndef FIFO_CMP_ASYNC
230
`define FIFO_CMP_ASYNC
231
`endif
232
`endif
233
 
234
`ifdef FIFO_CMP_ASYNC
235
`ifndef DFF_SR
236
`define DFF_SR
237
`endif
238
`ifndef DFF
239
`define DFF
240
`endif
241
`endif
242 48 unneback
 
243
`ifdef REG_FILE
244
`ifndef DPRAM_1R1W
245
`define DPRAM_1R1W
246
`endif
247
`endif
248 62 unneback
//////////////////////////////////////////////////////////////////////
249 6 unneback
////                                                              ////
250
////  Versatile library, clock and reset                          ////
251
////                                                              ////
252
////  Description                                                 ////
253
////  Logic related to clock and reset                            ////
254
////                                                              ////
255
////                                                              ////
256
////  To Do:                                                      ////
257
////   - add more different registers                             ////
258
////                                                              ////
259
////  Author(s):                                                  ////
260
////      - Michael Unneback, unneback@opencores.org              ////
261
////        ORSoC AB                                              ////
262
////                                                              ////
263
//////////////////////////////////////////////////////////////////////
264
////                                                              ////
265
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
266
////                                                              ////
267
//// This source file may be used and distributed without         ////
268
//// restriction provided that this copyright statement is not    ////
269
//// removed from the file and that any derivative work contains  ////
270
//// the original copyright notice and the associated disclaimer. ////
271
////                                                              ////
272
//// This source file is free software; you can redistribute it   ////
273
//// and/or modify it under the terms of the GNU Lesser General   ////
274
//// Public License as published by the Free Software Foundation; ////
275
//// either version 2.1 of the License, or (at your option) any   ////
276
//// later version.                                               ////
277
////                                                              ////
278
//// This source is distributed in the hope that it will be       ////
279
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
280
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
281
//// PURPOSE.  See the GNU Lesser General Public License for more ////
282
//// details.                                                     ////
283
////                                                              ////
284
//// You should have received a copy of the GNU Lesser General    ////
285
//// Public License along with this source; if not, download it   ////
286
//// from http://www.opencores.org/lgpl.shtml                     ////
287
////                                                              ////
288
//////////////////////////////////////////////////////////////////////
289
 
290 48 unneback
`ifdef ACTEL
291
`ifdef GBUF
292
`timescale 1 ns/100 ps
293 6 unneback
// Global buffer
294
// usage:
295
// use to enable global buffers for high fan out signals such as clock and reset
296
// Version: 8.4 8.4.0.33
297
module gbuf(GL,CLK);
298
output GL;
299
input  CLK;
300
 
301
    wire GND;
302
 
303
    GND GND_1_net(.Y(GND));
304
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
305
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
306
 
307
endmodule
308
`timescale 1 ns/1 ns
309 40 unneback
`define MODULE gbuf
310
module `BASE`MODULE ( i, o);
311
`undef MODULE
312 6 unneback
input i;
313
output o;
314
`ifdef SIM_GBUF
315
assign o=i;
316
`else
317
gbuf gbuf_i0 ( .CLK(i), .GL(o));
318
`endif
319
endmodule
320 40 unneback
`endif
321 33 unneback
 
322 6 unneback
`else
323 33 unneback
 
324 40 unneback
`ifdef ALTERA
325
`ifdef GBUF
326 21 unneback
//altera
327 40 unneback
`define MODULE gbuf
328
module `BASE`MODULE ( i, o);
329
`undef MODULE
330 33 unneback
input i;
331
output o;
332
assign o = i;
333
endmodule
334 40 unneback
`endif
335 33 unneback
 
336 6 unneback
`else
337
 
338 40 unneback
`ifdef GBUF
339 6 unneback
`timescale 1 ns/100 ps
340 40 unneback
`define MODULE
341
module `BASE`MODULE ( i, o);
342
`undef MODULE
343 6 unneback
input i;
344
output o;
345
assign o = i;
346
endmodule
347 40 unneback
`endif
348 6 unneback
`endif // ALTERA
349
`endif //ACTEL
350
 
351 40 unneback
`ifdef SYNC_RST
352 6 unneback
// sync reset
353 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
354 6 unneback
// output active high global reset sync with two DFFs 
355
`timescale 1 ns/100 ps
356 40 unneback
`define MODULE sync_rst
357
module `BASE`MODULE ( rst_n_i, rst_o, clk);
358
`undef MODULE
359 6 unneback
input rst_n_i, clk;
360
output rst_o;
361 18 unneback
reg [1:0] tmp;
362 6 unneback
always @ (posedge clk or negedge rst_n_i)
363
if (!rst_n_i)
364 17 unneback
        tmp <= 2'b11;
365 6 unneback
else
366 33 unneback
        tmp <= {1'b0,tmp[1]};
367 40 unneback
`define MODULE gbuf
368
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
369
`undef MODULE
370 6 unneback
endmodule
371 40 unneback
`endif
372 6 unneback
 
373 40 unneback
`ifdef PLL
374 6 unneback
// vl_pll
375
`ifdef ACTEL
376 32 unneback
///////////////////////////////////////////////////////////////////////////////
377 17 unneback
`timescale 1 ps/1 ps
378 40 unneback
`define MODULE pll
379
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
380
`undef MODULE
381 6 unneback
parameter index = 0;
382
parameter number_of_clk = 1;
383 17 unneback
parameter period_time_0 = 20000;
384
parameter period_time_1 = 20000;
385
parameter period_time_2 = 20000;
386
parameter lock_delay = 2000000;
387 6 unneback
input clk_i, rst_n_i;
388
output lock;
389
output reg [0:number_of_clk-1] clk_o;
390
output [0:number_of_clk-1] rst_o;
391
 
392
`ifdef SIM_PLL
393
 
394
always
395
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
396
 
397
generate if (number_of_clk > 1)
398
always
399
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
400
endgenerate
401
 
402
generate if (number_of_clk > 2)
403
always
404
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
405
endgenerate
406
 
407
genvar i;
408
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
409
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
410
end
411
endgenerate
412
 
413
assign #lock_delay lock = rst_n_i;
414
 
415
endmodule
416
`else
417
generate if (number_of_clk==1 & index==0) begin
418
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
419
end
420
endgenerate // index==0
421
generate if (number_of_clk==1 & index==1) begin
422
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
423
end
424
endgenerate // index==1
425
generate if (number_of_clk==1 & index==2) begin
426
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
427
end
428
endgenerate // index==2
429
generate if (number_of_clk==1 & index==3) begin
430
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
431
end
432
endgenerate // index==0
433
 
434
generate if (number_of_clk==2 & index==0) begin
435
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
436
end
437
endgenerate // index==0
438
generate if (number_of_clk==2 & index==1) begin
439
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
440
end
441
endgenerate // index==1
442
generate if (number_of_clk==2 & index==2) begin
443
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
444
end
445
endgenerate // index==2
446
generate if (number_of_clk==2 & index==3) begin
447
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
448
end
449
endgenerate // index==0
450
 
451
generate if (number_of_clk==3 & index==0) begin
452
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
453
end
454
endgenerate // index==0
455
generate if (number_of_clk==3 & index==1) begin
456
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
457
end
458
endgenerate // index==1
459
generate if (number_of_clk==3 & index==2) begin
460
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
461
end
462
endgenerate // index==2
463
generate if (number_of_clk==3 & index==3) begin
464
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
465
end
466
endgenerate // index==0
467
 
468
genvar i;
469
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
470 40 unneback
`define MODULE sync_rst
471
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
472
`undef MODULE
473 6 unneback
end
474
endgenerate
475
endmodule
476
`endif
477 32 unneback
///////////////////////////////////////////////////////////////////////////////
478 6 unneback
 
479
`else
480
 
481 32 unneback
///////////////////////////////////////////////////////////////////////////////
482 6 unneback
`ifdef ALTERA
483
 
484 32 unneback
`timescale 1 ps/1 ps
485 40 unneback
`define MODULE pll
486
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
487
`undef MODULE
488 32 unneback
parameter index = 0;
489
parameter number_of_clk = 1;
490
parameter period_time_0 = 20000;
491
parameter period_time_1 = 20000;
492
parameter period_time_2 = 20000;
493
parameter period_time_3 = 20000;
494
parameter period_time_4 = 20000;
495
parameter lock_delay = 2000000;
496
input clk_i, rst_n_i;
497
output lock;
498
output reg [0:number_of_clk-1] clk_o;
499
output [0:number_of_clk-1] rst_o;
500
 
501
`ifdef SIM_PLL
502
 
503
always
504
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
505
 
506
generate if (number_of_clk > 1)
507
always
508
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
509
endgenerate
510
 
511
generate if (number_of_clk > 2)
512
always
513
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
514
endgenerate
515
 
516 33 unneback
generate if (number_of_clk > 3)
517 32 unneback
always
518
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
519
endgenerate
520
 
521 33 unneback
generate if (number_of_clk > 4)
522 32 unneback
always
523
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
524
endgenerate
525
 
526
genvar i;
527
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
528
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
529
end
530
endgenerate
531
 
532 33 unneback
//assign #lock_delay lock = rst_n_i;
533
assign lock = rst_n_i;
534 32 unneback
 
535
endmodule
536 6 unneback
`else
537
 
538 33 unneback
`ifdef VL_PLL0
539
`ifdef VL_PLL0_CLK1
540
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
541
`endif
542
`ifdef VL_PLL0_CLK2
543
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
544
`endif
545
`ifdef VL_PLL0_CLK3
546
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
547
`endif
548
`ifdef VL_PLL0_CLK4
549
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
550
`endif
551
`ifdef VL_PLL0_CLK5
552
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
553
`endif
554
`endif
555 32 unneback
 
556 33 unneback
`ifdef VL_PLL1
557
`ifdef VL_PLL1_CLK1
558
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
559
`endif
560
`ifdef VL_PLL1_CLK2
561
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
562
`endif
563
`ifdef VL_PLL1_CLK3
564
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
565
`endif
566
`ifdef VL_PLL1_CLK4
567
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
568
`endif
569
`ifdef VL_PLL1_CLK5
570
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
571
`endif
572
`endif
573 32 unneback
 
574 33 unneback
`ifdef VL_PLL2
575
`ifdef VL_PLL2_CLK1
576
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
577
`endif
578
`ifdef VL_PLL2_CLK2
579
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
580
`endif
581
`ifdef VL_PLL2_CLK3
582
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
583
`endif
584
`ifdef VL_PLL2_CLK4
585
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
586
`endif
587
`ifdef VL_PLL2_CLK5
588
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
589
`endif
590
`endif
591 32 unneback
 
592 33 unneback
`ifdef VL_PLL3
593
`ifdef VL_PLL3_CLK1
594
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
595
`endif
596
`ifdef VL_PLL3_CLK2
597
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
598
`endif
599
`ifdef VL_PLL3_CLK3
600
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
601
`endif
602
`ifdef VL_PLL3_CLK4
603
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
604
`endif
605
`ifdef VL_PLL3_CLK5
606
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
607
`endif
608
`endif
609 32 unneback
 
610
genvar i;
611
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
612 40 unneback
`define MODULE sync_rst
613
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
614
`undef MODULE
615 32 unneback
end
616
endgenerate
617
endmodule
618
`endif
619
///////////////////////////////////////////////////////////////////////////////
620
 
621
`else
622
 
623 6 unneback
// generic PLL
624 17 unneback
`timescale 1 ps/1 ps
625 40 unneback
`define MODULE pll
626
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
627
`undef MODULE
628 6 unneback
parameter index = 0;
629
parameter number_of_clk = 1;
630 17 unneback
parameter period_time_0 = 20000;
631
parameter period_time_1 = 20000;
632
parameter period_time_2 = 20000;
633 6 unneback
parameter lock_delay = 2000;
634
input clk_i, rst_n_i;
635
output lock;
636
output reg [0:number_of_clk-1] clk_o;
637
output [0:number_of_clk-1] rst_o;
638
 
639
always
640
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
641
 
642
generate if (number_of_clk > 1)
643
always
644
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
645
endgenerate
646
 
647
generate if (number_of_clk > 2)
648
always
649
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
650
endgenerate
651
 
652
genvar i;
653
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
654 40 unneback
`define MODULE sync_rst
655
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
656
`undef MODULE
657 6 unneback
end
658
endgenerate
659
 
660
assign #lock_delay lock = rst_n_i;
661
 
662
endmodule
663
 
664
`endif //altera
665 17 unneback
`endif //actel
666 40 unneback
`undef MODULE
667
`endif//////////////////////////////////////////////////////////////////////
668 6 unneback
////                                                              ////
669
////  Versatile library, registers                                ////
670
////                                                              ////
671
////  Description                                                 ////
672
////  Different type of registers                                 ////
673
////                                                              ////
674
////                                                              ////
675
////  To Do:                                                      ////
676
////   - add more different registers                             ////
677
////                                                              ////
678
////  Author(s):                                                  ////
679
////      - Michael Unneback, unneback@opencores.org              ////
680
////        ORSoC AB                                              ////
681
////                                                              ////
682
//////////////////////////////////////////////////////////////////////
683
////                                                              ////
684
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
685
////                                                              ////
686
//// This source file may be used and distributed without         ////
687
//// restriction provided that this copyright statement is not    ////
688
//// removed from the file and that any derivative work contains  ////
689
//// the original copyright notice and the associated disclaimer. ////
690
////                                                              ////
691
//// This source file is free software; you can redistribute it   ////
692
//// and/or modify it under the terms of the GNU Lesser General   ////
693
//// Public License as published by the Free Software Foundation; ////
694
//// either version 2.1 of the License, or (at your option) any   ////
695
//// later version.                                               ////
696
////                                                              ////
697
//// This source is distributed in the hope that it will be       ////
698
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
699
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
700
//// PURPOSE.  See the GNU Lesser General Public License for more ////
701
//// details.                                                     ////
702
////                                                              ////
703
//// You should have received a copy of the GNU Lesser General    ////
704
//// Public License along with this source; if not, download it   ////
705
//// from http://www.opencores.org/lgpl.shtml                     ////
706
////                                                              ////
707
//////////////////////////////////////////////////////////////////////
708
 
709 40 unneback
`ifdef DFF
710
`define MODULE dff
711
module `BASE`MODULE ( d, q, clk, rst);
712
`undef MODULE
713 6 unneback
        parameter width = 1;
714
        parameter reset_value = 0;
715
 
716
        input [width-1:0] d;
717
        input clk, rst;
718
        output reg [width-1:0] q;
719
 
720
        always @ (posedge clk or posedge rst)
721
        if (rst)
722
                q <= reset_value;
723
        else
724
                q <= d;
725
 
726
endmodule
727 40 unneback
`endif
728 6 unneback
 
729 40 unneback
`ifdef DFF_ARRAY
730
`define MODULE dff_array
731
module `BASE`MODULE ( d, q, clk, rst);
732
`undef MODULE
733 6 unneback
 
734
        parameter width = 1;
735
        parameter depth = 2;
736
        parameter reset_value = 1'b0;
737
 
738
        input [width-1:0] d;
739
        input clk, rst;
740
        output [width-1:0] q;
741
        reg  [0:depth-1] q_tmp [width-1:0];
742
        integer i;
743
        always @ (posedge clk or posedge rst)
744
        if (rst) begin
745
            for (i=0;i<depth;i=i+1)
746
                q_tmp[i] <= {width{reset_value}};
747
        end else begin
748
            q_tmp[0] <= d;
749
            for (i=1;i<depth;i=i+1)
750
                q_tmp[i] <= q_tmp[i-1];
751
        end
752
 
753
    assign q = q_tmp[depth-1];
754
 
755
endmodule
756 40 unneback
`endif
757 6 unneback
 
758 40 unneback
`ifdef DFF_CE
759
`define MODULE dff_ce
760
module `BASE`MODULE ( d, ce, q, clk, rst);
761
`undef MODULE
762 6 unneback
 
763
        parameter width = 1;
764
        parameter reset_value = 0;
765
 
766
        input [width-1:0] d;
767
        input ce, clk, rst;
768
        output reg [width-1:0] q;
769
 
770
        always @ (posedge clk or posedge rst)
771
        if (rst)
772
                q <= reset_value;
773
        else
774
                if (ce)
775
                        q <= d;
776
 
777
endmodule
778 40 unneback
`endif
779 6 unneback
 
780 40 unneback
`ifdef DFF_CE_CLEAR
781
`define MODULE dff_ce_clear
782
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
783
`undef MODULE
784 8 unneback
 
785
        parameter width = 1;
786
        parameter reset_value = 0;
787
 
788
        input [width-1:0] d;
789 10 unneback
        input ce, clear, clk, rst;
790 8 unneback
        output reg [width-1:0] q;
791
 
792
        always @ (posedge clk or posedge rst)
793
        if (rst)
794
            q <= reset_value;
795
        else
796
            if (ce)
797
                if (clear)
798
                    q <= {width{1'b0}};
799
                else
800
                    q <= d;
801
 
802
endmodule
803 40 unneback
`endif
804 8 unneback
 
805 40 unneback
`ifdef DF_CE_SET
806
`define MODULE dff_ce_set
807
module `BASE`MODULE ( d, ce, set, q, clk, rst);
808
`undef MODULE
809 24 unneback
 
810
        parameter width = 1;
811
        parameter reset_value = 0;
812
 
813
        input [width-1:0] d;
814
        input ce, set, clk, rst;
815
        output reg [width-1:0] q;
816
 
817
        always @ (posedge clk or posedge rst)
818
        if (rst)
819
            q <= reset_value;
820
        else
821
            if (ce)
822
                if (set)
823
                    q <= {width{1'b1}};
824
                else
825
                    q <= d;
826
 
827
endmodule
828 40 unneback
`endif
829 24 unneback
 
830 40 unneback
`ifdef SPR
831
`define MODULE spr
832
module `BASE`MODULE ( sp, r, q, clk, rst);
833
`undef MODULE
834
 
835 64 unneback
        //parameter width = 1;
836
        parameter reset_value = 1'b0;
837 29 unneback
 
838
        input sp, r;
839
        output reg q;
840
        input clk, rst;
841
 
842
        always @ (posedge clk or posedge rst)
843
        if (rst)
844
            q <= reset_value;
845
        else
846
            if (sp)
847
                q <= 1'b1;
848
            else if (r)
849
                q <= 1'b0;
850
 
851
endmodule
852 40 unneback
`endif
853 29 unneback
 
854 40 unneback
`ifdef SRP
855
`define MODULE srp
856
module `BASE`MODULE ( s, rp, q, clk, rst);
857
`undef MODULE
858
 
859 29 unneback
        parameter width = 1;
860
        parameter reset_value = 0;
861
 
862
        input s, rp;
863
        output reg q;
864
        input clk, rst;
865
 
866
        always @ (posedge clk or posedge rst)
867
        if (rst)
868
            q <= reset_value;
869
        else
870
            if (rp)
871
                q <= 1'b0;
872
            else if (s)
873
                q <= 1'b1;
874
 
875
endmodule
876 40 unneback
`endif
877 29 unneback
 
878 40 unneback
`ifdef ALTERA
879 29 unneback
 
880 40 unneback
`ifdef DFF_SR
881 6 unneback
// megafunction wizard: %LPM_FF%
882
// GENERATION: STANDARD
883
// VERSION: WM1.0
884
// MODULE: lpm_ff 
885
 
886
// ============================================================
887
// File Name: dff_sr.v
888
// Megafunction Name(s):
889
//                      lpm_ff
890
//
891
// Simulation Library Files(s):
892
//                      lpm
893
// ============================================================
894
// ************************************************************
895
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
896
//
897
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
898
// ************************************************************
899
 
900
 
901
//Copyright (C) 1991-2010 Altera Corporation
902
//Your use of Altera Corporation's design tools, logic functions 
903
//and other software and tools, and its AMPP partner logic 
904
//functions, and any output files from any of the foregoing 
905
//(including device programming or simulation files), and any 
906
//associated documentation or information are expressly subject 
907
//to the terms and conditions of the Altera Program License 
908
//Subscription Agreement, Altera MegaCore Function License 
909
//Agreement, or other applicable license agreement, including, 
910
//without limitation, that your use is for the sole purpose of 
911
//programming logic devices manufactured by Altera and sold by 
912
//Altera or its authorized distributors.  Please refer to the 
913
//applicable agreement for further details.
914
 
915
 
916
// synopsys translate_off
917
`timescale 1 ps / 1 ps
918
// synopsys translate_on
919 40 unneback
`define MODULE dff_sr
920
module `BASE`MODULE (
921
`undef MODULE
922
 
923 6 unneback
        aclr,
924
        aset,
925
        clock,
926
        data,
927
        q);
928
 
929
        input     aclr;
930
        input     aset;
931
        input     clock;
932
        input     data;
933
        output    q;
934
 
935
        wire [0:0] sub_wire0;
936
        wire [0:0] sub_wire1 = sub_wire0[0:0];
937
        wire  q = sub_wire1;
938
        wire  sub_wire2 = data;
939
        wire  sub_wire3 = sub_wire2;
940
 
941
        lpm_ff  lpm_ff_component (
942
                                .aclr (aclr),
943
                                .clock (clock),
944
                                .data (sub_wire3),
945
                                .aset (aset),
946
                                .q (sub_wire0)
947
                                // synopsys translate_off
948
                                ,
949
                                .aload (),
950
                                .enable (),
951
                                .sclr (),
952
                                .sload (),
953
                                .sset ()
954
                                // synopsys translate_on
955
                                );
956
        defparam
957
                lpm_ff_component.lpm_fftype = "DFF",
958
                lpm_ff_component.lpm_type = "LPM_FF",
959
                lpm_ff_component.lpm_width = 1;
960
 
961
 
962
endmodule
963
 
964
// ============================================================
965
// CNX file retrieval info
966
// ============================================================
967
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
968
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
969
// Retrieval info: PRIVATE: ASET NUMERIC "1"
970
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
971
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
972
// Retrieval info: PRIVATE: DFF NUMERIC "1"
973
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
974
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
975
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
976
// Retrieval info: PRIVATE: SSET NUMERIC "0"
977
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
978
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
979
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
980
// Retrieval info: PRIVATE: nBit NUMERIC "1"
981
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
982
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
983
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
984
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
985
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
986
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
987
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
988
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
989
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
990
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
991
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
992
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
993
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
994
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
995
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
996
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
997
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
998
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
999
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1000
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1001
// Retrieval info: LIB_FILE: lpm
1002 40 unneback
`endif
1003 6 unneback
 
1004
`else
1005
 
1006 40 unneback
`ifdef DFF_SR
1007
`define MODULE dff_sr
1008
module `BASE`MODULE ( aclr, aset, clock, data, q);
1009
`undef MODULE
1010 6 unneback
 
1011
    input         aclr;
1012
    input         aset;
1013
    input         clock;
1014
    input         data;
1015
    output reg    q;
1016
 
1017
   always @ (posedge clock or posedge aclr or posedge aset)
1018
     if (aclr)
1019
       q <= 1'b0;
1020
     else if (aset)
1021
       q <= 1'b1;
1022
     else
1023
       q <= data;
1024
 
1025
endmodule
1026 40 unneback
`endif
1027 6 unneback
 
1028
`endif
1029
 
1030
// LATCH
1031
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1032
`ifdef ALTERA
1033 40 unneback
 
1034
`ifdef LATCH
1035
`define MODULE latch
1036
module `BASE`MODULE ( d, le, q, clk);
1037
`undef MODULE
1038 6 unneback
input d, le;
1039
output q;
1040
input clk;
1041
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1042
endmodule
1043 40 unneback
`endif
1044
 
1045 6 unneback
`else
1046 40 unneback
 
1047
`ifdef LATCH
1048
`define MODULE latch
1049
module `BASE`MODULE ( d, le, q, clk);
1050
`undef MODULE
1051 6 unneback
input d, le;
1052 48 unneback
input clk;
1053
always @ (le or d)
1054 60 unneback
if (le)
1055 48 unneback
    d <= q;
1056 6 unneback
endmodule
1057 15 unneback
`endif
1058
 
1059 40 unneback
`endif
1060
 
1061
`ifdef SHREG
1062
`define MODULE shreg
1063
module `BASE`MODULE ( d, q, clk, rst);
1064
`undef MODULE
1065
 
1066 17 unneback
parameter depth = 10;
1067
input d;
1068
output q;
1069
input clk, rst;
1070
 
1071
reg [1:depth] dffs;
1072
 
1073
always @ (posedge clk or posedge rst)
1074
if (rst)
1075
    dffs <= {depth{1'b0}};
1076
else
1077
    dffs <= {d,dffs[1:depth-1]};
1078
assign q = dffs[depth];
1079
endmodule
1080 40 unneback
`endif
1081 17 unneback
 
1082 40 unneback
`ifdef SHREG_CE
1083
`define MODULE shreg_ce
1084
module `BASE`MODULE ( d, ce, q, clk, rst);
1085
`undef MODULE
1086 17 unneback
parameter depth = 10;
1087
input d, ce;
1088
output q;
1089
input clk, rst;
1090
 
1091
reg [1:depth] dffs;
1092
 
1093
always @ (posedge clk or posedge rst)
1094
if (rst)
1095
    dffs <= {depth{1'b0}};
1096
else
1097
    if (ce)
1098
        dffs <= {d,dffs[1:depth-1]};
1099
assign q = dffs[depth];
1100
endmodule
1101 40 unneback
`endif
1102 17 unneback
 
1103 40 unneback
`ifdef DELAY
1104
`define MODULE delay
1105
module `BASE`MODULE ( d, q, clk, rst);
1106
`undef MODULE
1107 15 unneback
parameter depth = 10;
1108
input d;
1109
output q;
1110
input clk, rst;
1111
 
1112
reg [1:depth] dffs;
1113
 
1114
always @ (posedge clk or posedge rst)
1115
if (rst)
1116
    dffs <= {depth{1'b0}};
1117
else
1118
    dffs <= {d,dffs[1:depth-1]};
1119
assign q = dffs[depth];
1120 17 unneback
endmodule
1121 40 unneback
`endif
1122 17 unneback
 
1123 40 unneback
`ifdef DELAY_EMPTYFLAG
1124
`define MODULE delay_emptyflag
1125 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1126 40 unneback
`undef MODULE
1127 17 unneback
parameter depth = 10;
1128
input d;
1129
output q, emptyflag;
1130
input clk, rst;
1131
 
1132
reg [1:depth] dffs;
1133
 
1134
always @ (posedge clk or posedge rst)
1135
if (rst)
1136
    dffs <= {depth{1'b0}};
1137
else
1138
    dffs <= {d,dffs[1:depth-1]};
1139
assign q = dffs[depth];
1140
assign emptyflag = !(|dffs);
1141
endmodule
1142 40 unneback
`endif
1143 75 unneback
 
1144
`ifdef ASYNC_REG_REQ_ACK
1145
`define MODULE async_reg_req_ack
1146
module `BASE`MODULE ( d, q, req_i, req_o, ack_i, ack_o, clk_a, rst_a, clk_b, rst_b);
1147
`undef MODULE
1148
parameter data_width = 8;
1149
input [data_width-1:0] d;
1150
output [data_width-1:0] q;
1151
input req_i;
1152
output req_o;
1153
input ack_i;
1154
output ack_o;
1155
input clk_a, rst_a, clk_b, rst_b;
1156
 
1157
reg [3:0] reqi; // 3: last req in clk_a, 2: input dff, 1-0: sync
1158
wire rst;
1159
 
1160
always @ (posedge clk_a or rst_a)
1161
if (rst_a)
1162
    q <= {data_width{1'b0}};
1163
else
1164
    if (req_i)
1165
        q <= d;
1166
 
1167
assign rst = ack_i | rst_a;
1168
always @ (posedge clk_a or posedge rst)
1169
if (rst)
1170
    req[2] <= 1'b0;
1171
else
1172
    req[2] <= req_i & !ack_o;
1173
 
1174
always @ (posedge clk_a or posedge rst_a)
1175
if (rst_a)
1176
    req[3] <= 1'b0;
1177
else
1178
    req[3] <= req[2];
1179
 
1180
always @ (posedge clk_b or posedge rst_b)
1181
if (rst_b)
1182
    req[1:0] <= 2'b00;
1183
else
1184
    if (ack_i)
1185
        req[1:0] <= 2'b00;
1186
    else
1187
        req[1:0] <= req[2:1];
1188
assign req_o = req[0];
1189
 
1190
always @ (posedge clk_a or posedge rst_a)
1191
if (rst_a)
1192
    ack_o <= 1'b0;
1193
else
1194
    ack_o <= req[3] & req[2];
1195
 
1196
endmodule
1197
`endif
1198 17 unneback
//////////////////////////////////////////////////////////////////////
1199 6 unneback
////                                                              ////
1200 18 unneback
////  Logic functions                                             ////
1201
////                                                              ////
1202
////  Description                                                 ////
1203
////  Logic functions such as multiplexers                        ////
1204
////                                                              ////
1205
////                                                              ////
1206
////  To Do:                                                      ////
1207
////   -                                                          ////
1208
////                                                              ////
1209
////  Author(s):                                                  ////
1210
////      - Michael Unneback, unneback@opencores.org              ////
1211
////        ORSoC AB                                              ////
1212
////                                                              ////
1213
//////////////////////////////////////////////////////////////////////
1214
////                                                              ////
1215
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1216
////                                                              ////
1217
//// This source file may be used and distributed without         ////
1218
//// restriction provided that this copyright statement is not    ////
1219
//// removed from the file and that any derivative work contains  ////
1220
//// the original copyright notice and the associated disclaimer. ////
1221
////                                                              ////
1222
//// This source file is free software; you can redistribute it   ////
1223
//// and/or modify it under the terms of the GNU Lesser General   ////
1224
//// Public License as published by the Free Software Foundation; ////
1225
//// either version 2.1 of the License, or (at your option) any   ////
1226
//// later version.                                               ////
1227
////                                                              ////
1228
//// This source is distributed in the hope that it will be       ////
1229
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1230
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1231
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1232
//// details.                                                     ////
1233
////                                                              ////
1234
//// You should have received a copy of the GNU Lesser General    ////
1235
//// Public License along with this source; if not, download it   ////
1236
//// from http://www.opencores.org/lgpl.shtml                     ////
1237
////                                                              ////
1238
//////////////////////////////////////////////////////////////////////
1239 40 unneback
`ifdef MUX_ANDOR
1240
`define MODULE mux_andor
1241
module `BASE`MODULE ( a, sel, dout);
1242
`undef MODULE
1243 36 unneback
 
1244
parameter width = 32;
1245
parameter nr_of_ports = 4;
1246
 
1247
input [nr_of_ports*width-1:0] a;
1248
input [nr_of_ports-1:0] sel;
1249
output reg [width-1:0] dout;
1250
 
1251 38 unneback
integer i,j;
1252
 
1253 36 unneback
always @ (a, sel)
1254
begin
1255
    dout = a[width-1:0] & {width{sel[0]}};
1256 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1257
        for (j=0;j<width;j=j+1)
1258
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1259 36 unneback
end
1260
 
1261
endmodule
1262 40 unneback
`endif
1263 36 unneback
 
1264 40 unneback
`ifdef MUX2_ANDOR
1265
`define MODULE mux2_andor
1266
module `BASE`MODULE ( a1, a0, sel, dout);
1267
`undef MODULE
1268 18 unneback
 
1269 34 unneback
parameter width = 32;
1270 35 unneback
localparam nr_of_ports = 2;
1271 34 unneback
input [width-1:0] a1, a0;
1272
input [nr_of_ports-1:0] sel;
1273
output [width-1:0] dout;
1274
 
1275 40 unneback
`define MODULE mux_andor
1276
`BASE`MODULE
1277 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1278 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1279 40 unneback
`undef MODULE
1280
 
1281 34 unneback
endmodule
1282 40 unneback
`endif
1283 34 unneback
 
1284 40 unneback
`ifdef MUX3_ANDOR
1285
`define MODULE mux3_andor
1286
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1287
`undef MODULE
1288 34 unneback
 
1289
parameter width = 32;
1290 35 unneback
localparam nr_of_ports = 3;
1291 34 unneback
input [width-1:0] a2, a1, a0;
1292
input [nr_of_ports-1:0] sel;
1293
output [width-1:0] dout;
1294
 
1295 40 unneback
`define MODULE mux_andor
1296
`BASE`MODULE
1297 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1298 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1299 40 unneback
`undef MODULE
1300 34 unneback
endmodule
1301 40 unneback
`endif
1302 34 unneback
 
1303 40 unneback
`ifdef MUX4_ANDOR
1304
`define MODULE mux4_andor
1305
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1306
`undef MODULE
1307 18 unneback
 
1308
parameter width = 32;
1309 35 unneback
localparam nr_of_ports = 4;
1310 18 unneback
input [width-1:0] a3, a2, a1, a0;
1311
input [nr_of_ports-1:0] sel;
1312 22 unneback
output [width-1:0] dout;
1313 18 unneback
 
1314 40 unneback
`define MODULE mux_andor
1315
`BASE`MODULE
1316 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1317 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1318 40 unneback
`undef MODULE
1319 18 unneback
 
1320
endmodule
1321 40 unneback
`endif
1322 18 unneback
 
1323 40 unneback
`ifdef MUX5_ANDOR
1324
`define MODULE mux5_andor
1325
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1326
`undef MODULE
1327 18 unneback
 
1328
parameter width = 32;
1329 35 unneback
localparam nr_of_ports = 5;
1330 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1331
input [nr_of_ports-1:0] sel;
1332 22 unneback
output [width-1:0] dout;
1333 18 unneback
 
1334 40 unneback
`define MODULE mux_andor
1335
`BASE`MODULE
1336 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1337 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1338 40 unneback
`undef MODULE
1339 18 unneback
 
1340
endmodule
1341 40 unneback
`endif
1342 18 unneback
 
1343 40 unneback
`ifdef MUX6_ANDOR
1344
`define MODULE mux6_andor
1345
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1346
`undef MODULE
1347 18 unneback
 
1348
parameter width = 32;
1349 35 unneback
localparam nr_of_ports = 6;
1350 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1351
input [nr_of_ports-1:0] sel;
1352 22 unneback
output [width-1:0] dout;
1353 18 unneback
 
1354 40 unneback
`define MODULE mux_andor
1355
`BASE`MODULE
1356 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1357 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1358 40 unneback
`undef MODULE
1359 18 unneback
 
1360
endmodule
1361 40 unneback
`endif
1362 43 unneback
 
1363
`ifdef PARITY
1364
 
1365
`define MODULE parity_generate
1366
module `BASE`MODULE (data, parity);
1367
`undef MODULE
1368
parameter word_size = 32;
1369
parameter chunk_size = 8;
1370
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1371
input [word_size-1:0] data;
1372
output reg [word_size/chunk_size-1:0] parity;
1373
integer i,j;
1374
always @ (data)
1375
for (i=0;i<word_size/chunk_size;i=i+1) begin
1376
    parity[i] = parity_type;
1377
    for (j=0;j<chunk_size;j=j+1) begin
1378 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1379 43 unneback
    end
1380
end
1381
endmodule
1382
 
1383
`define MODULE parity_check
1384
module `BASE`MODULE( data, parity, parity_error);
1385
`undef MODULE
1386
parameter word_size = 32;
1387
parameter chunk_size = 8;
1388
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1389
input [word_size-1:0] data;
1390
input [word_size/chunk_size-1:0] parity;
1391
output parity_error;
1392 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1393 43 unneback
integer i,j;
1394
always @ (data or parity)
1395
for (i=0;i<word_size/chunk_size;i=i+1) begin
1396
    error_flag[i] = parity[i] ^ parity_type;
1397
    for (j=0;j<chunk_size;j=j+1) begin
1398 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1399 43 unneback
    end
1400
end
1401
assign parity_error = |error_flag;
1402
endmodule
1403
 
1404 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1405
////                                                              ////
1406
////  IO functions                                                ////
1407
////                                                              ////
1408
////  Description                                                 ////
1409
////  IO functions such as IOB flip-flops                         ////
1410
////                                                              ////
1411
////                                                              ////
1412
////  To Do:                                                      ////
1413
////   -                                                          ////
1414
////                                                              ////
1415
////  Author(s):                                                  ////
1416
////      - Michael Unneback, unneback@opencores.org              ////
1417
////        ORSoC AB                                              ////
1418
////                                                              ////
1419 18 unneback
//////////////////////////////////////////////////////////////////////
1420
////                                                              ////
1421 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1422
////                                                              ////
1423
//// This source file may be used and distributed without         ////
1424
//// restriction provided that this copyright statement is not    ////
1425
//// removed from the file and that any derivative work contains  ////
1426
//// the original copyright notice and the associated disclaimer. ////
1427
////                                                              ////
1428
//// This source file is free software; you can redistribute it   ////
1429
//// and/or modify it under the terms of the GNU Lesser General   ////
1430
//// Public License as published by the Free Software Foundation; ////
1431
//// either version 2.1 of the License, or (at your option) any   ////
1432
//// later version.                                               ////
1433
////                                                              ////
1434
//// This source is distributed in the hope that it will be       ////
1435
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1436
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1437
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1438
//// details.                                                     ////
1439
////                                                              ////
1440
//// You should have received a copy of the GNU Lesser General    ////
1441
//// Public License along with this source; if not, download it   ////
1442
//// from http://www.opencores.org/lgpl.shtml                     ////
1443
////                                                              ////
1444
//////////////////////////////////////////////////////////////////////
1445 45 unneback
`timescale 1ns/1ns
1446 44 unneback
`ifdef O_DFF
1447
`define MODULE o_dff
1448
module `BASE`MODULE (d_i, o_pad, clk, rst);
1449
`undef MODULE
1450
parameter width = 1;
1451 45 unneback
parameter reset_value = {width{1'b0}};
1452
input  [width-1:0]  d_i;
1453 44 unneback
output [width-1:0] o_pad;
1454
input clk, rst;
1455
wire [width-1:0] d_i_int `SYN_KEEP;
1456 45 unneback
reg  [width-1:0] o_pad_int;
1457 44 unneback
assign d_i_int = d_i;
1458
genvar i;
1459 45 unneback
generate
1460 44 unneback
for (i=0;i<width;i=i+1) begin
1461
    always @ (posedge clk or posedge rst)
1462
    if (rst)
1463 45 unneback
        o_pad_int[i] <= reset_value[i];
1464 44 unneback
    else
1465 45 unneback
        o_pad_int[i] <= d_i_int[i];
1466
    assign #1 o_pad[i] = o_pad_int[i];
1467 44 unneback
end
1468
endgenerate
1469
endmodule
1470
`endif
1471
 
1472 45 unneback
`timescale 1ns/1ns
1473 44 unneback
`ifdef IO_DFF_OE
1474
`define MODULE io_dff_oe
1475
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1476
`undef MODULE
1477
parameter width = 1;
1478
input  [width-1:0] d_o;
1479
output reg [width-1:0] d_i;
1480
input oe;
1481
inout [width-1:0] io_pad;
1482
input clk, rst;
1483
wire [width-1:0] oe_d `SYN_KEEP;
1484
reg [width-1:0] oe_q;
1485
reg [width-1:0] d_o_q;
1486
assign oe_d = {width{oe}};
1487
genvar i;
1488
generate
1489
for (i=0;i<width;i=i+1) begin
1490
    always @ (posedge clk or posedge rst)
1491
    if (rst)
1492
        oe_q[i] <= 1'b0;
1493
    else
1494
        oe_q[i] <= oe_d[i];
1495
    always @ (posedge clk or posedge rst)
1496
    if (rst)
1497
        d_o_q[i] <= 1'b0;
1498
    else
1499
        d_o_q[i] <= d_o[i];
1500
    always @ (posedge clk or posedge rst)
1501
    if (rst)
1502
        d_i[i] <= 1'b0;
1503
    else
1504
        d_i[i] <= io_pad[i];
1505 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1506 44 unneback
end
1507
endgenerate
1508
endmodule
1509
`endif
1510
`ifdef CNT_BIN
1511
//////////////////////////////////////////////////////////////////////
1512
////                                                              ////
1513 6 unneback
////  Versatile counter                                           ////
1514
////                                                              ////
1515
////  Description                                                 ////
1516
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1517
////  counter                                                     ////
1518
////                                                              ////
1519
////  To Do:                                                      ////
1520
////   - add LFSR with more taps                                  ////
1521
////                                                              ////
1522
////  Author(s):                                                  ////
1523
////      - Michael Unneback, unneback@opencores.org              ////
1524
////        ORSoC AB                                              ////
1525
////                                                              ////
1526
//////////////////////////////////////////////////////////////////////
1527
////                                                              ////
1528
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1529
////                                                              ////
1530
//// This source file may be used and distributed without         ////
1531
//// restriction provided that this copyright statement is not    ////
1532
//// removed from the file and that any derivative work contains  ////
1533
//// the original copyright notice and the associated disclaimer. ////
1534
////                                                              ////
1535
//// This source file is free software; you can redistribute it   ////
1536
//// and/or modify it under the terms of the GNU Lesser General   ////
1537
//// Public License as published by the Free Software Foundation; ////
1538
//// either version 2.1 of the License, or (at your option) any   ////
1539
//// later version.                                               ////
1540
////                                                              ////
1541
//// This source is distributed in the hope that it will be       ////
1542
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1543
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1544
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1545
//// details.                                                     ////
1546
////                                                              ////
1547
//// You should have received a copy of the GNU Lesser General    ////
1548
//// Public License along with this source; if not, download it   ////
1549
//// from http://www.opencores.org/lgpl.shtml                     ////
1550
////                                                              ////
1551
//////////////////////////////////////////////////////////////////////
1552
 
1553
// binary counter
1554 22 unneback
 
1555 40 unneback
`define MODULE cnt_bin
1556
module `BASE`MODULE (
1557
`undef MODULE
1558
 q, rst, clk);
1559
 
1560 22 unneback
   parameter length = 4;
1561
   output [length:1] q;
1562
   input rst;
1563
   input clk;
1564
 
1565
   parameter clear_value = 0;
1566
   parameter set_value = 1;
1567
   parameter wrap_value = 0;
1568
   parameter level1_value = 15;
1569
 
1570
   reg  [length:1] qi;
1571
   wire [length:1] q_next;
1572
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1573
 
1574
   always @ (posedge clk or posedge rst)
1575
     if (rst)
1576
       qi <= {length{1'b0}};
1577
     else
1578
       qi <= q_next;
1579
 
1580
   assign q = qi;
1581
 
1582
endmodule
1583 40 unneback
`endif
1584
`ifdef CNT_BIN_CLEAR
1585 22 unneback
//////////////////////////////////////////////////////////////////////
1586
////                                                              ////
1587
////  Versatile counter                                           ////
1588
////                                                              ////
1589
////  Description                                                 ////
1590
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1591
////  counter                                                     ////
1592
////                                                              ////
1593
////  To Do:                                                      ////
1594
////   - add LFSR with more taps                                  ////
1595
////                                                              ////
1596
////  Author(s):                                                  ////
1597
////      - Michael Unneback, unneback@opencores.org              ////
1598
////        ORSoC AB                                              ////
1599
////                                                              ////
1600
//////////////////////////////////////////////////////////////////////
1601
////                                                              ////
1602
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1603
////                                                              ////
1604
//// This source file may be used and distributed without         ////
1605
//// restriction provided that this copyright statement is not    ////
1606
//// removed from the file and that any derivative work contains  ////
1607
//// the original copyright notice and the associated disclaimer. ////
1608
////                                                              ////
1609
//// This source file is free software; you can redistribute it   ////
1610
//// and/or modify it under the terms of the GNU Lesser General   ////
1611
//// Public License as published by the Free Software Foundation; ////
1612
//// either version 2.1 of the License, or (at your option) any   ////
1613
//// later version.                                               ////
1614
////                                                              ////
1615
//// This source is distributed in the hope that it will be       ////
1616
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1617
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1618
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1619
//// details.                                                     ////
1620
////                                                              ////
1621
//// You should have received a copy of the GNU Lesser General    ////
1622
//// Public License along with this source; if not, download it   ////
1623
//// from http://www.opencores.org/lgpl.shtml                     ////
1624
////                                                              ////
1625
//////////////////////////////////////////////////////////////////////
1626
 
1627
// binary counter
1628
 
1629 40 unneback
`define MODULE cnt_bin_clear
1630
module `BASE`MODULE (
1631
`undef MODULE
1632
 clear, q, rst, clk);
1633
 
1634 22 unneback
   parameter length = 4;
1635
   input clear;
1636
   output [length:1] q;
1637
   input rst;
1638
   input clk;
1639
 
1640
   parameter clear_value = 0;
1641
   parameter set_value = 1;
1642
   parameter wrap_value = 0;
1643
   parameter level1_value = 15;
1644
 
1645
   reg  [length:1] qi;
1646
   wire [length:1] q_next;
1647
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1648
 
1649
   always @ (posedge clk or posedge rst)
1650
     if (rst)
1651
       qi <= {length{1'b0}};
1652
     else
1653
       qi <= q_next;
1654
 
1655
   assign q = qi;
1656
 
1657
endmodule
1658 40 unneback
`endif
1659
`ifdef CNT_BIN_CE
1660 22 unneback
//////////////////////////////////////////////////////////////////////
1661
////                                                              ////
1662
////  Versatile counter                                           ////
1663
////                                                              ////
1664
////  Description                                                 ////
1665
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1666
////  counter                                                     ////
1667
////                                                              ////
1668
////  To Do:                                                      ////
1669
////   - add LFSR with more taps                                  ////
1670
////                                                              ////
1671
////  Author(s):                                                  ////
1672
////      - Michael Unneback, unneback@opencores.org              ////
1673
////        ORSoC AB                                              ////
1674
////                                                              ////
1675
//////////////////////////////////////////////////////////////////////
1676
////                                                              ////
1677
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1678
////                                                              ////
1679
//// This source file may be used and distributed without         ////
1680
//// restriction provided that this copyright statement is not    ////
1681
//// removed from the file and that any derivative work contains  ////
1682
//// the original copyright notice and the associated disclaimer. ////
1683
////                                                              ////
1684
//// This source file is free software; you can redistribute it   ////
1685
//// and/or modify it under the terms of the GNU Lesser General   ////
1686
//// Public License as published by the Free Software Foundation; ////
1687
//// either version 2.1 of the License, or (at your option) any   ////
1688
//// later version.                                               ////
1689
////                                                              ////
1690
//// This source is distributed in the hope that it will be       ////
1691
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1692
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1693
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1694
//// details.                                                     ////
1695
////                                                              ////
1696
//// You should have received a copy of the GNU Lesser General    ////
1697
//// Public License along with this source; if not, download it   ////
1698
//// from http://www.opencores.org/lgpl.shtml                     ////
1699
////                                                              ////
1700
//////////////////////////////////////////////////////////////////////
1701
 
1702
// binary counter
1703 6 unneback
 
1704 40 unneback
`define MODULE cnt_bin_ce
1705
module `BASE`MODULE (
1706
`undef MODULE
1707
 cke, q, rst, clk);
1708
 
1709 6 unneback
   parameter length = 4;
1710
   input cke;
1711
   output [length:1] q;
1712
   input rst;
1713
   input clk;
1714
 
1715
   parameter clear_value = 0;
1716
   parameter set_value = 1;
1717
   parameter wrap_value = 0;
1718
   parameter level1_value = 15;
1719
 
1720
   reg  [length:1] qi;
1721
   wire [length:1] q_next;
1722
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1723
 
1724
   always @ (posedge clk or posedge rst)
1725
     if (rst)
1726
       qi <= {length{1'b0}};
1727
     else
1728
     if (cke)
1729
       qi <= q_next;
1730
 
1731
   assign q = qi;
1732
 
1733
endmodule
1734 40 unneback
`endif
1735
`ifdef CNT_BIN_CE_CLEAR
1736 6 unneback
//////////////////////////////////////////////////////////////////////
1737
////                                                              ////
1738
////  Versatile counter                                           ////
1739
////                                                              ////
1740
////  Description                                                 ////
1741
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1742
////  counter                                                     ////
1743
////                                                              ////
1744
////  To Do:                                                      ////
1745
////   - add LFSR with more taps                                  ////
1746
////                                                              ////
1747
////  Author(s):                                                  ////
1748
////      - Michael Unneback, unneback@opencores.org              ////
1749
////        ORSoC AB                                              ////
1750
////                                                              ////
1751
//////////////////////////////////////////////////////////////////////
1752
////                                                              ////
1753
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1754
////                                                              ////
1755
//// This source file may be used and distributed without         ////
1756
//// restriction provided that this copyright statement is not    ////
1757
//// removed from the file and that any derivative work contains  ////
1758
//// the original copyright notice and the associated disclaimer. ////
1759
////                                                              ////
1760
//// This source file is free software; you can redistribute it   ////
1761
//// and/or modify it under the terms of the GNU Lesser General   ////
1762
//// Public License as published by the Free Software Foundation; ////
1763
//// either version 2.1 of the License, or (at your option) any   ////
1764
//// later version.                                               ////
1765
////                                                              ////
1766
//// This source is distributed in the hope that it will be       ////
1767
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1768
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1769
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1770
//// details.                                                     ////
1771
////                                                              ////
1772
//// You should have received a copy of the GNU Lesser General    ////
1773
//// Public License along with this source; if not, download it   ////
1774
//// from http://www.opencores.org/lgpl.shtml                     ////
1775
////                                                              ////
1776
//////////////////////////////////////////////////////////////////////
1777
 
1778
// binary counter
1779
 
1780 40 unneback
`define MODULE cnt_bin_ce_clear
1781
module `BASE`MODULE (
1782
`undef MODULE
1783
 clear, cke, q, rst, clk);
1784
 
1785 6 unneback
   parameter length = 4;
1786
   input clear;
1787
   input cke;
1788
   output [length:1] q;
1789
   input rst;
1790
   input clk;
1791
 
1792
   parameter clear_value = 0;
1793
   parameter set_value = 1;
1794
   parameter wrap_value = 0;
1795
   parameter level1_value = 15;
1796
 
1797
   reg  [length:1] qi;
1798
   wire [length:1] q_next;
1799
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1800
 
1801
   always @ (posedge clk or posedge rst)
1802
     if (rst)
1803
       qi <= {length{1'b0}};
1804
     else
1805
     if (cke)
1806
       qi <= q_next;
1807
 
1808
   assign q = qi;
1809
 
1810
endmodule
1811 40 unneback
`endif
1812
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1813 6 unneback
//////////////////////////////////////////////////////////////////////
1814
////                                                              ////
1815
////  Versatile counter                                           ////
1816
////                                                              ////
1817
////  Description                                                 ////
1818
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1819
////  counter                                                     ////
1820
////                                                              ////
1821
////  To Do:                                                      ////
1822
////   - add LFSR with more taps                                  ////
1823
////                                                              ////
1824
////  Author(s):                                                  ////
1825
////      - Michael Unneback, unneback@opencores.org              ////
1826
////        ORSoC AB                                              ////
1827
////                                                              ////
1828
//////////////////////////////////////////////////////////////////////
1829
////                                                              ////
1830
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1831
////                                                              ////
1832
//// This source file may be used and distributed without         ////
1833
//// restriction provided that this copyright statement is not    ////
1834
//// removed from the file and that any derivative work contains  ////
1835
//// the original copyright notice and the associated disclaimer. ////
1836
////                                                              ////
1837
//// This source file is free software; you can redistribute it   ////
1838
//// and/or modify it under the terms of the GNU Lesser General   ////
1839
//// Public License as published by the Free Software Foundation; ////
1840
//// either version 2.1 of the License, or (at your option) any   ////
1841
//// later version.                                               ////
1842
////                                                              ////
1843
//// This source is distributed in the hope that it will be       ////
1844
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1845
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1846
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1847
//// details.                                                     ////
1848
////                                                              ////
1849
//// You should have received a copy of the GNU Lesser General    ////
1850
//// Public License along with this source; if not, download it   ////
1851
//// from http://www.opencores.org/lgpl.shtml                     ////
1852
////                                                              ////
1853
//////////////////////////////////////////////////////////////////////
1854
 
1855
// binary counter
1856 29 unneback
 
1857 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1858
module `BASE`MODULE (
1859
`undef MODULE
1860
 clear, cke, q, level1, level2, rst, clk);
1861
 
1862 29 unneback
   parameter length = 4;
1863
   input clear;
1864
   input cke;
1865
   output [length:1] q;
1866
   output reg level1;
1867
   output reg level2;
1868
   input rst;
1869
   input clk;
1870
 
1871
   parameter clear_value = 0;
1872
   parameter set_value = 1;
1873 30 unneback
   parameter wrap_value = 15;
1874
   parameter level1_value = 8;
1875
   parameter level2_value = 15;
1876 29 unneback
 
1877
   wire rew;
1878 30 unneback
   assign rew = 1'b0;
1879 29 unneback
   reg  [length:1] qi;
1880
   wire [length:1] q_next;
1881
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1882
 
1883
   always @ (posedge clk or posedge rst)
1884
     if (rst)
1885
       qi <= {length{1'b0}};
1886
     else
1887
     if (cke)
1888
       qi <= q_next;
1889
 
1890
   assign q = qi;
1891
 
1892
 
1893
    always @ (posedge clk or posedge rst)
1894
    if (rst)
1895
        level1 <= 1'b0;
1896
    else
1897
    if (cke)
1898
    if (clear)
1899
        level1 <= 1'b0;
1900
    else if (q_next == level1_value)
1901
        level1 <= 1'b1;
1902
    else if (qi == level1_value & rew)
1903
        level1 <= 1'b0;
1904
 
1905
    always @ (posedge clk or posedge rst)
1906
    if (rst)
1907
        level2 <= 1'b0;
1908
    else
1909
    if (cke)
1910
    if (clear)
1911
        level2 <= 1'b0;
1912
    else if (q_next == level2_value)
1913
        level2 <= 1'b1;
1914
    else if (qi == level2_value & rew)
1915
        level2 <= 1'b0;
1916
endmodule
1917 40 unneback
`endif
1918
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1919 29 unneback
//////////////////////////////////////////////////////////////////////
1920
////                                                              ////
1921
////  Versatile counter                                           ////
1922
////                                                              ////
1923
////  Description                                                 ////
1924
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1925
////  counter                                                     ////
1926
////                                                              ////
1927
////  To Do:                                                      ////
1928
////   - add LFSR with more taps                                  ////
1929
////                                                              ////
1930
////  Author(s):                                                  ////
1931
////      - Michael Unneback, unneback@opencores.org              ////
1932
////        ORSoC AB                                              ////
1933
////                                                              ////
1934
//////////////////////////////////////////////////////////////////////
1935
////                                                              ////
1936
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1937
////                                                              ////
1938
//// This source file may be used and distributed without         ////
1939
//// restriction provided that this copyright statement is not    ////
1940
//// removed from the file and that any derivative work contains  ////
1941
//// the original copyright notice and the associated disclaimer. ////
1942
////                                                              ////
1943
//// This source file is free software; you can redistribute it   ////
1944
//// and/or modify it under the terms of the GNU Lesser General   ////
1945
//// Public License as published by the Free Software Foundation; ////
1946
//// either version 2.1 of the License, or (at your option) any   ////
1947
//// later version.                                               ////
1948
////                                                              ////
1949
//// This source is distributed in the hope that it will be       ////
1950
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1951
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1952
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1953
//// details.                                                     ////
1954
////                                                              ////
1955
//// You should have received a copy of the GNU Lesser General    ////
1956
//// Public License along with this source; if not, download it   ////
1957
//// from http://www.opencores.org/lgpl.shtml                     ////
1958
////                                                              ////
1959
//////////////////////////////////////////////////////////////////////
1960
 
1961
// binary counter
1962 6 unneback
 
1963 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1964
module `BASE`MODULE (
1965
`undef MODULE
1966
 clear, set, cke, rew, q, rst, clk);
1967
 
1968 6 unneback
   parameter length = 4;
1969
   input clear;
1970
   input set;
1971
   input cke;
1972
   input rew;
1973
   output [length:1] q;
1974
   input rst;
1975
   input clk;
1976
 
1977
   parameter clear_value = 0;
1978
   parameter set_value = 1;
1979
   parameter wrap_value = 0;
1980
   parameter level1_value = 15;
1981
 
1982
   reg  [length:1] qi;
1983
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1984
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1985
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1986
   assign q_next = rew ? q_next_rew : q_next_fw;
1987
 
1988
   always @ (posedge clk or posedge rst)
1989
     if (rst)
1990
       qi <= {length{1'b0}};
1991
     else
1992
     if (cke)
1993
       qi <= q_next;
1994
 
1995
   assign q = qi;
1996
 
1997
endmodule
1998 40 unneback
`endif
1999
`ifdef CNT_BIN_CE_REW_L1
2000 6 unneback
//////////////////////////////////////////////////////////////////////
2001
////                                                              ////
2002
////  Versatile counter                                           ////
2003
////                                                              ////
2004
////  Description                                                 ////
2005
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2006
////  counter                                                     ////
2007
////                                                              ////
2008
////  To Do:                                                      ////
2009
////   - add LFSR with more taps                                  ////
2010
////                                                              ////
2011
////  Author(s):                                                  ////
2012
////      - Michael Unneback, unneback@opencores.org              ////
2013
////        ORSoC AB                                              ////
2014
////                                                              ////
2015
//////////////////////////////////////////////////////////////////////
2016
////                                                              ////
2017
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2018
////                                                              ////
2019
//// This source file may be used and distributed without         ////
2020
//// restriction provided that this copyright statement is not    ////
2021
//// removed from the file and that any derivative work contains  ////
2022
//// the original copyright notice and the associated disclaimer. ////
2023
////                                                              ////
2024
//// This source file is free software; you can redistribute it   ////
2025
//// and/or modify it under the terms of the GNU Lesser General   ////
2026
//// Public License as published by the Free Software Foundation; ////
2027
//// either version 2.1 of the License, or (at your option) any   ////
2028
//// later version.                                               ////
2029
////                                                              ////
2030
//// This source is distributed in the hope that it will be       ////
2031
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2032
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2033
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2034
//// details.                                                     ////
2035
////                                                              ////
2036
//// You should have received a copy of the GNU Lesser General    ////
2037
//// Public License along with this source; if not, download it   ////
2038
//// from http://www.opencores.org/lgpl.shtml                     ////
2039
////                                                              ////
2040
//////////////////////////////////////////////////////////////////////
2041
 
2042
// binary counter
2043
 
2044 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2045
module `BASE`MODULE (
2046
`undef MODULE
2047
 cke, rew, level1, rst, clk);
2048
 
2049 6 unneback
   parameter length = 4;
2050
   input cke;
2051
   input rew;
2052
   output reg level1;
2053
   input rst;
2054
   input clk;
2055
 
2056
   parameter clear_value = 0;
2057
   parameter set_value = 1;
2058
   parameter wrap_value = 1;
2059
   parameter level1_value = 15;
2060
 
2061 29 unneback
   wire clear;
2062 30 unneback
   assign clear = 1'b0;
2063 6 unneback
   reg  [length:1] qi;
2064
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2065
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2066
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2067
   assign q_next = rew ? q_next_rew : q_next_fw;
2068
 
2069
   always @ (posedge clk or posedge rst)
2070
     if (rst)
2071
       qi <= {length{1'b0}};
2072
     else
2073
     if (cke)
2074
       qi <= q_next;
2075
 
2076
 
2077
 
2078
    always @ (posedge clk or posedge rst)
2079
    if (rst)
2080
        level1 <= 1'b0;
2081
    else
2082
    if (cke)
2083 29 unneback
    if (clear)
2084
        level1 <= 1'b0;
2085
    else if (q_next == level1_value)
2086 6 unneback
        level1 <= 1'b1;
2087
    else if (qi == level1_value & rew)
2088
        level1 <= 1'b0;
2089
endmodule
2090 40 unneback
`endif
2091
`ifdef CNT_BIN_CE_REW_ZQ_L1
2092 6 unneback
//////////////////////////////////////////////////////////////////////
2093
////                                                              ////
2094
////  Versatile counter                                           ////
2095
////                                                              ////
2096
////  Description                                                 ////
2097
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2098
////  counter                                                     ////
2099
////                                                              ////
2100
////  To Do:                                                      ////
2101
////   - add LFSR with more taps                                  ////
2102
////                                                              ////
2103
////  Author(s):                                                  ////
2104
////      - Michael Unneback, unneback@opencores.org              ////
2105
////        ORSoC AB                                              ////
2106
////                                                              ////
2107
//////////////////////////////////////////////////////////////////////
2108
////                                                              ////
2109
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2110
////                                                              ////
2111
//// This source file may be used and distributed without         ////
2112
//// restriction provided that this copyright statement is not    ////
2113
//// removed from the file and that any derivative work contains  ////
2114
//// the original copyright notice and the associated disclaimer. ////
2115
////                                                              ////
2116
//// This source file is free software; you can redistribute it   ////
2117
//// and/or modify it under the terms of the GNU Lesser General   ////
2118
//// Public License as published by the Free Software Foundation; ////
2119
//// either version 2.1 of the License, or (at your option) any   ////
2120
//// later version.                                               ////
2121
////                                                              ////
2122
//// This source is distributed in the hope that it will be       ////
2123
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2124
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2125
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2126
//// details.                                                     ////
2127
////                                                              ////
2128
//// You should have received a copy of the GNU Lesser General    ////
2129
//// Public License along with this source; if not, download it   ////
2130
//// from http://www.opencores.org/lgpl.shtml                     ////
2131
////                                                              ////
2132
//////////////////////////////////////////////////////////////////////
2133
 
2134 25 unneback
// binary counter
2135
 
2136 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2137
module `BASE`MODULE (
2138
`undef MODULE
2139
 cke, rew, zq, level1, rst, clk);
2140
 
2141 25 unneback
   parameter length = 4;
2142
   input cke;
2143
   input rew;
2144
   output reg zq;
2145
   output reg level1;
2146
   input rst;
2147
   input clk;
2148
 
2149
   parameter clear_value = 0;
2150
   parameter set_value = 1;
2151
   parameter wrap_value = 1;
2152
   parameter level1_value = 15;
2153
 
2154 29 unneback
   wire clear;
2155 30 unneback
   assign clear = 1'b0;
2156 25 unneback
   reg  [length:1] qi;
2157
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2158
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2159
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2160
   assign q_next = rew ? q_next_rew : q_next_fw;
2161
 
2162
   always @ (posedge clk or posedge rst)
2163
     if (rst)
2164
       qi <= {length{1'b0}};
2165
     else
2166
     if (cke)
2167
       qi <= q_next;
2168
 
2169
 
2170
 
2171
   always @ (posedge clk or posedge rst)
2172
     if (rst)
2173
       zq <= 1'b1;
2174
     else
2175
     if (cke)
2176
       zq <= q_next == {length{1'b0}};
2177
 
2178
    always @ (posedge clk or posedge rst)
2179
    if (rst)
2180
        level1 <= 1'b0;
2181
    else
2182
    if (cke)
2183 29 unneback
    if (clear)
2184
        level1 <= 1'b0;
2185
    else if (q_next == level1_value)
2186 25 unneback
        level1 <= 1'b1;
2187
    else if (qi == level1_value & rew)
2188
        level1 <= 1'b0;
2189
endmodule
2190 40 unneback
`endif
2191
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2192 25 unneback
//////////////////////////////////////////////////////////////////////
2193
////                                                              ////
2194
////  Versatile counter                                           ////
2195
////                                                              ////
2196
////  Description                                                 ////
2197
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2198
////  counter                                                     ////
2199
////                                                              ////
2200
////  To Do:                                                      ////
2201
////   - add LFSR with more taps                                  ////
2202
////                                                              ////
2203
////  Author(s):                                                  ////
2204
////      - Michael Unneback, unneback@opencores.org              ////
2205
////        ORSoC AB                                              ////
2206
////                                                              ////
2207
//////////////////////////////////////////////////////////////////////
2208
////                                                              ////
2209
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2210
////                                                              ////
2211
//// This source file may be used and distributed without         ////
2212
//// restriction provided that this copyright statement is not    ////
2213
//// removed from the file and that any derivative work contains  ////
2214
//// the original copyright notice and the associated disclaimer. ////
2215
////                                                              ////
2216
//// This source file is free software; you can redistribute it   ////
2217
//// and/or modify it under the terms of the GNU Lesser General   ////
2218
//// Public License as published by the Free Software Foundation; ////
2219
//// either version 2.1 of the License, or (at your option) any   ////
2220
//// later version.                                               ////
2221
////                                                              ////
2222
//// This source is distributed in the hope that it will be       ////
2223
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2224
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2225
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2226
//// details.                                                     ////
2227
////                                                              ////
2228
//// You should have received a copy of the GNU Lesser General    ////
2229
//// Public License along with this source; if not, download it   ////
2230
//// from http://www.opencores.org/lgpl.shtml                     ////
2231
////                                                              ////
2232
//////////////////////////////////////////////////////////////////////
2233
 
2234
// binary counter
2235
 
2236 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2237
module `BASE`MODULE (
2238
`undef MODULE
2239
 cke, rew, q, zq, level1, rst, clk);
2240
 
2241 25 unneback
   parameter length = 4;
2242
   input cke;
2243
   input rew;
2244
   output [length:1] q;
2245
   output reg zq;
2246
   output reg level1;
2247
   input rst;
2248
   input clk;
2249
 
2250
   parameter clear_value = 0;
2251
   parameter set_value = 1;
2252
   parameter wrap_value = 1;
2253
   parameter level1_value = 15;
2254
 
2255 29 unneback
   wire clear;
2256 30 unneback
   assign clear = 1'b0;
2257 25 unneback
   reg  [length:1] qi;
2258
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2259
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2260
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2261
   assign q_next = rew ? q_next_rew : q_next_fw;
2262
 
2263
   always @ (posedge clk or posedge rst)
2264
     if (rst)
2265
       qi <= {length{1'b0}};
2266
     else
2267
     if (cke)
2268
       qi <= q_next;
2269
 
2270
   assign q = qi;
2271
 
2272
 
2273
   always @ (posedge clk or posedge rst)
2274
     if (rst)
2275
       zq <= 1'b1;
2276
     else
2277
     if (cke)
2278
       zq <= q_next == {length{1'b0}};
2279
 
2280
    always @ (posedge clk or posedge rst)
2281
    if (rst)
2282
        level1 <= 1'b0;
2283
    else
2284
    if (cke)
2285 29 unneback
    if (clear)
2286
        level1 <= 1'b0;
2287
    else if (q_next == level1_value)
2288 25 unneback
        level1 <= 1'b1;
2289
    else if (qi == level1_value & rew)
2290
        level1 <= 1'b0;
2291
endmodule
2292 40 unneback
`endif
2293
`ifdef CNT_LFSR_ZQ
2294 25 unneback
//////////////////////////////////////////////////////////////////////
2295
////                                                              ////
2296
////  Versatile counter                                           ////
2297
////                                                              ////
2298
////  Description                                                 ////
2299
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2300
////  counter                                                     ////
2301
////                                                              ////
2302
////  To Do:                                                      ////
2303
////   - add LFSR with more taps                                  ////
2304
////                                                              ////
2305
////  Author(s):                                                  ////
2306
////      - Michael Unneback, unneback@opencores.org              ////
2307
////        ORSoC AB                                              ////
2308
////                                                              ////
2309
//////////////////////////////////////////////////////////////////////
2310
////                                                              ////
2311
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2312
////                                                              ////
2313
//// This source file may be used and distributed without         ////
2314
//// restriction provided that this copyright statement is not    ////
2315
//// removed from the file and that any derivative work contains  ////
2316
//// the original copyright notice and the associated disclaimer. ////
2317
////                                                              ////
2318
//// This source file is free software; you can redistribute it   ////
2319
//// and/or modify it under the terms of the GNU Lesser General   ////
2320
//// Public License as published by the Free Software Foundation; ////
2321
//// either version 2.1 of the License, or (at your option) any   ////
2322
//// later version.                                               ////
2323
////                                                              ////
2324
//// This source is distributed in the hope that it will be       ////
2325
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2326
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2327
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2328
//// details.                                                     ////
2329
////                                                              ////
2330
//// You should have received a copy of the GNU Lesser General    ////
2331
//// Public License along with this source; if not, download it   ////
2332
//// from http://www.opencores.org/lgpl.shtml                     ////
2333
////                                                              ////
2334
//////////////////////////////////////////////////////////////////////
2335
 
2336 6 unneback
// LFSR counter
2337
 
2338 40 unneback
`define MODULE cnt_lfsr_zq
2339
module `BASE`MODULE (
2340
`undef MODULE
2341
 zq, rst, clk);
2342
 
2343 6 unneback
   parameter length = 4;
2344
   output reg zq;
2345
   input rst;
2346
   input clk;
2347
 
2348
   parameter clear_value = 0;
2349
   parameter set_value = 1;
2350
   parameter wrap_value = 8;
2351
   parameter level1_value = 15;
2352
 
2353
   reg  [length:1] qi;
2354
   reg lfsr_fb;
2355
   wire [length:1] q_next;
2356
   reg [32:1] polynom;
2357
   integer i;
2358
 
2359
   always @ (qi)
2360
   begin
2361
        case (length)
2362
         2: polynom = 32'b11;                               // 0x3
2363
         3: polynom = 32'b110;                              // 0x6
2364
         4: polynom = 32'b1100;                             // 0xC
2365
         5: polynom = 32'b10100;                            // 0x14
2366
         6: polynom = 32'b110000;                           // 0x30
2367
         7: polynom = 32'b1100000;                          // 0x60
2368
         8: polynom = 32'b10111000;                         // 0xb8
2369
         9: polynom = 32'b100010000;                        // 0x110
2370
        10: polynom = 32'b1001000000;                       // 0x240
2371
        11: polynom = 32'b10100000000;                      // 0x500
2372
        12: polynom = 32'b100000101001;                     // 0x829
2373
        13: polynom = 32'b1000000001100;                    // 0x100C
2374
        14: polynom = 32'b10000000010101;                   // 0x2015
2375
        15: polynom = 32'b110000000000000;                  // 0x6000
2376
        16: polynom = 32'b1101000000001000;                 // 0xD008
2377
        17: polynom = 32'b10010000000000000;                // 0x12000
2378
        18: polynom = 32'b100000010000000000;               // 0x20400
2379
        19: polynom = 32'b1000000000000100011;              // 0x40023
2380 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2381 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2382
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2383
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2384
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2385
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2386
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2387
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2388
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2389
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2390
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2391
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2392
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2393
        default: polynom = 32'b0;
2394
        endcase
2395
        lfsr_fb = qi[length];
2396
        for (i=length-1; i>=1; i=i-1) begin
2397
            if (polynom[i])
2398
                lfsr_fb = lfsr_fb  ~^ qi[i];
2399
        end
2400
    end
2401
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2402
 
2403
   always @ (posedge clk or posedge rst)
2404
     if (rst)
2405
       qi <= {length{1'b0}};
2406
     else
2407
       qi <= q_next;
2408
 
2409
 
2410
 
2411
   always @ (posedge clk or posedge rst)
2412
     if (rst)
2413
       zq <= 1'b1;
2414
     else
2415
       zq <= q_next == {length{1'b0}};
2416
endmodule
2417 40 unneback
`endif
2418 75 unneback
`ifdef CNT_LFSR_CE
2419
//////////////////////////////////////////////////////////////////////
2420
////                                                              ////
2421
////  Versatile counter                                           ////
2422
////                                                              ////
2423
////  Description                                                 ////
2424
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2425
////  counter                                                     ////
2426
////                                                              ////
2427
////  To Do:                                                      ////
2428
////   - add LFSR with more taps                                  ////
2429
////                                                              ////
2430
////  Author(s):                                                  ////
2431
////      - Michael Unneback, unneback@opencores.org              ////
2432
////        ORSoC AB                                              ////
2433
////                                                              ////
2434
//////////////////////////////////////////////////////////////////////
2435
////                                                              ////
2436
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2437
////                                                              ////
2438
//// This source file may be used and distributed without         ////
2439
//// restriction provided that this copyright statement is not    ////
2440
//// removed from the file and that any derivative work contains  ////
2441
//// the original copyright notice and the associated disclaimer. ////
2442
////                                                              ////
2443
//// This source file is free software; you can redistribute it   ////
2444
//// and/or modify it under the terms of the GNU Lesser General   ////
2445
//// Public License as published by the Free Software Foundation; ////
2446
//// either version 2.1 of the License, or (at your option) any   ////
2447
//// later version.                                               ////
2448
////                                                              ////
2449
//// This source is distributed in the hope that it will be       ////
2450
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2451
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2452
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2453
//// details.                                                     ////
2454
////                                                              ////
2455
//// You should have received a copy of the GNU Lesser General    ////
2456
//// Public License along with this source; if not, download it   ////
2457
//// from http://www.opencores.org/lgpl.shtml                     ////
2458
////                                                              ////
2459
//////////////////////////////////////////////////////////////////////
2460
 
2461
// LFSR counter
2462
 
2463
`define MODULE cnt_lfsr_ce
2464
module `BASE`MODULE (
2465
`undef MODULE
2466
 cke, zq, rst, clk);
2467
 
2468
   parameter length = 4;
2469
   input cke;
2470
   output reg zq;
2471
   input rst;
2472
   input clk;
2473
 
2474
   parameter clear_value = 0;
2475
   parameter set_value = 1;
2476
   parameter wrap_value = 0;
2477
   parameter level1_value = 15;
2478
 
2479
   reg  [length:1] qi;
2480
   reg lfsr_fb;
2481
   wire [length:1] q_next;
2482
   reg [32:1] polynom;
2483
   integer i;
2484
 
2485
   always @ (qi)
2486
   begin
2487
        case (length)
2488
         2: polynom = 32'b11;                               // 0x3
2489
         3: polynom = 32'b110;                              // 0x6
2490
         4: polynom = 32'b1100;                             // 0xC
2491
         5: polynom = 32'b10100;                            // 0x14
2492
         6: polynom = 32'b110000;                           // 0x30
2493
         7: polynom = 32'b1100000;                          // 0x60
2494
         8: polynom = 32'b10111000;                         // 0xb8
2495
         9: polynom = 32'b100010000;                        // 0x110
2496
        10: polynom = 32'b1001000000;                       // 0x240
2497
        11: polynom = 32'b10100000000;                      // 0x500
2498
        12: polynom = 32'b100000101001;                     // 0x829
2499
        13: polynom = 32'b1000000001100;                    // 0x100C
2500
        14: polynom = 32'b10000000010101;                   // 0x2015
2501
        15: polynom = 32'b110000000000000;                  // 0x6000
2502
        16: polynom = 32'b1101000000001000;                 // 0xD008
2503
        17: polynom = 32'b10010000000000000;                // 0x12000
2504
        18: polynom = 32'b100000010000000000;               // 0x20400
2505
        19: polynom = 32'b1000000000000100011;              // 0x40023
2506
        20: polynom = 32'b10010000000000000000;             // 0x90000
2507
        21: polynom = 32'b101000000000000000000;            // 0x140000
2508
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2509
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2510
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2511
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2512
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2513
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2514
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2515
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2516
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2517
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2518
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2519
        default: polynom = 32'b0;
2520
        endcase
2521
        lfsr_fb = qi[length];
2522
        for (i=length-1; i>=1; i=i-1) begin
2523
            if (polynom[i])
2524
                lfsr_fb = lfsr_fb  ~^ qi[i];
2525
        end
2526
    end
2527
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2528
 
2529
   always @ (posedge clk or posedge rst)
2530
     if (rst)
2531
       qi <= {length{1'b0}};
2532
     else
2533
     if (cke)
2534
       qi <= q_next;
2535
 
2536
 
2537
 
2538
   always @ (posedge clk or posedge rst)
2539
     if (rst)
2540
       zq <= 1'b1;
2541
     else
2542
     if (cke)
2543
       zq <= q_next == {length{1'b0}};
2544
endmodule
2545
`endif
2546 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2547 6 unneback
//////////////////////////////////////////////////////////////////////
2548
////                                                              ////
2549
////  Versatile counter                                           ////
2550
////                                                              ////
2551
////  Description                                                 ////
2552
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2553
////  counter                                                     ////
2554
////                                                              ////
2555
////  To Do:                                                      ////
2556
////   - add LFSR with more taps                                  ////
2557
////                                                              ////
2558
////  Author(s):                                                  ////
2559
////      - Michael Unneback, unneback@opencores.org              ////
2560
////        ORSoC AB                                              ////
2561
////                                                              ////
2562
//////////////////////////////////////////////////////////////////////
2563
////                                                              ////
2564
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2565
////                                                              ////
2566
//// This source file may be used and distributed without         ////
2567
//// restriction provided that this copyright statement is not    ////
2568
//// removed from the file and that any derivative work contains  ////
2569
//// the original copyright notice and the associated disclaimer. ////
2570
////                                                              ////
2571
//// This source file is free software; you can redistribute it   ////
2572
//// and/or modify it under the terms of the GNU Lesser General   ////
2573
//// Public License as published by the Free Software Foundation; ////
2574
//// either version 2.1 of the License, or (at your option) any   ////
2575
//// later version.                                               ////
2576
////                                                              ////
2577
//// This source is distributed in the hope that it will be       ////
2578
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2579
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2580
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2581
//// details.                                                     ////
2582
////                                                              ////
2583
//// You should have received a copy of the GNU Lesser General    ////
2584
//// Public License along with this source; if not, download it   ////
2585
//// from http://www.opencores.org/lgpl.shtml                     ////
2586
////                                                              ////
2587
//////////////////////////////////////////////////////////////////////
2588
 
2589
// LFSR counter
2590
 
2591 40 unneback
`define MODULE cnt_lfsr_ce_zq
2592
module `BASE`MODULE (
2593
`undef MODULE
2594
 cke, zq, rst, clk);
2595
 
2596 6 unneback
   parameter length = 4;
2597
   input cke;
2598
   output reg zq;
2599
   input rst;
2600
   input clk;
2601
 
2602
   parameter clear_value = 0;
2603
   parameter set_value = 1;
2604
   parameter wrap_value = 8;
2605
   parameter level1_value = 15;
2606
 
2607
   reg  [length:1] qi;
2608
   reg lfsr_fb;
2609
   wire [length:1] q_next;
2610
   reg [32:1] polynom;
2611
   integer i;
2612
 
2613
   always @ (qi)
2614
   begin
2615
        case (length)
2616
         2: polynom = 32'b11;                               // 0x3
2617
         3: polynom = 32'b110;                              // 0x6
2618
         4: polynom = 32'b1100;                             // 0xC
2619
         5: polynom = 32'b10100;                            // 0x14
2620
         6: polynom = 32'b110000;                           // 0x30
2621
         7: polynom = 32'b1100000;                          // 0x60
2622
         8: polynom = 32'b10111000;                         // 0xb8
2623
         9: polynom = 32'b100010000;                        // 0x110
2624
        10: polynom = 32'b1001000000;                       // 0x240
2625
        11: polynom = 32'b10100000000;                      // 0x500
2626
        12: polynom = 32'b100000101001;                     // 0x829
2627
        13: polynom = 32'b1000000001100;                    // 0x100C
2628
        14: polynom = 32'b10000000010101;                   // 0x2015
2629
        15: polynom = 32'b110000000000000;                  // 0x6000
2630
        16: polynom = 32'b1101000000001000;                 // 0xD008
2631
        17: polynom = 32'b10010000000000000;                // 0x12000
2632
        18: polynom = 32'b100000010000000000;               // 0x20400
2633
        19: polynom = 32'b1000000000000100011;              // 0x40023
2634 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2635 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2636
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2637
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2638
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2639
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2640
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2641
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2642
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2643
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2644
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2645
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2646
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2647
        default: polynom = 32'b0;
2648
        endcase
2649
        lfsr_fb = qi[length];
2650
        for (i=length-1; i>=1; i=i-1) begin
2651
            if (polynom[i])
2652
                lfsr_fb = lfsr_fb  ~^ qi[i];
2653
        end
2654
    end
2655
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2656
 
2657
   always @ (posedge clk or posedge rst)
2658
     if (rst)
2659
       qi <= {length{1'b0}};
2660
     else
2661
     if (cke)
2662
       qi <= q_next;
2663
 
2664
 
2665
 
2666
   always @ (posedge clk or posedge rst)
2667
     if (rst)
2668
       zq <= 1'b1;
2669
     else
2670
     if (cke)
2671
       zq <= q_next == {length{1'b0}};
2672
endmodule
2673 40 unneback
`endif
2674
`ifdef CNT_LFSR_CE_Q
2675 6 unneback
//////////////////////////////////////////////////////////////////////
2676
////                                                              ////
2677
////  Versatile counter                                           ////
2678
////                                                              ////
2679
////  Description                                                 ////
2680
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2681
////  counter                                                     ////
2682
////                                                              ////
2683
////  To Do:                                                      ////
2684
////   - add LFSR with more taps                                  ////
2685
////                                                              ////
2686
////  Author(s):                                                  ////
2687
////      - Michael Unneback, unneback@opencores.org              ////
2688
////        ORSoC AB                                              ////
2689
////                                                              ////
2690
//////////////////////////////////////////////////////////////////////
2691
////                                                              ////
2692
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2693
////                                                              ////
2694
//// This source file may be used and distributed without         ////
2695
//// restriction provided that this copyright statement is not    ////
2696
//// removed from the file and that any derivative work contains  ////
2697
//// the original copyright notice and the associated disclaimer. ////
2698
////                                                              ////
2699
//// This source file is free software; you can redistribute it   ////
2700
//// and/or modify it under the terms of the GNU Lesser General   ////
2701
//// Public License as published by the Free Software Foundation; ////
2702
//// either version 2.1 of the License, or (at your option) any   ////
2703
//// later version.                                               ////
2704
////                                                              ////
2705
//// This source is distributed in the hope that it will be       ////
2706
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2707
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2708
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2709
//// details.                                                     ////
2710
////                                                              ////
2711
//// You should have received a copy of the GNU Lesser General    ////
2712
//// Public License along with this source; if not, download it   ////
2713
//// from http://www.opencores.org/lgpl.shtml                     ////
2714
////                                                              ////
2715
//////////////////////////////////////////////////////////////////////
2716 22 unneback
 
2717
// LFSR counter
2718 27 unneback
 
2719 40 unneback
`define MODULE cnt_lfsr_ce_q
2720
module `BASE`MODULE (
2721
`undef MODULE
2722
 cke, q, rst, clk);
2723
 
2724 27 unneback
   parameter length = 4;
2725
   input cke;
2726
   output [length:1] q;
2727
   input rst;
2728
   input clk;
2729
 
2730
   parameter clear_value = 0;
2731
   parameter set_value = 1;
2732
   parameter wrap_value = 8;
2733
   parameter level1_value = 15;
2734
 
2735
   reg  [length:1] qi;
2736
   reg lfsr_fb;
2737
   wire [length:1] q_next;
2738
   reg [32:1] polynom;
2739
   integer i;
2740
 
2741
   always @ (qi)
2742
   begin
2743
        case (length)
2744
         2: polynom = 32'b11;                               // 0x3
2745
         3: polynom = 32'b110;                              // 0x6
2746
         4: polynom = 32'b1100;                             // 0xC
2747
         5: polynom = 32'b10100;                            // 0x14
2748
         6: polynom = 32'b110000;                           // 0x30
2749
         7: polynom = 32'b1100000;                          // 0x60
2750
         8: polynom = 32'b10111000;                         // 0xb8
2751
         9: polynom = 32'b100010000;                        // 0x110
2752
        10: polynom = 32'b1001000000;                       // 0x240
2753
        11: polynom = 32'b10100000000;                      // 0x500
2754
        12: polynom = 32'b100000101001;                     // 0x829
2755
        13: polynom = 32'b1000000001100;                    // 0x100C
2756
        14: polynom = 32'b10000000010101;                   // 0x2015
2757
        15: polynom = 32'b110000000000000;                  // 0x6000
2758
        16: polynom = 32'b1101000000001000;                 // 0xD008
2759
        17: polynom = 32'b10010000000000000;                // 0x12000
2760
        18: polynom = 32'b100000010000000000;               // 0x20400
2761
        19: polynom = 32'b1000000000000100011;              // 0x40023
2762 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2763 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2764
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2765
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2766
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2767
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2768
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2769
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2770
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2771
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2772
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2773
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2774
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2775
        default: polynom = 32'b0;
2776
        endcase
2777
        lfsr_fb = qi[length];
2778
        for (i=length-1; i>=1; i=i-1) begin
2779
            if (polynom[i])
2780
                lfsr_fb = lfsr_fb  ~^ qi[i];
2781
        end
2782
    end
2783
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2784
 
2785
   always @ (posedge clk or posedge rst)
2786
     if (rst)
2787
       qi <= {length{1'b0}};
2788
     else
2789
     if (cke)
2790
       qi <= q_next;
2791
 
2792
   assign q = qi;
2793
 
2794
endmodule
2795 40 unneback
`endif
2796
`ifdef CNT_LFSR_CE_CLEAR_Q
2797 27 unneback
//////////////////////////////////////////////////////////////////////
2798
////                                                              ////
2799
////  Versatile counter                                           ////
2800
////                                                              ////
2801
////  Description                                                 ////
2802
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2803
////  counter                                                     ////
2804
////                                                              ////
2805
////  To Do:                                                      ////
2806
////   - add LFSR with more taps                                  ////
2807
////                                                              ////
2808
////  Author(s):                                                  ////
2809
////      - Michael Unneback, unneback@opencores.org              ////
2810
////        ORSoC AB                                              ////
2811
////                                                              ////
2812
//////////////////////////////////////////////////////////////////////
2813
////                                                              ////
2814