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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 75

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 40 unneback 
`ifdef ALL
14 
 
15 
`define GBUF
16 
`define SYNC_RST
17 
`define PLL
18 
 
19 
`define MULTS
20 
`define MULTS18X18
21 
`define MULT
22 
`define SHIFT_UNIT_32
23 
`define LOGIC_UNIT
24 
 
25 
`define CNT_SHREG_WRAP
26 
`define CNT_SHREG_CE_WRAP
27 
`define CNT_SHREG_CE_CLEAR
28 
`define CNT_SHREG_CE_CLEAR_WRAP
29 
 
30 
`define MUX_ANDOR
31 
`define MUX2_ANDOR
32 
`define MUX3_ANDOR
33 
`define MUX4_ANDOR
34 
`define MUX5_ANDOR
35 
`define MUX6_ANDOR
36 43 unneback 
`define PARITY
37 40 unneback 
 
38 
`define ROM_INIT
39 
`define RAM
40 
`define RAM_BE
41 
`define DPRAM_1R1W
42 
`define DPRAM_2R1W
43 
`define DPRAM_2R2W
44 75 unneback 
`define DPRAM_BE_2R2W
45 40 unneback 
`define FIFO_1R1W_FILL_LEVEL_SYNC
46 
`define FIFO_2R2W_SYNC_SIMPLEX
47 
`define FIFO_CMP_ASYNC
48 
`define FIFO_1R1W_ASYNC
49 
`define FIFO_2R2W_ASYNC
50 
`define FIFO_2R2W_ASYNC_SIMPLEX
51 48 unneback 
`define REG_FILE
52 40 unneback 
 
53 
`define DFF
54 
`define DFF_ARRAY
55 
`define DFF_CE
56 
`define DFF_CE_CLEAR
57 
`define DF_CE_SET
58 
`define SPR
59 
`define SRP
60 
`define DFF_SR
61 
`define LATCH
62 
`define SHREG
63 
`define SHREG_CE
64 
`define DELAY
65 
`define DELAY_EMPTYFLAG
66 
 
67 75 unneback 
`define WB3AVALON_BRIDGE
68 40 unneback 
`define WB3WB3_BRIDGE
69 
`define WB3_ARBITER_TYPE1
70 59 unneback 
`define WB_B3_RAM_BE
71 49 unneback 
`define WB_B4_RAM_BE
72 48 unneback 
`define WB_B4_ROM
73 40 unneback 
`define WB_BOOT_ROM
74 
`define WB_DPRAM
75 
 
76 44 unneback 
`define IO_DFF_OE
77 
`define O_DFF
78 
 
79 40 unneback 
`endif
80 
 
81 
`ifdef PLL
82 
`ifndef SYNC_RST
83 
`define SYNC_RST
84 
`endif
85 
`endif
86 
 
87 
`ifdef SYNC_RST
88 
`ifndef GBUF
89 
`define GBUF
90 
`endif
91 
`endif
92 
 
93 
`ifdef WB_DPRAM
94 
`ifndef DPRAM_2R2W
95 
`define DPRAM_2R2W
96 
`endif
97 
`ifndef SPR
98 
`define SPR
99 
`endif
100 
`endif
101 
 
102 62 unneback 
`ifdef WB_B3_RAM_BE
103 
`ifndef WB3_ARBITER_TYPE1
104 
`define WB3_ARBITER_TYPE1
105 
`endif
106 
`ifndef RAM_BE
107 
`define RAM_BE
108 
`endif
109 
`endif
110 
 
111 40 unneback 
`ifdef WB3_ARBITER_TYPE1
112 42 unneback 
`ifndef SPR
113 
`define SPR
114 
`endif
115 40 unneback 
`ifndef MUX_ANDOR
116 
`define MUX_ANDOR
117 
`endif
118 
`endif
119 
 
120 
`ifdef WB3WB3_BRIDGE
121 
`ifndef CNT_SHREG_CE_CLEAR
122 
`define CNT_SHREG_CE_CLEAR
123 
`endif
124 
`ifndef DFF
125 
`define DFF
126 
`endif
127 
`ifndef DFF_CE
128 
`define DFF_CE
129 
`endif
130 
`ifndef CNT_SHREG_CE_CLEAR
131 
`define CNT_SHREG_CE_CLEAR
132 
`endif
133 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
134 
`define FIFO_2R2W_ASYNC_SIMPLEX
135 
`endif
136 
`endif
137 
 
138 
`ifdef MULTS18X18
139 
`ifndef MULTS
140 
`define MULTS
141 
`endif
142 
`endif
143 
 
144 
`ifdef SHIFT_UNIT_32
145 
`ifndef MULTS
146 
`define MULTS
147 
`endif
148 
`endif
149 
 
150 
`ifdef MUX2_ANDOR
151 
`ifndef MUX_ANDOR
152 
`define MUX_ANDOR
153 
`endif
154 
`endif
155 
 
156 
`ifdef MUX3_ANDOR
157 
`ifndef MUX_ANDOR
158 
`define MUX_ANDOR
159 
`endif
160 
`endif
161 
 
162 
`ifdef MUX4_ANDOR
163 
`ifndef MUX_ANDOR
164 
`define MUX_ANDOR
165 
`endif
166 
`endif
167 
 
168 
`ifdef MUX5_ANDOR
169 
`ifndef MUX_ANDOR
170 
`define MUX_ANDOR
171 
`endif
172 
`endif
173 
 
174 
`ifdef MUX6_ANDOR
175 
`ifndef MUX_ANDOR
176 
`define MUX_ANDOR
177 
`endif
178 
`endif
179 
 
180 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
181 
`ifndef CNT_BIN_CE
182 
`define CNT_BIN_CE
183 
`endif
184 
`ifndef DPRAM_1R1W
185 
`define DPRAM_1R1W
186 
`endif
187 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
188 
`define CNT_BIN_CE_REW_Q_ZQ_L1
189 
`endif
190 
`endif
191 
 
192 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
193 
`ifndef CNT_LFSR_CE
194 
`define CNT_LFSR_CE
195 
`endif
196 
`ifndef DPRAM_2R2W
197 
`define DPRAM_2R2W
198 
`endif
199 
`ifndef CNT_BIN_CE_REW_ZQ_L1
200 
`define CNT_BIN_CE_REW_ZQ_L1
201 
`endif
202 
`endif
203 
 
204 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
205 
`ifndef CNT_GRAY_CE_BIN
206 
`define CNT_GRAY_CE_BIN
207 
`endif
208 
`ifndef DPRAM_2R2W
209 
`define DPRAM_2R2W
210 
`endif
211 
`ifndef FIFO_CMP_ASYNC
212 
`define FIFO_CMP_ASYNC
213 
`endif
214 
`endif
215 
 
216 
`ifdef FIFO_2R2W_ASYNC
217 
`ifndef FIFO_1R1W_ASYNC
218 
`define FIFO_1R1W_ASYNC
219 
`endif
220 
`endif
221 
 
222 
`ifdef FIFO_1R1W_ASYNC
223 
`ifndef CNT_GRAY_CE_BIN
224 
`define CNT_GRAY_CE_BIN
225 
`endif
226 
`ifndef DPRAM_1R1W
227 
`define DPRAM_1R1W
228 
`endif
229 
`ifndef FIFO_CMP_ASYNC
230 
`define FIFO_CMP_ASYNC
231 
`endif
232 
`endif
233 
 
234 
`ifdef FIFO_CMP_ASYNC
235 
`ifndef DFF_SR
236 
`define DFF_SR
237 
`endif
238 
`ifndef DFF
239 
`define DFF
240 
`endif
241 
`endif
242 48 unneback 
 
243 
`ifdef REG_FILE
244 
`ifndef DPRAM_1R1W
245 
`define DPRAM_1R1W
246 
`endif
247 
`endif
248 62 unneback 
//////////////////////////////////////////////////////////////////////
249 6 unneback 
////                                                              ////
250 
////  Versatile library, clock and reset                          ////
251 
////                                                              ////
252 
////  Description                                                 ////
253 
////  Logic related to clock and reset                            ////
254 
////                                                              ////
255 
////                                                              ////
256 
////  To Do:                                                      ////
257 
////   - add more different registers                             ////
258 
////                                                              ////
259 
////  Author(s):                                                  ////
260 
////      - Michael Unneback, unneback@opencores.org              ////
261 
////        ORSoC AB                                              ////
262 
////                                                              ////
263 
//////////////////////////////////////////////////////////////////////
264 
////                                                              ////
265 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
266 
////                                                              ////
267 
//// This source file may be used and distributed without         ////
268 
//// restriction provided that this copyright statement is not    ////
269 
//// removed from the file and that any derivative work contains  ////
270 
//// the original copyright notice and the associated disclaimer. ////
271 
////                                                              ////
272 
//// This source file is free software; you can redistribute it   ////
273 
//// and/or modify it under the terms of the GNU Lesser General   ////
274 
//// Public License as published by the Free Software Foundation; ////
275 
//// either version 2.1 of the License, or (at your option) any   ////
276 
//// later version.                                               ////
277 
////                                                              ////
278 
//// This source is distributed in the hope that it will be       ////
279 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
280 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
281 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
282 
//// details.                                                     ////
283 
////                                                              ////
284 
//// You should have received a copy of the GNU Lesser General    ////
285 
//// Public License along with this source; if not, download it   ////
286 
//// from http://www.opencores.org/lgpl.shtml                     ////
287 
////                                                              ////
288 
//////////////////////////////////////////////////////////////////////
289 
 
290 48 unneback 
`ifdef ACTEL
291 
`ifdef GBUF
292 
`timescale 1 ns/100 ps
293 6 unneback 
// Global buffer
294 
// usage:
295 
// use to enable global buffers for high fan out signals such as clock and reset
296 
// Version: 8.4 8.4.0.33
297 
module gbuf(GL,CLK);
298 
output GL;
299 
input  CLK;
300 
 
301 
    wire GND;
302 
 
303 
    GND GND_1_net(.Y(GND));
304 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
305 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
306 
 
307 
endmodule
308 
`timescale 1 ns/1 ns
309 40 unneback 
`define MODULE gbuf
310 
module `BASE`MODULE ( i, o);
311 
`undef MODULE
312 6 unneback 
input i;
313 
output o;
314 
`ifdef SIM_GBUF
315 
assign o=i;
316 
`else
317 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
318 
`endif
319 
endmodule
320 40 unneback 
`endif
321 33 unneback 
 
322 6 unneback 
`else
323 33 unneback 
 
324 40 unneback 
`ifdef ALTERA
325 
`ifdef GBUF
326 21 unneback 
//altera
327 40 unneback 
`define MODULE gbuf
328 
module `BASE`MODULE ( i, o);
329 
`undef MODULE
330 33 unneback 
input i;
331 
output o;
332 
assign o = i;
333 
endmodule
334 40 unneback 
`endif
335 33 unneback 
 
336 6 unneback 
`else
337 
 
338 40 unneback 
`ifdef GBUF
339 6 unneback 
`timescale 1 ns/100 ps
340 40 unneback 
`define MODULE
341 
module `BASE`MODULE ( i, o);
342 
`undef MODULE
343 6 unneback 
input i;
344 
output o;
345 
assign o = i;
346 
endmodule
347 40 unneback 
`endif
348 6 unneback 
`endif // ALTERA
349 
`endif //ACTEL
350 
 
351 40 unneback 
`ifdef SYNC_RST
352 6 unneback 
// sync reset
353 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
354 6 unneback 
// output active high global reset sync with two DFFs
355 
`timescale 1 ns/100 ps
356 40 unneback 
`define MODULE sync_rst
357 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
358 
`undef MODULE
359 6 unneback 
input rst_n_i, clk;
360 
output rst_o;
361 18 unneback 
reg [1:0] tmp;
362 6 unneback 
always @ (posedge clk or negedge rst_n_i)
363 
if (!rst_n_i)
364 17 unneback 
        tmp <= 2'b11;
365 6 unneback 
else
366 33 unneback 
        tmp <= {1'b0,tmp[1]};
367 40 unneback 
`define MODULE gbuf
368 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
369 
`undef MODULE
370 6 unneback 
endmodule
371 40 unneback 
`endif
372 6 unneback 
 
373 40 unneback 
`ifdef PLL
374 6 unneback 
// vl_pll
375 
`ifdef ACTEL
376 32 unneback 
///////////////////////////////////////////////////////////////////////////////
377 17 unneback 
`timescale 1 ps/1 ps
378 40 unneback 
`define MODULE pll
379 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
380 
`undef MODULE
381 6 unneback 
parameter index = 0;
382 
parameter number_of_clk = 1;
383 17 unneback 
parameter period_time_0 = 20000;
384 
parameter period_time_1 = 20000;
385 
parameter period_time_2 = 20000;
386 
parameter lock_delay = 2000000;
387 6 unneback 
input clk_i, rst_n_i;
388 
output lock;
389 
output reg [0:number_of_clk-1] clk_o;
390 
output [0:number_of_clk-1] rst_o;
391 
 
392 
`ifdef SIM_PLL
393 
 
394 
always
395 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
396 
 
397 
generate if (number_of_clk > 1)
398 
always
399 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
400 
endgenerate
401 
 
402 
generate if (number_of_clk > 2)
403 
always
404 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
405 
endgenerate
406 
 
407 
genvar i;
408 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
409 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
410 
end
411 
endgenerate
412 
 
413 
assign #lock_delay lock = rst_n_i;
414 
 
415 
endmodule
416 
`else
417 
generate if (number_of_clk==1 & index==0) begin
418 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
419 
end
420 
endgenerate // index==0
421 
generate if (number_of_clk==1 & index==1) begin
422 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
423 
end
424 
endgenerate // index==1
425 
generate if (number_of_clk==1 & index==2) begin
426 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
427 
end
428 
endgenerate // index==2
429 
generate if (number_of_clk==1 & index==3) begin
430 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
431 
end
432 
endgenerate // index==0
433 
 
434 
generate if (number_of_clk==2 & index==0) begin
435 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
436 
end
437 
endgenerate // index==0
438 
generate if (number_of_clk==2 & index==1) begin
439 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
440 
end
441 
endgenerate // index==1
442 
generate if (number_of_clk==2 & index==2) begin
443 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
444 
end
445 
endgenerate // index==2
446 
generate if (number_of_clk==2 & index==3) begin
447 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
448 
end
449 
endgenerate // index==0
450 
 
451 
generate if (number_of_clk==3 & index==0) begin
452 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
453 
end
454 
endgenerate // index==0
455 
generate if (number_of_clk==3 & index==1) begin
456 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
457 
end
458 
endgenerate // index==1
459 
generate if (number_of_clk==3 & index==2) begin
460 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
461 
end
462 
endgenerate // index==2
463 
generate if (number_of_clk==3 & index==3) begin
464 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
465 
end
466 
endgenerate // index==0
467 
 
468 
genvar i;
469 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
470 40 unneback 
`define MODULE sync_rst
471 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
472 
`undef MODULE
473 6 unneback 
end
474 
endgenerate
475 
endmodule
476 
`endif
477 32 unneback 
///////////////////////////////////////////////////////////////////////////////
478 6 unneback 
 
479 
`else
480 
 
481 32 unneback 
///////////////////////////////////////////////////////////////////////////////
482 6 unneback 
`ifdef ALTERA
483 
 
484 32 unneback 
`timescale 1 ps/1 ps
485 40 unneback 
`define MODULE pll
486 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
487 
`undef MODULE
488 32 unneback 
parameter index = 0;
489 
parameter number_of_clk = 1;
490 
parameter period_time_0 = 20000;
491 
parameter period_time_1 = 20000;
492 
parameter period_time_2 = 20000;
493 
parameter period_time_3 = 20000;
494 
parameter period_time_4 = 20000;
495 
parameter lock_delay = 2000000;
496 
input clk_i, rst_n_i;
497 
output lock;
498 
output reg [0:number_of_clk-1] clk_o;
499 
output [0:number_of_clk-1] rst_o;
500 
 
501 
`ifdef SIM_PLL
502 
 
503 
always
504 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
505 
 
506 
generate if (number_of_clk > 1)
507 
always
508 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
509 
endgenerate
510 
 
511 
generate if (number_of_clk > 2)
512 
always
513 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
514 
endgenerate
515 
 
516 33 unneback 
generate if (number_of_clk > 3)
517 32 unneback 
always
518 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
519 
endgenerate
520 
 
521 33 unneback 
generate if (number_of_clk > 4)
522 32 unneback 
always
523 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
524 
endgenerate
525 
 
526 
genvar i;
527 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
528 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
529 
end
530 
endgenerate
531 
 
532 33 unneback 
//assign #lock_delay lock = rst_n_i;
533 
assign lock = rst_n_i;
534 32 unneback 
 
535 
endmodule
536 6 unneback 
`else
537 
 
538 33 unneback 
`ifdef VL_PLL0
539 
`ifdef VL_PLL0_CLK1
540 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
541 
`endif
542 
`ifdef VL_PLL0_CLK2
543 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
544 
`endif
545 
`ifdef VL_PLL0_CLK3
546 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
547 
`endif
548 
`ifdef VL_PLL0_CLK4
549 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
550 
`endif
551 
`ifdef VL_PLL0_CLK5
552 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
553 
`endif
554 
`endif
555 32 unneback 
 
556 33 unneback 
`ifdef VL_PLL1
557 
`ifdef VL_PLL1_CLK1
558 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
559 
`endif
560 
`ifdef VL_PLL1_CLK2
561 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
562 
`endif
563 
`ifdef VL_PLL1_CLK3
564 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
565 
`endif
566 
`ifdef VL_PLL1_CLK4
567 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
568 
`endif
569 
`ifdef VL_PLL1_CLK5
570 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
571 
`endif
572 
`endif
573 32 unneback 
 
574 33 unneback 
`ifdef VL_PLL2
575 
`ifdef VL_PLL2_CLK1
576 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
577 
`endif
578 
`ifdef VL_PLL2_CLK2
579 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
580 
`endif
581 
`ifdef VL_PLL2_CLK3
582 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
583 
`endif
584 
`ifdef VL_PLL2_CLK4
585 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
586 
`endif
587 
`ifdef VL_PLL2_CLK5
588 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
589 
`endif
590 
`endif
591 32 unneback 
 
592 33 unneback 
`ifdef VL_PLL3
593 
`ifdef VL_PLL3_CLK1
594 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
595 
`endif
596 
`ifdef VL_PLL3_CLK2
597 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
598 
`endif
599 
`ifdef VL_PLL3_CLK3
600 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
601 
`endif
602 
`ifdef VL_PLL3_CLK4
603 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
604 
`endif
605 
`ifdef VL_PLL3_CLK5
606 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
607 
`endif
608 
`endif
609 32 unneback 
 
610 
genvar i;
611 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
612 40 unneback 
`define MODULE sync_rst
613 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
614 
`undef MODULE
615 32 unneback 
end
616 
endgenerate
617 
endmodule
618 
`endif
619 
///////////////////////////////////////////////////////////////////////////////
620 
 
621 
`else
622 
 
623 6 unneback 
// generic PLL
624 17 unneback 
`timescale 1 ps/1 ps
625 40 unneback 
`define MODULE pll
626 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
627 
`undef MODULE
628 6 unneback 
parameter index = 0;
629 
parameter number_of_clk = 1;
630 17 unneback 
parameter period_time_0 = 20000;
631 
parameter period_time_1 = 20000;
632 
parameter period_time_2 = 20000;
633 6 unneback 
parameter lock_delay = 2000;
634 
input clk_i, rst_n_i;
635 
output lock;
636 
output reg [0:number_of_clk-1] clk_o;
637 
output [0:number_of_clk-1] rst_o;
638 
 
639 
always
640 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
641 
 
642 
generate if (number_of_clk > 1)
643 
always
644 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
645 
endgenerate
646 
 
647 
generate if (number_of_clk > 2)
648 
always
649 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
650 
endgenerate
651 
 
652 
genvar i;
653 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
654 40 unneback 
`define MODULE sync_rst
655 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
656 
`undef MODULE
657 6 unneback 
end
658 
endgenerate
659 
 
660 
assign #lock_delay lock = rst_n_i;
661 
 
662 
endmodule
663 
 
664 
`endif //altera
665 17 unneback 
`endif //actel
666 40 unneback 
`undef MODULE
667 
`endif//////////////////////////////////////////////////////////////////////
668 6 unneback 
////                                                              ////
669 
////  Versatile library, registers                                ////
670 
////                                                              ////
671 
////  Description                                                 ////
672 
////  Different type of registers                                 ////
673 
////                                                              ////
674 
////                                                              ////
675 
////  To Do:                                                      ////
676 
////   - add more different registers                             ////
677 
////                                                              ////
678 
////  Author(s):                                                  ////
679 
////      - Michael Unneback, unneback@opencores.org              ////
680 
////        ORSoC AB                                              ////
681 
////                                                              ////
682 
//////////////////////////////////////////////////////////////////////
683 
////                                                              ////
684 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
685 
////                                                              ////
686 
//// This source file may be used and distributed without         ////
687 
//// restriction provided that this copyright statement is not    ////
688 
//// removed from the file and that any derivative work contains  ////
689 
//// the original copyright notice and the associated disclaimer. ////
690 
////                                                              ////
691 
//// This source file is free software; you can redistribute it   ////
692 
//// and/or modify it under the terms of the GNU Lesser General   ////
693 
//// Public License as published by the Free Software Foundation; ////
694 
//// either version 2.1 of the License, or (at your option) any   ////
695 
//// later version.                                               ////
696 
////                                                              ////
697 
//// This source is distributed in the hope that it will be       ////
698 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
699 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
700 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
701 
//// details.                                                     ////
702 
////                                                              ////
703 
//// You should have received a copy of the GNU Lesser General    ////
704 
//// Public License along with this source; if not, download it   ////
705 
//// from http://www.opencores.org/lgpl.shtml                     ////
706 
////                                                              ////
707 
//////////////////////////////////////////////////////////////////////
708 
 
709 40 unneback 
`ifdef DFF
710 
`define MODULE dff
711 
module `BASE`MODULE ( d, q, clk, rst);
712 
`undef MODULE
713 6 unneback 
        parameter width = 1;
714 
        parameter reset_value = 0;
715 
 
716 
        input [width-1:0] d;
717 
        input clk, rst;
718 
        output reg [width-1:0] q;
719 
 
720 
        always @ (posedge clk or posedge rst)
721 
        if (rst)
722 
                q <= reset_value;
723 
        else
724 
                q <= d;
725 
 
726 
endmodule
727 40 unneback 
`endif
728 6 unneback 
 
729 40 unneback 
`ifdef DFF_ARRAY
730 
`define MODULE dff_array
731 
module `BASE`MODULE ( d, q, clk, rst);
732 
`undef MODULE
733 6 unneback 
 
734 
        parameter width = 1;
735 
        parameter depth = 2;
736 
        parameter reset_value = 1'b0;
737 
 
738 
        input [width-1:0] d;
739 
        input clk, rst;
740 
        output [width-1:0] q;
741 
        reg  [0:depth-1] q_tmp [width-1:0];
742 
        integer i;
743 
        always @ (posedge clk or posedge rst)
744 
        if (rst) begin
745 
            for (i=0;i<depth;i=i+1)
746 
                q_tmp[i] <= {width{reset_value}};
747 
        end else begin
748 
            q_tmp[0] <= d;
749 
            for (i=1;i<depth;i=i+1)
750 
                q_tmp[i] <= q_tmp[i-1];
751 
        end
752 
 
753 
    assign q = q_tmp[depth-1];
754 
 
755 
endmodule
756 40 unneback 
`endif
757 6 unneback 
 
758 40 unneback 
`ifdef DFF_CE
759 
`define MODULE dff_ce
760 
module `BASE`MODULE ( d, ce, q, clk, rst);
761 
`undef MODULE
762 6 unneback 
 
763 
        parameter width = 1;
764 
        parameter reset_value = 0;
765 
 
766 
        input [width-1:0] d;
767 
        input ce, clk, rst;
768 
        output reg [width-1:0] q;
769 
 
770 
        always @ (posedge clk or posedge rst)
771 
        if (rst)
772 
                q <= reset_value;
773 
        else
774 
                if (ce)
775 
                        q <= d;
776 
 
777 
endmodule
778 40 unneback 
`endif
779 6 unneback 
 
780 40 unneback 
`ifdef DFF_CE_CLEAR
781 
`define MODULE dff_ce_clear
782 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
783 
`undef MODULE
784 8 unneback 
 
785 
        parameter width = 1;
786 
        parameter reset_value = 0;
787 
 
788 
        input [width-1:0] d;
789 10 unneback 
        input ce, clear, clk, rst;
790 8 unneback 
        output reg [width-1:0] q;
791 
 
792 
        always @ (posedge clk or posedge rst)
793 
        if (rst)
794 
            q <= reset_value;
795 
        else
796 
            if (ce)
797 
                if (clear)
798 
                    q <= {width{1'b0}};
799 
                else
800 
                    q <= d;
801 
 
802 
endmodule
803 40 unneback 
`endif
804 8 unneback 
 
805 40 unneback 
`ifdef DF_CE_SET
806 
`define MODULE dff_ce_set
807 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
808 
`undef MODULE
809 24 unneback 
 
810 
        parameter width = 1;
811 
        parameter reset_value = 0;
812 
 
813 
        input [width-1:0] d;
814 
        input ce, set, clk, rst;
815 
        output reg [width-1:0] q;
816 
 
817 
        always @ (posedge clk or posedge rst)
818 
        if (rst)
819 
            q <= reset_value;
820 
        else
821 
            if (ce)
822 
                if (set)
823 
                    q <= {width{1'b1}};
824 
                else
825 
                    q <= d;
826 
 
827 
endmodule
828 40 unneback 
`endif
829 24 unneback 
 
830 40 unneback 
`ifdef SPR
831 
`define MODULE spr
832 
module `BASE`MODULE ( sp, r, q, clk, rst);
833 
`undef MODULE
834 
 
835 64 unneback 
        //parameter width = 1;
836 
        parameter reset_value = 1'b0;
837 29 unneback 
 
838 
        input sp, r;
839 
        output reg q;
840 
        input clk, rst;
841 
 
842 
        always @ (posedge clk or posedge rst)
843 
        if (rst)
844 
            q <= reset_value;
845 
        else
846 
            if (sp)
847 
                q <= 1'b1;
848 
            else if (r)
849 
                q <= 1'b0;
850 
 
851 
endmodule
852 40 unneback 
`endif
853 29 unneback 
 
854 40 unneback 
`ifdef SRP
855 
`define MODULE srp
856 
module `BASE`MODULE ( s, rp, q, clk, rst);
857 
`undef MODULE
858 
 
859 29 unneback 
        parameter width = 1;
860 
        parameter reset_value = 0;
861 
 
862 
        input s, rp;
863 
        output reg q;
864 
        input clk, rst;
865 
 
866 
        always @ (posedge clk or posedge rst)
867 
        if (rst)
868 
            q <= reset_value;
869 
        else
870 
            if (rp)
871 
                q <= 1'b0;
872 
            else if (s)
873 
                q <= 1'b1;
874 
 
875 
endmodule
876 40 unneback 
`endif
877 29 unneback 
 
878 40 unneback 
`ifdef ALTERA
879 29 unneback 
 
880 40 unneback 
`ifdef DFF_SR
881 6 unneback 
// megafunction wizard: %LPM_FF%
882 
// GENERATION: STANDARD
883 
// VERSION: WM1.0
884 
// MODULE: lpm_ff
885 
 
886 
// ============================================================
887 
// File Name: dff_sr.v
888 
// Megafunction Name(s):
889 
//                      lpm_ff
890 
//
891 
// Simulation Library Files(s):
892 
//                      lpm
893 
// ============================================================
894 
// ************************************************************
895 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
896 
//
897 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
898 
// ************************************************************
899 
 
900 
 
901 
//Copyright (C) 1991-2010 Altera Corporation
902 
//Your use of Altera Corporation's design tools, logic functions
903 
//and other software and tools, and its AMPP partner logic
904 
//functions, and any output files from any of the foregoing
905 
//(including device programming or simulation files), and any
906 
//associated documentation or information are expressly subject
907 
//to the terms and conditions of the Altera Program License
908 
//Subscription Agreement, Altera MegaCore Function License
909 
//Agreement, or other applicable license agreement, including,
910 
//without limitation, that your use is for the sole purpose of
911 
//programming logic devices manufactured by Altera and sold by
912 
//Altera or its authorized distributors.  Please refer to the
913 
//applicable agreement for further details.
914 
 
915 
 
916 
// synopsys translate_off
917 
`timescale 1 ps / 1 ps
918 
// synopsys translate_on
919 40 unneback 
`define MODULE dff_sr
920 
module `BASE`MODULE (
921 
`undef MODULE
922 
 
923 6 unneback 
        aclr,
924 
        aset,
925 
        clock,
926 
        data,
927 
        q);
928 
 
929 
        input     aclr;
930 
        input     aset;
931 
        input     clock;
932 
        input     data;
933 
        output    q;
934 
 
935 
        wire [0:0] sub_wire0;
936 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
937 
        wire  q = sub_wire1;
938 
        wire  sub_wire2 = data;
939 
        wire  sub_wire3 = sub_wire2;
940 
 
941 
        lpm_ff  lpm_ff_component (
942 
                                .aclr (aclr),
943 
                                .clock (clock),
944 
                                .data (sub_wire3),
945 
                                .aset (aset),
946 
                                .q (sub_wire0)
947 
                                // synopsys translate_off
948 
                                ,
949 
                                .aload (),
950 
                                .enable (),
951 
                                .sclr (),
952 
                                .sload (),
953 
                                .sset ()
954 
                                // synopsys translate_on
955 
                                );
956 
        defparam
957 
                lpm_ff_component.lpm_fftype = "DFF",
958 
                lpm_ff_component.lpm_type = "LPM_FF",
959 
                lpm_ff_component.lpm_width = 1;
960 
 
961 
 
962 
endmodule
963 
 
964 
// ============================================================
965 
// CNX file retrieval info
966 
// ============================================================
967 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
968 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
969 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
970 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
971 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
972 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
973 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
974 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
975 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
976 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
977 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
978 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
979 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
980 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
981 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
982 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
983 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
984 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
985 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
986 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
987 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
988 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
989 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
990 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
991 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
992 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
993 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
994 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
995 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
996 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
997 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
998 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
999 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1000 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1001 
// Retrieval info: LIB_FILE: lpm
1002 40 unneback 
`endif
1003 6 unneback 
 
1004 
`else
1005 
 
1006 40 unneback 
`ifdef DFF_SR
1007 
`define MODULE dff_sr
1008 
module `BASE`MODULE ( aclr, aset, clock, data, q);
1009 
`undef MODULE
1010 6 unneback 
 
1011 
    input         aclr;
1012 
    input         aset;
1013 
    input         clock;
1014 
    input         data;
1015 
    output reg    q;
1016 
 
1017 
   always @ (posedge clock or posedge aclr or posedge aset)
1018 
     if (aclr)
1019 
       q <= 1'b0;
1020 
     else if (aset)
1021 
       q <= 1'b1;
1022 
     else
1023 
       q <= data;
1024 
 
1025 
endmodule
1026 40 unneback 
`endif
1027 6 unneback 
 
1028 
`endif
1029 
 
1030 
// LATCH
1031 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1032 
`ifdef ALTERA
1033 40 unneback 
 
1034 
`ifdef LATCH
1035 
`define MODULE latch
1036 
module `BASE`MODULE ( d, le, q, clk);
1037 
`undef MODULE
1038 6 unneback 
input d, le;
1039 
output q;
1040 
input clk;
1041 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1042 
endmodule
1043 40 unneback 
`endif
1044 
 
1045 6 unneback 
`else
1046 40 unneback 
 
1047 
`ifdef LATCH
1048 
`define MODULE latch
1049 
module `BASE`MODULE ( d, le, q, clk);
1050 
`undef MODULE
1051 6 unneback 
input d, le;
1052 48 unneback 
input clk;
1053 
always @ (le or d)
1054 60 unneback 
if (le)
1055 48 unneback 
    d <= q;
1056 6 unneback 
endmodule
1057 15 unneback 
`endif
1058 
 
1059 40 unneback 
`endif
1060 
 
1061 
`ifdef SHREG
1062 
`define MODULE shreg
1063 
module `BASE`MODULE ( d, q, clk, rst);
1064 
`undef MODULE
1065 
 
1066 17 unneback 
parameter depth = 10;
1067 
input d;
1068 
output q;
1069 
input clk, rst;
1070 
 
1071 
reg [1:depth] dffs;
1072 
 
1073 
always @ (posedge clk or posedge rst)
1074 
if (rst)
1075 
    dffs <= {depth{1'b0}};
1076 
else
1077 
    dffs <= {d,dffs[1:depth-1]};
1078 
assign q = dffs[depth];
1079 
endmodule
1080 40 unneback 
`endif
1081 17 unneback 
 
1082 40 unneback 
`ifdef SHREG_CE
1083 
`define MODULE shreg_ce
1084 
module `BASE`MODULE ( d, ce, q, clk, rst);
1085 
`undef MODULE
1086 17 unneback 
parameter depth = 10;
1087 
input d, ce;
1088 
output q;
1089 
input clk, rst;
1090 
 
1091 
reg [1:depth] dffs;
1092 
 
1093 
always @ (posedge clk or posedge rst)
1094 
if (rst)
1095 
    dffs <= {depth{1'b0}};
1096 
else
1097 
    if (ce)
1098 
        dffs <= {d,dffs[1:depth-1]};
1099 
assign q = dffs[depth];
1100 
endmodule
1101 40 unneback 
`endif
1102 17 unneback 
 
1103 40 unneback 
`ifdef DELAY
1104 
`define MODULE delay
1105 
module `BASE`MODULE ( d, q, clk, rst);
1106 
`undef MODULE
1107 15 unneback 
parameter depth = 10;
1108 
input d;
1109 
output q;
1110 
input clk, rst;
1111 
 
1112 
reg [1:depth] dffs;
1113 
 
1114 
always @ (posedge clk or posedge rst)
1115 
if (rst)
1116 
    dffs <= {depth{1'b0}};
1117 
else
1118 
    dffs <= {d,dffs[1:depth-1]};
1119 
assign q = dffs[depth];
1120 17 unneback 
endmodule
1121 40 unneback 
`endif
1122 17 unneback 
 
1123 40 unneback 
`ifdef DELAY_EMPTYFLAG
1124 
`define MODULE delay_emptyflag
1125 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1126 40 unneback 
`undef MODULE
1127 17 unneback 
parameter depth = 10;
1128 
input d;
1129 
output q, emptyflag;
1130 
input clk, rst;
1131 
 
1132 
reg [1:depth] dffs;
1133 
 
1134 
always @ (posedge clk or posedge rst)
1135 
if (rst)
1136 
    dffs <= {depth{1'b0}};
1137 
else
1138 
    dffs <= {d,dffs[1:depth-1]};
1139 
assign q = dffs[depth];
1140 
assign emptyflag = !(|dffs);
1141 
endmodule
1142 40 unneback 
`endif
1143 75 unneback 
 
1144 
`ifdef ASYNC_REG_REQ_ACK
1145 
`define MODULE async_reg_req_ack
1146 
module `BASE`MODULE ( d, q, req_i, req_o, ack_i, ack_o, clk_a, rst_a, clk_b, rst_b);
1147 
`undef MODULE
1148 
parameter data_width = 8;
1149 
input [data_width-1:0] d;
1150 
output [data_width-1:0] q;
1151 
input req_i;
1152 
output req_o;
1153 
input ack_i;
1154 
output ack_o;
1155 
input clk_a, rst_a, clk_b, rst_b;
1156 
 
1157 
reg [3:0] reqi; // 3: last req in clk_a, 2: input dff, 1-0: sync
1158 
wire rst;
1159 
 
1160 
always @ (posedge clk_a or rst_a)
1161 
if (rst_a)
1162 
    q <= {data_width{1'b0}};
1163 
else
1164 
    if (req_i)
1165 
        q <= d;
1166 
 
1167 
assign rst = ack_i | rst_a;
1168 
always @ (posedge clk_a or posedge rst)
1169 
if (rst)
1170 
    req[2] <= 1'b0;
1171 
else
1172 
    req[2] <= req_i & !ack_o;
1173 
 
1174 
always @ (posedge clk_a or posedge rst_a)
1175 
if (rst_a)
1176 
    req[3] <= 1'b0;
1177 
else
1178 
    req[3] <= req[2];
1179 
 
1180 
always @ (posedge clk_b or posedge rst_b)
1181 
if (rst_b)
1182 
    req[1:0] <= 2'b00;
1183 
else
1184 
    if (ack_i)
1185 
        req[1:0] <= 2'b00;
1186 
    else
1187 
        req[1:0] <= req[2:1];
1188 
assign req_o = req[0];
1189 
 
1190 
always @ (posedge clk_a or posedge rst_a)
1191 
if (rst_a)
1192 
    ack_o <= 1'b0;
1193 
else
1194 
    ack_o <= req[3] & req[2];
1195 
 
1196 
endmodule
1197 
`endif
1198 17 unneback 
//////////////////////////////////////////////////////////////////////
1199 6 unneback 
////                                                              ////
1200 18 unneback 
////  Logic functions                                             ////
1201 
////                                                              ////
1202 
////  Description                                                 ////
1203 
////  Logic functions such as multiplexers                        ////
1204 
////                                                              ////
1205 
////                                                              ////
1206 
////  To Do:                                                      ////
1207 
////   -                                                          ////
1208 
////                                                              ////
1209 
////  Author(s):                                                  ////
1210 
////      - Michael Unneback, unneback@opencores.org              ////
1211 
////        ORSoC AB                                              ////
1212 
////                                                              ////
1213 
//////////////////////////////////////////////////////////////////////
1214 
////                                                              ////
1215 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1216 
////                                                              ////
1217 
//// This source file may be used and distributed without         ////
1218 
//// restriction provided that this copyright statement is not    ////
1219 
//// removed from the file and that any derivative work contains  ////
1220 
//// the original copyright notice and the associated disclaimer. ////
1221 
////                                                              ////
1222 
//// This source file is free software; you can redistribute it   ////
1223 
//// and/or modify it under the terms of the GNU Lesser General   ////
1224 
//// Public License as published by the Free Software Foundation; ////
1225 
//// either version 2.1 of the License, or (at your option) any   ////
1226 
//// later version.                                               ////
1227 
////                                                              ////
1228 
//// This source is distributed in the hope that it will be       ////
1229 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1230 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1231 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1232 
//// details.                                                     ////
1233 
////                                                              ////
1234 
//// You should have received a copy of the GNU Lesser General    ////
1235 
//// Public License along with this source; if not, download it   ////
1236 
//// from http://www.opencores.org/lgpl.shtml                     ////
1237 
////                                                              ////
1238 
//////////////////////////////////////////////////////////////////////
1239 40 unneback 
`ifdef MUX_ANDOR
1240 
`define MODULE mux_andor
1241 
module `BASE`MODULE ( a, sel, dout);
1242 
`undef MODULE
1243 36 unneback 
 
1244 
parameter width = 32;
1245 
parameter nr_of_ports = 4;
1246 
 
1247 
input [nr_of_ports*width-1:0] a;
1248 
input [nr_of_ports-1:0] sel;
1249 
output reg [width-1:0] dout;
1250 
 
1251 38 unneback 
integer i,j;
1252 
 
1253 36 unneback 
always @ (a, sel)
1254 
begin
1255 
    dout = a[width-1:0] & {width{sel[0]}};
1256 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1257 
        for (j=0;j<width;j=j+1)
1258 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1259 36 unneback 
end
1260 
 
1261 
endmodule
1262 40 unneback 
`endif
1263 36 unneback 
 
1264 40 unneback 
`ifdef MUX2_ANDOR
1265 
`define MODULE mux2_andor
1266 
module `BASE`MODULE ( a1, a0, sel, dout);
1267 
`undef MODULE
1268 18 unneback 
 
1269 34 unneback 
parameter width = 32;
1270 35 unneback 
localparam nr_of_ports = 2;
1271 34 unneback 
input [width-1:0] a1, a0;
1272 
input [nr_of_ports-1:0] sel;
1273 
output [width-1:0] dout;
1274 
 
1275 40 unneback 
`define MODULE mux_andor
1276 
`BASE`MODULE
1277 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1278 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1279 40 unneback 
`undef MODULE
1280 
 
1281 34 unneback 
endmodule
1282 40 unneback 
`endif
1283 34 unneback 
 
1284 40 unneback 
`ifdef MUX3_ANDOR
1285 
`define MODULE mux3_andor
1286 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1287 
`undef MODULE
1288 34 unneback 
 
1289 
parameter width = 32;
1290 35 unneback 
localparam nr_of_ports = 3;
1291 34 unneback 
input [width-1:0] a2, a1, a0;
1292 
input [nr_of_ports-1:0] sel;
1293 
output [width-1:0] dout;
1294 
 
1295 40 unneback 
`define MODULE mux_andor
1296 
`BASE`MODULE
1297 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1298 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1299 40 unneback 
`undef MODULE
1300 34 unneback 
endmodule
1301 40 unneback 
`endif
1302 34 unneback 
 
1303 40 unneback 
`ifdef MUX4_ANDOR
1304 
`define MODULE mux4_andor
1305 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1306 
`undef MODULE
1307 18 unneback 
 
1308 
parameter width = 32;
1309 35 unneback 
localparam nr_of_ports = 4;
1310 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1311 
input [nr_of_ports-1:0] sel;
1312 22 unneback 
output [width-1:0] dout;
1313 18 unneback 
 
1314 40 unneback 
`define MODULE mux_andor
1315 
`BASE`MODULE
1316 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1317 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1318 40 unneback 
`undef MODULE
1319 18 unneback 
 
1320 
endmodule
1321 40 unneback 
`endif
1322 18 unneback 
 
1323 40 unneback 
`ifdef MUX5_ANDOR
1324 
`define MODULE mux5_andor
1325 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1326 
`undef MODULE
1327 18 unneback 
 
1328 
parameter width = 32;
1329 35 unneback 
localparam nr_of_ports = 5;
1330 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1331 
input [nr_of_ports-1:0] sel;
1332 22 unneback 
output [width-1:0] dout;
1333 18 unneback 
 
1334 40 unneback 
`define MODULE mux_andor
1335 
`BASE`MODULE
1336 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1337 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1338 40 unneback 
`undef MODULE
1339 18 unneback 
 
1340 
endmodule
1341 40 unneback 
`endif
1342 18 unneback 
 
1343 40 unneback 
`ifdef MUX6_ANDOR
1344 
`define MODULE mux6_andor
1345 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1346 
`undef MODULE
1347 18 unneback 
 
1348 
parameter width = 32;
1349 35 unneback 
localparam nr_of_ports = 6;
1350 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1351 
input [nr_of_ports-1:0] sel;
1352 22 unneback 
output [width-1:0] dout;
1353 18 unneback 
 
1354 40 unneback 
`define MODULE mux_andor
1355 
`BASE`MODULE
1356 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1357 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1358 40 unneback 
`undef MODULE
1359 18 unneback 
 
1360 
endmodule
1361 40 unneback 
`endif
1362 43 unneback 
 
1363 
`ifdef PARITY
1364 
 
1365 
`define MODULE parity_generate
1366 
module `BASE`MODULE (data, parity);
1367 
`undef MODULE
1368 
parameter word_size = 32;
1369 
parameter chunk_size = 8;
1370 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1371 
input [word_size-1:0] data;
1372 
output reg [word_size/chunk_size-1:0] parity;
1373 
integer i,j;
1374 
always @ (data)
1375 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1376 
    parity[i] = parity_type;
1377 
    for (j=0;j<chunk_size;j=j+1) begin
1378 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1379 43 unneback 
    end
1380 
end
1381 
endmodule
1382 
 
1383 
`define MODULE parity_check
1384 
module `BASE`MODULE( data, parity, parity_error);
1385 
`undef MODULE
1386 
parameter word_size = 32;
1387 
parameter chunk_size = 8;
1388 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1389 
input [word_size-1:0] data;
1390 
input [word_size/chunk_size-1:0] parity;
1391 
output parity_error;
1392 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1393 43 unneback 
integer i,j;
1394 
always @ (data or parity)
1395 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1396 
    error_flag[i] = parity[i] ^ parity_type;
1397 
    for (j=0;j<chunk_size;j=j+1) begin
1398 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1399 43 unneback 
    end
1400 
end
1401 
assign parity_error = |error_flag;
1402 
endmodule
1403 
 
1404 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1405 
////                                                              ////
1406 
////  IO functions                                                ////
1407 
////                                                              ////
1408 
////  Description                                                 ////
1409 
////  IO functions such as IOB flip-flops                         ////
1410 
////                                                              ////
1411 
////                                                              ////
1412 
////  To Do:                                                      ////
1413 
////   -                                                          ////
1414 
////                                                              ////
1415 
////  Author(s):                                                  ////
1416 
////      - Michael Unneback, unneback@opencores.org              ////
1417 
////        ORSoC AB                                              ////
1418 
////                                                              ////
1419 18 unneback 
//////////////////////////////////////////////////////////////////////
1420 
////                                                              ////
1421 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1422 
////                                                              ////
1423 
//// This source file may be used and distributed without         ////
1424 
//// restriction provided that this copyright statement is not    ////
1425 
//// removed from the file and that any derivative work contains  ////
1426 
//// the original copyright notice and the associated disclaimer. ////
1427 
////                                                              ////
1428 
//// This source file is free software; you can redistribute it   ////
1429 
//// and/or modify it under the terms of the GNU Lesser General   ////
1430 
//// Public License as published by the Free Software Foundation; ////
1431 
//// either version 2.1 of the License, or (at your option) any   ////
1432 
//// later version.                                               ////
1433 
////                                                              ////
1434 
//// This source is distributed in the hope that it will be       ////
1435 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1436 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1437 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1438 
//// details.                                                     ////
1439 
////                                                              ////
1440 
//// You should have received a copy of the GNU Lesser General    ////
1441 
//// Public License along with this source; if not, download it   ////
1442 
//// from http://www.opencores.org/lgpl.shtml                     ////
1443 
////                                                              ////
1444 
//////////////////////////////////////////////////////////////////////
1445 45 unneback 
`timescale 1ns/1ns
1446 44 unneback 
`ifdef O_DFF
1447 
`define MODULE o_dff
1448 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1449 
`undef MODULE
1450 
parameter width = 1;
1451 45 unneback 
parameter reset_value = {width{1'b0}};
1452 
input  [width-1:0]  d_i;
1453 44 unneback 
output [width-1:0] o_pad;
1454 
input clk, rst;
1455 
wire [width-1:0] d_i_int `SYN_KEEP;
1456 45 unneback 
reg  [width-1:0] o_pad_int;
1457 44 unneback 
assign d_i_int = d_i;
1458 
genvar i;
1459 45 unneback 
generate
1460 44 unneback 
for (i=0;i<width;i=i+1) begin
1461 
    always @ (posedge clk or posedge rst)
1462 
    if (rst)
1463 45 unneback 
        o_pad_int[i] <= reset_value[i];
1464 44 unneback 
    else
1465 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1466 
    assign #1 o_pad[i] = o_pad_int[i];
1467 44 unneback 
end
1468 
endgenerate
1469 
endmodule
1470 
`endif
1471 
 
1472 45 unneback 
`timescale 1ns/1ns
1473 44 unneback 
`ifdef IO_DFF_OE
1474 
`define MODULE io_dff_oe
1475 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1476 
`undef MODULE
1477 
parameter width = 1;
1478 
input  [width-1:0] d_o;
1479 
output reg [width-1:0] d_i;
1480 
input oe;
1481 
inout [width-1:0] io_pad;
1482 
input clk, rst;
1483 
wire [width-1:0] oe_d `SYN_KEEP;
1484 
reg [width-1:0] oe_q;
1485 
reg [width-1:0] d_o_q;
1486 
assign oe_d = {width{oe}};
1487 
genvar i;
1488 
generate
1489 
for (i=0;i<width;i=i+1) begin
1490 
    always @ (posedge clk or posedge rst)
1491 
    if (rst)
1492 
        oe_q[i] <= 1'b0;
1493 
    else
1494 
        oe_q[i] <= oe_d[i];
1495 
    always @ (posedge clk or posedge rst)
1496 
    if (rst)
1497 
        d_o_q[i] <= 1'b0;
1498 
    else
1499 
        d_o_q[i] <= d_o[i];
1500 
    always @ (posedge clk or posedge rst)
1501 
    if (rst)
1502 
        d_i[i] <= 1'b0;
1503 
    else
1504 
        d_i[i] <= io_pad[i];
1505 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1506 44 unneback 
end
1507 
endgenerate
1508 
endmodule
1509 
`endif
1510 
`ifdef CNT_BIN
1511 
//////////////////////////////////////////////////////////////////////
1512 
////                                                              ////
1513 6 unneback 
////  Versatile counter                                           ////
1514 
////                                                              ////
1515 
////  Description                                                 ////
1516 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1517 
////  counter                                                     ////
1518 
////                                                              ////
1519 
////  To Do:                                                      ////
1520 
////   - add LFSR with more taps                                  ////
1521 
////                                                              ////
1522 
////  Author(s):                                                  ////
1523 
////      - Michael Unneback, unneback@opencores.org              ////
1524 
////        ORSoC AB                                              ////
1525 
////                                                              ////
1526 
//////////////////////////////////////////////////////////////////////
1527 
////                                                              ////
1528 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1529 
////                                                              ////
1530 
//// This source file may be used and distributed without         ////
1531 
//// restriction provided that this copyright statement is not    ////
1532 
//// removed from the file and that any derivative work contains  ////
1533 
//// the original copyright notice and the associated disclaimer. ////
1534 
////                                                              ////
1535 
//// This source file is free software; you can redistribute it   ////
1536 
//// and/or modify it under the terms of the GNU Lesser General   ////
1537 
//// Public License as published by the Free Software Foundation; ////
1538 
//// either version 2.1 of the License, or (at your option) any   ////
1539 
//// later version.                                               ////
1540 
////                                                              ////
1541 
//// This source is distributed in the hope that it will be       ////
1542 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1543 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1544 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1545 
//// details.                                                     ////
1546 
////                                                              ////
1547 
//// You should have received a copy of the GNU Lesser General    ////
1548 
//// Public License along with this source; if not, download it   ////
1549 
//// from http://www.opencores.org/lgpl.shtml                     ////
1550 
////                                                              ////
1551 
//////////////////////////////////////////////////////////////////////
1552 
 
1553 
// binary counter
1554 22 unneback 
 
1555 40 unneback 
`define MODULE cnt_bin
1556 
module `BASE`MODULE (
1557 
`undef MODULE
1558 
 q, rst, clk);
1559 
 
1560 22 unneback 
   parameter length = 4;
1561 
   output [length:1] q;
1562 
   input rst;
1563 
   input clk;
1564 
 
1565 
   parameter clear_value = 0;
1566 
   parameter set_value = 1;
1567 
   parameter wrap_value = 0;
1568 
   parameter level1_value = 15;
1569 
 
1570 
   reg  [length:1] qi;
1571 
   wire [length:1] q_next;
1572 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1573 
 
1574 
   always @ (posedge clk or posedge rst)
1575 
     if (rst)
1576 
       qi <= {length{1'b0}};
1577 
     else
1578 
       qi <= q_next;
1579 
 
1580 
   assign q = qi;
1581 
 
1582 
endmodule
1583 40 unneback 
`endif
1584 
`ifdef CNT_BIN_CLEAR
1585 22 unneback 
//////////////////////////////////////////////////////////////////////
1586 
////                                                              ////
1587 
////  Versatile counter                                           ////
1588 
////                                                              ////
1589 
////  Description                                                 ////
1590 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1591 
////  counter                                                     ////
1592 
////                                                              ////
1593 
////  To Do:                                                      ////
1594 
////   - add LFSR with more taps                                  ////
1595 
////                                                              ////
1596 
////  Author(s):                                                  ////
1597 
////      - Michael Unneback, unneback@opencores.org              ////
1598 
////        ORSoC AB                                              ////
1599 
////                                                              ////
1600 
//////////////////////////////////////////////////////////////////////
1601 
////                                                              ////
1602 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1603 
////                                                              ////
1604 
//// This source file may be used and distributed without         ////
1605 
//// restriction provided that this copyright statement is not    ////
1606 
//// removed from the file and that any derivative work contains  ////
1607 
//// the original copyright notice and the associated disclaimer. ////
1608 
////                                                              ////
1609 
//// This source file is free software; you can redistribute it   ////
1610 
//// and/or modify it under the terms of the GNU Lesser General   ////
1611 
//// Public License as published by the Free Software Foundation; ////
1612 
//// either version 2.1 of the License, or (at your option) any   ////
1613 
//// later version.                                               ////
1614 
////                                                              ////
1615 
//// This source is distributed in the hope that it will be       ////
1616 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1617 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1618 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1619 
//// details.                                                     ////
1620 
////                                                              ////
1621 
//// You should have received a copy of the GNU Lesser General    ////
1622 
//// Public License along with this source; if not, download it   ////
1623 
//// from http://www.opencores.org/lgpl.shtml                     ////
1624 
////                                                              ////
1625 
//////////////////////////////////////////////////////////////////////
1626 
 
1627 
// binary counter
1628 
 
1629 40 unneback 
`define MODULE cnt_bin_clear
1630 
module `BASE`MODULE (
1631 
`undef MODULE
1632 
 clear, q, rst, clk);
1633 
 
1634 22 unneback 
   parameter length = 4;
1635 
   input clear;
1636 
   output [length:1] q;
1637 
   input rst;
1638 
   input clk;
1639 
 
1640 
   parameter clear_value = 0;
1641 
   parameter set_value = 1;
1642 
   parameter wrap_value = 0;
1643 
   parameter level1_value = 15;
1644 
 
1645 
   reg  [length:1] qi;
1646 
   wire [length:1] q_next;
1647 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1648 
 
1649 
   always @ (posedge clk or posedge rst)
1650 
     if (rst)
1651 
       qi <= {length{1'b0}};
1652 
     else
1653 
       qi <= q_next;
1654 
 
1655 
   assign q = qi;
1656 
 
1657 
endmodule
1658 40 unneback 
`endif
1659 
`ifdef CNT_BIN_CE
1660 22 unneback 
//////////////////////////////////////////////////////////////////////
1661 
////                                                              ////
1662 
////  Versatile counter                                           ////
1663 
////                                                              ////
1664 
////  Description                                                 ////
1665 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1666 
////  counter                                                     ////
1667 
////                                                              ////
1668 
////  To Do:                                                      ////
1669 
////   - add LFSR with more taps                                  ////
1670 
////                                                              ////
1671 
////  Author(s):                                                  ////
1672 
////      - Michael Unneback, unneback@opencores.org              ////
1673 
////        ORSoC AB                                              ////
1674 
////                                                              ////
1675 
//////////////////////////////////////////////////////////////////////
1676 
////                                                              ////
1677 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1678 
////                                                              ////
1679 
//// This source file may be used and distributed without         ////
1680 
//// restriction provided that this copyright statement is not    ////
1681 
//// removed from the file and that any derivative work contains  ////
1682 
//// the original copyright notice and the associated disclaimer. ////
1683 
////                                                              ////
1684 
//// This source file is free software; you can redistribute it   ////
1685 
//// and/or modify it under the terms of the GNU Lesser General   ////
1686 
//// Public License as published by the Free Software Foundation; ////
1687 
//// either version 2.1 of the License, or (at your option) any   ////
1688 
//// later version.                                               ////
1689 
////                                                              ////
1690 
//// This source is distributed in the hope that it will be       ////
1691 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1692 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1693 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1694 
//// details.                                                     ////
1695 
////                                                              ////
1696 
//// You should have received a copy of the GNU Lesser General    ////
1697 
//// Public License along with this source; if not, download it   ////
1698 
//// from http://www.opencores.org/lgpl.shtml                     ////
1699 
////                                                              ////
1700 
//////////////////////////////////////////////////////////////////////
1701 
 
1702 
// binary counter
1703 6 unneback 
 
1704 40 unneback 
`define MODULE cnt_bin_ce
1705 
module `BASE`MODULE (
1706 
`undef MODULE
1707 
 cke, q, rst, clk);
1708 
 
1709 6 unneback 
   parameter length = 4;
1710 
   input cke;
1711 
   output [length:1] q;
1712 
   input rst;
1713 
   input clk;
1714 
 
1715 
   parameter clear_value = 0;
1716 
   parameter set_value = 1;
1717 
   parameter wrap_value = 0;
1718 
   parameter level1_value = 15;
1719 
 
1720 
   reg  [length:1] qi;
1721 
   wire [length:1] q_next;
1722 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1723 
 
1724 
   always @ (posedge clk or posedge rst)
1725 
     if (rst)
1726 
       qi <= {length{1'b0}};
1727 
     else
1728 
     if (cke)
1729 
       qi <= q_next;
1730 
 
1731 
   assign q = qi;
1732 
 
1733 
endmodule
1734 40 unneback 
`endif
1735 
`ifdef CNT_BIN_CE_CLEAR
1736 6 unneback 
//////////////////////////////////////////////////////////////////////
1737 
////                                                              ////
1738 
////  Versatile counter                                           ////
1739 
////                                                              ////
1740 
////  Description                                                 ////
1741 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1742 
////  counter                                                     ////
1743 
////                                                              ////
1744 
////  To Do:                                                      ////
1745 
////   - add LFSR with more taps                                  ////
1746 
////                                                              ////
1747 
////  Author(s):                                                  ////
1748 
////      - Michael Unneback, unneback@opencores.org              ////
1749 
////        ORSoC AB                                              ////
1750 
////                                                              ////
1751 
//////////////////////////////////////////////////////////////////////
1752 
////                                                              ////
1753 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1754 
////                                                              ////
1755 
//// This source file may be used and distributed without         ////
1756 
//// restriction provided that this copyright statement is not    ////
1757 
//// removed from the file and that any derivative work contains  ////
1758 
//// the original copyright notice and the associated disclaimer. ////
1759 
////                                                              ////
1760 
//// This source file is free software; you can redistribute it   ////
1761 
//// and/or modify it under the terms of the GNU Lesser General   ////
1762 
//// Public License as published by the Free Software Foundation; ////
1763 
//// either version 2.1 of the License, or (at your option) any   ////
1764 
//// later version.                                               ////
1765 
////                                                              ////
1766 
//// This source is distributed in the hope that it will be       ////
1767 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1768 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1769 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1770 
//// details.                                                     ////
1771 
////                                                              ////
1772 
//// You should have received a copy of the GNU Lesser General    ////
1773 
//// Public License along with this source; if not, download it   ////
1774 
//// from http://www.opencores.org/lgpl.shtml                     ////
1775 
////                                                              ////
1776 
//////////////////////////////////////////////////////////////////////
1777 
 
1778 
// binary counter
1779 
 
1780 40 unneback 
`define MODULE cnt_bin_ce_clear
1781 
module `BASE`MODULE (
1782 
`undef MODULE
1783 
 clear, cke, q, rst, clk);
1784 
 
1785 6 unneback 
   parameter length = 4;
1786 
   input clear;
1787 
   input cke;
1788 
   output [length:1] q;
1789 
   input rst;
1790 
   input clk;
1791 
 
1792 
   parameter clear_value = 0;
1793 
   parameter set_value = 1;
1794 
   parameter wrap_value = 0;
1795 
   parameter level1_value = 15;
1796 
 
1797 
   reg  [length:1] qi;
1798 
   wire [length:1] q_next;
1799 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1800 
 
1801 
   always @ (posedge clk or posedge rst)
1802 
     if (rst)
1803 
       qi <= {length{1'b0}};
1804 
     else
1805 
     if (cke)
1806 
       qi <= q_next;
1807 
 
1808 
   assign q = qi;
1809 
 
1810 
endmodule
1811 40 unneback 
`endif
1812 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1813 6 unneback 
//////////////////////////////////////////////////////////////////////
1814 
////                                                              ////
1815 
////  Versatile counter                                           ////
1816 
////                                                              ////
1817 
////  Description                                                 ////
1818 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1819 
////  counter                                                     ////
1820 
////                                                              ////
1821 
////  To Do:                                                      ////
1822 
////   - add LFSR with more taps                                  ////
1823 
////                                                              ////
1824 
////  Author(s):                                                  ////
1825 
////      - Michael Unneback, unneback@opencores.org              ////
1826 
////        ORSoC AB                                              ////
1827 
////                                                              ////
1828 
//////////////////////////////////////////////////////////////////////
1829 
////                                                              ////
1830 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1831 
////                                                              ////
1832 
//// This source file may be used and distributed without         ////
1833 
//// restriction provided that this copyright statement is not    ////
1834 
//// removed from the file and that any derivative work contains  ////
1835 
//// the original copyright notice and the associated disclaimer. ////
1836 
////                                                              ////
1837 
//// This source file is free software; you can redistribute it   ////
1838 
//// and/or modify it under the terms of the GNU Lesser General   ////
1839 
//// Public License as published by the Free Software Foundation; ////
1840 
//// either version 2.1 of the License, or (at your option) any   ////
1841 
//// later version.                                               ////
1842 
////                                                              ////
1843 
//// This source is distributed in the hope that it will be       ////
1844 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1845 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1846 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1847 
//// details.                                                     ////
1848 
////                                                              ////
1849 
//// You should have received a copy of the GNU Lesser General    ////
1850 
//// Public License along with this source; if not, download it   ////
1851 
//// from http://www.opencores.org/lgpl.shtml                     ////
1852 
////                                                              ////
1853 
//////////////////////////////////////////////////////////////////////
1854 
 
1855 
// binary counter
1856 29 unneback 
 
1857 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1858 
module `BASE`MODULE (
1859 
`undef MODULE
1860 
 clear, cke, q, level1, level2, rst, clk);
1861 
 
1862 29 unneback 
   parameter length = 4;
1863 
   input clear;
1864 
   input cke;
1865 
   output [length:1] q;
1866 
   output reg level1;
1867 
   output reg level2;
1868 
   input rst;
1869 
   input clk;
1870 
 
1871 
   parameter clear_value = 0;
1872 
   parameter set_value = 1;
1873 30 unneback 
   parameter wrap_value = 15;
1874 
   parameter level1_value = 8;
1875 
   parameter level2_value = 15;
1876 29 unneback 
 
1877 
   wire rew;
1878 30 unneback 
   assign rew = 1'b0;
1879 29 unneback 
   reg  [length:1] qi;
1880 
   wire [length:1] q_next;
1881 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1882 
 
1883 
   always @ (posedge clk or posedge rst)
1884 
     if (rst)
1885 
       qi <= {length{1'b0}};
1886 
     else
1887 
     if (cke)
1888 
       qi <= q_next;
1889 
 
1890 
   assign q = qi;
1891 
 
1892 
 
1893 
    always @ (posedge clk or posedge rst)
1894 
    if (rst)
1895 
        level1 <= 1'b0;
1896 
    else
1897 
    if (cke)
1898 
    if (clear)
1899 
        level1 <= 1'b0;
1900 
    else if (q_next == level1_value)
1901 
        level1 <= 1'b1;
1902 
    else if (qi == level1_value & rew)
1903 
        level1 <= 1'b0;
1904 
 
1905 
    always @ (posedge clk or posedge rst)
1906 
    if (rst)
1907 
        level2 <= 1'b0;
1908 
    else
1909 
    if (cke)
1910 
    if (clear)
1911 
        level2 <= 1'b0;
1912 
    else if (q_next == level2_value)
1913 
        level2 <= 1'b1;
1914 
    else if (qi == level2_value & rew)
1915 
        level2 <= 1'b0;
1916 
endmodule
1917 40 unneback 
`endif
1918 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1919 29 unneback 
//////////////////////////////////////////////////////////////////////
1920 
////                                                              ////
1921 
////  Versatile counter                                           ////
1922 
////                                                              ////
1923 
////  Description                                                 ////
1924 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1925 
////  counter                                                     ////
1926 
////                                                              ////
1927 
////  To Do:                                                      ////
1928 
////   - add LFSR with more taps                                  ////
1929 
////                                                              ////
1930 
////  Author(s):                                                  ////
1931 
////      - Michael Unneback, unneback@opencores.org              ////
1932 
////        ORSoC AB                                              ////
1933 
////                                                              ////
1934 
//////////////////////////////////////////////////////////////////////
1935 
////                                                              ////
1936 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1937 
////                                                              ////
1938 
//// This source file may be used and distributed without         ////
1939 
//// restriction provided that this copyright statement is not    ////
1940 
//// removed from the file and that any derivative work contains  ////
1941 
//// the original copyright notice and the associated disclaimer. ////
1942 
////                                                              ////
1943 
//// This source file is free software; you can redistribute it   ////
1944 
//// and/or modify it under the terms of the GNU Lesser General   ////
1945 
//// Public License as published by the Free Software Foundation; ////
1946 
//// either version 2.1 of the License, or (at your option) any   ////
1947 
//// later version.                                               ////
1948 
////                                                              ////
1949 
//// This source is distributed in the hope that it will be       ////
1950 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1951 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1952 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1953 
//// details.                                                     ////
1954 
////                                                              ////
1955 
//// You should have received a copy of the GNU Lesser General    ////
1956 
//// Public License along with this source; if not, download it   ////
1957 
//// from http://www.opencores.org/lgpl.shtml                     ////
1958 
////                                                              ////
1959 
//////////////////////////////////////////////////////////////////////
1960 
 
1961 
// binary counter
1962 6 unneback 
 
1963 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
1964 
module `BASE`MODULE (
1965 
`undef MODULE
1966 
 clear, set, cke, rew, q, rst, clk);
1967 
 
1968 6 unneback 
   parameter length = 4;
1969 
   input clear;
1970 
   input set;
1971 
   input cke;
1972 
   input rew;
1973 
   output [length:1] q;
1974 
   input rst;
1975 
   input clk;
1976 
 
1977 
   parameter clear_value = 0;
1978 
   parameter set_value = 1;
1979 
   parameter wrap_value = 0;
1980 
   parameter level1_value = 15;
1981 
 
1982 
   reg  [length:1] qi;
1983 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1984 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1985 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1986 
   assign q_next = rew ? q_next_rew : q_next_fw;
1987 
 
1988 
   always @ (posedge clk or posedge rst)
1989 
     if (rst)
1990 
       qi <= {length{1'b0}};
1991 
     else
1992 
     if (cke)
1993 
       qi <= q_next;
1994 
 
1995 
   assign q = qi;
1996 
 
1997 
endmodule
1998 40 unneback 
`endif
1999 
`ifdef CNT_BIN_CE_REW_L1
2000 6 unneback 
//////////////////////////////////////////////////////////////////////
2001 
////                                                              ////
2002 
////  Versatile counter                                           ////
2003 
////                                                              ////
2004 
////  Description                                                 ////
2005 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2006 
////  counter                                                     ////
2007 
////                                                              ////
2008 
////  To Do:                                                      ////
2009 
////   - add LFSR with more taps                                  ////
2010 
////                                                              ////
2011 
////  Author(s):                                                  ////
2012 
////      - Michael Unneback, unneback@opencores.org              ////
2013 
////        ORSoC AB                                              ////
2014 
////                                                              ////
2015 
//////////////////////////////////////////////////////////////////////
2016 
////                                                              ////
2017 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2018 
////                                                              ////
2019 
//// This source file may be used and distributed without         ////
2020 
//// restriction provided that this copyright statement is not    ////
2021 
//// removed from the file and that any derivative work contains  ////
2022 
//// the original copyright notice and the associated disclaimer. ////
2023 
////                                                              ////
2024 
//// This source file is free software; you can redistribute it   ////
2025 
//// and/or modify it under the terms of the GNU Lesser General   ////
2026 
//// Public License as published by the Free Software Foundation; ////
2027 
//// either version 2.1 of the License, or (at your option) any   ////
2028 
//// later version.                                               ////
2029 
////                                                              ////
2030 
//// This source is distributed in the hope that it will be       ////
2031 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2032 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2033 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2034 
//// details.                                                     ////
2035 
////                                                              ////
2036 
//// You should have received a copy of the GNU Lesser General    ////
2037 
//// Public License along with this source; if not, download it   ////
2038 
//// from http://www.opencores.org/lgpl.shtml                     ////
2039 
////                                                              ////
2040 
//////////////////////////////////////////////////////////////////////
2041 
 
2042 
// binary counter
2043 
 
2044 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
2045 
module `BASE`MODULE (
2046 
`undef MODULE
2047 
 cke, rew, level1, rst, clk);
2048 
 
2049 6 unneback 
   parameter length = 4;
2050 
   input cke;
2051 
   input rew;
2052 
   output reg level1;
2053 
   input rst;
2054 
   input clk;
2055 
 
2056 
   parameter clear_value = 0;
2057 
   parameter set_value = 1;
2058 
   parameter wrap_value = 1;
2059 
   parameter level1_value = 15;
2060 
 
2061 29 unneback 
   wire clear;
2062 30 unneback 
   assign clear = 1'b0;
2063 6 unneback 
   reg  [length:1] qi;
2064 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2065 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2066 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2067 
   assign q_next = rew ? q_next_rew : q_next_fw;
2068 
 
2069 
   always @ (posedge clk or posedge rst)
2070 
     if (rst)
2071 
       qi <= {length{1'b0}};
2072 
     else
2073 
     if (cke)
2074 
       qi <= q_next;
2075 
 
2076 
 
2077 
 
2078 
    always @ (posedge clk or posedge rst)
2079 
    if (rst)
2080 
        level1 <= 1'b0;
2081 
    else
2082 
    if (cke)
2083 29 unneback 
    if (clear)
2084 
        level1 <= 1'b0;
2085 
    else if (q_next == level1_value)
2086 6 unneback 
        level1 <= 1'b1;
2087 
    else if (qi == level1_value & rew)
2088 
        level1 <= 1'b0;
2089 
endmodule
2090 40 unneback 
`endif
2091 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2092 6 unneback 
//////////////////////////////////////////////////////////////////////
2093 
////                                                              ////
2094 
////  Versatile counter                                           ////
2095 
////                                                              ////
2096 
////  Description                                                 ////
2097 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2098 
////  counter                                                     ////
2099 
////                                                              ////
2100 
////  To Do:                                                      ////
2101 
////   - add LFSR with more taps                                  ////
2102 
////                                                              ////
2103 
////  Author(s):                                                  ////
2104 
////      - Michael Unneback, unneback@opencores.org              ////
2105 
////        ORSoC AB                                              ////
2106 
////                                                              ////
2107 
//////////////////////////////////////////////////////////////////////
2108 
////                                                              ////
2109 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2110 
////                                                              ////
2111 
//// This source file may be used and distributed without         ////
2112 
//// restriction provided that this copyright statement is not    ////
2113 
//// removed from the file and that any derivative work contains  ////
2114 
//// the original copyright notice and the associated disclaimer. ////
2115 
////                                                              ////
2116 
//// This source file is free software; you can redistribute it   ////
2117 
//// and/or modify it under the terms of the GNU Lesser General   ////
2118 
//// Public License as published by the Free Software Foundation; ////
2119 
//// either version 2.1 of the License, or (at your option) any   ////
2120 
//// later version.                                               ////
2121 
////                                                              ////
2122 
//// This source is distributed in the hope that it will be       ////
2123 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2124 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2125 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2126 
//// details.                                                     ////
2127 
////                                                              ////
2128 
//// You should have received a copy of the GNU Lesser General    ////
2129 
//// Public License along with this source; if not, download it   ////
2130 
//// from http://www.opencores.org/lgpl.shtml                     ////
2131 
////                                                              ////
2132 
//////////////////////////////////////////////////////////////////////
2133 
 
2134 25 unneback 
// binary counter
2135 
 
2136 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2137 
module `BASE`MODULE (
2138 
`undef MODULE
2139 
 cke, rew, zq, level1, rst, clk);
2140 
 
2141 25 unneback 
   parameter length = 4;
2142 
   input cke;
2143 
   input rew;
2144 
   output reg zq;
2145 
   output reg level1;
2146 
   input rst;
2147 
   input clk;
2148 
 
2149 
   parameter clear_value = 0;
2150 
   parameter set_value = 1;
2151 
   parameter wrap_value = 1;
2152 
   parameter level1_value = 15;
2153 
 
2154 29 unneback 
   wire clear;
2155 30 unneback 
   assign clear = 1'b0;
2156 25 unneback 
   reg  [length:1] qi;
2157 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2158 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2159 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2160 
   assign q_next = rew ? q_next_rew : q_next_fw;
2161 
 
2162 
   always @ (posedge clk or posedge rst)
2163 
     if (rst)
2164 
       qi <= {length{1'b0}};
2165 
     else
2166 
     if (cke)
2167 
       qi <= q_next;
2168 
 
2169 
 
2170 
 
2171 
   always @ (posedge clk or posedge rst)
2172 
     if (rst)
2173 
       zq <= 1'b1;
2174 
     else
2175 
     if (cke)
2176 
       zq <= q_next == {length{1'b0}};
2177 
 
2178 
    always @ (posedge clk or posedge rst)
2179 
    if (rst)
2180 
        level1 <= 1'b0;
2181 
    else
2182 
    if (cke)
2183 29 unneback 
    if (clear)
2184 
        level1 <= 1'b0;
2185 
    else if (q_next == level1_value)
2186 25 unneback 
        level1 <= 1'b1;
2187 
    else if (qi == level1_value & rew)
2188 
        level1 <= 1'b0;
2189 
endmodule
2190 40 unneback 
`endif
2191 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2192 25 unneback 
//////////////////////////////////////////////////////////////////////
2193 
////                                                              ////
2194 
////  Versatile counter                                           ////
2195 
////                                                              ////
2196 
////  Description                                                 ////
2197 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2198 
////  counter                                                     ////
2199 
////                                                              ////
2200 
////  To Do:                                                      ////
2201 
////   - add LFSR with more taps                                  ////
2202 
////                                                              ////
2203 
////  Author(s):                                                  ////
2204 
////      - Michael Unneback, unneback@opencores.org              ////
2205 
////        ORSoC AB                                              ////
2206 
////                                                              ////
2207 
//////////////////////////////////////////////////////////////////////
2208 
////                                                              ////
2209 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2210 
////                                                              ////
2211 
//// This source file may be used and distributed without         ////
2212 
//// restriction provided that this copyright statement is not    ////
2213 
//// removed from the file and that any derivative work contains  ////
2214 
//// the original copyright notice and the associated disclaimer. ////
2215 
////                                                              ////
2216 
//// This source file is free software; you can redistribute it   ////
2217 
//// and/or modify it under the terms of the GNU Lesser General   ////
2218 
//// Public License as published by the Free Software Foundation; ////
2219 
//// either version 2.1 of the License, or (at your option) any   ////
2220 
//// later version.                                               ////
2221 
////                                                              ////
2222 
//// This source is distributed in the hope that it will be       ////
2223 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2224 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2225 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2226 
//// details.                                                     ////
2227 
////                                                              ////
2228 
//// You should have received a copy of the GNU Lesser General    ////
2229 
//// Public License along with this source; if not, download it   ////
2230 
//// from http://www.opencores.org/lgpl.shtml                     ////
2231 
////                                                              ////
2232 
//////////////////////////////////////////////////////////////////////
2233 
 
2234 
// binary counter
2235 
 
2236 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2237 
module `BASE`MODULE (
2238 
`undef MODULE
2239 
 cke, rew, q, zq, level1, rst, clk);
2240 
 
2241 25 unneback 
   parameter length = 4;
2242 
   input cke;
2243 
   input rew;
2244 
   output [length:1] q;
2245 
   output reg zq;
2246 
   output reg level1;
2247 
   input rst;
2248 
   input clk;
2249 
 
2250 
   parameter clear_value = 0;
2251 
   parameter set_value = 1;
2252 
   parameter wrap_value = 1;
2253 
   parameter level1_value = 15;
2254 
 
2255 29 unneback 
   wire clear;
2256 30 unneback 
   assign clear = 1'b0;
2257 25 unneback 
   reg  [length:1] qi;
2258 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2259 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2260 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2261 
   assign q_next = rew ? q_next_rew : q_next_fw;
2262 
 
2263 
   always @ (posedge clk or posedge rst)
2264 
     if (rst)
2265 
       qi <= {length{1'b0}};
2266 
     else
2267 
     if (cke)
2268 
       qi <= q_next;
2269 
 
2270 
   assign q = qi;
2271 
 
2272 
 
2273 
   always @ (posedge clk or posedge rst)
2274 
     if (rst)
2275 
       zq <= 1'b1;
2276 
     else
2277 
     if (cke)
2278 
       zq <= q_next == {length{1'b0}};
2279 
 
2280 
    always @ (posedge clk or posedge rst)
2281 
    if (rst)
2282 
        level1 <= 1'b0;
2283 
    else
2284 
    if (cke)
2285 29 unneback 
    if (clear)
2286 
        level1 <= 1'b0;
2287 
    else if (q_next == level1_value)
2288 25 unneback 
        level1 <= 1'b1;
2289 
    else if (qi == level1_value & rew)
2290 
        level1 <= 1'b0;
2291 
endmodule
2292 40 unneback 
`endif
2293 
`ifdef CNT_LFSR_ZQ
2294 25 unneback 
//////////////////////////////////////////////////////////////////////
2295 
////                                                              ////
2296 
////  Versatile counter                                           ////
2297 
////                                                              ////
2298 
////  Description                                                 ////
2299 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2300 
////  counter                                                     ////
2301 
////                                                              ////
2302 
////  To Do:                                                      ////
2303 
////   - add LFSR with more taps                                  ////
2304 
////                                                              ////
2305 
////  Author(s):                                                  ////
2306 
////      - Michael Unneback, unneback@opencores.org              ////
2307 
////        ORSoC AB                                              ////
2308 
////                                                              ////
2309 
//////////////////////////////////////////////////////////////////////
2310 
////                                                              ////
2311 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2312 
////                                                              ////
2313 
//// This source file may be used and distributed without         ////
2314 
//// restriction provided that this copyright statement is not    ////
2315 
//// removed from the file and that any derivative work contains  ////
2316 
//// the original copyright notice and the associated disclaimer. ////
2317 
////                                                              ////
2318 
//// This source file is free software; you can redistribute it   ////
2319 
//// and/or modify it under the terms of the GNU Lesser General   ////
2320 
//// Public License as published by the Free Software Foundation; ////
2321 
//// either version 2.1 of the License, or (at your option) any   ////
2322 
//// later version.                                               ////
2323 
////                                                              ////
2324 
//// This source is distributed in the hope that it will be       ////
2325 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2326 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2327 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2328 
//// details.                                                     ////
2329 
////                                                              ////
2330 
//// You should have received a copy of the GNU Lesser General    ////
2331 
//// Public License along with this source; if not, download it   ////
2332 
//// from http://www.opencores.org/lgpl.shtml                     ////
2333 
////                                                              ////
2334 
//////////////////////////////////////////////////////////////////////
2335 
 
2336 6 unneback 
// LFSR counter
2337 
 
2338 40 unneback 
`define MODULE cnt_lfsr_zq
2339 
module `BASE`MODULE (
2340 
`undef MODULE
2341 
 zq, rst, clk);
2342 
 
2343 6 unneback 
   parameter length = 4;
2344 
   output reg zq;
2345 
   input rst;
2346 
   input clk;
2347 
 
2348 
   parameter clear_value = 0;
2349 
   parameter set_value = 1;
2350 
   parameter wrap_value = 8;
2351 
   parameter level1_value = 15;
2352 
 
2353 
   reg  [length:1] qi;
2354 
   reg lfsr_fb;
2355 
   wire [length:1] q_next;
2356 
   reg [32:1] polynom;
2357 
   integer i;
2358 
 
2359 
   always @ (qi)
2360 
   begin
2361 
        case (length)
2362 
         2: polynom = 32'b11;                               // 0x3
2363 
         3: polynom = 32'b110;                              // 0x6
2364 
         4: polynom = 32'b1100;                             // 0xC
2365 
         5: polynom = 32'b10100;                            // 0x14
2366 
         6: polynom = 32'b110000;                           // 0x30
2367 
         7: polynom = 32'b1100000;                          // 0x60
2368 
         8: polynom = 32'b10111000;                         // 0xb8
2369 
         9: polynom = 32'b100010000;                        // 0x110
2370 
        10: polynom = 32'b1001000000;                       // 0x240
2371 
        11: polynom = 32'b10100000000;                      // 0x500
2372 
        12: polynom = 32'b100000101001;                     // 0x829
2373 
        13: polynom = 32'b1000000001100;                    // 0x100C
2374 
        14: polynom = 32'b10000000010101;                   // 0x2015
2375 
        15: polynom = 32'b110000000000000;                  // 0x6000
2376 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2377 
        17: polynom = 32'b10010000000000000;                // 0x12000
2378 
        18: polynom = 32'b100000010000000000;               // 0x20400
2379 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2380 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2381 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2382 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2383 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2384 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2385 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2386 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2387 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2388 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2389 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2390 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2391 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2392 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2393 
        default: polynom = 32'b0;
2394 
        endcase
2395 
        lfsr_fb = qi[length];
2396 
        for (i=length-1; i>=1; i=i-1) begin
2397 
            if (polynom[i])
2398 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2399 
        end
2400 
    end
2401 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2402 
 
2403 
   always @ (posedge clk or posedge rst)
2404 
     if (rst)
2405 
       qi <= {length{1'b0}};
2406 
     else
2407 
       qi <= q_next;
2408 
 
2409 
 
2410 
 
2411 
   always @ (posedge clk or posedge rst)
2412 
     if (rst)
2413 
       zq <= 1'b1;
2414 
     else
2415 
       zq <= q_next == {length{1'b0}};
2416 
endmodule
2417 40 unneback 
`endif
2418 75 unneback 
`ifdef CNT_LFSR_CE
2419 
//////////////////////////////////////////////////////////////////////
2420 
////                                                              ////
2421 
////  Versatile counter                                           ////
2422 
////                                                              ////
2423 
////  Description                                                 ////
2424 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2425 
////  counter                                                     ////
2426 
////                                                              ////
2427 
////  To Do:                                                      ////
2428 
////   - add LFSR with more taps                                  ////
2429 
////                                                              ////
2430 
////  Author(s):                                                  ////
2431 
////      - Michael Unneback, unneback@opencores.org              ////
2432 
////        ORSoC AB                                              ////
2433 
////                                                              ////
2434 
//////////////////////////////////////////////////////////////////////
2435 
////                                                              ////
2436 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2437 
////                                                              ////
2438 
//// This source file may be used and distributed without         ////
2439 
//// restriction provided that this copyright statement is not    ////
2440 
//// removed from the file and that any derivative work contains  ////
2441 
//// the original copyright notice and the associated disclaimer. ////
2442 
////                                                              ////
2443 
//// This source file is free software; you can redistribute it   ////
2444 
//// and/or modify it under the terms of the GNU Lesser General   ////
2445 
//// Public License as published by the Free Software Foundation; ////
2446 
//// either version 2.1 of the License, or (at your option) any   ////
2447 
//// later version.                                               ////
2448 
////                                                              ////
2449 
//// This source is distributed in the hope that it will be       ////
2450 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2451 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2452 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2453 
//// details.                                                     ////
2454 
////                                                              ////
2455 
//// You should have received a copy of the GNU Lesser General    ////
2456 
//// Public License along with this source; if not, download it   ////
2457 
//// from http://www.opencores.org/lgpl.shtml                     ////
2458 
////                                                              ////
2459 
//////////////////////////////////////////////////////////////////////
2460 
 
2461 
// LFSR counter
2462 
 
2463 
`define MODULE cnt_lfsr_ce
2464 
module `BASE`MODULE (
2465 
`undef MODULE
2466 
 cke, zq, rst, clk);
2467 
 
2468 
   parameter length = 4;
2469 
   input cke;
2470 
   output reg zq;
2471 
   input rst;
2472 
   input clk;
2473 
 
2474 
   parameter clear_value = 0;
2475 
   parameter set_value = 1;
2476 
   parameter wrap_value = 0;
2477 
   parameter level1_value = 15;
2478 
 
2479 
   reg  [length:1] qi;
2480 
   reg lfsr_fb;
2481 
   wire [length:1] q_next;
2482 
   reg [32:1] polynom;
2483 
   integer i;
2484 
 
2485 
   always @ (qi)
2486 
   begin
2487 
        case (length)
2488 
         2: polynom = 32'b11;                               // 0x3
2489 
         3: polynom = 32'b110;                              // 0x6
2490 
         4: polynom = 32'b1100;                             // 0xC
2491 
         5: polynom = 32'b10100;                            // 0x14
2492 
         6: polynom = 32'b110000;                           // 0x30
2493 
         7: polynom = 32'b1100000;                          // 0x60
2494 
         8: polynom = 32'b10111000;                         // 0xb8
2495 
         9: polynom = 32'b100010000;                        // 0x110
2496 
        10: polynom = 32'b1001000000;                       // 0x240
2497 
        11: polynom = 32'b10100000000;                      // 0x500
2498 
        12: polynom = 32'b100000101001;                     // 0x829
2499 
        13: polynom = 32'b1000000001100;                    // 0x100C
2500 
        14: polynom = 32'b10000000010101;                   // 0x2015
2501 
        15: polynom = 32'b110000000000000;                  // 0x6000
2502 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2503 
        17: polynom = 32'b10010000000000000;                // 0x12000
2504 
        18: polynom = 32'b100000010000000000;               // 0x20400
2505 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2506 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2507 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2508 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2509 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2510 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2511 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2512 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2513 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2514 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2515 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2516 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2517 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2518 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2519 
        default: polynom = 32'b0;
2520 
        endcase
2521 
        lfsr_fb = qi[length];
2522 
        for (i=length-1; i>=1; i=i-1) begin
2523 
            if (polynom[i])
2524 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2525 
        end
2526 
    end
2527 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2528 
 
2529 
   always @ (posedge clk or posedge rst)
2530 
     if (rst)
2531 
       qi <= {length{1'b0}};
2532 
     else
2533 
     if (cke)
2534 
       qi <= q_next;
2535 
 
2536 
 
2537 
 
2538 
   always @ (posedge clk or posedge rst)
2539 
     if (rst)
2540 
       zq <= 1'b1;
2541 
     else
2542 
     if (cke)
2543 
       zq <= q_next == {length{1'b0}};
2544 
endmodule
2545 
`endif
2546 40 unneback 
`ifdef CNT_LFSR_CE_ZQ
2547 6 unneback 
//////////////////////////////////////////////////////////////////////
2548 
////                                                              ////
2549 
////  Versatile counter                                           ////
2550 
////                                                              ////
2551 
////  Description                                                 ////
2552 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2553 
////  counter                                                     ////
2554 
////                                                              ////
2555 
////  To Do:                                                      ////
2556 
////   - add LFSR with more taps                                  ////
2557 
////                                                              ////
2558 
////  Author(s):                                                  ////
2559 
////      - Michael Unneback, unneback@opencores.org              ////
2560 
////        ORSoC AB                                              ////
2561 
////                                                              ////
2562 
//////////////////////////////////////////////////////////////////////
2563 
////                                                              ////
2564 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2565 
////                                                              ////
2566 
//// This source file may be used and distributed without         ////
2567 
//// restriction provided that this copyright statement is not    ////
2568 
//// removed from the file and that any derivative work contains  ////
2569 
//// the original copyright notice and the associated disclaimer. ////
2570 
////                                                              ////
2571 
//// This source file is free software; you can redistribute it   ////
2572 
//// and/or modify it under the terms of the GNU Lesser General   ////
2573 
//// Public License as published by the Free Software Foundation; ////
2574 
//// either version 2.1 of the License, or (at your option) any   ////
2575 
//// later version.                                               ////
2576 
////                                                              ////
2577 
//// This source is distributed in the hope that it will be       ////
2578 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2579 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2580 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2581 
//// details.                                                     ////
2582 
////                                                              ////
2583 
//// You should have received a copy of the GNU Lesser General    ////
2584 
//// Public License along with this source; if not, download it   ////
2585 
//// from http://www.opencores.org/lgpl.shtml                     ////
2586 
////                                                              ////
2587 
//////////////////////////////////////////////////////////////////////
2588 
 
2589 
// LFSR counter
2590 
 
2591 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2592 
module `BASE`MODULE (
2593 
`undef MODULE
2594 
 cke, zq, rst, clk);
2595 
 
2596 6 unneback 
   parameter length = 4;
2597 
   input cke;
2598 
   output reg zq;
2599 
   input rst;
2600 
   input clk;
2601 
 
2602 
   parameter clear_value = 0;
2603 
   parameter set_value = 1;
2604 
   parameter wrap_value = 8;
2605 
   parameter level1_value = 15;
2606 
 
2607 
   reg  [length:1] qi;
2608 
   reg lfsr_fb;
2609 
   wire [length:1] q_next;
2610 
   reg [32:1] polynom;
2611 
   integer i;
2612 
 
2613 
   always @ (qi)
2614 
   begin
2615 
        case (length)
2616 
         2: polynom = 32'b11;                               // 0x3
2617 
         3: polynom = 32'b110;                              // 0x6
2618 
         4: polynom = 32'b1100;                             // 0xC
2619 
         5: polynom = 32'b10100;                            // 0x14
2620 
         6: polynom = 32'b110000;                           // 0x30
2621 
         7: polynom = 32'b1100000;                          // 0x60
2622 
         8: polynom = 32'b10111000;                         // 0xb8
2623 
         9: polynom = 32'b100010000;                        // 0x110
2624 
        10: polynom = 32'b1001000000;                       // 0x240
2625 
        11: polynom = 32'b10100000000;                      // 0x500
2626 
        12: polynom = 32'b100000101001;                     // 0x829
2627 
        13: polynom = 32'b1000000001100;                    // 0x100C
2628 
        14: polynom = 32'b10000000010101;                   // 0x2015
2629 
        15: polynom = 32'b110000000000000;                  // 0x6000
2630 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2631 
        17: polynom = 32'b10010000000000000;                // 0x12000
2632 
        18: polynom = 32'b100000010000000000;               // 0x20400
2633 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2634 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2635 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2636 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2637 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2638 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2639 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2640 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2641 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2642 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2643 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2644 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2645 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2646 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2647 
        default: polynom = 32'b0;
2648 
        endcase
2649 
        lfsr_fb = qi[length];
2650 
        for (i=length-1; i>=1; i=i-1) begin
2651 
            if (polynom[i])
2652 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2653 
        end
2654 
    end
2655 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2656 
 
2657 
   always @ (posedge clk or posedge rst)
2658 
     if (rst)
2659 
       qi <= {length{1'b0}};
2660 
     else
2661 
     if (cke)
2662 
       qi <= q_next;
2663 
 
2664 
 
2665 
 
2666 
   always @ (posedge clk or posedge rst)
2667 
     if (rst)
2668 
       zq <= 1'b1;
2669 
     else
2670 
     if (cke)
2671 
       zq <= q_next == {length{1'b0}};
2672 
endmodule
2673 40 unneback 
`endif
2674 
`ifdef CNT_LFSR_CE_Q
2675 6 unneback 
//////////////////////////////////////////////////////////////////////
2676 
////                                                              ////
2677 
////  Versatile counter                                           ////
2678 
////                                                              ////
2679 
////  Description                                                 ////
2680 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2681 
////  counter                                                     ////
2682 
////                                                              ////
2683 
////  To Do:                                                      ////
2684 
////   - add LFSR with more taps                                  ////
2685 
////                                                              ////
2686 
////  Author(s):                                                  ////
2687 
////      - Michael Unneback, unneback@opencores.org              ////
2688 
////        ORSoC AB                                              ////
2689 
////                                                              ////
2690 
//////////////////////////////////////////////////////////////////////
2691 
////                                                              ////
2692 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2693 
////                                                              ////
2694 
//// This source file may be used and distributed without         ////
2695 
//// restriction provided that this copyright statement is not    ////
2696 
//// removed from the file and that any derivative work contains  ////
2697 
//// the original copyright notice and the associated disclaimer. ////
2698 
////                                                              ////
2699 
//// This source file is free software; you can redistribute it   ////
2700 
//// and/or modify it under the terms of the GNU Lesser General   ////
2701 
//// Public License as published by the Free Software Foundation; ////
2702 
//// either version 2.1 of the License, or (at your option) any   ////
2703 
//// later version.                                               ////
2704 
////                                                              ////
2705 
//// This source is distributed in the hope that it will be       ////
2706 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2707 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2708 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2709 
//// details.                                                     ////
2710 
////                                                              ////
2711 
//// You should have received a copy of the GNU Lesser General    ////
2712 
//// Public License along with this source; if not, download it   ////
2713 
//// from http://www.opencores.org/lgpl.shtml                     ////
2714 
////                                                              ////
2715 
//////////////////////////////////////////////////////////////////////
2716 22 unneback 
 
2717 
// LFSR counter
2718 27 unneback 
 
2719 40 unneback 
`define MODULE cnt_lfsr_ce_q
2720 
module `BASE`MODULE (
2721 
`undef MODULE
2722 
 cke, q, rst, clk);
2723 
 
2724 27 unneback 
   parameter length = 4;
2725 
   input cke;
2726 
   output [length:1] q;
2727 
   input rst;
2728 
   input clk;
2729 
 
2730 
   parameter clear_value = 0;
2731 
   parameter set_value = 1;
2732 
   parameter wrap_value = 8;
2733 
   parameter level1_value = 15;
2734 
 
2735 
   reg  [length:1] qi;
2736 
   reg lfsr_fb;
2737 
   wire [length:1] q_next;
2738 
   reg [32:1] polynom;
2739 
   integer i;
2740 
 
2741 
   always @ (qi)
2742 
   begin
2743 
        case (length)
2744 
         2: polynom = 32'b11;                               // 0x3
2745 
         3: polynom = 32'b110;                              // 0x6
2746 
         4: polynom = 32'b1100;                             // 0xC
2747 
         5: polynom = 32'b10100;                            // 0x14
2748 
         6: polynom = 32'b110000;                           // 0x30
2749 
         7: polynom = 32'b1100000;                          // 0x60
2750 
         8: polynom = 32'b10111000;                         // 0xb8
2751 
         9: polynom = 32'b100010000;                        // 0x110
2752 
        10: polynom = 32'b1001000000;                       // 0x240
2753 
        11: polynom = 32'b10100000000;                      // 0x500
2754 
        12: polynom = 32'b100000101001;                     // 0x829
2755 
        13: polynom = 32'b1000000001100;                    // 0x100C
2756 
        14: polynom = 32'b10000000010101;                   // 0x2015
2757 
        15: polynom = 32'b110000000000000;                  // 0x6000
2758 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2759 
        17: polynom = 32'b10010000000000000;                // 0x12000
2760 
        18: polynom = 32'b100000010000000000;               // 0x20400
2761 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2762 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2763 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2764 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2765 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2766 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2767 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2768 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2769 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2770 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2771 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2772 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2773 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2774 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2775 
        default: polynom = 32'b0;
2776 
        endcase
2777 
        lfsr_fb = qi[length];
2778 
        for (i=length-1; i>=1; i=i-1) begin
2779 
            if (polynom[i])
2780 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2781 
        end
2782 
    end
2783 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2784 
 
2785 
   always @ (posedge clk or posedge rst)
2786 
     if (rst)
2787 
       qi <= {length{1'b0}};
2788 
     else
2789 
     if (cke)
2790 
       qi <= q_next;
2791 
 
2792 
   assign q = qi;
2793 
 
2794 
endmodule
2795 40 unneback 
`endif
2796 
`ifdef CNT_LFSR_CE_CLEAR_Q
2797 27 unneback 
//////////////////////////////////////////////////////////////////////
2798 
////                                                              ////
2799 
////  Versatile counter                                           ////
2800 
////                                                              ////
2801 
////  Description                                                 ////
2802 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2803 
////  counter                                                     ////
2804 
////                                                              ////
2805 
////  To Do:                                                      ////
2806 
////   - add LFSR with more taps                                  ////
2807 
////                                                              ////
2808 
////  Author(s):                                                  ////
2809 
////      - Michael Unneback, unneback@opencores.org              ////
2810 
////        ORSoC AB                                              ////
2811 
////                                                              ////
2812 
//////////////////////////////////////////////////////////////////////
2813 
////                                                              ////
2814 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2815 
////                                                              ////
2816 
//// This source file may be used and distributed without         ////
2817 
//// restriction provided that this copyright statement is not    ////
2818 
//// removed from the file and that any derivative work contains  ////
2819 
//// the original copyright notice and the associated disclaimer. ////
2820 
////                                                              ////
2821 
//// This source file is free software; you can redistribute it   ////
2822 
//// and/or modify it under the terms of the GNU Lesser General   ////
2823 
//// Public License as published by the Free Software Foundation; ////
2824 
//// either version 2.1 of the License, or (at your option) any   ////
2825 
//// later version.                                               ////
2826 
////                                                              ////
2827 
//// This source is distributed in the hope that it will be       ////
2828 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2829 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2830 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2831 
//// details.                                                     ////
2832 
////                                                              ////
2833 
//// You should have received a copy of the GNU Lesser General    ////
2834 
//// Public License along with this source; if not, download it   ////
2835 
//// from http://www.opencores.org/lgpl.shtml                     ////
2836 
////                                                              ////
2837 
//////////////////////////////////////////////////////////////////////
2838 
 
2839 
// LFSR counter
2840 
 
2841 40 unneback 
`define MODULE cnt_lfsr_ce_clear_q
2842 
module `BASE`MODULE (
2843 
`undef MODULE
2844 
 clear, cke, q, rst, clk);
2845 
 
2846 27 unneback 
   parameter length = 4;
2847 
   input clear;
2848 
   input cke;
2849 
   output [length:1] q;
2850 
   input rst;
2851 
   input clk;
2852 
 
2853 
   parameter clear_value = 0;
2854 
   parameter set_value = 1;
2855 
   parameter wrap_value = 8;
2856 
   parameter level1_value = 15;
2857 
 
2858 
   reg  [length:1] qi;
2859 
   reg lfsr_fb;
2860 
   wire [length:1] q_next;
2861 
   reg [32:1] polynom;
2862 
   integer i;
2863 
 
2864 
   always @ (qi)
2865 
   begin
2866 
        case (length)
2867 
         2: polynom = 32'b11;                               // 0x3
2868 
         3: polynom = 32'b110;                              // 0x6
2869 
         4: polynom = 32'b1100;                             // 0xC
2870 
         5: polynom = 32'b10100;                            // 0x14
2871 
         6: polynom = 32'b110000;                           // 0x30
2872 
         7: polynom = 32'b1100000;                          // 0x60
2873 
         8: polynom = 32'b10111000;                         // 0xb8
2874 
         9: polynom = 32'b100010000;                        // 0x110
2875 
        10: polynom = 32'b1001000000;                       // 0x240
2876 
        11: polynom = 32'b10100000000;                      // 0x500
2877 
        12: polynom = 32'b100000101001;                     // 0x829
2878 
        13: polynom = 32'b1000000001100;                    // 0x100C
2879 
        14: polynom = 32'b10000000010101;                   // 0x2015
2880 
        15: polynom = 32'b110000000000000;                  // 0x6000
2881 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2882 
        17: polynom = 32'b10010000000000000;                // 0x12000
2883 
        18: polynom = 32'b100000010000000000;               // 0x20400
2884 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2885 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2886 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2887 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2888 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2889 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2890 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2891 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2892 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2893 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2894 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2895 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2896 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2897 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2898 
        default: polynom = 32'b0;
2899 
        endcase
2900 
        lfsr_fb = qi[length];
2901 
        for (i=length-1; i>=1; i=i-1) begin
2902 
            if (polynom[i])
2903 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2904 
        end
2905 
    end
2906 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2907 
 
2908 
   always @ (posedge clk or posedge rst)
2909 
     if (rst)
2910 
       qi <= {length{1'b0}};
2911 
     else
2912 
     if (cke)
2913 
       qi <= q_next;
2914 
 
2915 
   assign q = qi;
2916 
 
2917 
endmodule
2918 40 unneback 
`endif
2919 
`ifdef CNT_LFSR_CE_Q_ZQ
2920 27 unneback 
//////////////////////////////////////////////////////////////////////
2921 
////                                                              ////
2922 
////  Versatile counter                                           ////
2923 
////                                                              ////
2924 
////  Description                                                 ////
2925 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2926 
////  counter                                                     ////
2927 
////                                                              ////
2928 
////  To Do:                                                      ////
2929 
////   - add LFSR with more taps                                  ////
2930 
////                                                              ////
2931 
////  Author(s):                                                  ////
2932 
////      - Michael Unneback, unneback@opencores.org              ////
2933 
////        ORSoC AB                                              ////
2934 
////                                                              ////
2935 
//////////////////////////////////////////////////////////////////////
2936 
////                                                              ////
2937 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2938 
////                                                              ////
2939 
//// This source file may be used and distributed without         ////
2940 
//// restriction provided that this copyright statement is not    ////
2941 
//// removed from the file and that any derivative work contains  ////
2942 
//// the original copyright notice and the associated disclaimer. ////
2943 
////                                                              ////
2944 
//// This source file is free software; you can redistribute it   ////
2945 
//// and/or modify it under the terms of the GNU Lesser General   ////
2946 
//// Public License as published by the Free Software Foundation; ////
2947 
//// either version 2.1 of the License, or (at your option) any   ////
2948 
//// later version.                                               ////
2949 
////                                                              ////
2950 
//// This source is distributed in the hope that it will be       ////
2951 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2952 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2953 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2954 
//// details.                                                     ////
2955 
////                                                              ////
2956 
//// You should have received a copy of the GNU Lesser General    ////
2957 
//// Public License along with this source; if not, download it   ////
2958 
//// from http://www.opencores.org/lgpl.shtml                     ////
2959 
////                                                              ////
2960 
//////////////////////////////////////////////////////////////////////
2961 
 
2962 
// LFSR counter
2963 22 unneback 
 
2964 40 unneback 
`define MODULE cnt_lfsr_ce_q_zq
2965 
module `BASE`MODULE (
2966 
`undef MODULE
2967 
 cke, q, zq, rst, clk);
2968 
 
2969 22 unneback 
   parameter length = 4;
2970 
   input cke;
2971 
   output [length:1] q;
2972 
   output reg zq;
2973 
   input rst;
2974 
   input clk;
2975 
 
2976 
   parameter clear_value = 0;
2977 
   parameter set_value = 1;
2978 
   parameter wrap_value = 8;
2979 
   parameter level1_value = 15;
2980 
 
2981 
   reg  [length:1] qi;
2982 
   reg lfsr_fb;
2983 
   wire [length:1] q_next;
2984 
   reg [32:1] polynom;
2985 
   integer i;
2986 
 
2987 
   always @ (qi)
2988 
   begin
2989 
        case (length)
2990 
         2: polynom = 32'b11;                               // 0x3
2991 
         3: polynom = 32'b110;                              // 0x6
2992 
         4: polynom = 32'b1100;                             // 0xC
2993 
         5: polynom = 32'b10100;                            // 0x14
2994 
         6: polynom = 32'b110000;                           // 0x30
2995 
         7: polynom = 32'b1100000;                          // 0x60
2996 
         8: polynom = 32'b10111000;                         // 0xb8
2997 
         9: polynom = 32'b100010000;                        // 0x110
2998 
        10: polynom = 32'b1001000000;                       // 0x240
2999 
        11: polynom = 32'b10100000000;                      // 0x500
3000 
        12: polynom = 32'b100000101001;                     // 0x829
3001 
        13: polynom = 32'b1000000001100;                    // 0x100C
3002 
        14: polynom = 32'b10000000010101;                   // 0x2015
3003 
        15: polynom = 32'b110000000000000;                  // 0x6000
3004 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3005 
        17: polynom = 32'b10010000000000000;                // 0x12000
3006 
        18: polynom = 32'b100000010000000000;               // 0x20400
3007 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3008 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3009 22 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3010 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3011 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3012 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3013 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3014 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3015 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3016 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3017 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3018 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3019 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3020 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3021 
        default: polynom = 32'b0;
3022 
        endcase
3023 
        lfsr_fb = qi[length];
3024 
        for (i=length-1; i>=1; i=i-1) begin
3025 
            if (polynom[i])
3026 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3027 
        end
3028 
    end
3029 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3030 
 
3031 
   always @ (posedge clk or posedge rst)
3032 
     if (rst)
3033 
       qi <= {length{1'b0}};
3034 
     else
3035 
     if (cke)
3036 
       qi <= q_next;
3037 
 
3038 
   assign q = qi;
3039 
 
3040 
 
3041 
   always @ (posedge clk or posedge rst)
3042 
     if (rst)
3043 
       zq <= 1'b1;
3044 
     else
3045 
     if (cke)
3046 
       zq <= q_next == {length{1'b0}};
3047 
endmodule
3048 40 unneback 
`endif
3049 
`ifdef CNT_LFSR_CE_REW_L1
3050 22 unneback 
//////////////////////////////////////////////////////////////////////
3051 
////                                                              ////
3052 
////  Versatile counter                                           ////
3053 
////                                                              ////
3054 
////  Description                                                 ////
3055 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3056 
////  counter                                                     ////
3057 
////                                                              ////
3058 
////  To Do:                                                      ////
3059 
////   - add LFSR with more taps                                  ////
3060 
////                                                              ////
3061 
////  Author(s):                                                  ////
3062 
////      - Michael Unneback, unneback@opencores.org              ////
3063 
////        ORSoC AB                                              ////
3064 
////                                                              ////
3065 
//////////////////////////////////////////////////////////////////////
3066 
////                                                              ////
3067 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3068 
////                                                              ////
3069 
//// This source file may be used and distributed without         ////
3070 
//// restriction provided that this copyright statement is not    ////
3071 
//// removed from the file and that any derivative work contains  ////
3072 
//// the original copyright notice and the associated disclaimer. ////
3073 
////                                                              ////
3074 
//// This source file is free software; you can redistribute it   ////
3075 
//// and/or modify it under the terms of the GNU Lesser General   ////
3076 
//// Public License as published by the Free Software Foundation; ////
3077 
//// either version 2.1 of the License, or (at your option) any   ////
3078 
//// later version.                                               ////
3079 
////                                                              ////
3080 
//// This source is distributed in the hope that it will be       ////
3081 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3082 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3083 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3084 
//// details.                                                     ////
3085 
////                                                              ////
3086 
//// You should have received a copy of the GNU Lesser General    ////
3087 
//// Public License along with this source; if not, download it   ////
3088 
//// from http://www.opencores.org/lgpl.shtml                     ////
3089 
////                                                              ////
3090 
//////////////////////////////////////////////////////////////////////
3091 6 unneback 
 
3092 
// LFSR counter
3093 
 
3094 40 unneback 
`define MODULE cnt_lfsr_ce_rew_l1
3095 
module `BASE`MODULE (
3096 
`undef MODULE
3097 
 cke, rew, level1, rst, clk);
3098 
 
3099 6 unneback 
   parameter length = 4;
3100 
   input cke;
3101 
   input rew;
3102 
   output reg level1;
3103 
   input rst;
3104 
   input clk;
3105 
 
3106 
   parameter clear_value = 0;
3107 
   parameter set_value = 1;
3108 
   parameter wrap_value = 8;
3109 
   parameter level1_value = 15;
3110 
 
3111 29 unneback 
   wire clear;
3112 30 unneback 
   assign clear = 1'b0;
3113 6 unneback 
   reg  [length:1] qi;
3114 
   reg lfsr_fb, lfsr_fb_rew;
3115 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
3116 
   reg [32:1] polynom_rew;
3117 
   integer j;
3118 
   reg [32:1] polynom;
3119 
   integer i;
3120 
 
3121 
   always @ (qi)
3122 
   begin
3123 
        case (length)
3124 
         2: polynom = 32'b11;                               // 0x3
3125 
         3: polynom = 32'b110;                              // 0x6
3126 
         4: polynom = 32'b1100;                             // 0xC
3127 
         5: polynom = 32'b10100;                            // 0x14
3128 
         6: polynom = 32'b110000;                           // 0x30
3129 
         7: polynom = 32'b1100000;                          // 0x60
3130 
         8: polynom = 32'b10111000;                         // 0xb8
3131 
         9: polynom = 32'b100010000;                        // 0x110
3132 
        10: polynom = 32'b1001000000;                       // 0x240
3133 
        11: polynom = 32'b10100000000;                      // 0x500
3134 
        12: polynom = 32'b100000101001;                     // 0x829
3135 
        13: polynom = 32'b1000000001100;                    // 0x100C
3136 
        14: polynom = 32'b10000000010101;                   // 0x2015
3137 
        15: polynom = 32'b110000000000000;                  // 0x6000
3138 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3139 
        17: polynom = 32'b10010000000000000;                // 0x12000
3140 
        18: polynom = 32'b100000010000000000;               // 0x20400
3141 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3142 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3143 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3144 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3145 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3146 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3147 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3148 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3149 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3150 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3151 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3152 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3153 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3154 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3155 
        default: polynom = 32'b0;
3156 
        endcase
3157 
        lfsr_fb = qi[length];
3158 
        for (i=length-1; i>=1; i=i-1) begin
3159 
            if (polynom[i])
3160 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3161 
        end
3162 
    end
3163 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3164 
   always @ (qi)
3165 
   begin
3166 
        case (length)
3167 
         2: polynom_rew = 32'b11;
3168 
         3: polynom_rew = 32'b110;
3169 
         4: polynom_rew = 32'b1100;
3170 
         5: polynom_rew = 32'b10100;
3171 
         6: polynom_rew = 32'b110000;
3172 
         7: polynom_rew = 32'b1100000;
3173 
         8: polynom_rew = 32'b10111000;
3174 
         9: polynom_rew = 32'b100010000;
3175 
        10: polynom_rew = 32'b1001000000;
3176 
        11: polynom_rew = 32'b10100000000;
3177 
        12: polynom_rew = 32'b100000101001;
3178 
        13: polynom_rew = 32'b1000000001100;
3179 
        14: polynom_rew = 32'b10000000010101;
3180 
        15: polynom_rew = 32'b110000000000000;
3181 
        16: polynom_rew = 32'b1101000000001000;
3182 
        17: polynom_rew = 32'b10010000000000000;
3183 
        18: polynom_rew = 32'b100000010000000000;
3184 
        19: polynom_rew = 32'b1000000000000100011;
3185 
        20: polynom_rew = 32'b10000010000000000000;
3186 
        21: polynom_rew = 32'b101000000000000000000;
3187 
        22: polynom_rew = 32'b1100000000000000000000;
3188 
        23: polynom_rew = 32'b10000100000000000000000;
3189 
        24: polynom_rew = 32'b111000010000000000000000;
3190 
        25: polynom_rew = 32'b1001000000000000000000000;
3191 
        26: polynom_rew = 32'b10000000000000000000100011;
3192 
        27: polynom_rew = 32'b100000000000000000000010011;
3193 
        28: polynom_rew = 32'b1100100000000000000000000000;
3194 
        29: polynom_rew = 32'b10100000000000000000000000000;
3195 
        30: polynom_rew = 32'b100000000000000000000000101001;
3196 
        31: polynom_rew = 32'b1001000000000000000000000000000;
3197 
        32: polynom_rew = 32'b10000000001000000000000000000011;
3198 
        default: polynom_rew = 32'b0;
3199 
        endcase
3200 
        // rotate left
3201 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3202 
        lfsr_fb_rew = qi[length];
3203 
        for (i=length-1; i>=1; i=i-1) begin
3204 
            if (polynom_rew[i])
3205 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3206 
        end
3207 
    end
3208 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3209 
   assign q_next = rew ? q_next_rew : q_next_fw;
3210 
 
3211 
   always @ (posedge clk or posedge rst)
3212 
     if (rst)
3213 
       qi <= {length{1'b0}};
3214 
     else
3215 
     if (cke)
3216 
       qi <= q_next;
3217 
 
3218 
 
3219 
 
3220 
    always @ (posedge clk or posedge rst)
3221 
    if (rst)
3222 
        level1 <= 1'b0;
3223 
    else
3224 
    if (cke)
3225 29 unneback 
    if (clear)
3226 
        level1 <= 1'b0;
3227 
    else if (q_next == level1_value)
3228 6 unneback 
        level1 <= 1'b1;
3229 
    else if (qi == level1_value & rew)
3230 
        level1 <= 1'b0;
3231 
endmodule
3232 40 unneback 
`endif
3233 
`ifdef CNT_GRAY
3234 6 unneback 
//////////////////////////////////////////////////////////////////////
3235 
////                                                              ////
3236 
////  Versatile counter                                           ////
3237 
////                                                              ////
3238 
////  Description                                                 ////
3239 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3240 
////  counter                                                     ////
3241 
////                                                              ////
3242 
////  To Do:                                                      ////
3243 
////   - add LFSR with more taps                                  ////
3244 
////                                                              ////
3245 
////  Author(s):                                                  ////
3246 
////      - Michael Unneback, unneback@opencores.org              ////
3247 
////        ORSoC AB                                              ////
3248 
////                                                              ////
3249 
//////////////////////////////////////////////////////////////////////
3250 
////                                                              ////
3251 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3252 
////                                                              ////
3253 
//// This source file may be used and distributed without         ////
3254 
//// restriction provided that this copyright statement is not    ////
3255 
//// removed from the file and that any derivative work contains  ////
3256 
//// the original copyright notice and the associated disclaimer. ////
3257 
////                                                              ////
3258 
//// This source file is free software; you can redistribute it   ////
3259 
//// and/or modify it under the terms of the GNU Lesser General   ////
3260 
//// Public License as published by the Free Software Foundation; ////
3261 
//// either version 2.1 of the License, or (at your option) any   ////
3262 
//// later version.                                               ////
3263 
////                                                              ////
3264 
//// This source is distributed in the hope that it will be       ////
3265 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3266 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3267 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3268 
//// details.                                                     ////
3269 
////                                                              ////
3270 
//// You should have received a copy of the GNU Lesser General    ////
3271 
//// Public License along with this source; if not, download it   ////
3272 
//// from http://www.opencores.org/lgpl.shtml                     ////
3273 
////                                                              ////
3274 
//////////////////////////////////////////////////////////////////////
3275 
 
3276 
// GRAY counter
3277 
 
3278 40 unneback 
`define MODULE cnt_gray
3279 
module `BASE`MODULE (
3280 
`undef MODULE
3281 
 q, rst, clk);
3282 
 
3283 6 unneback 
   parameter length = 4;
3284 
   output reg [length:1] q;
3285 
   input rst;
3286 
   input clk;
3287 
 
3288 
   parameter clear_value = 0;
3289 
   parameter set_value = 1;
3290 
   parameter wrap_value = 8;
3291 
   parameter level1_value = 15;
3292 
 
3293 
   reg  [length:1] qi;
3294 
   wire [length:1] q_next;
3295 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3296 
 
3297 
   always @ (posedge clk or posedge rst)
3298 
     if (rst)
3299 
       qi <= {length{1'b0}};
3300 
     else
3301 
       qi <= q_next;
3302 
 
3303 
   always @ (posedge clk or posedge rst)
3304 
     if (rst)
3305 
       q <= {length{1'b0}};
3306 
     else
3307 
         q <= (q_next>>1) ^ q_next;
3308 
 
3309 
endmodule
3310 40 unneback 
`endif
3311 
`ifdef CNT_GRAY_CE
3312 6 unneback 
//////////////////////////////////////////////////////////////////////
3313 
////                                                              ////
3314 
////  Versatile counter                                           ////
3315 
////                                                              ////
3316 
////  Description                                                 ////
3317 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3318 
////  counter                                                     ////
3319 
////                                                              ////
3320 
////  To Do:                                                      ////
3321 
////   - add LFSR with more taps                                  ////
3322 
////                                                              ////
3323 
////  Author(s):                                                  ////
3324 
////      - Michael Unneback, unneback@opencores.org              ////
3325 
////        ORSoC AB                                              ////
3326 
////                                                              ////
3327 
//////////////////////////////////////////////////////////////////////
3328 
////                                                              ////
3329 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3330 
////                                                              ////
3331 
//// This source file may be used and distributed without         ////
3332 
//// restriction provided that this copyright statement is not    ////
3333 
//// removed from the file and that any derivative work contains  ////
3334 
//// the original copyright notice and the associated disclaimer. ////
3335 
////                                                              ////
3336 
//// This source file is free software; you can redistribute it   ////
3337 
//// and/or modify it under the terms of the GNU Lesser General   ////
3338 
//// Public License as published by the Free Software Foundation; ////
3339 
//// either version 2.1 of the License, or (at your option) any   ////
3340 
//// later version.                                               ////
3341 
////                                                              ////
3342 
//// This source is distributed in the hope that it will be       ////
3343 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3344 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3345 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3346 
//// details.                                                     ////
3347 
////                                                              ////
3348 
//// You should have received a copy of the GNU Lesser General    ////
3349 
//// Public License along with this source; if not, download it   ////
3350 
//// from http://www.opencores.org/lgpl.shtml                     ////
3351 
////                                                              ////
3352 
//////////////////////////////////////////////////////////////////////
3353 
 
3354 
// GRAY counter
3355 
 
3356 40 unneback 
`define MODULE cnt_gray_ce
3357 
module `BASE`MODULE (
3358 
`undef MODULE
3359 
 cke, q, rst, clk);
3360 
 
3361 6 unneback 
   parameter length = 4;
3362 
   input cke;
3363 
   output reg [length:1] q;
3364 
   input rst;
3365 
   input clk;
3366 
 
3367 
   parameter clear_value = 0;
3368 
   parameter set_value = 1;
3369 
   parameter wrap_value = 8;
3370 
   parameter level1_value = 15;
3371 
 
3372 
   reg  [length:1] qi;
3373 
   wire [length:1] q_next;
3374 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3375 
 
3376 
   always @ (posedge clk or posedge rst)
3377 
     if (rst)
3378 
       qi <= {length{1'b0}};
3379 
     else
3380 
     if (cke)
3381 
       qi <= q_next;
3382 
 
3383 
   always @ (posedge clk or posedge rst)
3384 
     if (rst)
3385 
       q <= {length{1'b0}};
3386 
     else
3387 
       if (cke)
3388 
         q <= (q_next>>1) ^ q_next;
3389 
 
3390 
endmodule
3391 40 unneback 
`endif
3392 
`ifdef CNT_GRAY_CE_BIN
3393 6 unneback 
//////////////////////////////////////////////////////////////////////
3394 
////                                                              ////
3395 
////  Versatile counter                                           ////
3396 
////                                                              ////
3397 
////  Description                                                 ////
3398 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3399 
////  counter                                                     ////
3400 
////                                                              ////
3401 
////  To Do:                                                      ////
3402 
////   - add LFSR with more taps                                  ////
3403 
////                                                              ////
3404 
////  Author(s):                                                  ////
3405 
////      - Michael Unneback, unneback@opencores.org              ////
3406 
////        ORSoC AB                                              ////
3407 
////                                                              ////
3408 
//////////////////////////////////////////////////////////////////////
3409 
////                                                              ////
3410 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3411 
////                                                              ////
3412 
//// This source file may be used and distributed without         ////
3413 
//// restriction provided that this copyright statement is not    ////
3414 
//// removed from the file and that any derivative work contains  ////
3415 
//// the original copyright notice and the associated disclaimer. ////
3416 
////                                                              ////
3417 
//// This source file is free software; you can redistribute it   ////
3418 
//// and/or modify it under the terms of the GNU Lesser General   ////
3419 
//// Public License as published by the Free Software Foundation; ////
3420 
//// either version 2.1 of the License, or (at your option) any   ////
3421 
//// later version.                                               ////
3422 
////                                                              ////
3423 
//// This source is distributed in the hope that it will be       ////
3424 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3425 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3426 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3427 
//// details.                                                     ////
3428 
////                                                              ////
3429 
//// You should have received a copy of the GNU Lesser General    ////
3430 
//// Public License along with this source; if not, download it   ////
3431 
//// from http://www.opencores.org/lgpl.shtml                     ////
3432 
////                                                              ////
3433 
//////////////////////////////////////////////////////////////////////
3434 
 
3435 
// GRAY counter
3436 
 
3437 40 unneback 
`define MODULE cnt_gray_ce_bin
3438 
module `BASE`MODULE (
3439 
`undef MODULE
3440 
 cke, q, q_bin, rst, clk);
3441 
 
3442 6 unneback 
   parameter length = 4;
3443 
   input cke;
3444 
   output reg [length:1] q;
3445 
   output [length:1] q_bin;
3446 
   input rst;
3447 
   input clk;
3448 
 
3449 
   parameter clear_value = 0;
3450 
   parameter set_value = 1;
3451 
   parameter wrap_value = 8;
3452 
   parameter level1_value = 15;
3453 
 
3454 
   reg  [length:1] qi;
3455 
   wire [length:1] q_next;
3456 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3457 
 
3458 
   always @ (posedge clk or posedge rst)
3459 
     if (rst)
3460 
       qi <= {length{1'b0}};
3461 
     else
3462 
     if (cke)
3463 
       qi <= q_next;
3464 
 
3465 
   always @ (posedge clk or posedge rst)
3466 
     if (rst)
3467 
       q <= {length{1'b0}};
3468 
     else
3469 
       if (cke)
3470 
         q <= (q_next>>1) ^ q_next;
3471 
 
3472 
   assign q_bin = qi;
3473 
 
3474 
endmodule
3475 40 unneback 
`endif
3476 6 unneback 
//////////////////////////////////////////////////////////////////////
3477 
////                                                              ////
3478 
////  Versatile library, counters                                 ////
3479 
////                                                              ////
3480 
////  Description                                                 ////
3481 
////  counters                                                    ////
3482 
////                                                              ////
3483 
////                                                              ////
3484 
////  To Do:                                                      ////
3485 
////   - add more counters                                        ////
3486 
////                                                              ////
3487 
////  Author(s):                                                  ////
3488 
////      - Michael Unneback, unneback@opencores.org              ////
3489 
////        ORSoC AB                                              ////
3490 
////                                                              ////
3491 
//////////////////////////////////////////////////////////////////////
3492 
////                                                              ////
3493 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3494 
////                                                              ////
3495 
//// This source file may be used and distributed without         ////
3496 
//// restriction provided that this copyright statement is not    ////
3497 
//// removed from the file and that any derivative work contains  ////
3498 
//// the original copyright notice and the associated disclaimer. ////
3499 
////                                                              ////
3500 
//// This source file is free software; you can redistribute it   ////
3501 
//// and/or modify it under the terms of the GNU Lesser General   ////
3502 
//// Public License as published by the Free Software Foundation; ////
3503 
//// either version 2.1 of the License, or (at your option) any   ////
3504 
//// later version.                                               ////
3505 
////                                                              ////
3506 
//// This source is distributed in the hope that it will be       ////
3507 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3508 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3509 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3510 
//// details.                                                     ////
3511 
////                                                              ////
3512 
//// You should have received a copy of the GNU Lesser General    ////
3513 
//// Public License along with this source; if not, download it   ////
3514 
//// from http://www.opencores.org/lgpl.shtml                     ////
3515 
////                                                              ////
3516 
//////////////////////////////////////////////////////////////////////
3517 
 
3518 40 unneback 
`ifdef CNT_SHREG_WRAP
3519 
`define MODULE cnt_shreg_wrap
3520 
module `BASE`MODULE ( q, rst, clk);
3521 
`undef MODULE
3522 6 unneback 
 
3523 
   parameter length = 4;
3524 
   output reg [0:length-1] q;
3525 
   input rst;
3526 
   input clk;
3527 
 
3528 
    always @ (posedge clk or posedge rst)
3529 
    if (rst)
3530 
        q <= {1'b1,{length-1{1'b0}}};
3531 
    else
3532 
        q <= {q[length-1],q[0:length-2]};
3533 
 
3534 
endmodule
3535 40 unneback 
`endif
3536 6 unneback 
 
3537 40 unneback 
`ifdef CNT_SHREG_CE_WRAP
3538 
`define MODULE cnt_shreg_ce_wrap
3539 
module `BASE`MODULE ( cke, q, rst, clk);
3540 
`undef MODULE
3541 6 unneback 
 
3542 
   parameter length = 4;
3543 
   input cke;
3544 
   output reg [0:length-1] q;
3545 
   input rst;
3546 
   input clk;
3547 
 
3548 
    always @ (posedge clk or posedge rst)
3549 
    if (rst)
3550 
        q <= {1'b1,{length-1{1'b0}}};
3551 
    else
3552 
        if (cke)
3553 
            q <= {q[length-1],q[0:length-2]};
3554 
 
3555 
endmodule
3556 40 unneback 
`endif
3557 6 unneback 
 
3558 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR
3559 
`define MODULE cnt_shreg_ce_clear
3560 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3561 
`undef MODULE
3562 6 unneback 
 
3563 
   parameter length = 4;
3564 
   input cke, clear;
3565 
   output reg [0:length-1] q;
3566 
   input rst;
3567 
   input clk;
3568 
 
3569 
    always @ (posedge clk or posedge rst)
3570 
    if (rst)
3571 
        q <= {1'b1,{length-1{1'b0}}};
3572 
    else
3573 
        if (cke)
3574 
            if (clear)
3575 
                q <= {1'b1,{length-1{1'b0}}};
3576 
            else
3577 
                q <= q >> 1;
3578 
 
3579 
endmodule
3580 40 unneback 
`endif
3581 6 unneback 
 
3582 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3583 
`define MODULE cnt_shreg_ce_clear_wrap
3584 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3585 
`undef MODULE
3586 6 unneback 
 
3587 
   parameter length = 4;
3588 
   input cke, clear;
3589 
   output reg [0:length-1] q;
3590 
   input rst;
3591 
   input clk;
3592 
 
3593 
    always @ (posedge clk or posedge rst)
3594 
    if (rst)
3595 
        q <= {1'b1,{length-1{1'b0}}};
3596 
    else
3597 
        if (cke)
3598 
            if (clear)
3599 
                q <= {1'b1,{length-1{1'b0}}};
3600 
            else
3601 
            q <= {q[length-1],q[0:length-2]};
3602 
 
3603 
endmodule
3604 40 unneback 
`endif
3605 6 unneback 
//////////////////////////////////////////////////////////////////////
3606 
////                                                              ////
3607 
////  Versatile library, memories                                 ////
3608 
////                                                              ////
3609 
////  Description                                                 ////
3610 
////  memories                                                    ////
3611 
////                                                              ////
3612 
////                                                              ////
3613 
////  To Do:                                                      ////
3614 
////   - add more memory types                                    ////
3615 
////                                                              ////
3616 
////  Author(s):                                                  ////
3617 
////      - Michael Unneback, unneback@opencores.org              ////
3618 
////        ORSoC AB                                              ////
3619 
////                                                              ////
3620 
//////////////////////////////////////////////////////////////////////
3621 
////                                                              ////
3622 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3623 
////                                                              ////
3624 
//// This source file may be used and distributed without         ////
3625 
//// restriction provided that this copyright statement is not    ////
3626 
//// removed from the file and that any derivative work contains  ////
3627 
//// the original copyright notice and the associated disclaimer. ////
3628 
////                                                              ////
3629 
//// This source file is free software; you can redistribute it   ////
3630 
//// and/or modify it under the terms of the GNU Lesser General   ////
3631 
//// Public License as published by the Free Software Foundation; ////
3632 
//// either version 2.1 of the License, or (at your option) any   ////
3633 
//// later version.                                               ////
3634 
////                                                              ////
3635 
//// This source is distributed in the hope that it will be       ////
3636 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3637 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3638 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3639 
//// details.                                                     ////
3640 
////                                                              ////
3641 
//// You should have received a copy of the GNU Lesser General    ////
3642 
//// Public License along with this source; if not, download it   ////
3643 
//// from http://www.opencores.org/lgpl.shtml                     ////
3644 
////                                                              ////
3645 
//////////////////////////////////////////////////////////////////////
3646 
 
3647 40 unneback 
`ifdef ROM_INIT
3648 6 unneback 
/// ROM
3649 40 unneback 
`define MODULE rom_init
3650 
module `BASE`MODULE ( adr, q, clk);
3651 
`undef MODULE
3652 6 unneback 
 
3653 7 unneback 
   parameter data_width = 32;
3654 
   parameter addr_width = 8;
3655 75 unneback 
   parameter mem_size = 1<<addr_width;
3656 7 unneback 
   input [(addr_width-1):0]       adr;
3657 
   output reg [(data_width-1):0] q;
3658 
   input                         clk;
3659 75 unneback 
   reg [data_width-1:0] rom [mem_size-1:0];
3660 7 unneback 
   parameter memory_file = "vl_rom.vmem";
3661 
   initial
3662 
     begin
3663 
        $readmemh(memory_file, rom);
3664 
     end
3665 
 
3666 
   always @ (posedge clk)
3667 
     q <= rom[adr];
3668 6 unneback 
 
3669 7 unneback 
endmodule
3670 40 unneback 
`endif
3671 7 unneback 
 
3672 40 unneback 
`ifdef RAM
3673 
`define MODULE ram
3674 6 unneback 
// Single port RAM
3675 40 unneback 
module `BASE`MODULE ( d, adr, we, q, clk);
3676 
`undef MODULE
3677 6 unneback 
 
3678 
   parameter data_width = 32;
3679 
   parameter addr_width = 8;
3680 75 unneback 
   parameter mem_size = 1<<addr_width;
3681 6 unneback 
   input [(data_width-1):0]      d;
3682 
   input [(addr_width-1):0]       adr;
3683 
   input                         we;
3684 7 unneback 
   output reg [(data_width-1):0] q;
3685 6 unneback 
   input                         clk;
3686 75 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0];
3687 7 unneback 
   parameter init = 0;
3688 
   parameter memory_file = "vl_ram.vmem";
3689 
   generate if (init) begin : init_mem
3690 
   initial
3691 
     begin
3692 
        $readmemh(memory_file, ram);
3693 
     end
3694 
   end
3695 
   endgenerate
3696 
 
3697 6 unneback 
   always @ (posedge clk)
3698 
   begin
3699 
   if (we)
3700 
     ram[adr] <= d;
3701 
   q <= ram[adr];
3702 
   end
3703 
 
3704 
endmodule
3705 40 unneback 
`endif
3706 6 unneback 
 
3707 40 unneback 
`ifdef RAM_BE
3708 
`define MODULE ram_be
3709 
module `BASE`MODULE ( d, adr, be, we, q, clk);
3710 
`undef MODULE
3711 
 
3712 7 unneback 
   parameter data_width = 32;
3713 72 unneback 
   parameter addr_width = 6;
3714 75 unneback 
   parameter mem_size = 1<<addr_width;
3715 7 unneback 
   input [(data_width-1):0]      d;
3716 
   input [(addr_width-1):0]       adr;
3717 73 unneback 
   input [(data_width/8)-1:0]    be;
3718 7 unneback 
   input                         we;
3719 
   output reg [(data_width-1):0] q;
3720 
   input                         clk;
3721 
 
3722 65 unneback 
`ifdef SYSTEMVERILOG
3723 68 unneback 
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
3724 65 unneback 
`else
3725 68 unneback 
   reg [data_width-1:0] ram [mem_size-1:0];
3726 65 unneback 
`endif
3727 
 
3728 60 unneback 
   parameter memory_init = 0;
3729 7 unneback 
   parameter memory_file = "vl_ram.vmem";
3730 60 unneback 
   generate if (memory_init) begin : init_mem
3731 7 unneback 
   initial
3732 
     begin
3733 
        $readmemh(memory_file, ram);
3734 
     end
3735 
   end
3736 
   endgenerate
3737 
 
3738 60 unneback 
`ifdef SYSTEMVERILOG
3739 
// use a multi-dimensional packed array
3740 
//to model individual bytes within the word
3741 
 
3742 
always_ff@(posedge clk)
3743 
begin
3744 
    if(we) begin // note: we should have a for statement to support any bus width
3745 65 unneback 
        if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
3746 
        if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
3747 
        if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
3748 
        if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
3749 60 unneback 
    end
3750 65 unneback 
    q <= ram[adr];
3751 60 unneback 
end
3752 
 
3753 
`else
3754 
 
3755 7 unneback 
   genvar i;
3756 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
3757 
      always @ (posedge clk)
3758 
      if (we & be[i])
3759 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3760 
   end
3761 
   endgenerate
3762 
 
3763 
   always @ (posedge clk)
3764 
      q <= ram[adr];
3765 
 
3766 60 unneback 
`endif
3767 
 
3768 7 unneback 
endmodule
3769 40 unneback 
`endif
3770 7 unneback 
 
3771 6 unneback 
`ifdef ACTEL
3772 48 unneback 
        // ACTEL FPGA should not use logic to handle rw collision
3773 6 unneback 
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
3774 
`else
3775 
        `define SYN
3776 
`endif
3777 
 
3778 40 unneback 
`ifdef DPRAM_1R1W
3779 
`define MODULE dpram_1r1w
3780 
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3781 
`undef MODULE
3782 6 unneback 
   parameter data_width = 32;
3783 
   parameter addr_width = 8;
3784 75 unneback 
   parameter mem_size = 1<<addr_width;
3785 6 unneback 
   input [(data_width-1):0]      d_a;
3786 
   input [(addr_width-1):0]       adr_a;
3787 
   input [(addr_width-1):0]       adr_b;
3788 
   input                         we_a;
3789 
   output [(data_width-1):0]      q_b;
3790 
   input                         clk_a, clk_b;
3791 
   reg [(addr_width-1):0]         adr_b_reg;
3792 75 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
3793 7 unneback 
 
3794 
   parameter init = 0;
3795 
   parameter memory_file = "vl_ram.vmem";
3796 
   generate if (init) begin : init_mem
3797 
   initial
3798 
     begin
3799 
        $readmemh(memory_file, ram);
3800 
     end
3801 
   end
3802 
   endgenerate
3803 
 
3804 6 unneback 
   always @ (posedge clk_a)
3805 
   if (we_a)
3806 
     ram[adr_a] <= d_a;
3807 
   always @ (posedge clk_b)
3808 
   adr_b_reg <= adr_b;
3809 
   assign q_b = ram[adr_b_reg];
3810 40 unneback 
 
3811 6 unneback 
endmodule
3812 40 unneback 
`endif
3813 6 unneback 
 
3814 40 unneback 
`ifdef DPRAM_2R1W
3815 
`define MODULE dpram_2r1w
3816 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3817 
`undef MODULE
3818 
 
3819 6 unneback 
   parameter data_width = 32;
3820 
   parameter addr_width = 8;
3821 75 unneback 
   parameter mem_size = 1<<addr_width;
3822 6 unneback 
   input [(data_width-1):0]      d_a;
3823 
   input [(addr_width-1):0]       adr_a;
3824 
   input [(addr_width-1):0]       adr_b;
3825 
   input                         we_a;
3826 
   output [(data_width-1):0]      q_b;
3827 
   output reg [(data_width-1):0] q_a;
3828 
   input                         clk_a, clk_b;
3829 
   reg [(data_width-1):0]         q_b;
3830 75 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
3831 7 unneback 
 
3832 
   parameter init = 0;
3833 
   parameter memory_file = "vl_ram.vmem";
3834 
   generate if (init) begin : init_mem
3835 
   initial
3836 
     begin
3837 
        $readmemh(memory_file, ram);
3838 
     end
3839 
   end
3840 
   endgenerate
3841 
 
3842 6 unneback 
   always @ (posedge clk_a)
3843 
     begin
3844 
        q_a <= ram[adr_a];
3845 
        if (we_a)
3846 
             ram[adr_a] <= d_a;
3847 
     end
3848 
   always @ (posedge clk_b)
3849 
          q_b <= ram[adr_b];
3850 
endmodule
3851 40 unneback 
`endif
3852 6 unneback 
 
3853 40 unneback 
`ifdef DPRAM_2R2W
3854 
`define MODULE dpram_2r2w
3855 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3856 
`undef MODULE
3857 
 
3858 6 unneback 
   parameter data_width = 32;
3859 
   parameter addr_width = 8;
3860 75 unneback 
   parameter mem_size = 1<<addr_width;
3861 6 unneback 
   input [(data_width-1):0]      d_a;
3862 
   input [(addr_width-1):0]       adr_a;
3863 
   input [(addr_width-1):0]       adr_b;
3864 
   input                         we_a;
3865 
   output [(data_width-1):0]      q_b;
3866 
   input [(data_width-1):0]       d_b;
3867 
   output reg [(data_width-1):0] q_a;
3868 
   input                         we_b;
3869 
   input                         clk_a, clk_b;
3870 
   reg [(data_width-1):0]         q_b;
3871 75 unneback 
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
3872 7 unneback 
 
3873 
   parameter init = 0;
3874 
   parameter memory_file = "vl_ram.vmem";
3875 
   generate if (init) begin : init_mem
3876 
   initial
3877 
     begin
3878 
        $readmemh(memory_file, ram);
3879 
     end
3880 
   end
3881 
   endgenerate
3882 
 
3883 6 unneback 
   always @ (posedge clk_a)
3884 
     begin
3885 
        q_a <= ram[adr_a];
3886 
        if (we_a)
3887 
             ram[adr_a] <= d_a;
3888 
     end
3889 
   always @ (posedge clk_b)
3890 
     begin
3891 
        q_b <= ram[adr_b];
3892 
        if (we_b)
3893 
          ram[adr_b] <= d_b;
3894 
     end
3895 
endmodule
3896 40 unneback 
`endif
3897 6 unneback 
 
3898 75 unneback 
`ifdef DPRAM_BE_2R2W
3899 
`define MODULE dpram_be_2r2w
3900 
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
3901 
`undef MODULE
3902 
 
3903 
   parameter a_data_width = 32;
3904 
   parameter a_addr_width = 8;
3905 
   parameter b_data_width = 64;
3906 
   parameter b_addr_width = 7;
3907 
   //parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
3908 
   parameter mem_size = 1024;
3909 
   input [(a_data_width-1):0]      d_a;
3910 
   input [(a_addr_width-1):0]     adr_a;
3911 
   input [(b_addr_width-1):0]     adr_b;
3912 
   input [(a_data_width/4-1):0]    be_a;
3913 
   input                         we_a;
3914 
   output [(b_data_width-1):0]    q_b;
3915 
   input [(b_data_width-1):0]     d_b;
3916 
   output reg [(a_data_width-1):0] q_a;
3917 
   input [(b_data_width/4-1):0]    be_b;
3918 
   input                         we_b;
3919 
   input                         clk_a, clk_b;
3920 
   reg [(b_data_width-1):0]       q_b;
3921 
 
3922 
generate
3923 
if (a_data_width==32 & b_data_width==64) begin : inst32to64
3924 
 
3925 
    wire [63:0] temp;
3926 
    `define MODULE dpram_2r2w
3927 
    `BASE`MODULE
3928 
    # (.data_width(8), .addr_width(b_addr_width-3))
3929 
    ram0 (
3930 
        .d_a(d_a[7:0]),
3931 
        .q_a(tmp[7:0]),
3932 
        .adr_a(adr_a[a_addr_width-3-1:0]),
3933 
        .we_a(we_a & be_a[0] & !adr_a[0]),
3934 
        .clk_a(clk_a),
3935 
        .d_b(d_b[7:0]),
3936 
        .q_b(q_b[7:0]),
3937 
        .adr_b(adr_b[b_addr_width-3-1:0]),
3938 
        .we_b(we_b),
3939 
        .clk_b(clk_b) );
3940 
    `BASE`MODULE
3941 
    # (.data_width(8), .addr_width(b_addr_width-3))
3942 
    ram1 (
3943 
        .d_a(d_a[7:0]),
3944 
        .q_a(tmp[7:0]),
3945 
        .adr_a(adr_a[a_addr_width-3-1:0]),
3946 
        .we_a(we_a),
3947 
        .clk_a(clk_a),
3948 
        .d_b(d_b[7:0]),
3949 
        .q_b(q_b[7:0]),
3950 
        .adr_b(adr_b[b_addr_width-3-1:0]),
3951 
        .we_b(we_b),
3952 
        .clk_b(clk_b) );
3953 
    `BASE`MODULE
3954 
    # (.data_width(8), .addr_width(b_addr_width-3))
3955 
    ram2 (
3956 
        .d_a(d_a[15:8]),
3957 
        .q_a(tmp[7:0]),
3958 
        .adr_a(adr_a[a_addr_width-3-1:0]),
3959 
        .we_a(we_a),
3960 
        .clk_a(clk_a),
3961 
        .d_b(d_b[7:0]),
3962 
        .q_b(q_b[7:0]),
3963 
        .adr_b(adr_b[b_addr_width-3-1:0]),
3964 
        .we_b(we_b),
3965 
        .clk_b(clk_b) );
3966 
    `BASE`MODULE
3967 
    # (.data_width(8), .addr_width(b_addr_width-3))
3968 
    ram3 (
3969 
        .d_a(d_a[15:8]),
3970 
        .q_a(tmp[7:0]),
3971 
        .adr_a(adr_a[a_addr_width-3-1:0]),
3972 
        .we_a(we_a),
3973 
        .clk_a(clk_a),
3974 
        .d_b(d_b[7:0]),
3975 
        .q_b(q_b[7:0]),
3976 
        .adr_b(adr_b[b_addr_width-3-1:0]),
3977 
        .we_b(we_b),
3978 
        .clk_b(clk_b) );
3979 
    `BASE`MODULE
3980 
    # (.data_width(8), .addr_width(b_addr_width-3))
3981 
    ram4 (
3982 
        .d_a(d_a[23:16]),
3983 
        .q_a(tmp[7:0]),
3984 
        .adr_a(adr_a[a_addr_width-3-1:0]),
3985 
        .we_a(we_a),
3986 
        .clk_a(clk_a),
3987 
        .d_b(d_b[7:0]),
3988 
        .q_b(q_b[7:0]),
3989 
        .adr_b(adr_b[b_addr_width-3-1:0]),
3990 
        .we_b(we_b),
3991 
        .clk_b(clk_b) );
3992 
    `BASE`MODULE
3993 
    # (.data_width(8), .addr_width(b_addr_width-3))
3994 
    ram5 (
3995 
        .d_a(d_a[23:16]),
3996 
        .q_a(tmp[7:0]),
3997 
        .adr_a(adr_a[a_addr_width-3-1:0]),
3998 
        .we_a(we_a),
3999 
        .clk_a(clk_a),
4000 
        .d_b(d_b[7:0]),
4001 
        .q_b(q_b[7:0]),
4002 
        .adr_b(adr_b[b_addr_width-3-1:0]),
4003 
        .we_b(we_b),
4004 
        .clk_b(clk_b) );
4005 
    `BASE`MODULE
4006 
    # (.data_width(8), .addr_width(b_addr_width-3))
4007 
    ram6 (
4008 
        .d_a(d_a[31:24]),
4009 
        .q_a(tmp[7:0]),
4010 
        .adr_a(adr_a[a_addr_width-3-1:0]),
4011 
        .we_a(we_a),
4012 
        .clk_a(clk_a),
4013 
        .d_b(d_b[7:0]),
4014 
        .q_b(q_b[7:0]),
4015 
        .adr_b(adr_b[b_addr_width-3-1:0]),
4016 
        .we_b(we_b),
4017 
        .clk_b(clk_b) );
4018 
    `BASE`MODULE
4019 
    # (.data_width(8), .addr_width(b_addr_width-3))
4020 
    ram7 (
4021 
        .d_a(d_a[31:24]),
4022 
        .q_a(tmp[7:0]),
4023 
        .adr_a(adr_a[a_addr_width-3-1:0]),
4024 
        .we_a(we_a),
4025 
        .clk_a(clk_a),
4026 
        .d_b(d_b[7:0]),
4027 
        .q_b(q_b[7:0]),
4028 
        .adr_b(adr_b[b_addr_width-3-1:0]),
4029 
        .we_b(we_b),
4030 
        .clk_b(clk_b) );
4031 
`undef MODULE
4032 
/*
4033 
   reg [7:0] ram0 [mem_size/8-1:0];
4034 
   wire [7:0] wea, web;
4035 
   assign wea = we_a & be_a[0];
4036 
   assign web = we_b & be_b[0];
4037 
   always @ (posedge clk_a)
4038 
    if (wea)
4039 
        ram0[adr_a] <= d_a[7:0];
4040 
    always @ (posedge clk_a)
4041 
        q_a[7:0] <= ram0[adr_a];
4042 
   always @ (posedge clk_a)
4043 
    if (web)
4044 
        ram0[adr_b] <= d_b[7:0];
4045 
    always @ (posedge clk_b)
4046 
        q_b[7:0] <= ram0[adr_b];
4047 
*/
4048 
end
4049 
endgenerate
4050 
/*
4051 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_rama
4052 
      always @ (posedge clk_a)
4053 
      if (we_a & be_a[i])
4054 
        ram[adr_a][(i+1)*8-1:i*8] <= d_a[(i+1)*8-1:i*8];
4055 
   end
4056 
   endgenerate
4057 
 
4058 
   always @ (posedge clk_a)
4059 
      q_a <= ram[adr_a];
4060 
 
4061 
   genvar i;
4062 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ramb
4063 
      always @ (posedge clk_a)
4064 
      if (we_b & be_b[i])
4065 
        ram[adr_b][(i+1)*8-1:i*8] <= d_b[(i+1)*8-1:i*8];
4066 
   end
4067 
   endgenerate
4068 
 
4069 
   always @ (posedge clk_b)
4070 
      q_b <= ram[adr_b];
4071 
*/
4072 
/*
4073 
   always @ (posedge clk_a)
4074 
     begin
4075 
        q_a <= ram[adr_a];
4076 
        if (we_a)
4077 
             ram[adr_a] <= d_a;
4078 
     end
4079 
   always @ (posedge clk_b)
4080 
     begin
4081 
        q_b <= ram[adr_b];
4082 
        if (we_b)
4083 
          ram[adr_b] <= d_b;
4084 
     end
4085 
*/
4086 
endmodule
4087 
`endif
4088 
 
4089 6 unneback 
// Content addresable memory, CAM
4090 
 
4091 40 unneback 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
4092 6 unneback 
// FIFO
4093 40 unneback 
`define MODULE fifo_1r1w_fill_level_sync
4094 
module `BASE`MODULE (
4095 
`undef MODULE
4096 25 unneback 
    d, wr, fifo_full,
4097 
    q, rd, fifo_empty,
4098 
    fill_level,
4099 
    clk, rst
4100 
    );
4101 
 
4102 
parameter data_width = 18;
4103 
parameter addr_width = 4;
4104 6 unneback 
 
4105 25 unneback 
// write side
4106 
input  [data_width-1:0] d;
4107 
input                   wr;
4108 
output                  fifo_full;
4109 
// read side
4110 
output [data_width-1:0] q;
4111 
input                   rd;
4112 
output                  fifo_empty;
4113 
// common
4114 
output [addr_width:0]   fill_level;
4115 
input rst, clk;
4116 
 
4117 
wire [addr_width:1] wadr, radr;
4118 
 
4119 40 unneback 
`define MODULE cnt_bin_ce
4120 
`BASE`MODULE
4121 25 unneback 
    # ( .length(addr_width))
4122 
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
4123 40 unneback 
`BASE`MODULE
4124 25 unneback 
    # (.length(addr_width))
4125 
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
4126 40 unneback 
`undef MODULE
4127 25 unneback 
 
4128 40 unneback 
`define MODULE dpram_1r1w
4129 
`BASE`MODULE
4130 25 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4131 
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
4132 40 unneback 
`undef MODULE
4133 25 unneback 
 
4134 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
4135 
`BASE`MODULE
4136 27 unneback 
    # (.length(addr_width+1), .level1_value(1<<addr_width))
4137 25 unneback 
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
4138 40 unneback 
`undef MODULE
4139 25 unneback 
endmodule
4140 40 unneback 
`endif
4141 25 unneback 
 
4142 40 unneback 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
4143 27 unneback 
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
4144 
// RAM is supposed to be larger than the two FIFOs
4145 
// LFSR counters used adr pointers
4146 40 unneback 
`define MODULE fifo_2r2w_sync_simplex
4147 
module `BASE`MODULE (
4148 
`undef MODULE
4149 27 unneback 
    // a side
4150 
    a_d, a_wr, a_fifo_full,
4151 
    a_q, a_rd, a_fifo_empty,
4152 
    a_fill_level,
4153 
    // b side
4154 
    b_d, b_wr, b_fifo_full,
4155 
    b_q, b_rd, b_fifo_empty,
4156 
    b_fill_level,
4157 
    // common
4158 
    clk, rst
4159 
    );
4160 
parameter data_width = 8;
4161 
parameter addr_width = 5;
4162 
parameter fifo_full_level = (1<<addr_width)-1;
4163 
 
4164 
// a side
4165 
input  [data_width-1:0] a_d;
4166 
input                   a_wr;
4167 
output                  a_fifo_full;
4168 
output [data_width-1:0] a_q;
4169 
input                   a_rd;
4170 
output                  a_fifo_empty;
4171 
output [addr_width-1:0] a_fill_level;
4172 
 
4173 
// b side
4174 
input  [data_width-1:0] b_d;
4175 
input                   b_wr;
4176 
output                  b_fifo_full;
4177 
output [data_width-1:0] b_q;
4178 
input                   b_rd;
4179 
output                  b_fifo_empty;
4180 
output [addr_width-1:0] b_fill_level;
4181 
 
4182 
input                   clk;
4183 
input                   rst;
4184 
 
4185 
// adr_gen
4186 
wire [addr_width:1] a_wadr, a_radr;
4187 
wire [addr_width:1] b_wadr, b_radr;
4188 
// dpram
4189 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4190 
 
4191 40 unneback 
`define MODULE cnt_lfsr_ce
4192 
`BASE`MODULE
4193 27 unneback 
    # ( .length(addr_width))
4194 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
4195 
 
4196 40 unneback 
`BASE`MODULE
4197 27 unneback 
    # (.length(addr_width))
4198 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
4199 
 
4200 40 unneback 
`BASE`MODULE
4201 27 unneback 
    # ( .length(addr_width))
4202 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
4203 
 
4204 40 unneback 
`BASE`MODULE
4205 27 unneback 
    # (.length(addr_width))
4206 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
4207 40 unneback 
`undef MODULE
4208 27 unneback 
 
4209 
// mux read or write adr to DPRAM
4210 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
4211 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
4212 
 
4213 40 unneback 
`define MODULE dpram_2r2w
4214 
`BASE`MODULE
4215 27 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4216 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4217 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4218 40 unneback 
`undef MODULE
4219 
 
4220 
`define MODULE cnt_bin_ce_rew_zq_l1
4221 
`BASE`MODULE
4222 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4223 27 unneback 
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
4224 
 
4225 40 unneback 
`BASE`MODULE
4226 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4227 27 unneback 
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
4228 40 unneback 
`undef MODULE
4229 27 unneback 
 
4230 
endmodule
4231 40 unneback 
`endif
4232 27 unneback 
 
4233 40 unneback 
`ifdef FIFO_CMP_ASYNC
4234 
`define MODULE fifo_cmp_async
4235 
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
4236 
`undef MODULE
4237 6 unneback 
 
4238 11 unneback 
   parameter addr_width = 4;
4239 
   parameter N = addr_width-1;
4240 6 unneback 
 
4241 
   parameter Q1 = 2'b00;
4242 
   parameter Q2 = 2'b01;
4243 
   parameter Q3 = 2'b11;
4244 
   parameter Q4 = 2'b10;
4245 
 
4246 
   parameter going_empty = 1'b0;
4247 
   parameter going_full  = 1'b1;
4248 
 
4249 
   input [N:0]  wptr, rptr;
4250 14 unneback 
   output       fifo_empty;
4251 6 unneback 
   output       fifo_full;
4252 
   input        wclk, rclk, rst;
4253 
 
4254 
`ifndef GENERATE_DIRECTION_AS_LATCH
4255 
   wire direction;
4256 
`endif
4257 
`ifdef GENERATE_DIRECTION_AS_LATCH
4258 
   reg direction;
4259 
`endif
4260 
   reg  direction_set, direction_clr;
4261 
 
4262 
   wire async_empty, async_full;
4263 
   wire fifo_full2;
4264 14 unneback 
   wire fifo_empty2;
4265 6 unneback 
 
4266 
   // direction_set
4267 
   always @ (wptr[N:N-1] or rptr[N:N-1])
4268 
     case ({wptr[N:N-1],rptr[N:N-1]})
4269 
       {Q1,Q2} : direction_set <= 1'b1;
4270 
       {Q2,Q3} : direction_set <= 1'b1;
4271 
       {Q3,Q4} : direction_set <= 1'b1;
4272 
       {Q4,Q1} : direction_set <= 1'b1;
4273 
       default : direction_set <= 1'b0;
4274 
     endcase
4275 
 
4276 
   // direction_clear
4277 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
4278 
     if (rst)
4279 
       direction_clr <= 1'b1;
4280 
     else
4281 
       case ({wptr[N:N-1],rptr[N:N-1]})
4282 
         {Q2,Q1} : direction_clr <= 1'b1;
4283 
         {Q3,Q2} : direction_clr <= 1'b1;
4284 
         {Q4,Q3} : direction_clr <= 1'b1;
4285 
         {Q1,Q4} : direction_clr <= 1'b1;
4286 
         default : direction_clr <= 1'b0;
4287 
       endcase
4288 
 
4289 40 unneback 
`define MODULE dff_sr
4290 6 unneback 
`ifndef GENERATE_DIRECTION_AS_LATCH
4291 40 unneback 
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
4292 6 unneback 
`endif
4293 
 
4294 
`ifdef GENERATE_DIRECTION_AS_LATCH
4295 
   always @ (posedge direction_set or posedge direction_clr)
4296 
     if (direction_clr)
4297 
       direction <= going_empty;
4298 
     else
4299 
       direction <= going_full;
4300 
`endif
4301 
 
4302 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
4303 
   assign async_full  = (wptr == rptr) && (direction==going_full);
4304 
 
4305 40 unneback 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
4306 
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
4307 
`undef MODULE
4308 6 unneback 
 
4309 
/*
4310 
   always @ (posedge wclk or posedge rst or posedge async_full)
4311 
     if (rst)
4312 
       {fifo_full, fifo_full2} <= 2'b00;
4313 
     else if (async_full)
4314 
       {fifo_full, fifo_full2} <= 2'b11;
4315 
     else
4316 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
4317 
*/
4318 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
4319 6 unneback 
     if (async_empty)
4320 
       {fifo_empty, fifo_empty2} <= 2'b11;
4321 
     else
4322 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
4323 40 unneback 
`define MODULE dff
4324 
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
4325 
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
4326 
`undef MODULE
4327 27 unneback 
endmodule // async_compb
4328 40 unneback 
`endif
4329 6 unneback 
 
4330 40 unneback 
`ifdef FIFO_1R1W_ASYNC
4331 
`define MODULE fifo_1r1w_async
4332 
module `BASE`MODULE (
4333 
`undef MODULE
4334 6 unneback 
    d, wr, fifo_full, wr_clk, wr_rst,
4335 
    q, rd, fifo_empty, rd_clk, rd_rst
4336 
    );
4337 
 
4338 
parameter data_width = 18;
4339 
parameter addr_width = 4;
4340 
 
4341 
// write side
4342 
input  [data_width-1:0] d;
4343 
input                   wr;
4344 
output                  fifo_full;
4345 
input                   wr_clk;
4346 
input                   wr_rst;
4347 
// read side
4348 
output [data_width-1:0] q;
4349 
input                   rd;
4350 
output                  fifo_empty;
4351 
input                   rd_clk;
4352 
input                   rd_rst;
4353 
 
4354 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
4355 23 unneback 
 
4356 40 unneback 
`define MODULE cnt_gray_ce_bin
4357 
`BASE`MODULE
4358 6 unneback 
    # ( .length(addr_width))
4359 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
4360 
 
4361 40 unneback 
`BASE`MODULE
4362 6 unneback 
    # (.length(addr_width))
4363 23 unneback 
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
4364 40 unneback 
`undef MODULE
4365 6 unneback 
 
4366 40 unneback 
`define MODULE dpram_1r1w
4367 
`BASE`MODULE
4368 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4369 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
4370 40 unneback 
`undef MODULE
4371 6 unneback 
 
4372 40 unneback 
`define MODULE fifo_cmp_async
4373 
`BASE`MODULE
4374 6 unneback 
    # (.addr_width(addr_width))
4375 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
4376 40 unneback 
`undef MODULE
4377 6 unneback 
 
4378 
endmodule
4379 40 unneback 
`endif
4380 6 unneback 
 
4381 40 unneback 
`ifdef FIFO_2R2W_ASYNC
4382 
`define MODULE fifo_2r2w_async
4383 
module `BASE`MODULE (
4384 
`undef MODULE
4385 6 unneback 
    // a side
4386 
    a_d, a_wr, a_fifo_full,
4387 
    a_q, a_rd, a_fifo_empty,
4388 
    a_clk, a_rst,
4389 
    // b side
4390 
    b_d, b_wr, b_fifo_full,
4391 
    b_q, b_rd, b_fifo_empty,
4392 
    b_clk, b_rst
4393 
    );
4394 
 
4395 
parameter data_width = 18;
4396 
parameter addr_width = 4;
4397 
 
4398 
// a side
4399 
input  [data_width-1:0] a_d;
4400 
input                   a_wr;
4401 
output                  a_fifo_full;
4402 
output [data_width-1:0] a_q;
4403 
input                   a_rd;
4404 
output                  a_fifo_empty;
4405 
input                   a_clk;
4406 
input                   a_rst;
4407 
 
4408 
// b side
4409 
input  [data_width-1:0] b_d;
4410 
input                   b_wr;
4411 
output                  b_fifo_full;
4412 
output [data_width-1:0] b_q;
4413 
input                   b_rd;
4414 
output                  b_fifo_empty;
4415 
input                   b_clk;
4416 
input                   b_rst;
4417 
 
4418 40 unneback 
`define MODULE fifo_1r1w_async
4419 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4420 6 unneback 
vl_fifo_1r1w_async_a (
4421 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4422 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4423 
    );
4424 
 
4425 40 unneback 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4426 6 unneback 
vl_fifo_1r1w_async_b (
4427 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4428 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4429 
    );
4430 40 unneback 
`undef MODULE
4431 
 
4432 6 unneback 
endmodule
4433 40 unneback 
`endif
4434 6 unneback 
 
4435 40 unneback 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4436 
`define MODULE fifo_2r2w_async_simplex
4437 
module `BASE`MODULE (
4438 
`undef MODULE
4439 6 unneback 
    // a side
4440 
    a_d, a_wr, a_fifo_full,
4441 
    a_q, a_rd, a_fifo_empty,
4442 
    a_clk, a_rst,
4443 
    // b side
4444 
    b_d, b_wr, b_fifo_full,
4445 
    b_q, b_rd, b_fifo_empty,
4446 
    b_clk, b_rst
4447 
    );
4448 
 
4449 
parameter data_width = 18;
4450 
parameter addr_width = 4;
4451 
 
4452 
// a side
4453 
input  [data_width-1:0] a_d;
4454 
input                   a_wr;
4455 
output                  a_fifo_full;
4456 
output [data_width-1:0] a_q;
4457 
input                   a_rd;
4458 
output                  a_fifo_empty;
4459 
input                   a_clk;
4460 
input                   a_rst;
4461 
 
4462 
// b side
4463 
input  [data_width-1:0] b_d;
4464 
input                   b_wr;
4465 
output                  b_fifo_full;
4466 
output [data_width-1:0] b_q;
4467 
input                   b_rd;
4468 
output                  b_fifo_empty;
4469 
input                   b_clk;
4470 
input                   b_rst;
4471 
 
4472 
// adr_gen
4473 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4474 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4475 
// dpram
4476 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4477 
 
4478 40 unneback 
`define MODULE cnt_gray_ce_bin
4479 
`BASE`MODULE
4480 6 unneback 
    # ( .length(addr_width))
4481 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4482 
 
4483 40 unneback 
`BASE`MODULE
4484 6 unneback 
    # (.length(addr_width))
4485 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4486 
 
4487 40 unneback 
`BASE`MODULE
4488 6 unneback 
    # ( .length(addr_width))
4489 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4490 
 
4491 40 unneback 
`BASE`MODULE
4492 6 unneback 
    # (.length(addr_width))
4493 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4494 40 unneback 
`undef MODULE
4495 6 unneback 
 
4496 
// mux read or write adr to DPRAM
4497 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4498 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4499 
 
4500 40 unneback 
`define MODULE dpram_2r2w
4501 
`BASE`MODULE
4502 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4503 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4504 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4505 40 unneback 
`undef MODULE
4506 6 unneback 
 
4507 40 unneback 
`define MODULE fifo_cmp_async
4508 
`BASE`MODULE
4509 6 unneback 
    # (.addr_width(addr_width))
4510 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4511 
 
4512 40 unneback 
`BASE`MODULE
4513 6 unneback 
    # (.addr_width(addr_width))
4514 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4515 40 unneback 
`undef MODULE
4516 6 unneback 
 
4517 
endmodule
4518 40 unneback 
`endif
4519 48 unneback 
 
4520 
`ifdef REG_FILE
4521 
`define MODULE reg_file
4522 
module `BASE`MODULE (
4523 
`undef MODULE
4524 
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4525 
);
4526 
parameter data_width = 32;
4527 
parameter addr_width = 5;
4528 
input [addr_width-1:0] a1, a2, a3;
4529 
input [data_width-1:0] wd3;
4530 
input we3;
4531 
output [data_width-1:0] rd1, rd2;
4532 
input clk;
4533 
 
4534 
`ifdef ACTEL
4535 
reg [data_width-1:0] wd3_reg;
4536 
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4537 
reg we3_reg;
4538 
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
4539 
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
4540 
always @ (posedge clk or posedge rst)
4541 
if (rst)
4542 
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4543 
else
4544 
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4545 
 
4546 
    always @ (negedge clk)
4547 
    if (we3_reg)
4548 
        ram1[a3_reg] <= wd3;
4549 
    always @ (posedge clk)
4550 
        a1_reg <= a1;
4551 
    assign rd1 = ram1[a1_reg];
4552 
 
4553 
    always @ (negedge clk)
4554 
    if (we3_reg)
4555 
        ram2[a3_reg] <= wd3;
4556 
    always @ (posedge clk)
4557 
        a2_reg <= a2;
4558 
    assign rd2 = ram2[a2_reg];
4559 
 
4560 
`else
4561 
 
4562 
`define MODULE dpram_1r1w
4563 
`BASE`MODULE
4564 
    # ( .data_width(data_width), .addr_width(addr_width))
4565 
    ram1 (
4566 
        .d_a(wd3),
4567 
        .adr_a(a3),
4568 
        .we_a(we3),
4569 
        .clk_a(clk),
4570 
        .q_b(rd1),
4571 
        .adr_b(a1),
4572 
        .clk_b(clk) );
4573 
 
4574 
`BASE`MODULE
4575 
    # ( .data_width(data_width), .addr_width(addr_width))
4576 
    ram2 (
4577 
        .d_a(wd3),
4578 
        .adr_a(a3),
4579 
        .we_a(we3),
4580 
        .clk_a(clk),
4581 
        .q_b(rd2),
4582 
        .adr_b(a2),
4583 
        .clk_b(clk) );
4584 
`undef MODULE
4585 
 
4586 
`endif
4587 
 
4588 
endmodule
4589 
`endif
4590 12 unneback 
//////////////////////////////////////////////////////////////////////
4591 
////                                                              ////
4592 
////  Versatile library, wishbone stuff                           ////
4593 
////                                                              ////
4594 
////  Description                                                 ////
4595 
////  Wishbone compliant modules                                  ////
4596 
////                                                              ////
4597 
////                                                              ////
4598 
////  To Do:                                                      ////
4599 
////   -                                                          ////
4600 
////                                                              ////
4601 
////  Author(s):                                                  ////
4602 
////      - Michael Unneback, unneback@opencores.org              ////
4603 
////        ORSoC AB                                              ////
4604 
////                                                              ////
4605 
//////////////////////////////////////////////////////////////////////
4606 
////                                                              ////
4607 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4608 
////                                                              ////
4609 
//// This source file may be used and distributed without         ////
4610 
//// restriction provided that this copyright statement is not    ////
4611 
//// removed from the file and that any derivative work contains  ////
4612 
//// the original copyright notice and the associated disclaimer. ////
4613 
////                                                              ////
4614 
//// This source file is free software; you can redistribute it   ////
4615 
//// and/or modify it under the terms of the GNU Lesser General   ////
4616 
//// Public License as published by the Free Software Foundation; ////
4617 
//// either version 2.1 of the License, or (at your option) any   ////
4618 
//// later version.                                               ////
4619 
////                                                              ////
4620 
//// This source is distributed in the hope that it will be       ////
4621 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4622 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4623 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4624 
//// details.                                                     ////
4625 
////                                                              ////
4626 
//// You should have received a copy of the GNU Lesser General    ////
4627 
//// Public License along with this source; if not, download it   ////
4628 
//// from http://www.opencores.org/lgpl.shtml                     ////
4629 
////                                                              ////
4630 
//////////////////////////////////////////////////////////////////////
4631 
 
4632 75 unneback 
`ifdef WB_ADR_INC
4633 
// async wb3 - wb3 bridge
4634 
`timescale 1ns/1ns
4635 
`define MODULE wb_adr_inc
4636 
module `BASE`MODULE (
4637 
`undef MODULE
4638 
 
4639 
    always @ (posedge clk or posedge rst)
4640 
        if (rst)
4641 
           col_reg <= {col_reg_width{1'b0}};
4642 
        else
4643 
            case (state)
4644 
            `FSM_IDLE:
4645 
               col_reg <= col[col_reg_width-1:0];
4646 
            `FSM_RW:
4647 
               if (~stall)
4648 
                  case (bte_i)
4649 
`ifdef SDR_BEAT4
4650 
                        beat4:  col_reg[2:0] <= col_reg[2:0] + 3'd1;
4651 
`endif
4652 
`ifdef SDR_BEAT8
4653 
                        beat8:  col_reg[3:0] <= col_reg[3:0] + 4'd1;
4654 
`endif
4655 
`ifdef SDR_BEAT16
4656 
                        beat16: col_reg[4:0] <= col_reg[4:0] + 5'd1;
4657 
`endif
4658 
                  endcase
4659 
            endcase
4660 
`endif
4661 
 
4662 40 unneback 
`ifdef WB3WB3_BRIDGE
4663 12 unneback 
// async wb3 - wb3 bridge
4664 
`timescale 1ns/1ns
4665 40 unneback 
`define MODULE wb3wb3_bridge
4666 
module `BASE`MODULE (
4667 
`undef MODULE
4668 12 unneback 
        // wishbone slave side
4669 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4670 
        // wishbone master side
4671 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4672 
 
4673 
input [31:0] wbs_dat_i;
4674 
input [31:2] wbs_adr_i;
4675 
input [3:0]  wbs_sel_i;
4676 
input [1:0]  wbs_bte_i;
4677 
input [2:0]  wbs_cti_i;
4678 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4679 
output [31:0] wbs_dat_o;
4680 14 unneback 
output wbs_ack_o;
4681 12 unneback 
input wbs_clk, wbs_rst;
4682 
 
4683 
output [31:0] wbm_dat_o;
4684 
output reg [31:2] wbm_adr_o;
4685 
output [3:0]  wbm_sel_o;
4686 
output reg [1:0]  wbm_bte_o;
4687 
output reg [2:0]  wbm_cti_o;
4688 14 unneback 
output reg wbm_we_o;
4689 
output wbm_cyc_o;
4690 12 unneback 
output wbm_stb_o;
4691 
input [31:0]  wbm_dat_i;
4692 
input wbm_ack_i;
4693 
input wbm_clk, wbm_rst;
4694 
 
4695 
parameter addr_width = 4;
4696 
 
4697 
// bte
4698 
parameter linear       = 2'b00;
4699 
parameter wrap4        = 2'b01;
4700 
parameter wrap8        = 2'b10;
4701 
parameter wrap16       = 2'b11;
4702 
// cti
4703 
parameter classic      = 3'b000;
4704 
parameter incburst     = 3'b010;
4705 
parameter endofburst   = 3'b111;
4706 
 
4707 
parameter wbs_adr  = 1'b0;
4708 
parameter wbs_data = 1'b1;
4709 
 
4710 33 unneback 
parameter wbm_adr0      = 2'b00;
4711 
parameter wbm_adr1      = 2'b01;
4712 
parameter wbm_data      = 2'b10;
4713 
parameter wbm_data_wait = 2'b11;
4714 12 unneback 
 
4715 
reg [1:0] wbs_bte_reg;
4716 
reg wbs;
4717 
wire wbs_eoc_alert, wbm_eoc_alert;
4718 
reg wbs_eoc, wbm_eoc;
4719 
reg [1:0] wbm;
4720 
 
4721 14 unneback 
wire [1:16] wbs_count, wbm_count;
4722 12 unneback 
 
4723 
wire [35:0] a_d, a_q, b_d, b_q;
4724 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4725 
reg a_rd_reg;
4726 
wire b_rd_adr, b_rd_data;
4727 14 unneback 
wire b_rd_data_reg;
4728 
wire [35:0] temp;
4729 12 unneback 
 
4730 
`define WE 5
4731 
`define BTE 4:3
4732 
`define CTI 2:0
4733 
 
4734 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4735 
always @ (posedge wbs_clk or posedge wbs_rst)
4736 
if (wbs_rst)
4737 
        wbs_eoc <= 1'b0;
4738 
else
4739 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4740 
                wbs_eoc <= wbs_bte_i==linear;
4741 
        else if (wbs_eoc_alert & (a_rd | a_wr))
4742 
                wbs_eoc <= 1'b1;
4743 
 
4744 40 unneback 
`define MODULE cnt_shreg_ce_clear
4745 
`BASE`MODULE # ( .length(16))
4746 
`undef MODULE
4747 12 unneback 
    cnt0 (
4748 
        .cke(wbs_ack_o),
4749 
        .clear(wbs_eoc),
4750 
        .q(wbs_count),
4751 
        .rst(wbs_rst),
4752 
        .clk(wbs_clk));
4753 
 
4754 
always @ (posedge wbs_clk or posedge wbs_rst)
4755 
if (wbs_rst)
4756 
        wbs <= wbs_adr;
4757 
else
4758 75 unneback 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
4759 12 unneback 
                wbs <= wbs_data;
4760 
        else if (wbs_eoc & wbs_ack_o)
4761 
                wbs <= wbs_adr;
4762 
 
4763 
// wbs FIFO
4764 75 unneback 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
4765 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
4766 12 unneback 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4767 
              1'b0;
4768 
assign a_rd = !a_fifo_empty;
4769 
always @ (posedge wbs_clk or posedge wbs_rst)
4770 
if (wbs_rst)
4771 
        a_rd_reg <= 1'b0;
4772 
else
4773 
        a_rd_reg <= a_rd;
4774 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4775 
 
4776 
assign wbs_dat_o = a_q[35:4];
4777 
 
4778 
always @ (posedge wbs_clk or posedge wbs_rst)
4779 
if (wbs_rst)
4780 13 unneback 
        wbs_bte_reg <= 2'b00;
4781 12 unneback 
else
4782 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
4783 12 unneback 
 
4784 
// wbm FIFO
4785 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4786 
always @ (posedge wbm_clk or posedge wbm_rst)
4787 
if (wbm_rst)
4788 
        wbm_eoc <= 1'b0;
4789 
else
4790 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4791 
                wbm_eoc <= b_q[`BTE] == linear;
4792 
        else if (wbm_eoc_alert & wbm_ack_i)
4793 
                wbm_eoc <= 1'b1;
4794 
 
4795 
always @ (posedge wbm_clk or posedge wbm_rst)
4796 
if (wbm_rst)
4797 
        wbm <= wbm_adr0;
4798 
else
4799 33 unneback 
/*
4800 12 unneback 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
4801 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
4802 
        (wbm==wbm_adr1 & !wbm_we_o) |
4803 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
4804 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
4805 33 unneback 
*/
4806 
    case (wbm)
4807 
    wbm_adr0:
4808 
        if (!b_fifo_empty)
4809 
            wbm <= wbm_adr1;
4810 
    wbm_adr1:
4811 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
4812 
            wbm <= wbm_data;
4813 
    wbm_data:
4814 
        if (wbm_ack_i & wbm_eoc)
4815 
            wbm <= wbm_adr0;
4816 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
4817 
            wbm <= wbm_data_wait;
4818 
    wbm_data_wait:
4819 
        if (!b_fifo_empty)
4820 
            wbm <= wbm_data;
4821 
    endcase
4822 12 unneback 
 
4823 
assign b_d = {wbm_dat_i,4'b1111};
4824 
assign b_wr = !wbm_we_o & wbm_ack_i;
4825 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
4826 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
4827 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
4828 33 unneback 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
4829 12 unneback 
                   1'b0;
4830 
assign b_rd = b_rd_adr | b_rd_data;
4831 
 
4832 40 unneback 
`define MODULE dff
4833 
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
4834 
`undef MODULE
4835 
`define MODULE dff_ce
4836 
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
4837 
`undef MODULE
4838 12 unneback 
 
4839 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
4840 
 
4841 40 unneback 
`define MODULE cnt_shreg_ce_clear
4842 42 unneback 
`BASE`MODULE # ( .length(16))
4843 40 unneback 
`undef MODULE
4844 12 unneback 
    cnt1 (
4845 
        .cke(wbm_ack_i),
4846 
        .clear(wbm_eoc),
4847 
        .q(wbm_count),
4848 
        .rst(wbm_rst),
4849 
        .clk(wbm_clk));
4850 
 
4851 33 unneback 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
4852 
assign wbm_stb_o = (wbm==wbm_data);
4853 12 unneback 
 
4854 
always @ (posedge wbm_clk or posedge wbm_rst)
4855 
if (wbm_rst)
4856 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
4857 
else begin
4858 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4859 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
4860 
        else if (wbm_eoc_alert & wbm_ack_i)
4861 
                wbm_cti_o <= endofburst;
4862 
end
4863 
 
4864 
//async_fifo_dw_simplex_top
4865 40 unneback 
`define MODULE fifo_2r2w_async_simplex
4866 
`BASE`MODULE
4867 
`undef MODULE
4868 12 unneback 
# ( .data_width(36), .addr_width(addr_width))
4869 
fifo (
4870 
    // a side
4871 
    .a_d(a_d),
4872 
    .a_wr(a_wr),
4873 
    .a_fifo_full(a_fifo_full),
4874 
    .a_q(a_q),
4875 
    .a_rd(a_rd),
4876 
    .a_fifo_empty(a_fifo_empty),
4877 
    .a_clk(wbs_clk),
4878 
    .a_rst(wbs_rst),
4879 
    // b side
4880 
    .b_d(b_d),
4881 
    .b_wr(b_wr),
4882 
    .b_fifo_full(b_fifo_full),
4883 
    .b_q(b_q),
4884 
    .b_rd(b_rd),
4885 
    .b_fifo_empty(b_fifo_empty),
4886 
    .b_clk(wbm_clk),
4887 
    .b_rst(wbm_rst)
4888 
    );
4889 
 
4890 
endmodule
4891 40 unneback 
`undef WE
4892 
`undef BTE
4893 
`undef CTI
4894 
`endif
4895 17 unneback 
 
4896 75 unneback 
`ifdef WB3AVALON_BRIDGE
4897 
`define MODULE wb3avalon_bridge
4898 
module `BASE`MODULE (
4899 
`undef MODULE
4900 
        // wishbone slave side
4901 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4902 
        // wishbone master side
4903 
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
4904 
 
4905 
input [31:0] wbs_dat_i;
4906 
input [31:2] wbs_adr_i;
4907 
input [3:0]  wbs_sel_i;
4908 
input [1:0]  wbs_bte_i;
4909 
input [2:0]  wbs_cti_i;
4910 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4911 
output [31:0] wbs_dat_o;
4912 
output wbs_ack_o;
4913 
input wbs_clk, wbs_rst;
4914 
 
4915 
input [31:0] readdata;
4916 
output [31:0] writedata;
4917 
output [31:2] address;
4918 
output [3:0]  be;
4919 
output write;
4920 
output read;
4921 
output beginbursttransfer;
4922 
output [3:0] burstcount;
4923 
input readdatavalid;
4924 
input waitrequest;
4925 
input clk;
4926 
input rst;
4927 
 
4928 
wire [1:0] wbm_bte_o;
4929 
wire [2:0] wbm_cti_o;
4930 
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
4931 
reg last_cyc;
4932 
 
4933 
always @ (posedge clk or posedge rst)
4934 
if (rst)
4935 
    last_cyc <= 1'b0;
4936 
else
4937 
    last_cyc <= wbm_cyc_o;
4938 
 
4939 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
4940 
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
4941 
                    (wbm_bte_o==2'b10) ? 4'd8 :
4942 
                    4'd16;
4943 
assign write = wbm_cyc_o & wbm_stb_o &  wbm_we_o;
4944 
assign read  = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
4945 
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
4946 
 
4947 
`define MODULE wb3wb3_bridge
4948 
`BASE`MODULE (
4949 
`undef MODULE
4950 
    // wishbone slave side
4951 
    .wbs_dat_i(wbs_dat_i),
4952 
    .wbs_adr_i(wbs_adr_i),
4953 
    .wbs_sel_i(wbs_sel_i),
4954 
    .wbs_bte_i(wbs_bte_i),
4955 
    .wbs_cti_i(wbs_cti_i),
4956 
    .wbs_we_i(wbs_we_i),
4957 
    .wbs_cyc_i(wbs_cyc_i),
4958 
    .wbs_stb_i(wbs_stb_i),
4959 
    .wbs_dat_o(wbs_dat_o),
4960 
    .wbs_ack_o(wbs_ack_o),
4961 
    .wbs_clk(wbs_clk),
4962 
    .wbs_rst(wbs_rst),
4963 
    // wishbone master side
4964 
    .wbm_dat_o(writedata),
4965 
    .wbm_adr_o(adress),
4966 
    .wbm_sel_o(be),
4967 
    .wbm_bte_o(wbm_bte_o),
4968 
    .wbm_cti_o(wbm_cti_o),
4969 
    .wbm_we_o(wbm_we_o),
4970 
    .wbm_cyc_o(wbm_cyc_o),
4971 
    .wbm_stb_o(wbm_stb_o),
4972 
    .wbm_dat_i(readdata),
4973 
    .wbm_ack_i(wbm_ack_i),
4974 
    .wbm_clk(clk),
4975 
    .wbm_rst(rst));
4976 
 
4977 
 
4978 
endmodule
4979 
`endif
4980 
 
4981 40 unneback 
`ifdef WB3_ARBITER_TYPE1
4982 
`define MODULE wb3_arbiter_type1
4983 42 unneback 
module `BASE`MODULE (
4984 40 unneback 
`undef MODULE
4985 39 unneback 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
4986 
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
4987 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
4988 
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
4989 
    wb_clk, wb_rst
4990 
);
4991 
 
4992 
parameter nr_of_ports = 3;
4993 
parameter adr_size = 26;
4994 
parameter adr_lo   = 2;
4995 
parameter dat_size = 32;
4996 
parameter sel_size = dat_size/8;
4997 
 
4998 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
4999 
localparam dw = dat_size * nr_of_ports;
5000 
localparam sw = sel_size * nr_of_ports;
5001 
localparam cw = 3 * nr_of_ports;
5002 
localparam bw = 2 * nr_of_ports;
5003 
 
5004 
input  [dw-1:0] wbm_dat_o;
5005 
input  [aw-1:0] wbm_adr_o;
5006 
input  [sw-1:0] wbm_sel_o;
5007 
input  [cw-1:0] wbm_cti_o;
5008 
input  [bw-1:0] wbm_bte_o;
5009 
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
5010 
output [dw-1:0] wbm_dat_i;
5011 
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
5012 
 
5013 
output [dat_size-1:0] wbs_dat_i;
5014 
output [adr_size-1:adr_lo] wbs_adr_i;
5015 
output [sel_size-1:0] wbs_sel_i;
5016 
output [2:0] wbs_cti_i;
5017 
output [1:0] wbs_bte_i;
5018 
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
5019 
input  [dat_size-1:0] wbs_dat_o;
5020 
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
5021 
 
5022 
input wb_clk, wb_rst;
5023 
 
5024 44 unneback 
reg  [nr_of_ports-1:0] select;
5025 39 unneback 
wire [nr_of_ports-1:0] state;
5026 
wire [nr_of_ports-1:0] eoc; // end-of-cycle
5027 
wire [nr_of_ports-1:0] sel;
5028 
wire idle;
5029 
 
5030 
genvar i;
5031 
 
5032 
assign idle = !(|state);
5033 
 
5034 
generate
5035 
if (nr_of_ports == 2) begin
5036 
 
5037 
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
5038 
 
5039 
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5040 
 
5041 44 unneback 
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5042 
 
5043 
    always @ (idle or wbm_cyc_o)
5044 
    if (idle)
5045 
        casex (wbm_cyc_o)
5046 
        2'b1x : select = 2'b10;
5047 
        2'b01 : select = 2'b01;
5048 
        default : select = {nr_of_ports{1'b0}};
5049 
        endcase
5050 
    else
5051 
        select = {nr_of_ports{1'b0}};
5052 
 
5053 39 unneback 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5054 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5055 
 
5056 
end
5057 
endgenerate
5058 
 
5059 
generate
5060 
if (nr_of_ports == 3) begin
5061 
 
5062 
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5063 
 
5064 
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5065 
 
5066 44 unneback 
    always @ (idle or wbm_cyc_o)
5067 
    if (idle)
5068 
        casex (wbm_cyc_o)
5069 
        3'b1xx : select = 3'b100;
5070 
        3'b01x : select = 3'b010;
5071 
        3'b001 : select = 3'b001;
5072 
        default : select = {nr_of_ports{1'b0}};
5073 
        endcase
5074 
    else
5075 
        select = {nr_of_ports{1'b0}};
5076 
 
5077 
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5078 39 unneback 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5079 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5080 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5081 
 
5082 
end
5083 
endgenerate
5084 
 
5085 
generate
5086 44 unneback 
if (nr_of_ports == 4) begin
5087 
 
5088 
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5089 
 
5090 
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5091 
 
5092 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5093 
 
5094 
    always @ (idle or wbm_cyc_o)
5095 
    if (idle)
5096 
        casex (wbm_cyc_o)
5097 
        4'b1xxx : select = 4'b1000;
5098 
        4'b01xx : select = 4'b0100;
5099 
        4'b001x : select = 4'b0010;
5100 
        4'b0001 : select = 4'b0001;
5101 
        default : select = {nr_of_ports{1'b0}};
5102 
        endcase
5103 
    else
5104 
        select = {nr_of_ports{1'b0}};
5105 
 
5106 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5107 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5108 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5109 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5110 
 
5111 
end
5112 
endgenerate
5113 
 
5114 
generate
5115 
if (nr_of_ports == 5) begin
5116 
 
5117 
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5118 
 
5119 
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5120 
 
5121 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5122 
 
5123 
    always @ (idle or wbm_cyc_o)
5124 
    if (idle)
5125 
        casex (wbm_cyc_o)
5126 
        5'b1xxxx : select = 5'b10000;
5127 
        5'b01xxx : select = 5'b01000;
5128 
        5'b001xx : select = 5'b00100;
5129 
        5'b0001x : select = 5'b00010;
5130 
        5'b00001 : select = 5'b00001;
5131 
        default : select = {nr_of_ports{1'b0}};
5132 
        endcase
5133 
    else
5134 
        select = {nr_of_ports{1'b0}};
5135 
 
5136 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5137 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5138 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5139 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5140 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5141 
 
5142 
end
5143 
endgenerate
5144 
 
5145 
generate
5146 67 unneback 
if (nr_of_ports == 6) begin
5147 
 
5148 
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5149 
 
5150 
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5151 
 
5152 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5153 
 
5154 
    always @ (idle or wbm_cyc_o)
5155 
    if (idle)
5156 
        casex (wbm_cyc_o)
5157 
        6'b1xxxxx : select = 6'b100000;
5158 
        6'b01xxxx : select = 6'b010000;
5159 
        6'b001xxx : select = 6'b001000;
5160 
        6'b0001xx : select = 6'b000100;
5161 
        6'b00001x : select = 6'b000010;
5162 
        6'b000001 : select = 6'b000001;
5163 
        default : select = {nr_of_ports{1'b0}};
5164 
        endcase
5165 
    else
5166 
        select = {nr_of_ports{1'b0}};
5167 
 
5168 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5169 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5170 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5171 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5172 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5173 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5174 
 
5175 
end
5176 
endgenerate
5177 
 
5178 
generate
5179 
if (nr_of_ports == 7) begin
5180 
 
5181 
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5182 
 
5183 
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5184 
 
5185 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5186 
 
5187 
    always @ (idle or wbm_cyc_o)
5188 
    if (idle)
5189 
        casex (wbm_cyc_o)
5190 
        7'b1xxxxxx : select = 7'b1000000;
5191 
        7'b01xxxxx : select = 7'b0100000;
5192 
        7'b001xxxx : select = 7'b0010000;
5193 
        7'b0001xxx : select = 7'b0001000;
5194 
        7'b00001xx : select = 7'b0000100;
5195 
        7'b000001x : select = 7'b0000010;
5196 
        7'b0000001 : select = 7'b0000001;
5197 
        default : select = {nr_of_ports{1'b0}};
5198 
        endcase
5199 
    else
5200 
        select = {nr_of_ports{1'b0}};
5201 
 
5202 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5203 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5204 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5205 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5206 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5207 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5208 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5209 
 
5210 
end
5211 
endgenerate
5212 
 
5213 
generate
5214 
if (nr_of_ports == 8) begin
5215 
 
5216 
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5217 
 
5218 
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5219 
 
5220 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5221 
 
5222 
    always @ (idle or wbm_cyc_o)
5223 
    if (idle)
5224 
        casex (wbm_cyc_o)
5225 
        8'b1xxxxxxx : select = 8'b10000000;
5226 
        8'b01xxxxxx : select = 8'b01000000;
5227 
        8'b001xxxxx : select = 8'b00100000;
5228 
        8'b0001xxxx : select = 8'b00010000;
5229 
        8'b00001xxx : select = 8'b00001000;
5230 
        8'b000001xx : select = 8'b00000100;
5231 
        8'b0000001x : select = 8'b00000010;
5232 
        8'b00000001 : select = 8'b00000001;
5233 
        default : select = {nr_of_ports{1'b0}};
5234 
        endcase
5235 
    else
5236 
        select = {nr_of_ports{1'b0}};
5237 
 
5238 
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
5239 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5240 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5241 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5242 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5243 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5244 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5245 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5246 
 
5247 
end
5248 
endgenerate
5249 
 
5250 
generate
5251 63 unneback 
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
5252 42 unneback 
`define MODULE spr
5253 
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
5254 
`undef MODULE
5255 39 unneback 
end
5256 
endgenerate
5257 
 
5258 
    assign sel = select | state;
5259 
 
5260 40 unneback 
`define MODULE mux_andor
5261 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
5262 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
5263 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
5264 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
5265 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
5266 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
5267 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
5268 
`undef MODULE
5269 39 unneback 
    assign wbs_cyc_i = |sel;
5270 
 
5271 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
5272 
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
5273 
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
5274 
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
5275 
 
5276 
endmodule
5277 40 unneback 
`endif
5278 39 unneback 
 
5279 60 unneback 
`ifdef WB_B3_RAM_BE
5280 49 unneback 
// WB RAM with byte enable
5281 59 unneback 
`define MODULE wb_b3_ram_be
5282 
module `BASE`MODULE (
5283 
`undef MODULE
5284 69 unneback 
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5285 
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
5286 59 unneback 
 
5287 68 unneback 
parameter adr_size = 16;
5288 60 unneback 
parameter adr_lo   = 2;
5289 68 unneback 
parameter mem_size = 1<<16;
5290 60 unneback 
parameter dat_size = 32;
5291 
parameter memory_init = 1;
5292 
parameter memory_file = "vl_ram.vmem";
5293 59 unneback 
 
5294 69 unneback 
localparam aw = (adr_size - adr_lo);
5295 
localparam dw = dat_size;
5296 
localparam sw = dat_size/8;
5297 
localparam cw = 3;
5298 
localparam bw = 2;
5299 60 unneback 
 
5300 70 unneback 
input [dw-1:0] wbs_dat_i;
5301 
input [aw-1:0] wbs_adr_i;
5302 
input [cw-1:0] wbs_cti_i;
5303 
input [bw-1:0] wbs_bte_i;
5304 
input [sw-1:0] wbs_sel_i;
5305 
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5306 
output [dw-1:0] wbs_dat_o;
5307 
output wbs_ack_o;
5308 71 unneback 
input wb_clk, wb_rst;
5309 59 unneback 
 
5310 60 unneback 
wire [sw-1:0] cke;
5311 59 unneback 
 
5312 60 unneback 
reg wbs_ack_o;
5313 
 
5314 
`define MODULE ram_be
5315 
`BASE`MODULE # (
5316 
    .data_width(dat_size),
5317 72 unneback 
    .addr_width(adr_size-2),
5318 69 unneback 
    .mem_size(mem_size),
5319 68 unneback 
    .memory_init(memory_init),
5320 
    .memory_file(memory_file))
5321 60 unneback 
ram0(
5322 
`undef MODULE
5323 
    .d(wbs_dat_i),
5324 
    .adr(wbs_adr_i[adr_size-1:2]),
5325 
    .be(wbs_sel_i),
5326 
    .we(wbs_we_i),
5327 
    .q(wbs_dat_o),
5328 
    .clk(wb_clk)
5329 
);
5330 
 
5331 59 unneback 
always @ (posedge wb_clk or posedge wb_rst)
5332 
if (wb_rst)
5333 60 unneback 
    wbs_ack_o <= 1'b0;
5334 59 unneback 
else
5335 60 unneback 
    if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
5336 
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
5337 59 unneback 
    else
5338 60 unneback 
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
5339 
 
5340 59 unneback 
endmodule
5341 
`endif
5342 
 
5343 
`ifdef WB_B4_RAM_BE
5344 
// WB RAM with byte enable
5345 49 unneback 
`define MODULE wb_b4_ram_be
5346 
module `BASE`MODULE (
5347 
`undef MODULE
5348 
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
5349 52 unneback 
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
5350 49 unneback 
 
5351 
    parameter dat_width = 32;
5352 
    parameter adr_width = 8;
5353 
 
5354 
input [dat_width-1:0] wb_dat_i;
5355 
input [adr_width-1:0] wb_adr_i;
5356 
input [dat_width/8-1:0] wb_sel_i;
5357 
input wb_we_i, wb_stb_i, wb_cyc_i;
5358 
output [dat_width-1:0] wb_dat_o;
5359 51 unneback 
reg [dat_width-1:0] wb_dat_o;
5360 52 unneback 
output wb_stall_o;
5361 49 unneback 
output wb_ack_o;
5362 
reg wb_ack_o;
5363 
input wb_clk, wb_rst;
5364 
 
5365 56 unneback 
wire [dat_width/8-1:0] cke;
5366 
 
5367 49 unneback 
generate
5368 
if (dat_width==32) begin
5369 51 unneback 
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
5370 
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
5371 
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
5372 
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
5373 56 unneback 
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
5374 49 unneback 
    always @ (posedge wb_clk)
5375 
    begin
5376 56 unneback 
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
5377 
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
5378 
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
5379 
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
5380 49 unneback 
    end
5381 59 unneback 
    always @ (posedge wb_clk or posedge wb_rst)
5382 
    begin
5383 
        if (wb_rst)
5384 
            wb_dat_o <= 32'h0;
5385 
        else
5386 
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
5387 
    end
5388 49 unneback 
end
5389 
endgenerate
5390 
 
5391 52 unneback 
always @ (posedge wb_clk or posedge wb_rst)
5392 55 unneback 
if (wb_rst)
5393 52 unneback 
    wb_ack_o <= 1'b0;
5394 
else
5395 54 unneback 
    wb_ack_o <= wb_stb_i & wb_cyc_i;
5396 52 unneback 
 
5397 
assign wb_stall_o = 1'b0;
5398 
 
5399 49 unneback 
endmodule
5400 
`endif
5401 
 
5402 48 unneback 
`ifdef WB_B4_ROM
5403 
// WB ROM
5404 
`define MODULE wb_b4_rom
5405 
module `BASE`MODULE (
5406 
`undef MODULE
5407 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5408 
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
5409 
 
5410 
    parameter dat_width = 32;
5411 
    parameter dat_default = 32'h15000000;
5412 
    parameter adr_width = 32;
5413 
 
5414 
/*
5415 
`ifndef ROM
5416 
`define ROM "rom.v"
5417 
`endif
5418 
*/
5419 
    input [adr_width-1:2]   wb_adr_i;
5420 
    input                   wb_stb_i;
5421 
    input                   wb_cyc_i;
5422 
    output [dat_width-1:0]  wb_dat_o;
5423 
    reg [dat_width-1:0]     wb_dat_o;
5424 
    output                  wb_ack_o;
5425 
    reg                     wb_ack_o;
5426 
    output                  stall_o;
5427 
    input                   wb_clk;
5428 
    input                   wb_rst;
5429 
 
5430 
always @ (posedge wb_clk or posedge wb_rst)
5431 
    if (wb_rst)
5432 
        wb_dat_o <= {dat_width{1'b0}};
5433 
    else
5434 
         case (wb_adr_i[adr_width-1:2])
5435 
`ifdef ROM
5436 
`include `ROM
5437 
`endif
5438 
           default:
5439 
             wb_dat_o <= dat_default;
5440 
 
5441 
         endcase // case (wb_adr_i)
5442 
 
5443 
 
5444 
always @ (posedge wb_clk or posedge wb_rst)
5445 
    if (wb_rst)
5446 
        wb_ack_o <= 1'b0;
5447 
    else
5448 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
5449 
 
5450 
assign stall_o = 1'b0;
5451 
 
5452 
endmodule
5453 
`endif
5454 
 
5455 
 
5456 40 unneback 
`ifdef WB_BOOT_ROM
5457 17 unneback 
// WB ROM
5458 40 unneback 
`define MODULE wb_boot_rom
5459 
module `BASE`MODULE (
5460 
`undef MODULE
5461 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5462 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
5463 17 unneback 
 
5464 18 unneback 
    parameter adr_hi = 31;
5465 
    parameter adr_lo = 28;
5466 
    parameter adr_sel = 4'hf;
5467 
    parameter addr_width = 5;
5468 33 unneback 
/*
5469 17 unneback 
`ifndef BOOT_ROM
5470 
`define BOOT_ROM "boot_rom.v"
5471 
`endif
5472 33 unneback 
*/
5473 18 unneback 
    input [adr_hi:2]    wb_adr_i;
5474 
    input               wb_stb_i;
5475 
    input               wb_cyc_i;
5476 
    output [31:0]        wb_dat_o;
5477 
    output              wb_ack_o;
5478 
    output              hit_o;
5479 
    input               wb_clk;
5480 
    input               wb_rst;
5481 
 
5482 
    wire hit;
5483 
    reg [31:0] wb_dat;
5484 
    reg wb_ack;
5485 
 
5486 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
5487 17 unneback 
 
5488 
always @ (posedge wb_clk or posedge wb_rst)
5489 
    if (wb_rst)
5490 18 unneback 
        wb_dat <= 32'h15000000;
5491 17 unneback 
    else
5492 18 unneback 
         case (wb_adr_i[addr_width-1:2])
5493 33 unneback 
`ifdef BOOT_ROM
5494 17 unneback 
`include `BOOT_ROM
5495 33 unneback 
`endif
5496 17 unneback 
           /*
5497 
            // Zero r0 and jump to 0x00000100
5498 18 unneback 
 
5499 
            1 : wb_dat <= 32'hA8200000;
5500 
            2 : wb_dat <= 32'hA8C00100;
5501 
            3 : wb_dat <= 32'h44003000;
5502 
            4 : wb_dat <= 32'h15000000;
5503 17 unneback 
            */
5504 
           default:
5505 18 unneback 
             wb_dat <= 32'h00000000;
5506 17 unneback 
 
5507 
         endcase // case (wb_adr_i)
5508 
 
5509 
 
5510 
always @ (posedge wb_clk or posedge wb_rst)
5511 
    if (wb_rst)
5512 18 unneback 
        wb_ack <= 1'b0;
5513 17 unneback 
    else
5514 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
5515 17 unneback 
 
5516 18 unneback 
assign hit_o = hit;
5517 
assign wb_dat_o = wb_dat & {32{wb_ack}};
5518 
assign wb_ack_o = wb_ack;
5519 
 
5520 17 unneback 
endmodule
5521 40 unneback 
`endif
5522 32 unneback 
 
5523 40 unneback 
`ifdef WB_DPRAM
5524 
`define MODULE wb_dpram
5525 
module `BASE`MODULE (
5526 
`undef MODULE
5527 32 unneback 
        // wishbone slave side a
5528 
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
5529 
        wbsa_clk, wbsa_rst,
5530 
        // wishbone slave side a
5531 
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
5532 
        wbsb_clk, wbsb_rst);
5533 
 
5534 
parameter data_width = 32;
5535 
parameter addr_width = 8;
5536 
 
5537 
parameter dat_o_mask_a = 1;
5538 
parameter dat_o_mask_b = 1;
5539 
 
5540 
input [31:0] wbsa_dat_i;
5541 
input [addr_width-1:2] wbsa_adr_i;
5542 
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
5543 
output [31:0] wbsa_dat_o;
5544 
output wbsa_ack_o;
5545 
input wbsa_clk, wbsa_rst;
5546 
 
5547 
input [31:0] wbsb_dat_i;
5548 
input [addr_width-1:2] wbsb_adr_i;
5549 
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
5550 
output [31:0] wbsb_dat_o;
5551 
output wbsb_ack_o;
5552 
input wbsb_clk, wbsb_rst;
5553 
 
5554 
wire wbsa_dat_tmp, wbsb_dat_tmp;
5555 
 
5556 40 unneback 
`define MODULE dpram_2r2w
5557 
`BASE`MODULE # (
5558 
`undef MODULE
5559 33 unneback 
    .data_width(data_width), .addr_width(addr_width) )
5560 32 unneback 
dpram0(
5561 
    .d_a(wbsa_dat_i),
5562 
    .q_a(wbsa_dat_tmp),
5563 
    .adr_a(wbsa_adr_i),
5564 
    .we_a(wbsa_we_i),
5565 
    .clk_a(wbsa_clk),
5566 
    .d_b(wbsb_dat_i),
5567 
    .q_b(wbsb_dat_tmp),
5568 
    .adr_b(wbsb_adr_i),
5569 
    .we_b(wbsb_we_i),
5570 
    .clk_b(wbsb_clk) );
5571 
 
5572 33 unneback 
generate if (dat_o_mask_a==1)
5573 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
5574 
endgenerate
5575 33 unneback 
generate if (dat_o_mask_a==0)
5576 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp;
5577 
endgenerate
5578 
 
5579 33 unneback 
generate if (dat_o_mask_b==1)
5580 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
5581 
endgenerate
5582 33 unneback 
generate if (dat_o_mask_b==0)
5583 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp;
5584 
endgenerate
5585 
 
5586 40 unneback 
`define MODULE spr
5587 
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
5588 
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
5589 
`undef MODULE
5590 32 unneback 
 
5591 
endmodule
5592 40 unneback 
`endif
5593 18 unneback 
//////////////////////////////////////////////////////////////////////
5594 
////                                                              ////
5595 
////  Arithmetic functions                                        ////
5596 
////                                                              ////
5597 
////  Description                                                 ////
5598 
////  Arithmetic functions for ALU and DSP                        ////
5599 
////                                                              ////
5600 
////                                                              ////
5601 
////  To Do:                                                      ////
5602 
////   -                                                          ////
5603 
////                                                              ////
5604 
////  Author(s):                                                  ////
5605 
////      - Michael Unneback, unneback@opencores.org              ////
5606 
////        ORSoC AB                                              ////
5607 
////                                                              ////
5608 
//////////////////////////////////////////////////////////////////////
5609 
////                                                              ////
5610 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
5611 
////                                                              ////
5612 
//// This source file may be used and distributed without         ////
5613 
//// restriction provided that this copyright statement is not    ////
5614 
//// removed from the file and that any derivative work contains  ////
5615 
//// the original copyright notice and the associated disclaimer. ////
5616 
////                                                              ////
5617 
//// This source file is free software; you can redistribute it   ////
5618 
//// and/or modify it under the terms of the GNU Lesser General   ////
5619 
//// Public License as published by the Free Software Foundation; ////
5620 
//// either version 2.1 of the License, or (at your option) any   ////
5621 
//// later version.                                               ////
5622 
////                                                              ////
5623 
//// This source is distributed in the hope that it will be       ////
5624 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
5625 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
5626 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
5627 
//// details.                                                     ////
5628 
////                                                              ////
5629 
//// You should have received a copy of the GNU Lesser General    ////
5630 
//// Public License along with this source; if not, download it   ////
5631 
//// from http://www.opencores.org/lgpl.shtml                     ////
5632 
////                                                              ////
5633 
//////////////////////////////////////////////////////////////////////
5634 
 
5635 40 unneback 
`ifdef MULTS
5636 18 unneback 
// signed multiplication
5637 40 unneback 
`define MODULE mults
5638 
module `BASE`MODULE (a,b,p);
5639 
`undef MODULE
5640 18 unneback 
parameter operand_a_width = 18;
5641 
parameter operand_b_width = 18;
5642 
parameter result_hi = 35;
5643 
parameter result_lo = 0;
5644 
input [operand_a_width-1:0] a;
5645 
input [operand_b_width-1:0] b;
5646 
output [result_hi:result_lo] p;
5647 
wire signed [operand_a_width-1:0] ai;
5648 
wire signed [operand_b_width-1:0] bi;
5649 
wire signed [operand_a_width+operand_b_width-1:0] result;
5650 
 
5651 
    assign ai = a;
5652 
    assign bi = b;
5653 
    assign result = ai * bi;
5654 
    assign p = result[result_hi:result_lo];
5655 
 
5656 
endmodule
5657 40 unneback 
`endif
5658 
`ifdef MULTS18X18
5659 
`define MODULE mults18x18
5660 
module `BASE`MODULE (a,b,p);
5661 
`undef MODULE
5662 18 unneback 
input [17:0] a,b;
5663 
output [35:0] p;
5664 
vl_mult
5665 
    # (.operand_a_width(18), .operand_b_width(18))
5666 
    mult0 (.a(a), .b(b), .p(p));
5667 
endmodule
5668 40 unneback 
`endif
5669 18 unneback 
 
5670 40 unneback 
`ifdef MULT
5671 
`define MODULE mult
5672 18 unneback 
// unsigned multiplication
5673 40 unneback 
module `BASE`MODULE (a,b,p);
5674 
`undef MODULE
5675 18 unneback 
parameter operand_a_width = 18;
5676 
parameter operand_b_width = 18;
5677 
parameter result_hi = 35;
5678 
parameter result_lo = 0;
5679 
input [operand_a_width-1:0] a;
5680 
input [operand_b_width-1:0] b;
5681 
output [result_hi:result_hi] p;
5682 
 
5683 
wire [operand_a_width+operand_b_width-1:0] result;
5684 
 
5685 
    assign result = a * b;
5686 
    assign p = result[result_hi:result_lo];
5687 
 
5688 
endmodule
5689 40 unneback 
`endif
5690 18 unneback 
 
5691 40 unneback 
`ifdef SHIFT_UNIT_32
5692 
`define MODULE shift_unit_32
5693 18 unneback 
// shift unit
5694 
// supporting the following shift functions
5695 
//   SLL
5696 
//   SRL
5697 
//   SRA
5698 
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
5699 40 unneback 
module `BASE`MODULE( din, s, dout, opcode);
5700 
`undef MODULE
5701 18 unneback 
input [31:0] din; // data in operand
5702 
input [4:0] s; // shift operand
5703 
input [1:0] opcode;
5704 
output [31:0] dout;
5705 
 
5706 
parameter opcode_sll = 2'b00;
5707 
//parameter opcode_srl = 2'b01;
5708 
parameter opcode_sra = 2'b10;
5709 
//parameter opcode_ror = 2'b11;
5710 
 
5711 
wire sll, sra;
5712 
assign sll = opcode == opcode_sll;
5713 
assign sra = opcode == opcode_sra;
5714 
 
5715 
wire [15:1] s1;
5716 
wire [3:0] sign;
5717 
wire [7:0] tmp [0:3];
5718 
 
5719 
// first stage is multiplier based
5720 
// shift operand as fractional 8.7
5721 
assign s1[15] = sll & s[2:0]==3'd7;
5722 
assign s1[14] = sll & s[2:0]==3'd6;
5723 
assign s1[13] = sll & s[2:0]==3'd5;
5724 
assign s1[12] = sll & s[2:0]==3'd4;
5725 
assign s1[11] = sll & s[2:0]==3'd3;
5726 
assign s1[10] = sll & s[2:0]==3'd2;
5727 
assign s1[ 9] = sll & s[2:0]==3'd1;
5728 
assign s1[ 8] = s[2:0]==3'd0;
5729 
assign s1[ 7] = !sll & s[2:0]==3'd1;
5730 
assign s1[ 6] = !sll & s[2:0]==3'd2;
5731 
assign s1[ 5] = !sll & s[2:0]==3'd3;
5732 
assign s1[ 4] = !sll & s[2:0]==3'd4;
5733 
assign s1[ 3] = !sll & s[2:0]==3'd5;
5734 
assign s1[ 2] = !sll & s[2:0]==3'd6;
5735 
assign s1[ 1] = !sll & s[2:0]==3'd7;
5736 
 
5737 
assign sign[3] = din[31] & sra;
5738 
assign sign[2] = sign[3] & (&din[31:24]);
5739 
assign sign[1] = sign[2] & (&din[23:16]);
5740 
assign sign[0] = sign[1] & (&din[15:8]);
5741 40 unneback 
`define MODULE mults
5742 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
5743 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
5744 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
5745 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
5746 
`undef MODULE
5747 18 unneback 
// second stage is multiplexer based
5748 
// shift on byte level
5749 
 
5750 
// mux byte 3
5751 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
5752 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
5753 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
5754 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
5755 
                     {8{sign[3]}};
5756 
 
5757 
// mux byte 2
5758 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
5759 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
5760 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
5761 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5762 
                     (s[4:3]==2'b01) ? tmp[3] :
5763 
                     {8{sign[3]}};
5764 
 
5765 
// mux byte 1
5766 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
5767 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
5768 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
5769 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5770 
                     (s[4:3]==2'b01) ? tmp[2] :
5771 
                     (s[4:3]==2'b10) ? tmp[3] :
5772 
                     {8{sign[3]}};
5773 
 
5774 
// mux byte 0
5775 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
5776 
                     (sll) ?  {8{1'b0}}:
5777 
                     (s[4:3]==2'b01) ? tmp[1] :
5778 
                     (s[4:3]==2'b10) ? tmp[2] :
5779 
                     tmp[3];
5780 
 
5781 
endmodule
5782 40 unneback 
`endif
5783 18 unneback 
 
5784 40 unneback 
`ifdef LOGIC_UNIT
5785 18 unneback 
// logic unit
5786 
// supporting the following logic functions
5787 
//    a and b
5788 
//    a or  b
5789 
//    a xor b
5790 
//    not b
5791 40 unneback 
`define MODULE logic_unit
5792 
module `BASE`MODULE( a, b, result, opcode);
5793 
`undef MODULE
5794 18 unneback 
parameter width = 32;
5795 
parameter opcode_and = 2'b00;
5796 
parameter opcode_or  = 2'b01;
5797 
parameter opcode_xor = 2'b10;
5798 
input [width-1:0] a,b;
5799 
output [width-1:0] result;
5800 
input [1:0] opcode;
5801 
 
5802 
assign result = (opcode==opcode_and) ? a & b :
5803 
                (opcode==opcode_or)  ? a | b :
5804 
                (opcode==opcode_xor) ? a ^ b :
5805 
                b;
5806 
 
5807 
endmodule
5808 48 unneback 
`endif
5809 18 unneback 
 
5810 48 unneback 
`ifdef ARITH_UNIT
5811 
`define MODULE arith_unit
5812 
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
5813 
`undef MODULE
5814 18 unneback 
parameter width = 32;
5815 
parameter opcode_add = 1'b0;
5816 
parameter opcode_sub = 1'b1;
5817 
input [width-1:0] a,b;
5818 
input c_in, add_sub, sign;
5819 
output [width-1:0] result;
5820 
output c_out, z, ovfl;
5821 
 
5822 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
5823 
assign z = (result=={width{1'b0}});
5824 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
5825 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
5826 
endmodule
5827 40 unneback 
`endif
5828 48 unneback 
 
5829 
`ifdef COUNT_UNIT
5830 
`define MODULE count_unit
5831 
module `BASE`MODULE (din, dout, opcode);
5832 
`undef MODULE
5833 
parameter width = 32;
5834 
input [width-1:0] din;
5835 
output [width-1:0] dout;
5836 
input opcode;
5837 
 
5838 
integer i;
5839 58 unneback 
wire [width/32+4:0] ff1, fl1;
5840 48 unneback 
 
5841 57 unneback 
/*
5842 48 unneback 
always @(din) begin
5843 
    ff1 = 0; i = 0;
5844 
    while (din[i] == 0 && i < width) begin // complex condition
5845 
        ff1 = ff1 + 1;
5846 
        i = i + 1;
5847 
    end
5848 
end
5849 
 
5850 
always @(din) begin
5851 
    fl1 = width; i = width-1;
5852 
    while (din[i] == 0 && i >= width) begin // complex condition
5853 
        fl1 = fl1 - 1;
5854 
        i = i - 1;
5855 
    end
5856 
end
5857 57 unneback 
*/
5858 48 unneback 
 
5859 
generate
5860 
if (width==32) begin
5861 57 unneback 
 
5862 
    assign ff1 = din[0] ? 6'd1 :
5863 
                 din[1] ? 6'd2 :
5864 
                 din[2] ? 6'd3 :
5865 
                 din[3] ? 6'd4 :
5866 
                 din[4] ? 6'd5 :
5867 
                 din[5] ? 6'd6 :
5868 
                 din[6] ? 6'd7 :
5869 
                 din[7] ? 6'd8 :
5870 
                 din[8] ? 6'd9 :
5871 
                 din[9] ? 6'd10 :
5872 
                 din[10] ? 6'd11 :
5873 
                 din[11] ? 6'd12 :
5874 
                 din[12] ? 6'd13 :
5875 
                 din[13] ? 6'd14 :
5876 
                 din[14] ? 6'd15 :
5877 
                 din[15] ? 6'd16 :
5878 
                 din[16] ? 6'd17 :
5879 
                 din[17] ? 6'd18 :
5880 
                 din[18] ? 6'd19 :
5881 
                 din[19] ? 6'd20 :
5882 
                 din[20] ? 6'd21 :
5883 
                 din[21] ? 6'd22 :
5884 
                 din[22] ? 6'd23 :
5885 
                 din[23] ? 6'd24 :
5886 
                 din[24] ? 6'd25 :
5887 
                 din[25] ? 6'd26 :
5888 
                 din[26] ? 6'd27 :
5889 
                 din[27] ? 6'd28 :
5890 
                 din[28] ? 6'd29 :
5891 
                 din[29] ? 6'd30 :
5892 
                 din[30] ? 6'd31 :
5893 
                 din[31] ? 6'd32 :
5894 
                 6'd0;
5895 
 
5896 
    assign fl1 = din[31] ? 6'd32 :
5897 
                 din[30] ? 6'd31 :
5898 
                 din[29] ? 6'd30 :
5899 
                 din[28] ? 6'd29 :
5900 
                 din[27] ? 6'd28 :
5901 
                 din[26] ? 6'd27 :
5902 
                 din[25] ? 6'd26 :
5903 
                 din[24] ? 6'd25 :
5904 
                 din[23] ? 6'd24 :
5905 
                 din[22] ? 6'd23 :
5906 
                 din[21] ? 6'd22 :
5907 
                 din[20] ? 6'd21 :
5908 
                 din[19] ? 6'd20 :
5909 
                 din[18] ? 6'd19 :
5910 
                 din[17] ? 6'd18 :
5911 
                 din[16] ? 6'd17 :
5912 
                 din[15] ? 6'd16 :
5913 
                 din[14] ? 6'd15 :
5914 
                 din[13] ? 6'd14 :
5915 
                 din[12] ? 6'd13 :
5916 
                 din[11] ? 6'd12 :
5917 
                 din[10] ? 6'd11 :
5918 
                 din[9] ? 6'd10 :
5919 
                 din[8] ? 6'd9 :
5920 
                 din[7] ? 6'd8 :
5921 
                 din[6] ? 6'd7 :
5922 
                 din[5] ? 6'd6 :
5923 
                 din[4] ? 6'd5 :
5924 
                 din[3] ? 6'd4 :
5925 
                 din[2] ? 6'd3 :
5926 
                 din[1] ? 6'd2 :
5927 
                 din[0] ? 6'd1 :
5928 
                 6'd0;
5929 
 
5930 
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
5931 48 unneback 
end
5932 
endgenerate
5933 57 unneback 
 
5934 48 unneback 
generate
5935 
if (width==64) begin
5936 57 unneback 
    assign ff1 = 7'd0;
5937 
    assign fl1 = 7'd0;
5938 
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
5939 48 unneback 
end
5940 
endgenerate
5941 
 
5942 
endmodule
5943 
`endif
5944 
 
5945 
`ifdef EXT_UNIT
5946 
`define MODULE ext_unit
5947 
module `BASE`MODULE ( a, b, F, result, opcode);
5948 
`undef MODULE
5949 
parameter width = 32;
5950 
input [width-1:0] a, b;
5951 
input F;
5952 
output reg [width-1:0] result;
5953 
input [2:0] opcode;
5954 
 
5955 
generate
5956 
if (width==32) begin
5957 
always @ (a or b or F or opcode)
5958 
begin
5959 
    case (opcode)
5960 
    3'b000: result = {{24{1'b0}},a[7:0]};
5961 
    3'b001: result = {{24{a[7]}},a[7:0]};
5962 
    3'b010: result = {{16{1'b0}},a[7:0]};
5963 
    3'b011: result = {{16{a[15]}},a[15:0]};
5964 
    3'b110: result = (F) ? a : b;
5965 
    default: result = {b[15:0],16'h0000};
5966 
    endcase
5967 
end
5968 
end
5969 
endgenerate
5970 
 
5971 
generate
5972 
if (width==64) begin
5973 
always @ (a or b or F or opcode)
5974 
begin
5975 
    case (opcode)
5976 
    3'b000: result = {{56{1'b0}},a[7:0]};
5977 
    3'b001: result = {{56{a[7]}},a[7:0]};
5978 
    3'b010: result = {{48{1'b0}},a[7:0]};
5979 
    3'b011: result = {{48{a[15]}},a[15:0]};
5980 57 unneback 
    3'b110: result = (F) ? a : b;
5981 48 unneback 
    default: result = {32'h00000000,b[15:0],16'h0000};
5982 
    endcase
5983 
end
5984 
end
5985 
endgenerate
5986 
endmodule
5987 
`endif

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