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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 77

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 40 unneback 
`ifdef ALL
14 
 
15 
`define GBUF
16 
`define SYNC_RST
17 
`define PLL
18 
 
19 
`define MULTS
20 
`define MULTS18X18
21 
`define MULT
22 
`define SHIFT_UNIT_32
23 
`define LOGIC_UNIT
24 
 
25 
`define CNT_SHREG_WRAP
26 
`define CNT_SHREG_CE_WRAP
27 
`define CNT_SHREG_CE_CLEAR
28 
`define CNT_SHREG_CE_CLEAR_WRAP
29 
 
30 
`define MUX_ANDOR
31 
`define MUX2_ANDOR
32 
`define MUX3_ANDOR
33 
`define MUX4_ANDOR
34 
`define MUX5_ANDOR
35 
`define MUX6_ANDOR
36 43 unneback 
`define PARITY
37 40 unneback 
 
38 
`define ROM_INIT
39 
`define RAM
40 
`define RAM_BE
41 
`define DPRAM_1R1W
42 
`define DPRAM_2R1W
43 
`define DPRAM_2R2W
44 75 unneback 
`define DPRAM_BE_2R2W
45 40 unneback 
`define FIFO_1R1W_FILL_LEVEL_SYNC
46 
`define FIFO_2R2W_SYNC_SIMPLEX
47 
`define FIFO_CMP_ASYNC
48 
`define FIFO_1R1W_ASYNC
49 
`define FIFO_2R2W_ASYNC
50 
`define FIFO_2R2W_ASYNC_SIMPLEX
51 48 unneback 
`define REG_FILE
52 40 unneback 
 
53 
`define DFF
54 
`define DFF_ARRAY
55 
`define DFF_CE
56 
`define DFF_CE_CLEAR
57 
`define DF_CE_SET
58 
`define SPR
59 
`define SRP
60 
`define DFF_SR
61 
`define LATCH
62 
`define SHREG
63 
`define SHREG_CE
64 
`define DELAY
65 
`define DELAY_EMPTYFLAG
66 
 
67 75 unneback 
`define WB3AVALON_BRIDGE
68 40 unneback 
`define WB3WB3_BRIDGE
69 
`define WB3_ARBITER_TYPE1
70 59 unneback 
`define WB_B3_RAM_BE
71 49 unneback 
`define WB_B4_RAM_BE
72 48 unneback 
`define WB_B4_ROM
73 40 unneback 
`define WB_BOOT_ROM
74 
`define WB_DPRAM
75 
 
76 44 unneback 
`define IO_DFF_OE
77 
`define O_DFF
78 
 
79 40 unneback 
`endif
80 
 
81 
`ifdef PLL
82 
`ifndef SYNC_RST
83 
`define SYNC_RST
84 
`endif
85 
`endif
86 
 
87 
`ifdef SYNC_RST
88 
`ifndef GBUF
89 
`define GBUF
90 
`endif
91 
`endif
92 
 
93 
`ifdef WB_DPRAM
94 
`ifndef DPRAM_2R2W
95 
`define DPRAM_2R2W
96 
`endif
97 
`ifndef SPR
98 
`define SPR
99 
`endif
100 
`endif
101 
 
102 62 unneback 
`ifdef WB_B3_RAM_BE
103 
`ifndef WB3_ARBITER_TYPE1
104 
`define WB3_ARBITER_TYPE1
105 
`endif
106 
`ifndef RAM_BE
107 
`define RAM_BE
108 
`endif
109 
`endif
110 
 
111 40 unneback 
`ifdef WB3_ARBITER_TYPE1
112 42 unneback 
`ifndef SPR
113 
`define SPR
114 
`endif
115 40 unneback 
`ifndef MUX_ANDOR
116 
`define MUX_ANDOR
117 
`endif
118 
`endif
119 
 
120 76 unneback 
`ifdef WB3AVALON_BRIDGE
121 
`ifndef WB3WB3_BRIDGE
122 
`define WB3WB3_BRIDGE
123 
`endif
124 
`endif
125 
 
126 40 unneback 
`ifdef WB3WB3_BRIDGE
127 
`ifndef CNT_SHREG_CE_CLEAR
128 
`define CNT_SHREG_CE_CLEAR
129 
`endif
130 
`ifndef DFF
131 
`define DFF
132 
`endif
133 
`ifndef DFF_CE
134 
`define DFF_CE
135 
`endif
136 
`ifndef CNT_SHREG_CE_CLEAR
137 
`define CNT_SHREG_CE_CLEAR
138 
`endif
139 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
140 
`define FIFO_2R2W_ASYNC_SIMPLEX
141 
`endif
142 
`endif
143 
 
144 
`ifdef MULTS18X18
145 
`ifndef MULTS
146 
`define MULTS
147 
`endif
148 
`endif
149 
 
150 
`ifdef SHIFT_UNIT_32
151 
`ifndef MULTS
152 
`define MULTS
153 
`endif
154 
`endif
155 
 
156 
`ifdef MUX2_ANDOR
157 
`ifndef MUX_ANDOR
158 
`define MUX_ANDOR
159 
`endif
160 
`endif
161 
 
162 
`ifdef MUX3_ANDOR
163 
`ifndef MUX_ANDOR
164 
`define MUX_ANDOR
165 
`endif
166 
`endif
167 
 
168 
`ifdef MUX4_ANDOR
169 
`ifndef MUX_ANDOR
170 
`define MUX_ANDOR
171 
`endif
172 
`endif
173 
 
174 
`ifdef MUX5_ANDOR
175 
`ifndef MUX_ANDOR
176 
`define MUX_ANDOR
177 
`endif
178 
`endif
179 
 
180 
`ifdef MUX6_ANDOR
181 
`ifndef MUX_ANDOR
182 
`define MUX_ANDOR
183 
`endif
184 
`endif
185 
 
186 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
187 
`ifndef CNT_BIN_CE
188 
`define CNT_BIN_CE
189 
`endif
190 
`ifndef DPRAM_1R1W
191 
`define DPRAM_1R1W
192 
`endif
193 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
194 
`define CNT_BIN_CE_REW_Q_ZQ_L1
195 
`endif
196 
`endif
197 
 
198 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
199 
`ifndef CNT_LFSR_CE
200 
`define CNT_LFSR_CE
201 
`endif
202 
`ifndef DPRAM_2R2W
203 
`define DPRAM_2R2W
204 
`endif
205 
`ifndef CNT_BIN_CE_REW_ZQ_L1
206 
`define CNT_BIN_CE_REW_ZQ_L1
207 
`endif
208 
`endif
209 
 
210 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
211 
`ifndef CNT_GRAY_CE_BIN
212 
`define CNT_GRAY_CE_BIN
213 
`endif
214 
`ifndef DPRAM_2R2W
215 
`define DPRAM_2R2W
216 
`endif
217 
`ifndef FIFO_CMP_ASYNC
218 
`define FIFO_CMP_ASYNC
219 
`endif
220 
`endif
221 
 
222 
`ifdef FIFO_2R2W_ASYNC
223 
`ifndef FIFO_1R1W_ASYNC
224 
`define FIFO_1R1W_ASYNC
225 
`endif
226 
`endif
227 
 
228 
`ifdef FIFO_1R1W_ASYNC
229 
`ifndef CNT_GRAY_CE_BIN
230 
`define CNT_GRAY_CE_BIN
231 
`endif
232 
`ifndef DPRAM_1R1W
233 
`define DPRAM_1R1W
234 
`endif
235 
`ifndef FIFO_CMP_ASYNC
236 
`define FIFO_CMP_ASYNC
237 
`endif
238 
`endif
239 
 
240 
`ifdef FIFO_CMP_ASYNC
241 
`ifndef DFF_SR
242 
`define DFF_SR
243 
`endif
244 
`ifndef DFF
245 
`define DFF
246 
`endif
247 
`endif
248 48 unneback 
 
249 
`ifdef REG_FILE
250 
`ifndef DPRAM_1R1W
251 
`define DPRAM_1R1W
252 
`endif
253 
`endif
254 62 unneback 
//////////////////////////////////////////////////////////////////////
255 6 unneback 
////                                                              ////
256 
////  Versatile library, clock and reset                          ////
257 
////                                                              ////
258 
////  Description                                                 ////
259 
////  Logic related to clock and reset                            ////
260 
////                                                              ////
261 
////                                                              ////
262 
////  To Do:                                                      ////
263 
////   - add more different registers                             ////
264 
////                                                              ////
265 
////  Author(s):                                                  ////
266 
////      - Michael Unneback, unneback@opencores.org              ////
267 
////        ORSoC AB                                              ////
268 
////                                                              ////
269 
//////////////////////////////////////////////////////////////////////
270 
////                                                              ////
271 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
272 
////                                                              ////
273 
//// This source file may be used and distributed without         ////
274 
//// restriction provided that this copyright statement is not    ////
275 
//// removed from the file and that any derivative work contains  ////
276 
//// the original copyright notice and the associated disclaimer. ////
277 
////                                                              ////
278 
//// This source file is free software; you can redistribute it   ////
279 
//// and/or modify it under the terms of the GNU Lesser General   ////
280 
//// Public License as published by the Free Software Foundation; ////
281 
//// either version 2.1 of the License, or (at your option) any   ////
282 
//// later version.                                               ////
283 
////                                                              ////
284 
//// This source is distributed in the hope that it will be       ////
285 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
286 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
287 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
288 
//// details.                                                     ////
289 
////                                                              ////
290 
//// You should have received a copy of the GNU Lesser General    ////
291 
//// Public License along with this source; if not, download it   ////
292 
//// from http://www.opencores.org/lgpl.shtml                     ////
293 
////                                                              ////
294 
//////////////////////////////////////////////////////////////////////
295 
 
296 48 unneback 
`ifdef ACTEL
297 
`ifdef GBUF
298 
`timescale 1 ns/100 ps
299 6 unneback 
// Global buffer
300 
// usage:
301 
// use to enable global buffers for high fan out signals such as clock and reset
302 
// Version: 8.4 8.4.0.33
303 
module gbuf(GL,CLK);
304 
output GL;
305 
input  CLK;
306 
 
307 
    wire GND;
308 
 
309 
    GND GND_1_net(.Y(GND));
310 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
311 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
312 
 
313 
endmodule
314 
`timescale 1 ns/1 ns
315 40 unneback 
`define MODULE gbuf
316 
module `BASE`MODULE ( i, o);
317 
`undef MODULE
318 6 unneback 
input i;
319 
output o;
320 
`ifdef SIM_GBUF
321 
assign o=i;
322 
`else
323 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
324 
`endif
325 
endmodule
326 40 unneback 
`endif
327 33 unneback 
 
328 6 unneback 
`else
329 33 unneback 
 
330 40 unneback 
`ifdef ALTERA
331 
`ifdef GBUF
332 21 unneback 
//altera
333 40 unneback 
`define MODULE gbuf
334 
module `BASE`MODULE ( i, o);
335 
`undef MODULE
336 33 unneback 
input i;
337 
output o;
338 
assign o = i;
339 
endmodule
340 40 unneback 
`endif
341 33 unneback 
 
342 6 unneback 
`else
343 
 
344 40 unneback 
`ifdef GBUF
345 6 unneback 
`timescale 1 ns/100 ps
346 40 unneback 
`define MODULE
347 
module `BASE`MODULE ( i, o);
348 
`undef MODULE
349 6 unneback 
input i;
350 
output o;
351 
assign o = i;
352 
endmodule
353 40 unneback 
`endif
354 6 unneback 
`endif // ALTERA
355 
`endif //ACTEL
356 
 
357 40 unneback 
`ifdef SYNC_RST
358 6 unneback 
// sync reset
359 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
360 6 unneback 
// output active high global reset sync with two DFFs
361 
`timescale 1 ns/100 ps
362 40 unneback 
`define MODULE sync_rst
363 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
364 
`undef MODULE
365 6 unneback 
input rst_n_i, clk;
366 
output rst_o;
367 18 unneback 
reg [1:0] tmp;
368 6 unneback 
always @ (posedge clk or negedge rst_n_i)
369 
if (!rst_n_i)
370 17 unneback 
        tmp <= 2'b11;
371 6 unneback 
else
372 33 unneback 
        tmp <= {1'b0,tmp[1]};
373 40 unneback 
`define MODULE gbuf
374 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
375 
`undef MODULE
376 6 unneback 
endmodule
377 40 unneback 
`endif
378 6 unneback 
 
379 40 unneback 
`ifdef PLL
380 6 unneback 
// vl_pll
381 
`ifdef ACTEL
382 32 unneback 
///////////////////////////////////////////////////////////////////////////////
383 17 unneback 
`timescale 1 ps/1 ps
384 40 unneback 
`define MODULE pll
385 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
386 
`undef MODULE
387 6 unneback 
parameter index = 0;
388 
parameter number_of_clk = 1;
389 17 unneback 
parameter period_time_0 = 20000;
390 
parameter period_time_1 = 20000;
391 
parameter period_time_2 = 20000;
392 
parameter lock_delay = 2000000;
393 6 unneback 
input clk_i, rst_n_i;
394 
output lock;
395 
output reg [0:number_of_clk-1] clk_o;
396 
output [0:number_of_clk-1] rst_o;
397 
 
398 
`ifdef SIM_PLL
399 
 
400 
always
401 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
402 
 
403 
generate if (number_of_clk > 1)
404 
always
405 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
406 
endgenerate
407 
 
408 
generate if (number_of_clk > 2)
409 
always
410 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
411 
endgenerate
412 
 
413 
genvar i;
414 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
415 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
416 
end
417 
endgenerate
418 
 
419 
assign #lock_delay lock = rst_n_i;
420 
 
421 
endmodule
422 
`else
423 
generate if (number_of_clk==1 & index==0) begin
424 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
425 
end
426 
endgenerate // index==0
427 
generate if (number_of_clk==1 & index==1) begin
428 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
429 
end
430 
endgenerate // index==1
431 
generate if (number_of_clk==1 & index==2) begin
432 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
433 
end
434 
endgenerate // index==2
435 
generate if (number_of_clk==1 & index==3) begin
436 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
437 
end
438 
endgenerate // index==0
439 
 
440 
generate if (number_of_clk==2 & index==0) begin
441 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
442 
end
443 
endgenerate // index==0
444 
generate if (number_of_clk==2 & index==1) begin
445 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
446 
end
447 
endgenerate // index==1
448 
generate if (number_of_clk==2 & index==2) begin
449 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
450 
end
451 
endgenerate // index==2
452 
generate if (number_of_clk==2 & index==3) begin
453 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
454 
end
455 
endgenerate // index==0
456 
 
457 
generate if (number_of_clk==3 & index==0) begin
458 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
459 
end
460 
endgenerate // index==0
461 
generate if (number_of_clk==3 & index==1) begin
462 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
463 
end
464 
endgenerate // index==1
465 
generate if (number_of_clk==3 & index==2) begin
466 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
467 
end
468 
endgenerate // index==2
469 
generate if (number_of_clk==3 & index==3) begin
470 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
471 
end
472 
endgenerate // index==0
473 
 
474 
genvar i;
475 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
476 40 unneback 
`define MODULE sync_rst
477 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
478 
`undef MODULE
479 6 unneback 
end
480 
endgenerate
481 
endmodule
482 
`endif
483 32 unneback 
///////////////////////////////////////////////////////////////////////////////
484 6 unneback 
 
485 
`else
486 
 
487 32 unneback 
///////////////////////////////////////////////////////////////////////////////
488 6 unneback 
`ifdef ALTERA
489 
 
490 32 unneback 
`timescale 1 ps/1 ps
491 40 unneback 
`define MODULE pll
492 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
493 
`undef MODULE
494 32 unneback 
parameter index = 0;
495 
parameter number_of_clk = 1;
496 
parameter period_time_0 = 20000;
497 
parameter period_time_1 = 20000;
498 
parameter period_time_2 = 20000;
499 
parameter period_time_3 = 20000;
500 
parameter period_time_4 = 20000;
501 
parameter lock_delay = 2000000;
502 
input clk_i, rst_n_i;
503 
output lock;
504 
output reg [0:number_of_clk-1] clk_o;
505 
output [0:number_of_clk-1] rst_o;
506 
 
507 
`ifdef SIM_PLL
508 
 
509 
always
510 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
511 
 
512 
generate if (number_of_clk > 1)
513 
always
514 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
515 
endgenerate
516 
 
517 
generate if (number_of_clk > 2)
518 
always
519 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
520 
endgenerate
521 
 
522 33 unneback 
generate if (number_of_clk > 3)
523 32 unneback 
always
524 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
525 
endgenerate
526 
 
527 33 unneback 
generate if (number_of_clk > 4)
528 32 unneback 
always
529 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
530 
endgenerate
531 
 
532 
genvar i;
533 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
534 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
535 
end
536 
endgenerate
537 
 
538 33 unneback 
//assign #lock_delay lock = rst_n_i;
539 
assign lock = rst_n_i;
540 32 unneback 
 
541 
endmodule
542 6 unneback 
`else
543 
 
544 33 unneback 
`ifdef VL_PLL0
545 
`ifdef VL_PLL0_CLK1
546 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
547 
`endif
548 
`ifdef VL_PLL0_CLK2
549 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
550 
`endif
551 
`ifdef VL_PLL0_CLK3
552 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
553 
`endif
554 
`ifdef VL_PLL0_CLK4
555 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
556 
`endif
557 
`ifdef VL_PLL0_CLK5
558 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
559 
`endif
560 
`endif
561 32 unneback 
 
562 33 unneback 
`ifdef VL_PLL1
563 
`ifdef VL_PLL1_CLK1
564 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
565 
`endif
566 
`ifdef VL_PLL1_CLK2
567 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
568 
`endif
569 
`ifdef VL_PLL1_CLK3
570 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
571 
`endif
572 
`ifdef VL_PLL1_CLK4
573 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
574 
`endif
575 
`ifdef VL_PLL1_CLK5
576 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
577 
`endif
578 
`endif
579 32 unneback 
 
580 33 unneback 
`ifdef VL_PLL2
581 
`ifdef VL_PLL2_CLK1
582 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
583 
`endif
584 
`ifdef VL_PLL2_CLK2
585 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
586 
`endif
587 
`ifdef VL_PLL2_CLK3
588 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
589 
`endif
590 
`ifdef VL_PLL2_CLK4
591 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
592 
`endif
593 
`ifdef VL_PLL2_CLK5
594 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
595 
`endif
596 
`endif
597 32 unneback 
 
598 33 unneback 
`ifdef VL_PLL3
599 
`ifdef VL_PLL3_CLK1
600 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
601 
`endif
602 
`ifdef VL_PLL3_CLK2
603 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
604 
`endif
605 
`ifdef VL_PLL3_CLK3
606 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
607 
`endif
608 
`ifdef VL_PLL3_CLK4
609 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
610 
`endif
611 
`ifdef VL_PLL3_CLK5
612 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
613 
`endif
614 
`endif
615 32 unneback 
 
616 
genvar i;
617 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
618 40 unneback 
`define MODULE sync_rst
619 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
620 
`undef MODULE
621 32 unneback 
end
622 
endgenerate
623 
endmodule
624 
`endif
625 
///////////////////////////////////////////////////////////////////////////////
626 
 
627 
`else
628 
 
629 6 unneback 
// generic PLL
630 17 unneback 
`timescale 1 ps/1 ps
631 40 unneback 
`define MODULE pll
632 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
633 
`undef MODULE
634 6 unneback 
parameter index = 0;
635 
parameter number_of_clk = 1;
636 17 unneback 
parameter period_time_0 = 20000;
637 
parameter period_time_1 = 20000;
638 
parameter period_time_2 = 20000;
639 6 unneback 
parameter lock_delay = 2000;
640 
input clk_i, rst_n_i;
641 
output lock;
642 
output reg [0:number_of_clk-1] clk_o;
643 
output [0:number_of_clk-1] rst_o;
644 
 
645 
always
646 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
647 
 
648 
generate if (number_of_clk > 1)
649 
always
650 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
651 
endgenerate
652 
 
653 
generate if (number_of_clk > 2)
654 
always
655 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
656 
endgenerate
657 
 
658 
genvar i;
659 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
660 40 unneback 
`define MODULE sync_rst
661 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
662 
`undef MODULE
663 6 unneback 
end
664 
endgenerate
665 
 
666 
assign #lock_delay lock = rst_n_i;
667 
 
668 
endmodule
669 
 
670 
`endif //altera
671 17 unneback 
`endif //actel
672 40 unneback 
`undef MODULE
673 
`endif//////////////////////////////////////////////////////////////////////
674 6 unneback 
////                                                              ////
675 
////  Versatile library, registers                                ////
676 
////                                                              ////
677 
////  Description                                                 ////
678 
////  Different type of registers                                 ////
679 
////                                                              ////
680 
////                                                              ////
681 
////  To Do:                                                      ////
682 
////   - add more different registers                             ////
683 
////                                                              ////
684 
////  Author(s):                                                  ////
685 
////      - Michael Unneback, unneback@opencores.org              ////
686 
////        ORSoC AB                                              ////
687 
////                                                              ////
688 
//////////////////////////////////////////////////////////////////////
689 
////                                                              ////
690 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
691 
////                                                              ////
692 
//// This source file may be used and distributed without         ////
693 
//// restriction provided that this copyright statement is not    ////
694 
//// removed from the file and that any derivative work contains  ////
695 
//// the original copyright notice and the associated disclaimer. ////
696 
////                                                              ////
697 
//// This source file is free software; you can redistribute it   ////
698 
//// and/or modify it under the terms of the GNU Lesser General   ////
699 
//// Public License as published by the Free Software Foundation; ////
700 
//// either version 2.1 of the License, or (at your option) any   ////
701 
//// later version.                                               ////
702 
////                                                              ////
703 
//// This source is distributed in the hope that it will be       ////
704 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
705 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
706 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
707 
//// details.                                                     ////
708 
////                                                              ////
709 
//// You should have received a copy of the GNU Lesser General    ////
710 
//// Public License along with this source; if not, download it   ////
711 
//// from http://www.opencores.org/lgpl.shtml                     ////
712 
////                                                              ////
713 
//////////////////////////////////////////////////////////////////////
714 
 
715 40 unneback 
`ifdef DFF
716 
`define MODULE dff
717 
module `BASE`MODULE ( d, q, clk, rst);
718 
`undef MODULE
719 6 unneback 
        parameter width = 1;
720 
        parameter reset_value = 0;
721 
 
722 
        input [width-1:0] d;
723 
        input clk, rst;
724 
        output reg [width-1:0] q;
725 
 
726 
        always @ (posedge clk or posedge rst)
727 
        if (rst)
728 
                q <= reset_value;
729 
        else
730 
                q <= d;
731 
 
732 
endmodule
733 40 unneback 
`endif
734 6 unneback 
 
735 40 unneback 
`ifdef DFF_ARRAY
736 
`define MODULE dff_array
737 
module `BASE`MODULE ( d, q, clk, rst);
738 
`undef MODULE
739 6 unneback 
 
740 
        parameter width = 1;
741 
        parameter depth = 2;
742 
        parameter reset_value = 1'b0;
743 
 
744 
        input [width-1:0] d;
745 
        input clk, rst;
746 
        output [width-1:0] q;
747 
        reg  [0:depth-1] q_tmp [width-1:0];
748 
        integer i;
749 
        always @ (posedge clk or posedge rst)
750 
        if (rst) begin
751 
            for (i=0;i<depth;i=i+1)
752 
                q_tmp[i] <= {width{reset_value}};
753 
        end else begin
754 
            q_tmp[0] <= d;
755 
            for (i=1;i<depth;i=i+1)
756 
                q_tmp[i] <= q_tmp[i-1];
757 
        end
758 
 
759 
    assign q = q_tmp[depth-1];
760 
 
761 
endmodule
762 40 unneback 
`endif
763 6 unneback 
 
764 40 unneback 
`ifdef DFF_CE
765 
`define MODULE dff_ce
766 
module `BASE`MODULE ( d, ce, q, clk, rst);
767 
`undef MODULE
768 6 unneback 
 
769 
        parameter width = 1;
770 
        parameter reset_value = 0;
771 
 
772 
        input [width-1:0] d;
773 
        input ce, clk, rst;
774 
        output reg [width-1:0] q;
775 
 
776 
        always @ (posedge clk or posedge rst)
777 
        if (rst)
778 
                q <= reset_value;
779 
        else
780 
                if (ce)
781 
                        q <= d;
782 
 
783 
endmodule
784 40 unneback 
`endif
785 6 unneback 
 
786 40 unneback 
`ifdef DFF_CE_CLEAR
787 
`define MODULE dff_ce_clear
788 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
789 
`undef MODULE
790 8 unneback 
 
791 
        parameter width = 1;
792 
        parameter reset_value = 0;
793 
 
794 
        input [width-1:0] d;
795 10 unneback 
        input ce, clear, clk, rst;
796 8 unneback 
        output reg [width-1:0] q;
797 
 
798 
        always @ (posedge clk or posedge rst)
799 
        if (rst)
800 
            q <= reset_value;
801 
        else
802 
            if (ce)
803 
                if (clear)
804 
                    q <= {width{1'b0}};
805 
                else
806 
                    q <= d;
807 
 
808 
endmodule
809 40 unneback 
`endif
810 8 unneback 
 
811 40 unneback 
`ifdef DF_CE_SET
812 
`define MODULE dff_ce_set
813 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
814 
`undef MODULE
815 24 unneback 
 
816 
        parameter width = 1;
817 
        parameter reset_value = 0;
818 
 
819 
        input [width-1:0] d;
820 
        input ce, set, clk, rst;
821 
        output reg [width-1:0] q;
822 
 
823 
        always @ (posedge clk or posedge rst)
824 
        if (rst)
825 
            q <= reset_value;
826 
        else
827 
            if (ce)
828 
                if (set)
829 
                    q <= {width{1'b1}};
830 
                else
831 
                    q <= d;
832 
 
833 
endmodule
834 40 unneback 
`endif
835 24 unneback 
 
836 40 unneback 
`ifdef SPR
837 
`define MODULE spr
838 
module `BASE`MODULE ( sp, r, q, clk, rst);
839 
`undef MODULE
840 
 
841 64 unneback 
        //parameter width = 1;
842 
        parameter reset_value = 1'b0;
843 29 unneback 
 
844 
        input sp, r;
845 
        output reg q;
846 
        input clk, rst;
847 
 
848 
        always @ (posedge clk or posedge rst)
849 
        if (rst)
850 
            q <= reset_value;
851 
        else
852 
            if (sp)
853 
                q <= 1'b1;
854 
            else if (r)
855 
                q <= 1'b0;
856 
 
857 
endmodule
858 40 unneback 
`endif
859 29 unneback 
 
860 40 unneback 
`ifdef SRP
861 
`define MODULE srp
862 
module `BASE`MODULE ( s, rp, q, clk, rst);
863 
`undef MODULE
864 
 
865 29 unneback 
        parameter width = 1;
866 
        parameter reset_value = 0;
867 
 
868 
        input s, rp;
869 
        output reg q;
870 
        input clk, rst;
871 
 
872 
        always @ (posedge clk or posedge rst)
873 
        if (rst)
874 
            q <= reset_value;
875 
        else
876 
            if (rp)
877 
                q <= 1'b0;
878 
            else if (s)
879 
                q <= 1'b1;
880 
 
881 
endmodule
882 40 unneback 
`endif
883 29 unneback 
 
884 40 unneback 
`ifdef ALTERA
885 29 unneback 
 
886 40 unneback 
`ifdef DFF_SR
887 6 unneback 
// megafunction wizard: %LPM_FF%
888 
// GENERATION: STANDARD
889 
// VERSION: WM1.0
890 
// MODULE: lpm_ff
891 
 
892 
// ============================================================
893 
// File Name: dff_sr.v
894 
// Megafunction Name(s):
895 
//                      lpm_ff
896 
//
897 
// Simulation Library Files(s):
898 
//                      lpm
899 
// ============================================================
900 
// ************************************************************
901 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
902 
//
903 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
904 
// ************************************************************
905 
 
906 
 
907 
//Copyright (C) 1991-2010 Altera Corporation
908 
//Your use of Altera Corporation's design tools, logic functions
909 
//and other software and tools, and its AMPP partner logic
910 
//functions, and any output files from any of the foregoing
911 
//(including device programming or simulation files), and any
912 
//associated documentation or information are expressly subject
913 
//to the terms and conditions of the Altera Program License
914 
//Subscription Agreement, Altera MegaCore Function License
915 
//Agreement, or other applicable license agreement, including,
916 
//without limitation, that your use is for the sole purpose of
917 
//programming logic devices manufactured by Altera and sold by
918 
//Altera or its authorized distributors.  Please refer to the
919 
//applicable agreement for further details.
920 
 
921 
 
922 
// synopsys translate_off
923 
`timescale 1 ps / 1 ps
924 
// synopsys translate_on
925 40 unneback 
`define MODULE dff_sr
926 
module `BASE`MODULE (
927 
`undef MODULE
928 
 
929 6 unneback 
        aclr,
930 
        aset,
931 
        clock,
932 
        data,
933 
        q);
934 
 
935 
        input     aclr;
936 
        input     aset;
937 
        input     clock;
938 
        input     data;
939 
        output    q;
940 
 
941 
        wire [0:0] sub_wire0;
942 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
943 
        wire  q = sub_wire1;
944 
        wire  sub_wire2 = data;
945 
        wire  sub_wire3 = sub_wire2;
946 
 
947 
        lpm_ff  lpm_ff_component (
948 
                                .aclr (aclr),
949 
                                .clock (clock),
950 
                                .data (sub_wire3),
951 
                                .aset (aset),
952 
                                .q (sub_wire0)
953 
                                // synopsys translate_off
954 
                                ,
955 
                                .aload (),
956 
                                .enable (),
957 
                                .sclr (),
958 
                                .sload (),
959 
                                .sset ()
960 
                                // synopsys translate_on
961 
                                );
962 
        defparam
963 
                lpm_ff_component.lpm_fftype = "DFF",
964 
                lpm_ff_component.lpm_type = "LPM_FF",
965 
                lpm_ff_component.lpm_width = 1;
966 
 
967 
 
968 
endmodule
969 
 
970 
// ============================================================
971 
// CNX file retrieval info
972 
// ============================================================
973 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
974 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
975 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
976 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
977 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
978 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
979 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
980 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
981 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
982 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
983 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
984 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
985 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
986 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
987 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
988 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
989 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
990 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
991 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
992 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
993 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
994 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
995 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
996 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
997 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
998 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
999 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1000 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1001 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1002 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1003 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1004 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1005 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1006 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1007 
// Retrieval info: LIB_FILE: lpm
1008 40 unneback 
`endif
1009 6 unneback 
 
1010 
`else
1011 
 
1012 40 unneback 
`ifdef DFF_SR
1013 
`define MODULE dff_sr
1014 
module `BASE`MODULE ( aclr, aset, clock, data, q);
1015 
`undef MODULE
1016 6 unneback 
 
1017 
    input         aclr;
1018 
    input         aset;
1019 
    input         clock;
1020 
    input         data;
1021 
    output reg    q;
1022 
 
1023 
   always @ (posedge clock or posedge aclr or posedge aset)
1024 
     if (aclr)
1025 
       q <= 1'b0;
1026 
     else if (aset)
1027 
       q <= 1'b1;
1028 
     else
1029 
       q <= data;
1030 
 
1031 
endmodule
1032 40 unneback 
`endif
1033 6 unneback 
 
1034 
`endif
1035 
 
1036 
// LATCH
1037 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1038 
`ifdef ALTERA
1039 40 unneback 
 
1040 
`ifdef LATCH
1041 
`define MODULE latch
1042 
module `BASE`MODULE ( d, le, q, clk);
1043 
`undef MODULE
1044 6 unneback 
input d, le;
1045 
output q;
1046 
input clk;
1047 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1048 
endmodule
1049 40 unneback 
`endif
1050 
 
1051 6 unneback 
`else
1052 40 unneback 
 
1053 
`ifdef LATCH
1054 
`define MODULE latch
1055 
module `BASE`MODULE ( d, le, q, clk);
1056 
`undef MODULE
1057 6 unneback 
input d, le;
1058 48 unneback 
input clk;
1059 
always @ (le or d)
1060 60 unneback 
if (le)
1061 48 unneback 
    d <= q;
1062 6 unneback 
endmodule
1063 15 unneback 
`endif
1064 
 
1065 40 unneback 
`endif
1066 
 
1067 
`ifdef SHREG
1068 
`define MODULE shreg
1069 
module `BASE`MODULE ( d, q, clk, rst);
1070 
`undef MODULE
1071 
 
1072 17 unneback 
parameter depth = 10;
1073 
input d;
1074 
output q;
1075 
input clk, rst;
1076 
 
1077 
reg [1:depth] dffs;
1078 
 
1079 
always @ (posedge clk or posedge rst)
1080 
if (rst)
1081 
    dffs <= {depth{1'b0}};
1082 
else
1083 
    dffs <= {d,dffs[1:depth-1]};
1084 
assign q = dffs[depth];
1085 
endmodule
1086 40 unneback 
`endif
1087 17 unneback 
 
1088 40 unneback 
`ifdef SHREG_CE
1089 
`define MODULE shreg_ce
1090 
module `BASE`MODULE ( d, ce, q, clk, rst);
1091 
`undef MODULE
1092 17 unneback 
parameter depth = 10;
1093 
input d, ce;
1094 
output q;
1095 
input clk, rst;
1096 
 
1097 
reg [1:depth] dffs;
1098 
 
1099 
always @ (posedge clk or posedge rst)
1100 
if (rst)
1101 
    dffs <= {depth{1'b0}};
1102 
else
1103 
    if (ce)
1104 
        dffs <= {d,dffs[1:depth-1]};
1105 
assign q = dffs[depth];
1106 
endmodule
1107 40 unneback 
`endif
1108 17 unneback 
 
1109 40 unneback 
`ifdef DELAY
1110 
`define MODULE delay
1111 
module `BASE`MODULE ( d, q, clk, rst);
1112 
`undef MODULE
1113 15 unneback 
parameter depth = 10;
1114 
input d;
1115 
output q;
1116 
input clk, rst;
1117 
 
1118 
reg [1:depth] dffs;
1119 
 
1120 
always @ (posedge clk or posedge rst)
1121 
if (rst)
1122 
    dffs <= {depth{1'b0}};
1123 
else
1124 
    dffs <= {d,dffs[1:depth-1]};
1125 
assign q = dffs[depth];
1126 17 unneback 
endmodule
1127 40 unneback 
`endif
1128 17 unneback 
 
1129 40 unneback 
`ifdef DELAY_EMPTYFLAG
1130 
`define MODULE delay_emptyflag
1131 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1132 40 unneback 
`undef MODULE
1133 17 unneback 
parameter depth = 10;
1134 
input d;
1135 
output q, emptyflag;
1136 
input clk, rst;
1137 
 
1138 
reg [1:depth] dffs;
1139 
 
1140 
always @ (posedge clk or posedge rst)
1141 
if (rst)
1142 
    dffs <= {depth{1'b0}};
1143 
else
1144 
    dffs <= {d,dffs[1:depth-1]};
1145 
assign q = dffs[depth];
1146 
assign emptyflag = !(|dffs);
1147 
endmodule
1148 40 unneback 
`endif
1149 75 unneback 
 
1150 
`ifdef ASYNC_REG_REQ_ACK
1151 
`define MODULE async_reg_req_ack
1152 
module `BASE`MODULE ( d, q, req_i, req_o, ack_i, ack_o, clk_a, rst_a, clk_b, rst_b);
1153 
`undef MODULE
1154 
parameter data_width = 8;
1155 
input [data_width-1:0] d;
1156 
output [data_width-1:0] q;
1157 
input req_i;
1158 
output req_o;
1159 
input ack_i;
1160 
output ack_o;
1161 
input clk_a, rst_a, clk_b, rst_b;
1162 
 
1163 
reg [3:0] reqi; // 3: last req in clk_a, 2: input dff, 1-0: sync
1164 
wire rst;
1165 
 
1166 
always @ (posedge clk_a or rst_a)
1167 
if (rst_a)
1168 
    q <= {data_width{1'b0}};
1169 
else
1170 
    if (req_i)
1171 
        q <= d;
1172 
 
1173 
assign rst = ack_i | rst_a;
1174 
always @ (posedge clk_a or posedge rst)
1175 
if (rst)
1176 
    req[2] <= 1'b0;
1177 
else
1178 
    req[2] <= req_i & !ack_o;
1179 
 
1180 
always @ (posedge clk_a or posedge rst_a)
1181 
if (rst_a)
1182 
    req[3] <= 1'b0;
1183 
else
1184 
    req[3] <= req[2];
1185 
 
1186 
always @ (posedge clk_b or posedge rst_b)
1187 
if (rst_b)
1188 
    req[1:0] <= 2'b00;
1189 
else
1190 
    if (ack_i)
1191 
        req[1:0] <= 2'b00;
1192 
    else
1193 
        req[1:0] <= req[2:1];
1194 
assign req_o = req[0];
1195 
 
1196 
always @ (posedge clk_a or posedge rst_a)
1197 
if (rst_a)
1198 
    ack_o <= 1'b0;
1199 
else
1200 
    ack_o <= req[3] & req[2];
1201 
 
1202 
endmodule
1203 
`endif
1204 17 unneback 
//////////////////////////////////////////////////////////////////////
1205 6 unneback 
////                                                              ////
1206 18 unneback 
////  Logic functions                                             ////
1207 
////                                                              ////
1208 
////  Description                                                 ////
1209 
////  Logic functions such as multiplexers                        ////
1210 
////                                                              ////
1211 
////                                                              ////
1212 
////  To Do:                                                      ////
1213 
////   -                                                          ////
1214 
////                                                              ////
1215 
////  Author(s):                                                  ////
1216 
////      - Michael Unneback, unneback@opencores.org              ////
1217 
////        ORSoC AB                                              ////
1218 
////                                                              ////
1219 
//////////////////////////////////////////////////////////////////////
1220 
////                                                              ////
1221 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1222 
////                                                              ////
1223 
//// This source file may be used and distributed without         ////
1224 
//// restriction provided that this copyright statement is not    ////
1225 
//// removed from the file and that any derivative work contains  ////
1226 
//// the original copyright notice and the associated disclaimer. ////
1227 
////                                                              ////
1228 
//// This source file is free software; you can redistribute it   ////
1229 
//// and/or modify it under the terms of the GNU Lesser General   ////
1230 
//// Public License as published by the Free Software Foundation; ////
1231 
//// either version 2.1 of the License, or (at your option) any   ////
1232 
//// later version.                                               ////
1233 
////                                                              ////
1234 
//// This source is distributed in the hope that it will be       ////
1235 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1236 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1237 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1238 
//// details.                                                     ////
1239 
////                                                              ////
1240 
//// You should have received a copy of the GNU Lesser General    ////
1241 
//// Public License along with this source; if not, download it   ////
1242 
//// from http://www.opencores.org/lgpl.shtml                     ////
1243 
////                                                              ////
1244 
//////////////////////////////////////////////////////////////////////
1245 40 unneback 
`ifdef MUX_ANDOR
1246 
`define MODULE mux_andor
1247 
module `BASE`MODULE ( a, sel, dout);
1248 
`undef MODULE
1249 36 unneback 
 
1250 
parameter width = 32;
1251 
parameter nr_of_ports = 4;
1252 
 
1253 
input [nr_of_ports*width-1:0] a;
1254 
input [nr_of_ports-1:0] sel;
1255 
output reg [width-1:0] dout;
1256 
 
1257 38 unneback 
integer i,j;
1258 
 
1259 36 unneback 
always @ (a, sel)
1260 
begin
1261 
    dout = a[width-1:0] & {width{sel[0]}};
1262 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1263 
        for (j=0;j<width;j=j+1)
1264 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1265 36 unneback 
end
1266 
 
1267 
endmodule
1268 40 unneback 
`endif
1269 36 unneback 
 
1270 40 unneback 
`ifdef MUX2_ANDOR
1271 
`define MODULE mux2_andor
1272 
module `BASE`MODULE ( a1, a0, sel, dout);
1273 
`undef MODULE
1274 18 unneback 
 
1275 34 unneback 
parameter width = 32;
1276 35 unneback 
localparam nr_of_ports = 2;
1277 34 unneback 
input [width-1:0] a1, a0;
1278 
input [nr_of_ports-1:0] sel;
1279 
output [width-1:0] dout;
1280 
 
1281 40 unneback 
`define MODULE mux_andor
1282 
`BASE`MODULE
1283 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1284 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1285 40 unneback 
`undef MODULE
1286 
 
1287 34 unneback 
endmodule
1288 40 unneback 
`endif
1289 34 unneback 
 
1290 40 unneback 
`ifdef MUX3_ANDOR
1291 
`define MODULE mux3_andor
1292 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1293 
`undef MODULE
1294 34 unneback 
 
1295 
parameter width = 32;
1296 35 unneback 
localparam nr_of_ports = 3;
1297 34 unneback 
input [width-1:0] a2, a1, a0;
1298 
input [nr_of_ports-1:0] sel;
1299 
output [width-1:0] dout;
1300 
 
1301 40 unneback 
`define MODULE mux_andor
1302 
`BASE`MODULE
1303 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1304 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1305 40 unneback 
`undef MODULE
1306 34 unneback 
endmodule
1307 40 unneback 
`endif
1308 34 unneback 
 
1309 40 unneback 
`ifdef MUX4_ANDOR
1310 
`define MODULE mux4_andor
1311 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1312 
`undef MODULE
1313 18 unneback 
 
1314 
parameter width = 32;
1315 35 unneback 
localparam nr_of_ports = 4;
1316 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1317 
input [nr_of_ports-1:0] sel;
1318 22 unneback 
output [width-1:0] dout;
1319 18 unneback 
 
1320 40 unneback 
`define MODULE mux_andor
1321 
`BASE`MODULE
1322 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1323 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1324 40 unneback 
`undef MODULE
1325 18 unneback 
 
1326 
endmodule
1327 40 unneback 
`endif
1328 18 unneback 
 
1329 40 unneback 
`ifdef MUX5_ANDOR
1330 
`define MODULE mux5_andor
1331 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1332 
`undef MODULE
1333 18 unneback 
 
1334 
parameter width = 32;
1335 35 unneback 
localparam nr_of_ports = 5;
1336 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1337 
input [nr_of_ports-1:0] sel;
1338 22 unneback 
output [width-1:0] dout;
1339 18 unneback 
 
1340 40 unneback 
`define MODULE mux_andor
1341 
`BASE`MODULE
1342 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1343 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1344 40 unneback 
`undef MODULE
1345 18 unneback 
 
1346 
endmodule
1347 40 unneback 
`endif
1348 18 unneback 
 
1349 40 unneback 
`ifdef MUX6_ANDOR
1350 
`define MODULE mux6_andor
1351 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1352 
`undef MODULE
1353 18 unneback 
 
1354 
parameter width = 32;
1355 35 unneback 
localparam nr_of_ports = 6;
1356 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1357 
input [nr_of_ports-1:0] sel;
1358 22 unneback 
output [width-1:0] dout;
1359 18 unneback 
 
1360 40 unneback 
`define MODULE mux_andor
1361 
`BASE`MODULE
1362 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1363 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1364 40 unneback 
`undef MODULE
1365 18 unneback 
 
1366 
endmodule
1367 40 unneback 
`endif
1368 43 unneback 
 
1369 
`ifdef PARITY
1370 
 
1371 
`define MODULE parity_generate
1372 
module `BASE`MODULE (data, parity);
1373 
`undef MODULE
1374 
parameter word_size = 32;
1375 
parameter chunk_size = 8;
1376 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1377 
input [word_size-1:0] data;
1378 
output reg [word_size/chunk_size-1:0] parity;
1379 
integer i,j;
1380 
always @ (data)
1381 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1382 
    parity[i] = parity_type;
1383 
    for (j=0;j<chunk_size;j=j+1) begin
1384 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1385 43 unneback 
    end
1386 
end
1387 
endmodule
1388 
 
1389 
`define MODULE parity_check
1390 
module `BASE`MODULE( data, parity, parity_error);
1391 
`undef MODULE
1392 
parameter word_size = 32;
1393 
parameter chunk_size = 8;
1394 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1395 
input [word_size-1:0] data;
1396 
input [word_size/chunk_size-1:0] parity;
1397 
output parity_error;
1398 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1399 43 unneback 
integer i,j;
1400 
always @ (data or parity)
1401 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1402 
    error_flag[i] = parity[i] ^ parity_type;
1403 
    for (j=0;j<chunk_size;j=j+1) begin
1404 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1405 43 unneback 
    end
1406 
end
1407 
assign parity_error = |error_flag;
1408 
endmodule
1409 
 
1410 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1411 
////                                                              ////
1412 
////  IO functions                                                ////
1413 
////                                                              ////
1414 
////  Description                                                 ////
1415 
////  IO functions such as IOB flip-flops                         ////
1416 
////                                                              ////
1417 
////                                                              ////
1418 
////  To Do:                                                      ////
1419 
////   -                                                          ////
1420 
////                                                              ////
1421 
////  Author(s):                                                  ////
1422 
////      - Michael Unneback, unneback@opencores.org              ////
1423 
////        ORSoC AB                                              ////
1424 
////                                                              ////
1425 18 unneback 
//////////////////////////////////////////////////////////////////////
1426 
////                                                              ////
1427 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1428 
////                                                              ////
1429 
//// This source file may be used and distributed without         ////
1430 
//// restriction provided that this copyright statement is not    ////
1431 
//// removed from the file and that any derivative work contains  ////
1432 
//// the original copyright notice and the associated disclaimer. ////
1433 
////                                                              ////
1434 
//// This source file is free software; you can redistribute it   ////
1435 
//// and/or modify it under the terms of the GNU Lesser General   ////
1436 
//// Public License as published by the Free Software Foundation; ////
1437 
//// either version 2.1 of the License, or (at your option) any   ////
1438 
//// later version.                                               ////
1439 
////                                                              ////
1440 
//// This source is distributed in the hope that it will be       ////
1441 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1442 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1443 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1444 
//// details.                                                     ////
1445 
////                                                              ////
1446 
//// You should have received a copy of the GNU Lesser General    ////
1447 
//// Public License along with this source; if not, download it   ////
1448 
//// from http://www.opencores.org/lgpl.shtml                     ////
1449 
////                                                              ////
1450 
//////////////////////////////////////////////////////////////////////
1451 45 unneback 
`timescale 1ns/1ns
1452 44 unneback 
`ifdef O_DFF
1453 
`define MODULE o_dff
1454 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1455 
`undef MODULE
1456 
parameter width = 1;
1457 45 unneback 
parameter reset_value = {width{1'b0}};
1458 
input  [width-1:0]  d_i;
1459 44 unneback 
output [width-1:0] o_pad;
1460 
input clk, rst;
1461 
wire [width-1:0] d_i_int `SYN_KEEP;
1462 45 unneback 
reg  [width-1:0] o_pad_int;
1463 44 unneback 
assign d_i_int = d_i;
1464 
genvar i;
1465 45 unneback 
generate
1466 44 unneback 
for (i=0;i<width;i=i+1) begin
1467 
    always @ (posedge clk or posedge rst)
1468 
    if (rst)
1469 45 unneback 
        o_pad_int[i] <= reset_value[i];
1470 44 unneback 
    else
1471 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1472 
    assign #1 o_pad[i] = o_pad_int[i];
1473 44 unneback 
end
1474 
endgenerate
1475 
endmodule
1476 
`endif
1477 
 
1478 45 unneback 
`timescale 1ns/1ns
1479 44 unneback 
`ifdef IO_DFF_OE
1480 
`define MODULE io_dff_oe
1481 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1482 
`undef MODULE
1483 
parameter width = 1;
1484 
input  [width-1:0] d_o;
1485 
output reg [width-1:0] d_i;
1486 
input oe;
1487 
inout [width-1:0] io_pad;
1488 
input clk, rst;
1489 
wire [width-1:0] oe_d `SYN_KEEP;
1490 
reg [width-1:0] oe_q;
1491 
reg [width-1:0] d_o_q;
1492 
assign oe_d = {width{oe}};
1493 
genvar i;
1494 
generate
1495 
for (i=0;i<width;i=i+1) begin
1496 
    always @ (posedge clk or posedge rst)
1497 
    if (rst)
1498 
        oe_q[i] <= 1'b0;
1499 
    else
1500 
        oe_q[i] <= oe_d[i];
1501 
    always @ (posedge clk or posedge rst)
1502 
    if (rst)
1503 
        d_o_q[i] <= 1'b0;
1504 
    else
1505 
        d_o_q[i] <= d_o[i];
1506 
    always @ (posedge clk or posedge rst)
1507 
    if (rst)
1508 
        d_i[i] <= 1'b0;
1509 
    else
1510 
        d_i[i] <= io_pad[i];
1511 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1512 44 unneback 
end
1513 
endgenerate
1514 
endmodule
1515 
`endif
1516 
`ifdef CNT_BIN
1517 
//////////////////////////////////////////////////////////////////////
1518 
////                                                              ////
1519 6 unneback 
////  Versatile counter                                           ////
1520 
////                                                              ////
1521 
////  Description                                                 ////
1522 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1523 
////  counter                                                     ////
1524 
////                                                              ////
1525 
////  To Do:                                                      ////
1526 
////   - add LFSR with more taps                                  ////
1527 
////                                                              ////
1528 
////  Author(s):                                                  ////
1529 
////      - Michael Unneback, unneback@opencores.org              ////
1530 
////        ORSoC AB                                              ////
1531 
////                                                              ////
1532 
//////////////////////////////////////////////////////////////////////
1533 
////                                                              ////
1534 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1535 
////                                                              ////
1536 
//// This source file may be used and distributed without         ////
1537 
//// restriction provided that this copyright statement is not    ////
1538 
//// removed from the file and that any derivative work contains  ////
1539 
//// the original copyright notice and the associated disclaimer. ////
1540 
////                                                              ////
1541 
//// This source file is free software; you can redistribute it   ////
1542 
//// and/or modify it under the terms of the GNU Lesser General   ////
1543 
//// Public License as published by the Free Software Foundation; ////
1544 
//// either version 2.1 of the License, or (at your option) any   ////
1545 
//// later version.                                               ////
1546 
////                                                              ////
1547 
//// This source is distributed in the hope that it will be       ////
1548 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1549 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1550 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1551 
//// details.                                                     ////
1552 
////                                                              ////
1553 
//// You should have received a copy of the GNU Lesser General    ////
1554 
//// Public License along with this source; if not, download it   ////
1555 
//// from http://www.opencores.org/lgpl.shtml                     ////
1556 
////                                                              ////
1557 
//////////////////////////////////////////////////////////////////////
1558 
 
1559 
// binary counter
1560 22 unneback 
 
1561 40 unneback 
`define MODULE cnt_bin
1562 
module `BASE`MODULE (
1563 
`undef MODULE
1564 
 q, rst, clk);
1565 
 
1566 22 unneback 
   parameter length = 4;
1567 
   output [length:1] q;
1568 
   input rst;
1569 
   input clk;
1570 
 
1571 
   parameter clear_value = 0;
1572 
   parameter set_value = 1;
1573 
   parameter wrap_value = 0;
1574 
   parameter level1_value = 15;
1575 
 
1576 
   reg  [length:1] qi;
1577 
   wire [length:1] q_next;
1578 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1579 
 
1580 
   always @ (posedge clk or posedge rst)
1581 
     if (rst)
1582 
       qi <= {length{1'b0}};
1583 
     else
1584 
       qi <= q_next;
1585 
 
1586 
   assign q = qi;
1587 
 
1588 
endmodule
1589 40 unneback 
`endif
1590 
`ifdef CNT_BIN_CLEAR
1591 22 unneback 
//////////////////////////////////////////////////////////////////////
1592 
////                                                              ////
1593 
////  Versatile counter                                           ////
1594 
////                                                              ////
1595 
////  Description                                                 ////
1596 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1597 
////  counter                                                     ////
1598 
////                                                              ////
1599 
////  To Do:                                                      ////
1600 
////   - add LFSR with more taps                                  ////
1601 
////                                                              ////
1602 
////  Author(s):                                                  ////
1603 
////      - Michael Unneback, unneback@opencores.org              ////
1604 
////        ORSoC AB                                              ////
1605 
////                                                              ////
1606 
//////////////////////////////////////////////////////////////////////
1607 
////                                                              ////
1608 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1609 
////                                                              ////
1610 
//// This source file may be used and distributed without         ////
1611 
//// restriction provided that this copyright statement is not    ////
1612 
//// removed from the file and that any derivative work contains  ////
1613 
//// the original copyright notice and the associated disclaimer. ////
1614 
////                                                              ////
1615 
//// This source file is free software; you can redistribute it   ////
1616 
//// and/or modify it under the terms of the GNU Lesser General   ////
1617 
//// Public License as published by the Free Software Foundation; ////
1618 
//// either version 2.1 of the License, or (at your option) any   ////
1619 
//// later version.                                               ////
1620 
////                                                              ////
1621 
//// This source is distributed in the hope that it will be       ////
1622 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1623 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1624 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1625 
//// details.                                                     ////
1626 
////                                                              ////
1627 
//// You should have received a copy of the GNU Lesser General    ////
1628 
//// Public License along with this source; if not, download it   ////
1629 
//// from http://www.opencores.org/lgpl.shtml                     ////
1630 
////                                                              ////
1631 
//////////////////////////////////////////////////////////////////////
1632 
 
1633 
// binary counter
1634 
 
1635 40 unneback 
`define MODULE cnt_bin_clear
1636 
module `BASE`MODULE (
1637 
`undef MODULE
1638 
 clear, q, rst, clk);
1639 
 
1640 22 unneback 
   parameter length = 4;
1641 
   input clear;
1642 
   output [length:1] q;
1643 
   input rst;
1644 
   input clk;
1645 
 
1646 
   parameter clear_value = 0;
1647 
   parameter set_value = 1;
1648 
   parameter wrap_value = 0;
1649 
   parameter level1_value = 15;
1650 
 
1651 
   reg  [length:1] qi;
1652 
   wire [length:1] q_next;
1653 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1654 
 
1655 
   always @ (posedge clk or posedge rst)
1656 
     if (rst)
1657 
       qi <= {length{1'b0}};
1658 
     else
1659 
       qi <= q_next;
1660 
 
1661 
   assign q = qi;
1662 
 
1663 
endmodule
1664 40 unneback 
`endif
1665 
`ifdef CNT_BIN_CE
1666 22 unneback 
//////////////////////////////////////////////////////////////////////
1667 
////                                                              ////
1668 
////  Versatile counter                                           ////
1669 
////                                                              ////
1670 
////  Description                                                 ////
1671 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1672 
////  counter                                                     ////
1673 
////                                                              ////
1674 
////  To Do:                                                      ////
1675 
////   - add LFSR with more taps                                  ////
1676 
////                                                              ////
1677 
////  Author(s):                                                  ////
1678 
////      - Michael Unneback, unneback@opencores.org              ////
1679 
////        ORSoC AB                                              ////
1680 
////                                                              ////
1681 
//////////////////////////////////////////////////////////////////////
1682 
////                                                              ////
1683 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1684 
////                                                              ////
1685 
//// This source file may be used and distributed without         ////
1686 
//// restriction provided that this copyright statement is not    ////
1687 
//// removed from the file and that any derivative work contains  ////
1688 
//// the original copyright notice and the associated disclaimer. ////
1689 
////                                                              ////
1690 
//// This source file is free software; you can redistribute it   ////
1691 
//// and/or modify it under the terms of the GNU Lesser General   ////
1692 
//// Public License as published by the Free Software Foundation; ////
1693 
//// either version 2.1 of the License, or (at your option) any   ////
1694 
//// later version.                                               ////
1695 
////                                                              ////
1696 
//// This source is distributed in the hope that it will be       ////
1697 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1698 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1699 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1700 
//// details.                                                     ////
1701 
////                                                              ////
1702 
//// You should have received a copy of the GNU Lesser General    ////
1703 
//// Public License along with this source; if not, download it   ////
1704 
//// from http://www.opencores.org/lgpl.shtml                     ////
1705 
////                                                              ////
1706 
//////////////////////////////////////////////////////////////////////
1707 
 
1708 
// binary counter
1709 6 unneback 
 
1710 40 unneback 
`define MODULE cnt_bin_ce
1711 
module `BASE`MODULE (
1712 
`undef MODULE
1713 
 cke, q, rst, clk);
1714 
 
1715 6 unneback 
   parameter length = 4;
1716 
   input cke;
1717 
   output [length:1] q;
1718 
   input rst;
1719 
   input clk;
1720 
 
1721 
   parameter clear_value = 0;
1722 
   parameter set_value = 1;
1723 
   parameter wrap_value = 0;
1724 
   parameter level1_value = 15;
1725 
 
1726 
   reg  [length:1] qi;
1727 
   wire [length:1] q_next;
1728 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1729 
 
1730 
   always @ (posedge clk or posedge rst)
1731 
     if (rst)
1732 
       qi <= {length{1'b0}};
1733 
     else
1734 
     if (cke)
1735 
       qi <= q_next;
1736 
 
1737 
   assign q = qi;
1738 
 
1739 
endmodule
1740 40 unneback 
`endif
1741 
`ifdef CNT_BIN_CE_CLEAR
1742 6 unneback 
//////////////////////////////////////////////////////////////////////
1743 
////                                                              ////
1744 
////  Versatile counter                                           ////
1745 
////                                                              ////
1746 
////  Description                                                 ////
1747 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1748 
////  counter                                                     ////
1749 
////                                                              ////
1750 
////  To Do:                                                      ////
1751 
////   - add LFSR with more taps                                  ////
1752 
////                                                              ////
1753 
////  Author(s):                                                  ////
1754 
////      - Michael Unneback, unneback@opencores.org              ////
1755 
////        ORSoC AB                                              ////
1756 
////                                                              ////
1757 
//////////////////////////////////////////////////////////////////////
1758 
////                                                              ////
1759 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1760 
////                                                              ////
1761 
//// This source file may be used and distributed without         ////
1762 
//// restriction provided that this copyright statement is not    ////
1763 
//// removed from the file and that any derivative work contains  ////
1764 
//// the original copyright notice and the associated disclaimer. ////
1765 
////                                                              ////
1766 
//// This source file is free software; you can redistribute it   ////
1767 
//// and/or modify it under the terms of the GNU Lesser General   ////
1768 
//// Public License as published by the Free Software Foundation; ////
1769 
//// either version 2.1 of the License, or (at your option) any   ////
1770 
//// later version.                                               ////
1771 
////                                                              ////
1772 
//// This source is distributed in the hope that it will be       ////
1773 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1774 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1775 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1776 
//// details.                                                     ////
1777 
////                                                              ////
1778 
//// You should have received a copy of the GNU Lesser General    ////
1779 
//// Public License along with this source; if not, download it   ////
1780 
//// from http://www.opencores.org/lgpl.shtml                     ////
1781 
////                                                              ////
1782 
//////////////////////////////////////////////////////////////////////
1783 
 
1784 
// binary counter
1785 
 
1786 40 unneback 
`define MODULE cnt_bin_ce_clear
1787 
module `BASE`MODULE (
1788 
`undef MODULE
1789 
 clear, cke, q, rst, clk);
1790 
 
1791 6 unneback 
   parameter length = 4;
1792 
   input clear;
1793 
   input cke;
1794 
   output [length:1] q;
1795 
   input rst;
1796 
   input clk;
1797 
 
1798 
   parameter clear_value = 0;
1799 
   parameter set_value = 1;
1800 
   parameter wrap_value = 0;
1801 
   parameter level1_value = 15;
1802 
 
1803 
   reg  [length:1] qi;
1804 
   wire [length:1] q_next;
1805 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1806 
 
1807 
   always @ (posedge clk or posedge rst)
1808 
     if (rst)
1809 
       qi <= {length{1'b0}};
1810 
     else
1811 
     if (cke)
1812 
       qi <= q_next;
1813 
 
1814 
   assign q = qi;
1815 
 
1816 
endmodule
1817 40 unneback 
`endif
1818 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1819 6 unneback 
//////////////////////////////////////////////////////////////////////
1820 
////                                                              ////
1821 
////  Versatile counter                                           ////
1822 
////                                                              ////
1823 
////  Description                                                 ////
1824 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1825 
////  counter                                                     ////
1826 
////                                                              ////
1827 
////  To Do:                                                      ////
1828 
////   - add LFSR with more taps                                  ////
1829 
////                                                              ////
1830 
////  Author(s):                                                  ////
1831 
////      - Michael Unneback, unneback@opencores.org              ////
1832 
////        ORSoC AB                                              ////
1833 
////                                                              ////
1834 
//////////////////////////////////////////////////////////////////////
1835 
////                                                              ////
1836 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1837 
////                                                              ////
1838 
//// This source file may be used and distributed without         ////
1839 
//// restriction provided that this copyright statement is not    ////
1840 
//// removed from the file and that any derivative work contains  ////
1841 
//// the original copyright notice and the associated disclaimer. ////
1842 
////                                                              ////
1843 
//// This source file is free software; you can redistribute it   ////
1844 
//// and/or modify it under the terms of the GNU Lesser General   ////
1845 
//// Public License as published by the Free Software Foundation; ////
1846 
//// either version 2.1 of the License, or (at your option) any   ////
1847 
//// later version.                                               ////
1848 
////                                                              ////
1849 
//// This source is distributed in the hope that it will be       ////
1850 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1851 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1852 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1853 
//// details.                                                     ////
1854 
////                                                              ////
1855 
//// You should have received a copy of the GNU Lesser General    ////
1856 
//// Public License along with this source; if not, download it   ////
1857 
//// from http://www.opencores.org/lgpl.shtml                     ////
1858 
////                                                              ////
1859 
//////////////////////////////////////////////////////////////////////
1860 
 
1861 
// binary counter
1862 29 unneback 
 
1863 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1864 
module `BASE`MODULE (
1865 
`undef MODULE
1866 
 clear, cke, q, level1, level2, rst, clk);
1867 
 
1868 29 unneback 
   parameter length = 4;
1869 
   input clear;
1870 
   input cke;
1871 
   output [length:1] q;
1872 
   output reg level1;
1873 
   output reg level2;
1874 
   input rst;
1875 
   input clk;
1876 
 
1877 
   parameter clear_value = 0;
1878 
   parameter set_value = 1;
1879 30 unneback 
   parameter wrap_value = 15;
1880 
   parameter level1_value = 8;
1881 
   parameter level2_value = 15;
1882 29 unneback 
 
1883 
   wire rew;
1884 30 unneback 
   assign rew = 1'b0;
1885 29 unneback 
   reg  [length:1] qi;
1886 
   wire [length:1] q_next;
1887 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1888 
 
1889 
   always @ (posedge clk or posedge rst)
1890 
     if (rst)
1891 
       qi <= {length{1'b0}};
1892 
     else
1893 
     if (cke)
1894 
       qi <= q_next;
1895 
 
1896 
   assign q = qi;
1897 
 
1898 
 
1899 
    always @ (posedge clk or posedge rst)
1900 
    if (rst)
1901 
        level1 <= 1'b0;
1902 
    else
1903 
    if (cke)
1904 
    if (clear)
1905 
        level1 <= 1'b0;
1906 
    else if (q_next == level1_value)
1907 
        level1 <= 1'b1;
1908 
    else if (qi == level1_value & rew)
1909 
        level1 <= 1'b0;
1910 
 
1911 
    always @ (posedge clk or posedge rst)
1912 
    if (rst)
1913 
        level2 <= 1'b0;
1914 
    else
1915 
    if (cke)
1916 
    if (clear)
1917 
        level2 <= 1'b0;
1918 
    else if (q_next == level2_value)
1919 
        level2 <= 1'b1;
1920 
    else if (qi == level2_value & rew)
1921 
        level2 <= 1'b0;
1922 
endmodule
1923 40 unneback 
`endif
1924 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1925 29 unneback 
//////////////////////////////////////////////////////////////////////
1926 
////                                                              ////
1927 
////  Versatile counter                                           ////
1928 
////                                                              ////
1929 
////  Description                                                 ////
1930 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1931 
////  counter                                                     ////
1932 
////                                                              ////
1933 
////  To Do:                                                      ////
1934 
////   - add LFSR with more taps                                  ////
1935 
////                                                              ////
1936 
////  Author(s):                                                  ////
1937 
////      - Michael Unneback, unneback@opencores.org              ////
1938 
////        ORSoC AB                                              ////
1939 
////                                                              ////
1940 
//////////////////////////////////////////////////////////////////////
1941 
////                                                              ////
1942 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1943 
////                                                              ////
1944 
//// This source file may be used and distributed without         ////
1945 
//// restriction provided that this copyright statement is not    ////
1946 
//// removed from the file and that any derivative work contains  ////
1947 
//// the original copyright notice and the associated disclaimer. ////
1948 
////                                                              ////
1949 
//// This source file is free software; you can redistribute it   ////
1950 
//// and/or modify it under the terms of the GNU Lesser General   ////
1951 
//// Public License as published by the Free Software Foundation; ////
1952 
//// either version 2.1 of the License, or (at your option) any   ////
1953 
//// later version.                                               ////
1954 
////                                                              ////
1955 
//// This source is distributed in the hope that it will be       ////
1956 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1957 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1958 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1959 
//// details.                                                     ////
1960 
////                                                              ////
1961 
//// You should have received a copy of the GNU Lesser General    ////
1962 
//// Public License along with this source; if not, download it   ////
1963 
//// from http://www.opencores.org/lgpl.shtml                     ////
1964 
////                                                              ////
1965 
//////////////////////////////////////////////////////////////////////
1966 
 
1967 
// binary counter
1968 6 unneback 
 
1969 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
1970 
module `BASE`MODULE (
1971 
`undef MODULE
1972 
 clear, set, cke, rew, q, rst, clk);
1973 
 
1974 6 unneback 
   parameter length = 4;
1975 
   input clear;
1976 
   input set;
1977 
   input cke;
1978 
   input rew;
1979 
   output [length:1] q;
1980 
   input rst;
1981 
   input clk;
1982 
 
1983 
   parameter clear_value = 0;
1984 
   parameter set_value = 1;
1985 
   parameter wrap_value = 0;
1986 
   parameter level1_value = 15;
1987 
 
1988 
   reg  [length:1] qi;
1989 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1990 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1991 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1992 
   assign q_next = rew ? q_next_rew : q_next_fw;
1993 
 
1994 
   always @ (posedge clk or posedge rst)
1995 
     if (rst)
1996 
       qi <= {length{1'b0}};
1997 
     else
1998 
     if (cke)
1999 
       qi <= q_next;
2000 
 
2001 
   assign q = qi;
2002 
 
2003 
endmodule
2004 40 unneback 
`endif
2005 
`ifdef CNT_BIN_CE_REW_L1
2006 6 unneback 
//////////////////////////////////////////////////////////////////////
2007 
////                                                              ////
2008 
////  Versatile counter                                           ////
2009 
////                                                              ////
2010 
////  Description                                                 ////
2011 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2012 
////  counter                                                     ////
2013 
////                                                              ////
2014 
////  To Do:                                                      ////
2015 
////   - add LFSR with more taps                                  ////
2016 
////                                                              ////
2017 
////  Author(s):                                                  ////
2018 
////      - Michael Unneback, unneback@opencores.org              ////
2019 
////        ORSoC AB                                              ////
2020 
////                                                              ////
2021 
//////////////////////////////////////////////////////////////////////
2022 
////                                                              ////
2023 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2024 
////                                                              ////
2025 
//// This source file may be used and distributed without         ////
2026 
//// restriction provided that this copyright statement is not    ////
2027 
//// removed from the file and that any derivative work contains  ////
2028 
//// the original copyright notice and the associated disclaimer. ////
2029 
////                                                              ////
2030 
//// This source file is free software; you can redistribute it   ////
2031 
//// and/or modify it under the terms of the GNU Lesser General   ////
2032 
//// Public License as published by the Free Software Foundation; ////
2033 
//// either version 2.1 of the License, or (at your option) any   ////
2034 
//// later version.                                               ////
2035 
////                                                              ////
2036 
//// This source is distributed in the hope that it will be       ////
2037 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2038 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2039 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2040 
//// details.                                                     ////
2041 
////                                                              ////
2042 
//// You should have received a copy of the GNU Lesser General    ////
2043 
//// Public License along with this source; if not, download it   ////
2044 
//// from http://www.opencores.org/lgpl.shtml                     ////
2045 
////                                                              ////
2046 
//////////////////////////////////////////////////////////////////////
2047 
 
2048 
// binary counter
2049 
 
2050 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
2051 
module `BASE`MODULE (
2052 
`undef MODULE
2053 
 cke, rew, level1, rst, clk);
2054 
 
2055 6 unneback 
   parameter length = 4;
2056 
   input cke;
2057 
   input rew;
2058 
   output reg level1;
2059 
   input rst;
2060 
   input clk;
2061 
 
2062 
   parameter clear_value = 0;
2063 
   parameter set_value = 1;
2064 
   parameter wrap_value = 1;
2065 
   parameter level1_value = 15;
2066 
 
2067 29 unneback 
   wire clear;
2068 30 unneback 
   assign clear = 1'b0;
2069 6 unneback 
   reg  [length:1] qi;
2070 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2071 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2072 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2073 
   assign q_next = rew ? q_next_rew : q_next_fw;
2074 
 
2075 
   always @ (posedge clk or posedge rst)
2076 
     if (rst)
2077 
       qi <= {length{1'b0}};
2078 
     else
2079 
     if (cke)
2080 
       qi <= q_next;
2081 
 
2082 
 
2083 
 
2084 
    always @ (posedge clk or posedge rst)
2085 
    if (rst)
2086 
        level1 <= 1'b0;
2087 
    else
2088 
    if (cke)
2089 29 unneback 
    if (clear)
2090 
        level1 <= 1'b0;
2091 
    else if (q_next == level1_value)
2092 6 unneback 
        level1 <= 1'b1;
2093 
    else if (qi == level1_value & rew)
2094 
        level1 <= 1'b0;
2095 
endmodule
2096 40 unneback 
`endif
2097 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2098 6 unneback 
//////////////////////////////////////////////////////////////////////
2099 
////                                                              ////
2100 
////  Versatile counter                                           ////
2101 
////                                                              ////
2102 
////  Description                                                 ////
2103 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2104 
////  counter                                                     ////
2105 
////                                                              ////
2106 
////  To Do:                                                      ////
2107 
////   - add LFSR with more taps                                  ////
2108 
////                                                              ////
2109 
////  Author(s):                                                  ////
2110 
////      - Michael Unneback, unneback@opencores.org              ////
2111 
////        ORSoC AB                                              ////
2112 
////                                                              ////
2113 
//////////////////////////////////////////////////////////////////////
2114 
////                                                              ////
2115 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2116 
////                                                              ////
2117 
//// This source file may be used and distributed without         ////
2118 
//// restriction provided that this copyright statement is not    ////
2119 
//// removed from the file and that any derivative work contains  ////
2120 
//// the original copyright notice and the associated disclaimer. ////
2121 
////                                                              ////
2122 
//// This source file is free software; you can redistribute it   ////
2123 
//// and/or modify it under the terms of the GNU Lesser General   ////
2124 
//// Public License as published by the Free Software Foundation; ////
2125 
//// either version 2.1 of the License, or (at your option) any   ////
2126 
//// later version.                                               ////
2127 
////                                                              ////
2128 
//// This source is distributed in the hope that it will be       ////
2129 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2130 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2131 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2132 
//// details.                                                     ////
2133 
////                                                              ////
2134 
//// You should have received a copy of the GNU Lesser General    ////
2135 
//// Public License along with this source; if not, download it   ////
2136 
//// from http://www.opencores.org/lgpl.shtml                     ////
2137 
////                                                              ////
2138 
//////////////////////////////////////////////////////////////////////
2139 
 
2140 25 unneback 
// binary counter
2141 
 
2142 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2143 
module `BASE`MODULE (
2144 
`undef MODULE
2145 
 cke, rew, zq, level1, rst, clk);
2146 
 
2147 25 unneback 
   parameter length = 4;
2148 
   input cke;
2149 
   input rew;
2150 
   output reg zq;
2151 
   output reg level1;
2152 
   input rst;
2153 
   input clk;
2154 
 
2155 
   parameter clear_value = 0;
2156 
   parameter set_value = 1;
2157 
   parameter wrap_value = 1;
2158 
   parameter level1_value = 15;
2159 
 
2160 29 unneback 
   wire clear;
2161 30 unneback 
   assign clear = 1'b0;
2162 25 unneback 
   reg  [length:1] qi;
2163 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2164 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2165 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2166 
   assign q_next = rew ? q_next_rew : q_next_fw;
2167 
 
2168 
   always @ (posedge clk or posedge rst)
2169 
     if (rst)
2170 
       qi <= {length{1'b0}};
2171 
     else
2172 
     if (cke)
2173 
       qi <= q_next;
2174 
 
2175 
 
2176 
 
2177 
   always @ (posedge clk or posedge rst)
2178 
     if (rst)
2179 
       zq <= 1'b1;
2180 
     else
2181 
     if (cke)
2182 
       zq <= q_next == {length{1'b0}};
2183 
 
2184 
    always @ (posedge clk or posedge rst)
2185 
    if (rst)
2186 
        level1 <= 1'b0;
2187 
    else
2188 
    if (cke)
2189 29 unneback 
    if (clear)
2190 
        level1 <= 1'b0;
2191 
    else if (q_next == level1_value)
2192 25 unneback 
        level1 <= 1'b1;
2193 
    else if (qi == level1_value & rew)
2194 
        level1 <= 1'b0;
2195 
endmodule
2196 40 unneback 
`endif
2197 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2198 25 unneback 
//////////////////////////////////////////////////////////////////////
2199 
////                                                              ////
2200 
////  Versatile counter                                           ////
2201 
////                                                              ////
2202 
////  Description                                                 ////
2203 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2204 
////  counter                                                     ////
2205 
////                                                              ////
2206 
////  To Do:                                                      ////
2207 
////   - add LFSR with more taps                                  ////
2208 
////                                                              ////
2209 
////  Author(s):                                                  ////
2210 
////      - Michael Unneback, unneback@opencores.org              ////
2211 
////        ORSoC AB                                              ////
2212 
////                                                              ////
2213 
//////////////////////////////////////////////////////////////////////
2214 
////                                                              ////
2215 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2216 
////                                                              ////
2217 
//// This source file may be used and distributed without         ////
2218 
//// restriction provided that this copyright statement is not    ////
2219 
//// removed from the file and that any derivative work contains  ////
2220 
//// the original copyright notice and the associated disclaimer. ////
2221 
////                                                              ////
2222 
//// This source file is free software; you can redistribute it   ////
2223 
//// and/or modify it under the terms of the GNU Lesser General   ////
2224 
//// Public License as published by the Free Software Foundation; ////
2225 
//// either version 2.1 of the License, or (at your option) any   ////
2226 
//// later version.                                               ////
2227 
////                                                              ////
2228 
//// This source is distributed in the hope that it will be       ////
2229 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2230 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2231 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2232 
//// details.                                                     ////
2233 
////                                                              ////
2234 
//// You should have received a copy of the GNU Lesser General    ////
2235 
//// Public License along with this source; if not, download it   ////
2236 
//// from http://www.opencores.org/lgpl.shtml                     ////
2237 
////                                                              ////
2238 
//////////////////////////////////////////////////////////////////////
2239 
 
2240 
// binary counter
2241 
 
2242 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2243 
module `BASE`MODULE (
2244 
`undef MODULE
2245 
 cke, rew, q, zq, level1, rst, clk);
2246 
 
2247 25 unneback 
   parameter length = 4;
2248 
   input cke;
2249 
   input rew;
2250 
   output [length:1] q;
2251 
   output reg zq;
2252 
   output reg level1;
2253 
   input rst;
2254 
   input clk;
2255 
 
2256 
   parameter clear_value = 0;
2257 
   parameter set_value = 1;
2258 
   parameter wrap_value = 1;
2259 
   parameter level1_value = 15;
2260 
 
2261 29 unneback 
   wire clear;
2262 30 unneback 
   assign clear = 1'b0;
2263 25 unneback 
   reg  [length:1] qi;
2264 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2265 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2266 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2267 
   assign q_next = rew ? q_next_rew : q_next_fw;
2268 
 
2269 
   always @ (posedge clk or posedge rst)
2270 
     if (rst)
2271 
       qi <= {length{1'b0}};
2272 
     else
2273 
     if (cke)
2274 
       qi <= q_next;
2275 
 
2276 
   assign q = qi;
2277 
 
2278 
 
2279 
   always @ (posedge clk or posedge rst)
2280 
     if (rst)
2281 
       zq <= 1'b1;
2282 
     else
2283 
     if (cke)
2284 
       zq <= q_next == {length{1'b0}};
2285 
 
2286 
    always @ (posedge clk or posedge rst)
2287 
    if (rst)
2288 
        level1 <= 1'b0;
2289 
    else
2290 
    if (cke)
2291 29 unneback 
    if (clear)
2292 
        level1 <= 1'b0;
2293 
    else if (q_next == level1_value)
2294 25 unneback 
        level1 <= 1'b1;
2295 
    else if (qi == level1_value & rew)
2296 
        level1 <= 1'b0;
2297 
endmodule
2298 40 unneback 
`endif
2299 
`ifdef CNT_LFSR_ZQ
2300 25 unneback 
//////////////////////////////////////////////////////////////////////
2301 
////                                                              ////
2302 
////  Versatile counter                                           ////
2303 
////                                                              ////
2304 
////  Description                                                 ////
2305 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2306 
////  counter                                                     ////
2307 
////                                                              ////
2308 
////  To Do:                                                      ////
2309 
////   - add LFSR with more taps                                  ////
2310 
////                                                              ////
2311 
////  Author(s):                                                  ////
2312 
////      - Michael Unneback, unneback@opencores.org              ////
2313 
////        ORSoC AB                                              ////
2314 
////                                                              ////
2315 
//////////////////////////////////////////////////////////////////////
2316 
////                                                              ////
2317 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2318 
////                                                              ////
2319 
//// This source file may be used and distributed without         ////
2320 
//// restriction provided that this copyright statement is not    ////
2321 
//// removed from the file and that any derivative work contains  ////
2322 
//// the original copyright notice and the associated disclaimer. ////
2323 
////                                                              ////
2324 
//// This source file is free software; you can redistribute it   ////
2325 
//// and/or modify it under the terms of the GNU Lesser General   ////
2326 
//// Public License as published by the Free Software Foundation; ////
2327 
//// either version 2.1 of the License, or (at your option) any   ////
2328 
//// later version.                                               ////
2329 
////                                                              ////
2330 
//// This source is distributed in the hope that it will be       ////
2331 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2332 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2333 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2334 
//// details.                                                     ////
2335 
////                                                              ////
2336 
//// You should have received a copy of the GNU Lesser General    ////
2337 
//// Public License along with this source; if not, download it   ////
2338 
//// from http://www.opencores.org/lgpl.shtml                     ////
2339 
////                                                              ////
2340 
//////////////////////////////////////////////////////////////////////
2341 
 
2342 6 unneback 
// LFSR counter
2343 
 
2344 40 unneback 
`define MODULE cnt_lfsr_zq
2345 
module `BASE`MODULE (
2346 
`undef MODULE
2347 
 zq, rst, clk);
2348 
 
2349 6 unneback 
   parameter length = 4;
2350 
   output reg zq;
2351 
   input rst;
2352 
   input clk;
2353 
 
2354 
   parameter clear_value = 0;
2355 
   parameter set_value = 1;
2356 
   parameter wrap_value = 8;
2357 
   parameter level1_value = 15;
2358 
 
2359 
   reg  [length:1] qi;
2360 
   reg lfsr_fb;
2361 
   wire [length:1] q_next;
2362 
   reg [32:1] polynom;
2363 
   integer i;
2364 
 
2365 
   always @ (qi)
2366 
   begin
2367 
        case (length)
2368 
         2: polynom = 32'b11;                               // 0x3
2369 
         3: polynom = 32'b110;                              // 0x6
2370 
         4: polynom = 32'b1100;                             // 0xC
2371 
         5: polynom = 32'b10100;                            // 0x14
2372 
         6: polynom = 32'b110000;                           // 0x30
2373 
         7: polynom = 32'b1100000;                          // 0x60
2374 
         8: polynom = 32'b10111000;                         // 0xb8
2375 
         9: polynom = 32'b100010000;                        // 0x110
2376 
        10: polynom = 32'b1001000000;                       // 0x240
2377 
        11: polynom = 32'b10100000000;                      // 0x500
2378 
        12: polynom = 32'b100000101001;                     // 0x829
2379 
        13: polynom = 32'b1000000001100;                    // 0x100C
2380 
        14: polynom = 32'b10000000010101;                   // 0x2015
2381 
        15: polynom = 32'b110000000000000;                  // 0x6000
2382 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2383 
        17: polynom = 32'b10010000000000000;                // 0x12000
2384 
        18: polynom = 32'b100000010000000000;               // 0x20400
2385 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2386 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2387 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2388 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2389 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2390 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2391 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2392 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2393 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2394 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2395 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2396 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2397 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2398 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2399 
        default: polynom = 32'b0;
2400 
        endcase
2401 
        lfsr_fb = qi[length];
2402 
        for (i=length-1; i>=1; i=i-1) begin
2403 
            if (polynom[i])
2404 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2405 
        end
2406 
    end
2407 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2408 
 
2409 
   always @ (posedge clk or posedge rst)
2410 
     if (rst)
2411 
       qi <= {length{1'b0}};
2412 
     else
2413 
       qi <= q_next;
2414 
 
2415 
 
2416 
 
2417 
   always @ (posedge clk or posedge rst)
2418 
     if (rst)
2419 
       zq <= 1'b1;
2420 
     else
2421 
       zq <= q_next == {length{1'b0}};
2422 
endmodule
2423 40 unneback 
`endif
2424 75 unneback 
`ifdef CNT_LFSR_CE
2425 
//////////////////////////////////////////////////////////////////////
2426 
////                                                              ////
2427 
////  Versatile counter                                           ////
2428 
////                                                              ////
2429 
////  Description                                                 ////
2430 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2431 
////  counter                                                     ////
2432 
////                                                              ////
2433 
////  To Do:                                                      ////
2434 
////   - add LFSR with more taps                                  ////
2435 
////                                                              ////
2436 
////  Author(s):                                                  ////
2437 
////      - Michael Unneback, unneback@opencores.org              ////
2438 
////        ORSoC AB                                              ////
2439 
////                                                              ////
2440 
//////////////////////////////////////////////////////////////////////
2441 
////                                                              ////
2442 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2443 
////                                                              ////
2444 
//// This source file may be used and distributed without         ////
2445 
//// restriction provided that this copyright statement is not    ////
2446 
//// removed from the file and that any derivative work contains  ////
2447 
//// the original copyright notice and the associated disclaimer. ////
2448 
////                                                              ////
2449 
//// This source file is free software; you can redistribute it   ////
2450 
//// and/or modify it under the terms of the GNU Lesser General   ////
2451 
//// Public License as published by the Free Software Foundation; ////
2452 
//// either version 2.1 of the License, or (at your option) any   ////
2453 
//// later version.                                               ////
2454 
////                                                              ////
2455 
//// This source is distributed in the hope that it will be       ////
2456 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2457 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2458 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2459 
//// details.                                                     ////
2460 
////                                                              ////
2461 
//// You should have received a copy of the GNU Lesser General    ////
2462 
//// Public License along with this source; if not, download it   ////
2463 
//// from http://www.opencores.org/lgpl.shtml                     ////
2464 
////                                                              ////
2465 
//////////////////////////////////////////////////////////////////////
2466 
 
2467 
// LFSR counter
2468 
 
2469 
`define MODULE cnt_lfsr_ce
2470 
module `BASE`MODULE (
2471 
`undef MODULE
2472 
 cke, zq, rst, clk);
2473 
 
2474 
   parameter length = 4;
2475 
   input cke;
2476 
   output reg zq;
2477 
   input rst;
2478 
   input clk;
2479 
 
2480 
   parameter clear_value = 0;
2481 
   parameter set_value = 1;
2482 
   parameter wrap_value = 0;
2483 
   parameter level1_value = 15;
2484 
 
2485 
   reg  [length:1] qi;
2486 
   reg lfsr_fb;
2487 
   wire [length:1] q_next;
2488 
   reg [32:1] polynom;
2489 
   integer i;
2490 
 
2491 
   always @ (qi)
2492 
   begin
2493 
        case (length)
2494 
         2: polynom = 32'b11;                               // 0x3
2495 
         3: polynom = 32'b110;                              // 0x6
2496 
         4: polynom = 32'b1100;                             // 0xC
2497 
         5: polynom = 32'b10100;                            // 0x14
2498 
         6: polynom = 32'b110000;                           // 0x30
2499 
         7: polynom = 32'b1100000;                          // 0x60
2500 
         8: polynom = 32'b10111000;                         // 0xb8
2501 
         9: polynom = 32'b100010000;                        // 0x110
2502 
        10: polynom = 32'b1001000000;                       // 0x240
2503 
        11: polynom = 32'b10100000000;                      // 0x500
2504 
        12: polynom = 32'b100000101001;                     // 0x829
2505 
        13: polynom = 32'b1000000001100;                    // 0x100C
2506 
        14: polynom = 32'b10000000010101;                   // 0x2015
2507 
        15: polynom = 32'b110000000000000;                  // 0x6000
2508 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2509 
        17: polynom = 32'b10010000000000000;                // 0x12000
2510 
        18: polynom = 32'b100000010000000000;               // 0x20400
2511 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2512 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2513 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2514 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2515 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2516 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2517 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2518 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2519 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2520 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2521 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2522 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2523 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2524 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2525 
        default: polynom = 32'b0;
2526 
        endcase
2527 
        lfsr_fb = qi[length];
2528 
        for (i=length-1; i>=1; i=i-1) begin
2529 
            if (polynom[i])
2530 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2531 
        end
2532 
    end
2533 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2534 
 
2535 
   always @ (posedge clk or posedge rst)
2536 
     if (rst)
2537 
       qi <= {length{1'b0}};
2538 
     else
2539 
     if (cke)
2540 
       qi <= q_next;
2541 
 
2542 
 
2543 
 
2544 
   always @ (posedge clk or posedge rst)
2545 
     if (rst)
2546 
       zq <= 1'b1;
2547 
     else
2548 
     if (cke)
2549 
       zq <= q_next == {length{1'b0}};
2550 
endmodule
2551 
`endif
2552 40 unneback 
`ifdef CNT_LFSR_CE_ZQ
2553 6 unneback 
//////////////////////////////////////////////////////////////////////
2554 
////                                                              ////
2555 
////  Versatile counter                                           ////
2556 
////                                                              ////
2557 
////  Description                                                 ////
2558 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2559 
////  counter                                                     ////
2560 
////                                                              ////
2561 
////  To Do:                                                      ////
2562 
////   - add LFSR with more taps                                  ////
2563 
////                                                              ////
2564 
////  Author(s):                                                  ////
2565 
////      - Michael Unneback, unneback@opencores.org              ////
2566 
////        ORSoC AB                                              ////
2567 
////                                                              ////
2568 
//////////////////////////////////////////////////////////////////////
2569 
////                                                              ////
2570 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2571 
////                                                              ////
2572 
//// This source file may be used and distributed without         ////
2573 
//// restriction provided that this copyright statement is not    ////
2574 
//// removed from the file and that any derivative work contains  ////
2575 
//// the original copyright notice and the associated disclaimer. ////
2576 
////                                                              ////
2577 
//// This source file is free software; you can redistribute it   ////
2578 
//// and/or modify it under the terms of the GNU Lesser General   ////
2579 
//// Public License as published by the Free Software Foundation; ////
2580 
//// either version 2.1 of the License, or (at your option) any   ////
2581 
//// later version.                                               ////
2582 
////                                                              ////
2583 
//// This source is distributed in the hope that it will be       ////
2584 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2585 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2586 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2587 
//// details.                                                     ////
2588 
////                                                              ////
2589 
//// You should have received a copy of the GNU Lesser General    ////
2590 
//// Public License along with this source; if not, download it   ////
2591 
//// from http://www.opencores.org/lgpl.shtml                     ////
2592 
////                                                              ////
2593 
//////////////////////////////////////////////////////////////////////
2594 
 
2595 
// LFSR counter
2596 
 
2597 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2598 
module `BASE`MODULE (
2599 
`undef MODULE
2600 
 cke, zq, rst, clk);
2601 
 
2602 6 unneback 
   parameter length = 4;
2603 
   input cke;
2604 
   output reg zq;
2605 
   input rst;
2606 
   input clk;
2607 
 
2608 
   parameter clear_value = 0;
2609 
   parameter set_value = 1;
2610 
   parameter wrap_value = 8;
2611 
   parameter level1_value = 15;
2612 
 
2613 
   reg  [length:1] qi;
2614 
   reg lfsr_fb;
2615 
   wire [length:1] q_next;
2616 
   reg [32:1] polynom;
2617 
   integer i;
2618 
 
2619 
   always @ (qi)
2620 
   begin
2621 
        case (length)
2622 
         2: polynom = 32'b11;                               // 0x3
2623 
         3: polynom = 32'b110;                              // 0x6
2624 
         4: polynom = 32'b1100;                             // 0xC
2625 
         5: polynom = 32'b10100;                            // 0x14
2626 
         6: polynom = 32'b110000;                           // 0x30
2627 
         7: polynom = 32'b1100000;                          // 0x60
2628 
         8: polynom = 32'b10111000;                         // 0xb8
2629 
         9: polynom = 32'b100010000;                        // 0x110
2630 
        10: polynom = 32'b1001000000;                       // 0x240
2631 
        11: polynom = 32'b10100000000;                      // 0x500
2632 
        12: polynom = 32'b100000101001;                     // 0x829
2633 
        13: polynom = 32'b1000000001100;                    // 0x100C
2634 
        14: polynom = 32'b10000000010101;                   // 0x2015
2635 
        15: polynom = 32'b110000000000000;                  // 0x6000
2636 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2637 
        17: polynom = 32'b10010000000000000;                // 0x12000
2638 
        18: polynom = 32'b100000010000000000;               // 0x20400
2639 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2640 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2641 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2642 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2643 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2644 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2645 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2646 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2647 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2648 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2649 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2650 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2651 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2652 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2653 
        default: polynom = 32'b0;
2654 
        endcase
2655 
        lfsr_fb = qi[length];
2656 
        for (i=length-1; i>=1; i=i-1) begin
2657 
            if (polynom[i])
2658 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2659 
        end
2660 
    end
2661 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2662 
 
2663 
   always @ (posedge clk or posedge rst)
2664 
     if (rst)
2665 
       qi <= {length{1'b0}};
2666 
     else
2667 
     if (cke)
2668 
       qi <= q_next;
2669 
 
2670 
 
2671 
 
2672 
   always @ (posedge clk or posedge rst)
2673 
     if (rst)
2674 
       zq <= 1'b1;
2675 
     else
2676 
     if (cke)
2677 
       zq <= q_next == {length{1'b0}};
2678 
endmodule
2679 40 unneback 
`endif
2680 
`ifdef CNT_LFSR_CE_Q
2681 6 unneback 
//////////////////////////////////////////////////////////////////////
2682 
////                                                              ////
2683 
////  Versatile counter                                           ////
2684 
////                                                              ////
2685 
////  Description                                                 ////
2686 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2687 
////  counter                                                     ////
2688 
////                                                              ////
2689 
////  To Do:                                                      ////
2690 
////   - add LFSR with more taps                                  ////
2691 
////                                                              ////
2692 
////  Author(s):                                                  ////
2693 
////      - Michael Unneback, unneback@opencores.org              ////
2694 
////        ORSoC AB                                              ////
2695 
////                                                              ////
2696 
//////////////////////////////////////////////////////////////////////
2697 
////                                                              ////
2698 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2699 
////                                                              ////
2700 
//// This source file may be used and distributed without         ////
2701 
//// restriction provided that this copyright statement is not    ////
2702 
//// removed from the file and that any derivative work contains  ////
2703 
//// the original copyright notice and the associated disclaimer. ////
2704 
////                                                              ////
2705 
//// This source file is free software; you can redistribute it   ////
2706 
//// and/or modify it under the terms of the GNU Lesser General   ////
2707 
//// Public License as published by the Free Software Foundation; ////
2708 
//// either version 2.1 of the License, or (at your option) any   ////
2709 
//// later version.                                               ////
2710 
////                                                              ////
2711 
//// This source is distributed in the hope that it will be       ////
2712 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2713 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2714 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2715 
//// details.                                                     ////
2716 
////                                                              ////
2717 
//// You should have received a copy of the GNU Lesser General    ////
2718 
//// Public License along with this source; if not, download it   ////
2719 
//// from http://www.opencores.org/lgpl.shtml                     ////
2720 
////                                                              ////
2721 
//////////////////////////////////////////////////////////////////////
2722 22 unneback 
 
2723 
// LFSR counter
2724 27 unneback 
 
2725 40 unneback 
`define MODULE cnt_lfsr_ce_q
2726 
module `BASE`MODULE (
2727 
`undef MODULE
2728 
 cke, q, rst, clk);
2729 
 
2730 27 unneback 
   parameter length = 4;
2731 
   input cke;
2732 
   output [length:1] q;
2733 
   input rst;
2734 
   input clk;
2735 
 
2736 
   parameter clear_value = 0;
2737 
   parameter set_value = 1;
2738 
   parameter wrap_value = 8;
2739 
   parameter level1_value = 15;
2740 
 
2741 
   reg  [length:1] qi;
2742 
   reg lfsr_fb;
2743 
   wire [length:1] q_next;
2744 
   reg [32:1] polynom;
2745 
   integer i;
2746 
 
2747 
   always @ (qi)
2748 
   begin
2749 
        case (length)
2750 
         2: polynom = 32'b11;                               // 0x3
2751 
         3: polynom = 32'b110;                              // 0x6
2752 
         4: polynom = 32'b1100;                             // 0xC
2753 
         5: polynom = 32'b10100;                            // 0x14
2754 
         6: polynom = 32'b110000;                           // 0x30
2755 
         7: polynom = 32'b1100000;                          // 0x60
2756 
         8: polynom = 32'b10111000;                         // 0xb8
2757 
         9: polynom = 32'b100010000;                        // 0x110
2758 
        10: polynom = 32'b1001000000;                       // 0x240
2759 
        11: polynom = 32'b10100000000;                      // 0x500
2760 
        12: polynom = 32'b100000101001;                     // 0x829
2761 
        13: polynom = 32'b1000000001100;                    // 0x100C
2762 
        14: polynom = 32'b10000000010101;                   // 0x2015
2763 
        15: polynom = 32'b110000000000000;                  // 0x6000
2764 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2765 
        17: polynom = 32'b10010000000000000;                // 0x12000
2766 
        18: polynom = 32'b100000010000000000;               // 0x20400
2767 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2768 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2769 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2770 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2771 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2772 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2773 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2774 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2775 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2776 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2777 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2778 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2779 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2780 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2781 
        default: polynom = 32'b0;
2782 
        endcase
2783 
        lfsr_fb = qi[length];
2784 
        for (i=length-1; i>=1; i=i-1) begin
2785 
            if (polynom[i])
2786 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2787 
        end
2788 
    end
2789 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2790 
 
2791 
   always @ (posedge clk or posedge rst)
2792 
     if (rst)
2793 
       qi <= {length{1'b0}};
2794 
     else
2795 
     if (cke)
2796 
       qi <= q_next;
2797 
 
2798 
   assign q = qi;
2799 
 
2800 
endmodule
2801