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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 91

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 40 unneback
`ifdef ALL
14
 
15
`define GBUF
16
`define SYNC_RST
17
`define PLL
18
 
19
`define MULTS
20
`define MULTS18X18
21
`define MULT
22
`define SHIFT_UNIT_32
23
`define LOGIC_UNIT
24
 
25
`define CNT_SHREG_WRAP
26
`define CNT_SHREG_CE_WRAP
27
`define CNT_SHREG_CE_CLEAR
28
`define CNT_SHREG_CE_CLEAR_WRAP
29
 
30
`define MUX_ANDOR
31
`define MUX2_ANDOR
32
`define MUX3_ANDOR
33
`define MUX4_ANDOR
34
`define MUX5_ANDOR
35
`define MUX6_ANDOR
36 43 unneback
`define PARITY
37 40 unneback
 
38
`define ROM_INIT
39
`define RAM
40
`define RAM_BE
41
`define DPRAM_1R1W
42
`define DPRAM_2R1W
43
`define DPRAM_2R2W
44 75 unneback
`define DPRAM_BE_2R2W
45 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
46
`define FIFO_2R2W_SYNC_SIMPLEX
47
`define FIFO_CMP_ASYNC
48
`define FIFO_1R1W_ASYNC
49
`define FIFO_2R2W_ASYNC
50
`define FIFO_2R2W_ASYNC_SIMPLEX
51 48 unneback
`define REG_FILE
52 40 unneback
 
53
`define DFF
54
`define DFF_ARRAY
55
`define DFF_CE
56
`define DFF_CE_CLEAR
57
`define DF_CE_SET
58
`define SPR
59
`define SRP
60
`define DFF_SR
61
`define LATCH
62
`define SHREG
63
`define SHREG_CE
64
`define DELAY
65
`define DELAY_EMPTYFLAG
66
 
67 75 unneback
`define WB3AVALON_BRIDGE
68 40 unneback
`define WB3WB3_BRIDGE
69
`define WB3_ARBITER_TYPE1
70 83 unneback
`define WB_ADR_INC
71 59 unneback
`define WB_B3_RAM_BE
72 49 unneback
`define WB_B4_RAM_BE
73 48 unneback
`define WB_B4_ROM
74 40 unneback
`define WB_BOOT_ROM
75
`define WB_DPRAM
76
 
77 44 unneback
`define IO_DFF_OE
78
`define O_DFF
79
 
80 40 unneback
`endif
81
 
82
`ifdef PLL
83
`ifndef SYNC_RST
84
`define SYNC_RST
85
`endif
86
`endif
87
 
88
`ifdef SYNC_RST
89
`ifndef GBUF
90
`define GBUF
91
`endif
92
`endif
93
 
94
`ifdef WB_DPRAM
95
`ifndef DPRAM_2R2W
96
`define DPRAM_2R2W
97
`endif
98
`ifndef SPR
99
`define SPR
100
`endif
101
`endif
102
 
103 62 unneback
`ifdef WB_B3_RAM_BE
104 83 unneback
`ifndef WB_ADR_INC
105
`define WB_ADR_INC
106 62 unneback
`endif
107
`ifndef RAM_BE
108
`define RAM_BE
109
`endif
110
`endif
111
 
112 40 unneback
`ifdef WB3_ARBITER_TYPE1
113 42 unneback
`ifndef SPR
114
`define SPR
115
`endif
116 40 unneback
`ifndef MUX_ANDOR
117
`define MUX_ANDOR
118
`endif
119
`endif
120
 
121 76 unneback
`ifdef WB3AVALON_BRIDGE
122
`ifndef WB3WB3_BRIDGE
123
`define WB3WB3_BRIDGE
124
`endif
125
`endif
126
 
127 40 unneback
`ifdef WB3WB3_BRIDGE
128
`ifndef CNT_SHREG_CE_CLEAR
129
`define CNT_SHREG_CE_CLEAR
130
`endif
131
`ifndef DFF
132
`define DFF
133
`endif
134
`ifndef DFF_CE
135
`define DFF_CE
136
`endif
137
`ifndef CNT_SHREG_CE_CLEAR
138
`define CNT_SHREG_CE_CLEAR
139
`endif
140
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
141
`define FIFO_2R2W_ASYNC_SIMPLEX
142
`endif
143
`endif
144
 
145
`ifdef MULTS18X18
146
`ifndef MULTS
147
`define MULTS
148
`endif
149
`endif
150
 
151
`ifdef SHIFT_UNIT_32
152
`ifndef MULTS
153
`define MULTS
154
`endif
155
`endif
156
 
157
`ifdef MUX2_ANDOR
158
`ifndef MUX_ANDOR
159
`define MUX_ANDOR
160
`endif
161
`endif
162
 
163
`ifdef MUX3_ANDOR
164
`ifndef MUX_ANDOR
165
`define MUX_ANDOR
166
`endif
167
`endif
168
 
169
`ifdef MUX4_ANDOR
170
`ifndef MUX_ANDOR
171
`define MUX_ANDOR
172
`endif
173
`endif
174
 
175
`ifdef MUX5_ANDOR
176
`ifndef MUX_ANDOR
177
`define MUX_ANDOR
178
`endif
179
`endif
180
 
181
`ifdef MUX6_ANDOR
182
`ifndef MUX_ANDOR
183
`define MUX_ANDOR
184
`endif
185
`endif
186
 
187
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
188
`ifndef CNT_BIN_CE
189
`define CNT_BIN_CE
190
`endif
191
`ifndef DPRAM_1R1W
192
`define DPRAM_1R1W
193
`endif
194
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
195
`define CNT_BIN_CE_REW_Q_ZQ_L1
196
`endif
197
`endif
198
 
199
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
200
`ifndef CNT_LFSR_CE
201
`define CNT_LFSR_CE
202
`endif
203
`ifndef DPRAM_2R2W
204
`define DPRAM_2R2W
205
`endif
206
`ifndef CNT_BIN_CE_REW_ZQ_L1
207
`define CNT_BIN_CE_REW_ZQ_L1
208
`endif
209
`endif
210
 
211
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
212
`ifndef CNT_GRAY_CE_BIN
213
`define CNT_GRAY_CE_BIN
214
`endif
215
`ifndef DPRAM_2R2W
216
`define DPRAM_2R2W
217
`endif
218
`ifndef FIFO_CMP_ASYNC
219
`define FIFO_CMP_ASYNC
220
`endif
221
`endif
222
 
223
`ifdef FIFO_2R2W_ASYNC
224
`ifndef FIFO_1R1W_ASYNC
225
`define FIFO_1R1W_ASYNC
226
`endif
227
`endif
228
 
229
`ifdef FIFO_1R1W_ASYNC
230
`ifndef CNT_GRAY_CE_BIN
231
`define CNT_GRAY_CE_BIN
232
`endif
233
`ifndef DPRAM_1R1W
234
`define DPRAM_1R1W
235
`endif
236
`ifndef FIFO_CMP_ASYNC
237
`define FIFO_CMP_ASYNC
238
`endif
239
`endif
240
 
241
`ifdef FIFO_CMP_ASYNC
242
`ifndef DFF_SR
243
`define DFF_SR
244
`endif
245
`ifndef DFF
246
`define DFF
247
`endif
248
`endif
249 48 unneback
 
250
`ifdef REG_FILE
251
`ifndef DPRAM_1R1W
252
`define DPRAM_1R1W
253
`endif
254
`endif
255 62 unneback
//////////////////////////////////////////////////////////////////////
256 6 unneback
////                                                              ////
257
////  Versatile library, clock and reset                          ////
258
////                                                              ////
259
////  Description                                                 ////
260
////  Logic related to clock and reset                            ////
261
////                                                              ////
262
////                                                              ////
263
////  To Do:                                                      ////
264
////   - add more different registers                             ////
265
////                                                              ////
266
////  Author(s):                                                  ////
267
////      - Michael Unneback, unneback@opencores.org              ////
268
////        ORSoC AB                                              ////
269
////                                                              ////
270
//////////////////////////////////////////////////////////////////////
271
////                                                              ////
272
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
273
////                                                              ////
274
//// This source file may be used and distributed without         ////
275
//// restriction provided that this copyright statement is not    ////
276
//// removed from the file and that any derivative work contains  ////
277
//// the original copyright notice and the associated disclaimer. ////
278
////                                                              ////
279
//// This source file is free software; you can redistribute it   ////
280
//// and/or modify it under the terms of the GNU Lesser General   ////
281
//// Public License as published by the Free Software Foundation; ////
282
//// either version 2.1 of the License, or (at your option) any   ////
283
//// later version.                                               ////
284
////                                                              ////
285
//// This source is distributed in the hope that it will be       ////
286
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
287
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
288
//// PURPOSE.  See the GNU Lesser General Public License for more ////
289
//// details.                                                     ////
290
////                                                              ////
291
//// You should have received a copy of the GNU Lesser General    ////
292
//// Public License along with this source; if not, download it   ////
293
//// from http://www.opencores.org/lgpl.shtml                     ////
294
////                                                              ////
295
//////////////////////////////////////////////////////////////////////
296
 
297 48 unneback
`ifdef ACTEL
298
`ifdef GBUF
299
`timescale 1 ns/100 ps
300 6 unneback
// Global buffer
301
// usage:
302
// use to enable global buffers for high fan out signals such as clock and reset
303
// Version: 8.4 8.4.0.33
304
module gbuf(GL,CLK);
305
output GL;
306
input  CLK;
307
 
308
    wire GND;
309
 
310
    GND GND_1_net(.Y(GND));
311
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
312
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
313
 
314
endmodule
315
`timescale 1 ns/1 ns
316 40 unneback
`define MODULE gbuf
317
module `BASE`MODULE ( i, o);
318
`undef MODULE
319 6 unneback
input i;
320
output o;
321
`ifdef SIM_GBUF
322
assign o=i;
323
`else
324
gbuf gbuf_i0 ( .CLK(i), .GL(o));
325
`endif
326
endmodule
327 40 unneback
`endif
328 33 unneback
 
329 6 unneback
`else
330 33 unneback
 
331 40 unneback
`ifdef ALTERA
332
`ifdef GBUF
333 21 unneback
//altera
334 40 unneback
`define MODULE gbuf
335
module `BASE`MODULE ( i, o);
336
`undef MODULE
337 33 unneback
input i;
338
output o;
339
assign o = i;
340
endmodule
341 40 unneback
`endif
342 33 unneback
 
343 6 unneback
`else
344
 
345 40 unneback
`ifdef GBUF
346 6 unneback
`timescale 1 ns/100 ps
347 40 unneback
`define MODULE
348
module `BASE`MODULE ( i, o);
349
`undef MODULE
350 6 unneback
input i;
351
output o;
352
assign o = i;
353
endmodule
354 40 unneback
`endif
355 6 unneback
`endif // ALTERA
356
`endif //ACTEL
357
 
358 40 unneback
`ifdef SYNC_RST
359 6 unneback
// sync reset
360 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
361 6 unneback
// output active high global reset sync with two DFFs 
362
`timescale 1 ns/100 ps
363 40 unneback
`define MODULE sync_rst
364
module `BASE`MODULE ( rst_n_i, rst_o, clk);
365
`undef MODULE
366 6 unneback
input rst_n_i, clk;
367
output rst_o;
368 18 unneback
reg [1:0] tmp;
369 6 unneback
always @ (posedge clk or negedge rst_n_i)
370
if (!rst_n_i)
371 17 unneback
        tmp <= 2'b11;
372 6 unneback
else
373 33 unneback
        tmp <= {1'b0,tmp[1]};
374 40 unneback
`define MODULE gbuf
375
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
376
`undef MODULE
377 6 unneback
endmodule
378 40 unneback
`endif
379 6 unneback
 
380 40 unneback
`ifdef PLL
381 6 unneback
// vl_pll
382
`ifdef ACTEL
383 32 unneback
///////////////////////////////////////////////////////////////////////////////
384 17 unneback
`timescale 1 ps/1 ps
385 40 unneback
`define MODULE pll
386
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
387
`undef MODULE
388 6 unneback
parameter index = 0;
389
parameter number_of_clk = 1;
390 17 unneback
parameter period_time_0 = 20000;
391
parameter period_time_1 = 20000;
392
parameter period_time_2 = 20000;
393
parameter lock_delay = 2000000;
394 6 unneback
input clk_i, rst_n_i;
395
output lock;
396
output reg [0:number_of_clk-1] clk_o;
397
output [0:number_of_clk-1] rst_o;
398
 
399
`ifdef SIM_PLL
400
 
401
always
402
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
403
 
404
generate if (number_of_clk > 1)
405
always
406
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
407
endgenerate
408
 
409
generate if (number_of_clk > 2)
410
always
411
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
412
endgenerate
413
 
414
genvar i;
415
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
416
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
417
end
418
endgenerate
419
 
420
assign #lock_delay lock = rst_n_i;
421
 
422
endmodule
423
`else
424
generate if (number_of_clk==1 & index==0) begin
425
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
426
end
427
endgenerate // index==0
428
generate if (number_of_clk==1 & index==1) begin
429
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
430
end
431
endgenerate // index==1
432
generate if (number_of_clk==1 & index==2) begin
433
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
434
end
435
endgenerate // index==2
436
generate if (number_of_clk==1 & index==3) begin
437
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
438
end
439
endgenerate // index==0
440
 
441
generate if (number_of_clk==2 & index==0) begin
442
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
443
end
444
endgenerate // index==0
445
generate if (number_of_clk==2 & index==1) begin
446
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
447
end
448
endgenerate // index==1
449
generate if (number_of_clk==2 & index==2) begin
450
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
451
end
452
endgenerate // index==2
453
generate if (number_of_clk==2 & index==3) begin
454
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
455
end
456
endgenerate // index==0
457
 
458
generate if (number_of_clk==3 & index==0) begin
459
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
460
end
461
endgenerate // index==0
462
generate if (number_of_clk==3 & index==1) begin
463
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
464
end
465
endgenerate // index==1
466
generate if (number_of_clk==3 & index==2) begin
467
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
468
end
469
endgenerate // index==2
470
generate if (number_of_clk==3 & index==3) begin
471
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
472
end
473
endgenerate // index==0
474
 
475
genvar i;
476
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
477 40 unneback
`define MODULE sync_rst
478
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
479
`undef MODULE
480 6 unneback
end
481
endgenerate
482
endmodule
483
`endif
484 32 unneback
///////////////////////////////////////////////////////////////////////////////
485 6 unneback
 
486
`else
487
 
488 32 unneback
///////////////////////////////////////////////////////////////////////////////
489 6 unneback
`ifdef ALTERA
490
 
491 32 unneback
`timescale 1 ps/1 ps
492 40 unneback
`define MODULE pll
493
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
494
`undef MODULE
495 32 unneback
parameter index = 0;
496
parameter number_of_clk = 1;
497
parameter period_time_0 = 20000;
498
parameter period_time_1 = 20000;
499
parameter period_time_2 = 20000;
500
parameter period_time_3 = 20000;
501
parameter period_time_4 = 20000;
502
parameter lock_delay = 2000000;
503
input clk_i, rst_n_i;
504
output lock;
505
output reg [0:number_of_clk-1] clk_o;
506
output [0:number_of_clk-1] rst_o;
507
 
508
`ifdef SIM_PLL
509
 
510
always
511
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
512
 
513
generate if (number_of_clk > 1)
514
always
515
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
516
endgenerate
517
 
518
generate if (number_of_clk > 2)
519
always
520
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
521
endgenerate
522
 
523 33 unneback
generate if (number_of_clk > 3)
524 32 unneback
always
525
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
526
endgenerate
527
 
528 33 unneback
generate if (number_of_clk > 4)
529 32 unneback
always
530
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
531
endgenerate
532
 
533
genvar i;
534
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
535
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
536
end
537
endgenerate
538
 
539 33 unneback
//assign #lock_delay lock = rst_n_i;
540
assign lock = rst_n_i;
541 32 unneback
 
542
endmodule
543 6 unneback
`else
544
 
545 33 unneback
`ifdef VL_PLL0
546
`ifdef VL_PLL0_CLK1
547
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
548
`endif
549
`ifdef VL_PLL0_CLK2
550
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
551
`endif
552
`ifdef VL_PLL0_CLK3
553
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
554
`endif
555
`ifdef VL_PLL0_CLK4
556
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
557
`endif
558
`ifdef VL_PLL0_CLK5
559
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
560
`endif
561
`endif
562 32 unneback
 
563 33 unneback
`ifdef VL_PLL1
564
`ifdef VL_PLL1_CLK1
565
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
566
`endif
567
`ifdef VL_PLL1_CLK2
568
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
569
`endif
570
`ifdef VL_PLL1_CLK3
571
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
572
`endif
573
`ifdef VL_PLL1_CLK4
574
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
575
`endif
576
`ifdef VL_PLL1_CLK5
577
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
578
`endif
579
`endif
580 32 unneback
 
581 33 unneback
`ifdef VL_PLL2
582
`ifdef VL_PLL2_CLK1
583
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
584
`endif
585
`ifdef VL_PLL2_CLK2
586
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
587
`endif
588
`ifdef VL_PLL2_CLK3
589
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
590
`endif
591
`ifdef VL_PLL2_CLK4
592
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
593
`endif
594
`ifdef VL_PLL2_CLK5
595
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
596
`endif
597
`endif
598 32 unneback
 
599 33 unneback
`ifdef VL_PLL3
600
`ifdef VL_PLL3_CLK1
601
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
602
`endif
603
`ifdef VL_PLL3_CLK2
604
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
605
`endif
606
`ifdef VL_PLL3_CLK3
607
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
608
`endif
609
`ifdef VL_PLL3_CLK4
610
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
611
`endif
612
`ifdef VL_PLL3_CLK5
613
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
614
`endif
615
`endif
616 32 unneback
 
617
genvar i;
618
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
619 40 unneback
`define MODULE sync_rst
620
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
621
`undef MODULE
622 32 unneback
end
623
endgenerate
624
endmodule
625
`endif
626
///////////////////////////////////////////////////////////////////////////////
627
 
628
`else
629
 
630 6 unneback
// generic PLL
631 17 unneback
`timescale 1 ps/1 ps
632 40 unneback
`define MODULE pll
633
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
634
`undef MODULE
635 6 unneback
parameter index = 0;
636
parameter number_of_clk = 1;
637 17 unneback
parameter period_time_0 = 20000;
638
parameter period_time_1 = 20000;
639
parameter period_time_2 = 20000;
640 6 unneback
parameter lock_delay = 2000;
641
input clk_i, rst_n_i;
642
output lock;
643
output reg [0:number_of_clk-1] clk_o;
644
output [0:number_of_clk-1] rst_o;
645
 
646
always
647
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
648
 
649
generate if (number_of_clk > 1)
650
always
651
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
652
endgenerate
653
 
654
generate if (number_of_clk > 2)
655
always
656
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
657
endgenerate
658
 
659
genvar i;
660
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
661 40 unneback
`define MODULE sync_rst
662
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
663
`undef MODULE
664 6 unneback
end
665
endgenerate
666
 
667
assign #lock_delay lock = rst_n_i;
668
 
669
endmodule
670
 
671
`endif //altera
672 17 unneback
`endif //actel
673 40 unneback
`undef MODULE
674
`endif//////////////////////////////////////////////////////////////////////
675 6 unneback
////                                                              ////
676
////  Versatile library, registers                                ////
677
////                                                              ////
678
////  Description                                                 ////
679
////  Different type of registers                                 ////
680
////                                                              ////
681
////                                                              ////
682
////  To Do:                                                      ////
683
////   - add more different registers                             ////
684
////                                                              ////
685
////  Author(s):                                                  ////
686
////      - Michael Unneback, unneback@opencores.org              ////
687
////        ORSoC AB                                              ////
688
////                                                              ////
689
//////////////////////////////////////////////////////////////////////
690
////                                                              ////
691
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
692
////                                                              ////
693
//// This source file may be used and distributed without         ////
694
//// restriction provided that this copyright statement is not    ////
695
//// removed from the file and that any derivative work contains  ////
696
//// the original copyright notice and the associated disclaimer. ////
697
////                                                              ////
698
//// This source file is free software; you can redistribute it   ////
699
//// and/or modify it under the terms of the GNU Lesser General   ////
700
//// Public License as published by the Free Software Foundation; ////
701
//// either version 2.1 of the License, or (at your option) any   ////
702
//// later version.                                               ////
703
////                                                              ////
704
//// This source is distributed in the hope that it will be       ////
705
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
706
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
707
//// PURPOSE.  See the GNU Lesser General Public License for more ////
708
//// details.                                                     ////
709
////                                                              ////
710
//// You should have received a copy of the GNU Lesser General    ////
711
//// Public License along with this source; if not, download it   ////
712
//// from http://www.opencores.org/lgpl.shtml                     ////
713
////                                                              ////
714
//////////////////////////////////////////////////////////////////////
715
 
716 40 unneback
`ifdef DFF
717
`define MODULE dff
718
module `BASE`MODULE ( d, q, clk, rst);
719
`undef MODULE
720 6 unneback
        parameter width = 1;
721
        parameter reset_value = 0;
722
 
723
        input [width-1:0] d;
724
        input clk, rst;
725
        output reg [width-1:0] q;
726
 
727
        always @ (posedge clk or posedge rst)
728
        if (rst)
729
                q <= reset_value;
730
        else
731
                q <= d;
732
 
733
endmodule
734 40 unneback
`endif
735 6 unneback
 
736 40 unneback
`ifdef DFF_ARRAY
737
`define MODULE dff_array
738
module `BASE`MODULE ( d, q, clk, rst);
739
`undef MODULE
740 6 unneback
 
741
        parameter width = 1;
742
        parameter depth = 2;
743
        parameter reset_value = 1'b0;
744
 
745
        input [width-1:0] d;
746
        input clk, rst;
747
        output [width-1:0] q;
748
        reg  [0:depth-1] q_tmp [width-1:0];
749
        integer i;
750
        always @ (posedge clk or posedge rst)
751
        if (rst) begin
752
            for (i=0;i<depth;i=i+1)
753
                q_tmp[i] <= {width{reset_value}};
754
        end else begin
755
            q_tmp[0] <= d;
756
            for (i=1;i<depth;i=i+1)
757
                q_tmp[i] <= q_tmp[i-1];
758
        end
759
 
760
    assign q = q_tmp[depth-1];
761
 
762
endmodule
763 40 unneback
`endif
764 6 unneback
 
765 40 unneback
`ifdef DFF_CE
766
`define MODULE dff_ce
767
module `BASE`MODULE ( d, ce, q, clk, rst);
768
`undef MODULE
769 6 unneback
 
770
        parameter width = 1;
771
        parameter reset_value = 0;
772
 
773
        input [width-1:0] d;
774
        input ce, clk, rst;
775
        output reg [width-1:0] q;
776
 
777
        always @ (posedge clk or posedge rst)
778
        if (rst)
779
                q <= reset_value;
780
        else
781
                if (ce)
782
                        q <= d;
783
 
784
endmodule
785 40 unneback
`endif
786 6 unneback
 
787 40 unneback
`ifdef DFF_CE_CLEAR
788
`define MODULE dff_ce_clear
789
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
790
`undef MODULE
791 8 unneback
 
792
        parameter width = 1;
793
        parameter reset_value = 0;
794
 
795
        input [width-1:0] d;
796 10 unneback
        input ce, clear, clk, rst;
797 8 unneback
        output reg [width-1:0] q;
798
 
799
        always @ (posedge clk or posedge rst)
800
        if (rst)
801
            q <= reset_value;
802
        else
803
            if (ce)
804
                if (clear)
805
                    q <= {width{1'b0}};
806
                else
807
                    q <= d;
808
 
809
endmodule
810 40 unneback
`endif
811 8 unneback
 
812 40 unneback
`ifdef DF_CE_SET
813
`define MODULE dff_ce_set
814
module `BASE`MODULE ( d, ce, set, q, clk, rst);
815
`undef MODULE
816 24 unneback
 
817
        parameter width = 1;
818
        parameter reset_value = 0;
819
 
820
        input [width-1:0] d;
821
        input ce, set, clk, rst;
822
        output reg [width-1:0] q;
823
 
824
        always @ (posedge clk or posedge rst)
825
        if (rst)
826
            q <= reset_value;
827
        else
828
            if (ce)
829
                if (set)
830
                    q <= {width{1'b1}};
831
                else
832
                    q <= d;
833
 
834
endmodule
835 40 unneback
`endif
836 24 unneback
 
837 40 unneback
`ifdef SPR
838
`define MODULE spr
839
module `BASE`MODULE ( sp, r, q, clk, rst);
840
`undef MODULE
841
 
842 64 unneback
        //parameter width = 1;
843
        parameter reset_value = 1'b0;
844 29 unneback
 
845
        input sp, r;
846
        output reg q;
847
        input clk, rst;
848
 
849
        always @ (posedge clk or posedge rst)
850
        if (rst)
851
            q <= reset_value;
852
        else
853
            if (sp)
854
                q <= 1'b1;
855
            else if (r)
856
                q <= 1'b0;
857
 
858
endmodule
859 40 unneback
`endif
860 29 unneback
 
861 40 unneback
`ifdef SRP
862
`define MODULE srp
863
module `BASE`MODULE ( s, rp, q, clk, rst);
864
`undef MODULE
865
 
866 29 unneback
        parameter width = 1;
867
        parameter reset_value = 0;
868
 
869
        input s, rp;
870
        output reg q;
871
        input clk, rst;
872
 
873
        always @ (posedge clk or posedge rst)
874
        if (rst)
875
            q <= reset_value;
876
        else
877
            if (rp)
878
                q <= 1'b0;
879
            else if (s)
880
                q <= 1'b1;
881
 
882
endmodule
883 40 unneback
`endif
884 29 unneback
 
885 40 unneback
`ifdef ALTERA
886 29 unneback
 
887 40 unneback
`ifdef DFF_SR
888 6 unneback
// megafunction wizard: %LPM_FF%
889
// GENERATION: STANDARD
890
// VERSION: WM1.0
891
// MODULE: lpm_ff 
892
 
893
// ============================================================
894
// File Name: dff_sr.v
895
// Megafunction Name(s):
896
//                      lpm_ff
897
//
898
// Simulation Library Files(s):
899
//                      lpm
900
// ============================================================
901
// ************************************************************
902
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
903
//
904
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
905
// ************************************************************
906
 
907
 
908
//Copyright (C) 1991-2010 Altera Corporation
909
//Your use of Altera Corporation's design tools, logic functions 
910
//and other software and tools, and its AMPP partner logic 
911
//functions, and any output files from any of the foregoing 
912
//(including device programming or simulation files), and any 
913
//associated documentation or information are expressly subject 
914
//to the terms and conditions of the Altera Program License 
915
//Subscription Agreement, Altera MegaCore Function License 
916
//Agreement, or other applicable license agreement, including, 
917
//without limitation, that your use is for the sole purpose of 
918
//programming logic devices manufactured by Altera and sold by 
919
//Altera or its authorized distributors.  Please refer to the 
920
//applicable agreement for further details.
921
 
922
 
923
// synopsys translate_off
924
`timescale 1 ps / 1 ps
925
// synopsys translate_on
926 40 unneback
`define MODULE dff_sr
927
module `BASE`MODULE (
928
`undef MODULE
929
 
930 6 unneback
        aclr,
931
        aset,
932
        clock,
933
        data,
934
        q);
935
 
936
        input     aclr;
937
        input     aset;
938
        input     clock;
939
        input     data;
940
        output    q;
941
 
942
        wire [0:0] sub_wire0;
943
        wire [0:0] sub_wire1 = sub_wire0[0:0];
944
        wire  q = sub_wire1;
945
        wire  sub_wire2 = data;
946
        wire  sub_wire3 = sub_wire2;
947
 
948
        lpm_ff  lpm_ff_component (
949
                                .aclr (aclr),
950
                                .clock (clock),
951
                                .data (sub_wire3),
952
                                .aset (aset),
953
                                .q (sub_wire0)
954
                                // synopsys translate_off
955
                                ,
956
                                .aload (),
957
                                .enable (),
958
                                .sclr (),
959
                                .sload (),
960
                                .sset ()
961
                                // synopsys translate_on
962
                                );
963
        defparam
964
                lpm_ff_component.lpm_fftype = "DFF",
965
                lpm_ff_component.lpm_type = "LPM_FF",
966
                lpm_ff_component.lpm_width = 1;
967
 
968
 
969
endmodule
970
 
971
// ============================================================
972
// CNX file retrieval info
973
// ============================================================
974
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
975
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
976
// Retrieval info: PRIVATE: ASET NUMERIC "1"
977
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
978
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
979
// Retrieval info: PRIVATE: DFF NUMERIC "1"
980
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
981
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
982
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
983
// Retrieval info: PRIVATE: SSET NUMERIC "0"
984
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
985
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
986
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
987
// Retrieval info: PRIVATE: nBit NUMERIC "1"
988
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
989
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
990
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
991
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
992
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
993
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
994
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
995
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
996
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
997
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
998
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
999
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1000
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1001
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1002
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1003
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1004
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1005
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1006
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1007
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1008
// Retrieval info: LIB_FILE: lpm
1009 40 unneback
`endif
1010 6 unneback
 
1011
`else
1012
 
1013 40 unneback
`ifdef DFF_SR
1014
`define MODULE dff_sr
1015
module `BASE`MODULE ( aclr, aset, clock, data, q);
1016
`undef MODULE
1017 6 unneback
 
1018
    input         aclr;
1019
    input         aset;
1020
    input         clock;
1021
    input         data;
1022
    output reg    q;
1023
 
1024
   always @ (posedge clock or posedge aclr or posedge aset)
1025
     if (aclr)
1026
       q <= 1'b0;
1027
     else if (aset)
1028
       q <= 1'b1;
1029
     else
1030
       q <= data;
1031
 
1032
endmodule
1033 40 unneback
`endif
1034 6 unneback
 
1035
`endif
1036
 
1037
// LATCH
1038
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1039
`ifdef ALTERA
1040 40 unneback
 
1041
`ifdef LATCH
1042
`define MODULE latch
1043
module `BASE`MODULE ( d, le, q, clk);
1044
`undef MODULE
1045 6 unneback
input d, le;
1046
output q;
1047
input clk;
1048
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1049
endmodule
1050 40 unneback
`endif
1051
 
1052 6 unneback
`else
1053 40 unneback
 
1054
`ifdef LATCH
1055
`define MODULE latch
1056
module `BASE`MODULE ( d, le, q, clk);
1057
`undef MODULE
1058 6 unneback
input d, le;
1059 48 unneback
input clk;
1060
always @ (le or d)
1061 60 unneback
if (le)
1062 48 unneback
    d <= q;
1063 6 unneback
endmodule
1064 15 unneback
`endif
1065
 
1066 40 unneback
`endif
1067
 
1068
`ifdef SHREG
1069
`define MODULE shreg
1070
module `BASE`MODULE ( d, q, clk, rst);
1071
`undef MODULE
1072
 
1073 17 unneback
parameter depth = 10;
1074
input d;
1075
output q;
1076
input clk, rst;
1077
 
1078
reg [1:depth] dffs;
1079
 
1080
always @ (posedge clk or posedge rst)
1081
if (rst)
1082
    dffs <= {depth{1'b0}};
1083
else
1084
    dffs <= {d,dffs[1:depth-1]};
1085
assign q = dffs[depth];
1086
endmodule
1087 40 unneback
`endif
1088 17 unneback
 
1089 40 unneback
`ifdef SHREG_CE
1090
`define MODULE shreg_ce
1091
module `BASE`MODULE ( d, ce, q, clk, rst);
1092
`undef MODULE
1093 17 unneback
parameter depth = 10;
1094
input d, ce;
1095
output q;
1096
input clk, rst;
1097
 
1098
reg [1:depth] dffs;
1099
 
1100
always @ (posedge clk or posedge rst)
1101
if (rst)
1102
    dffs <= {depth{1'b0}};
1103
else
1104
    if (ce)
1105
        dffs <= {d,dffs[1:depth-1]};
1106
assign q = dffs[depth];
1107
endmodule
1108 40 unneback
`endif
1109 17 unneback
 
1110 40 unneback
`ifdef DELAY
1111
`define MODULE delay
1112
module `BASE`MODULE ( d, q, clk, rst);
1113
`undef MODULE
1114 15 unneback
parameter depth = 10;
1115
input d;
1116
output q;
1117
input clk, rst;
1118
 
1119
reg [1:depth] dffs;
1120
 
1121
always @ (posedge clk or posedge rst)
1122
if (rst)
1123
    dffs <= {depth{1'b0}};
1124
else
1125
    dffs <= {d,dffs[1:depth-1]};
1126
assign q = dffs[depth];
1127 17 unneback
endmodule
1128 40 unneback
`endif
1129 17 unneback
 
1130 40 unneback
`ifdef DELAY_EMPTYFLAG
1131
`define MODULE delay_emptyflag
1132 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1133 40 unneback
`undef MODULE
1134 17 unneback
parameter depth = 10;
1135
input d;
1136
output q, emptyflag;
1137
input clk, rst;
1138
 
1139
reg [1:depth] dffs;
1140
 
1141
always @ (posedge clk or posedge rst)
1142
if (rst)
1143
    dffs <= {depth{1'b0}};
1144
else
1145
    dffs <= {d,dffs[1:depth-1]};
1146
assign q = dffs[depth];
1147
assign emptyflag = !(|dffs);
1148
endmodule
1149 40 unneback
`endif
1150 75 unneback
 
1151
`ifdef ASYNC_REG_REQ_ACK
1152
`define MODULE async_reg_req_ack
1153
module `BASE`MODULE ( d, q, req_i, req_o, ack_i, ack_o, clk_a, rst_a, clk_b, rst_b);
1154
`undef MODULE
1155
parameter data_width = 8;
1156
input [data_width-1:0] d;
1157
output [data_width-1:0] q;
1158
input req_i;
1159
output req_o;
1160
input ack_i;
1161
output ack_o;
1162
input clk_a, rst_a, clk_b, rst_b;
1163
 
1164
reg [3:0] reqi; // 3: last req in clk_a, 2: input dff, 1-0: sync
1165
wire rst;
1166
 
1167
always @ (posedge clk_a or rst_a)
1168
if (rst_a)
1169
    q <= {data_width{1'b0}};
1170
else
1171
    if (req_i)
1172
        q <= d;
1173
 
1174
assign rst = ack_i | rst_a;
1175
always @ (posedge clk_a or posedge rst)
1176
if (rst)
1177
    req[2] <= 1'b0;
1178
else
1179
    req[2] <= req_i & !ack_o;
1180
 
1181
always @ (posedge clk_a or posedge rst_a)
1182
if (rst_a)
1183
    req[3] <= 1'b0;
1184
else
1185
    req[3] <= req[2];
1186
 
1187
always @ (posedge clk_b or posedge rst_b)
1188
if (rst_b)
1189
    req[1:0] <= 2'b00;
1190
else
1191
    if (ack_i)
1192
        req[1:0] <= 2'b00;
1193
    else
1194
        req[1:0] <= req[2:1];
1195
assign req_o = req[0];
1196
 
1197
always @ (posedge clk_a or posedge rst_a)
1198
if (rst_a)
1199
    ack_o <= 1'b0;
1200
else
1201
    ack_o <= req[3] & req[2];
1202
 
1203
endmodule
1204
`endif
1205 17 unneback
//////////////////////////////////////////////////////////////////////
1206 6 unneback
////                                                              ////
1207 18 unneback
////  Logic functions                                             ////
1208
////                                                              ////
1209
////  Description                                                 ////
1210
////  Logic functions such as multiplexers                        ////
1211
////                                                              ////
1212
////                                                              ////
1213
////  To Do:                                                      ////
1214
////   -                                                          ////
1215
////                                                              ////
1216
////  Author(s):                                                  ////
1217
////      - Michael Unneback, unneback@opencores.org              ////
1218
////        ORSoC AB                                              ////
1219
////                                                              ////
1220
//////////////////////////////////////////////////////////////////////
1221
////                                                              ////
1222
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1223
////                                                              ////
1224
//// This source file may be used and distributed without         ////
1225
//// restriction provided that this copyright statement is not    ////
1226
//// removed from the file and that any derivative work contains  ////
1227
//// the original copyright notice and the associated disclaimer. ////
1228
////                                                              ////
1229
//// This source file is free software; you can redistribute it   ////
1230
//// and/or modify it under the terms of the GNU Lesser General   ////
1231
//// Public License as published by the Free Software Foundation; ////
1232
//// either version 2.1 of the License, or (at your option) any   ////
1233
//// later version.                                               ////
1234
////                                                              ////
1235
//// This source is distributed in the hope that it will be       ////
1236
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1237
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1238
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1239
//// details.                                                     ////
1240
////                                                              ////
1241
//// You should have received a copy of the GNU Lesser General    ////
1242
//// Public License along with this source; if not, download it   ////
1243
//// from http://www.opencores.org/lgpl.shtml                     ////
1244
////                                                              ////
1245
//////////////////////////////////////////////////////////////////////
1246 40 unneback
`ifdef MUX_ANDOR
1247
`define MODULE mux_andor
1248
module `BASE`MODULE ( a, sel, dout);
1249
`undef MODULE
1250 36 unneback
 
1251
parameter width = 32;
1252
parameter nr_of_ports = 4;
1253
 
1254
input [nr_of_ports*width-1:0] a;
1255
input [nr_of_ports-1:0] sel;
1256
output reg [width-1:0] dout;
1257
 
1258 38 unneback
integer i,j;
1259
 
1260 36 unneback
always @ (a, sel)
1261
begin
1262
    dout = a[width-1:0] & {width{sel[0]}};
1263 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1264
        for (j=0;j<width;j=j+1)
1265
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1266 36 unneback
end
1267
 
1268
endmodule
1269 40 unneback
`endif
1270 36 unneback
 
1271 40 unneback
`ifdef MUX2_ANDOR
1272
`define MODULE mux2_andor
1273
module `BASE`MODULE ( a1, a0, sel, dout);
1274
`undef MODULE
1275 18 unneback
 
1276 34 unneback
parameter width = 32;
1277 35 unneback
localparam nr_of_ports = 2;
1278 34 unneback
input [width-1:0] a1, a0;
1279
input [nr_of_ports-1:0] sel;
1280
output [width-1:0] dout;
1281
 
1282 40 unneback
`define MODULE mux_andor
1283
`BASE`MODULE
1284 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1285 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1286 40 unneback
`undef MODULE
1287
 
1288 34 unneback
endmodule
1289 40 unneback
`endif
1290 34 unneback
 
1291 40 unneback
`ifdef MUX3_ANDOR
1292
`define MODULE mux3_andor
1293
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1294
`undef MODULE
1295 34 unneback
 
1296
parameter width = 32;
1297 35 unneback
localparam nr_of_ports = 3;
1298 34 unneback
input [width-1:0] a2, a1, a0;
1299
input [nr_of_ports-1:0] sel;
1300
output [width-1:0] dout;
1301
 
1302 40 unneback
`define MODULE mux_andor
1303
`BASE`MODULE
1304 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1305 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1306 40 unneback
`undef MODULE
1307 34 unneback
endmodule
1308 40 unneback
`endif
1309 34 unneback
 
1310 40 unneback
`ifdef MUX4_ANDOR
1311
`define MODULE mux4_andor
1312
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1313
`undef MODULE
1314 18 unneback
 
1315
parameter width = 32;
1316 35 unneback
localparam nr_of_ports = 4;
1317 18 unneback
input [width-1:0] a3, a2, a1, a0;
1318
input [nr_of_ports-1:0] sel;
1319 22 unneback
output [width-1:0] dout;
1320 18 unneback
 
1321 40 unneback
`define MODULE mux_andor
1322
`BASE`MODULE
1323 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1324 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1325 40 unneback
`undef MODULE
1326 18 unneback
 
1327
endmodule
1328 40 unneback
`endif
1329 18 unneback
 
1330 40 unneback
`ifdef MUX5_ANDOR
1331
`define MODULE mux5_andor
1332
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1333
`undef MODULE
1334 18 unneback
 
1335
parameter width = 32;
1336 35 unneback
localparam nr_of_ports = 5;
1337 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1338
input [nr_of_ports-1:0] sel;
1339 22 unneback
output [width-1:0] dout;
1340 18 unneback
 
1341 40 unneback
`define MODULE mux_andor
1342
`BASE`MODULE
1343 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1344 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1345 40 unneback
`undef MODULE
1346 18 unneback
 
1347
endmodule
1348 40 unneback
`endif
1349 18 unneback
 
1350 40 unneback
`ifdef MUX6_ANDOR
1351
`define MODULE mux6_andor
1352
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1353
`undef MODULE
1354 18 unneback
 
1355
parameter width = 32;
1356 35 unneback
localparam nr_of_ports = 6;
1357 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1358
input [nr_of_ports-1:0] sel;
1359 22 unneback
output [width-1:0] dout;
1360 18 unneback
 
1361 40 unneback
`define MODULE mux_andor
1362
`BASE`MODULE
1363 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1364 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1365 40 unneback
`undef MODULE
1366 18 unneback
 
1367
endmodule
1368 40 unneback
`endif
1369 43 unneback
 
1370
`ifdef PARITY
1371
 
1372
`define MODULE parity_generate
1373
module `BASE`MODULE (data, parity);
1374
`undef MODULE
1375
parameter word_size = 32;
1376
parameter chunk_size = 8;
1377
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1378
input [word_size-1:0] data;
1379
output reg [word_size/chunk_size-1:0] parity;
1380
integer i,j;
1381
always @ (data)
1382
for (i=0;i<word_size/chunk_size;i=i+1) begin
1383
    parity[i] = parity_type;
1384
    for (j=0;j<chunk_size;j=j+1) begin
1385 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1386 43 unneback
    end
1387
end
1388
endmodule
1389
 
1390
`define MODULE parity_check
1391
module `BASE`MODULE( data, parity, parity_error);
1392
`undef MODULE
1393
parameter word_size = 32;
1394
parameter chunk_size = 8;
1395
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1396
input [word_size-1:0] data;
1397
input [word_size/chunk_size-1:0] parity;
1398
output parity_error;
1399 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1400 43 unneback
integer i,j;
1401
always @ (data or parity)
1402
for (i=0;i<word_size/chunk_size;i=i+1) begin
1403
    error_flag[i] = parity[i] ^ parity_type;
1404
    for (j=0;j<chunk_size;j=j+1) begin
1405 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1406 43 unneback
    end
1407
end
1408
assign parity_error = |error_flag;
1409
endmodule
1410
 
1411 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1412
////                                                              ////
1413
////  IO functions                                                ////
1414
////                                                              ////
1415
////  Description                                                 ////
1416
////  IO functions such as IOB flip-flops                         ////
1417
////                                                              ////
1418
////                                                              ////
1419
////  To Do:                                                      ////
1420
////   -                                                          ////
1421
////                                                              ////
1422
////  Author(s):                                                  ////
1423
////      - Michael Unneback, unneback@opencores.org              ////
1424
////        ORSoC AB                                              ////
1425
////                                                              ////
1426 18 unneback
//////////////////////////////////////////////////////////////////////
1427
////                                                              ////
1428 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1429
////                                                              ////
1430
//// This source file may be used and distributed without         ////
1431
//// restriction provided that this copyright statement is not    ////
1432
//// removed from the file and that any derivative work contains  ////
1433
//// the original copyright notice and the associated disclaimer. ////
1434
////                                                              ////
1435
//// This source file is free software; you can redistribute it   ////
1436
//// and/or modify it under the terms of the GNU Lesser General   ////
1437
//// Public License as published by the Free Software Foundation; ////
1438
//// either version 2.1 of the License, or (at your option) any   ////
1439
//// later version.                                               ////
1440
////                                                              ////
1441
//// This source is distributed in the hope that it will be       ////
1442
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1443
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1444
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1445
//// details.                                                     ////
1446
////                                                              ////
1447
//// You should have received a copy of the GNU Lesser General    ////
1448
//// Public License along with this source; if not, download it   ////
1449
//// from http://www.opencores.org/lgpl.shtml                     ////
1450
////                                                              ////
1451
//////////////////////////////////////////////////////////////////////
1452 45 unneback
`timescale 1ns/1ns
1453 44 unneback
`ifdef O_DFF
1454
`define MODULE o_dff
1455
module `BASE`MODULE (d_i, o_pad, clk, rst);
1456
`undef MODULE
1457
parameter width = 1;
1458 45 unneback
parameter reset_value = {width{1'b0}};
1459
input  [width-1:0]  d_i;
1460 44 unneback
output [width-1:0] o_pad;
1461
input clk, rst;
1462
wire [width-1:0] d_i_int `SYN_KEEP;
1463 45 unneback
reg  [width-1:0] o_pad_int;
1464 44 unneback
assign d_i_int = d_i;
1465
genvar i;
1466 45 unneback
generate
1467 44 unneback
for (i=0;i<width;i=i+1) begin
1468
    always @ (posedge clk or posedge rst)
1469
    if (rst)
1470 45 unneback
        o_pad_int[i] <= reset_value[i];
1471 44 unneback
    else
1472 45 unneback
        o_pad_int[i] <= d_i_int[i];
1473
    assign #1 o_pad[i] = o_pad_int[i];
1474 44 unneback
end
1475
endgenerate
1476
endmodule
1477
`endif
1478
 
1479 45 unneback
`timescale 1ns/1ns
1480 44 unneback
`ifdef IO_DFF_OE
1481
`define MODULE io_dff_oe
1482
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1483
`undef MODULE
1484
parameter width = 1;
1485
input  [width-1:0] d_o;
1486
output reg [width-1:0] d_i;
1487
input oe;
1488
inout [width-1:0] io_pad;
1489
input clk, rst;
1490
wire [width-1:0] oe_d `SYN_KEEP;
1491
reg [width-1:0] oe_q;
1492
reg [width-1:0] d_o_q;
1493
assign oe_d = {width{oe}};
1494
genvar i;
1495
generate
1496
for (i=0;i<width;i=i+1) begin
1497
    always @ (posedge clk or posedge rst)
1498
    if (rst)
1499
        oe_q[i] <= 1'b0;
1500
    else
1501
        oe_q[i] <= oe_d[i];
1502
    always @ (posedge clk or posedge rst)
1503
    if (rst)
1504
        d_o_q[i] <= 1'b0;
1505
    else
1506
        d_o_q[i] <= d_o[i];
1507
    always @ (posedge clk or posedge rst)
1508
    if (rst)
1509
        d_i[i] <= 1'b0;
1510
    else
1511
        d_i[i] <= io_pad[i];
1512 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1513 44 unneback
end
1514
endgenerate
1515
endmodule
1516
`endif
1517
`ifdef CNT_BIN
1518
//////////////////////////////////////////////////////////////////////
1519
////                                                              ////
1520 6 unneback
////  Versatile counter                                           ////
1521
////                                                              ////
1522
////  Description                                                 ////
1523
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1524
////  counter                                                     ////
1525
////                                                              ////
1526
////  To Do:                                                      ////
1527
////   - add LFSR with more taps                                  ////
1528
////                                                              ////
1529
////  Author(s):                                                  ////
1530
////      - Michael Unneback, unneback@opencores.org              ////
1531
////        ORSoC AB                                              ////
1532
////                                                              ////
1533
//////////////////////////////////////////////////////////////////////
1534
////                                                              ////
1535
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1536
////                                                              ////
1537
//// This source file may be used and distributed without         ////
1538
//// restriction provided that this copyright statement is not    ////
1539
//// removed from the file and that any derivative work contains  ////
1540
//// the original copyright notice and the associated disclaimer. ////
1541
////                                                              ////
1542
//// This source file is free software; you can redistribute it   ////
1543
//// and/or modify it under the terms of the GNU Lesser General   ////
1544
//// Public License as published by the Free Software Foundation; ////
1545
//// either version 2.1 of the License, or (at your option) any   ////
1546
//// later version.                                               ////
1547
////                                                              ////
1548
//// This source is distributed in the hope that it will be       ////
1549
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1550
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1551
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1552
//// details.                                                     ////
1553
////                                                              ////
1554
//// You should have received a copy of the GNU Lesser General    ////
1555
//// Public License along with this source; if not, download it   ////
1556
//// from http://www.opencores.org/lgpl.shtml                     ////
1557
////                                                              ////
1558
//////////////////////////////////////////////////////////////////////
1559
 
1560
// binary counter
1561 22 unneback
 
1562 40 unneback
`define MODULE cnt_bin
1563
module `BASE`MODULE (
1564
`undef MODULE
1565
 q, rst, clk);
1566
 
1567 22 unneback
   parameter length = 4;
1568
   output [length:1] q;
1569
   input rst;
1570
   input clk;
1571
 
1572
   parameter clear_value = 0;
1573
   parameter set_value = 1;
1574
   parameter wrap_value = 0;
1575
   parameter level1_value = 15;
1576
 
1577
   reg  [length:1] qi;
1578
   wire [length:1] q_next;
1579
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1580
 
1581
   always @ (posedge clk or posedge rst)
1582
     if (rst)
1583
       qi <= {length{1'b0}};
1584
     else
1585
       qi <= q_next;
1586
 
1587
   assign q = qi;
1588
 
1589
endmodule
1590 40 unneback
`endif
1591
`ifdef CNT_BIN_CLEAR
1592 22 unneback
//////////////////////////////////////////////////////////////////////
1593
////                                                              ////
1594
////  Versatile counter                                           ////
1595
////                                                              ////
1596
////  Description                                                 ////
1597
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1598
////  counter                                                     ////
1599
////                                                              ////
1600
////  To Do:                                                      ////
1601
////   - add LFSR with more taps                                  ////
1602
////                                                              ////
1603
////  Author(s):                                                  ////
1604
////      - Michael Unneback, unneback@opencores.org              ////
1605
////        ORSoC AB                                              ////
1606
////                                                              ////
1607
//////////////////////////////////////////////////////////////////////
1608
////                                                              ////
1609
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1610
////                                                              ////
1611
//// This source file may be used and distributed without         ////
1612
//// restriction provided that this copyright statement is not    ////
1613
//// removed from the file and that any derivative work contains  ////
1614
//// the original copyright notice and the associated disclaimer. ////
1615
////                                                              ////
1616
//// This source file is free software; you can redistribute it   ////
1617
//// and/or modify it under the terms of the GNU Lesser General   ////
1618
//// Public License as published by the Free Software Foundation; ////
1619
//// either version 2.1 of the License, or (at your option) any   ////
1620
//// later version.                                               ////
1621
////                                                              ////
1622
//// This source is distributed in the hope that it will be       ////
1623
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1624
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1625
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1626
//// details.                                                     ////
1627
////                                                              ////
1628
//// You should have received a copy of the GNU Lesser General    ////
1629
//// Public License along with this source; if not, download it   ////
1630
//// from http://www.opencores.org/lgpl.shtml                     ////
1631
////                                                              ////
1632
//////////////////////////////////////////////////////////////////////
1633
 
1634
// binary counter
1635
 
1636 40 unneback
`define MODULE cnt_bin_clear
1637
module `BASE`MODULE (
1638
`undef MODULE
1639
 clear, q, rst, clk);
1640
 
1641 22 unneback
   parameter length = 4;
1642
   input clear;
1643
   output [length:1] q;
1644
   input rst;
1645
   input clk;
1646
 
1647
   parameter clear_value = 0;
1648
   parameter set_value = 1;
1649
   parameter wrap_value = 0;
1650
   parameter level1_value = 15;
1651
 
1652
   reg  [length:1] qi;
1653
   wire [length:1] q_next;
1654
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1655
 
1656
   always @ (posedge clk or posedge rst)
1657
     if (rst)
1658
       qi <= {length{1'b0}};
1659
     else
1660
       qi <= q_next;
1661
 
1662
   assign q = qi;
1663
 
1664
endmodule
1665 40 unneback
`endif
1666
`ifdef CNT_BIN_CE
1667 22 unneback
//////////////////////////////////////////////////////////////////////
1668
////                                                              ////
1669
////  Versatile counter                                           ////
1670
////                                                              ////
1671
////  Description                                                 ////
1672
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1673
////  counter                                                     ////
1674
////                                                              ////
1675
////  To Do:                                                      ////
1676
////   - add LFSR with more taps                                  ////
1677
////                                                              ////
1678
////  Author(s):                                                  ////
1679
////      - Michael Unneback, unneback@opencores.org              ////
1680
////        ORSoC AB                                              ////
1681
////                                                              ////
1682
//////////////////////////////////////////////////////////////////////
1683
////                                                              ////
1684
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1685
////                                                              ////
1686
//// This source file may be used and distributed without         ////
1687
//// restriction provided that this copyright statement is not    ////
1688
//// removed from the file and that any derivative work contains  ////
1689
//// the original copyright notice and the associated disclaimer. ////
1690
////                                                              ////
1691
//// This source file is free software; you can redistribute it   ////
1692
//// and/or modify it under the terms of the GNU Lesser General   ////
1693
//// Public License as published by the Free Software Foundation; ////
1694
//// either version 2.1 of the License, or (at your option) any   ////
1695
//// later version.                                               ////
1696
////                                                              ////
1697
//// This source is distributed in the hope that it will be       ////
1698
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1699
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1700
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1701
//// details.                                                     ////
1702
////                                                              ////
1703
//// You should have received a copy of the GNU Lesser General    ////
1704
//// Public License along with this source; if not, download it   ////
1705
//// from http://www.opencores.org/lgpl.shtml                     ////
1706
////                                                              ////
1707
//////////////////////////////////////////////////////////////////////
1708
 
1709
// binary counter
1710 6 unneback
 
1711 40 unneback
`define MODULE cnt_bin_ce
1712
module `BASE`MODULE (
1713
`undef MODULE
1714
 cke, q, rst, clk);
1715
 
1716 6 unneback
   parameter length = 4;
1717
   input cke;
1718
   output [length:1] q;
1719
   input rst;
1720
   input clk;
1721
 
1722
   parameter clear_value = 0;
1723
   parameter set_value = 1;
1724
   parameter wrap_value = 0;
1725
   parameter level1_value = 15;
1726
 
1727
   reg  [length:1] qi;
1728
   wire [length:1] q_next;
1729
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1730
 
1731
   always @ (posedge clk or posedge rst)
1732
     if (rst)
1733
       qi <= {length{1'b0}};
1734
     else
1735
     if (cke)
1736
       qi <= q_next;
1737
 
1738
   assign q = qi;
1739
 
1740
endmodule
1741 40 unneback
`endif
1742
`ifdef CNT_BIN_CE_CLEAR
1743 6 unneback
//////////////////////////////////////////////////////////////////////
1744
////                                                              ////
1745
////  Versatile counter                                           ////
1746
////                                                              ////
1747
////  Description                                                 ////
1748
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1749
////  counter                                                     ////
1750
////                                                              ////
1751
////  To Do:                                                      ////
1752
////   - add LFSR with more taps                                  ////
1753
////                                                              ////
1754
////  Author(s):                                                  ////
1755
////      - Michael Unneback, unneback@opencores.org              ////
1756
////        ORSoC AB                                              ////
1757
////                                                              ////
1758
//////////////////////////////////////////////////////////////////////
1759
////                                                              ////
1760
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1761
////                                                              ////
1762
//// This source file may be used and distributed without         ////
1763
//// restriction provided that this copyright statement is not    ////
1764
//// removed from the file and that any derivative work contains  ////
1765
//// the original copyright notice and the associated disclaimer. ////
1766
////                                                              ////
1767
//// This source file is free software; you can redistribute it   ////
1768
//// and/or modify it under the terms of the GNU Lesser General   ////
1769
//// Public License as published by the Free Software Foundation; ////
1770
//// either version 2.1 of the License, or (at your option) any   ////
1771
//// later version.                                               ////
1772
////                                                              ////
1773
//// This source is distributed in the hope that it will be       ////
1774
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1775
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1776
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1777
//// details.                                                     ////
1778
////                                                              ////
1779
//// You should have received a copy of the GNU Lesser General    ////
1780
//// Public License along with this source; if not, download it   ////
1781
//// from http://www.opencores.org/lgpl.shtml                     ////
1782
////                                                              ////
1783
//////////////////////////////////////////////////////////////////////
1784
 
1785
// binary counter
1786
 
1787 40 unneback
`define MODULE cnt_bin_ce_clear
1788
module `BASE`MODULE (
1789
`undef MODULE
1790
 clear, cke, q, rst, clk);
1791
 
1792 6 unneback
   parameter length = 4;
1793
   input clear;
1794
   input cke;
1795
   output [length:1] q;
1796
   input rst;
1797
   input clk;
1798
 
1799
   parameter clear_value = 0;
1800
   parameter set_value = 1;
1801
   parameter wrap_value = 0;
1802
   parameter level1_value = 15;
1803
 
1804
   reg  [length:1] qi;
1805
   wire [length:1] q_next;
1806
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1807
 
1808
   always @ (posedge clk or posedge rst)
1809
     if (rst)
1810
       qi <= {length{1'b0}};
1811
     else
1812
     if (cke)
1813
       qi <= q_next;
1814
 
1815
   assign q = qi;
1816
 
1817
endmodule
1818 40 unneback
`endif
1819
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1820 6 unneback
//////////////////////////////////////////////////////////////////////
1821
////                                                              ////
1822
////  Versatile counter                                           ////
1823
////                                                              ////
1824
////  Description                                                 ////
1825
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1826
////  counter                                                     ////
1827
////                                                              ////
1828
////  To Do:                                                      ////
1829
////   - add LFSR with more taps                                  ////
1830
////                                                              ////
1831
////  Author(s):                                                  ////
1832
////      - Michael Unneback, unneback@opencores.org              ////
1833
////        ORSoC AB                                              ////
1834
////                                                              ////
1835
//////////////////////////////////////////////////////////////////////
1836
////                                                              ////
1837
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1838
////                                                              ////
1839
//// This source file may be used and distributed without         ////
1840
//// restriction provided that this copyright statement is not    ////
1841
//// removed from the file and that any derivative work contains  ////
1842
//// the original copyright notice and the associated disclaimer. ////
1843
////                                                              ////
1844
//// This source file is free software; you can redistribute it   ////
1845
//// and/or modify it under the terms of the GNU Lesser General   ////
1846
//// Public License as published by the Free Software Foundation; ////
1847
//// either version 2.1 of the License, or (at your option) any   ////
1848
//// later version.                                               ////
1849
////                                                              ////
1850
//// This source is distributed in the hope that it will be       ////
1851
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1852
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1853
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1854
//// details.                                                     ////
1855
////                                                              ////
1856
//// You should have received a copy of the GNU Lesser General    ////
1857
//// Public License along with this source; if not, download it   ////
1858
//// from http://www.opencores.org/lgpl.shtml                     ////
1859
////                                                              ////
1860
//////////////////////////////////////////////////////////////////////
1861
 
1862
// binary counter
1863 29 unneback
 
1864 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1865
module `BASE`MODULE (
1866
`undef MODULE
1867
 clear, cke, q, level1, level2, rst, clk);
1868
 
1869 29 unneback
   parameter length = 4;
1870
   input clear;
1871
   input cke;
1872
   output [length:1] q;
1873
   output reg level1;
1874
   output reg level2;
1875
   input rst;
1876
   input clk;
1877
 
1878
   parameter clear_value = 0;
1879
   parameter set_value = 1;
1880 30 unneback
   parameter wrap_value = 15;
1881
   parameter level1_value = 8;
1882
   parameter level2_value = 15;
1883 29 unneback
 
1884
   wire rew;
1885 30 unneback
   assign rew = 1'b0;
1886 29 unneback
   reg  [length:1] qi;
1887
   wire [length:1] q_next;
1888
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1889
 
1890
   always @ (posedge clk or posedge rst)
1891
     if (rst)
1892
       qi <= {length{1'b0}};
1893
     else
1894
     if (cke)
1895
       qi <= q_next;
1896
 
1897
   assign q = qi;
1898
 
1899
 
1900
    always @ (posedge clk or posedge rst)
1901
    if (rst)
1902
        level1 <= 1'b0;
1903
    else
1904
    if (cke)
1905
    if (clear)
1906
        level1 <= 1'b0;
1907
    else if (q_next == level1_value)
1908
        level1 <= 1'b1;
1909
    else if (qi == level1_value & rew)
1910
        level1 <= 1'b0;
1911
 
1912
    always @ (posedge clk or posedge rst)
1913
    if (rst)
1914
        level2 <= 1'b0;
1915
    else
1916
    if (cke)
1917
    if (clear)
1918
        level2 <= 1'b0;
1919
    else if (q_next == level2_value)
1920
        level2 <= 1'b1;
1921
    else if (qi == level2_value & rew)
1922
        level2 <= 1'b0;
1923
endmodule
1924 40 unneback
`endif
1925
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1926 29 unneback
//////////////////////////////////////////////////////////////////////
1927
////                                                              ////
1928
////  Versatile counter                                           ////
1929
////                                                              ////
1930
////  Description                                                 ////
1931
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1932
////  counter                                                     ////
1933
////                                                              ////
1934
////  To Do:                                                      ////
1935
////   - add LFSR with more taps                                  ////
1936
////                                                              ////
1937
////  Author(s):                                                  ////
1938
////      - Michael Unneback, unneback@opencores.org              ////
1939
////        ORSoC AB                                              ////
1940
////                                                              ////
1941
//////////////////////////////////////////////////////////////////////
1942
////                                                              ////
1943
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1944
////                                                              ////
1945
//// This source file may be used and distributed without         ////
1946
//// restriction provided that this copyright statement is not    ////
1947
//// removed from the file and that any derivative work contains  ////
1948
//// the original copyright notice and the associated disclaimer. ////
1949
////                                                              ////
1950
//// This source file is free software; you can redistribute it   ////
1951
//// and/or modify it under the terms of the GNU Lesser General   ////
1952
//// Public License as published by the Free Software Foundation; ////
1953
//// either version 2.1 of the License, or (at your option) any   ////
1954
//// later version.                                               ////
1955
////                                                              ////
1956
//// This source is distributed in the hope that it will be       ////
1957
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1958
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1959
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1960
//// details.                                                     ////
1961
////                                                              ////
1962
//// You should have received a copy of the GNU Lesser General    ////
1963
//// Public License along with this source; if not, download it   ////
1964
//// from http://www.opencores.org/lgpl.shtml                     ////
1965
////                                                              ////
1966
//////////////////////////////////////////////////////////////////////
1967
 
1968
// binary counter
1969 6 unneback
 
1970 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1971
module `BASE`MODULE (
1972
`undef MODULE
1973
 clear, set, cke, rew, q, rst, clk);
1974
 
1975 6 unneback
   parameter length = 4;
1976
   input clear;
1977
   input set;
1978
   input cke;
1979
   input rew;
1980
   output [length:1] q;
1981
   input rst;
1982
   input clk;
1983
 
1984
   parameter clear_value = 0;
1985
   parameter set_value = 1;
1986
   parameter wrap_value = 0;
1987
   parameter level1_value = 15;
1988
 
1989
   reg  [length:1] qi;
1990
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1991
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1992
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1993
   assign q_next = rew ? q_next_rew : q_next_fw;
1994
 
1995
   always @ (posedge clk or posedge rst)
1996
     if (rst)
1997
       qi <= {length{1'b0}};
1998
     else
1999
     if (cke)
2000
       qi <= q_next;
2001
 
2002
   assign q = qi;
2003
 
2004
endmodule
2005 40 unneback
`endif
2006
`ifdef CNT_BIN_CE_REW_L1
2007 6 unneback
//////////////////////////////////////////////////////////////////////
2008
////                                                              ////
2009
////  Versatile counter                                           ////
2010
////                                                              ////
2011
////  Description                                                 ////
2012
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2013
////  counter                                                     ////
2014
////                                                              ////
2015
////  To Do:                                                      ////
2016
////   - add LFSR with more taps                                  ////
2017
////                                                              ////
2018
////  Author(s):                                                  ////
2019
////      - Michael Unneback, unneback@opencores.org              ////
2020
////        ORSoC AB                                              ////
2021
////                                                              ////
2022
//////////////////////////////////////////////////////////////////////
2023
////                                                              ////
2024
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2025
////                                                              ////
2026
//// This source file may be used and distributed without         ////
2027
//// restriction provided that this copyright statement is not    ////
2028
//// removed from the file and that any derivative work contains  ////
2029
//// the original copyright notice and the associated disclaimer. ////
2030
////                                                              ////
2031
//// This source file is free software; you can redistribute it   ////
2032
//// and/or modify it under the terms of the GNU Lesser General   ////
2033
//// Public License as published by the Free Software Foundation; ////
2034
//// either version 2.1 of the License, or (at your option) any   ////
2035
//// later version.                                               ////
2036
////                                                              ////
2037
//// This source is distributed in the hope that it will be       ////
2038
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2039
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2040
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2041
//// details.                                                     ////
2042
////                                                              ////
2043
//// You should have received a copy of the GNU Lesser General    ////
2044
//// Public License along with this source; if not, download it   ////
2045
//// from http://www.opencores.org/lgpl.shtml                     ////
2046
////                                                              ////
2047
//////////////////////////////////////////////////////////////////////
2048
 
2049
// binary counter
2050
 
2051 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2052
module `BASE`MODULE (
2053
`undef MODULE
2054
 cke, rew, level1, rst, clk);
2055
 
2056 6 unneback
   parameter length = 4;
2057
   input cke;
2058
   input rew;
2059
   output reg level1;
2060
   input rst;
2061
   input clk;
2062
 
2063
   parameter clear_value = 0;
2064
   parameter set_value = 1;
2065
   parameter wrap_value = 1;
2066
   parameter level1_value = 15;
2067
 
2068 29 unneback
   wire clear;
2069 30 unneback
   assign clear = 1'b0;
2070 6 unneback
   reg  [length:1] qi;
2071
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2072
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2073
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2074
   assign q_next = rew ? q_next_rew : q_next_fw;
2075
 
2076
   always @ (posedge clk or posedge rst)
2077
     if (rst)
2078
       qi <= {length{1'b0}};
2079
     else
2080
     if (cke)
2081
       qi <= q_next;
2082
 
2083
 
2084
 
2085
    always @ (posedge clk or posedge rst)
2086
    if (rst)
2087
        level1 <= 1'b0;
2088
    else
2089
    if (cke)
2090 29 unneback
    if (clear)
2091
        level1 <= 1'b0;
2092
    else if (q_next == level1_value)
2093 6 unneback
        level1 <= 1'b1;
2094
    else if (qi == level1_value & rew)
2095
        level1 <= 1'b0;
2096
endmodule
2097 40 unneback
`endif
2098
`ifdef CNT_BIN_CE_REW_ZQ_L1
2099 6 unneback
//////////////////////////////////////////////////////////////////////
2100
////                                                              ////
2101
////  Versatile counter                                           ////
2102
////                                                              ////
2103
////  Description                                                 ////
2104
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2105
////  counter                                                     ////
2106
////                                                              ////
2107
////  To Do:                                                      ////
2108
////   - add LFSR with more taps                                  ////
2109
////                                                              ////
2110
////  Author(s):                                                  ////
2111
////      - Michael Unneback, unneback@opencores.org              ////
2112
////        ORSoC AB                                              ////
2113
////                                                              ////
2114
//////////////////////////////////////////////////////////////////////
2115
////                                                              ////
2116
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2117
////                                                              ////
2118
//// This source file may be used and distributed without         ////
2119
//// restriction provided that this copyright statement is not    ////
2120
//// removed from the file and that any derivative work contains  ////
2121
//// the original copyright notice and the associated disclaimer. ////
2122
////                                                              ////
2123
//// This source file is free software; you can redistribute it   ////
2124
//// and/or modify it under the terms of the GNU Lesser General   ////
2125
//// Public License as published by the Free Software Foundation; ////
2126
//// either version 2.1 of the License, or (at your option) any   ////
2127
//// later version.                                               ////
2128
////                                                              ////
2129
//// This source is distributed in the hope that it will be       ////
2130
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2131
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2132
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2133
//// details.                                                     ////
2134
////                                                              ////
2135
//// You should have received a copy of the GNU Lesser General    ////
2136
//// Public License along with this source; if not, download it   ////
2137
//// from http://www.opencores.org/lgpl.shtml                     ////
2138
////                                                              ////
2139
//////////////////////////////////////////////////////////////////////
2140
 
2141 25 unneback
// binary counter
2142
 
2143 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2144
module `BASE`MODULE (
2145
`undef MODULE
2146
 cke, rew, zq, level1, rst, clk);
2147
 
2148 25 unneback
   parameter length = 4;
2149
   input cke;
2150
   input rew;
2151
   output reg zq;
2152
   output reg level1;
2153
   input rst;
2154
   input clk;
2155
 
2156
   parameter clear_value = 0;
2157
   parameter set_value = 1;
2158
   parameter wrap_value = 1;
2159
   parameter level1_value = 15;
2160
 
2161 29 unneback
   wire clear;
2162 30 unneback
   assign clear = 1'b0;
2163 25 unneback
   reg  [length:1] qi;
2164
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2165
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2166
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2167
   assign q_next = rew ? q_next_rew : q_next_fw;
2168
 
2169
   always @ (posedge clk or posedge rst)
2170
     if (rst)
2171
       qi <= {length{1'b0}};
2172
     else
2173
     if (cke)
2174
       qi <= q_next;
2175
 
2176
 
2177
 
2178
   always @ (posedge clk or posedge rst)
2179
     if (rst)
2180
       zq <= 1'b1;
2181
     else
2182
     if (cke)
2183
       zq <= q_next == {length{1'b0}};
2184
 
2185
    always @ (posedge clk or posedge rst)
2186
    if (rst)
2187
        level1 <= 1'b0;
2188
    else
2189
    if (cke)
2190 29 unneback
    if (clear)
2191
        level1 <= 1'b0;
2192
    else if (q_next == level1_value)
2193 25 unneback
        level1 <= 1'b1;
2194
    else if (qi == level1_value & rew)
2195
        level1 <= 1'b0;
2196
endmodule
2197 40 unneback
`endif
2198
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2199 25 unneback
//////////////////////////////////////////////////////////////////////
2200
////                                                              ////
2201
////  Versatile counter                                           ////
2202
////                                                              ////
2203
////  Description                                                 ////
2204
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2205
////  counter                                                     ////
2206
////                                                              ////
2207
////  To Do:                                                      ////
2208
////   - add LFSR with more taps                                  ////
2209
////                                                              ////
2210
////  Author(s):                                                  ////
2211
////      - Michael Unneback, unneback@opencores.org              ////
2212
////        ORSoC AB                                              ////
2213
////                                                              ////
2214
//////////////////////////////////////////////////////////////////////
2215
////                                                              ////
2216
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2217
////                                                              ////
2218
//// This source file may be used and distributed without         ////
2219
//// restriction provided that this copyright statement is not    ////
2220
//// removed from the file and that any derivative work contains  ////
2221
//// the original copyright notice and the associated disclaimer. ////
2222
////                                                              ////
2223
//// This source file is free software; you can redistribute it   ////
2224
//// and/or modify it under the terms of the GNU Lesser General   ////
2225
//// Public License as published by the Free Software Foundation; ////
2226
//// either version 2.1 of the License, or (at your option) any   ////
2227
//// later version.                                               ////
2228
////                                                              ////
2229
//// This source is distributed in the hope that it will be       ////
2230
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2231
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2232
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2233
//// details.                                                     ////
2234
////                                                              ////
2235
//// You should have received a copy of the GNU Lesser General    ////
2236
//// Public License along with this source; if not, download it   ////
2237
//// from http://www.opencores.org/lgpl.shtml                     ////
2238
////                                                              ////
2239
//////////////////////////////////////////////////////////////////////
2240
 
2241
// binary counter
2242
 
2243 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2244
module `BASE`MODULE (
2245
`undef MODULE
2246
 cke, rew, q, zq, level1, rst, clk);
2247
 
2248 25 unneback
   parameter length = 4;
2249
   input cke;
2250
   input rew;
2251
   output [length:1] q;
2252
   output reg zq;
2253
   output reg level1;
2254
   input rst;
2255
   input clk;
2256
 
2257
   parameter clear_value = 0;
2258
   parameter set_value = 1;
2259
   parameter wrap_value = 1;
2260
   parameter level1_value = 15;
2261
 
2262 29 unneback
   wire clear;
2263 30 unneback
   assign clear = 1'b0;
2264 25 unneback
   reg  [length:1] qi;
2265
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2266
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2267
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2268
   assign q_next = rew ? q_next_rew : q_next_fw;
2269
 
2270
   always @ (posedge clk or posedge rst)
2271
     if (rst)
2272
       qi <= {length{1'b0}};
2273
     else
2274
     if (cke)
2275
       qi <= q_next;
2276
 
2277
   assign q = qi;
2278
 
2279
 
2280
   always @ (posedge clk or posedge rst)
2281
     if (rst)
2282
       zq <= 1'b1;
2283
     else
2284
     if (cke)
2285
       zq <= q_next == {length{1'b0}};
2286
 
2287
    always @ (posedge clk or posedge rst)
2288
    if (rst)
2289
        level1 <= 1'b0;
2290
    else
2291
    if (cke)
2292 29 unneback
    if (clear)
2293
        level1 <= 1'b0;
2294
    else if (q_next == level1_value)
2295 25 unneback
        level1 <= 1'b1;
2296
    else if (qi == level1_value & rew)
2297
        level1 <= 1'b0;
2298
endmodule
2299 40 unneback
`endif
2300
`ifdef CNT_LFSR_ZQ
2301 25 unneback
//////////////////////////////////////////////////////////////////////
2302
////                                                              ////
2303
////  Versatile counter                                           ////
2304
////                                                              ////
2305
////  Description                                                 ////
2306
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2307
////  counter                                                     ////
2308
////                                                              ////
2309
////  To Do:                                                      ////
2310
////   - add LFSR with more taps                                  ////
2311
////                                                              ////
2312
////  Author(s):                                                  ////
2313
////      - Michael Unneback, unneback@opencores.org              ////
2314
////        ORSoC AB                                              ////
2315
////                                                              ////
2316
//////////////////////////////////////////////////////////////////////
2317
////                                                              ////
2318
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2319
////                                                              ////
2320
//// This source file may be used and distributed without         ////
2321
//// restriction provided that this copyright statement is not    ////
2322
//// removed from the file and that any derivative work contains  ////
2323
//// the original copyright notice and the associated disclaimer. ////
2324
////                                                              ////
2325
//// This source file is free software; you can redistribute it   ////
2326
//// and/or modify it under the terms of the GNU Lesser General   ////
2327
//// Public License as published by the Free Software Foundation; ////
2328
//// either version 2.1 of the License, or (at your option) any   ////
2329
//// later version.                                               ////
2330
////                                                              ////
2331
//// This source is distributed in the hope that it will be       ////
2332
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2333
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2334
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2335
//// details.                                                     ////
2336
////                                                              ////
2337
//// You should have received a copy of the GNU Lesser General    ////
2338
//// Public License along with this source; if not, download it   ////
2339
//// from http://www.opencores.org/lgpl.shtml                     ////
2340
////                                                              ////
2341
//////////////////////////////////////////////////////////////////////
2342
 
2343 6 unneback
// LFSR counter
2344
 
2345 40 unneback
`define MODULE cnt_lfsr_zq
2346
module `BASE`MODULE (
2347
`undef MODULE
2348
 zq, rst, clk);
2349
 
2350 6 unneback
   parameter length = 4;
2351
   output reg zq;
2352
   input rst;
2353
   input clk;
2354
 
2355
   parameter clear_value = 0;
2356
   parameter set_value = 1;
2357
   parameter wrap_value = 8;
2358
   parameter level1_value = 15;
2359
 
2360
   reg  [length:1] qi;
2361
   reg lfsr_fb;
2362
   wire [length:1] q_next;
2363
   reg [32:1] polynom;
2364
   integer i;
2365
 
2366
   always @ (qi)
2367
   begin
2368
        case (length)
2369
         2: polynom = 32'b11;                               // 0x3
2370
         3: polynom = 32'b110;                              // 0x6
2371
         4: polynom = 32'b1100;                             // 0xC
2372
         5: polynom = 32'b10100;                            // 0x14
2373
         6: polynom = 32'b110000;                           // 0x30
2374
         7: polynom = 32'b1100000;                          // 0x60
2375
         8: polynom = 32'b10111000;                         // 0xb8
2376
         9: polynom = 32'b100010000;                        // 0x110
2377
        10: polynom = 32'b1001000000;                       // 0x240
2378
        11: polynom = 32'b10100000000;                      // 0x500
2379
        12: polynom = 32'b100000101001;                     // 0x829
2380
        13: polynom = 32'b1000000001100;                    // 0x100C
2381
        14: polynom = 32'b10000000010101;                   // 0x2015
2382
        15: polynom = 32'b110000000000000;                  // 0x6000
2383
        16: polynom = 32'b1101000000001000;                 // 0xD008
2384
        17: polynom = 32'b10010000000000000;                // 0x12000
2385
        18: polynom = 32'b100000010000000000;               // 0x20400
2386
        19: polynom = 32'b1000000000000100011;              // 0x40023
2387 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2388 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2389
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2390
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2391
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2392
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2393
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2394
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2395
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2396
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2397
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2398
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2399
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2400
        default: polynom = 32'b0;
2401
        endcase
2402
        lfsr_fb = qi[length];
2403
        for (i=length-1; i>=1; i=i-1) begin
2404
            if (polynom[i])
2405
                lfsr_fb = lfsr_fb  ~^ qi[i];
2406
        end
2407
    end
2408
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2409
 
2410
   always @ (posedge clk or posedge rst)
2411
     if (rst)
2412
       qi <= {length{1'b0}};
2413
     else
2414
       qi <= q_next;
2415
 
2416
 
2417
 
2418
   always @ (posedge clk or posedge rst)
2419
     if (rst)
2420
       zq <= 1'b1;
2421
     else
2422
       zq <= q_next == {length{1'b0}};
2423
endmodule
2424 40 unneback
`endif
2425 75 unneback
`ifdef CNT_LFSR_CE
2426
//////////////////////////////////////////////////////////////////////
2427
////                                                              ////
2428
////  Versatile counter                                           ////
2429
////                                                              ////
2430
////  Description                                                 ////
2431
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2432
////  counter                                                     ////
2433
////                                                              ////
2434
////  To Do:                                                      ////
2435
////   - add LFSR with more taps                                  ////
2436
////                                                              ////
2437
////  Author(s):                                                  ////
2438
////      - Michael Unneback, unneback@opencores.org              ////
2439
////        ORSoC AB                                              ////
2440
////                                                              ////
2441
//////////////////////////////////////////////////////////////////////
2442
////                                                              ////
2443
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2444
////                                                              ////
2445
//// This source file may be used and distributed without         ////
2446
//// restriction provided that this copyright statement is not    ////
2447
//// removed from the file and that any derivative work contains  ////
2448
//// the original copyright notice and the associated disclaimer. ////
2449
////                                                              ////
2450
//// This source file is free software; you can redistribute it   ////
2451
//// and/or modify it under the terms of the GNU Lesser General   ////
2452
//// Public License as published by the Free Software Foundation; ////
2453
//// either version 2.1 of the License, or (at your option) any   ////
2454
//// later version.                                               ////
2455
////                                                              ////
2456
//// This source is distributed in the hope that it will be       ////
2457
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2458
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2459
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2460
//// details.                                                     ////
2461
////                                                              ////
2462
//// You should have received a copy of the GNU Lesser General    ////
2463
//// Public License along with this source; if not, download it   ////
2464
//// from http://www.opencores.org/lgpl.shtml                     ////
2465
////                                                              ////
2466
//////////////////////////////////////////////////////////////////////
2467
 
2468
// LFSR counter
2469
 
2470
`define MODULE cnt_lfsr_ce
2471
module `BASE`MODULE (
2472
`undef MODULE
2473
 cke, zq, rst, clk);
2474
 
2475
   parameter length = 4;
2476
   input cke;
2477
   output reg zq;
2478
   input rst;
2479
   input clk;
2480
 
2481
   parameter clear_value = 0;
2482
   parameter set_value = 1;
2483
   parameter wrap_value = 0;
2484
   parameter level1_value = 15;
2485
 
2486
   reg  [length:1] qi;
2487
   reg lfsr_fb;
2488
   wire [length:1] q_next;
2489
   reg [32:1] polynom;
2490
   integer i;
2491
 
2492
   always @ (qi)
2493
   begin
2494
        case (length)
2495
         2: polynom = 32'b11;                               // 0x3
2496
         3: polynom = 32'b110;                              // 0x6
2497
         4: polynom = 32'b1100;                             // 0xC
2498
         5: polynom = 32'b10100;                            // 0x14
2499
         6: polynom = 32'b110000;                           // 0x30
2500
         7: polynom = 32'b1100000;                          // 0x60
2501
         8: polynom = 32'b10111000;                         // 0xb8
2502
         9: polynom = 32'b100010000;                        // 0x110
2503
        10: polynom = 32'b1001000000;                       // 0x240
2504
        11: polynom = 32'b10100000000;                      // 0x500
2505
        12: polynom = 32'b100000101001;                     // 0x829
2506
        13: polynom = 32'b1000000001100;                    // 0x100C
2507
        14: polynom = 32'b10000000010101;                   // 0x2015
2508
        15: polynom = 32'b110000000000000;                  // 0x6000
2509
        16: polynom = 32'b1101000000001000;                 // 0xD008
2510
        17: polynom = 32'b10010000000000000;                // 0x12000
2511
        18: polynom = 32'b100000010000000000;               // 0x20400
2512
        19: polynom = 32'b1000000000000100011;              // 0x40023
2513
        20: polynom = 32'b10010000000000000000;             // 0x90000
2514
        21: polynom = 32'b101000000000000000000;            // 0x140000
2515
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2516
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2517
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2518
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2519
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2520
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2521
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2522
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2523
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2524
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2525
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2526
        default: polynom = 32'b0;
2527
        endcase
2528
        lfsr_fb = qi[length];
2529
        for (i=length-1; i>=1; i=i-1) begin
2530
            if (polynom[i])
2531
                lfsr_fb = lfsr_fb  ~^ qi[i];
2532
        end
2533
    end
2534
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2535
 
2536
   always @ (posedge clk or posedge rst)
2537
     if (rst)
2538
       qi <= {length{1'b0}};
2539
     else
2540
     if (cke)
2541
       qi <= q_next;
2542
 
2543
 
2544
 
2545
   always @ (posedge clk or posedge rst)
2546
     if (rst)
2547
       zq <= 1'b1;
2548
     else
2549
     if (cke)
2550
       zq <= q_next == {length{1'b0}};
2551
endmodule
2552
`endif
2553 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2554 6 unneback
//////////////////////////////////////////////////////////////////////
2555
////                                                              ////
2556
////  Versatile counter                                           ////
2557
////                                                              ////
2558
////  Description                                                 ////
2559
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2560
////  counter                                                     ////
2561
////                                                              ////
2562
////  To Do:                                                      ////
2563
////   - add LFSR with more taps                                  ////
2564
////                                                              ////
2565
////  Author(s):                                                  ////
2566
////      - Michael Unneback, unneback@opencores.org              ////
2567
////        ORSoC AB                                              ////
2568
////                                                              ////
2569
//////////////////////////////////////////////////////////////////////
2570
////                                                              ////
2571
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2572
////                                                              ////
2573
//// This source file may be used and distributed without         ////
2574
//// restriction provided that this copyright statement is not    ////
2575
//// removed from the file and that any derivative work contains  ////
2576
//// the original copyright notice and the associated disclaimer. ////
2577
////                                                              ////
2578
//// This source file is free software; you can redistribute it   ////
2579
//// and/or modify it under the terms of the GNU Lesser General   ////
2580
//// Public License as published by the Free Software Foundation; ////
2581
//// either version 2.1 of the License, or (at your option) any   ////
2582
//// later version.                                               ////
2583
////                                                              ////
2584
//// This source is distributed in the hope that it will be       ////
2585
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2586
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2587
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2588
//// details.                                                     ////
2589
////                                                              ////
2590
//// You should have received a copy of the GNU Lesser General    ////
2591
//// Public License along with this source; if not, download it   ////
2592
//// from http://www.opencores.org/lgpl.shtml                     ////
2593
////                                                              ////
2594
//////////////////////////////////////////////////////////////////////
2595
 
2596
// LFSR counter
2597
 
2598 40 unneback
`define MODULE cnt_lfsr_ce_zq
2599
module `BASE`MODULE (
2600
`undef MODULE
2601
 cke, zq, rst, clk);
2602
 
2603 6 unneback
   parameter length = 4;
2604
   input cke;
2605
   output reg zq;
2606
   input rst;
2607
   input clk;
2608
 
2609
   parameter clear_value = 0;
2610
   parameter set_value = 1;
2611
   parameter wrap_value = 8;
2612
   parameter level1_value = 15;
2613
 
2614
   reg  [length:1] qi;
2615
   reg lfsr_fb;
2616
   wire [length:1] q_next;
2617
   reg [32:1] polynom;
2618
   integer i;
2619
 
2620
   always @ (qi)
2621
   begin
2622
        case (length)
2623
         2: polynom = 32'b11;                               // 0x3
2624
         3: polynom = 32'b110;                              // 0x6
2625
         4: polynom = 32'b1100;                             // 0xC
2626
         5: polynom = 32'b10100;                            // 0x14
2627
         6: polynom = 32'b110000;                           // 0x30
2628
         7: polynom = 32'b1100000;                          // 0x60
2629
         8: polynom = 32'b10111000;                         // 0xb8
2630
         9: polynom = 32'b100010000;                        // 0x110
2631
        10: polynom = 32'b1001000000;                       // 0x240
2632
        11: polynom = 32'b10100000000;                      // 0x500
2633
        12: polynom = 32'b100000101001;                     // 0x829
2634
        13: polynom = 32'b1000000001100;                    // 0x100C
2635
        14: polynom = 32'b10000000010101;                   // 0x2015
2636
        15: polynom = 32'b110000000000000;                  // 0x6000
2637
        16: polynom = 32'b1101000000001000;                 // 0xD008
2638
        17: polynom = 32'b10010000000000000;                // 0x12000
2639
        18: polynom = 32'b100000010000000000;               // 0x20400
2640
        19: polynom = 32'b1000000000000100011;              // 0x40023
2641 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2642 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2643
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2644
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2645
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2646
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2647
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2648
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2649
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2650
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2651
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2652
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2653
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2654
        default: polynom = 32'b0;
2655
        endcase
2656
        lfsr_fb = qi[length];
2657
        for (i=length-1; i>=1; i=i-1) begin
2658
            if (polynom[i])
2659
                lfsr_fb = lfsr_fb  ~^ qi[i];
2660
        end
2661
    end
2662
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2663
 
2664
   always @ (posedge clk or posedge rst)
2665
     if (rst)
2666
       qi <= {length{1'b0}};
2667
     else
2668
     if (cke)
2669
       qi <= q_next;
2670
 
2671
 
2672
 
2673
   always @ (posedge clk or posedge rst)
2674
     if (rst)
2675
       zq <= 1'b1;
2676
     else
2677
     if (cke)
2678
       zq <= q_next == {length{1'b0}};
2679
endmodule
2680 40 unneback
`endif
2681
`ifdef CNT_LFSR_CE_Q
2682 6 unneback
//////////////////////////////////////////////////////////////////////
2683
////                                                              ////
2684
////  Versatile counter                                           ////
2685
////                                                              ////
2686
////  Description                                                 ////
2687
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2688
////  counter                                                     ////
2689
////                                                              ////
2690
////  To Do:                                                      ////
2691
////   - add LFSR with more taps                                  ////
2692
////                                                              ////
2693
////  Author(s):                                                  ////
2694
////      - Michael Unneback, unneback@opencores.org              ////
2695
////        ORSoC AB                                              ////
2696
////                                                              ////
2697
//////////////////////////////////////////////////////////////////////
2698
////                                                              ////
2699
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2700
////                                                              ////
2701
//// This source file may be used and distributed without         ////
2702
//// restriction provided that this copyright statement is not    ////
2703
//// removed from the file and that any derivative work contains  ////
2704
//// the original copyright notice and the associated disclaimer. ////
2705
////                                                              ////
2706
//// This source file is free software; you can redistribute it   ////
2707
//// and/or modify it under the terms of the GNU Lesser General   ////
2708
//// Public License as published by the Free Software Foundation; ////
2709
//// either version 2.1 of the License, or (at your option) any   ////
2710
//// later version.                                               ////
2711
////                                                              ////
2712
//// This source is distributed in the hope that it will be       ////
2713
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2714
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2715
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2716
//// details.                                                     ////
2717
////                                                              ////
2718
//// You should have received a copy of the GNU Lesser General    ////
2719
//// Public License along with this source; if not, download it   ////
2720
//// from http://www.opencores.org/lgpl.shtml                     ////
2721
////                                                              ////
2722
//////////////////////////////////////////////////////////////////////
2723 22 unneback
 
2724
// LFSR counter
2725 27 unneback
 
2726 40 unneback
`define MODULE cnt_lfsr_ce_q
2727
module `BASE`MODULE (
2728
`undef MODULE
2729
 cke, q, rst, clk);
2730
 
2731 27 unneback
   parameter length = 4;
2732
   input cke;
2733
   output [length:1] q;
2734
   input rst;
2735
   input clk;
2736
 
2737
   parameter clear_value = 0;
2738
   parameter set_value = 1;
2739
   parameter wrap_value = 8;
2740
   parameter level1_value = 15;
2741
 
2742
   reg  [length:1] qi;
2743
   reg lfsr_fb;
2744
   wire [length:1] q_next;
2745
   reg [32:1] polynom;
2746
   integer i;
2747
 
2748
   always @ (qi)
2749
   begin
2750
        case (length)
2751
         2: polynom = 32'b11;                               // 0x3
2752
         3: polynom = 32'b110;                              // 0x6
2753
         4: polynom = 32'b1100;                             // 0xC
2754
         5: polynom = 32'b10100;                            // 0x14
2755
         6: polynom = 32'b110000;                           // 0x30
2756
         7: polynom = 32'b1100000;                          // 0x60
2757
         8: polynom = 32'b10111000;                         // 0xb8
2758
         9: polynom = 32'b100010000;                        // 0x110
2759
        10: polynom = 32'b1001000000;                       // 0x240
2760
        11: polynom = 32'b10100000000;                      // 0x500
2761
        12: polynom = 32'b100000101001;                     // 0x829
2762
        13: polynom = 32'b1000000001100;                    // 0x100C
2763
        14: polynom = 32'b10000000010101;                   // 0x2015
2764
        15: polynom = 32'b110000000000000;                  // 0x6000
2765
        16: polynom = 32'b1101000000001000;                 // 0xD008
2766
        17: polynom = 32'b10010000000000000;                // 0x12000
2767
        18: polynom = 32'b100000010000000000;               // 0x20400
2768
        19: polynom = 32'b1000000000000100011;              // 0x40023
2769 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2770 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2771
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2772
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2773
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2774
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2775
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2776
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2777
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2778
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2779
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2780
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2781
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2782
        default: polynom = 32'b0;
2783
        endcase
2784
        lfsr_fb = qi[length];
2785
        for (i=length-1; i>=1; i=i-1) begin
2786
            if (polynom[i])
2787
                lfsr_fb = lfsr_fb  ~^ qi[i];
2788
        end
2789
    end
2790
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2791
 
2792
   always @ (posedge clk or posedge rst)
2793
     if (rst)
2794
       qi <= {length{1'b0}};
2795
     else
2796
     if (cke)
2797
       qi <= q_next;
2798
 
2799
   assign q = qi;
2800
 
2801
endmodule
2802 40 unneback
`endif
2803
`ifdef CNT_LFSR_CE_CLEAR_Q
2804 27 unneback
//////////////////////////////////////////////////////////////////////
2805
////                                                              ////
2806
////  Versatile counter                                           ////
2807
////                                                              ////
2808
////  Description                                                 ////
2809
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2810
////  counter                                                     ////
2811
////                                                              ////
2812
////  To Do:                                                      ////
2813