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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 95

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 40 unneback
`ifdef ALL
14
 
15
`define GBUF
16
`define SYNC_RST
17
`define PLL
18
 
19
`define MULTS
20
`define MULTS18X18
21
`define MULT
22
`define SHIFT_UNIT_32
23
`define LOGIC_UNIT
24
 
25
`define CNT_SHREG_WRAP
26
`define CNT_SHREG_CE_WRAP
27
`define CNT_SHREG_CE_CLEAR
28
`define CNT_SHREG_CE_CLEAR_WRAP
29
 
30
`define MUX_ANDOR
31
`define MUX2_ANDOR
32
`define MUX3_ANDOR
33
`define MUX4_ANDOR
34
`define MUX5_ANDOR
35
`define MUX6_ANDOR
36 43 unneback
`define PARITY
37 40 unneback
 
38
`define ROM_INIT
39
`define RAM
40
`define RAM_BE
41
`define DPRAM_1R1W
42
`define DPRAM_2R1W
43
`define DPRAM_2R2W
44 75 unneback
`define DPRAM_BE_2R2W
45 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
46
`define FIFO_2R2W_SYNC_SIMPLEX
47
`define FIFO_CMP_ASYNC
48
`define FIFO_1R1W_ASYNC
49
`define FIFO_2R2W_ASYNC
50
`define FIFO_2R2W_ASYNC_SIMPLEX
51 48 unneback
`define REG_FILE
52 40 unneback
 
53
`define DFF
54
`define DFF_ARRAY
55
`define DFF_CE
56
`define DFF_CE_CLEAR
57
`define DF_CE_SET
58
`define SPR
59
`define SRP
60
`define DFF_SR
61
`define LATCH
62
`define SHREG
63
`define SHREG_CE
64
`define DELAY
65
`define DELAY_EMPTYFLAG
66 94 unneback
`define PULSE2TOGGLE
67
`define TOGGLE2PULSE
68
`define SYNCHRONIZER
69
`define CDC
70 40 unneback
 
71 75 unneback
`define WB3AVALON_BRIDGE
72 40 unneback
`define WB3WB3_BRIDGE
73
`define WB3_ARBITER_TYPE1
74 83 unneback
`define WB_ADR_INC
75 59 unneback
`define WB_B3_RAM_BE
76 49 unneback
`define WB_B4_RAM_BE
77 48 unneback
`define WB_B4_ROM
78 40 unneback
`define WB_BOOT_ROM
79
`define WB_DPRAM
80
 
81 44 unneback
`define IO_DFF_OE
82
`define O_DFF
83
 
84 40 unneback
`endif
85
 
86
`ifdef PLL
87
`ifndef SYNC_RST
88
`define SYNC_RST
89
`endif
90
`endif
91
 
92
`ifdef SYNC_RST
93
`ifndef GBUF
94
`define GBUF
95
`endif
96
`endif
97
 
98 94 unneback
`ifdef CDC
99
`ifndef PULSE2TOGGLE
100
`define PULSE2TOGGLE
101
`endif
102
`ifndef TOGGLE2PULSE
103
`define TOGGLE2PULSE
104
`endif
105
`ifndef SYNCHRONIZER
106
`define SYNCHRONIZER
107
`endif
108
`endif
109
 
110 92 unneback
`ifdef WB_B3_DPRAM
111
`ifndef WB_ADR_INC
112
`define WB_ADR_INC
113 40 unneback
`endif
114 92 unneback
`ifndef DPRAM_BE_2R2W
115
`define DPRAM_BE_2R2W
116 40 unneback
`endif
117
`endif
118
 
119 62 unneback
`ifdef WB_B3_RAM_BE
120 83 unneback
`ifndef WB_ADR_INC
121
`define WB_ADR_INC
122 62 unneback
`endif
123
`ifndef RAM_BE
124
`define RAM_BE
125
`endif
126
`endif
127
 
128 40 unneback
`ifdef WB3_ARBITER_TYPE1
129 42 unneback
`ifndef SPR
130
`define SPR
131
`endif
132 40 unneback
`ifndef MUX_ANDOR
133
`define MUX_ANDOR
134
`endif
135
`endif
136
 
137 76 unneback
`ifdef WB3AVALON_BRIDGE
138
`ifndef WB3WB3_BRIDGE
139
`define WB3WB3_BRIDGE
140
`endif
141
`endif
142
 
143 40 unneback
`ifdef WB3WB3_BRIDGE
144
`ifndef CNT_SHREG_CE_CLEAR
145
`define CNT_SHREG_CE_CLEAR
146
`endif
147
`ifndef DFF
148
`define DFF
149
`endif
150
`ifndef DFF_CE
151
`define DFF_CE
152
`endif
153
`ifndef CNT_SHREG_CE_CLEAR
154
`define CNT_SHREG_CE_CLEAR
155
`endif
156
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
157
`define FIFO_2R2W_ASYNC_SIMPLEX
158
`endif
159
`endif
160
 
161
`ifdef MULTS18X18
162
`ifndef MULTS
163
`define MULTS
164
`endif
165
`endif
166
 
167
`ifdef SHIFT_UNIT_32
168
`ifndef MULTS
169
`define MULTS
170
`endif
171
`endif
172
 
173
`ifdef MUX2_ANDOR
174
`ifndef MUX_ANDOR
175
`define MUX_ANDOR
176
`endif
177
`endif
178
 
179
`ifdef MUX3_ANDOR
180
`ifndef MUX_ANDOR
181
`define MUX_ANDOR
182
`endif
183
`endif
184
 
185
`ifdef MUX4_ANDOR
186
`ifndef MUX_ANDOR
187
`define MUX_ANDOR
188
`endif
189
`endif
190
 
191
`ifdef MUX5_ANDOR
192
`ifndef MUX_ANDOR
193
`define MUX_ANDOR
194
`endif
195
`endif
196
 
197
`ifdef MUX6_ANDOR
198
`ifndef MUX_ANDOR
199
`define MUX_ANDOR
200
`endif
201
`endif
202
 
203
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
204
`ifndef CNT_BIN_CE
205
`define CNT_BIN_CE
206
`endif
207
`ifndef DPRAM_1R1W
208
`define DPRAM_1R1W
209
`endif
210
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
211
`define CNT_BIN_CE_REW_Q_ZQ_L1
212
`endif
213
`endif
214
 
215
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
216
`ifndef CNT_LFSR_CE
217
`define CNT_LFSR_CE
218
`endif
219
`ifndef DPRAM_2R2W
220
`define DPRAM_2R2W
221
`endif
222
`ifndef CNT_BIN_CE_REW_ZQ_L1
223
`define CNT_BIN_CE_REW_ZQ_L1
224
`endif
225
`endif
226
 
227
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
228
`ifndef CNT_GRAY_CE_BIN
229
`define CNT_GRAY_CE_BIN
230
`endif
231
`ifndef DPRAM_2R2W
232
`define DPRAM_2R2W
233
`endif
234
`ifndef FIFO_CMP_ASYNC
235
`define FIFO_CMP_ASYNC
236
`endif
237
`endif
238
 
239
`ifdef FIFO_2R2W_ASYNC
240
`ifndef FIFO_1R1W_ASYNC
241
`define FIFO_1R1W_ASYNC
242
`endif
243
`endif
244
 
245
`ifdef FIFO_1R1W_ASYNC
246
`ifndef CNT_GRAY_CE_BIN
247
`define CNT_GRAY_CE_BIN
248
`endif
249
`ifndef DPRAM_1R1W
250
`define DPRAM_1R1W
251
`endif
252
`ifndef FIFO_CMP_ASYNC
253
`define FIFO_CMP_ASYNC
254
`endif
255
`endif
256
 
257
`ifdef FIFO_CMP_ASYNC
258
`ifndef DFF_SR
259
`define DFF_SR
260
`endif
261
`ifndef DFF
262
`define DFF
263
`endif
264
`endif
265 48 unneback
 
266
`ifdef REG_FILE
267
`ifndef DPRAM_1R1W
268
`define DPRAM_1R1W
269
`endif
270
`endif
271 62 unneback
//////////////////////////////////////////////////////////////////////
272 6 unneback
////                                                              ////
273
////  Versatile library, clock and reset                          ////
274
////                                                              ////
275
////  Description                                                 ////
276
////  Logic related to clock and reset                            ////
277
////                                                              ////
278
////                                                              ////
279
////  To Do:                                                      ////
280
////   - add more different registers                             ////
281
////                                                              ////
282
////  Author(s):                                                  ////
283
////      - Michael Unneback, unneback@opencores.org              ////
284
////        ORSoC AB                                              ////
285
////                                                              ////
286
//////////////////////////////////////////////////////////////////////
287
////                                                              ////
288
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
289
////                                                              ////
290
//// This source file may be used and distributed without         ////
291
//// restriction provided that this copyright statement is not    ////
292
//// removed from the file and that any derivative work contains  ////
293
//// the original copyright notice and the associated disclaimer. ////
294
////                                                              ////
295
//// This source file is free software; you can redistribute it   ////
296
//// and/or modify it under the terms of the GNU Lesser General   ////
297
//// Public License as published by the Free Software Foundation; ////
298
//// either version 2.1 of the License, or (at your option) any   ////
299
//// later version.                                               ////
300
////                                                              ////
301
//// This source is distributed in the hope that it will be       ////
302
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
303
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
304
//// PURPOSE.  See the GNU Lesser General Public License for more ////
305
//// details.                                                     ////
306
////                                                              ////
307
//// You should have received a copy of the GNU Lesser General    ////
308
//// Public License along with this source; if not, download it   ////
309
//// from http://www.opencores.org/lgpl.shtml                     ////
310
////                                                              ////
311
//////////////////////////////////////////////////////////////////////
312
 
313 48 unneback
`ifdef ACTEL
314
`ifdef GBUF
315
`timescale 1 ns/100 ps
316 6 unneback
// Global buffer
317
// usage:
318
// use to enable global buffers for high fan out signals such as clock and reset
319
// Version: 8.4 8.4.0.33
320
module gbuf(GL,CLK);
321
output GL;
322
input  CLK;
323
 
324
    wire GND;
325
 
326
    GND GND_1_net(.Y(GND));
327
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
328
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
329
 
330
endmodule
331
`timescale 1 ns/1 ns
332 40 unneback
`define MODULE gbuf
333
module `BASE`MODULE ( i, o);
334
`undef MODULE
335 6 unneback
input i;
336
output o;
337
`ifdef SIM_GBUF
338
assign o=i;
339
`else
340
gbuf gbuf_i0 ( .CLK(i), .GL(o));
341
`endif
342
endmodule
343 40 unneback
`endif
344 33 unneback
 
345 6 unneback
`else
346 33 unneback
 
347 40 unneback
`ifdef ALTERA
348
`ifdef GBUF
349 21 unneback
//altera
350 40 unneback
`define MODULE gbuf
351
module `BASE`MODULE ( i, o);
352
`undef MODULE
353 33 unneback
input i;
354
output o;
355
assign o = i;
356
endmodule
357 40 unneback
`endif
358 33 unneback
 
359 6 unneback
`else
360
 
361 40 unneback
`ifdef GBUF
362 6 unneback
`timescale 1 ns/100 ps
363 40 unneback
`define MODULE
364
module `BASE`MODULE ( i, o);
365
`undef MODULE
366 6 unneback
input i;
367
output o;
368
assign o = i;
369
endmodule
370 40 unneback
`endif
371 6 unneback
`endif // ALTERA
372
`endif //ACTEL
373
 
374 40 unneback
`ifdef SYNC_RST
375 6 unneback
// sync reset
376 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
377 6 unneback
// output active high global reset sync with two DFFs 
378
`timescale 1 ns/100 ps
379 40 unneback
`define MODULE sync_rst
380
module `BASE`MODULE ( rst_n_i, rst_o, clk);
381
`undef MODULE
382 6 unneback
input rst_n_i, clk;
383
output rst_o;
384 18 unneback
reg [1:0] tmp;
385 6 unneback
always @ (posedge clk or negedge rst_n_i)
386
if (!rst_n_i)
387 17 unneback
        tmp <= 2'b11;
388 6 unneback
else
389 33 unneback
        tmp <= {1'b0,tmp[1]};
390 40 unneback
`define MODULE gbuf
391
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
392
`undef MODULE
393 6 unneback
endmodule
394 40 unneback
`endif
395 6 unneback
 
396 40 unneback
`ifdef PLL
397 6 unneback
// vl_pll
398
`ifdef ACTEL
399 32 unneback
///////////////////////////////////////////////////////////////////////////////
400 17 unneback
`timescale 1 ps/1 ps
401 40 unneback
`define MODULE pll
402
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
403
`undef MODULE
404 6 unneback
parameter index = 0;
405
parameter number_of_clk = 1;
406 17 unneback
parameter period_time_0 = 20000;
407
parameter period_time_1 = 20000;
408
parameter period_time_2 = 20000;
409
parameter lock_delay = 2000000;
410 6 unneback
input clk_i, rst_n_i;
411
output lock;
412
output reg [0:number_of_clk-1] clk_o;
413
output [0:number_of_clk-1] rst_o;
414
 
415
`ifdef SIM_PLL
416
 
417
always
418
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
419
 
420
generate if (number_of_clk > 1)
421
always
422
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
423
endgenerate
424
 
425
generate if (number_of_clk > 2)
426
always
427
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
428
endgenerate
429
 
430
genvar i;
431
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
432
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
433
end
434
endgenerate
435
 
436
assign #lock_delay lock = rst_n_i;
437
 
438
endmodule
439
`else
440
generate if (number_of_clk==1 & index==0) begin
441
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
442
end
443
endgenerate // index==0
444
generate if (number_of_clk==1 & index==1) begin
445
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
446
end
447
endgenerate // index==1
448
generate if (number_of_clk==1 & index==2) begin
449
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
450
end
451
endgenerate // index==2
452
generate if (number_of_clk==1 & index==3) begin
453
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
454
end
455
endgenerate // index==0
456
 
457
generate if (number_of_clk==2 & index==0) begin
458
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
459
end
460
endgenerate // index==0
461
generate if (number_of_clk==2 & index==1) begin
462
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
463
end
464
endgenerate // index==1
465
generate if (number_of_clk==2 & index==2) begin
466
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
467
end
468
endgenerate // index==2
469
generate if (number_of_clk==2 & index==3) begin
470
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
471
end
472
endgenerate // index==0
473
 
474
generate if (number_of_clk==3 & index==0) begin
475
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
476
end
477
endgenerate // index==0
478
generate if (number_of_clk==3 & index==1) begin
479
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
480
end
481
endgenerate // index==1
482
generate if (number_of_clk==3 & index==2) begin
483
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
484
end
485
endgenerate // index==2
486
generate if (number_of_clk==3 & index==3) begin
487
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
488
end
489
endgenerate // index==0
490
 
491
genvar i;
492
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
493 40 unneback
`define MODULE sync_rst
494
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
495
`undef MODULE
496 6 unneback
end
497
endgenerate
498
endmodule
499
`endif
500 32 unneback
///////////////////////////////////////////////////////////////////////////////
501 6 unneback
 
502
`else
503
 
504 32 unneback
///////////////////////////////////////////////////////////////////////////////
505 6 unneback
`ifdef ALTERA
506
 
507 32 unneback
`timescale 1 ps/1 ps
508 40 unneback
`define MODULE pll
509
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
510
`undef MODULE
511 32 unneback
parameter index = 0;
512
parameter number_of_clk = 1;
513
parameter period_time_0 = 20000;
514
parameter period_time_1 = 20000;
515
parameter period_time_2 = 20000;
516
parameter period_time_3 = 20000;
517
parameter period_time_4 = 20000;
518
parameter lock_delay = 2000000;
519
input clk_i, rst_n_i;
520
output lock;
521
output reg [0:number_of_clk-1] clk_o;
522
output [0:number_of_clk-1] rst_o;
523
 
524
`ifdef SIM_PLL
525
 
526
always
527
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
528
 
529
generate if (number_of_clk > 1)
530
always
531
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
532
endgenerate
533
 
534
generate if (number_of_clk > 2)
535
always
536
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
537
endgenerate
538
 
539 33 unneback
generate if (number_of_clk > 3)
540 32 unneback
always
541
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
542
endgenerate
543
 
544 33 unneback
generate if (number_of_clk > 4)
545 32 unneback
always
546
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
547
endgenerate
548
 
549
genvar i;
550
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
551
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
552
end
553
endgenerate
554
 
555 33 unneback
//assign #lock_delay lock = rst_n_i;
556
assign lock = rst_n_i;
557 32 unneback
 
558
endmodule
559 6 unneback
`else
560
 
561 33 unneback
`ifdef VL_PLL0
562
`ifdef VL_PLL0_CLK1
563
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
564
`endif
565
`ifdef VL_PLL0_CLK2
566
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
567
`endif
568
`ifdef VL_PLL0_CLK3
569
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
570
`endif
571
`ifdef VL_PLL0_CLK4
572
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
573
`endif
574
`ifdef VL_PLL0_CLK5
575
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
576
`endif
577
`endif
578 32 unneback
 
579 33 unneback
`ifdef VL_PLL1
580
`ifdef VL_PLL1_CLK1
581
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
582
`endif
583
`ifdef VL_PLL1_CLK2
584
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
585
`endif
586
`ifdef VL_PLL1_CLK3
587
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
588
`endif
589
`ifdef VL_PLL1_CLK4
590
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
591
`endif
592
`ifdef VL_PLL1_CLK5
593
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
594
`endif
595
`endif
596 32 unneback
 
597 33 unneback
`ifdef VL_PLL2
598
`ifdef VL_PLL2_CLK1
599
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
600
`endif
601
`ifdef VL_PLL2_CLK2
602
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
603
`endif
604
`ifdef VL_PLL2_CLK3
605
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
606
`endif
607
`ifdef VL_PLL2_CLK4
608
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
609
`endif
610
`ifdef VL_PLL2_CLK5
611
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
612
`endif
613
`endif
614 32 unneback
 
615 33 unneback
`ifdef VL_PLL3
616
`ifdef VL_PLL3_CLK1
617
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
618
`endif
619
`ifdef VL_PLL3_CLK2
620
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
621
`endif
622
`ifdef VL_PLL3_CLK3
623
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
624
`endif
625
`ifdef VL_PLL3_CLK4
626
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
627
`endif
628
`ifdef VL_PLL3_CLK5
629
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
630
`endif
631
`endif
632 32 unneback
 
633
genvar i;
634
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
635 40 unneback
`define MODULE sync_rst
636
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
637
`undef MODULE
638 32 unneback
end
639
endgenerate
640
endmodule
641
`endif
642
///////////////////////////////////////////////////////////////////////////////
643
 
644
`else
645
 
646 6 unneback
// generic PLL
647 17 unneback
`timescale 1 ps/1 ps
648 40 unneback
`define MODULE pll
649
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
650
`undef MODULE
651 6 unneback
parameter index = 0;
652
parameter number_of_clk = 1;
653 17 unneback
parameter period_time_0 = 20000;
654
parameter period_time_1 = 20000;
655
parameter period_time_2 = 20000;
656 6 unneback
parameter lock_delay = 2000;
657
input clk_i, rst_n_i;
658
output lock;
659
output reg [0:number_of_clk-1] clk_o;
660
output [0:number_of_clk-1] rst_o;
661
 
662
always
663
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
664
 
665
generate if (number_of_clk > 1)
666
always
667
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
668
endgenerate
669
 
670
generate if (number_of_clk > 2)
671
always
672
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
673
endgenerate
674
 
675
genvar i;
676
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
677 40 unneback
`define MODULE sync_rst
678
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
679
`undef MODULE
680 6 unneback
end
681
endgenerate
682
 
683
assign #lock_delay lock = rst_n_i;
684
 
685
endmodule
686
 
687
`endif //altera
688 17 unneback
`endif //actel
689 40 unneback
`undef MODULE
690
`endif//////////////////////////////////////////////////////////////////////
691 6 unneback
////                                                              ////
692
////  Versatile library, registers                                ////
693
////                                                              ////
694
////  Description                                                 ////
695
////  Different type of registers                                 ////
696
////                                                              ////
697
////                                                              ////
698
////  To Do:                                                      ////
699
////   - add more different registers                             ////
700
////                                                              ////
701
////  Author(s):                                                  ////
702
////      - Michael Unneback, unneback@opencores.org              ////
703
////        ORSoC AB                                              ////
704
////                                                              ////
705
//////////////////////////////////////////////////////////////////////
706
////                                                              ////
707
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
708
////                                                              ////
709
//// This source file may be used and distributed without         ////
710
//// restriction provided that this copyright statement is not    ////
711
//// removed from the file and that any derivative work contains  ////
712
//// the original copyright notice and the associated disclaimer. ////
713
////                                                              ////
714
//// This source file is free software; you can redistribute it   ////
715
//// and/or modify it under the terms of the GNU Lesser General   ////
716
//// Public License as published by the Free Software Foundation; ////
717
//// either version 2.1 of the License, or (at your option) any   ////
718
//// later version.                                               ////
719
////                                                              ////
720
//// This source is distributed in the hope that it will be       ////
721
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
722
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
723
//// PURPOSE.  See the GNU Lesser General Public License for more ////
724
//// details.                                                     ////
725
////                                                              ////
726
//// You should have received a copy of the GNU Lesser General    ////
727
//// Public License along with this source; if not, download it   ////
728
//// from http://www.opencores.org/lgpl.shtml                     ////
729
////                                                              ////
730
//////////////////////////////////////////////////////////////////////
731
 
732 40 unneback
`ifdef DFF
733
`define MODULE dff
734
module `BASE`MODULE ( d, q, clk, rst);
735
`undef MODULE
736 6 unneback
        parameter width = 1;
737
        parameter reset_value = 0;
738
 
739
        input [width-1:0] d;
740
        input clk, rst;
741
        output reg [width-1:0] q;
742
 
743
        always @ (posedge clk or posedge rst)
744
        if (rst)
745
                q <= reset_value;
746
        else
747
                q <= d;
748
 
749
endmodule
750 40 unneback
`endif
751 6 unneback
 
752 40 unneback
`ifdef DFF_ARRAY
753
`define MODULE dff_array
754
module `BASE`MODULE ( d, q, clk, rst);
755
`undef MODULE
756 6 unneback
 
757
        parameter width = 1;
758
        parameter depth = 2;
759
        parameter reset_value = 1'b0;
760
 
761
        input [width-1:0] d;
762
        input clk, rst;
763
        output [width-1:0] q;
764
        reg  [0:depth-1] q_tmp [width-1:0];
765
        integer i;
766
        always @ (posedge clk or posedge rst)
767
        if (rst) begin
768
            for (i=0;i<depth;i=i+1)
769
                q_tmp[i] <= {width{reset_value}};
770
        end else begin
771
            q_tmp[0] <= d;
772
            for (i=1;i<depth;i=i+1)
773
                q_tmp[i] <= q_tmp[i-1];
774
        end
775
 
776
    assign q = q_tmp[depth-1];
777
 
778
endmodule
779 40 unneback
`endif
780 6 unneback
 
781 40 unneback
`ifdef DFF_CE
782
`define MODULE dff_ce
783
module `BASE`MODULE ( d, ce, q, clk, rst);
784
`undef MODULE
785 6 unneback
 
786
        parameter width = 1;
787
        parameter reset_value = 0;
788
 
789
        input [width-1:0] d;
790
        input ce, clk, rst;
791
        output reg [width-1:0] q;
792
 
793
        always @ (posedge clk or posedge rst)
794
        if (rst)
795
                q <= reset_value;
796
        else
797
                if (ce)
798
                        q <= d;
799
 
800
endmodule
801 40 unneback
`endif
802 6 unneback
 
803 40 unneback
`ifdef DFF_CE_CLEAR
804
`define MODULE dff_ce_clear
805
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
806
`undef MODULE
807 8 unneback
 
808
        parameter width = 1;
809
        parameter reset_value = 0;
810
 
811
        input [width-1:0] d;
812 10 unneback
        input ce, clear, clk, rst;
813 8 unneback
        output reg [width-1:0] q;
814
 
815
        always @ (posedge clk or posedge rst)
816
        if (rst)
817
            q <= reset_value;
818
        else
819
            if (ce)
820
                if (clear)
821
                    q <= {width{1'b0}};
822
                else
823
                    q <= d;
824
 
825
endmodule
826 40 unneback
`endif
827 8 unneback
 
828 40 unneback
`ifdef DF_CE_SET
829
`define MODULE dff_ce_set
830
module `BASE`MODULE ( d, ce, set, q, clk, rst);
831
`undef MODULE
832 24 unneback
 
833
        parameter width = 1;
834
        parameter reset_value = 0;
835
 
836
        input [width-1:0] d;
837
        input ce, set, clk, rst;
838
        output reg [width-1:0] q;
839
 
840
        always @ (posedge clk or posedge rst)
841
        if (rst)
842
            q <= reset_value;
843
        else
844
            if (ce)
845
                if (set)
846
                    q <= {width{1'b1}};
847
                else
848
                    q <= d;
849
 
850
endmodule
851 40 unneback
`endif
852 24 unneback
 
853 40 unneback
`ifdef SPR
854
`define MODULE spr
855
module `BASE`MODULE ( sp, r, q, clk, rst);
856
`undef MODULE
857
 
858 64 unneback
        //parameter width = 1;
859
        parameter reset_value = 1'b0;
860 29 unneback
 
861
        input sp, r;
862
        output reg q;
863
        input clk, rst;
864
 
865
        always @ (posedge clk or posedge rst)
866
        if (rst)
867
            q <= reset_value;
868
        else
869
            if (sp)
870
                q <= 1'b1;
871
            else if (r)
872
                q <= 1'b0;
873
 
874
endmodule
875 40 unneback
`endif
876 29 unneback
 
877 40 unneback
`ifdef SRP
878
`define MODULE srp
879
module `BASE`MODULE ( s, rp, q, clk, rst);
880
`undef MODULE
881
 
882 29 unneback
        parameter width = 1;
883
        parameter reset_value = 0;
884
 
885
        input s, rp;
886
        output reg q;
887
        input clk, rst;
888
 
889
        always @ (posedge clk or posedge rst)
890
        if (rst)
891
            q <= reset_value;
892
        else
893
            if (rp)
894
                q <= 1'b0;
895
            else if (s)
896
                q <= 1'b1;
897
 
898
endmodule
899 40 unneback
`endif
900 29 unneback
 
901 40 unneback
`ifdef ALTERA
902 29 unneback
 
903 40 unneback
`ifdef DFF_SR
904 6 unneback
// megafunction wizard: %LPM_FF%
905
// GENERATION: STANDARD
906
// VERSION: WM1.0
907
// MODULE: lpm_ff 
908
 
909
// ============================================================
910
// File Name: dff_sr.v
911
// Megafunction Name(s):
912
//                      lpm_ff
913
//
914
// Simulation Library Files(s):
915
//                      lpm
916
// ============================================================
917
// ************************************************************
918
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
919
//
920
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
921
// ************************************************************
922
 
923
 
924
//Copyright (C) 1991-2010 Altera Corporation
925
//Your use of Altera Corporation's design tools, logic functions 
926
//and other software and tools, and its AMPP partner logic 
927
//functions, and any output files from any of the foregoing 
928
//(including device programming or simulation files), and any 
929
//associated documentation or information are expressly subject 
930
//to the terms and conditions of the Altera Program License 
931
//Subscription Agreement, Altera MegaCore Function License 
932
//Agreement, or other applicable license agreement, including, 
933
//without limitation, that your use is for the sole purpose of 
934
//programming logic devices manufactured by Altera and sold by 
935
//Altera or its authorized distributors.  Please refer to the 
936
//applicable agreement for further details.
937
 
938
 
939
// synopsys translate_off
940
`timescale 1 ps / 1 ps
941
// synopsys translate_on
942 40 unneback
`define MODULE dff_sr
943
module `BASE`MODULE (
944
`undef MODULE
945
 
946 6 unneback
        aclr,
947
        aset,
948
        clock,
949
        data,
950
        q);
951
 
952
        input     aclr;
953
        input     aset;
954
        input     clock;
955
        input     data;
956
        output    q;
957
 
958
        wire [0:0] sub_wire0;
959
        wire [0:0] sub_wire1 = sub_wire0[0:0];
960
        wire  q = sub_wire1;
961
        wire  sub_wire2 = data;
962
        wire  sub_wire3 = sub_wire2;
963
 
964
        lpm_ff  lpm_ff_component (
965
                                .aclr (aclr),
966
                                .clock (clock),
967
                                .data (sub_wire3),
968
                                .aset (aset),
969
                                .q (sub_wire0)
970
                                // synopsys translate_off
971
                                ,
972
                                .aload (),
973
                                .enable (),
974
                                .sclr (),
975
                                .sload (),
976
                                .sset ()
977
                                // synopsys translate_on
978
                                );
979
        defparam
980
                lpm_ff_component.lpm_fftype = "DFF",
981
                lpm_ff_component.lpm_type = "LPM_FF",
982
                lpm_ff_component.lpm_width = 1;
983
 
984
 
985
endmodule
986
 
987
// ============================================================
988
// CNX file retrieval info
989
// ============================================================
990
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
991
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
992
// Retrieval info: PRIVATE: ASET NUMERIC "1"
993
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
994
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
995
// Retrieval info: PRIVATE: DFF NUMERIC "1"
996
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
997
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
998
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
999
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1000
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1001
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1002
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1003
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1004
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1005
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1006
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1007
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1008
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1009
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1010
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1011
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1012
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1013
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1014
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1015
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1016
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1017
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1018
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1019
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1020
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1021
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1022
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1023
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1024
// Retrieval info: LIB_FILE: lpm
1025 40 unneback
`endif
1026 6 unneback
 
1027
`else
1028
 
1029 40 unneback
`ifdef DFF_SR
1030
`define MODULE dff_sr
1031
module `BASE`MODULE ( aclr, aset, clock, data, q);
1032
`undef MODULE
1033 6 unneback
 
1034
    input         aclr;
1035
    input         aset;
1036
    input         clock;
1037
    input         data;
1038
    output reg    q;
1039
 
1040
   always @ (posedge clock or posedge aclr or posedge aset)
1041
     if (aclr)
1042
       q <= 1'b0;
1043
     else if (aset)
1044
       q <= 1'b1;
1045
     else
1046
       q <= data;
1047
 
1048
endmodule
1049 40 unneback
`endif
1050 6 unneback
 
1051
`endif
1052
 
1053
// LATCH
1054
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1055
`ifdef ALTERA
1056 40 unneback
 
1057
`ifdef LATCH
1058
`define MODULE latch
1059
module `BASE`MODULE ( d, le, q, clk);
1060
`undef MODULE
1061 6 unneback
input d, le;
1062
output q;
1063
input clk;
1064
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1065
endmodule
1066 40 unneback
`endif
1067
 
1068 6 unneback
`else
1069 40 unneback
 
1070
`ifdef LATCH
1071
`define MODULE latch
1072
module `BASE`MODULE ( d, le, q, clk);
1073
`undef MODULE
1074 6 unneback
input d, le;
1075 48 unneback
input clk;
1076
always @ (le or d)
1077 60 unneback
if (le)
1078 48 unneback
    d <= q;
1079 6 unneback
endmodule
1080 15 unneback
`endif
1081
 
1082 40 unneback
`endif
1083
 
1084
`ifdef SHREG
1085
`define MODULE shreg
1086
module `BASE`MODULE ( d, q, clk, rst);
1087
`undef MODULE
1088
 
1089 17 unneback
parameter depth = 10;
1090
input d;
1091
output q;
1092
input clk, rst;
1093
 
1094
reg [1:depth] dffs;
1095
 
1096
always @ (posedge clk or posedge rst)
1097
if (rst)
1098
    dffs <= {depth{1'b0}};
1099
else
1100
    dffs <= {d,dffs[1:depth-1]};
1101
assign q = dffs[depth];
1102
endmodule
1103 40 unneback
`endif
1104 17 unneback
 
1105 40 unneback
`ifdef SHREG_CE
1106
`define MODULE shreg_ce
1107
module `BASE`MODULE ( d, ce, q, clk, rst);
1108
`undef MODULE
1109 17 unneback
parameter depth = 10;
1110
input d, ce;
1111
output q;
1112
input clk, rst;
1113
 
1114
reg [1:depth] dffs;
1115
 
1116
always @ (posedge clk or posedge rst)
1117
if (rst)
1118
    dffs <= {depth{1'b0}};
1119
else
1120
    if (ce)
1121
        dffs <= {d,dffs[1:depth-1]};
1122
assign q = dffs[depth];
1123
endmodule
1124 40 unneback
`endif
1125 17 unneback
 
1126 40 unneback
`ifdef DELAY
1127
`define MODULE delay
1128
module `BASE`MODULE ( d, q, clk, rst);
1129
`undef MODULE
1130 15 unneback
parameter depth = 10;
1131
input d;
1132
output q;
1133
input clk, rst;
1134
 
1135
reg [1:depth] dffs;
1136
 
1137
always @ (posedge clk or posedge rst)
1138
if (rst)
1139
    dffs <= {depth{1'b0}};
1140
else
1141
    dffs <= {d,dffs[1:depth-1]};
1142
assign q = dffs[depth];
1143 17 unneback
endmodule
1144 40 unneback
`endif
1145 17 unneback
 
1146 40 unneback
`ifdef DELAY_EMPTYFLAG
1147
`define MODULE delay_emptyflag
1148 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1149 40 unneback
`undef MODULE
1150 17 unneback
parameter depth = 10;
1151
input d;
1152
output q, emptyflag;
1153
input clk, rst;
1154
 
1155
reg [1:depth] dffs;
1156
 
1157
always @ (posedge clk or posedge rst)
1158
if (rst)
1159
    dffs <= {depth{1'b0}};
1160
else
1161
    dffs <= {d,dffs[1:depth-1]};
1162
assign q = dffs[depth];
1163
assign emptyflag = !(|dffs);
1164
endmodule
1165 40 unneback
`endif
1166 75 unneback
 
1167 94 unneback
`ifdef PULSE2TOGGLE
1168
`define MODULE pules2toggle
1169
module `BASE`MODULE ( pl, q, clk, rst)
1170 75 unneback
`undef MODULE
1171 94 unneback
input pl;
1172
output q;
1173
input clk, rst;
1174
input
1175
always @ (posedge clk or posedge rst)
1176 75 unneback
if (rst)
1177 94 unneback
    q <= 1'b0;
1178 75 unneback
else
1179 94 unneback
    q <= pl ^ q;
1180
endmodule
1181
`endif
1182 75 unneback
 
1183 94 unneback
`ifdef TOGGLE2PULSE
1184
`define MODULE toggle2pulse;
1185
module `BASE`MODULE (d, pl, clk, rst);
1186
input d;
1187
output pl;
1188
input clk, rst;
1189
reg dff;
1190
always @ (posedge clk or posedge rst)
1191
if (rst)
1192
    dff <= 1'b0;
1193 75 unneback
else
1194 94 unneback
    dff <= d;
1195
assign d ^ dff;
1196
endmodule
1197
`endif
1198 75 unneback
 
1199 94 unneback
`ifdef SYNCHRONIZER
1200
`define MODULE synchronizer
1201
module `BASE`MODULE (d, q, clk, rst);
1202
`undef MODULE
1203
input d;
1204
output reg q;
1205
output clk, rst;
1206
reg dff;
1207
always @ (posedge clk or posedge rst)
1208
if (rst)
1209
    {dff,q} <= 2'b00;
1210 75 unneback
else
1211 94 unneback
    {dff,q} <= {d,dff};
1212
endmodule
1213
`endif
1214 75 unneback
 
1215 94 unneback
`ifdef CDC
1216
`define MODULE cdc
1217
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst)
1218
`undef MODULE
1219
input start_pl;
1220
output take_it_pl;
1221
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1222
output got_it_pl;
1223
input clk_src, rst_src;
1224
input clk_dst, rst_dst;
1225
wire take_it_tg, take_it_tg_sync;
1226
wire got_it_tg, got_it_tg_sync;
1227
// src -> dst
1228
`define MODULE pulse2toggle
1229
`BASE`MODULE p2t0 (
1230
`undef MODULE
1231
    .pl(start_pl),
1232
    .q(take_it_tg),
1233
    .clk(clk_src),
1234
    .rst(rst_src));
1235 75 unneback
 
1236 94 unneback
`define MODULE synchronizer
1237
`BASE`MODULE sync0 (
1238
`undef MODULE
1239
    .d(take_it_tg),
1240
    .q(take_it_tg_sync),
1241
    .clk(clk_dst),
1242
    .rst(rst_dst));
1243
 
1244
`define MODULE toggle2pulse
1245
`BASE`MODULE t2p0 (
1246
`undef MODULE
1247
    .d(take_it_sync),
1248
    .pl(take_it_pl),
1249
    .clk(clk_dst),
1250
    .rst(rst_dst));
1251
 
1252
// dst -> src
1253
`define MODULE pulse2toggle
1254
`BASE`MODULE p2t0 (
1255
`undef MODULE
1256
    .pl(take_it_grant_pl),
1257
    .q(got_it_tg),
1258
    .clk(clk_dst),
1259
    .rst(rst_dst));
1260
 
1261
`define MODULE synchronizer
1262
`BASE`MODULE sync1 (
1263
`undef MODULE
1264
    .d(got_it_tg),
1265
    .q(got_it_tg_sync),
1266
    .clk(clk_src),
1267
    .rst(rst_src));
1268
 
1269
`define MODULE toggle2pulse
1270
`BASE`MODULE t2p1 (
1271
`undef MODULE
1272
    .d(take_it_grant_tg_sync),
1273
    .pl(got_it_pl),
1274
    .clk(clk_src),
1275
    .rst(rst_src));
1276
 
1277 75 unneback
endmodule
1278
`endif
1279 17 unneback
//////////////////////////////////////////////////////////////////////
1280 6 unneback
////                                                              ////
1281 18 unneback
////  Logic functions                                             ////
1282
////                                                              ////
1283
////  Description                                                 ////
1284
////  Logic functions such as multiplexers                        ////
1285
////                                                              ////
1286
////                                                              ////
1287
////  To Do:                                                      ////
1288
////   -                                                          ////
1289
////                                                              ////
1290
////  Author(s):                                                  ////
1291
////      - Michael Unneback, unneback@opencores.org              ////
1292
////        ORSoC AB                                              ////
1293
////                                                              ////
1294
//////////////////////////////////////////////////////////////////////
1295
////                                                              ////
1296
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1297
////                                                              ////
1298
//// This source file may be used and distributed without         ////
1299
//// restriction provided that this copyright statement is not    ////
1300
//// removed from the file and that any derivative work contains  ////
1301
//// the original copyright notice and the associated disclaimer. ////
1302
////                                                              ////
1303
//// This source file is free software; you can redistribute it   ////
1304
//// and/or modify it under the terms of the GNU Lesser General   ////
1305
//// Public License as published by the Free Software Foundation; ////
1306
//// either version 2.1 of the License, or (at your option) any   ////
1307
//// later version.                                               ////
1308
////                                                              ////
1309
//// This source is distributed in the hope that it will be       ////
1310
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1311
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1312
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1313
//// details.                                                     ////
1314
////                                                              ////
1315
//// You should have received a copy of the GNU Lesser General    ////
1316
//// Public License along with this source; if not, download it   ////
1317
//// from http://www.opencores.org/lgpl.shtml                     ////
1318
////                                                              ////
1319
//////////////////////////////////////////////////////////////////////
1320 40 unneback
`ifdef MUX_ANDOR
1321
`define MODULE mux_andor
1322
module `BASE`MODULE ( a, sel, dout);
1323
`undef MODULE
1324 36 unneback
 
1325
parameter width = 32;
1326
parameter nr_of_ports = 4;
1327
 
1328
input [nr_of_ports*width-1:0] a;
1329
input [nr_of_ports-1:0] sel;
1330
output reg [width-1:0] dout;
1331
 
1332 38 unneback
integer i,j;
1333
 
1334 36 unneback
always @ (a, sel)
1335
begin
1336
    dout = a[width-1:0] & {width{sel[0]}};
1337 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1338
        for (j=0;j<width;j=j+1)
1339
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1340 36 unneback
end
1341
 
1342
endmodule
1343 40 unneback
`endif
1344 36 unneback
 
1345 40 unneback
`ifdef MUX2_ANDOR
1346
`define MODULE mux2_andor
1347
module `BASE`MODULE ( a1, a0, sel, dout);
1348
`undef MODULE
1349 18 unneback
 
1350 34 unneback
parameter width = 32;
1351 35 unneback
localparam nr_of_ports = 2;
1352 34 unneback
input [width-1:0] a1, a0;
1353
input [nr_of_ports-1:0] sel;
1354
output [width-1:0] dout;
1355
 
1356 40 unneback
`define MODULE mux_andor
1357
`BASE`MODULE
1358 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1359 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1360 40 unneback
`undef MODULE
1361
 
1362 34 unneback
endmodule
1363 40 unneback
`endif
1364 34 unneback
 
1365 40 unneback
`ifdef MUX3_ANDOR
1366
`define MODULE mux3_andor
1367
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1368
`undef MODULE
1369 34 unneback
 
1370
parameter width = 32;
1371 35 unneback
localparam nr_of_ports = 3;
1372 34 unneback
input [width-1:0] a2, a1, a0;
1373
input [nr_of_ports-1:0] sel;
1374
output [width-1:0] dout;
1375
 
1376 40 unneback
`define MODULE mux_andor
1377
`BASE`MODULE
1378 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1379 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1380 40 unneback
`undef MODULE
1381 34 unneback
endmodule
1382 40 unneback
`endif
1383 34 unneback
 
1384 40 unneback
`ifdef MUX4_ANDOR
1385
`define MODULE mux4_andor
1386
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1387
`undef MODULE
1388 18 unneback
 
1389
parameter width = 32;
1390 35 unneback
localparam nr_of_ports = 4;
1391 18 unneback
input [width-1:0] a3, a2, a1, a0;
1392
input [nr_of_ports-1:0] sel;
1393 22 unneback
output [width-1:0] dout;
1394 18 unneback
 
1395 40 unneback
`define MODULE mux_andor
1396
`BASE`MODULE
1397 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1398 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1399 40 unneback
`undef MODULE
1400 18 unneback
 
1401
endmodule
1402 40 unneback
`endif
1403 18 unneback
 
1404 40 unneback
`ifdef MUX5_ANDOR
1405
`define MODULE mux5_andor
1406
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1407
`undef MODULE
1408 18 unneback
 
1409
parameter width = 32;
1410 35 unneback
localparam nr_of_ports = 5;
1411 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1412
input [nr_of_ports-1:0] sel;
1413 22 unneback
output [width-1:0] dout;
1414 18 unneback
 
1415 40 unneback
`define MODULE mux_andor
1416
`BASE`MODULE
1417 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1418 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1419 40 unneback
`undef MODULE
1420 18 unneback
 
1421
endmodule
1422 40 unneback
`endif
1423 18 unneback
 
1424 40 unneback
`ifdef MUX6_ANDOR
1425
`define MODULE mux6_andor
1426
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1427
`undef MODULE
1428 18 unneback
 
1429
parameter width = 32;
1430 35 unneback
localparam nr_of_ports = 6;
1431 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1432
input [nr_of_ports-1:0] sel;
1433 22 unneback
output [width-1:0] dout;
1434 18 unneback
 
1435 40 unneback
`define MODULE mux_andor
1436
`BASE`MODULE
1437 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1438 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1439 40 unneback
`undef MODULE
1440 18 unneback
 
1441
endmodule
1442 40 unneback
`endif
1443 43 unneback
 
1444
`ifdef PARITY
1445
 
1446
`define MODULE parity_generate
1447
module `BASE`MODULE (data, parity);
1448
`undef MODULE
1449
parameter word_size = 32;
1450
parameter chunk_size = 8;
1451
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1452
input [word_size-1:0] data;
1453
output reg [word_size/chunk_size-1:0] parity;
1454
integer i,j;
1455
always @ (data)
1456
for (i=0;i<word_size/chunk_size;i=i+1) begin
1457
    parity[i] = parity_type;
1458
    for (j=0;j<chunk_size;j=j+1) begin
1459 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1460 43 unneback
    end
1461
end
1462
endmodule
1463
 
1464
`define MODULE parity_check
1465
module `BASE`MODULE( data, parity, parity_error);
1466
`undef MODULE
1467
parameter word_size = 32;
1468
parameter chunk_size = 8;
1469
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1470
input [word_size-1:0] data;
1471
input [word_size/chunk_size-1:0] parity;
1472
output parity_error;
1473 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1474 43 unneback
integer i,j;
1475
always @ (data or parity)
1476
for (i=0;i<word_size/chunk_size;i=i+1) begin
1477
    error_flag[i] = parity[i] ^ parity_type;
1478
    for (j=0;j<chunk_size;j=j+1) begin
1479 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1480 43 unneback
    end
1481
end
1482
assign parity_error = |error_flag;
1483
endmodule
1484
 
1485 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1486
////                                                              ////
1487
////  IO functions                                                ////
1488
////                                                              ////
1489
////  Description                                                 ////
1490
////  IO functions such as IOB flip-flops                         ////
1491
////                                                              ////
1492
////                                                              ////
1493
////  To Do:                                                      ////
1494
////   -                                                          ////
1495
////                                                              ////
1496
////  Author(s):                                                  ////
1497
////      - Michael Unneback, unneback@opencores.org              ////
1498
////        ORSoC AB                                              ////
1499
////                                                              ////
1500 18 unneback
//////////////////////////////////////////////////////////////////////
1501
////                                                              ////
1502 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1503
////                                                              ////
1504
//// This source file may be used and distributed without         ////
1505
//// restriction provided that this copyright statement is not    ////
1506
//// removed from the file and that any derivative work contains  ////
1507
//// the original copyright notice and the associated disclaimer. ////
1508
////                                                              ////
1509
//// This source file is free software; you can redistribute it   ////
1510
//// and/or modify it under the terms of the GNU Lesser General   ////
1511
//// Public License as published by the Free Software Foundation; ////
1512
//// either version 2.1 of the License, or (at your option) any   ////
1513
//// later version.                                               ////
1514
////                                                              ////
1515
//// This source is distributed in the hope that it will be       ////
1516
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1517
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1518
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1519
//// details.                                                     ////
1520
////                                                              ////
1521
//// You should have received a copy of the GNU Lesser General    ////
1522
//// Public License along with this source; if not, download it   ////
1523
//// from http://www.opencores.org/lgpl.shtml                     ////
1524
////                                                              ////
1525
//////////////////////////////////////////////////////////////////////
1526 45 unneback
`timescale 1ns/1ns
1527 44 unneback
`ifdef O_DFF
1528
`define MODULE o_dff
1529
module `BASE`MODULE (d_i, o_pad, clk, rst);
1530
`undef MODULE
1531
parameter width = 1;
1532 45 unneback
parameter reset_value = {width{1'b0}};
1533
input  [width-1:0]  d_i;
1534 44 unneback
output [width-1:0] o_pad;
1535
input clk, rst;
1536
wire [width-1:0] d_i_int `SYN_KEEP;
1537 45 unneback
reg  [width-1:0] o_pad_int;
1538 44 unneback
assign d_i_int = d_i;
1539
genvar i;
1540 45 unneback
generate
1541 44 unneback
for (i=0;i<width;i=i+1) begin
1542
    always @ (posedge clk or posedge rst)
1543
    if (rst)
1544 45 unneback
        o_pad_int[i] <= reset_value[i];
1545 44 unneback
    else
1546 45 unneback
        o_pad_int[i] <= d_i_int[i];
1547
    assign #1 o_pad[i] = o_pad_int[i];
1548 44 unneback
end
1549
endgenerate
1550
endmodule
1551
`endif
1552
 
1553 45 unneback
`timescale 1ns/1ns
1554 44 unneback
`ifdef IO_DFF_OE
1555
`define MODULE io_dff_oe
1556
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1557
`undef MODULE
1558
parameter width = 1;
1559
input  [width-1:0] d_o;
1560
output reg [width-1:0] d_i;
1561
input oe;
1562
inout [width-1:0] io_pad;
1563
input clk, rst;
1564
wire [width-1:0] oe_d `SYN_KEEP;
1565
reg [width-1:0] oe_q;
1566
reg [width-1:0] d_o_q;
1567
assign oe_d = {width{oe}};
1568
genvar i;
1569
generate
1570
for (i=0;i<width;i=i+1) begin
1571
    always @ (posedge clk or posedge rst)
1572
    if (rst)
1573
        oe_q[i] <= 1'b0;
1574
    else
1575
        oe_q[i] <= oe_d[i];
1576
    always @ (posedge clk or posedge rst)
1577
    if (rst)
1578
        d_o_q[i] <= 1'b0;
1579
    else
1580
        d_o_q[i] <= d_o[i];
1581
    always @ (posedge clk or posedge rst)
1582
    if (rst)
1583
        d_i[i] <= 1'b0;
1584
    else
1585
        d_i[i] <= io_pad[i];
1586 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1587 44 unneback
end
1588
endgenerate
1589
endmodule
1590
`endif
1591
`ifdef CNT_BIN
1592
//////////////////////////////////////////////////////////////////////
1593
////                                                              ////
1594 6 unneback
////  Versatile counter                                           ////
1595
////                                                              ////
1596
////  Description                                                 ////
1597
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1598
////  counter                                                     ////
1599
////                                                              ////
1600
////  To Do:                                                      ////
1601
////   - add LFSR with more taps                                  ////
1602
////                                                              ////
1603
////  Author(s):                                                  ////
1604
////      - Michael Unneback, unneback@opencores.org              ////
1605
////        ORSoC AB                                              ////
1606
////                                                              ////
1607
//////////////////////////////////////////////////////////////////////
1608
////                                                              ////
1609
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1610
////                                                              ////
1611
//// This source file may be used and distributed without         ////
1612
//// restriction provided that this copyright statement is not    ////
1613
//// removed from the file and that any derivative work contains  ////
1614
//// the original copyright notice and the associated disclaimer. ////
1615
////                                                              ////
1616
//// This source file is free software; you can redistribute it   ////
1617
//// and/or modify it under the terms of the GNU Lesser General   ////
1618
//// Public License as published by the Free Software Foundation; ////
1619
//// either version 2.1 of the License, or (at your option) any   ////
1620
//// later version.                                               ////
1621
////                                                              ////
1622
//// This source is distributed in the hope that it will be       ////
1623
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1624
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1625
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1626
//// details.                                                     ////
1627
////                                                              ////
1628
//// You should have received a copy of the GNU Lesser General    ////
1629
//// Public License along with this source; if not, download it   ////
1630
//// from http://www.opencores.org/lgpl.shtml                     ////
1631
////                                                              ////
1632
//////////////////////////////////////////////////////////////////////
1633
 
1634
// binary counter
1635 22 unneback
 
1636 40 unneback
`define MODULE cnt_bin
1637
module `BASE`MODULE (
1638
`undef MODULE
1639
 q, rst, clk);
1640
 
1641 22 unneback
   parameter length = 4;
1642
   output [length:1] q;
1643
   input rst;
1644
   input clk;
1645
 
1646
   parameter clear_value = 0;
1647
   parameter set_value = 1;
1648
   parameter wrap_value = 0;
1649
   parameter level1_value = 15;
1650
 
1651
   reg  [length:1] qi;
1652
   wire [length:1] q_next;
1653
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1654
 
1655
   always @ (posedge clk or posedge rst)
1656
     if (rst)
1657
       qi <= {length{1'b0}};
1658
     else
1659
       qi <= q_next;
1660
 
1661
   assign q = qi;
1662
 
1663
endmodule
1664 40 unneback
`endif
1665
`ifdef CNT_BIN_CLEAR
1666 22 unneback
//////////////////////////////////////////////////////////////////////
1667
////                                                              ////
1668
////  Versatile counter                                           ////
1669
////                                                              ////
1670
////  Description                                                 ////
1671
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1672
////  counter                                                     ////
1673
////                                                              ////
1674
////  To Do:                                                      ////
1675
////   - add LFSR with more taps                                  ////
1676
////                                                              ////
1677
////  Author(s):                                                  ////
1678
////      - Michael Unneback, unneback@opencores.org              ////
1679
////        ORSoC AB                                              ////
1680
////                                                              ////
1681
//////////////////////////////////////////////////////////////////////
1682
////                                                              ////
1683
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1684
////                                                              ////
1685
//// This source file may be used and distributed without         ////
1686
//// restriction provided that this copyright statement is not    ////
1687
//// removed from the file and that any derivative work contains  ////
1688
//// the original copyright notice and the associated disclaimer. ////
1689
////                                                              ////
1690
//// This source file is free software; you can redistribute it   ////
1691
//// and/or modify it under the terms of the GNU Lesser General   ////
1692
//// Public License as published by the Free Software Foundation; ////
1693
//// either version 2.1 of the License, or (at your option) any   ////
1694
//// later version.                                               ////
1695
////                                                              ////
1696
//// This source is distributed in the hope that it will be       ////
1697
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1698
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1699
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1700
//// details.                                                     ////
1701
////                                                              ////
1702
//// You should have received a copy of the GNU Lesser General    ////
1703
//// Public License along with this source; if not, download it   ////
1704
//// from http://www.opencores.org/lgpl.shtml                     ////
1705
////                                                              ////
1706
//////////////////////////////////////////////////////////////////////
1707
 
1708
// binary counter
1709
 
1710 40 unneback
`define MODULE cnt_bin_clear
1711
module `BASE`MODULE (
1712
`undef MODULE
1713
 clear, q, rst, clk);
1714
 
1715 22 unneback
   parameter length = 4;
1716
   input clear;
1717
   output [length:1] q;
1718
   input rst;
1719
   input clk;
1720
 
1721
   parameter clear_value = 0;
1722
   parameter set_value = 1;
1723
   parameter wrap_value = 0;
1724
   parameter level1_value = 15;
1725
 
1726
   reg  [length:1] qi;
1727
   wire [length:1] q_next;
1728
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1729
 
1730
   always @ (posedge clk or posedge rst)
1731
     if (rst)
1732
       qi <= {length{1'b0}};
1733
     else
1734
       qi <= q_next;
1735
 
1736
   assign q = qi;
1737
 
1738
endmodule
1739 40 unneback
`endif
1740
`ifdef CNT_BIN_CE
1741 22 unneback
//////////////////////////////////////////////////////////////////////
1742
////                                                              ////
1743
////  Versatile counter                                           ////
1744
////                                                              ////
1745
////  Description                                                 ////
1746
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1747
////  counter                                                     ////
1748
////                                                              ////
1749
////  To Do:                                                      ////
1750
////   - add LFSR with more taps                                  ////
1751
////                                                              ////
1752
////  Author(s):                                                  ////
1753
////      - Michael Unneback, unneback@opencores.org              ////
1754
////        ORSoC AB                                              ////
1755
////                                                              ////
1756
//////////////////////////////////////////////////////////////////////
1757
////                                                              ////
1758
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1759
////                                                              ////
1760
//// This source file may be used and distributed without         ////
1761
//// restriction provided that this copyright statement is not    ////
1762
//// removed from the file and that any derivative work contains  ////
1763
//// the original copyright notice and the associated disclaimer. ////
1764
////                                                              ////
1765
//// This source file is free software; you can redistribute it   ////
1766
//// and/or modify it under the terms of the GNU Lesser General   ////
1767
//// Public License as published by the Free Software Foundation; ////
1768
//// either version 2.1 of the License, or (at your option) any   ////
1769
//// later version.                                               ////
1770
////                                                              ////
1771
//// This source is distributed in the hope that it will be       ////
1772
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1773
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1774
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1775
//// details.                                                     ////
1776
////                                                              ////
1777
//// You should have received a copy of the GNU Lesser General    ////
1778
//// Public License along with this source; if not, download it   ////
1779
//// from http://www.opencores.org/lgpl.shtml                     ////
1780
////                                                              ////
1781
//////////////////////////////////////////////////////////////////////
1782
 
1783
// binary counter
1784 6 unneback
 
1785 40 unneback
`define MODULE cnt_bin_ce
1786
module `BASE`MODULE (
1787
`undef MODULE
1788
 cke, q, rst, clk);
1789
 
1790 6 unneback
   parameter length = 4;
1791
   input cke;
1792
   output [length:1] q;
1793
   input rst;
1794
   input clk;
1795
 
1796
   parameter clear_value = 0;
1797
   parameter set_value = 1;
1798
   parameter wrap_value = 0;
1799
   parameter level1_value = 15;
1800
 
1801
   reg  [length:1] qi;
1802
   wire [length:1] q_next;
1803
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1804
 
1805
   always @ (posedge clk or posedge rst)
1806
     if (rst)
1807
       qi <= {length{1'b0}};
1808
     else
1809
     if (cke)
1810
       qi <= q_next;
1811
 
1812
   assign q = qi;
1813
 
1814
endmodule
1815 40 unneback
`endif
1816
`ifdef CNT_BIN_CE_CLEAR
1817 6 unneback
//////////////////////////////////////////////////////////////////////
1818
////                                                              ////
1819
////  Versatile counter                                           ////
1820
////                                                              ////
1821
////  Description                                                 ////
1822
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1823
////  counter                                                     ////
1824
////                                                              ////
1825
////  To Do:                                                      ////
1826
////   - add LFSR with more taps                                  ////
1827
////                                                              ////
1828
////  Author(s):                                                  ////
1829
////      - Michael Unneback, unneback@opencores.org              ////
1830
////        ORSoC AB                                              ////
1831
////                                                              ////
1832
//////////////////////////////////////////////////////////////////////
1833
////                                                              ////
1834
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1835
////                                                              ////
1836
//// This source file may be used and distributed without         ////
1837
//// restriction provided that this copyright statement is not    ////
1838
//// removed from the file and that any derivative work contains  ////
1839
//// the original copyright notice and the associated disclaimer. ////
1840
////                                                              ////
1841
//// This source file is free software; you can redistribute it   ////
1842
//// and/or modify it under the terms of the GNU Lesser General   ////
1843
//// Public License as published by the Free Software Foundation; ////
1844
//// either version 2.1 of the License, or (at your option) any   ////
1845
//// later version.                                               ////
1846
////                                                              ////
1847
//// This source is distributed in the hope that it will be       ////
1848
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1849
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1850
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1851
//// details.                                                     ////
1852
////                                                              ////
1853
//// You should have received a copy of the GNU Lesser General    ////
1854
//// Public License along with this source; if not, download it   ////
1855
//// from http://www.opencores.org/lgpl.shtml                     ////
1856
////                                                              ////
1857
//////////////////////////////////////////////////////////////////////
1858
 
1859
// binary counter
1860
 
1861 40 unneback
`define MODULE cnt_bin_ce_clear
1862
module `BASE`MODULE (
1863
`undef MODULE
1864
 clear, cke, q, rst, clk);
1865
 
1866 6 unneback
   parameter length = 4;
1867
   input clear;
1868
   input cke;
1869
   output [length:1] q;
1870
   input rst;
1871
   input clk;
1872
 
1873
   parameter clear_value = 0;
1874
   parameter set_value = 1;
1875
   parameter wrap_value = 0;
1876
   parameter level1_value = 15;
1877
 
1878
   reg  [length:1] qi;
1879
   wire [length:1] q_next;
1880
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1881
 
1882
   always @ (posedge clk or posedge rst)
1883
     if (rst)
1884
       qi <= {length{1'b0}};
1885
     else
1886
     if (cke)
1887
       qi <= q_next;
1888
 
1889
   assign q = qi;
1890
 
1891
endmodule
1892 40 unneback
`endif
1893
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1894 6 unneback
//////////////////////////////////////////////////////////////////////
1895
////                                                              ////
1896
////  Versatile counter                                           ////
1897
////                                                              ////
1898
////  Description                                                 ////
1899
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1900
////  counter                                                     ////
1901
////                                                              ////
1902
////  To Do:                                                      ////
1903
////   - add LFSR with more taps                                  ////
1904
////                                                              ////
1905
////  Author(s):                                                  ////
1906
////      - Michael Unneback, unneback@opencores.org              ////
1907
////        ORSoC AB                                              ////
1908
////                                                              ////
1909
//////////////////////////////////////////////////////////////////////
1910
////                                                              ////
1911
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1912
////                                                              ////
1913
//// This source file may be used and distributed without         ////
1914
//// restriction provided that this copyright statement is not    ////
1915
//// removed from the file and that any derivative work contains  ////
1916
//// the original copyright notice and the associated disclaimer. ////
1917
////                                                              ////
1918
//// This source file is free software; you can redistribute it   ////
1919
//// and/or modify it under the terms of the GNU Lesser General   ////
1920
//// Public License as published by the Free Software Foundation; ////
1921
//// either version 2.1 of the License, or (at your option) any   ////
1922
//// later version.                                               ////
1923
////                                                              ////
1924
//// This source is distributed in the hope that it will be       ////
1925
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1926
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1927
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1928
//// details.                                                     ////
1929
////                                                              ////
1930
//// You should have received a copy of the GNU Lesser General    ////
1931
//// Public License along with this source; if not, download it   ////
1932
//// from http://www.opencores.org/lgpl.shtml                     ////
1933
////                                                              ////
1934
//////////////////////////////////////////////////////////////////////
1935
 
1936
// binary counter
1937 29 unneback
 
1938 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1939
module `BASE`MODULE (
1940
`undef MODULE
1941
 clear, cke, q, level1, level2, rst, clk);
1942
 
1943 29 unneback
   parameter length = 4;
1944
   input clear;
1945
   input cke;
1946
   output [length:1] q;
1947
   output reg level1;
1948
   output reg level2;
1949
   input rst;
1950
   input clk;
1951
 
1952
   parameter clear_value = 0;
1953
   parameter set_value = 1;
1954 30 unneback
   parameter wrap_value = 15;
1955
   parameter level1_value = 8;
1956
   parameter level2_value = 15;
1957 29 unneback
 
1958
   wire rew;
1959 30 unneback
   assign rew = 1'b0;
1960 29 unneback
   reg  [length:1] qi;
1961
   wire [length:1] q_next;
1962
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1963
 
1964
   always @ (posedge clk or posedge rst)
1965
     if (rst)
1966
       qi <= {length{1'b0}};
1967
     else
1968
     if (cke)
1969
       qi <= q_next;
1970
 
1971
   assign q = qi;
1972
 
1973
 
1974
    always @ (posedge clk or posedge rst)
1975
    if (rst)
1976
        level1 <= 1'b0;
1977
    else
1978
    if (cke)
1979
    if (clear)
1980
        level1 <= 1'b0;
1981
    else if (q_next == level1_value)
1982
        level1 <= 1'b1;
1983
    else if (qi == level1_value & rew)
1984
        level1 <= 1'b0;
1985
 
1986
    always @ (posedge clk or posedge rst)
1987
    if (rst)
1988
        level2 <= 1'b0;
1989
    else
1990
    if (cke)
1991
    if (clear)
1992
        level2 <= 1'b0;
1993
    else if (q_next == level2_value)
1994
        level2 <= 1'b1;
1995
    else if (qi == level2_value & rew)
1996
        level2 <= 1'b0;
1997
endmodule
1998 40 unneback
`endif
1999
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2000 29 unneback
//////////////////////////////////////////////////////////////////////
2001
////                                                              ////
2002
////  Versatile counter                                           ////
2003
////                                                              ////
2004
////  Description                                                 ////
2005
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2006
////  counter                                                     ////
2007
////                                                              ////
2008
////  To Do:                                                      ////
2009
////   - add LFSR with more taps                                  ////
2010
////                                                              ////
2011
////  Author(s):                                                  ////
2012
////      - Michael Unneback, unneback@opencores.org              ////
2013
////        ORSoC AB                                              ////
2014
////                                                              ////
2015
//////////////////////////////////////////////////////////////////////
2016
////                                                              ////
2017
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2018
////                                                              ////
2019
//// This source file may be used and distributed without         ////
2020
//// restriction provided that this copyright statement is not    ////
2021
//// removed from the file and that any derivative work contains  ////
2022
//// the original copyright notice and the associated disclaimer. ////
2023
////                                                              ////
2024
//// This source file is free software; you can redistribute it   ////
2025
//// and/or modify it under the terms of the GNU Lesser General   ////
2026
//// Public License as published by the Free Software Foundation; ////
2027
//// either version 2.1 of the License, or (at your option) any   ////
2028
//// later version.                                               ////
2029
////                                                              ////
2030
//// This source is distributed in the hope that it will be       ////
2031
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2032
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2033
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2034
//// details.                                                     ////
2035
////                                                              ////
2036
//// You should have received a copy of the GNU Lesser General    ////
2037
//// Public License along with this source; if not, download it   ////
2038
//// from http://www.opencores.org/lgpl.shtml                     ////
2039
////                                                              ////
2040
//////////////////////////////////////////////////////////////////////
2041
 
2042
// binary counter
2043 6 unneback
 
2044 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2045
module `BASE`MODULE (
2046
`undef MODULE
2047
 clear, set, cke, rew, q, rst, clk);
2048
 
2049 6 unneback
   parameter length = 4;
2050
   input clear;
2051
   input set;
2052
   input cke;
2053
   input rew;
2054
   output [length:1] q;
2055
   input rst;
2056
   input clk;
2057
 
2058
   parameter clear_value = 0;
2059
   parameter set_value = 1;
2060
   parameter wrap_value = 0;
2061
   parameter level1_value = 15;
2062
 
2063
   reg  [length:1] qi;
2064
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2065
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2066
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2067
   assign q_next = rew ? q_next_rew : q_next_fw;
2068
 
2069
   always @ (posedge clk or posedge rst)
2070
     if (rst)
2071
       qi <= {length{1'b0}};
2072
     else
2073
     if (cke)
2074
       qi <= q_next;
2075
 
2076
   assign q = qi;
2077
 
2078
endmodule
2079 40 unneback
`endif
2080
`ifdef CNT_BIN_CE_REW_L1
2081 6 unneback
//////////////////////////////////////////////////////////////////////
2082
////                                                              ////
2083
////  Versatile counter                                           ////
2084
////                                                              ////
2085
////  Description                                                 ////
2086
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2087
////  counter                                                     ////
2088
////                                                              ////
2089
////  To Do:                                                      ////
2090
////   - add LFSR with more taps                                  ////
2091
////                                                              ////
2092
////  Author(s):                                                  ////
2093
////      - Michael Unneback, unneback@opencores.org              ////
2094
////        ORSoC AB                                              ////
2095
////                                                              ////
2096
//////////////////////////////////////////////////////////////////////
2097
////                                                              ////
2098
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2099
////                                                              ////
2100
//// This source file may be used and distributed without         ////
2101
//// restriction provided that this copyright statement is not    ////
2102
//// removed from the file and that any derivative work contains  ////
2103
//// the original copyright notice and the associated disclaimer. ////
2104
////                                                              ////
2105
//// This source file is free software; you can redistribute it   ////
2106
//// and/or modify it under the terms of the GNU Lesser General   ////
2107
//// Public License as published by the Free Software Foundation; ////
2108
//// either version 2.1 of the License, or (at your option) any   ////
2109
//// later version.                                               ////
2110
////                                                              ////
2111
//// This source is distributed in the hope that it will be       ////
2112
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2113
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2114
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2115
//// details.                                                     ////
2116
////                                                              ////
2117
//// You should have received a copy of the GNU Lesser General    ////
2118
//// Public License along with this source; if not, download it   ////
2119
//// from http://www.opencores.org/lgpl.shtml                     ////
2120
////                                                              ////
2121
//////////////////////////////////////////////////////////////////////
2122
 
2123
// binary counter
2124
 
2125 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2126
module `BASE`MODULE (
2127
`undef MODULE
2128
 cke, rew, level1, rst, clk);
2129
 
2130 6 unneback
   parameter length = 4;
2131
   input cke;
2132
   input rew;
2133
   output reg level1;
2134
   input rst;
2135
   input clk;
2136
 
2137
   parameter clear_value = 0;
2138
   parameter set_value = 1;
2139
   parameter wrap_value = 1;
2140
   parameter level1_value = 15;
2141
 
2142 29 unneback
   wire clear;
2143 30 unneback
   assign clear = 1'b0;
2144 6 unneback
   reg  [length:1] qi;
2145
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2146
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2147
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2148
   assign q_next = rew ? q_next_rew : q_next_fw;
2149
 
2150
   always @ (posedge clk or posedge rst)
2151
     if (rst)
2152
       qi <= {length{1'b0}};
2153
     else
2154
     if (cke)
2155
       qi <= q_next;
2156
 
2157
 
2158
 
2159
    always @ (posedge clk or posedge rst)
2160
    if (rst)
2161
        level1 <= 1'b0;
2162
    else
2163
    if (cke)
2164 29 unneback
    if (clear)
2165
        level1 <= 1'b0;
2166
    else if (q_next == level1_value)
2167 6 unneback
        level1 <= 1'b1;
2168
    else if (qi == level1_value & rew)
2169
        level1 <= 1'b0;
2170
endmodule
2171 40 unneback
`endif
2172
`ifdef CNT_BIN_CE_REW_ZQ_L1
2173 6 unneback
//////////////////////////////////////////////////////////////////////
2174
////                                                              ////
2175
////  Versatile counter                                           ////
2176
////                                                              ////
2177
////  Description                                                 ////
2178
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2179
////  counter                                                     ////
2180
////                                                              ////
2181
////  To Do:                                                      ////
2182
////   - add LFSR with more taps                                  ////
2183
////                                                              ////
2184
////  Author(s):                                                  ////
2185
////      - Michael Unneback, unneback@opencores.org              ////
2186
////        ORSoC AB                                              ////
2187
////                                                              ////
2188
//////////////////////////////////////////////////////////////////////
2189
////                                                              ////
2190
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2191
////                                                              ////
2192
//// This source file may be used and distributed without         ////
2193
//// restriction provided that this copyright statement is not    ////
2194
//// removed from the file and that any derivative work contains  ////
2195
//// the original copyright notice and the associated disclaimer. ////
2196
////                                                              ////
2197
//// This source file is free software; you can redistribute it   ////
2198
//// and/or modify it under the terms of the GNU Lesser General   ////
2199
//// Public License as published by the Free Software Foundation; ////
2200
//// either version 2.1 of the License, or (at your option) any   ////
2201
//// later version.                                               ////
2202
////                                                              ////
2203
//// This source is distributed in the hope that it will be       ////
2204
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2205
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2206
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2207
//// details.                                                     ////
2208
////                                                              ////
2209
//// You should have received a copy of the GNU Lesser General    ////
2210
//// Public License along with this source; if not, download it   ////
2211
//// from http://www.opencores.org/lgpl.shtml                     ////
2212
////                                                              ////
2213
//////////////////////////////////////////////////////////////////////
2214
 
2215 25 unneback
// binary counter
2216
 
2217 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2218
module `BASE`MODULE (
2219
`undef MODULE
2220
 cke, rew, zq, level1, rst, clk);
2221
 
2222 25 unneback
   parameter length = 4;
2223
   input cke;
2224
   input rew;
2225
   output reg zq;
2226
   output reg level1;
2227
   input rst;
2228
   input clk;
2229
 
2230
   parameter clear_value = 0;
2231
   parameter set_value = 1;
2232
   parameter wrap_value = 1;
2233
   parameter level1_value = 15;
2234
 
2235 29 unneback
   wire clear;
2236 30 unneback
   assign clear = 1'b0;
2237 25 unneback
   reg  [length:1] qi;
2238
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2239
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2240
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2241
   assign q_next = rew ? q_next_rew : q_next_fw;
2242
 
2243
   always @ (posedge clk or posedge rst)
2244
     if (rst)
2245
       qi <= {length{1'b0}};
2246
     else
2247
     if (cke)
2248
       qi <= q_next;
2249
 
2250
 
2251
 
2252
   always @ (posedge clk or posedge rst)
2253
     if (rst)
2254
       zq <= 1'b1;
2255
     else
2256
     if (cke)
2257
       zq <= q_next == {length{1'b0}};
2258
 
2259
    always @ (posedge clk or posedge rst)
2260
    if (rst)
2261
        level1 <= 1'b0;
2262
    else
2263
    if (cke)
2264 29 unneback
    if (clear)
2265
        level1 <= 1'b0;
2266
    else if (q_next == level1_value)
2267 25 unneback
        level1 <= 1'b1;
2268
    else if (qi == level1_value & rew)
2269
        level1 <= 1'b0;
2270
endmodule
2271 40 unneback
`endif
2272
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2273 25 unneback
//////////////////////////////////////////////////////////////////////
2274
////                                                              ////
2275
////  Versatile counter                                           ////
2276
////                                                              ////
2277
////  Description                                                 ////
2278
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2279
////  counter                                                     ////
2280
////                                                              ////
2281
////  To Do:                                                      ////
2282
////   - add LFSR with more taps                                  ////
2283
////                                                              ////
2284
////  Author(s):                                                  ////
2285
////      - Michael Unneback, unneback@opencores.org              ////
2286
////        ORSoC AB                                              ////
2287
////                                                              ////
2288
//////////////////////////////////////////////////////////////////////
2289
////                                                              ////
2290
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2291
////                                                              ////
2292
//// This source file may be used and distributed without         ////
2293
//// restriction provided that this copyright statement is not    ////
2294
//// removed from the file and that any derivative work contains  ////
2295
//// the original copyright notice and the associated disclaimer. ////
2296
////                                                              ////
2297
//// This source file is free software; you can redistribute it   ////
2298
//// and/or modify it under the terms of the GNU Lesser General   ////
2299
//// Public License as published by the Free Software Foundation; ////
2300
//// either version 2.1 of the License, or (at your option) any   ////
2301
//// later version.                                               ////
2302
////                                                              ////
2303
//// This source is distributed in the hope that it will be       ////
2304
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2305
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2306
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2307
//// details.                                                     ////
2308
////                                                              ////
2309
//// You should have received a copy of the GNU Lesser General    ////
2310
//// Public License along with this source; if not, download it   ////
2311
//// from http://www.opencores.org/lgpl.shtml                     ////
2312
////                                                              ////
2313
//////////////////////////////////////////////////////////////////////
2314
 
2315
// binary counter
2316
 
2317 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2318
module `BASE`MODULE (
2319
`undef MODULE
2320
 cke, rew, q, zq, level1, rst, clk);
2321
 
2322 25 unneback
   parameter length = 4;
2323
   input cke;
2324
   input rew;
2325
   output [length:1] q;
2326
   output reg zq;
2327
   output reg level1;
2328
   input rst;
2329
   input clk;
2330
 
2331
   parameter clear_value = 0;
2332
   parameter set_value = 1;
2333
   parameter wrap_value = 1;
2334
   parameter level1_value = 15;
2335
 
2336 29 unneback
   wire clear;
2337 30 unneback
   assign clear = 1'b0;
2338 25 unneback
   reg  [length:1] qi;
2339
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2340
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2341
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2342
   assign q_next = rew ? q_next_rew : q_next_fw;
2343
 
2344
   always @ (posedge clk or posedge rst)
2345
     if (rst)
2346
       qi <= {length{1'b0}};
2347
     else
2348
     if (cke)
2349
       qi <= q_next;
2350
 
2351
   assign q = qi;
2352
 
2353
 
2354
   always @ (posedge clk or posedge rst)
2355
     if (rst)
2356
       zq <= 1'b1;
2357
     else
2358
     if (cke)
2359
       zq <= q_next == {length{1'b0}};
2360
 
2361
    always @ (posedge clk or posedge rst)
2362
    if (rst)
2363
        level1 <= 1'b0;
2364
    else
2365
    if (cke)
2366 29 unneback
    if (clear)
2367
        level1 <= 1'b0;
2368
    else if (q_next == level1_value)
2369 25 unneback
        level1 <= 1'b1;
2370
    else if (qi == level1_value & rew)
2371
        level1 <= 1'b0;
2372
endmodule
2373 40 unneback
`endif
2374
`ifdef CNT_LFSR_ZQ
2375 25 unneback
//////////////////////////////////////////////////////////////////////
2376
////                                                              ////
2377
////  Versatile counter                                           ////
2378
////                                                              ////
2379
////  Description                                                 ////
2380
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2381
////  counter                                                     ////
2382
////                                                              ////
2383
////  To Do:                                                      ////
2384
////   - add LFSR with more taps                                  ////
2385
////                                                              ////
2386
////  Author(s):                                                  ////
2387
////      - Michael Unneback, unneback@opencores.org              ////
2388
////        ORSoC AB                                              ////
2389
////                                                              ////
2390
//////////////////////////////////////////////////////////////////////
2391
////                                                              ////
2392
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2393
////                                                              ////
2394
//// This source file may be used and distributed without         ////
2395
//// restriction provided that this copyright statement is not    ////
2396
//// removed from the file and that any derivative work contains  ////
2397
//// the original copyright notice and the associated disclaimer. ////
2398
////                                                              ////
2399
//// This source file is free software; you can redistribute it   ////
2400
//// and/or modify it under the terms of the GNU Lesser General   ////
2401
//// Public License as published by the Free Software Foundation; ////
2402
//// either version 2.1 of the License, or (at your option) any   ////
2403
//// later version.                                               ////
2404
////                                                              ////
2405
//// This source is distributed in the hope that it will be       ////
2406
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2407
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2408
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2409
//// details.                                                     ////
2410
////                                                              ////
2411
//// You should have received a copy of the GNU Lesser General    ////
2412
//// Public License along with this source; if not, download it   ////
2413
//// from http://www.opencores.org/lgpl.shtml                     ////
2414
////                                                              ////
2415
//////////////////////////////////////////////////////////////////////
2416
 
2417 6 unneback
// LFSR counter
2418
 
2419 40 unneback
`define MODULE cnt_lfsr_zq
2420
module `BASE`MODULE (
2421
`undef MODULE
2422
 zq, rst, clk);
2423
 
2424 6 unneback
   parameter length = 4;
2425
   output reg zq;
2426
   input rst;
2427
   input clk;
2428
 
2429
   parameter clear_value = 0;
2430
   parameter set_value = 1;
2431
   parameter wrap_value = 8;
2432
   parameter level1_value = 15;
2433
 
2434
   reg  [length:1] qi;
2435
   reg lfsr_fb;
2436
   wire [length:1] q_next;
2437
   reg [32:1] polynom;
2438
   integer i;
2439
 
2440
   always @ (qi)
2441
   begin
2442
        case (length)
2443
         2: polynom = 32'b11;                               // 0x3
2444
         3: polynom = 32'b110;                              // 0x6
2445
         4: polynom = 32'b1100;                             // 0xC
2446
         5: polynom = 32'b10100;                            // 0x14
2447
         6: polynom = 32'b110000;                           // 0x30
2448
         7: polynom = 32'b1100000;                          // 0x60
2449
         8: polynom = 32'b10111000;                         // 0xb8
2450
         9: polynom = 32'b100010000;                        // 0x110
2451
        10: polynom = 32'b1001000000;                       // 0x240
2452
        11: polynom = 32'b10100000000;                      // 0x500
2453
        12: polynom = 32'b100000101001;                     // 0x829
2454
        13: polynom = 32'b1000000001100;                    // 0x100C
2455
        14: polynom = 32'b10000000010101;                   // 0x2015
2456
        15: polynom = 32'b110000000000000;                  // 0x6000
2457
        16: polynom = 32'b1101000000001000;                 // 0xD008
2458
        17: polynom = 32'b10010000000000000;                // 0x12000
2459
        18: polynom = 32'b100000010000000000;               // 0x20400
2460
        19: polynom = 32'b1000000000000100011;              // 0x40023
2461 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2462 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2463
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2464
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2465
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2466
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2467
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2468
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2469
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2470
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2471
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2472
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2473
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2474
        default: polynom = 32'b0;
2475
        endcase
2476
        lfsr_fb = qi[length];
2477
        for (i=length-1; i>=1; i=i-1) begin
2478
            if (polynom[i])
2479
                lfsr_fb = lfsr_fb  ~^ qi[i];
2480
        end
2481
    end
2482
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2483
 
2484
   always @ (posedge clk or posedge rst)
2485
     if (rst)
2486
       qi <= {length{1'b0}};
2487
     else
2488
       qi <= q_next;
2489
 
2490
 
2491
 
2492
   always @ (posedge clk or posedge rst)
2493
     if (rst)
2494
       zq <= 1'b1;
2495
     else
2496
       zq <= q_next == {length{1'b0}};
2497
endmodule
2498 40 unneback
`endif
2499 75 unneback
`ifdef CNT_LFSR_CE
2500
//////////////////////////////////////////////////////////////////////
2501
////                                                              ////
2502
////  Versatile counter                                           ////
2503
////                                                              ////
2504
////  Description                                                 ////
2505
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2506
////  counter                                                     ////
2507
////                                                              ////
2508
////  To Do:                                                      ////
2509
////   - add LFSR with more taps                                  ////
2510
////                                                              ////
2511
////  Author(s):                                                  ////
2512
////      - Michael Unneback, unneback@opencores.org              ////
2513
////        ORSoC AB                                              ////
2514
////                                                              ////
2515
//////////////////////////////////////////////////////////////////////
2516
////                                                              ////
2517
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2518
////                                                              ////
2519
//// This source file may be used and distributed without         ////
2520
//// restriction provided that this copyright statement is not    ////
2521
//// removed from the file and that any derivative work contains  ////
2522
//// the original copyright notice and the associated disclaimer. ////
2523
////                                                              ////
2524
//// This source file is free software; you can redistribute it   ////
2525
//// and/or modify it under the terms of the GNU Lesser General   ////
2526
//// Public License as published by the Free Software Foundation; ////
2527
//// either version 2.1 of the License, or (at your option) any   ////
2528
//// later version.                                               ////
2529
////                                                              ////
2530
//// This source is distributed in the hope that it will be       ////
2531
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2532
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2533
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2534
//// details.                                                     ////
2535
////                                                              ////
2536
//// You should have received a copy of the GNU Lesser General    ////
2537
//// Public License along with this source; if not, download it   ////
2538
//// from http://www.opencores.org/lgpl.shtml                     ////
2539
////                                                              ////
2540
//////////////////////////////////////////////////////////////////////
2541
 
2542
// LFSR counter
2543
 
2544
`define MODULE cnt_lfsr_ce
2545
module `BASE`MODULE (
2546
`undef MODULE
2547
 cke, zq, rst, clk);
2548
 
2549
   parameter length = 4;
2550
   input cke;
2551
   output reg zq;
2552
   input rst;
2553
   input clk;
2554
 
2555
   parameter clear_value = 0;
2556
   parameter set_value = 1;
2557
   parameter wrap_value = 0;
2558
   parameter level1_value = 15;
2559
 
2560
   reg  [length:1] qi;
2561
   reg lfsr_fb;
2562
   wire [length:1] q_next;
2563
   reg [32:1] polynom;
2564
   integer i;
2565
 
2566
   always @ (qi)
2567
   begin
2568
        case (length)
2569
         2: polynom = 32'b11;                               // 0x3
2570
         3: polynom = 32'b110;                              // 0x6
2571
         4: polynom = 32'b1100;                             // 0xC
2572
         5: polynom = 32'b10100;                            // 0x14
2573
         6: polynom = 32'b110000;                           // 0x30
2574
         7: polynom = 32'b1100000;                          // 0x60
2575
         8: polynom = 32'b10111000;                         // 0xb8
2576
         9: polynom = 32'b100010000;                        // 0x110
2577
        10: polynom = 32'b1001000000;                       // 0x240
2578
        11: polynom = 32'b10100000000;                      // 0x500
2579
        12: polynom = 32'b100000101001;                     // 0x829
2580
        13: polynom = 32'b1000000001100;                    // 0x100C
2581
        14: polynom = 32'b10000000010101;                   // 0x2015
2582
        15: polynom = 32'b110000000000000;                  // 0x6000
2583
        16: polynom = 32'b1101000000001000;                 // 0xD008
2584
        17: polynom = 32'b10010000000000000;                // 0x12000
2585
        18: polynom = 32'b100000010000000000;               // 0x20400
2586
        19: polynom = 32'b1000000000000100011;              // 0x40023
2587
        20: polynom = 32'b10010000000000000000;             // 0x90000
2588
        21: polynom = 32'b101000000000000000000;            // 0x140000
2589
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2590
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2591
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2592
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2593
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2594
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2595
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2596
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2597
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2598
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2599
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2600
        default: polynom = 32'b0;
2601
        endcase
2602
        lfsr_fb = qi[length];
2603
        for (i=length-1; i>=1; i=i-1) begin
2604
            if (polynom[i])
2605
                lfsr_fb = lfsr_fb  ~^ qi[i];
2606
        end
2607
    end
2608
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2609
 
2610
   always @ (posedge clk or posedge rst)
2611
     if (rst)
2612
       qi <= {length{1'b0}};
2613
     else
2614
     if (cke)
2615
       qi <= q_next;
2616
 
2617
 
2618
 
2619
   always @ (posedge clk or posedge rst)
2620
     if (rst)
2621
       zq <= 1'b1;
2622
     else
2623
     if (cke)
2624
       zq <= q_next == {length{1'b0}};
2625
endmodule
2626
`endif
2627 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2628 6 unneback
//////////////////////////////////////////////////////////////////////
2629
////                                                              ////
2630
////  Versatile counter                                           ////
2631
////                                                              ////
2632
////  Description                                                 ////
2633
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2634
////  counter                                                     ////
2635
////                                                              ////
2636
////  To Do:                                                      ////
2637
////   - add LFSR with more taps                                  ////
2638
////                                                              ////
2639
////  Author(s):                                                  ////
2640
////      - Michael Unneback, unneback@opencores.org              ////
2641
////        ORSoC AB                                              ////
2642
////                                                              ////
2643
//////////////////////////////////////////////////////////////////////
2644
////                                                              ////
2645
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2646
////                                                              ////
2647
//// This source file may be used and distributed without         ////
2648
//// restriction provided that this copyright statement is not    ////
2649
//// removed from the file and that any derivative work contains  ////
2650
//// the original copyright notice and the associated disclaimer. ////
2651
////                                                              ////
2652
//// This source file is free software; you can redistribute it   ////
2653
//// and/or modify it under the terms of the GNU Lesser General   ////
2654
//// Public License as published by the Free Software Foundation; ////
2655
//// either version 2.1 of the License, or (at your option) any   ////
2656
//// later version.                                               ////
2657
////                                                              ////
2658
//// This source is distributed in the hope that it will be       ////
2659
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2660
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2661
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2662
//// details.                                                     ////
2663
////                                                              ////
2664
//// You should have received a copy of the GNU Lesser General    ////
2665
//// Public License along with this source; if not, download it   ////
2666
//// from http://www.opencores.org/lgpl.shtml                     ////
2667
////                                                              ////
2668
//////////////////////////////////////////////////////////////////////
2669
 
2670
// LFSR counter
2671
 
2672 40 unneback
`define MODULE cnt_lfsr_ce_zq
2673
module `BASE`MODULE (
2674
`undef MODULE
2675
 cke, zq, rst, clk);
2676
 
2677 6 unneback
   parameter length = 4;
2678
   input cke;
2679
   output reg zq;
2680
   input rst;
2681
   input clk;
2682
 
2683
   parameter clear_value = 0;
2684
   parameter set_value = 1;
2685
   parameter wrap_value = 8;
2686
   parameter level1_value = 15;
2687
 
2688
   reg  [length:1] qi;
2689
   reg lfsr_fb;
2690
   wire [length:1] q_next;
2691
   reg [32:1] polynom;
2692
   integer i;
2693
 
2694
   always @ (qi)
2695
   begin
2696
        case (length)
2697
         2: polynom = 32'b11;                               // 0x3
2698
         3: polynom = 32'b110;                              // 0x6
2699
         4: polynom = 32'b1100;                             // 0xC
2700
         5: polynom = 32'b10100;                            // 0x14
2701
         6: polynom = 32'b110000;                           // 0x30
2702
         7: polynom = 32'b1100000;                          // 0x60
2703
         8: polynom = 32'b10111000;                         // 0xb8
2704
         9: polynom = 32'b100010000;                        // 0x110
2705
        10: polynom = 32'b1001000000;                       // 0x240
2706
        11: polynom = 32'b10100000000;                      // 0x500
2707
        12: polynom = 32'b100000101001;                     // 0x829
2708
        13: polynom = 32'b1000000001100;                    // 0x100C
2709
        14: polynom = 32'b10000000010101;                   // 0x2015
2710
        15: polynom = 32'b110000000000000;                  // 0x6000
2711
        16: polynom = 32'b1101000000001000;                 // 0xD008
2712
        17: polynom = 32'b10010000000000000;                // 0x12000
2713
        18: polynom = 32'b100000010000000000;               // 0x20400
2714
        19: polynom = 32'b1000000000000100011;              // 0x40023
2715 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2716 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2717
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2718
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2719
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2720
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2721
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2722
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2723
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2724
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2725
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2726
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2727
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2728
        default: polynom = 32'b0;
2729
        endcase
2730
        lfsr_fb = qi[length];
2731
        for (i=length-1; i>=1; i=i-1) begin
2732
            if (polynom[i])
2733
                lfsr_fb = lfsr_fb  ~^ qi[i];
2734
        end
2735
    end
2736
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2737
 
2738
   always @ (posedge clk or posedge rst)
2739
     if (rst)
2740
       qi <= {length{1'b0}};
2741
     else
2742
     if (cke)
2743
       qi <= q_next;
2744
 
2745
 
2746
 
2747
   always @ (posedge clk or posedge rst)
2748
     if (rst)
2749
       zq <= 1'b1;
2750
     else
2751
     if (cke)
2752
       zq <= q_next == {length{1'b0}};
2753
endmodule
2754 40 unneback
`endif
2755
`ifdef CNT_LFSR_CE_Q
2756 6 unneback
//////////////////////////////////////////////////////////////////////
2757
////                                                              ////
2758
////  Versatile counter                                           ////
2759
////                                                              ////
2760
////  Description                                                 ////
2761
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2762
////  counter                                                     ////
2763
////                                                              ////
2764
////  To Do:                                                      ////
2765
////   - add LFSR with more taps                                  ////
2766
////                                                              ////
2767
////  Author(s):                                                  ////
2768
////      - Michael Unneback, unneback@opencores.org              ////
2769
////        ORSoC AB                                              ////
2770
////                                                              ////
2771
//////////////////////////////////////////////////////////////////////
2772
////                                                              ////
2773
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2774
////                                                              ////
2775
//// This source file may be used and distributed without         ////
2776
//// restriction provided that this copyright statement is not    ////
2777
//// removed from the file and that any derivative work contains  ////
2778
//// the original copyright notice and the associated disclaimer. ////
2779
////                                                              ////
2780
//// This source file is free software; you can redistribute it   ////
2781
//// and/or modify it under the terms of the GNU Lesser General   ////
2782
//// Public License as published by the Free Software Foundation; ////
2783
//// either version 2.1 of the License, or (at your option) any   ////
2784
//// later version.                                               ////
2785
////                                                              ////
2786
//// This source is distributed in the hope that it will be       ////
2787
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2788
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2789
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2790
//// details.                                                     ////
2791
////                                                              ////
2792
//// You should have received a copy of the GNU Lesser General    ////
2793
//// Public License along with this source; if not, download it   ////
2794
//// from http://www.opencores.org/lgpl.shtml                     ////
2795
////                                                              ////
2796
//////////////////////////////////////////////////////////////////////
2797 22 unneback
 
2798
// LFSR counter
2799 27 unneback
 
2800 40 unneback
`define MODULE cnt_lfsr_ce_q
2801
module `BASE`MODULE (
2802
`undef MODULE
2803
 cke, q, rst, clk);
2804
 
2805 27 unneback
   parameter length = 4;
2806
   input cke;
2807
   output [length:1] q;
2808
   input rst;
2809
   input clk;
2810
 
2811
   parameter clear_value = 0;
2812
   parameter set_value = 1;
2813
   parameter wrap_value = 8;
2814
   parameter level1_value = 15;
2815
 
2816
   reg  [length:1] qi;
2817
   reg lfsr_fb;
2818
   wire [length:1] q_next;
2819
   reg [32:1] polynom;
2820
   integer i;
2821
 
2822
   always @ (qi)
2823
   begin
2824
        case (length)
2825
         2: polynom = 32'b11;                               // 0x3
2826
         3: polynom = 32'b110;                              // 0x6
2827
         4: polynom = 32'b1100;                             // 0xC
2828
         5: polynom = 32'b10100;                            // 0x14
2829
         6: polynom = 32'b110000;                           // 0x30
2830
         7: polynom = 32'b1100000;                          // 0x60
2831
         8: polynom = 32'b10111000;                         // 0xb8
2832
         9: polynom = 32'b100010000;                        // 0x110
2833
        10: polynom = 32'b1001000000;                       // 0x240
2834
        11: polynom = 32'b10100000000;                      // 0x500
2835
        12: polynom = 3