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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 95

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 40 unneback 
`ifdef ALL
14 
 
15 
`define GBUF
16 
`define SYNC_RST
17 
`define PLL
18 
 
19 
`define MULTS
20 
`define MULTS18X18
21 
`define MULT
22 
`define SHIFT_UNIT_32
23 
`define LOGIC_UNIT
24 
 
25 
`define CNT_SHREG_WRAP
26 
`define CNT_SHREG_CE_WRAP
27 
`define CNT_SHREG_CE_CLEAR
28 
`define CNT_SHREG_CE_CLEAR_WRAP
29 
 
30 
`define MUX_ANDOR
31 
`define MUX2_ANDOR
32 
`define MUX3_ANDOR
33 
`define MUX4_ANDOR
34 
`define MUX5_ANDOR
35 
`define MUX6_ANDOR
36 43 unneback 
`define PARITY
37 40 unneback 
 
38 
`define ROM_INIT
39 
`define RAM
40 
`define RAM_BE
41 
`define DPRAM_1R1W
42 
`define DPRAM_2R1W
43 
`define DPRAM_2R2W
44 75 unneback 
`define DPRAM_BE_2R2W
45 40 unneback 
`define FIFO_1R1W_FILL_LEVEL_SYNC
46 
`define FIFO_2R2W_SYNC_SIMPLEX
47 
`define FIFO_CMP_ASYNC
48 
`define FIFO_1R1W_ASYNC
49 
`define FIFO_2R2W_ASYNC
50 
`define FIFO_2R2W_ASYNC_SIMPLEX
51 48 unneback 
`define REG_FILE
52 40 unneback 
 
53 
`define DFF
54 
`define DFF_ARRAY
55 
`define DFF_CE
56 
`define DFF_CE_CLEAR
57 
`define DF_CE_SET
58 
`define SPR
59 
`define SRP
60 
`define DFF_SR
61 
`define LATCH
62 
`define SHREG
63 
`define SHREG_CE
64 
`define DELAY
65 
`define DELAY_EMPTYFLAG
66 94 unneback 
`define PULSE2TOGGLE
67 
`define TOGGLE2PULSE
68 
`define SYNCHRONIZER
69 
`define CDC
70 40 unneback 
 
71 75 unneback 
`define WB3AVALON_BRIDGE
72 40 unneback 
`define WB3WB3_BRIDGE
73 
`define WB3_ARBITER_TYPE1
74 83 unneback 
`define WB_ADR_INC
75 59 unneback 
`define WB_B3_RAM_BE
76 49 unneback 
`define WB_B4_RAM_BE
77 48 unneback 
`define WB_B4_ROM
78 40 unneback 
`define WB_BOOT_ROM
79 
`define WB_DPRAM
80 
 
81 44 unneback 
`define IO_DFF_OE
82 
`define O_DFF
83 
 
84 40 unneback 
`endif
85 
 
86 
`ifdef PLL
87 
`ifndef SYNC_RST
88 
`define SYNC_RST
89 
`endif
90 
`endif
91 
 
92 
`ifdef SYNC_RST
93 
`ifndef GBUF
94 
`define GBUF
95 
`endif
96 
`endif
97 
 
98 94 unneback 
`ifdef CDC
99 
`ifndef PULSE2TOGGLE
100 
`define PULSE2TOGGLE
101 
`endif
102 
`ifndef TOGGLE2PULSE
103 
`define TOGGLE2PULSE
104 
`endif
105 
`ifndef SYNCHRONIZER
106 
`define SYNCHRONIZER
107 
`endif
108 
`endif
109 
 
110 92 unneback 
`ifdef WB_B3_DPRAM
111 
`ifndef WB_ADR_INC
112 
`define WB_ADR_INC
113 40 unneback 
`endif
114 92 unneback 
`ifndef DPRAM_BE_2R2W
115 
`define DPRAM_BE_2R2W
116 40 unneback 
`endif
117 
`endif
118 
 
119 62 unneback 
`ifdef WB_B3_RAM_BE
120 83 unneback 
`ifndef WB_ADR_INC
121 
`define WB_ADR_INC
122 62 unneback 
`endif
123 
`ifndef RAM_BE
124 
`define RAM_BE
125 
`endif
126 
`endif
127 
 
128 40 unneback 
`ifdef WB3_ARBITER_TYPE1
129 42 unneback 
`ifndef SPR
130 
`define SPR
131 
`endif
132 40 unneback 
`ifndef MUX_ANDOR
133 
`define MUX_ANDOR
134 
`endif
135 
`endif
136 
 
137 76 unneback 
`ifdef WB3AVALON_BRIDGE
138 
`ifndef WB3WB3_BRIDGE
139 
`define WB3WB3_BRIDGE
140 
`endif
141 
`endif
142 
 
143 40 unneback 
`ifdef WB3WB3_BRIDGE
144 
`ifndef CNT_SHREG_CE_CLEAR
145 
`define CNT_SHREG_CE_CLEAR
146 
`endif
147 
`ifndef DFF
148 
`define DFF
149 
`endif
150 
`ifndef DFF_CE
151 
`define DFF_CE
152 
`endif
153 
`ifndef CNT_SHREG_CE_CLEAR
154 
`define CNT_SHREG_CE_CLEAR
155 
`endif
156 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
157 
`define FIFO_2R2W_ASYNC_SIMPLEX
158 
`endif
159 
`endif
160 
 
161 
`ifdef MULTS18X18
162 
`ifndef MULTS
163 
`define MULTS
164 
`endif
165 
`endif
166 
 
167 
`ifdef SHIFT_UNIT_32
168 
`ifndef MULTS
169 
`define MULTS
170 
`endif
171 
`endif
172 
 
173 
`ifdef MUX2_ANDOR
174 
`ifndef MUX_ANDOR
175 
`define MUX_ANDOR
176 
`endif
177 
`endif
178 
 
179 
`ifdef MUX3_ANDOR
180 
`ifndef MUX_ANDOR
181 
`define MUX_ANDOR
182 
`endif
183 
`endif
184 
 
185 
`ifdef MUX4_ANDOR
186 
`ifndef MUX_ANDOR
187 
`define MUX_ANDOR
188 
`endif
189 
`endif
190 
 
191 
`ifdef MUX5_ANDOR
192 
`ifndef MUX_ANDOR
193 
`define MUX_ANDOR
194 
`endif
195 
`endif
196 
 
197 
`ifdef MUX6_ANDOR
198 
`ifndef MUX_ANDOR
199 
`define MUX_ANDOR
200 
`endif
201 
`endif
202 
 
203 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
204 
`ifndef CNT_BIN_CE
205 
`define CNT_BIN_CE
206 
`endif
207 
`ifndef DPRAM_1R1W
208 
`define DPRAM_1R1W
209 
`endif
210 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
211 
`define CNT_BIN_CE_REW_Q_ZQ_L1
212 
`endif
213 
`endif
214 
 
215 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
216 
`ifndef CNT_LFSR_CE
217 
`define CNT_LFSR_CE
218 
`endif
219 
`ifndef DPRAM_2R2W
220 
`define DPRAM_2R2W
221 
`endif
222 
`ifndef CNT_BIN_CE_REW_ZQ_L1
223 
`define CNT_BIN_CE_REW_ZQ_L1
224 
`endif
225 
`endif
226 
 
227 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
228 
`ifndef CNT_GRAY_CE_BIN
229 
`define CNT_GRAY_CE_BIN
230 
`endif
231 
`ifndef DPRAM_2R2W
232 
`define DPRAM_2R2W
233 
`endif
234 
`ifndef FIFO_CMP_ASYNC
235 
`define FIFO_CMP_ASYNC
236 
`endif
237 
`endif
238 
 
239 
`ifdef FIFO_2R2W_ASYNC
240 
`ifndef FIFO_1R1W_ASYNC
241 
`define FIFO_1R1W_ASYNC
242 
`endif
243 
`endif
244 
 
245 
`ifdef FIFO_1R1W_ASYNC
246 
`ifndef CNT_GRAY_CE_BIN
247 
`define CNT_GRAY_CE_BIN
248 
`endif
249 
`ifndef DPRAM_1R1W
250 
`define DPRAM_1R1W
251 
`endif
252 
`ifndef FIFO_CMP_ASYNC
253 
`define FIFO_CMP_ASYNC
254 
`endif
255 
`endif
256 
 
257 
`ifdef FIFO_CMP_ASYNC
258 
`ifndef DFF_SR
259 
`define DFF_SR
260 
`endif
261 
`ifndef DFF
262 
`define DFF
263 
`endif
264 
`endif
265 48 unneback 
 
266 
`ifdef REG_FILE
267 
`ifndef DPRAM_1R1W
268 
`define DPRAM_1R1W
269 
`endif
270 
`endif
271 62 unneback 
//////////////////////////////////////////////////////////////////////
272 6 unneback 
////                                                              ////
273 
////  Versatile library, clock and reset                          ////
274 
////                                                              ////
275 
////  Description                                                 ////
276 
////  Logic related to clock and reset                            ////
277 
////                                                              ////
278 
////                                                              ////
279 
////  To Do:                                                      ////
280 
////   - add more different registers                             ////
281 
////                                                              ////
282 
////  Author(s):                                                  ////
283 
////      - Michael Unneback, unneback@opencores.org              ////
284 
////        ORSoC AB                                              ////
285 
////                                                              ////
286 
//////////////////////////////////////////////////////////////////////
287 
////                                                              ////
288 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
289 
////                                                              ////
290 
//// This source file may be used and distributed without         ////
291 
//// restriction provided that this copyright statement is not    ////
292 
//// removed from the file and that any derivative work contains  ////
293 
//// the original copyright notice and the associated disclaimer. ////
294 
////                                                              ////
295 
//// This source file is free software; you can redistribute it   ////
296 
//// and/or modify it under the terms of the GNU Lesser General   ////
297 
//// Public License as published by the Free Software Foundation; ////
298 
//// either version 2.1 of the License, or (at your option) any   ////
299 
//// later version.                                               ////
300 
////                                                              ////
301 
//// This source is distributed in the hope that it will be       ////
302 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
303 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
304 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
305 
//// details.                                                     ////
306 
////                                                              ////
307 
//// You should have received a copy of the GNU Lesser General    ////
308 
//// Public License along with this source; if not, download it   ////
309 
//// from http://www.opencores.org/lgpl.shtml                     ////
310 
////                                                              ////
311 
//////////////////////////////////////////////////////////////////////
312 
 
313 48 unneback 
`ifdef ACTEL
314 
`ifdef GBUF
315 
`timescale 1 ns/100 ps
316 6 unneback 
// Global buffer
317 
// usage:
318 
// use to enable global buffers for high fan out signals such as clock and reset
319 
// Version: 8.4 8.4.0.33
320 
module gbuf(GL,CLK);
321 
output GL;
322 
input  CLK;
323 
 
324 
    wire GND;
325 
 
326 
    GND GND_1_net(.Y(GND));
327 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
328 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
329 
 
330 
endmodule
331 
`timescale 1 ns/1 ns
332 40 unneback 
`define MODULE gbuf
333 
module `BASE`MODULE ( i, o);
334 
`undef MODULE
335 6 unneback 
input i;
336 
output o;
337 
`ifdef SIM_GBUF
338 
assign o=i;
339 
`else
340 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
341 
`endif
342 
endmodule
343 40 unneback 
`endif
344 33 unneback 
 
345 6 unneback 
`else
346 33 unneback 
 
347 40 unneback 
`ifdef ALTERA
348 
`ifdef GBUF
349 21 unneback 
//altera
350 40 unneback 
`define MODULE gbuf
351 
module `BASE`MODULE ( i, o);
352 
`undef MODULE
353 33 unneback 
input i;
354 
output o;
355 
assign o = i;
356 
endmodule
357 40 unneback 
`endif
358 33 unneback 
 
359 6 unneback 
`else
360 
 
361 40 unneback 
`ifdef GBUF
362 6 unneback 
`timescale 1 ns/100 ps
363 40 unneback 
`define MODULE
364 
module `BASE`MODULE ( i, o);
365 
`undef MODULE
366 6 unneback 
input i;
367 
output o;
368 
assign o = i;
369 
endmodule
370 40 unneback 
`endif
371 6 unneback 
`endif // ALTERA
372 
`endif //ACTEL
373 
 
374 40 unneback 
`ifdef SYNC_RST
375 6 unneback 
// sync reset
376 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
377 6 unneback 
// output active high global reset sync with two DFFs
378 
`timescale 1 ns/100 ps
379 40 unneback 
`define MODULE sync_rst
380 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
381 
`undef MODULE
382 6 unneback 
input rst_n_i, clk;
383 
output rst_o;
384 18 unneback 
reg [1:0] tmp;
385 6 unneback 
always @ (posedge clk or negedge rst_n_i)
386 
if (!rst_n_i)
387 17 unneback 
        tmp <= 2'b11;
388 6 unneback 
else
389 33 unneback 
        tmp <= {1'b0,tmp[1]};
390 40 unneback 
`define MODULE gbuf
391 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
392 
`undef MODULE
393 6 unneback 
endmodule
394 40 unneback 
`endif
395 6 unneback 
 
396 40 unneback 
`ifdef PLL
397 6 unneback 
// vl_pll
398 
`ifdef ACTEL
399 32 unneback 
///////////////////////////////////////////////////////////////////////////////
400 17 unneback 
`timescale 1 ps/1 ps
401 40 unneback 
`define MODULE pll
402 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
403 
`undef MODULE
404 6 unneback 
parameter index = 0;
405 
parameter number_of_clk = 1;
406 17 unneback 
parameter period_time_0 = 20000;
407 
parameter period_time_1 = 20000;
408 
parameter period_time_2 = 20000;
409 
parameter lock_delay = 2000000;
410 6 unneback 
input clk_i, rst_n_i;
411 
output lock;
412 
output reg [0:number_of_clk-1] clk_o;
413 
output [0:number_of_clk-1] rst_o;
414 
 
415 
`ifdef SIM_PLL
416 
 
417 
always
418 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
419 
 
420 
generate if (number_of_clk > 1)
421 
always
422 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
423 
endgenerate
424 
 
425 
generate if (number_of_clk > 2)
426 
always
427 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
428 
endgenerate
429 
 
430 
genvar i;
431 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
432 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
433 
end
434 
endgenerate
435 
 
436 
assign #lock_delay lock = rst_n_i;
437 
 
438 
endmodule
439 
`else
440 
generate if (number_of_clk==1 & index==0) begin
441 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
442 
end
443 
endgenerate // index==0
444 
generate if (number_of_clk==1 & index==1) begin
445 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
446 
end
447 
endgenerate // index==1
448 
generate if (number_of_clk==1 & index==2) begin
449 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
450 
end
451 
endgenerate // index==2
452 
generate if (number_of_clk==1 & index==3) begin
453 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
454 
end
455 
endgenerate // index==0
456 
 
457 
generate if (number_of_clk==2 & index==0) begin
458 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
459 
end
460 
endgenerate // index==0
461 
generate if (number_of_clk==2 & index==1) begin
462 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
463 
end
464 
endgenerate // index==1
465 
generate if (number_of_clk==2 & index==2) begin
466 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
467 
end
468 
endgenerate // index==2
469 
generate if (number_of_clk==2 & index==3) begin
470 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
471 
end
472 
endgenerate // index==0
473 
 
474 
generate if (number_of_clk==3 & index==0) begin
475 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
476 
end
477 
endgenerate // index==0
478 
generate if (number_of_clk==3 & index==1) begin
479 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
480 
end
481 
endgenerate // index==1
482 
generate if (number_of_clk==3 & index==2) begin
483 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
484 
end
485 
endgenerate // index==2
486 
generate if (number_of_clk==3 & index==3) begin
487 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
488 
end
489 
endgenerate // index==0
490 
 
491 
genvar i;
492 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
493 40 unneback 
`define MODULE sync_rst
494 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
495 
`undef MODULE
496 6 unneback 
end
497 
endgenerate
498 
endmodule
499 
`endif
500 32 unneback 
///////////////////////////////////////////////////////////////////////////////
501 6 unneback 
 
502 
`else
503 
 
504 32 unneback 
///////////////////////////////////////////////////////////////////////////////
505 6 unneback 
`ifdef ALTERA
506 
 
507 32 unneback 
`timescale 1 ps/1 ps
508 40 unneback 
`define MODULE pll
509 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
510 
`undef MODULE
511 32 unneback 
parameter index = 0;
512 
parameter number_of_clk = 1;
513 
parameter period_time_0 = 20000;
514 
parameter period_time_1 = 20000;
515 
parameter period_time_2 = 20000;
516 
parameter period_time_3 = 20000;
517 
parameter period_time_4 = 20000;
518 
parameter lock_delay = 2000000;
519 
input clk_i, rst_n_i;
520 
output lock;
521 
output reg [0:number_of_clk-1] clk_o;
522 
output [0:number_of_clk-1] rst_o;
523 
 
524 
`ifdef SIM_PLL
525 
 
526 
always
527 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
528 
 
529 
generate if (number_of_clk > 1)
530 
always
531 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
532 
endgenerate
533 
 
534 
generate if (number_of_clk > 2)
535 
always
536 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
537 
endgenerate
538 
 
539 33 unneback 
generate if (number_of_clk > 3)
540 32 unneback 
always
541 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
542 
endgenerate
543 
 
544 33 unneback 
generate if (number_of_clk > 4)
545 32 unneback 
always
546 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
547 
endgenerate
548 
 
549 
genvar i;
550 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
551 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
552 
end
553 
endgenerate
554 
 
555 33 unneback 
//assign #lock_delay lock = rst_n_i;
556 
assign lock = rst_n_i;
557 32 unneback 
 
558 
endmodule
559 6 unneback 
`else
560 
 
561 33 unneback 
`ifdef VL_PLL0
562 
`ifdef VL_PLL0_CLK1
563 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
564 
`endif
565 
`ifdef VL_PLL0_CLK2
566 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
567 
`endif
568 
`ifdef VL_PLL0_CLK3
569 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
570 
`endif
571 
`ifdef VL_PLL0_CLK4
572 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
573 
`endif
574 
`ifdef VL_PLL0_CLK5
575 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
576 
`endif
577 
`endif
578 32 unneback 
 
579 33 unneback 
`ifdef VL_PLL1
580 
`ifdef VL_PLL1_CLK1
581 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
582 
`endif
583 
`ifdef VL_PLL1_CLK2
584 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
585 
`endif
586 
`ifdef VL_PLL1_CLK3
587 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
588 
`endif
589 
`ifdef VL_PLL1_CLK4
590 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
591 
`endif
592 
`ifdef VL_PLL1_CLK5
593 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
594 
`endif
595 
`endif
596 32 unneback 
 
597 33 unneback 
`ifdef VL_PLL2
598 
`ifdef VL_PLL2_CLK1
599 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
600 
`endif
601 
`ifdef VL_PLL2_CLK2
602 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
603 
`endif
604 
`ifdef VL_PLL2_CLK3
605 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
606 
`endif
607 
`ifdef VL_PLL2_CLK4
608 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
609 
`endif
610 
`ifdef VL_PLL2_CLK5
611 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
612 
`endif
613 
`endif
614 32 unneback 
 
615 33 unneback 
`ifdef VL_PLL3
616 
`ifdef VL_PLL3_CLK1
617 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
618 
`endif
619 
`ifdef VL_PLL3_CLK2
620 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
621 
`endif
622 
`ifdef VL_PLL3_CLK3
623 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
624 
`endif
625 
`ifdef VL_PLL3_CLK4
626 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
627 
`endif
628 
`ifdef VL_PLL3_CLK5
629 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
630 
`endif
631 
`endif
632 32 unneback 
 
633 
genvar i;
634 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
635 40 unneback 
`define MODULE sync_rst
636 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
637 
`undef MODULE
638 32 unneback 
end
639 
endgenerate
640 
endmodule
641 
`endif
642 
///////////////////////////////////////////////////////////////////////////////
643 
 
644 
`else
645 
 
646 6 unneback 
// generic PLL
647 17 unneback 
`timescale 1 ps/1 ps
648 40 unneback 
`define MODULE pll
649 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
650 
`undef MODULE
651 6 unneback 
parameter index = 0;
652 
parameter number_of_clk = 1;
653 17 unneback 
parameter period_time_0 = 20000;
654 
parameter period_time_1 = 20000;
655 
parameter period_time_2 = 20000;
656 6 unneback 
parameter lock_delay = 2000;
657 
input clk_i, rst_n_i;
658 
output lock;
659 
output reg [0:number_of_clk-1] clk_o;
660 
output [0:number_of_clk-1] rst_o;
661 
 
662 
always
663 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
664 
 
665 
generate if (number_of_clk > 1)
666 
always
667 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
668 
endgenerate
669 
 
670 
generate if (number_of_clk > 2)
671 
always
672 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
673 
endgenerate
674 
 
675 
genvar i;
676 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
677 40 unneback 
`define MODULE sync_rst
678 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
679 
`undef MODULE
680 6 unneback 
end
681 
endgenerate
682 
 
683 
assign #lock_delay lock = rst_n_i;
684 
 
685 
endmodule
686 
 
687 
`endif //altera
688 17 unneback 
`endif //actel
689 40 unneback 
`undef MODULE
690 
`endif//////////////////////////////////////////////////////////////////////
691 6 unneback 
////                                                              ////
692 
////  Versatile library, registers                                ////
693 
////                                                              ////
694 
////  Description                                                 ////
695 
////  Different type of registers                                 ////
696 
////                                                              ////
697 
////                                                              ////
698 
////  To Do:                                                      ////
699 
////   - add more different registers                             ////
700 
////                                                              ////
701 
////  Author(s):                                                  ////
702 
////      - Michael Unneback, unneback@opencores.org              ////
703 
////        ORSoC AB                                              ////
704 
////                                                              ////
705 
//////////////////////////////////////////////////////////////////////
706 
////                                                              ////
707 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
708 
////                                                              ////
709 
//// This source file may be used and distributed without         ////
710 
//// restriction provided that this copyright statement is not    ////
711 
//// removed from the file and that any derivative work contains  ////
712 
//// the original copyright notice and the associated disclaimer. ////
713 
////                                                              ////
714 
//// This source file is free software; you can redistribute it   ////
715 
//// and/or modify it under the terms of the GNU Lesser General   ////
716 
//// Public License as published by the Free Software Foundation; ////
717 
//// either version 2.1 of the License, or (at your option) any   ////
718 
//// later version.                                               ////
719 
////                                                              ////
720 
//// This source is distributed in the hope that it will be       ////
721 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
722 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
723 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
724 
//// details.                                                     ////
725 
////                                                              ////
726 
//// You should have received a copy of the GNU Lesser General    ////
727 
//// Public License along with this source; if not, download it   ////
728 
//// from http://www.opencores.org/lgpl.shtml                     ////
729 
////                                                              ////
730 
//////////////////////////////////////////////////////////////////////
731 
 
732 40 unneback 
`ifdef DFF
733 
`define MODULE dff
734 
module `BASE`MODULE ( d, q, clk, rst);
735 
`undef MODULE
736 6 unneback 
        parameter width = 1;
737 
        parameter reset_value = 0;
738 
 
739 
        input [width-1:0] d;
740 
        input clk, rst;
741 
        output reg [width-1:0] q;
742 
 
743 
        always @ (posedge clk or posedge rst)
744 
        if (rst)
745 
                q <= reset_value;
746 
        else
747 
                q <= d;
748 
 
749 
endmodule
750 40 unneback 
`endif
751 6 unneback 
 
752 40 unneback 
`ifdef DFF_ARRAY
753 
`define MODULE dff_array
754 
module `BASE`MODULE ( d, q, clk, rst);
755 
`undef MODULE
756 6 unneback 
 
757 
        parameter width = 1;
758 
        parameter depth = 2;
759 
        parameter reset_value = 1'b0;
760 
 
761 
        input [width-1:0] d;
762 
        input clk, rst;
763 
        output [width-1:0] q;
764 
        reg  [0:depth-1] q_tmp [width-1:0];
765 
        integer i;
766 
        always @ (posedge clk or posedge rst)
767 
        if (rst) begin
768 
            for (i=0;i<depth;i=i+1)
769 
                q_tmp[i] <= {width{reset_value}};
770 
        end else begin
771 
            q_tmp[0] <= d;
772 
            for (i=1;i<depth;i=i+1)
773 
                q_tmp[i] <= q_tmp[i-1];
774 
        end
775 
 
776 
    assign q = q_tmp[depth-1];
777 
 
778 
endmodule
779 40 unneback 
`endif
780 6 unneback 
 
781 40 unneback 
`ifdef DFF_CE
782 
`define MODULE dff_ce
783 
module `BASE`MODULE ( d, ce, q, clk, rst);
784 
`undef MODULE
785 6 unneback 
 
786 
        parameter width = 1;
787 
        parameter reset_value = 0;
788 
 
789 
        input [width-1:0] d;
790 
        input ce, clk, rst;
791 
        output reg [width-1:0] q;
792 
 
793 
        always @ (posedge clk or posedge rst)
794 
        if (rst)
795 
                q <= reset_value;
796 
        else
797 
                if (ce)
798 
                        q <= d;
799 
 
800 
endmodule
801 40 unneback 
`endif
802 6 unneback 
 
803 40 unneback 
`ifdef DFF_CE_CLEAR
804 
`define MODULE dff_ce_clear
805 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
806 
`undef MODULE
807 8 unneback 
 
808 
        parameter width = 1;
809 
        parameter reset_value = 0;
810 
 
811 
        input [width-1:0] d;
812 10 unneback 
        input ce, clear, clk, rst;
813 8 unneback 
        output reg [width-1:0] q;
814 
 
815 
        always @ (posedge clk or posedge rst)
816 
        if (rst)
817 
            q <= reset_value;
818 
        else
819 
            if (ce)
820 
                if (clear)
821 
                    q <= {width{1'b0}};
822 
                else
823 
                    q <= d;
824 
 
825 
endmodule
826 40 unneback 
`endif
827 8 unneback 
 
828 40 unneback 
`ifdef DF_CE_SET
829 
`define MODULE dff_ce_set
830 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
831 
`undef MODULE
832 24 unneback 
 
833 
        parameter width = 1;
834 
        parameter reset_value = 0;
835 
 
836 
        input [width-1:0] d;
837 
        input ce, set, clk, rst;
838 
        output reg [width-1:0] q;
839 
 
840 
        always @ (posedge clk or posedge rst)
841 
        if (rst)
842 
            q <= reset_value;
843 
        else
844 
            if (ce)
845 
                if (set)
846 
                    q <= {width{1'b1}};
847 
                else
848 
                    q <= d;
849 
 
850 
endmodule
851 40 unneback 
`endif
852 24 unneback 
 
853 40 unneback 
`ifdef SPR
854 
`define MODULE spr
855 
module `BASE`MODULE ( sp, r, q, clk, rst);
856 
`undef MODULE
857 
 
858 64 unneback 
        //parameter width = 1;
859 
        parameter reset_value = 1'b0;
860 29 unneback 
 
861 
        input sp, r;
862 
        output reg q;
863 
        input clk, rst;
864 
 
865 
        always @ (posedge clk or posedge rst)
866 
        if (rst)
867 
            q <= reset_value;
868 
        else
869 
            if (sp)
870 
                q <= 1'b1;
871 
            else if (r)
872 
                q <= 1'b0;
873 
 
874 
endmodule
875 40 unneback 
`endif
876 29 unneback 
 
877 40 unneback 
`ifdef SRP
878 
`define MODULE srp
879 
module `BASE`MODULE ( s, rp, q, clk, rst);
880 
`undef MODULE
881 
 
882 29 unneback 
        parameter width = 1;
883 
        parameter reset_value = 0;
884 
 
885 
        input s, rp;
886 
        output reg q;
887 
        input clk, rst;
888 
 
889 
        always @ (posedge clk or posedge rst)
890 
        if (rst)
891 
            q <= reset_value;
892 
        else
893 
            if (rp)
894 
                q <= 1'b0;
895 
            else if (s)
896 
                q <= 1'b1;
897 
 
898 
endmodule
899 40 unneback 
`endif
900 29 unneback 
 
901 40 unneback 
`ifdef ALTERA
902 29 unneback 
 
903 40 unneback 
`ifdef DFF_SR
904 6 unneback 
// megafunction wizard: %LPM_FF%
905 
// GENERATION: STANDARD
906 
// VERSION: WM1.0
907 
// MODULE: lpm_ff
908 
 
909 
// ============================================================
910 
// File Name: dff_sr.v
911 
// Megafunction Name(s):
912 
//                      lpm_ff
913 
//
914 
// Simulation Library Files(s):
915 
//                      lpm
916 
// ============================================================
917 
// ************************************************************
918 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
919 
//
920 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
921 
// ************************************************************
922 
 
923 
 
924 
//Copyright (C) 1991-2010 Altera Corporation
925 
//Your use of Altera Corporation's design tools, logic functions
926 
//and other software and tools, and its AMPP partner logic
927 
//functions, and any output files from any of the foregoing
928 
//(including device programming or simulation files), and any
929 
//associated documentation or information are expressly subject
930 
//to the terms and conditions of the Altera Program License
931 
//Subscription Agreement, Altera MegaCore Function License
932 
//Agreement, or other applicable license agreement, including,
933 
//without limitation, that your use is for the sole purpose of
934 
//programming logic devices manufactured by Altera and sold by
935 
//Altera or its authorized distributors.  Please refer to the
936 
//applicable agreement for further details.
937 
 
938 
 
939 
// synopsys translate_off
940 
`timescale 1 ps / 1 ps
941 
// synopsys translate_on
942 40 unneback 
`define MODULE dff_sr
943 
module `BASE`MODULE (
944 
`undef MODULE
945 
 
946 6 unneback 
        aclr,
947 
        aset,
948 
        clock,
949 
        data,
950 
        q);
951 
 
952 
        input     aclr;
953 
        input     aset;
954 
        input     clock;
955 
        input     data;
956 
        output    q;
957 
 
958 
        wire [0:0] sub_wire0;
959 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
960 
        wire  q = sub_wire1;
961 
        wire  sub_wire2 = data;
962 
        wire  sub_wire3 = sub_wire2;
963 
 
964 
        lpm_ff  lpm_ff_component (
965 
                                .aclr (aclr),
966 
                                .clock (clock),
967 
                                .data (sub_wire3),
968 
                                .aset (aset),
969 
                                .q (sub_wire0)
970 
                                // synopsys translate_off
971 
                                ,
972 
                                .aload (),
973 
                                .enable (),
974 
                                .sclr (),
975 
                                .sload (),
976 
                                .sset ()
977 
                                // synopsys translate_on
978 
                                );
979 
        defparam
980 
                lpm_ff_component.lpm_fftype = "DFF",
981 
                lpm_ff_component.lpm_type = "LPM_FF",
982 
                lpm_ff_component.lpm_width = 1;
983 
 
984 
 
985 
endmodule
986 
 
987 
// ============================================================
988 
// CNX file retrieval info
989 
// ============================================================
990 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
991 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
992 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
993 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
994 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
995 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
996 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
997 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
998 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
999 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1000 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1001 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1002 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1003 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1004 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1005 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1006 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1007 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1008 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1009 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1010 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1011 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1012 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1013 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1014 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1015 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1016 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1017 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1018 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1019 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1020 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1021 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1022 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1023 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1024 
// Retrieval info: LIB_FILE: lpm
1025 40 unneback 
`endif
1026 6 unneback 
 
1027 
`else
1028 
 
1029 40 unneback 
`ifdef DFF_SR
1030 
`define MODULE dff_sr
1031 
module `BASE`MODULE ( aclr, aset, clock, data, q);
1032 
`undef MODULE
1033 6 unneback 
 
1034 
    input         aclr;
1035 
    input         aset;
1036 
    input         clock;
1037 
    input         data;
1038 
    output reg    q;
1039 
 
1040 
   always @ (posedge clock or posedge aclr or posedge aset)
1041 
     if (aclr)
1042 
       q <= 1'b0;
1043 
     else if (aset)
1044 
       q <= 1'b1;
1045 
     else
1046 
       q <= data;
1047 
 
1048 
endmodule
1049 40 unneback 
`endif
1050 6 unneback 
 
1051 
`endif
1052 
 
1053 
// LATCH
1054 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1055 
`ifdef ALTERA
1056 40 unneback 
 
1057 
`ifdef LATCH
1058 
`define MODULE latch
1059 
module `BASE`MODULE ( d, le, q, clk);
1060 
`undef MODULE
1061 6 unneback 
input d, le;
1062 
output q;
1063 
input clk;
1064 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1065 
endmodule
1066 40 unneback 
`endif
1067 
 
1068 6 unneback 
`else
1069 40 unneback 
 
1070 
`ifdef LATCH
1071 
`define MODULE latch
1072 
module `BASE`MODULE ( d, le, q, clk);
1073 
`undef MODULE
1074 6 unneback 
input d, le;
1075 48 unneback 
input clk;
1076 
always @ (le or d)
1077 60 unneback 
if (le)
1078 48 unneback 
    d <= q;
1079 6 unneback 
endmodule
1080 15 unneback 
`endif
1081 
 
1082 40 unneback 
`endif
1083 
 
1084 
`ifdef SHREG
1085 
`define MODULE shreg
1086 
module `BASE`MODULE ( d, q, clk, rst);
1087 
`undef MODULE
1088 
 
1089 17 unneback 
parameter depth = 10;
1090 
input d;
1091 
output q;
1092 
input clk, rst;
1093 
 
1094 
reg [1:depth] dffs;
1095 
 
1096 
always @ (posedge clk or posedge rst)
1097 
if (rst)
1098 
    dffs <= {depth{1'b0}};
1099 
else
1100 
    dffs <= {d,dffs[1:depth-1]};
1101 
assign q = dffs[depth];
1102 
endmodule
1103 40 unneback 
`endif
1104 17 unneback 
 
1105 40 unneback 
`ifdef SHREG_CE
1106 
`define MODULE shreg_ce
1107 
module `BASE`MODULE ( d, ce, q, clk, rst);
1108 
`undef MODULE
1109 17 unneback 
parameter depth = 10;
1110 
input d, ce;
1111 
output q;
1112 
input clk, rst;
1113 
 
1114 
reg [1:depth] dffs;
1115 
 
1116 
always @ (posedge clk or posedge rst)
1117 
if (rst)
1118 
    dffs <= {depth{1'b0}};
1119 
else
1120 
    if (ce)
1121 
        dffs <= {d,dffs[1:depth-1]};
1122 
assign q = dffs[depth];
1123 
endmodule
1124 40 unneback 
`endif
1125 17 unneback 
 
1126 40 unneback 
`ifdef DELAY
1127 
`define MODULE delay
1128 
module `BASE`MODULE ( d, q, clk, rst);
1129 
`undef MODULE
1130 15 unneback 
parameter depth = 10;
1131 
input d;
1132 
output q;
1133 
input clk, rst;
1134 
 
1135 
reg [1:depth] dffs;
1136 
 
1137 
always @ (posedge clk or posedge rst)
1138 
if (rst)
1139 
    dffs <= {depth{1'b0}};
1140 
else
1141 
    dffs <= {d,dffs[1:depth-1]};
1142 
assign q = dffs[depth];
1143 17 unneback 
endmodule
1144 40 unneback 
`endif
1145 17 unneback 
 
1146 40 unneback 
`ifdef DELAY_EMPTYFLAG
1147 
`define MODULE delay_emptyflag
1148 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1149 40 unneback 
`undef MODULE
1150 17 unneback 
parameter depth = 10;
1151 
input d;
1152 
output q, emptyflag;
1153 
input clk, rst;
1154 
 
1155 
reg [1:depth] dffs;
1156 
 
1157 
always @ (posedge clk or posedge rst)
1158 
if (rst)
1159 
    dffs <= {depth{1'b0}};
1160 
else
1161 
    dffs <= {d,dffs[1:depth-1]};
1162 
assign q = dffs[depth];
1163 
assign emptyflag = !(|dffs);
1164 
endmodule
1165 40 unneback 
`endif
1166 75 unneback 
 
1167 94 unneback 
`ifdef PULSE2TOGGLE
1168 
`define MODULE pules2toggle
1169 
module `BASE`MODULE ( pl, q, clk, rst)
1170 75 unneback 
`undef MODULE
1171 94 unneback 
input pl;
1172 
output q;
1173 
input clk, rst;
1174 
input
1175 
always @ (posedge clk or posedge rst)
1176 75 unneback 
if (rst)
1177 94 unneback 
    q <= 1'b0;
1178 75 unneback 
else
1179 94 unneback 
    q <= pl ^ q;
1180 
endmodule
1181 
`endif
1182 75 unneback 
 
1183 94 unneback 
`ifdef TOGGLE2PULSE
1184 
`define MODULE toggle2pulse;
1185 
module `BASE`MODULE (d, pl, clk, rst);
1186 
input d;
1187 
output pl;
1188 
input clk, rst;
1189 
reg dff;
1190 
always @ (posedge clk or posedge rst)
1191 
if (rst)
1192 
    dff <= 1'b0;
1193 75 unneback 
else
1194 94 unneback 
    dff <= d;
1195 
assign d ^ dff;
1196 
endmodule
1197 
`endif
1198 75 unneback 
 
1199 94 unneback 
`ifdef SYNCHRONIZER
1200 
`define MODULE synchronizer
1201 
module `BASE`MODULE (d, q, clk, rst);
1202 
`undef MODULE
1203 
input d;
1204 
output reg q;
1205 
output clk, rst;
1206 
reg dff;
1207 
always @ (posedge clk or posedge rst)
1208 
if (rst)
1209 
    {dff,q} <= 2'b00;
1210 75 unneback 
else
1211 94 unneback 
    {dff,q} <= {d,dff};
1212 
endmodule
1213 
`endif
1214 75 unneback 
 
1215 94 unneback 
`ifdef CDC
1216 
`define MODULE cdc
1217 
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst)
1218 
`undef MODULE
1219 
input start_pl;
1220 
output take_it_pl;
1221 
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1222 
output got_it_pl;
1223 
input clk_src, rst_src;
1224 
input clk_dst, rst_dst;
1225 
wire take_it_tg, take_it_tg_sync;
1226 
wire got_it_tg, got_it_tg_sync;
1227 
// src -> dst
1228 
`define MODULE pulse2toggle
1229 
`BASE`MODULE p2t0 (
1230 
`undef MODULE
1231 
    .pl(start_pl),
1232 
    .q(take_it_tg),
1233 
    .clk(clk_src),
1234 
    .rst(rst_src));
1235 75 unneback 
 
1236 94 unneback 
`define MODULE synchronizer
1237 
`BASE`MODULE sync0 (
1238 
`undef MODULE
1239 
    .d(take_it_tg),
1240 
    .q(take_it_tg_sync),
1241 
    .clk(clk_dst),
1242 
    .rst(rst_dst));
1243 
 
1244 
`define MODULE toggle2pulse
1245 
`BASE`MODULE t2p0 (
1246 
`undef MODULE
1247 
    .d(take_it_sync),
1248 
    .pl(take_it_pl),
1249 
    .clk(clk_dst),
1250 
    .rst(rst_dst));
1251 
 
1252 
// dst -> src
1253 
`define MODULE pulse2toggle
1254 
`BASE`MODULE p2t0 (
1255 
`undef MODULE
1256 
    .pl(take_it_grant_pl),
1257 
    .q(got_it_tg),
1258 
    .clk(clk_dst),
1259 
    .rst(rst_dst));
1260 
 
1261 
`define MODULE synchronizer
1262 
`BASE`MODULE sync1 (
1263 
`undef MODULE
1264 
    .d(got_it_tg),
1265 
    .q(got_it_tg_sync),
1266 
    .clk(clk_src),
1267 
    .rst(rst_src));
1268 
 
1269 
`define MODULE toggle2pulse
1270 
`BASE`MODULE t2p1 (
1271 
`undef MODULE
1272 
    .d(take_it_grant_tg_sync),
1273 
    .pl(got_it_pl),
1274 
    .clk(clk_src),
1275 
    .rst(rst_src));
1276 
 
1277 75 unneback 
endmodule
1278 
`endif
1279 17 unneback 
//////////////////////////////////////////////////////////////////////
1280 6 unneback 
////                                                              ////
1281 18 unneback 
////  Logic functions                                             ////
1282 
////                                                              ////
1283 
////  Description                                                 ////
1284 
////  Logic functions such as multiplexers                        ////
1285 
////                                                              ////
1286 
////                                                              ////
1287 
////  To Do:                                                      ////
1288 
////   -                                                          ////
1289 
////                                                              ////
1290 
////  Author(s):                                                  ////
1291 
////      - Michael Unneback, unneback@opencores.org              ////
1292 
////        ORSoC AB                                              ////
1293 
////                                                              ////
1294 
//////////////////////////////////////////////////////////////////////
1295 
////                                                              ////
1296 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1297 
////                                                              ////
1298 
//// This source file may be used and distributed without         ////
1299 
//// restriction provided that this copyright statement is not    ////
1300 
//// removed from the file and that any derivative work contains  ////
1301 
//// the original copyright notice and the associated disclaimer. ////
1302 
////                                                              ////
1303 
//// This source file is free software; you can redistribute it   ////
1304 
//// and/or modify it under the terms of the GNU Lesser General   ////
1305 
//// Public License as published by the Free Software Foundation; ////
1306 
//// either version 2.1 of the License, or (at your option) any   ////
1307 
//// later version.                                               ////
1308 
////                                                              ////
1309 
//// This source is distributed in the hope that it will be       ////
1310 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1311 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1312 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1313 
//// details.                                                     ////
1314 
////                                                              ////
1315 
//// You should have received a copy of the GNU Lesser General    ////
1316 
//// Public License along with this source; if not, download it   ////
1317 
//// from http://www.opencores.org/lgpl.shtml                     ////
1318 
////                                                              ////
1319 
//////////////////////////////////////////////////////////////////////
1320 40 unneback 
`ifdef MUX_ANDOR
1321 
`define MODULE mux_andor
1322 
module `BASE`MODULE ( a, sel, dout);
1323 
`undef MODULE
1324 36 unneback 
 
1325 
parameter width = 32;
1326 
parameter nr_of_ports = 4;
1327 
 
1328 
input [nr_of_ports*width-1:0] a;
1329 
input [nr_of_ports-1:0] sel;
1330 
output reg [width-1:0] dout;
1331 
 
1332 38 unneback 
integer i,j;
1333 
 
1334 36 unneback 
always @ (a, sel)
1335 
begin
1336 
    dout = a[width-1:0] & {width{sel[0]}};
1337 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1338 
        for (j=0;j<width;j=j+1)
1339 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1340 36 unneback 
end
1341 
 
1342 
endmodule
1343 40 unneback 
`endif
1344 36 unneback 
 
1345 40 unneback 
`ifdef MUX2_ANDOR
1346 
`define MODULE mux2_andor
1347 
module `BASE`MODULE ( a1, a0, sel, dout);
1348 
`undef MODULE
1349 18 unneback 
 
1350 34 unneback 
parameter width = 32;
1351 35 unneback 
localparam nr_of_ports = 2;
1352 34 unneback 
input [width-1:0] a1, a0;
1353 
input [nr_of_ports-1:0] sel;
1354 
output [width-1:0] dout;
1355 
 
1356 40 unneback 
`define MODULE mux_andor
1357 
`BASE`MODULE
1358 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1359 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1360 40 unneback 
`undef MODULE
1361 
 
1362 34 unneback 
endmodule
1363 40 unneback 
`endif
1364 34 unneback 
 
1365 40 unneback 
`ifdef MUX3_ANDOR
1366 
`define MODULE mux3_andor
1367 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1368 
`undef MODULE
1369 34 unneback 
 
1370 
parameter width = 32;
1371 35 unneback 
localparam nr_of_ports = 3;
1372 34 unneback 
input [width-1:0] a2, a1, a0;
1373 
input [nr_of_ports-1:0] sel;
1374 
output [width-1:0] dout;
1375 
 
1376 40 unneback 
`define MODULE mux_andor
1377 
`BASE`MODULE
1378 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1379 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1380 40 unneback 
`undef MODULE
1381 34 unneback 
endmodule
1382 40 unneback 
`endif
1383 34 unneback 
 
1384 40 unneback 
`ifdef MUX4_ANDOR
1385 
`define MODULE mux4_andor
1386 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1387 
`undef MODULE
1388 18 unneback 
 
1389 
parameter width = 32;
1390 35 unneback 
localparam nr_of_ports = 4;
1391 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1392 
input [nr_of_ports-1:0] sel;
1393 22 unneback 
output [width-1:0] dout;
1394 18 unneback 
 
1395 40 unneback 
`define MODULE mux_andor
1396 
`BASE`MODULE
1397 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1398 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1399 40 unneback 
`undef MODULE
1400 18 unneback 
 
1401 
endmodule
1402 40 unneback 
`endif
1403 18 unneback 
 
1404 40 unneback 
`ifdef MUX5_ANDOR
1405 
`define MODULE mux5_andor
1406 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1407 
`undef MODULE
1408 18 unneback 
 
1409 
parameter width = 32;
1410 35 unneback 
localparam nr_of_ports = 5;
1411 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1412 
input [nr_of_ports-1:0] sel;
1413 22 unneback 
output [width-1:0] dout;
1414 18 unneback 
 
1415 40 unneback 
`define MODULE mux_andor
1416 
`BASE`MODULE
1417 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1418 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1419 40 unneback 
`undef MODULE
1420 18 unneback 
 
1421 
endmodule
1422 40 unneback 
`endif
1423 18 unneback 
 
1424 40 unneback 
`ifdef MUX6_ANDOR
1425 
`define MODULE mux6_andor
1426 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1427 
`undef MODULE
1428 18 unneback 
 
1429 
parameter width = 32;
1430 35 unneback 
localparam nr_of_ports = 6;
1431 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1432 
input [nr_of_ports-1:0] sel;
1433 22 unneback 
output [width-1:0] dout;
1434 18 unneback 
 
1435 40 unneback 
`define MODULE mux_andor
1436 
`BASE`MODULE
1437 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1438 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1439 40 unneback 
`undef MODULE
1440 18 unneback 
 
1441 
endmodule
1442 40 unneback 
`endif
1443 43 unneback 
 
1444 
`ifdef PARITY
1445 
 
1446 
`define MODULE parity_generate
1447 
module `BASE`MODULE (data, parity);
1448 
`undef MODULE
1449 
parameter word_size = 32;
1450 
parameter chunk_size = 8;
1451 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1452 
input [word_size-1:0] data;
1453 
output reg [word_size/chunk_size-1:0] parity;
1454 
integer i,j;
1455 
always @ (data)
1456 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1457 
    parity[i] = parity_type;
1458 
    for (j=0;j<chunk_size;j=j+1) begin
1459 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1460 43 unneback 
    end
1461 
end
1462 
endmodule
1463 
 
1464 
`define MODULE parity_check
1465 
module `BASE`MODULE( data, parity, parity_error);
1466 
`undef MODULE
1467 
parameter word_size = 32;
1468 
parameter chunk_size = 8;
1469 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1470 
input [word_size-1:0] data;
1471 
input [word_size/chunk_size-1:0] parity;
1472 
output parity_error;
1473 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1474 43 unneback 
integer i,j;
1475 
always @ (data or parity)
1476 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1477 
    error_flag[i] = parity[i] ^ parity_type;
1478 
    for (j=0;j<chunk_size;j=j+1) begin
1479 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1480 43 unneback 
    end
1481 
end
1482 
assign parity_error = |error_flag;
1483 
endmodule
1484 
 
1485 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1486 
////                                                              ////
1487 
////  IO functions                                                ////
1488 
////                                                              ////
1489 
////  Description                                                 ////
1490 
////  IO functions such as IOB flip-flops                         ////
1491 
////                                                              ////
1492 
////                                                              ////
1493 
////  To Do:                                                      ////
1494 
////   -                                                          ////
1495 
////                                                              ////
1496 
////  Author(s):                                                  ////
1497 
////      - Michael Unneback, unneback@opencores.org              ////
1498 
////        ORSoC AB                                              ////
1499 
////                                                              ////
1500 18 unneback 
//////////////////////////////////////////////////////////////////////
1501 
////                                                              ////
1502 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1503 
////                                                              ////
1504 
//// This source file may be used and distributed without         ////
1505 
//// restriction provided that this copyright statement is not    ////
1506 
//// removed from the file and that any derivative work contains  ////
1507 
//// the original copyright notice and the associated disclaimer. ////
1508 
////                                                              ////
1509 
//// This source file is free software; you can redistribute it   ////
1510 
//// and/or modify it under the terms of the GNU Lesser General   ////
1511 
//// Public License as published by the Free Software Foundation; ////
1512 
//// either version 2.1 of the License, or (at your option) any   ////
1513 
//// later version.                                               ////
1514 
////                                                              ////
1515 
//// This source is distributed in the hope that it will be       ////
1516 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1517 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1518 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1519 
//// details.                                                     ////
1520 
////                                                              ////
1521 
//// You should have received a copy of the GNU Lesser General    ////
1522 
//// Public License along with this source; if not, download it   ////
1523 
//// from http://www.opencores.org/lgpl.shtml                     ////
1524 
////                                                              ////
1525 
//////////////////////////////////////////////////////////////////////
1526 45 unneback 
`timescale 1ns/1ns
1527 44 unneback 
`ifdef O_DFF
1528 
`define MODULE o_dff
1529 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1530 
`undef MODULE
1531 
parameter width = 1;
1532 45 unneback 
parameter reset_value = {width{1'b0}};
1533 
input  [width-1:0]  d_i;
1534 44 unneback 
output [width-1:0] o_pad;
1535 
input clk, rst;
1536 
wire [width-1:0] d_i_int `SYN_KEEP;
1537 45 unneback 
reg  [width-1:0] o_pad_int;
1538 44 unneback 
assign d_i_int = d_i;
1539 
genvar i;
1540 45 unneback 
generate
1541 44 unneback 
for (i=0;i<width;i=i+1) begin
1542 
    always @ (posedge clk or posedge rst)
1543 
    if (rst)
1544 45 unneback 
        o_pad_int[i] <= reset_value[i];
1545 44 unneback 
    else
1546 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1547 
    assign #1 o_pad[i] = o_pad_int[i];
1548 44 unneback 
end
1549 
endgenerate
1550 
endmodule
1551 
`endif
1552 
 
1553 45 unneback 
`timescale 1ns/1ns
1554 44 unneback 
`ifdef IO_DFF_OE
1555 
`define MODULE io_dff_oe
1556 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1557 
`undef MODULE
1558 
parameter width = 1;
1559 
input  [width-1:0] d_o;
1560 
output reg [width-1:0] d_i;
1561 
input oe;
1562 
inout [width-1:0] io_pad;
1563 
input clk, rst;
1564 
wire [width-1:0] oe_d `SYN_KEEP;
1565 
reg [width-1:0] oe_q;
1566 
reg [width-1:0] d_o_q;
1567 
assign oe_d = {width{oe}};
1568 
genvar i;
1569 
generate
1570 
for (i=0;i<width;i=i+1) begin
1571 
    always @ (posedge clk or posedge rst)
1572 
    if (rst)
1573 
        oe_q[i] <= 1'b0;
1574 
    else
1575 
        oe_q[i] <= oe_d[i];
1576 
    always @ (posedge clk or posedge rst)
1577 
    if (rst)
1578 
        d_o_q[i] <= 1'b0;
1579 
    else
1580 
        d_o_q[i] <= d_o[i];
1581 
    always @ (posedge clk or posedge rst)
1582 
    if (rst)
1583 
        d_i[i] <= 1'b0;
1584 
    else
1585 
        d_i[i] <= io_pad[i];
1586 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1587 44 unneback 
end
1588 
endgenerate
1589 
endmodule
1590 
`endif
1591 
`ifdef CNT_BIN
1592 
//////////////////////////////////////////////////////////////////////
1593 
////                                                              ////
1594 6 unneback 
////  Versatile counter                                           ////
1595 
////                                                              ////
1596 
////  Description                                                 ////
1597 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1598 
////  counter                                                     ////
1599 
////                                                              ////
1600 
////  To Do:                                                      ////
1601 
////   - add LFSR with more taps                                  ////
1602 
////                                                              ////
1603 
////  Author(s):                                                  ////
1604 
////      - Michael Unneback, unneback@opencores.org              ////
1605 
////        ORSoC AB                                              ////
1606 
////                                                              ////
1607 
//////////////////////////////////////////////////////////////////////
1608 
////                                                              ////
1609 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1610 
////                                                              ////
1611 
//// This source file may be used and distributed without         ////
1612 
//// restriction provided that this copyright statement is not    ////
1613 
//// removed from the file and that any derivative work contains  ////
1614 
//// the original copyright notice and the associated disclaimer. ////
1615 
////                                                              ////
1616 
//// This source file is free software; you can redistribute it   ////
1617 
//// and/or modify it under the terms of the GNU Lesser General   ////
1618 
//// Public License as published by the Free Software Foundation; ////
1619 
//// either version 2.1 of the License, or (at your option) any   ////
1620 
//// later version.                                               ////
1621 
////                                                              ////
1622 
//// This source is distributed in the hope that it will be       ////
1623 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1624 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1625 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1626 
//// details.                                                     ////
1627 
////                                                              ////
1628 
//// You should have received a copy of the GNU Lesser General    ////
1629 
//// Public License along with this source; if not, download it   ////
1630 
//// from http://www.opencores.org/lgpl.shtml                     ////
1631 
////                                                              ////
1632 
//////////////////////////////////////////////////////////////////////
1633 
 
1634 
// binary counter
1635 22 unneback 
 
1636 40 unneback 
`define MODULE cnt_bin
1637 
module `BASE`MODULE (
1638 
`undef MODULE
1639 
 q, rst, clk);
1640 
 
1641 22 unneback 
   parameter length = 4;
1642 
   output [length:1] q;
1643 
   input rst;
1644 
   input clk;
1645 
 
1646 
   parameter clear_value = 0;
1647 
   parameter set_value = 1;
1648 
   parameter wrap_value = 0;
1649 
   parameter level1_value = 15;
1650 
 
1651 
   reg  [length:1] qi;
1652 
   wire [length:1] q_next;
1653 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1654 
 
1655 
   always @ (posedge clk or posedge rst)
1656 
     if (rst)
1657 
       qi <= {length{1'b0}};
1658 
     else
1659 
       qi <= q_next;
1660 
 
1661 
   assign q = qi;
1662 
 
1663 
endmodule
1664 40 unneback 
`endif
1665 
`ifdef CNT_BIN_CLEAR
1666 22 unneback 
//////////////////////////////////////////////////////////////////////
1667 
////                                                              ////
1668 
////  Versatile counter                                           ////
1669 
////                                                              ////
1670 
////  Description                                                 ////
1671 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1672 
////  counter                                                     ////
1673 
////                                                              ////
1674 
////  To Do:                                                      ////
1675 
////   - add LFSR with more taps                                  ////
1676 
////                                                              ////
1677 
////  Author(s):                                                  ////
1678 
////      - Michael Unneback, unneback@opencores.org              ////
1679 
////        ORSoC AB                                              ////
1680 
////                                                              ////
1681 
//////////////////////////////////////////////////////////////////////
1682 
////                                                              ////
1683 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1684 
////                                                              ////
1685 
//// This source file may be used and distributed without         ////
1686 
//// restriction provided that this copyright statement is not    ////
1687 
//// removed from the file and that any derivative work contains  ////
1688 
//// the original copyright notice and the associated disclaimer. ////
1689 
////                                                              ////
1690 
//// This source file is free software; you can redistribute it   ////
1691 
//// and/or modify it under the terms of the GNU Lesser General   ////
1692 
//// Public License as published by the Free Software Foundation; ////
1693 
//// either version 2.1 of the License, or (at your option) any   ////
1694 
//// later version.                                               ////
1695 
////                                                              ////
1696 
//// This source is distributed in the hope that it will be       ////
1697 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1698 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1699 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1700 
//// details.                                                     ////
1701 
////                                                              ////
1702 
//// You should have received a copy of the GNU Lesser General    ////
1703 
//// Public License along with this source; if not, download it   ////
1704 
//// from http://www.opencores.org/lgpl.shtml                     ////
1705 
////                                                              ////
1706 
//////////////////////////////////////////////////////////////////////
1707 
 
1708 
// binary counter
1709 
 
1710 40 unneback 
`define MODULE cnt_bin_clear
1711 
module `BASE`MODULE (
1712 
`undef MODULE
1713 
 clear, q, rst, clk);
1714 
 
1715 22 unneback 
   parameter length = 4;
1716 
   input clear;
1717 
   output [length:1] q;
1718 
   input rst;
1719 
   input clk;
1720 
 
1721 
   parameter clear_value = 0;
1722 
   parameter set_value = 1;
1723 
   parameter wrap_value = 0;
1724 
   parameter level1_value = 15;
1725 
 
1726 
   reg  [length:1] qi;
1727 
   wire [length:1] q_next;
1728 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1729 
 
1730 
   always @ (posedge clk or posedge rst)
1731 
     if (rst)
1732 
       qi <= {length{1'b0}};
1733 
     else
1734 
       qi <= q_next;
1735 
 
1736 
   assign q = qi;
1737 
 
1738 
endmodule
1739 40 unneback 
`endif
1740 
`ifdef CNT_BIN_CE
1741 22 unneback 
//////////////////////////////////////////////////////////////////////
1742 
////                                                              ////
1743 
////  Versatile counter                                           ////
1744 
////                                                              ////
1745 
////  Description                                                 ////
1746 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1747 
////  counter                                                     ////
1748 
////                                                              ////
1749 
////  To Do:                                                      ////
1750 
////   - add LFSR with more taps                                  ////
1751 
////                                                              ////
1752 
////  Author(s):                                                  ////
1753 
////      - Michael Unneback, unneback@opencores.org              ////
1754 
////        ORSoC AB                                              ////
1755 
////                                                              ////
1756 
//////////////////////////////////////////////////////////////////////
1757 
////                                                              ////
1758 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1759 
////                                                              ////
1760 
//// This source file may be used and distributed without         ////
1761 
//// restriction provided that this copyright statement is not    ////
1762 
//// removed from the file and that any derivative work contains  ////
1763 
//// the original copyright notice and the associated disclaimer. ////
1764 
////                                                              ////
1765 
//// This source file is free software; you can redistribute it   ////
1766 
//// and/or modify it under the terms of the GNU Lesser General   ////
1767 
//// Public License as published by the Free Software Foundation; ////
1768 
//// either version 2.1 of the License, or (at your option) any   ////
1769 
//// later version.                                               ////
1770 
////                                                              ////
1771 
//// This source is distributed in the hope that it will be       ////
1772 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1773 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1774 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1775 
//// details.                                                     ////
1776 
////                                                              ////
1777 
//// You should have received a copy of the GNU Lesser General    ////
1778 
//// Public License along with this source; if not, download it   ////
1779 
//// from http://www.opencores.org/lgpl.shtml                     ////
1780 
////                                                              ////
1781 
//////////////////////////////////////////////////////////////////////
1782 
 
1783 
// binary counter
1784 6 unneback 
 
1785 40 unneback 
`define MODULE cnt_bin_ce
1786 
module `BASE`MODULE (
1787 
`undef MODULE
1788 
 cke, q, rst, clk);
1789 
 
1790 6 unneback 
   parameter length = 4;
1791 
   input cke;
1792 
   output [length:1] q;
1793 
   input rst;
1794 
   input clk;
1795 
 
1796 
   parameter clear_value = 0;
1797 
   parameter set_value = 1;
1798 
   parameter wrap_value = 0;
1799 
   parameter level1_value = 15;
1800 
 
1801 
   reg  [length:1] qi;
1802 
   wire [length:1] q_next;
1803 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1804 
 
1805 
   always @ (posedge clk or posedge rst)
1806 
     if (rst)
1807 
       qi <= {length{1'b0}};
1808 
     else
1809 
     if (cke)
1810 
       qi <= q_next;
1811 
 
1812 
   assign q = qi;
1813 
 
1814 
endmodule
1815 40 unneback 
`endif
1816 
`ifdef CNT_BIN_CE_CLEAR
1817 6 unneback 
//////////////////////////////////////////////////////////////////////
1818 
////                                                              ////
1819 
////  Versatile counter                                           ////
1820 
////                                                              ////
1821 
////  Description                                                 ////
1822 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1823 
////  counter                                                     ////
1824 
////                                                              ////
1825 
////  To Do:                                                      ////
1826 
////   - add LFSR with more taps                                  ////
1827 
////                                                              ////
1828 
////  Author(s):                                                  ////
1829 
////      - Michael Unneback, unneback@opencores.org              ////
1830 
////        ORSoC AB                                              ////
1831 
////                                                              ////
1832 
//////////////////////////////////////////////////////////////////////
1833 
////                                                              ////
1834 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1835 
////                                                              ////
1836 
//// This source file may be used and distributed without         ////
1837 
//// restriction provided that this copyright statement is not    ////
1838 
//// removed from the file and that any derivative work contains  ////
1839 
//// the original copyright notice and the associated disclaimer. ////
1840 
////                                                              ////
1841 
//// This source file is free software; you can redistribute it   ////
1842 
//// and/or modify it under the terms of the GNU Lesser General   ////
1843 
//// Public License as published by the Free Software Foundation; ////
1844 
//// either version 2.1 of the License, or (at your option) any   ////
1845 
//// later version.                                               ////
1846 
////                                                              ////
1847 
//// This source is distributed in the hope that it will be       ////
1848 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1849 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1850 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1851 
//// details.                                                     ////
1852 
////                                                              ////
1853 
//// You should have received a copy of the GNU Lesser General    ////
1854 
//// Public License along with this source; if not, download it   ////
1855 
//// from http://www.opencores.org/lgpl.shtml                     ////
1856 
////                                                              ////
1857 
//////////////////////////////////////////////////////////////////////
1858 
 
1859 
// binary counter
1860 
 
1861 40 unneback 
`define MODULE cnt_bin_ce_clear
1862 
module `BASE`MODULE (
1863 
`undef MODULE
1864 
 clear, cke, q, rst, clk);
1865 
 
1866 6 unneback 
   parameter length = 4;
1867 
   input clear;
1868 
   input cke;
1869 
   output [length:1] q;
1870 
   input rst;
1871 
   input clk;
1872 
 
1873 
   parameter clear_value = 0;
1874 
   parameter set_value = 1;
1875 
   parameter wrap_value = 0;
1876 
   parameter level1_value = 15;
1877 
 
1878 
   reg  [length:1] qi;
1879 
   wire [length:1] q_next;
1880 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1881 
 
1882 
   always @ (posedge clk or posedge rst)
1883 
     if (rst)
1884 
       qi <= {length{1'b0}};
1885 
     else
1886 
     if (cke)
1887 
       qi <= q_next;
1888 
 
1889 
   assign q = qi;
1890 
 
1891 
endmodule
1892 40 unneback 
`endif
1893 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1894 6 unneback 
//////////////////////////////////////////////////////////////////////
1895 
////                                                              ////
1896 
////  Versatile counter                                           ////
1897 
////                                                              ////
1898 
////  Description                                                 ////
1899 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1900 
////  counter                                                     ////
1901 
////                                                              ////
1902 
////  To Do:                                                      ////
1903 
////   - add LFSR with more taps                                  ////
1904 
////                                                              ////
1905 
////  Author(s):                                                  ////
1906 
////      - Michael Unneback, unneback@opencores.org              ////
1907 
////        ORSoC AB                                              ////
1908 
////                                                              ////
1909 
//////////////////////////////////////////////////////////////////////
1910 
////                                                              ////
1911 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1912 
////                                                              ////
1913 
//// This source file may be used and distributed without         ////
1914 
//// restriction provided that this copyright statement is not    ////
1915 
//// removed from the file and that any derivative work contains  ////
1916 
//// the original copyright notice and the associated disclaimer. ////
1917 
////                                                              ////
1918 
//// This source file is free software; you can redistribute it   ////
1919 
//// and/or modify it under the terms of the GNU Lesser General   ////
1920 
//// Public License as published by the Free Software Foundation; ////
1921 
//// either version 2.1 of the License, or (at your option) any   ////
1922 
//// later version.                                               ////
1923 
////                                                              ////
1924 
//// This source is distributed in the hope that it will be       ////
1925 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1926 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1927 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1928 
//// details.                                                     ////
1929 
////                                                              ////
1930 
//// You should have received a copy of the GNU Lesser General    ////
1931 
//// Public License along with this source; if not, download it   ////
1932 
//// from http://www.opencores.org/lgpl.shtml                     ////
1933 
////                                                              ////
1934 
//////////////////////////////////////////////////////////////////////
1935 
 
1936 
// binary counter
1937 29 unneback 
 
1938 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1939 
module `BASE`MODULE (
1940 
`undef MODULE
1941 
 clear, cke, q, level1, level2, rst, clk);
1942 
 
1943 29 unneback 
   parameter length = 4;
1944 
   input clear;
1945 
   input cke;
1946 
   output [length:1] q;
1947 
   output reg level1;
1948 
   output reg level2;
1949 
   input rst;
1950 
   input clk;
1951 
 
1952 
   parameter clear_value = 0;
1953 
   parameter set_value = 1;
1954 30 unneback 
   parameter wrap_value = 15;
1955 
   parameter level1_value = 8;
1956 
   parameter level2_value = 15;
1957 29 unneback 
 
1958 
   wire rew;
1959 30 unneback 
   assign rew = 1'b0;
1960 29 unneback 
   reg  [length:1] qi;
1961 
   wire [length:1] q_next;
1962 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1963 
 
1964 
   always @ (posedge clk or posedge rst)
1965 
     if (rst)
1966 
       qi <= {length{1'b0}};
1967 
     else
1968 
     if (cke)
1969 
       qi <= q_next;
1970 
 
1971 
   assign q = qi;
1972 
 
1973 
 
1974 
    always @ (posedge clk or posedge rst)
1975 
    if (rst)
1976 
        level1 <= 1'b0;
1977 
    else
1978 
    if (cke)
1979 
    if (clear)
1980 
        level1 <= 1'b0;
1981 
    else if (q_next == level1_value)
1982 
        level1 <= 1'b1;
1983 
    else if (qi == level1_value & rew)
1984 
        level1 <= 1'b0;
1985 
 
1986 
    always @ (posedge clk or posedge rst)
1987 
    if (rst)
1988 
        level2 <= 1'b0;
1989 
    else
1990 
    if (cke)
1991 
    if (clear)
1992 
        level2 <= 1'b0;
1993 
    else if (q_next == level2_value)
1994 
        level2 <= 1'b1;
1995 
    else if (qi == level2_value & rew)
1996 
        level2 <= 1'b0;
1997 
endmodule
1998 40 unneback 
`endif
1999 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2000 29 unneback 
//////////////////////////////////////////////////////////////////////
2001 
////                                                              ////
2002 
////  Versatile counter                                           ////
2003 
////                                                              ////
2004 
////  Description                                                 ////
2005 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2006 
////  counter                                                     ////
2007 
////                                                              ////
2008 
////  To Do:                                                      ////
2009 
////   - add LFSR with more taps                                  ////
2010 
////                                                              ////
2011 
////  Author(s):                                                  ////
2012 
////      - Michael Unneback, unneback@opencores.org              ////
2013 
////        ORSoC AB                                              ////
2014 
////                                                              ////
2015 
//////////////////////////////////////////////////////////////////////
2016 
////                                                              ////
2017 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2018 
////                                                              ////
2019 
//// This source file may be used and distributed without         ////
2020 
//// restriction provided that this copyright statement is not    ////
2021 
//// removed from the file and that any derivative work contains  ////
2022 
//// the original copyright notice and the associated disclaimer. ////
2023 
////                                                              ////
2024 
//// This source file is free software; you can redistribute it   ////
2025 
//// and/or modify it under the terms of the GNU Lesser General   ////
2026 
//// Public License as published by the Free Software Foundation; ////
2027 
//// either version 2.1 of the License, or (at your option) any   ////
2028 
//// later version.                                               ////
2029 
////                                                              ////
2030 
//// This source is distributed in the hope that it will be       ////
2031 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2032 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2033 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2034 
//// details.                                                     ////
2035 
////                                                              ////
2036 
//// You should have received a copy of the GNU Lesser General    ////
2037 
//// Public License along with this source; if not, download it   ////
2038 
//// from http://www.opencores.org/lgpl.shtml                     ////
2039 
////                                                              ////
2040 
//////////////////////////////////////////////////////////////////////
2041 
 
2042 
// binary counter
2043 6 unneback 
 
2044 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
2045 
module `BASE`MODULE (
2046 
`undef MODULE
2047 
 clear, set, cke, rew, q, rst, clk);
2048 
 
2049 6 unneback 
   parameter length = 4;
2050 
   input clear;
2051 
   input set;
2052 
   input cke;
2053 
   input rew;
2054 
   output [length:1] q;
2055 
   input rst;
2056 
   input clk;
2057 
 
2058 
   parameter clear_value = 0;
2059 
   parameter set_value = 1;
2060 
   parameter wrap_value = 0;
2061 
   parameter level1_value = 15;
2062 
 
2063 
   reg  [length:1] qi;
2064 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2065 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2066 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2067 
   assign q_next = rew ? q_next_rew : q_next_fw;
2068 
 
2069 
   always @ (posedge clk or posedge rst)
2070 
     if (rst)
2071 
       qi <= {length{1'b0}};
2072 
     else
2073 
     if (cke)
2074 
       qi <= q_next;
2075 
 
2076 
   assign q = qi;
2077 
 
2078 
endmodule
2079 40 unneback 
`endif
2080 
`ifdef CNT_BIN_CE_REW_L1
2081 6 unneback 
//////////////////////////////////////////////////////////////////////
2082 
////                                                              ////
2083 
////  Versatile counter                                           ////
2084 
////                                                              ////
2085 
////  Description                                                 ////
2086 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2087 
////  counter                                                     ////
2088 
////                                                              ////
2089 
////  To Do:                                                      ////
2090 
////   - add LFSR with more taps                                  ////
2091 
////                                                              ////
2092 
////  Author(s):                                                  ////
2093 
////      - Michael Unneback, unneback@opencores.org              ////
2094 
////        ORSoC AB                                              ////
2095 
////                                                              ////
2096 
//////////////////////////////////////////////////////////////////////
2097 
////                                                              ////
2098 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2099 
////                                                              ////
2100 
//// This source file may be used and distributed without         ////
2101 
//// restriction provided that this copyright statement is not    ////
2102 
//// removed from the file and that any derivative work contains  ////
2103 
//// the original copyright notice and the associated disclaimer. ////
2104 
////                                                              ////
2105 
//// This source file is free software; you can redistribute it   ////
2106 
//// and/or modify it under the terms of the GNU Lesser General   ////
2107 
//// Public License as published by the Free Software Foundation; ////
2108 
//// either version 2.1 of the License, or (at your option) any   ////
2109 
//// later version.                                               ////
2110 
////                                                              ////
2111 
//// This source is distributed in the hope that it will be       ////
2112 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2113 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2114 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2115 
//// details.                                                     ////
2116 
////                                                              ////
2117 
//// You should have received a copy of the GNU Lesser General    ////
2118 
//// Public License along with this source; if not, download it   ////
2119 
//// from http://www.opencores.org/lgpl.shtml                     ////
2120 
////                                                              ////
2121 
//////////////////////////////////////////////////////////////////////
2122 
 
2123 
// binary counter
2124 
 
2125 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
2126 
module `BASE`MODULE (
2127 
`undef MODULE
2128 
 cke, rew, level1, rst, clk);
2129 
 
2130 6 unneback 
   parameter length = 4;
2131 
   input cke;
2132 
   input rew;
2133 
   output reg level1;
2134 
   input rst;
2135 
   input clk;
2136 
 
2137 
   parameter clear_value = 0;
2138 
   parameter set_value = 1;
2139 
   parameter wrap_value = 1;
2140 
   parameter level1_value = 15;
2141 
 
2142 29 unneback 
   wire clear;
2143 30 unneback 
   assign clear = 1'b0;
2144 6 unneback 
   reg  [length:1] qi;
2145 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2146 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2147 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2148 
   assign q_next = rew ? q_next_rew : q_next_fw;
2149 
 
2150 
   always @ (posedge clk or posedge rst)
2151 
     if (rst)
2152 
       qi <= {length{1'b0}};
2153 
     else
2154 
     if (cke)
2155 
       qi <= q_next;
2156 
 
2157 
 
2158 
 
2159 
    always @ (posedge clk or posedge rst)
2160 
    if (rst)
2161 
        level1 <= 1'b0;
2162 
    else
2163 
    if (cke)
2164 29 unneback 
    if (clear)
2165 
        level1 <= 1'b0;
2166 
    else if (q_next == level1_value)
2167 6 unneback 
        level1 <= 1'b1;
2168 
    else if (qi == level1_value & rew)
2169 
        level1 <= 1'b0;
2170 
endmodule
2171 40 unneback 
`endif
2172 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2173 6 unneback 
//////////////////////////////////////////////////////////////////////
2174 
////                                                              ////
2175 
////  Versatile counter                                           ////
2176 
////                                                              ////
2177 
////  Description                                                 ////
2178 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2179 
////  counter                                                     ////
2180 
////                                                              ////
2181 
////  To Do:                                                      ////
2182 
////   - add LFSR with more taps                                  ////
2183 
////                                                              ////
2184 
////  Author(s):                                                  ////
2185 
////      - Michael Unneback, unneback@opencores.org              ////
2186 
////        ORSoC AB                                              ////
2187 
////                                                              ////
2188 
//////////////////////////////////////////////////////////////////////
2189 
////                                                              ////
2190 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2191 
////                                                              ////
2192 
//// This source file may be used and distributed without         ////
2193 
//// restriction provided that this copyright statement is not    ////
2194 
//// removed from the file and that any derivative work contains  ////
2195 
//// the original copyright notice and the associated disclaimer. ////
2196 
////                                                              ////
2197 
//// This source file is free software; you can redistribute it   ////
2198 
//// and/or modify it under the terms of the GNU Lesser General   ////
2199 
//// Public License as published by the Free Software Foundation; ////
2200 
//// either version 2.1 of the License, or (at your option) any   ////
2201 
//// later version.                                               ////
2202 
////                                                              ////
2203 
//// This source is distributed in the hope that it will be       ////
2204 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2205 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2206 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2207 
//// details.                                                     ////
2208 
////                                                              ////
2209 
//// You should have received a copy of the GNU Lesser General    ////
2210 
//// Public License along with this source; if not, download it   ////
2211 
//// from http://www.opencores.org/lgpl.shtml                     ////
2212 
////                                                              ////
2213 
//////////////////////////////////////////////////////////////////////
2214 
 
2215 25 unneback 
// binary counter
2216 
 
2217 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2218 
module `BASE`MODULE (
2219 
`undef MODULE
2220 
 cke, rew, zq, level1, rst, clk);
2221 
 
2222 25 unneback 
   parameter length = 4;
2223 
   input cke;
2224 
   input rew;
2225 
   output reg zq;
2226 
   output reg level1;
2227 
   input rst;
2228 
   input clk;
2229 
 
2230 
   parameter clear_value = 0;
2231 
   parameter set_value = 1;
2232 
   parameter wrap_value = 1;
2233 
   parameter level1_value = 15;
2234 
 
2235 29 unneback 
   wire clear;
2236 30 unneback 
   assign clear = 1'b0;
2237 25 unneback 
   reg  [length:1] qi;
2238 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2239 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2240 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2241 
   assign q_next = rew ? q_next_rew : q_next_fw;
2242 
 
2243 
   always @ (posedge clk or posedge rst)
2244 
     if (rst)
2245 
       qi <= {length{1'b0}};
2246 
     else
2247 
     if (cke)
2248 
       qi <= q_next;
2249 
 
2250 
 
2251 
 
2252 
   always @ (posedge clk or posedge rst)
2253 
     if (rst)
2254 
       zq <= 1'b1;
2255 
     else
2256 
     if (cke)
2257 
       zq <= q_next == {length{1'b0}};
2258 
 
2259 
    always @ (posedge clk or posedge rst)
2260 
    if (rst)
2261 
        level1 <= 1'b0;
2262 
    else
2263 
    if (cke)
2264 29 unneback 
    if (clear)
2265 
        level1 <= 1'b0;
2266 
    else if (q_next == level1_value)
2267 25 unneback 
        level1 <= 1'b1;
2268 
    else if (qi == level1_value & rew)
2269 
        level1 <= 1'b0;
2270 
endmodule
2271 40 unneback 
`endif
2272 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2273 25 unneback 
//////////////////////////////////////////////////////////////////////
2274 
////                                                              ////
2275 
////  Versatile counter                                           ////
2276 
////                                                              ////
2277 
////  Description                                                 ////
2278 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2279 
////  counter                                                     ////
2280 
////                                                              ////
2281 
////  To Do:                                                      ////
2282 
////   - add LFSR with more taps                                  ////
2283 
////                                                              ////
2284 
////  Author(s):                                                  ////
2285 
////      - Michael Unneback, unneback@opencores.org              ////
2286 
////        ORSoC AB                                              ////
2287 
////                                                              ////
2288 
//////////////////////////////////////////////////////////////////////
2289 
////                                                              ////
2290 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2291 
////                                                              ////
2292 
//// This source file may be used and distributed without         ////
2293 
//// restriction provided that this copyright statement is not    ////
2294 
//// removed from the file and that any derivative work contains  ////
2295 
//// the original copyright notice and the associated disclaimer. ////
2296 
////                                                              ////
2297 
//// This source file is free software; you can redistribute it   ////
2298 
//// and/or modify it under the terms of the GNU Lesser General   ////
2299 
//// Public License as published by the Free Software Foundation; ////
2300 
//// either version 2.1 of the License, or (at your option) any   ////
2301 
//// later version.                                               ////
2302 
////                                                              ////
2303 
//// This source is distributed in the hope that it will be       ////
2304 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2305 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2306 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2307 
//// details.                                                     ////
2308 
////                                                              ////
2309 
//// You should have received a copy of the GNU Lesser General    ////
2310 
//// Public License along with this source; if not, download it   ////
2311 
//// from http://www.opencores.org/lgpl.shtml                     ////
2312 
////                                                              ////
2313 
//////////////////////////////////////////////////////////////////////
2314 
 
2315 
// binary counter
2316 
 
2317 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2318 
module `BASE`MODULE (
2319 
`undef MODULE
2320 
 cke, rew, q, zq, level1, rst, clk);
2321 
 
2322 25 unneback 
   parameter length = 4;
2323 
   input cke;
2324 
   input rew;
2325 
   output [length:1] q;
2326 
   output reg zq;
2327 
   output reg level1;
2328 
   input rst;
2329 
   input clk;
2330 
 
2331 
   parameter clear_value = 0;
2332 
   parameter set_value = 1;
2333 
   parameter wrap_value = 1;
2334 
   parameter level1_value = 15;
2335 
 
2336 29 unneback 
   wire clear;
2337 30 unneback 
   assign clear = 1'b0;
2338 25 unneback 
   reg  [length:1] qi;
2339 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2340 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2341 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2342 
   assign q_next = rew ? q_next_rew : q_next_fw;
2343 
 
2344 
   always @ (posedge clk or posedge rst)
2345 
     if (rst)
2346 
       qi <= {length{1'b0}};
2347 
     else
2348 
     if (cke)
2349 
       qi <= q_next;
2350 
 
2351 
   assign q = qi;
2352 
 
2353 
 
2354 
   always @ (posedge clk or posedge rst)
2355 
     if (rst)
2356 
       zq <= 1'b1;
2357 
     else
2358 
     if (cke)
2359 
       zq <= q_next == {length{1'b0}};
2360 
 
2361 
    always @ (posedge clk or posedge rst)
2362 
    if (rst)
2363 
        level1 <= 1'b0;
2364 
    else
2365 
    if (cke)
2366 29 unneback 
    if (clear)
2367 
        level1 <= 1'b0;
2368 
    else if (q_next == level1_value)
2369 25 unneback 
        level1 <= 1'b1;
2370 
    else if (qi == level1_value & rew)
2371 
        level1 <= 1'b0;
2372 
endmodule
2373 40 unneback 
`endif
2374 
`ifdef CNT_LFSR_ZQ
2375 25 unneback 
//////////////////////////////////////////////////////////////////////
2376 
////                                                              ////
2377 
////  Versatile counter                                           ////
2378 
////                                                              ////
2379 
////  Description                                                 ////
2380 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2381 
////  counter                                                     ////
2382 
////                                                              ////
2383 
////  To Do:                                                      ////
2384 
////   - add LFSR with more taps                                  ////
2385 
////                                                              ////
2386 
////  Author(s):                                                  ////
2387 
////      - Michael Unneback, unneback@opencores.org              ////
2388 
////        ORSoC AB                                              ////
2389 
////                                                              ////
2390 
//////////////////////////////////////////////////////////////////////
2391 
////                                                              ////
2392 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2393 
////                                                              ////
2394 
//// This source file may be used and distributed without         ////
2395 
//// restriction provided that this copyright statement is not    ////
2396 
//// removed from the file and that any derivative work contains  ////
2397 
//// the original copyright notice and the associated disclaimer. ////
2398 
////                                                              ////
2399 
//// This source file is free software; you can redistribute it   ////
2400 
//// and/or modify it under the terms of the GNU Lesser General   ////
2401 
//// Public License as published by the Free Software Foundation; ////
2402 
//// either version 2.1 of the License, or (at your option) any   ////
2403 
//// later version.                                               ////
2404 
////                                                              ////
2405 
//// This source is distributed in the hope that it will be       ////
2406 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2407 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2408 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2409 
//// details.                                                     ////
2410 
////                                                              ////
2411 
//// You should have received a copy of the GNU Lesser General    ////
2412 
//// Public License along with this source; if not, download it   ////
2413 
//// from http://www.opencores.org/lgpl.shtml                     ////
2414 
////                                                              ////
2415 
//////////////////////////////////////////////////////////////////////
2416 
 
2417 6 unneback 
// LFSR counter
2418 
 
2419 40 unneback 
`define MODULE cnt_lfsr_zq
2420 
module `BASE`MODULE (
2421 
`undef MODULE
2422 
 zq, rst, clk);
2423 
 
2424 6 unneback 
   parameter length = 4;
2425 
   output reg zq;
2426 
   input rst;
2427 
   input clk;
2428 
 
2429 
   parameter clear_value = 0;
2430 
   parameter set_value = 1;
2431 
   parameter wrap_value = 8;
2432 
   parameter level1_value = 15;
2433 
 
2434 
   reg  [length:1] qi;
2435 
   reg lfsr_fb;
2436 
   wire [length:1] q_next;
2437 
   reg [32:1] polynom;
2438 
   integer i;
2439 
 
2440 
   always @ (qi)
2441 
   begin
2442 
        case (length)
2443 
         2: polynom = 32'b11;                               // 0x3
2444 
         3: polynom = 32'b110;                              // 0x6
2445 
         4: polynom = 32'b1100;                             // 0xC
2446 
         5: polynom = 32'b10100;                            // 0x14
2447 
         6: polynom = 32'b110000;                           // 0x30
2448 
         7: polynom = 32'b1100000;                          // 0x60
2449 
         8: polynom = 32'b10111000;                         // 0xb8
2450 
         9: polynom = 32'b100010000;                        // 0x110
2451 
        10: polynom = 32'b1001000000;                       // 0x240
2452 
        11: polynom = 32'b10100000000;                      // 0x500
2453 
        12: polynom = 32'b100000101001;                     // 0x829
2454 
        13: polynom = 32'b1000000001100;                    // 0x100C
2455 
        14: polynom = 32'b10000000010101;                   // 0x2015
2456 
        15: polynom = 32'b110000000000000;                  // 0x6000
2457 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2458 
        17: polynom = 32'b10010000000000000;                // 0x12000
2459 
        18: polynom = 32'b100000010000000000;               // 0x20400
2460 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2461 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2462 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2463 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2464 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2465 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2466 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2467 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2468 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2469 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2470 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2471 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2472 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2473 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2474 
        default: polynom = 32'b0;
2475 
        endcase
2476 
        lfsr_fb = qi[length];
2477 
        for (i=length-1; i>=1; i=i-1) begin
2478 
            if (polynom[i])
2479 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2480 
        end
2481 
    end
2482 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2483 
 
2484 
   always @ (posedge clk or posedge rst)
2485 
     if (rst)
2486 
       qi <= {length{1'b0}};
2487 
     else
2488 
       qi <= q_next;
2489 
 
2490 
 
2491 
 
2492 
   always @ (posedge clk or posedge rst)
2493 
     if (rst)
2494 
       zq <= 1'b1;
2495 
     else
2496 
       zq <= q_next == {length{1'b0}};
2497 
endmodule
2498 40 unneback 
`endif
2499 75 unneback 
`ifdef CNT_LFSR_CE
2500 
//////////////////////////////////////////////////////////////////////
2501 
////                                                              ////
2502 
////  Versatile counter                                           ////
2503 
////                                                              ////
2504 
////  Description                                                 ////
2505 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2506 
////  counter                                                     ////
2507 
////                                                              ////
2508 
////  To Do:                                                      ////
2509 
////   - add LFSR with more taps                                  ////
2510 
////                                                              ////
2511 
////  Author(s):                                                  ////
2512 
////      - Michael Unneback, unneback@opencores.org              ////
2513 
////        ORSoC AB                                              ////
2514 
////                                                              ////
2515 
//////////////////////////////////////////////////////////////////////
2516 
////                                                              ////
2517 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2518 
////                                                              ////
2519 
//// This source file may be used and distributed without         ////
2520 
//// restriction provided that this copyright statement is not    ////
2521 
//// removed from the file and that any derivative work contains  ////
2522 
//// the original copyright notice and the associated disclaimer. ////
2523 
////                                                              ////
2524 
//// This source file is free software; you can redistribute it   ////
2525 
//// and/or modify it under the terms of the GNU Lesser General   ////
2526 
//// Public License as published by the Free Software Foundation; ////
2527 
//// either version 2.1 of the License, or (at your option) any   ////
2528 
//// later version.                                               ////
2529 
////                                                              ////
2530 
//// This source is distributed in the hope that it will be       ////
2531 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2532 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2533 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2534 
//// details.                                                     ////
2535 
////                                                              ////
2536 
//// You should have received a copy of the GNU Lesser General    ////
2537 
//// Public License along with this source; if not, download it   ////
2538 
//// from http://www.opencores.org/lgpl.shtml                     ////
2539 
////                                                              ////
2540 
//////////////////////////////////////////////////////////////////////
2541 
 
2542 
// LFSR counter
2543 
 
2544 
`define MODULE cnt_lfsr_ce
2545 
module `BASE`MODULE (
2546 
`undef MODULE
2547 
 cke, zq, rst, clk);
2548 
 
2549 
   parameter length = 4;
2550 
   input cke;
2551 
   output reg zq;
2552 
   input rst;
2553 
   input clk;
2554 
 
2555 
   parameter clear_value = 0;
2556 
   parameter set_value = 1;
2557 
   parameter wrap_value = 0;
2558 
   parameter level1_value = 15;
2559 
 
2560 
   reg  [length:1] qi;
2561 
   reg lfsr_fb;
2562 
   wire [length:1] q_next;
2563 
   reg [32:1] polynom;
2564 
   integer i;
2565 
 
2566 
   always @ (qi)
2567 
   begin
2568 
        case (length)
2569 
         2: polynom = 32'b11;                               // 0x3
2570 
         3: polynom = 32'b110;                              // 0x6
2571 
         4: polynom = 32'b1100;                             // 0xC
2572 
         5: polynom = 32'b10100;                            // 0x14
2573 
         6: polynom = 32'b110000;                           // 0x30
2574 
         7: polynom = 32'b1100000;                          // 0x60
2575 
         8: polynom = 32'b10111000;                         // 0xb8
2576 
         9: polynom = 32'b100010000;                        // 0x110
2577 
        10: polynom = 32'b1001000000;                       // 0x240
2578 
        11: polynom = 32'b10100000000;                      // 0x500
2579 
        12: polynom = 32'b100000101001;                     // 0x829
2580 
        13: polynom = 32'b1000000001100;                    // 0x100C
2581 
        14: polynom = 32'b10000000010101;                   // 0x2015
2582 
        15: polynom = 32'b110000000000000;                  // 0x6000
2583 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2584 
        17: polynom = 32'b10010000000000000;                // 0x12000
2585 
        18: polynom = 32'b100000010000000000;               // 0x20400
2586 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2587 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2588 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2589 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2590 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2591 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2592 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2593 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2594 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2595 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2596 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2597 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2598 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2599 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2600 
        default: polynom = 32'b0;
2601 
        endcase
2602 
        lfsr_fb = qi[length];
2603 
        for (i=length-1; i>=1; i=i-1) begin
2604 
            if (polynom[i])
2605 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2606 
        end
2607 
    end
2608 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2609 
 
2610 
   always @ (posedge clk or posedge rst)
2611 
     if (rst)
2612 
       qi <= {length{1'b0}};
2613 
     else
2614 
     if (cke)
2615 
       qi <= q_next;
2616 
 
2617 
 
2618 
 
2619 
   always @ (posedge clk or posedge rst)
2620 
     if (rst)
2621 
       zq <= 1'b1;
2622 
     else
2623 
     if (cke)
2624 
       zq <= q_next == {length{1'b0}};
2625 
endmodule
2626 
`endif
2627 40 unneback 
`ifdef CNT_LFSR_CE_ZQ
2628 6 unneback 
//////////////////////////////////////////////////////////////////////
2629 
////                                                              ////
2630 
////  Versatile counter                                           ////
2631 
////                                                              ////
2632 
////  Description                                                 ////
2633 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2634 
////  counter                                                     ////
2635 
////                                                              ////
2636 
////  To Do:                                                      ////
2637 
////   - add LFSR with more taps                                  ////
2638 
////                                                              ////
2639 
////  Author(s):                                                  ////
2640 
////      - Michael Unneback, unneback@opencores.org              ////
2641 
////        ORSoC AB                                              ////
2642 
////                                                              ////
2643 
//////////////////////////////////////////////////////////////////////
2644 
////                                                              ////
2645 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2646 
////                                                              ////
2647 
//// This source file may be used and distributed without         ////
2648 
//// restriction provided that this copyright statement is not    ////
2649 
//// removed from the file and that any derivative work contains  ////
2650 
//// the original copyright notice and the associated disclaimer. ////
2651 
////                                                              ////
2652 
//// This source file is free software; you can redistribute it   ////
2653 
//// and/or modify it under the terms of the GNU Lesser General   ////
2654 
//// Public License as published by the Free Software Foundation; ////
2655 
//// either version 2.1 of the License, or (at your option) any   ////
2656 
//// later version.                                               ////
2657 
////                                                              ////
2658 
//// This source is distributed in the hope that it will be       ////
2659 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2660 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2661 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2662 
//// details.                                                     ////
2663 
////                                                              ////
2664 
//// You should have received a copy of the GNU Lesser General    ////
2665 
//// Public License along with this source; if not, download it   ////
2666 
//// from http://www.opencores.org/lgpl.shtml                     ////
2667 
////                                                              ////
2668 
//////////////////////////////////////////////////////////////////////
2669 
 
2670 
// LFSR counter
2671 
 
2672 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2673 
module `BASE`MODULE (
2674 
`undef MODULE
2675 
 cke, zq, rst, clk);
2676 
 
2677 6 unneback 
   parameter length = 4;
2678 
   input cke;
2679 
   output reg zq;
2680 
   input rst;
2681 
   input clk;
2682 
 
2683 
   parameter clear_value = 0;
2684 
   parameter set_value = 1;
2685 
   parameter wrap_value = 8;
2686 
   parameter level1_value = 15;
2687 
 
2688 
   reg  [length:1] qi;
2689 
   reg lfsr_fb;
2690 
   wire [length:1] q_next;
2691 
   reg [32:1] polynom;
2692 
   integer i;
2693 
 
2694 
   always @ (qi)
2695 
   begin
2696 
        case (length)
2697 
         2: polynom = 32'b11;                               // 0x3
2698 
         3: polynom = 32'b110;                              // 0x6
2699 
         4: polynom = 32'b1100;                             // 0xC
2700 
         5: polynom = 32'b10100;                            // 0x14
2701 
         6: polynom = 32'b110000;                           // 0x30
2702 
         7: polynom = 32'b1100000;                          // 0x60
2703 
         8: polynom = 32'b10111000;                         // 0xb8
2704 
         9: polynom = 32'b100010000;                        // 0x110
2705 
        10: polynom = 32'b1001000000;                       // 0x240
2706 
        11: polynom = 32'b10100000000;                      // 0x500
2707 
        12: polynom = 32'b100000101001;                     // 0x829
2708 
        13: polynom = 32'b1000000001100;                    // 0x100C
2709 
        14: polynom = 32'b10000000010101;                   // 0x2015
2710 
        15: polynom = 32'b110000000000000;                  // 0x6000
2711 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2712 
        17: polynom = 32'b10010000000000000;                // 0x12000
2713 
        18: polynom = 32'b100000010000000000;               // 0x20400
2714 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2715 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2716 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2717 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2718 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2719 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2720 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2721 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2722 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2723 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2724 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2725 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2726 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2727 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2728 
        default: polynom = 32'b0;
2729 
        endcase
2730 
        lfsr_fb = qi[length];
2731 
        for (i=length-1; i>=1; i=i-1) begin
2732 
            if (polynom[i])
2733 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2734 
        end
2735 
    end
2736 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2737 
 
2738 
   always @ (posedge clk or posedge rst)
2739 
     if (rst)
2740 
       qi <= {length{1'b0}};
2741 
     else
2742 
     if (cke)
2743 
       qi <= q_next;
2744 
 
2745 
 
2746 
 
2747 
   always @ (posedge clk or posedge rst)
2748 
     if (rst)
2749 
       zq <= 1'b1;
2750 
     else
2751 
     if (cke)
2752 
       zq <= q_next == {length{1'b0}};
2753 
endmodule
2754 40 unneback 
`endif
2755 
`ifdef CNT_LFSR_CE_Q
2756 6 unneback 
//////////////////////////////////////////////////////////////////////
2757 
////                                                              ////
2758 
////  Versatile counter                                           ////
2759 
////                                                              ////
2760 
////  Description                                                 ////
2761 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2762 
////  counter                                                     ////
2763 
////                                                              ////
2764 
////  To Do:                                                      ////
2765 
////   - add LFSR with more taps                                  ////
2766 
////                                                              ////
2767 
////  Author(s):                                                  ////
2768 
////      - Michael Unneback, unneback@opencores.org              ////
2769 
////        ORSoC AB                                              ////
2770 
////                                                              ////
2771 
//////////////////////////////////////////////////////////////////////
2772 
////                                                              ////
2773 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2774 
////                                                              ////
2775 
//// This source file may be used and distributed without         ////
2776 
//// restriction provided that this copyright statement is not    ////
2777 
//// removed from the file and that any derivative work contains  ////
2778 
//// the original copyright notice and the associated disclaimer. ////
2779 
////                                                              ////
2780 
//// This source file is free software; you can redistribute it   ////
2781 
//// and/or modify it under the terms of the GNU Lesser General   ////
2782 
//// Public License as published by the Free Software Foundation; ////
2783 
//// either version 2.1 of the License, or (at your option) any   ////
2784 
//// later version.                                               ////
2785 
////                                                              ////
2786 
//// This source is distributed in the hope that it will be       ////
2787 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2788 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2789 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2790 
//// details.                                                     ////
2791 
////                                                              ////
2792 
//// You should have received a copy of the GNU Lesser General    ////
2793 
//// Public License along with this source; if not, download it   ////
2794 
//// from http://www.opencores.org/lgpl.shtml                     ////
2795 
////                                                              ////
2796 
//////////////////////////////////////////////////////////////////////
2797 22 unneback 
 
2798 
// LFSR counter
2799 27 unneback 
 
2800 40 unneback 
`define MODULE cnt_lfsr_ce_q
2801 
module `BASE`MODULE (
2802 
`undef MODULE
2803 
 cke, q, rst, clk);
2804 
 
2805 27 unneback 
   parameter length = 4;
2806 
   input cke;
2807 
   output [length:1] q;
2808 
   input rst;
2809 
   input clk;
2810 
 
2811 
   parameter clear_value = 0;
2812 
   parameter set_value = 1;
2813 
   parameter wrap_value = 8;
2814 
   parameter level1_value = 15;
2815 
 
2816 
   reg  [length:1] qi;
2817 
   reg lfsr_fb;
2818 
   wire [length:1] q_next;
2819 
   reg [32:1] polynom;
2820 
   integer i;
2821 
 
2822 
   always @ (qi)
2823 
   begin
2824 
        case (length)
2825 
         2: polynom = 32'b11;                               // 0x3
2826 
         3: polynom = 32'b110;                              // 0x6
2827 
         4: polynom = 32'b1100;                             // 0xC
2828 
         5: polynom = 32'b10100;                            // 0x14
2829 
         6: polynom = 32'b110000;                           // 0x30
2830 
         7: polynom = 32'b1100000;                          // 0x60
2831 
         8: polynom = 32'b10111000;                         // 0xb8
2832 
         9: polynom = 32'b100010000;                        // 0x110
2833 
        10: polynom = 32'b1001000000;                       // 0x240
2834 
        11: polynom = 32'b10100000000;                      // 0x500
2835 
        12: polynom = 32'b100000101001;                     // 0x829
2836 
        13: polynom = 32'b1000000001100;                    // 0x100C
2837 
        14: polynom = 32'b10000000010101;                   // 0x2015
2838 
        15: polynom = 32'b110000000000000;                  // 0x6000
2839 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2840 
        17: polynom = 32'b10010000000000000;                // 0x12000
2841 
        18: polynom = 32'b100000010000000000;               // 0x20400
2842 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2843 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2844 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2845 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2846 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2847 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2848 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2849 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2850 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2851 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2852 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2853 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2854 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2855 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2856 
        default: polynom = 32'b0;
2857 
        endcase
2858 
        lfsr_fb = qi[length];
2859 
        for (i=length-1; i>=1; i=i-1) begin
2860 
            if (polynom[i])
2861 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2862 
        end
2863 
    end
2864 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2865 
 
2866 
   always @ (posedge clk or posedge rst)
2867 
     if (rst)
2868 
       qi <= {length{1'b0}};
2869 
     else
2870 
     if (cke)
2871 
       qi <= q_next;
2872 
 
2873 
   assign q = qi;
2874 
 
2875 
endmodule
2876 40 unneback 
`endif
2877 
`ifdef CNT_LFSR_CE_CLEAR_Q
2878 27 unneback 
//////////////////////////////////////////////////////////////////////
2879 
////                                                              ////
2880 
////  Versatile counter                                           ////
2881 
////                                                              ////
2882 
////  Description                                                 ////
2883 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2884 
////  counter                                                     ////
2885 
////                                                              ////
2886 
////  To Do:                                                      ////
2887 
////   - add LFSR with more taps                                  ////
2888 
////                                                              ////
2889 
////  Author(s):                                                  ////
2890 
////      - Michael Unneback, unneback@opencores.org              ////
2891 
////        ORSoC AB                                              ////
2892 
////                                                              ////
2893 
//////////////////////////////////////////////////////////////////////
2894 
////                                                              ////
2895 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2896 
////                                                              ////
2897 
//// This source file may be used and distributed without         ////
2898 
//// restriction provided that this copyright statement is not    ////
2899 
//// removed from the file and that any derivative work contains  ////
2900 
//// the original copyright notice and the associated disclaimer. ////
2901 
////                                                              ////
2902 
//// This source file is free software; you can redistribute it   ////
2903 
//// and/or modify it under the terms of the GNU Lesser General   ////
2904 
//// Public License as published by the Free Software Foundation; ////
2905 
//// either version 2.1 of the License, or (at your option) any   ////
2906 
//// later version.                                               ////
2907 
////                                                              ////
2908 
//// This source is distributed in the hope that it will be       ////
2909 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2910 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2911 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2912 
//// details.                                                     ////
2913 
////                                                              ////
2914 
//// You should have received a copy of the GNU Lesser General    ////
2915 
//// Public License along with this source; if not, download it   ////
2916 
//// from http://www.opencores.org/lgpl.shtml                     ////
2917 
////                                                              ////
2918 
//////////////////////////////////////////////////////////////////////
2919 
 
2920 
// LFSR counter
2921 
 
2922 40 unneback 
`define MODULE cnt_lfsr_ce_clear_q
2923 
module `BASE`MODULE (
2924 
`undef MODULE
2925 
 clear, cke, q, rst, clk);
2926 
 
2927 27 unneback 
   parameter length = 4;
2928 
   input clear;
2929 
   input cke;
2930 
   output [length:1] q;
2931 
   input rst;
2932 
   input clk;
2933 
 
2934 
   parameter clear_value = 0;
2935 
   parameter set_value = 1;
2936 
   parameter wrap_value = 8;
2937 
   parameter level1_value = 15;
2938 
 
2939 
   reg  [length:1] qi;
2940 
   reg lfsr_fb;
2941 
   wire [length:1] q_next;
2942 
   reg [32:1] polynom;
2943 
   integer i;
2944 
 
2945 
   always @ (qi)
2946 
   begin
2947 
        case (length)
2948 
         2: polynom = 32'b11;                               // 0x3
2949 
         3: polynom = 32'b110;                              // 0x6
2950 
         4: polynom = 32'b1100;                             // 0xC
2951 
         5: polynom = 32'b10100;                            // 0x14
2952 
         6: polynom = 32'b110000;                           // 0x30
2953 
         7: polynom = 32'b1100000;                          // 0x60
2954 
         8: polynom = 32'b10111000;                         // 0xb8
2955 
         9: polynom = 32'b100010000;                        // 0x110
2956 
        10: polynom = 32'b1001000000;                       // 0x240
2957 
        11: polynom = 32'b10100000000;                      // 0x500
2958 
        12: polynom = 32'b100000101001;                     // 0x829
2959 
        13: polynom = 32'b1000000001100;                    // 0x100C
2960 
        14: polynom = 32'b10000000010101;                   // 0x2015
2961 
        15: polynom = 32'b110000000000000;                  // 0x6000
2962 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2963 
        17: polynom = 32'b10010000000000000;                // 0x12000
2964 
        18: polynom = 32'b100000010000000000;               // 0x20400
2965 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2966 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2967 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2968 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2969 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2970 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2971 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2972 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2973 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2974 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2975 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2976 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2977 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2978 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2979 
        default: polynom = 32'b0;
2980 
        endcase
2981 
        lfsr_fb = qi[length];
2982 
        for (i=length-1; i>=1; i=i-1) begin
2983 
            if (polynom[i])
2984 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2985 
        end
2986 
    end
2987 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2988 
 
2989 
   always @ (posedge clk or posedge rst)
2990 
     if (rst)
2991 
       qi <= {length{1'b0}};
2992 
     else
2993 
     if (cke)
2994 
       qi <= q_next;
2995 
 
2996 
   assign q = qi;
2997 
 
2998 
endmodule
2999 40 unneback 
`endif
3000 
`ifdef CNT_LFSR_CE_Q_ZQ
3001 27 unneback 
//////////////////////////////////////////////////////////////////////
3002 
////                                                              ////
3003 
////  Versatile counter                                           ////
3004 
////                                                              ////
3005 
////  Description                                                 ////
3006 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3007 
////  counter                                                     ////
3008 
////                                                              ////
3009 
////  To Do:                                                      ////
3010 
////   - add LFSR with more taps                                  ////
3011 
////                                                              ////
3012 
////  Author(s):                                                  ////
3013 
////      - Michael Unneback, unneback@opencores.org              ////
3014 
////        ORSoC AB                                              ////
3015 
////                                                              ////
3016 
//////////////////////////////////////////////////////////////////////
3017 
////                                                              ////
3018 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3019 
////                                                              ////
3020 
//// This source file may be used and distributed without         ////
3021 
//// restriction provided that this copyright statement is not    ////
3022 
//// removed from the file and that any derivative work contains  ////
3023 
//// the original copyright notice and the associated disclaimer. ////
3024 
////                                                              ////
3025 
//// This source file is free software; you can redistribute it   ////
3026 
//// and/or modify it under the terms of the GNU Lesser General   ////
3027 
//// Public License as published by the Free Software Foundation; ////
3028 
//// either version 2.1 of the License, or (at your option) any   ////
3029 
//// later version.                                               ////
3030 
////                                                              ////
3031 
//// This source is distributed in the hope that it will be       ////
3032 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3033 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3034 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3035 
//// details.                                                     ////
3036 
////                                                              ////
3037 
//// You should have received a copy of the GNU Lesser General    ////
3038 
//// Public License along with this source; if not, download it   ////
3039 
//// from http://www.opencores.org/lgpl.shtml                     ////
3040 
////                                                              ////
3041 
//////////////////////////////////////////////////////////////////////
3042 
 
3043 
// LFSR counter
3044 22 unneback 
 
3045 40 unneback 
`define MODULE cnt_lfsr_ce_q_zq
3046 
module `BASE`MODULE (
3047 
`undef MODULE
3048 
 cke, q, zq, rst, clk);
3049 
 
3050 22 unneback 
   parameter length = 4;
3051 
   input cke;
3052 
   output [length:1] q;
3053 
   output reg zq;
3054 
   input rst;
3055 
   input clk;
3056 
 
3057 
   parameter clear_value = 0;
3058 
   parameter set_value = 1;
3059 
   parameter wrap_value = 8;
3060 
   parameter level1_value = 15;
3061 
 
3062 
   reg  [length:1] qi;
3063 
   reg lfsr_fb;
3064 
   wire [length:1] q_next;
3065 
   reg [32:1] polynom;
3066 
   integer i;
3067 
 
3068 
   always @ (qi)
3069 
   begin
3070 
        case (length)
3071 
         2: polynom = 32'b11;                               // 0x3
3072 
         3: polynom = 32'b110;                              // 0x6
3073 
         4: polynom = 32'b1100;                             // 0xC
3074 
         5: polynom = 32'b10100;                            // 0x14
3075 
         6: polynom = 32'b110000;                           // 0x30
3076 
         7: polynom = 32'b1100000;                          // 0x60
3077 
         8: polynom = 32'b10111000;                         // 0xb8
3078 
         9: polynom = 32'b100010000;                        // 0x110
3079 
        10: polynom = 32'b1001000000;                       // 0x240
3080 
        11: polynom = 32'b10100000000;                      // 0x500
3081 
        12: polynom = 32'b100000101001;                     // 0x829
3082 
        13: polynom = 32'b1000000001100;                    // 0x100C
3083 
        14: polynom = 32'b10000000010101;                   // 0x2015
3084 
        15: polynom = 32'b110000000000000;                  // 0x6000
3085 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3086 
        17: polynom = 32'b10010000000000000;                // 0x12000
3087 
        18: polynom = 32'b100000010000000000;               // 0x20400
3088 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3089 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3090 22 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3091 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3092 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3093 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3094 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3095 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3096 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3097 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3098 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3099 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3100 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3101 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3102 
        default: polynom = 32'b0;
3103 
        endcase
3104 
        lfsr_fb = qi[length];
3105 
        for (i=length-1; i>=1; i=i-1) begin
3106 
            if (polynom[i])
3107 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3108 
        end
3109 
    end
3110 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3111 
 
3112 
   always @ (posedge clk or posedge rst)
3113 
     if (rst)
3114 
       qi <= {length{1'b0}};
3115 
     else
3116 
     if (cke)
3117 
       qi <= q_next;
3118 
 
3119 
   assign q = qi;
3120 
 
3121 
 
3122 
   always @ (posedge clk or posedge rst)
3123 
     if (rst)
3124 
       zq <= 1'b1;
3125 
     else
3126 
     if (cke)
3127 
       zq <= q_next == {length{1'b0}};
3128 
endmodule
3129 40 unneback 
`endif
3130 
`ifdef CNT_LFSR_CE_REW_L1
3131 22 unneback 
//////////////////////////////////////////////////////////////////////
3132 
////                                                              ////
3133 
////  Versatile counter                                           ////
3134 
////                                                              ////
3135 
////  Description                                                 ////
3136 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3137 
////  counter                                                     ////
3138 
////                                                              ////
3139 
////  To Do:                                                      ////
3140 
////   - add LFSR with more taps                                  ////
3141 
////                                                              ////
3142 
////  Author(s):                                                  ////
3143 
////      - Michael Unneback, unneback@opencores.org              ////
3144 
////        ORSoC AB                                              ////
3145 
////                                                              ////
3146 
//////////////////////////////////////////////////////////////////////
3147 
////                                                              ////
3148 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3149 
////                                                              ////
3150 
//// This source file may be used and distributed without         ////
3151 
//// restriction provided that this copyright statement is not    ////
3152 
//// removed from the file and that any derivative work contains  ////
3153 
//// the original copyright notice and the associated disclaimer. ////
3154 
////                                                              ////
3155 
//// This source file is free software; you can redistribute it   ////
3156 
//// and/or modify it under the terms of the GNU Lesser General   ////
3157 
//// Public License as published by the Free Software Foundation; ////
3158 
//// either version 2.1 of the License, or (at your option) any   ////
3159 
//// later version.                                               ////
3160 
////                                                              ////
3161 
//// This source is distributed in the hope that it will be       ////
3162 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3163 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3164 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3165 
//// details.                                                     ////
3166 
////                                                              ////
3167 
//// You should have received a copy of the GNU Lesser General    ////
3168 
//// Public License along with this source; if not, download it   ////
3169 
//// from http://www.opencores.org/lgpl.shtml                     ////
3170 
////                                                              ////
3171 
//////////////////////////////////////////////////////////////////////
3172 6 unneback 
 
3173 
// LFSR counter
3174 
 
3175 40 unneback 
`define MODULE cnt_lfsr_ce_rew_l1
3176 
module `BASE`MODULE (
3177 
`undef MODULE
3178 
 cke, rew, level1, rst, clk);
3179 
 
3180 6 unneback 
   parameter length = 4;
3181 
   input cke;
3182 
   input rew;
3183 
   output reg level1;
3184 
   input rst;
3185 
   input clk;
3186 
 
3187 
   parameter clear_value = 0;
3188 
   parameter set_value = 1;
3189 
   parameter wrap_value = 8;
3190 
   parameter level1_value = 15;
3191 
 
3192 29 unneback 
   wire clear;
3193 30 unneback 
   assign clear = 1'b0;
3194 6 unneback 
   reg  [length:1] qi;
3195 
   reg lfsr_fb, lfsr_fb_rew;
3196 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
3197 
   reg [32:1] polynom_rew;
3198 
   integer j;
3199 
   reg [32:1] polynom;
3200 
   integer i;
3201 
 
3202 
   always @ (qi)
3203 
   begin
3204 
        case (length)
3205 
         2: polynom = 32'b11;                               // 0x3
3206 
         3: polynom = 32'b110;                              // 0x6
3207 
         4: polynom = 32'b1100;                             // 0xC
3208 
         5: polynom = 32'b10100;                            // 0x14
3209 
         6: polynom = 32'b110000;                           // 0x30
3210 
         7: polynom = 32'b1100000;                          // 0x60
3211 
         8: polynom = 32'b10111000;                         // 0xb8
3212 
         9: polynom = 32'b100010000;                        // 0x110
3213 
        10: polynom = 32'b1001000000;                       // 0x240
3214 
        11: polynom = 32'b10100000000;                      // 0x500
3215 
        12: polynom = 32'b100000101001;                     // 0x829
3216 
        13: polynom = 32'b1000000001100;                    // 0x100C
3217 
        14: polynom = 32'b10000000010101;                   // 0x2015
3218 
        15: polynom = 32'b110000000000000;                  // 0x6000
3219 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3220 
        17: polynom = 32'b10010000000000000;                // 0x12000
3221 
        18: polynom = 32'b100000010000000000;               // 0x20400
3222 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3223 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3224 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3225 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3226 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3227 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3228 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3229 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3230 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3231 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3232 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3233 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3234 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3235 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3236 
        default: polynom = 32'b0;
3237 
        endcase
3238 
        lfsr_fb = qi[length];
3239 
        for (i=length-1; i>=1; i=i-1) begin
3240 
            if (polynom[i])
3241 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3242 
        end
3243 
    end
3244 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3245 
   always @ (qi)
3246 
   begin
3247 
        case (length)
3248 
         2: polynom_rew = 32'b11;
3249 
         3: polynom_rew = 32'b110;
3250 
         4: polynom_rew = 32'b1100;
3251 
         5: polynom_rew = 32'b10100;
3252 
         6: polynom_rew = 32'b110000;
3253 
         7: polynom_rew = 32'b1100000;
3254 
         8: polynom_rew = 32'b10111000;
3255 
         9: polynom_rew = 32'b100010000;
3256 
        10: polynom_rew = 32'b1001000000;
3257 
        11: polynom_rew = 32'b10100000000;
3258 
        12: polynom_rew = 32'b100000101001;
3259 
        13: polynom_rew = 32'b1000000001100;
3260 
        14: polynom_rew = 32'b10000000010101;
3261 
        15: polynom_rew = 32'b110000000000000;
3262 
        16: polynom_rew = 32'b1101000000001000;
3263 
        17: polynom_rew = 32'b10010000000000000;
3264 
        18: polynom_rew = 32'b100000010000000000;
3265 
        19: polynom_rew = 32'b1000000000000100011;
3266 
        20: polynom_rew = 32'b10000010000000000000;
3267 
        21: polynom_rew = 32'b101000000000000000000;
3268 
        22: polynom_rew = 32'b1100000000000000000000;
3269 
        23: polynom_rew = 32'b10000100000000000000000;
3270 
        24: polynom_rew = 32'b111000010000000000000000;
3271 
        25: polynom_rew = 32'b1001000000000000000000000;
3272 
        26: polynom_rew = 32'b10000000000000000000100011;
3273 
        27: polynom_rew = 32'b100000000000000000000010011;
3274 
        28: polynom_rew = 32'b1100100000000000000000000000;
3275 
        29: polynom_rew = 32'b10100000000000000000000000000;
3276 
        30: polynom_rew = 32'b100000000000000000000000101001;
3277 
        31: polynom_rew = 32'b1001000000000000000000000000000;
3278 
        32: polynom_rew = 32'b10000000001000000000000000000011;
3279 
        default: polynom_rew = 32'b0;
3280 
        endcase
3281 
        // rotate left
3282 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3283 
        lfsr_fb_rew = qi[length];
3284 
        for (i=length-1; i>=1; i=i-1) begin
3285 
            if (polynom_rew[i])
3286 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3287 
        end
3288 
    end
3289 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3290 
   assign q_next = rew ? q_next_rew : q_next_fw;
3291 
 
3292 
   always @ (posedge clk or posedge rst)
3293 
     if (rst)
3294 
       qi <= {length{1'b0}};
3295 
     else
3296 
     if (cke)
3297 
       qi <= q_next;
3298 
 
3299 
 
3300 
 
3301 
    always @ (posedge clk or posedge rst)
3302 
    if (rst)
3303 
        level1 <= 1'b0;
3304 
    else
3305 
    if (cke)
3306 29 unneback 
    if (clear)
3307 
        level1 <= 1'b0;
3308 
    else if (q_next == level1_value)
3309 6 unneback 
        level1 <= 1'b1;
3310 
    else if (qi == level1_value & rew)
3311 
        level1 <= 1'b0;
3312 
endmodule
3313 40 unneback 
`endif
3314 
`ifdef CNT_GRAY
3315 6 unneback 
//////////////////////////////////////////////////////////////////////
3316 
////                                                              ////
3317 
////  Versatile counter                                           ////
3318 
////                                                              ////
3319 
////  Description                                                 ////
3320 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3321 
////  counter                                                     ////
3322 
////                                                              ////
3323 
////  To Do:                                                      ////
3324 
////   - add LFSR with more taps                                  ////
3325 
////                                                              ////
3326 
////  Author(s):                                                  ////
3327 
////      - Michael Unneback, unneback@opencores.org              ////
3328 
////        ORSoC AB                                              ////
3329 
////                                                              ////
3330 
//////////////////////////////////////////////////////////////////////
3331 
////                                                              ////
3332 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3333 
////                                                              ////
3334 
//// This source file may be used and distributed without         ////
3335 
//// restriction provided that this copyright statement is not    ////
3336 
//// removed from the file and that any derivative work contains  ////
3337 
//// the original copyright notice and the associated disclaimer. ////
3338 
////                                                              ////
3339 
//// This source file is free software; you can redistribute it   ////
3340 
//// and/or modify it under the terms of the GNU Lesser General   ////
3341 
//// Public License as published by the Free Software Foundation; ////
3342 
//// either version 2.1 of the License, or (at your option) any   ////
3343 
//// later version.                                               ////
3344 
////                                                              ////
3345 
//// This source is distributed in the hope that it will be       ////
3346 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3347 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3348 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3349 
//// details.                                                     ////
3350 
////                                                              ////
3351 
//// You should have received a copy of the GNU Lesser General    ////
3352 
//// Public License along with this source; if not, download it   ////
3353 
//// from http://www.opencores.org/lgpl.shtml                     ////
3354 
////                                                              ////
3355 
//////////////////////////////////////////////////////////////////////
3356 
 
3357 
// GRAY counter
3358 
 
3359 40 unneback 
`define MODULE cnt_gray
3360 
module `BASE`MODULE (
3361 
`undef MODULE
3362 
 q, rst, clk);
3363 
 
3364 6 unneback 
   parameter length = 4;
3365 
   output reg [length:1] q;
3366 
   input rst;
3367 
   input clk;
3368 
 
3369 
   parameter clear_value = 0;
3370 
   parameter set_value = 1;
3371 
   parameter wrap_value = 8;
3372 
   parameter level1_value = 15;
3373 
 
3374 
   reg  [length:1] qi;
3375 
   wire [length:1] q_next;
3376 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3377 
 
3378 
   always @ (posedge clk or posedge rst)
3379 
     if (rst)
3380 
       qi <= {length{1'b0}};
3381 
     else
3382 
       qi <= q_next;
3383 
 
3384 
   always @ (posedge clk or posedge rst)
3385 
     if (rst)
3386 
       q <= {length{1'b0}};
3387 
     else
3388 
         q <= (q_next>>1) ^ q_next;
3389 
 
3390 
endmodule
3391 40 unneback 
`endif
3392 
`ifdef CNT_GRAY_CE
3393 6 unneback 
//////////////////////////////////////////////////////////////////////
3394 
////                                                              ////
3395 
////  Versatile counter                                           ////
3396 
////                                                              ////
3397 
////  Description                                                 ////
3398 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3399 
////  counter                                                     ////
3400 
////                                                              ////
3401 
////  To Do:                                                      ////
3402 
////   - add LFSR with more taps                                  ////
3403 
////                                                              ////
3404 
////  Author(s):                                                  ////
3405 
////      - Michael Unneback, unneback@opencores.org              ////
3406 
////        ORSoC AB                                              ////
3407 
////                                                              ////
3408 
//////////////////////////////////////////////////////////////////////
3409 
////                                                              ////
3410 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3411 
////                                                              ////
3412 
//// This source file may be used and distributed without         ////
3413 
//// restriction provided that this copyright statement is not    ////
3414 
//// removed from the file and that any derivative work contains  ////
3415 
//// the original copyright notice and the associated disclaimer. ////
3416 
////                                                              ////
3417 
//// This source file is free software; you can redistribute it   ////
3418 
//// and/or modify it under the terms of the GNU Lesser General   ////
3419 
//// Public License as published by the Free Software Foundation; ////
3420 
//// either version 2.1 of the License, or (at your option) any   ////
3421 
//// later version.                                               ////
3422 
////                                                              ////
3423 
//// This source is distributed in the hope that it will be       ////
3424 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3425 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3426 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3427 
//// details.                                                     ////
3428 
////                                                              ////
3429 
//// You should have received a copy of the GNU Lesser General    ////
3430 
//// Public License along with this source; if not, download it   ////
3431 
//// from http://www.opencores.org/lgpl.shtml                     ////
3432 
////                                                              ////
3433 
//////////////////////////////////////////////////////////////////////
3434 
 
3435 
// GRAY counter
3436 
 
3437 40 unneback 
`define MODULE cnt_gray_ce
3438 
module `BASE`MODULE (
3439 
`undef MODULE
3440 
 cke, q, rst, clk);
3441 
 
3442 6 unneback 
   parameter length = 4;
3443 
   input cke;
3444 
   output reg [length:1] q;
3445 
   input rst;
3446 
   input clk;
3447 
 
3448 
   parameter clear_value = 0;
3449 
   parameter set_value = 1;
3450 
   parameter wrap_value = 8;
3451 
   parameter level1_value = 15;
3452 
 
3453 
   reg  [length:1] qi;
3454 
   wire [length:1] q_next;
3455 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3456 
 
3457 
   always @ (posedge clk or posedge rst)
3458 
     if (rst)
3459 
       qi <= {length{1'b0}};
3460 
     else
3461 
     if (cke)
3462 
       qi <= q_next;
3463 
 
3464 
   always @ (posedge clk or posedge rst)
3465 
     if (rst)
3466 
       q <= {length{1'b0}};
3467 
     else
3468 
       if (cke)
3469 
         q <= (q_next>>1) ^ q_next;
3470 
 
3471 
endmodule
3472 40 unneback 
`endif
3473 
`ifdef CNT_GRAY_CE_BIN
3474 6 unneback 
//////////////////////////////////////////////////////////////////////
3475 
////                                                              ////
3476 
////  Versatile counter                                           ////
3477 
////                                                              ////
3478 
////  Description                                                 ////
3479 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3480 
////  counter                                                     ////
3481 
////                                                              ////
3482 
////  To Do:                                                      ////
3483 
////   - add LFSR with more taps                                  ////
3484 
////                                                              ////
3485 
////  Author(s):                                                  ////
3486 
////      - Michael Unneback, unneback@opencores.org              ////
3487 
////        ORSoC AB                                              ////
3488 
////                                                              ////
3489 
//////////////////////////////////////////////////////////////////////
3490 
////                                                              ////
3491 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3492 
////                                                              ////
3493 
//// This source file may be used and distributed without         ////
3494 
//// restriction provided that this copyright statement is not    ////
3495 
//// removed from the file and that any derivative work contains  ////
3496 
//// the original copyright notice and the associated disclaimer. ////
3497 
////                                                              ////
3498 
//// This source file is free software; you can redistribute it   ////
3499 
//// and/or modify it under the terms of the GNU Lesser General   ////
3500 
//// Public License as published by the Free Software Foundation; ////
3501 
//// either version 2.1 of the License, or (at your option) any   ////
3502 
//// later version.                                               ////
3503 
////                                                              ////
3504 
//// This source is distributed in the hope that it will be       ////
3505 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3506 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3507 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3508 
//// details.                                                     ////
3509 
////                                                              ////
3510 
//// You should have received a copy of the GNU Lesser General    ////
3511 
//// Public License along with this source; if not, download it   ////
3512 
//// from http://www.opencores.org/lgpl.shtml                     ////
3513 
////                                                              ////
3514 
//////////////////////////////////////////////////////////////////////
3515 
 
3516 
// GRAY counter
3517 
 
3518 40 unneback 
`define MODULE cnt_gray_ce_bin
3519 
module `BASE`MODULE (
3520 
`undef MODULE
3521 
 cke, q, q_bin, rst, clk);
3522 
 
3523 6 unneback 
   parameter length = 4;
3524 
   input cke;
3525 
   output reg [length:1] q;
3526 
   output [length:1] q_bin;
3527 
   input rst;
3528 
   input clk;
3529 
 
3530 
   parameter clear_value = 0;
3531 
   parameter set_value = 1;
3532 
   parameter wrap_value = 8;
3533 
   parameter level1_value = 15;
3534 
 
3535 
   reg  [length:1] qi;
3536 
   wire [length:1] q_next;
3537 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3538 
 
3539 
   always @ (posedge clk or posedge rst)
3540 
     if (rst)
3541 
       qi <= {length{1'b0}};
3542 
     else
3543 
     if (cke)
3544 
       qi <= q_next;
3545 
 
3546 
   always @ (posedge clk or posedge rst)
3547 
     if (rst)
3548 
       q <= {length{1'b0}};
3549 
     else
3550 
       if (cke)
3551 
         q <= (q_next>>1) ^ q_next;
3552 
 
3553 
   assign q_bin = qi;
3554 
 
3555 
endmodule
3556 40 unneback 
`endif
3557 6 unneback 
//////////////////////////////////////////////////////////////////////
3558 
////                                                              ////
3559 
////  Versatile library, counters                                 ////
3560 
////                                                              ////
3561 
////  Description                                                 ////
3562 
////  counters                                                    ////
3563 
////                                                              ////
3564 
////                                                              ////
3565 
////  To Do:                                                      ////
3566 
////   - add more counters                                        ////
3567 
////                                                              ////
3568 
////  Author(s):                                                  ////
3569 
////      - Michael Unneback, unneback@opencores.org              ////
3570 
////        ORSoC AB                                              ////
3571 
////                                                              ////
3572 
//////////////////////////////////////////////////////////////////////
3573 
////                                                              ////
3574 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3575 
////                                                              ////
3576 
//// This source file may be used and distributed without         ////
3577 
//// restriction provided that this copyright statement is not    ////
3578 
//// removed from the file and that any derivative work contains  ////
3579 
//// the original copyright notice and the associated disclaimer. ////
3580 
////                                                              ////
3581 
//// This source file is free software; you can redistribute it   ////
3582 
//// and/or modify it under the terms of the GNU Lesser General   ////
3583 
//// Public License as published by the Free Software Foundation; ////
3584 
//// either version 2.1 of the License, or (at your option) any   ////
3585 
//// later version.                                               ////
3586 
////                                                              ////
3587 
//// This source is distributed in the hope that it will be       ////
3588 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3589 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3590 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3591 
//// details.                                                     ////
3592 
////                                                              ////
3593 
//// You should have received a copy of the GNU Lesser General    ////
3594 
//// Public License along with this source; if not, download it   ////
3595 
//// from http://www.opencores.org/lgpl.shtml                     ////
3596 
////                                                              ////
3597 
//////////////////////////////////////////////////////////////////////
3598 
 
3599 40 unneback 
`ifdef CNT_SHREG_WRAP
3600 
`define MODULE cnt_shreg_wrap
3601 
module `BASE`MODULE ( q, rst, clk);
3602 
`undef MODULE
3603 6 unneback 
 
3604 
   parameter length = 4;
3605 
   output reg [0:length-1] q;
3606 
   input rst;
3607 
   input clk;
3608 
 
3609 
    always @ (posedge clk or posedge rst)
3610 
    if (rst)
3611 
        q <= {1'b1,{length-1{1'b0}}};
3612 
    else
3613 
        q <= {q[length-1],q[0:length-2]};
3614 
 
3615 
endmodule
3616 40 unneback 
`endif
3617 6 unneback 
 
3618 40 unneback 
`ifdef CNT_SHREG_CE_WRAP
3619 
`define MODULE cnt_shreg_ce_wrap
3620 
module `BASE`MODULE ( cke, q, rst, clk);
3621 
`undef MODULE
3622 6 unneback 
 
3623 
   parameter length = 4;
3624 
   input cke;
3625 
   output reg [0:length-1] q;
3626 
   input rst;
3627 
   input clk;
3628 
 
3629 
    always @ (posedge clk or posedge rst)
3630 
    if (rst)
3631 
        q <= {1'b1,{length-1{1'b0}}};
3632 
    else
3633 
        if (cke)
3634 
            q <= {q[length-1],q[0:length-2]};
3635 
 
3636 
endmodule
3637 40 unneback 
`endif
3638 6 unneback 
 
3639 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR
3640 
`define MODULE cnt_shreg_ce_clear
3641 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3642 
`undef MODULE
3643 6 unneback 
 
3644 
   parameter length = 4;
3645 
   input cke, clear;
3646 
   output reg [0:length-1] q;
3647 
   input rst;
3648 
   input clk;
3649 
 
3650 
    always @ (posedge clk or posedge rst)
3651 
    if (rst)
3652 
        q <= {1'b1,{length-1{1'b0}}};
3653 
    else
3654 
        if (cke)
3655 
            if (clear)
3656 
                q <= {1'b1,{length-1{1'b0}}};
3657 
            else
3658 
                q <= q >> 1;
3659 
 
3660 
endmodule
3661 40 unneback 
`endif
3662 6 unneback 
 
3663 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3664 
`define MODULE cnt_shreg_ce_clear_wrap
3665 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3666 
`undef MODULE
3667 6 unneback 
 
3668 
   parameter length = 4;
3669 
   input cke, clear;
3670 
   output reg [0:length-1] q;
3671 
   input rst;
3672 
   input clk;
3673 
 
3674 
    always @ (posedge clk or posedge rst)
3675 
    if (rst)
3676 
        q <= {1'b1,{length-1{1'b0}}};
3677 
    else
3678 
        if (cke)
3679 
            if (clear)
3680 
                q <= {1'b1,{length-1{1'b0}}};
3681 
            else
3682 
            q <= {q[length-1],q[0:length-2]};
3683 
 
3684 
endmodule
3685 40 unneback 
`endif
3686 6 unneback 
//////////////////////////////////////////////////////////////////////
3687 
////                                                              ////
3688 
////  Versatile library, memories                                 ////
3689 
////                                                              ////
3690 
////  Description                                                 ////
3691 
////  memories                                                    ////
3692 
////                                                              ////
3693 
////                                                              ////
3694 
////  To Do:                                                      ////
3695 
////   - add more memory types                                    ////
3696 
////                                                              ////
3697 
////  Author(s):                                                  ////
3698 
////      - Michael Unneback, unneback@opencores.org              ////
3699 
////        ORSoC AB                                              ////
3700 
////                                                              ////
3701 
//////////////////////////////////////////////////////////////////////
3702 
////                                                              ////
3703 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3704 
////                                                              ////
3705 
//// This source file may be used and distributed without         ////
3706 
//// restriction provided that this copyright statement is not    ////
3707 
//// removed from the file and that any derivative work contains  ////
3708 
//// the original copyright notice and the associated disclaimer. ////
3709 
////                                                              ////
3710 
//// This source file is free software; you can redistribute it   ////
3711 
//// and/or modify it under the terms of the GNU Lesser General   ////
3712 
//// Public License as published by the Free Software Foundation; ////
3713 
//// either version 2.1 of the License, or (at your option) any   ////
3714 
//// later version.                                               ////
3715 
////                                                              ////
3716 
//// This source is distributed in the hope that it will be       ////
3717 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3718 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3719 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3720 
//// details.                                                     ////
3721 
////                                                              ////
3722 
//// You should have received a copy of the GNU Lesser General    ////
3723 
//// Public License along with this source; if not, download it   ////
3724 
//// from http://www.opencores.org/lgpl.shtml                     ////
3725 
////                                                              ////
3726 
//////////////////////////////////////////////////////////////////////
3727 
 
3728 40 unneback 
`ifdef ROM_INIT
3729 6 unneback 
/// ROM
3730 40 unneback 
`define MODULE rom_init
3731 
module `BASE`MODULE ( adr, q, clk);
3732 
`undef MODULE
3733 6 unneback 
 
3734 7 unneback 
   parameter data_width = 32;
3735 
   parameter addr_width = 8;
3736 75 unneback 
   parameter mem_size = 1<<addr_width;
3737 7 unneback 
   input [(addr_width-1):0]       adr;
3738 
   output reg [(data_width-1):0] q;
3739 
   input                         clk;
3740 75 unneback 
   reg [data_width-1:0] rom [mem_size-1:0];
3741 7 unneback 
   parameter memory_file = "vl_rom.vmem";
3742 
   initial
3743 
     begin
3744 
        $readmemh(memory_file, rom);
3745 
     end
3746 
 
3747 
   always @ (posedge clk)
3748 
     q <= rom[adr];
3749 6 unneback 
 
3750 7 unneback 
endmodule
3751 40 unneback 
`endif
3752 7 unneback 
 
3753 40 unneback 
`ifdef RAM
3754 
`define MODULE ram
3755 6 unneback 
// Single port RAM
3756 40 unneback 
module `BASE`MODULE ( d, adr, we, q, clk);
3757 
`undef MODULE
3758 6 unneback 
 
3759 
   parameter data_width = 32;
3760 
   parameter addr_width = 8;
3761 75 unneback 
   parameter mem_size = 1<<addr_width;
3762 6 unneback 
   input [(data_width-1):0]      d;
3763 
   input [(addr_width-1):0]       adr;
3764 
   input                         we;
3765 7 unneback 
   output reg [(data_width-1):0] q;
3766 6 unneback 
   input                         clk;
3767 75 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0];
3768 7 unneback 
   parameter init = 0;
3769 
   parameter memory_file = "vl_ram.vmem";
3770 
   generate if (init) begin : init_mem
3771 
   initial
3772 
     begin
3773 
        $readmemh(memory_file, ram);
3774 
     end
3775 
   end
3776 
   endgenerate
3777 
 
3778 6 unneback 
   always @ (posedge clk)
3779 
   begin
3780 
   if (we)
3781 
     ram[adr] <= d;
3782 
   q <= ram[adr];
3783 
   end
3784 
 
3785 
endmodule
3786 40 unneback 
`endif
3787 6 unneback 
 
3788 40 unneback 
`ifdef RAM_BE
3789 
`define MODULE ram_be
3790 91 unneback 
module `BASE`MODULE ( d, adr, be, we, q, clk);
3791 40 unneback 
`undef MODULE
3792 
 
3793 7 unneback 
   parameter data_width = 32;
3794 72 unneback 
   parameter addr_width = 6;
3795 75 unneback 
   parameter mem_size = 1<<addr_width;
3796 7 unneback 
   input [(data_width-1):0]      d;
3797 
   input [(addr_width-1):0]       adr;
3798 73 unneback 
   input [(data_width/8)-1:0]    be;
3799 7 unneback 
   input                         we;
3800 
   output reg [(data_width-1):0] q;
3801 
   input                         clk;
3802 
 
3803 85 unneback 
 
3804 65 unneback 
`ifdef SYSTEMVERILOG
3805 95 unneback 
    // use a multi-dimensional packed array
3806 
    //t o model individual bytes within the word
3807 
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
3808 65 unneback 
`else
3809 85 unneback 
    reg [data_width-1:0] ram [mem_size-1:0];
3810 
    wire [data_width/8-1:0] cke;
3811 65 unneback 
`endif
3812 
 
3813 60 unneback 
   parameter memory_init = 0;
3814 7 unneback 
   parameter memory_file = "vl_ram.vmem";
3815 60 unneback 
   generate if (memory_init) begin : init_mem
3816 7 unneback 
   initial
3817 
     begin
3818 
        $readmemh(memory_file, ram);
3819 
     end
3820 
   end
3821 
   endgenerate
3822 
 
3823 60 unneback 
`ifdef SYSTEMVERILOG
3824 
 
3825 
always_ff@(posedge clk)
3826 
begin
3827 95 unneback 
    if(we) begin
3828 86 unneback 
        if(be[3]) ram[adr][3] <= d[31:24];
3829 
        if(be[2]) ram[adr][2] <= d[23:16];
3830 
        if(be[1]) ram[adr][1] <= d[15:8];
3831 
        if(be[0]) ram[adr][0] <= d[7:0];
3832 60 unneback 
    end
3833 90 unneback 
        q <= ram[adr];
3834 60 unneback 
end
3835 
 
3836 
`else
3837 
 
3838 85 unneback 
assign cke = {data_width/8{we}} & be;
3839 7 unneback 
   genvar i;
3840 85 unneback 
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
3841 7 unneback 
      always @ (posedge clk)
3842 85 unneback 
      if (cke[i])
3843 7 unneback 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3844 
   end
3845 
   endgenerate
3846 
 
3847 
   always @ (posedge clk)
3848 
      q <= ram[adr];
3849 
 
3850 60 unneback 
`endif
3851 
 
3852 93 unneback 
`ifdef verilator
3853 85 unneback 
   // Function to access RAM (for use by Verilator).
3854 
   function [31:0] get_mem;
3855 
      // verilator public
3856 90 unneback 
      input [addr_width-1:0]             addr;
3857 85 unneback 
      get_mem = ram[addr];
3858 
   endfunction // get_mem
3859 
 
3860 
   // Function to write RAM (for use by Verilator).
3861 
   function set_mem;
3862 
      // verilator public
3863 90 unneback 
      input [addr_width-1:0]             addr;
3864 
      input [data_width-1:0]             data;
3865 85 unneback 
      ram[addr] = data;
3866 
   endfunction // set_mem
3867 93 unneback 
`endif
3868 85 unneback 
 
3869 7 unneback 
endmodule
3870 40 unneback 
`endif
3871 7 unneback 
 
3872 6 unneback 
`ifdef ACTEL
3873 48 unneback 
        // ACTEL FPGA should not use logic to handle rw collision
3874 6 unneback 
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
3875 
`else
3876 
        `define SYN
3877 
`endif
3878 
 
3879 40 unneback 
`ifdef DPRAM_1R1W
3880 
`define MODULE dpram_1r1w
3881 
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3882 
`undef MODULE
3883 6 unneback 
   parameter data_width = 32;
3884 
   parameter addr_width = 8;
3885 75 unneback 
   parameter mem_size = 1<<addr_width;
3886 6 unneback 
   input [(data_width-1):0]      d_a;
3887 
   input [(addr_width-1):0]       adr_a;
3888 
   input [(addr_width-1):0]       adr_b;
3889 
   input                         we_a;
3890 
   output [(data_width-1):0]      q_b;
3891 
   input                         clk_a, clk_b;
3892 
   reg [(addr_width-1):0]         adr_b_reg;
3893 75 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
3894 7 unneback 
 
3895 
   parameter init = 0;
3896 
   parameter memory_file = "vl_ram.vmem";
3897 
   generate if (init) begin : init_mem
3898 
   initial
3899 
     begin
3900 
        $readmemh(memory_file, ram);
3901 
     end
3902 
   end
3903 
   endgenerate
3904 
 
3905 6 unneback 
   always @ (posedge clk_a)
3906 
   if (we_a)
3907 
     ram[adr_a] <= d_a;
3908 
   always @ (posedge clk_b)
3909 
   adr_b_reg <= adr_b;
3910 
   assign q_b = ram[adr_b_reg];
3911 40 unneback 
 
3912 6 unneback 
endmodule
3913 40 unneback 
`endif
3914 6 unneback 
 
3915 40 unneback 
`ifdef DPRAM_2R1W
3916 
`define MODULE dpram_2r1w
3917 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3918 
`undef MODULE
3919 
 
3920 6 unneback 
   parameter data_width = 32;
3921 
   parameter addr_width = 8;
3922 75 unneback 
   parameter mem_size = 1<<addr_width;
3923 6 unneback 
   input [(data_width-1):0]      d_a;
3924 
   input [(addr_width-1):0]       adr_a;
3925 
   input [(addr_width-1):0]       adr_b;
3926 
   input                         we_a;
3927 
   output [(data_width-1):0]      q_b;
3928 
   output reg [(data_width-1):0] q_a;
3929 
   input                         clk_a, clk_b;
3930 
   reg [(data_width-1):0]         q_b;
3931 75 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
3932 7 unneback 
 
3933 
   parameter init = 0;
3934 
   parameter memory_file = "vl_ram.vmem";
3935 
   generate if (init) begin : init_mem
3936 
   initial
3937 
     begin
3938 
        $readmemh(memory_file, ram);
3939 
     end
3940 
   end
3941 
   endgenerate
3942 
 
3943 6 unneback 
   always @ (posedge clk_a)
3944 
     begin
3945 
        q_a <= ram[adr_a];
3946 
        if (we_a)
3947 
             ram[adr_a] <= d_a;
3948 
     end
3949 
   always @ (posedge clk_b)
3950 
          q_b <= ram[adr_b];
3951 
endmodule
3952 40 unneback 
`endif
3953 6 unneback 
 
3954 40 unneback 
`ifdef DPRAM_2R2W
3955 
`define MODULE dpram_2r2w
3956 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3957 
`undef MODULE
3958 
 
3959 6 unneback 
   parameter data_width = 32;
3960 
   parameter addr_width = 8;
3961 75 unneback 
   parameter mem_size = 1<<addr_width;
3962 6 unneback 
   input [(data_width-1):0]      d_a;
3963 
   input [(addr_width-1):0]       adr_a;
3964 
   input [(addr_width-1):0]       adr_b;
3965 
   input                         we_a;
3966 
   output [(data_width-1):0]      q_b;
3967 
   input [(data_width-1):0]       d_b;
3968 
   output reg [(data_width-1):0] q_a;
3969 
   input                         we_b;
3970 
   input                         clk_a, clk_b;
3971 
   reg [(data_width-1):0]         q_b;
3972 75 unneback 
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
3973 7 unneback 
 
3974 
   parameter init = 0;
3975 
   parameter memory_file = "vl_ram.vmem";
3976 
   generate if (init) begin : init_mem
3977 
   initial
3978 
     begin
3979 
        $readmemh(memory_file, ram);
3980 
     end
3981 
   end
3982 
   endgenerate
3983 
 
3984 6 unneback 
   always @ (posedge clk_a)
3985 
     begin
3986 
        q_a <= ram[adr_a];
3987 
        if (we_a)
3988 
             ram[adr_a] <= d_a;
3989 
     end
3990 
   always @ (posedge clk_b)
3991 
     begin
3992 
        q_b <= ram[adr_b];
3993 
        if (we_b)
3994 
          ram[adr_b] <= d_b;
3995 
     end
3996 
endmodule
3997 40 unneback 
`endif
3998 6 unneback 
 
3999 83 unneback 
 
4000 75 unneback 
`ifdef DPRAM_BE_2R2W
4001 
`define MODULE dpram_be_2r2w
4002 92 unneback 
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
4003 75 unneback 
`undef MODULE
4004 
 
4005 
   parameter a_data_width = 32;
4006 
   parameter a_addr_width = 8;
4007 95 unneback 
   parameter b_data_width = 64; //a_data_width;
4008 91 unneback 
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
4009 95 unneback 
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
4010 
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
4011 91 unneback 
 
4012 95 unneback 
   parameter init = 0;
4013 
   parameter memory_file = "vl_ram.vmem";
4014 
 
4015 75 unneback 
   input [(a_data_width-1):0]      d_a;
4016 91 unneback 
   input [(a_addr_width-1):0]       adr_a;
4017 
   input [(a_data_width/8-1):0]    be_a;
4018 
   input                           we_a;
4019 75 unneback 
   output reg [(a_data_width-1):0] q_a;
4020 91 unneback 
   input [(b_data_width-1):0]       d_b;
4021 
   input [(b_addr_width-1):0]       adr_b;
4022 92 unneback 
   input [(b_data_width/8-1):0]    be_b;
4023 
   input                           we_b;
4024 
   output reg [(b_data_width-1):0]          q_b;
4025 91 unneback 
   input                           clk_a, clk_b;
4026 75 unneback 
 
4027 91 unneback 
`ifdef SYSTEMVERILOG
4028 
// use a multi-dimensional packed array
4029 
//to model individual bytes within the word
4030 
 
4031 75 unneback 
generate
4032 91 unneback 
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
4033 75 unneback 
 
4034 95 unneback 
    logic [0:3][7:0] ram [0:mem_size-1];
4035 
 
4036 
    initial
4037 
        if (init)
4038 
            $readmemh(memory_file, ram);
4039 91 unneback 
 
4040 
    always_ff@(posedge clk_a)
4041 
    begin
4042 
        if(we_a) begin
4043 
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
4044 
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
4045 
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
4046 
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
4047 
        end
4048 
    end
4049 
 
4050 92 unneback 
    always@(posedge clk_a)
4051 
        q_a = ram[adr_a];
4052 91 unneback 
 
4053 
    always_ff@(posedge clk_b)
4054 92 unneback 
    begin
4055 
        if(we_b) begin
4056 
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
4057 
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
4058 
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
4059 
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
4060 
        end
4061 
    end
4062 91 unneback 
 
4063 92 unneback 
    always@(posedge clk_b)
4064 
        q_b = ram[adr_b];
4065 91 unneback 
 
4066 75 unneback 
end
4067 
endgenerate
4068 
 
4069 95 unneback 
generate
4070 
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
4071 
 
4072 
    logic [0:7][7:0] ram [0:mem_size-1];
4073 
 
4074 
    initial
4075 
        if (init)
4076 
            $readmemh(memory_file, ram);
4077 
 
4078 
    always_ff@(posedge clk_a)
4079 
    begin
4080 
        if(we_a) begin
4081 
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
4082 
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
4083 
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
4084 
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
4085 
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
4086 
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
4087 
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
4088 
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
4089 
        end
4090 
    end
4091 
 
4092 
    always@(posedge clk_a)
4093 
        q_a = ram[adr_a];
4094 
 
4095 
    always_ff@(posedge clk_b)
4096 
    begin
4097 
        if(we_b) begin
4098 
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
4099 
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
4100 
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
4101 
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
4102 
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
4103 
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
4104 
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
4105 
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
4106 
        end
4107 
    end
4108 
 
4109 
    always@(posedge clk_b)
4110 
        q_b = ram[adr_b];
4111 
 
4112 
end
4113 
endgenerate
4114 
 
4115 
generate
4116 
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
4117 
logic [31:0] temp;
4118 
`define MODULE dpram_be_2r2w
4119 
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
4120 
`undef MODULE
4121 
dpram6464 (
4122 
    .d_a(d_a),
4123 
    .q_a(q_a),
4124 
    .adr_a(adr_a),
4125 
    .be_a(be_a),
4126 
    .we_a(we_a),
4127 
    .clk_a(clk_a),
4128 
    .d_b({d_b,d_b}),
4129 
    .q_b(temp),
4130 
    .adr_b(adr_b),
4131 
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
4132 
    .we_b(we_b),
4133 
    .clk_b(clk_b)
4134 
);
4135 
 
4136 
always_comb
4137 
    if (adr_b[0])
4138 
        q_b = temp[31:16];
4139 
    else
4140 
        q_b = temp[15:0];
4141 
 
4142 
end
4143 
endgenerate
4144 
 
4145 
generate
4146 
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
4147 
logic [63:0] temp;
4148 
`define MODULE dpram_be_2r2w
4149 
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
4150 
`undef MODULE
4151 
dpram6464 (
4152 
    .d_a({d_a,d_a}),
4153 
    .q_a(temp),
4154 
    .adr_a(adr_a[a_addr_width-1:1]),
4155 
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
4156 
    .we_a(we_a),
4157 
    .clk_a(clk_a),
4158 
    .d_b(d_b),
4159 
    .q_b(q_b),
4160 
    .adr_b(adr_b),
4161 
    .be_b(be_b),
4162 
    .we_b(we_b),
4163 
    .clk_b(clk_b)
4164 
);
4165 
 
4166 
always_comb
4167 
    if (adr_a[0])
4168 
        q_a = temp[63:32];
4169 
    else
4170 
        q_a = temp[31:0];
4171 
 
4172 
end
4173 
endgenerate
4174 
 
4175 91 unneback 
`else
4176 92 unneback 
    // This modules requires SystemVerilog
4177 91 unneback 
`endif
4178 75 unneback 
endmodule
4179 
`endif
4180 
 
4181 91 unneback 
`ifdef CAM
4182 6 unneback 
// Content addresable memory, CAM
4183 91 unneback 
`endif
4184 6 unneback 
 
4185 40 unneback 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
4186 6 unneback 
// FIFO
4187 40 unneback 
`define MODULE fifo_1r1w_fill_level_sync
4188 
module `BASE`MODULE (
4189 
`undef MODULE
4190 25 unneback 
    d, wr, fifo_full,
4191 
    q, rd, fifo_empty,
4192 
    fill_level,
4193 
    clk, rst
4194 
    );
4195 
 
4196 
parameter data_width = 18;
4197 
parameter addr_width = 4;
4198 6 unneback 
 
4199 25 unneback 
// write side
4200 
input  [data_width-1:0] d;
4201 
input                   wr;
4202 
output                  fifo_full;
4203 
// read side
4204 
output [data_width-1:0] q;
4205 
input                   rd;
4206 
output                  fifo_empty;
4207 
// common
4208 
output [addr_width:0]   fill_level;
4209 
input rst, clk;
4210 
 
4211 
wire [addr_width:1] wadr, radr;
4212 
 
4213 40 unneback 
`define MODULE cnt_bin_ce
4214 
`BASE`MODULE
4215 25 unneback 
    # ( .length(addr_width))
4216 
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
4217 40 unneback 
`BASE`MODULE
4218 25 unneback 
    # (.length(addr_width))
4219 
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
4220 40 unneback 
`undef MODULE
4221 25 unneback 
 
4222 40 unneback 
`define MODULE dpram_1r1w
4223 
`BASE`MODULE
4224 25 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4225 
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
4226 40 unneback 
`undef MODULE
4227 25 unneback 
 
4228 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
4229 
`BASE`MODULE
4230 27 unneback 
    # (.length(addr_width+1), .level1_value(1<<addr_width))
4231 25 unneback 
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
4232 40 unneback 
`undef MODULE
4233 25 unneback 
endmodule
4234 40 unneback 
`endif
4235 25 unneback 
 
4236 40 unneback 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
4237 27 unneback 
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
4238 
// RAM is supposed to be larger than the two FIFOs
4239 
// LFSR counters used adr pointers
4240 40 unneback 
`define MODULE fifo_2r2w_sync_simplex
4241 
module `BASE`MODULE (
4242 
`undef MODULE
4243 27 unneback 
    // a side
4244 
    a_d, a_wr, a_fifo_full,
4245 
    a_q, a_rd, a_fifo_empty,
4246 
    a_fill_level,
4247 
    // b side
4248 
    b_d, b_wr, b_fifo_full,
4249 
    b_q, b_rd, b_fifo_empty,
4250 
    b_fill_level,
4251 
    // common
4252 
    clk, rst
4253 
    );
4254 
parameter data_width = 8;
4255 
parameter addr_width = 5;
4256 
parameter fifo_full_level = (1<<addr_width)-1;
4257 
 
4258 
// a side
4259 
input  [data_width-1:0] a_d;
4260 
input                   a_wr;
4261 
output                  a_fifo_full;
4262 
output [data_width-1:0] a_q;
4263 
input                   a_rd;
4264 
output                  a_fifo_empty;
4265 
output [addr_width-1:0] a_fill_level;
4266 
 
4267 
// b side
4268 
input  [data_width-1:0] b_d;
4269 
input                   b_wr;
4270 
output                  b_fifo_full;
4271 
output [data_width-1:0] b_q;
4272 
input                   b_rd;
4273 
output                  b_fifo_empty;
4274 
output [addr_width-1:0] b_fill_level;
4275 
 
4276 
input                   clk;
4277 
input                   rst;
4278 
 
4279 
// adr_gen
4280 
wire [addr_width:1] a_wadr, a_radr;
4281 
wire [addr_width:1] b_wadr, b_radr;
4282 
// dpram
4283 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4284 
 
4285 40 unneback 
`define MODULE cnt_lfsr_ce
4286 
`BASE`MODULE
4287 27 unneback 
    # ( .length(addr_width))
4288 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
4289 
 
4290 40 unneback 
`BASE`MODULE
4291 27 unneback 
    # (.length(addr_width))
4292 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
4293 
 
4294 40 unneback 
`BASE`MODULE
4295 27 unneback 
    # ( .length(addr_width))
4296 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
4297 
 
4298 40 unneback 
`BASE`MODULE
4299 27 unneback 
    # (.length(addr_width))
4300 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
4301 40 unneback 
`undef MODULE
4302 27 unneback 
 
4303 
// mux read or write adr to DPRAM
4304 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
4305 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
4306 
 
4307 40 unneback 
`define MODULE dpram_2r2w
4308 
`BASE`MODULE
4309 27 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4310 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4311 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4312 40 unneback 
`undef MODULE
4313 
 
4314 
`define MODULE cnt_bin_ce_rew_zq_l1
4315 
`BASE`MODULE
4316 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4317 27 unneback 
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
4318 
 
4319 40 unneback 
`BASE`MODULE
4320 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4321 27 unneback 
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
4322 40 unneback 
`undef MODULE
4323 27 unneback 
 
4324 
endmodule
4325 40 unneback 
`endif
4326 27 unneback 
 
4327 40 unneback 
`ifdef FIFO_CMP_ASYNC
4328 
`define MODULE fifo_cmp_async
4329 
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
4330 
`undef MODULE
4331 6 unneback 
 
4332 11 unneback 
   parameter addr_width = 4;
4333 
   parameter N = addr_width-1;
4334 6 unneback 
 
4335 
   parameter Q1 = 2'b00;
4336 
   parameter Q2 = 2'b01;
4337 
   parameter Q3 = 2'b11;
4338 
   parameter Q4 = 2'b10;
4339 
 
4340 
   parameter going_empty = 1'b0;
4341 
   parameter going_full  = 1'b1;
4342 
 
4343 
   input [N:0]  wptr, rptr;
4344 14 unneback 
   output       fifo_empty;
4345 6 unneback 
   output       fifo_full;
4346 
   input        wclk, rclk, rst;
4347 
 
4348 
`ifndef GENERATE_DIRECTION_AS_LATCH
4349 
   wire direction;
4350 
`endif
4351 
`ifdef GENERATE_DIRECTION_AS_LATCH
4352 
   reg direction;
4353 
`endif
4354 
   reg  direction_set, direction_clr;
4355 
 
4356 
   wire async_empty, async_full;
4357 
   wire fifo_full2;
4358 14 unneback 
   wire fifo_empty2;
4359 6 unneback 
 
4360 
   // direction_set
4361 
   always @ (wptr[N:N-1] or rptr[N:N-1])
4362 
     case ({wptr[N:N-1],rptr[N:N-1]})
4363 
       {Q1,Q2} : direction_set <= 1'b1;
4364 
       {Q2,Q3} : direction_set <= 1'b1;
4365 
       {Q3,Q4} : direction_set <= 1'b1;
4366 
       {Q4,Q1} : direction_set <= 1'b1;
4367 
       default : direction_set <= 1'b0;
4368 
     endcase
4369 
 
4370 
   // direction_clear
4371 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
4372 
     if (rst)
4373 
       direction_clr <= 1'b1;
4374 
     else
4375 
       case ({wptr[N:N-1],rptr[N:N-1]})
4376 
         {Q2,Q1} : direction_clr <= 1'b1;
4377 
         {Q3,Q2} : direction_clr <= 1'b1;
4378 
         {Q4,Q3} : direction_clr <= 1'b1;
4379 
         {Q1,Q4} : direction_clr <= 1'b1;
4380 
         default : direction_clr <= 1'b0;
4381 
       endcase
4382 
 
4383 40 unneback 
`define MODULE dff_sr
4384 6 unneback 
`ifndef GENERATE_DIRECTION_AS_LATCH
4385 40 unneback 
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
4386 6 unneback 
`endif
4387 
 
4388 
`ifdef GENERATE_DIRECTION_AS_LATCH
4389 
   always @ (posedge direction_set or posedge direction_clr)
4390 
     if (direction_clr)
4391 
       direction <= going_empty;
4392 
     else
4393 
       direction <= going_full;
4394 
`endif
4395 
 
4396 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
4397 
   assign async_full  = (wptr == rptr) && (direction==going_full);
4398 
 
4399 40 unneback 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
4400 
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
4401 
`undef MODULE
4402 6 unneback 
 
4403 
/*
4404 
   always @ (posedge wclk or posedge rst or posedge async_full)
4405 
     if (rst)
4406 
       {fifo_full, fifo_full2} <= 2'b00;
4407 
     else if (async_full)
4408 
       {fifo_full, fifo_full2} <= 2'b11;
4409 
     else
4410 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
4411 
*/
4412 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
4413 6 unneback 
     if (async_empty)
4414 
       {fifo_empty, fifo_empty2} <= 2'b11;
4415 
     else
4416 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
4417 40 unneback 
`define MODULE dff
4418 
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
4419 
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
4420 
`undef MODULE
4421 27 unneback 
endmodule // async_compb
4422 40 unneback 
`endif
4423 6 unneback 
 
4424 40 unneback 
`ifdef FIFO_1R1W_ASYNC
4425 
`define MODULE fifo_1r1w_async
4426 
module `BASE`MODULE (
4427 
`undef MODULE
4428 6 unneback 
    d, wr, fifo_full, wr_clk, wr_rst,
4429 
    q, rd, fifo_empty, rd_clk, rd_rst
4430 
    );
4431 
 
4432 
parameter data_width = 18;
4433 
parameter addr_width = 4;
4434 
 
4435 
// write side
4436 
input  [data_width-1:0] d;
4437 
input                   wr;
4438 
output                  fifo_full;
4439 
input                   wr_clk;
4440 
input                   wr_rst;
4441 
// read side
4442 
output [data_width-1:0] q;
4443 
input                   rd;
4444 
output                  fifo_empty;
4445 
input                   rd_clk;
4446 
input                   rd_rst;
4447 
 
4448 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
4449 23 unneback 
 
4450 40 unneback 
`define MODULE cnt_gray_ce_bin
4451 
`BASE`MODULE
4452 6 unneback 
    # ( .length(addr_width))
4453 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
4454 
 
4455 40 unneback 
`BASE`MODULE
4456 6 unneback 
    # (.length(addr_width))
4457 23 unneback 
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
4458 40 unneback 
`undef MODULE
4459 6 unneback 
 
4460 40 unneback 
`define MODULE dpram_1r1w
4461 
`BASE`MODULE
4462 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4463 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
4464 40 unneback 
`undef MODULE
4465 6 unneback 
 
4466 40 unneback 
`define MODULE fifo_cmp_async
4467 
`BASE`MODULE
4468 6 unneback 
    # (.addr_width(addr_width))
4469 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
4470 40 unneback 
`undef MODULE
4471 6 unneback 
 
4472 
endmodule
4473 40 unneback 
`endif
4474 6 unneback 
 
4475 40 unneback 
`ifdef FIFO_2R2W_ASYNC
4476 
`define MODULE fifo_2r2w_async
4477 
module `BASE`MODULE (
4478 
`undef MODULE
4479 6 unneback 
    // a side
4480 
    a_d, a_wr, a_fifo_full,
4481 
    a_q, a_rd, a_fifo_empty,
4482 
    a_clk, a_rst,
4483 
    // b side
4484 
    b_d, b_wr, b_fifo_full,
4485 
    b_q, b_rd, b_fifo_empty,
4486 
    b_clk, b_rst
4487 
    );
4488 
 
4489 
parameter data_width = 18;
4490 
parameter addr_width = 4;
4491 
 
4492 
// a side
4493 
input  [data_width-1:0] a_d;
4494 
input                   a_wr;
4495 
output                  a_fifo_full;
4496 
output [data_width-1:0] a_q;
4497 
input                   a_rd;
4498 
output                  a_fifo_empty;
4499 
input                   a_clk;
4500 
input                   a_rst;
4501 
 
4502 
// b side
4503 
input  [data_width-1:0] b_d;
4504 
input                   b_wr;
4505 
output                  b_fifo_full;
4506 
output [data_width-1:0] b_q;
4507 
input                   b_rd;
4508 
output                  b_fifo_empty;
4509 
input                   b_clk;
4510 
input                   b_rst;
4511 
 
4512 40 unneback 
`define MODULE fifo_1r1w_async
4513 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4514 6 unneback 
vl_fifo_1r1w_async_a (
4515 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4516 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4517 
    );
4518 
 
4519 40 unneback 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4520 6 unneback 
vl_fifo_1r1w_async_b (
4521 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4522 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4523 
    );
4524 40 unneback 
`undef MODULE
4525 
 
4526 6 unneback 
endmodule
4527 40 unneback 
`endif
4528 6 unneback 
 
4529 40 unneback 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4530 
`define MODULE fifo_2r2w_async_simplex
4531 
module `BASE`MODULE (
4532 
`undef MODULE
4533 6 unneback 
    // a side
4534 
    a_d, a_wr, a_fifo_full,
4535 
    a_q, a_rd, a_fifo_empty,
4536 
    a_clk, a_rst,
4537 
    // b side
4538 
    b_d, b_wr, b_fifo_full,
4539 
    b_q, b_rd, b_fifo_empty,
4540 
    b_clk, b_rst
4541 
    );
4542 
 
4543 
parameter data_width = 18;
4544 
parameter addr_width = 4;
4545 
 
4546 
// a side
4547 
input  [data_width-1:0] a_d;
4548 
input                   a_wr;
4549 
output                  a_fifo_full;
4550 
output [data_width-1:0] a_q;
4551 
input                   a_rd;
4552 
output                  a_fifo_empty;
4553 
input                   a_clk;
4554 
input                   a_rst;
4555 
 
4556 
// b side
4557 
input  [data_width-1:0] b_d;
4558 
input                   b_wr;
4559 
output                  b_fifo_full;
4560 
output [data_width-1:0] b_q;
4561 
input                   b_rd;
4562 
output                  b_fifo_empty;
4563 
input                   b_clk;
4564 
input                   b_rst;
4565 
 
4566 
// adr_gen
4567 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4568 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4569 
// dpram
4570 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4571 
 
4572 40 unneback 
`define MODULE cnt_gray_ce_bin
4573 
`BASE`MODULE
4574 6 unneback 
    # ( .length(addr_width))
4575 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4576 
 
4577 40 unneback 
`BASE`MODULE
4578 6 unneback 
    # (.length(addr_width))
4579 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4580 
 
4581 40 unneback 
`BASE`MODULE
4582 6 unneback 
    # ( .length(addr_width))
4583 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4584 
 
4585 40 unneback 
`BASE`MODULE
4586 6 unneback 
    # (.length(addr_width))
4587 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4588 40 unneback 
`undef MODULE
4589 6 unneback 
 
4590 
// mux read or write adr to DPRAM
4591 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4592 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4593 
 
4594 40 unneback 
`define MODULE dpram_2r2w
4595 
`BASE`MODULE
4596 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4597 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4598 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4599 40 unneback 
`undef MODULE
4600 6 unneback 
 
4601 40 unneback 
`define MODULE fifo_cmp_async
4602 
`BASE`MODULE
4603 6 unneback 
    # (.addr_width(addr_width))
4604 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4605 
 
4606 40 unneback 
`BASE`MODULE
4607 6 unneback 
    # (.addr_width(addr_width))
4608 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4609 40 unneback 
`undef MODULE
4610 6 unneback 
 
4611 
endmodule
4612 40 unneback 
`endif
4613 48 unneback 
 
4614 
`ifdef REG_FILE
4615 
`define MODULE reg_file
4616 
module `BASE`MODULE (
4617 
`undef MODULE
4618 
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4619 
);
4620 
parameter data_width = 32;
4621 
parameter addr_width = 5;
4622 
input [addr_width-1:0] a1, a2, a3;
4623 
input [data_width-1:0] wd3;
4624 
input we3;
4625 
output [data_width-1:0] rd1, rd2;
4626 
input clk;
4627 
 
4628 
`ifdef ACTEL
4629 
reg [data_width-1:0] wd3_reg;
4630 
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4631 
reg we3_reg;
4632 
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
4633 
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
4634 
always @ (posedge clk or posedge rst)
4635 
if (rst)
4636 
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4637 
else
4638 
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4639 
 
4640 
    always @ (negedge clk)
4641 
    if (we3_reg)
4642 
        ram1[a3_reg] <= wd3;
4643 
    always @ (posedge clk)
4644 
        a1_reg <= a1;
4645 
    assign rd1 = ram1[a1_reg];
4646 
 
4647 
    always @ (negedge clk)
4648 
    if (we3_reg)
4649 
        ram2[a3_reg] <= wd3;
4650 
    always @ (posedge clk)
4651 
        a2_reg <= a2;
4652 
    assign rd2 = ram2[a2_reg];
4653 
 
4654 
`else
4655 
 
4656 
`define MODULE dpram_1r1w
4657 
`BASE`MODULE
4658 
    # ( .data_width(data_width), .addr_width(addr_width))
4659 
    ram1 (
4660 
        .d_a(wd3),
4661 
        .adr_a(a3),
4662 
        .we_a(we3),
4663 
        .clk_a(clk),
4664 
        .q_b(rd1),
4665 
        .adr_b(a1),
4666 
        .clk_b(clk) );
4667 
 
4668 
`BASE`MODULE
4669 
    # ( .data_width(data_width), .addr_width(addr_width))
4670 
    ram2 (
4671 
        .d_a(wd3),
4672 
        .adr_a(a3),
4673 
        .we_a(we3),
4674 
        .clk_a(clk),
4675 
        .q_b(rd2),
4676 
        .adr_b(a2),
4677 
        .clk_b(clk) );
4678 
`undef MODULE
4679 
 
4680 
`endif
4681 
 
4682 
endmodule
4683 
`endif
4684 12 unneback 
//////////////////////////////////////////////////////////////////////
4685 
////                                                              ////
4686 
////  Versatile library, wishbone stuff                           ////
4687 
////                                                              ////
4688 
////  Description                                                 ////
4689 
////  Wishbone compliant modules                                  ////
4690 
////                                                              ////
4691 
////                                                              ////
4692 
////  To Do:                                                      ////
4693 
////   -                                                          ////
4694 
////                                                              ////
4695 
////  Author(s):                                                  ////
4696 
////      - Michael Unneback, unneback@opencores.org              ////
4697 
////        ORSoC AB                                              ////
4698 
////                                                              ////
4699 
//////////////////////////////////////////////////////////////////////
4700 
////                                                              ////
4701 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4702 
////                                                              ////
4703 
//// This source file may be used and distributed without         ////
4704 
//// restriction provided that this copyright statement is not    ////
4705 
//// removed from the file and that any derivative work contains  ////
4706 
//// the original copyright notice and the associated disclaimer. ////
4707 
////                                                              ////
4708 
//// This source file is free software; you can redistribute it   ////
4709 
//// and/or modify it under the terms of the GNU Lesser General   ////
4710 
//// Public License as published by the Free Software Foundation; ////
4711 
//// either version 2.1 of the License, or (at your option) any   ////
4712 
//// later version.                                               ////
4713 
////                                                              ////
4714 
//// This source is distributed in the hope that it will be       ////
4715 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4716 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4717 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4718 
//// details.                                                     ////
4719 
////                                                              ////
4720 
//// You should have received a copy of the GNU Lesser General    ////
4721 
//// Public License along with this source; if not, download it   ////
4722 
//// from http://www.opencores.org/lgpl.shtml                     ////
4723 
////                                                              ////
4724 
//////////////////////////////////////////////////////////////////////
4725 
 
4726 75 unneback 
`ifdef WB_ADR_INC
4727 
// async wb3 - wb3 bridge
4728 
`timescale 1ns/1ns
4729 
`define MODULE wb_adr_inc
4730 85 unneback 
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
4731 75 unneback 
`undef MODULE
4732 83 unneback 
parameter adr_width = 10;
4733 
parameter max_burst_width = 4;
4734 85 unneback 
input cyc_i, stb_i, we_i;
4735 83 unneback 
input [2:0] cti_i;
4736 
input [1:0] bte_i;
4737 
input [adr_width-1:0] adr_i;
4738 
output [adr_width-1:0] adr_o;
4739 
output ack_o;
4740 
input clk, rst;
4741 75 unneback 
 
4742 83 unneback 
reg [adr_width-1:0] adr;
4743 90 unneback 
wire [max_burst_width-1:0] to_adr;
4744 91 unneback 
reg [max_burst_width-1:0] last_adr;
4745 92 unneback 
reg last_cycle;
4746 
localparam idle_or_eoc = 1'b0;
4747 
localparam cyc_or_ws   = 1'b1;
4748 90 unneback 
 
4749 91 unneback 
always @ (posedge clk or posedge rst)
4750 
if (rst)
4751 
    last_adr <= {max_burst_width{1'b0}};
4752 
else
4753 
    if (stb_i)
4754 92 unneback 
        last_adr <=adr_o[max_burst_width-1:0];
4755 91 unneback 
 
4756 83 unneback 
generate
4757 
if (max_burst_width==0) begin : inst_0
4758 
    reg ack_o;
4759 
    assign adr_o = adr_i;
4760 75 unneback 
    always @ (posedge clk or posedge rst)
4761 83 unneback 
    if (rst)
4762 
        ack_o <= 1'b0;
4763 
    else
4764 
        ack_o <= cyc_i & stb_i & !ack_o;
4765 
end else begin
4766 
 
4767 
    always @ (posedge clk or posedge rst)
4768 
    if (rst)
4769 92 unneback 
        last_cycle <= idle_or_eoc;
4770 83 unneback 
    else
4771 92 unneback 
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
4772 
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
4773 
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
4774 
                      cyc_or_ws; // cyc
4775 
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
4776 85 unneback 
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
4777 91 unneback 
                                        (!stb_i) ? last_adr :
4778 92 unneback 
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
4779 85 unneback 
                                        adr[max_burst_width-1:0];
4780 92 unneback 
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
4781 83 unneback 
end
4782 
endgenerate
4783 
 
4784 
generate
4785 
if (max_burst_width==2) begin : inst_2
4786 
    always @ (posedge clk or posedge rst)
4787 
    if (rst)
4788 
        adr <= 2'h0;
4789 
    else
4790 
        if (cyc_i & stb_i)
4791 
            adr[1:0] <= to_adr[1:0] + 2'd1;
4792 75 unneback 
        else
4793 83 unneback 
            adr <= to_adr[1:0];
4794 
end
4795 
endgenerate
4796 
 
4797 
generate
4798 
if (max_burst_width==3) begin : inst_3
4799 
    always @ (posedge clk or posedge rst)
4800 
    if (rst)
4801 
        adr <= 3'h0;
4802 
    else
4803 
        if (cyc_i & stb_i)
4804 
            case (bte_i)
4805 
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
4806 
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
4807 75 unneback 
            endcase
4808 83 unneback 
        else
4809 
            adr <= to_adr[2:0];
4810 
end
4811 
endgenerate
4812 
 
4813 
generate
4814 
if (max_burst_width==4) begin : inst_4
4815 
    always @ (posedge clk or posedge rst)
4816 
    if (rst)
4817 
        adr <= 4'h0;
4818 
    else
4819 91 unneback 
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
4820 83 unneback 
            case (bte_i)
4821 
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
4822 
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
4823 
            default: adr[3:0] <= to_adr + 4'd1;
4824 
            endcase
4825 
        else
4826 
            adr <= to_adr[3:0];
4827 
end
4828 
endgenerate
4829 
 
4830 
generate
4831 
if (adr_width > max_burst_width) begin : pass_through
4832 
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
4833 
end
4834 
endgenerate
4835 
 
4836 
endmodule
4837 75 unneback 
`endif
4838 
 
4839 40 unneback 
`ifdef WB3WB3_BRIDGE
4840 12 unneback 
// async wb3 - wb3 bridge
4841 
`timescale 1ns/1ns
4842 40 unneback 
`define MODULE wb3wb3_bridge
4843 
module `BASE`MODULE (
4844 
`undef MODULE
4845 12 unneback 
        // wishbone slave side
4846 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4847 
        // wishbone master side
4848 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4849 
 
4850 95 unneback 
parameter style = "FIFO"; // valid: simple, FIFO
4851 
parameter addr_width = 4;
4852 
 
4853 12 unneback 
input [31:0] wbs_dat_i;
4854 
input [31:2] wbs_adr_i;
4855 
input [3:0]  wbs_sel_i;
4856 
input [1:0]  wbs_bte_i;
4857 
input [2:0]  wbs_cti_i;
4858 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4859 
output [31:0] wbs_dat_o;
4860 14 unneback 
output wbs_ack_o;
4861 12 unneback 
input wbs_clk, wbs_rst;
4862 
 
4863 
output [31:0] wbm_dat_o;
4864 
output reg [31:2] wbm_adr_o;
4865 
output [3:0]  wbm_sel_o;
4866 
output reg [1:0]  wbm_bte_o;
4867 
output reg [2:0]  wbm_cti_o;
4868 14 unneback 
output reg wbm_we_o;
4869 
output wbm_cyc_o;
4870 12 unneback 
output wbm_stb_o;
4871 
input [31:0]  wbm_dat_i;
4872 
input wbm_ack_i;
4873 
input wbm_clk, wbm_rst;
4874 
 
4875 
// bte
4876 
parameter linear       = 2'b00;
4877 
parameter wrap4        = 2'b01;
4878 
parameter wrap8        = 2'b10;
4879 
parameter wrap16       = 2'b11;
4880 
// cti
4881 
parameter classic      = 3'b000;
4882 
parameter incburst     = 3'b010;
4883 
parameter endofburst   = 3'b111;
4884 
 
4885 95 unneback 
localparam wbs_adr  = 1'b0;
4886 
localparam wbs_data = 1'b1;
4887 12 unneback 
 
4888 95 unneback 
localparam wbm_adr0      = 2'b00;
4889 
localparam wbm_adr1      = 2'b01;
4890 
localparam wbm_data      = 2'b10;
4891 
localparam wbm_data_wait = 2'b11;
4892 12 unneback 
 
4893 
reg [1:0] wbs_bte_reg;
4894 
reg wbs;
4895 
wire wbs_eoc_alert, wbm_eoc_alert;
4896 
reg wbs_eoc, wbm_eoc;
4897 
reg [1:0] wbm;
4898 
 
4899 14 unneback 
wire [1:16] wbs_count, wbm_count;
4900 12 unneback 
 
4901 
wire [35:0] a_d, a_q, b_d, b_q;
4902 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4903 
reg a_rd_reg;
4904 
wire b_rd_adr, b_rd_data;
4905 14 unneback 
wire b_rd_data_reg;
4906 
wire [35:0] temp;
4907 12 unneback 
 
4908 
`define WE 5
4909 
`define BTE 4:3
4910 
`define CTI 2:0
4911 
 
4912 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4913 
always @ (posedge wbs_clk or posedge wbs_rst)
4914 
if (wbs_rst)
4915 
        wbs_eoc <= 1'b0;
4916 
else
4917 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4918 78 unneback 
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
4919 12 unneback 
        else if (wbs_eoc_alert & (a_rd | a_wr))
4920 
                wbs_eoc <= 1'b1;
4921 
 
4922 40 unneback 
`define MODULE cnt_shreg_ce_clear
4923 
`BASE`MODULE # ( .length(16))
4924 
`undef MODULE
4925 12 unneback 
    cnt0 (
4926 
        .cke(wbs_ack_o),
4927 
        .clear(wbs_eoc),
4928 
        .q(wbs_count),
4929 
        .rst(wbs_rst),
4930 
        .clk(wbs_clk));
4931 
 
4932 
always @ (posedge wbs_clk or posedge wbs_rst)
4933 
if (wbs_rst)
4934 
        wbs <= wbs_adr;
4935 
else
4936 75 unneback 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
4937 12 unneback 
                wbs <= wbs_data;
4938 
        else if (wbs_eoc & wbs_ack_o)
4939 
                wbs <= wbs_adr;
4940 
 
4941 
// wbs FIFO
4942 75 unneback 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
4943 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
4944 12 unneback 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4945 
              1'b0;
4946 
assign a_rd = !a_fifo_empty;
4947 
always @ (posedge wbs_clk or posedge wbs_rst)
4948 
if (wbs_rst)
4949 
        a_rd_reg <= 1'b0;
4950 
else
4951 
        a_rd_reg <= a_rd;
4952 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4953 
 
4954 
assign wbs_dat_o = a_q[35:4];
4955 
 
4956 
always @ (posedge wbs_clk or posedge wbs_rst)
4957 
if (wbs_rst)
4958 13 unneback 
        wbs_bte_reg <= 2'b00;
4959 12 unneback 
else
4960 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
4961 12 unneback 
 
4962 
// wbm FIFO
4963 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4964 
always @ (posedge wbm_clk or posedge wbm_rst)
4965 
if (wbm_rst)
4966 
        wbm_eoc <= 1'b0;
4967 
else
4968 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4969 
                wbm_eoc <= b_q[`BTE] == linear;
4970 
        else if (wbm_eoc_alert & wbm_ack_i)
4971 
                wbm_eoc <= 1'b1;
4972 
 
4973 
always @ (posedge wbm_clk or posedge wbm_rst)
4974 
if (wbm_rst)
4975 
        wbm <= wbm_adr0;
4976 
else
4977 33 unneback 
/*
4978 12 unneback 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
4979 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
4980 
        (wbm==wbm_adr1 & !wbm_we_o) |
4981 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
4982 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
4983 33 unneback 
*/
4984 
    case (wbm)
4985 
    wbm_adr0:
4986 
        if (!b_fifo_empty)
4987 
            wbm <= wbm_adr1;
4988 
    wbm_adr1:
4989 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
4990 
            wbm <= wbm_data;
4991 
    wbm_data:
4992 
        if (wbm_ack_i & wbm_eoc)
4993 
            wbm <= wbm_adr0;
4994 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
4995 
            wbm <= wbm_data_wait;
4996 
    wbm_data_wait:
4997 
        if (!b_fifo_empty)
4998 
            wbm <= wbm_data;
4999 
    endcase
5000 12 unneback 
 
5001 
assign b_d = {wbm_dat_i,4'b1111};
5002 
assign b_wr = !wbm_we_o & wbm_ack_i;
5003 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
5004 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
5005 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
5006 33 unneback 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
5007 12 unneback 
                   1'b0;
5008 
assign b_rd = b_rd_adr | b_rd_data;
5009 
 
5010 40 unneback 
`define MODULE dff
5011 
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
5012 
`undef MODULE
5013 
`define MODULE dff_ce
5014 
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
5015 
`undef MODULE
5016 12 unneback 
 
5017 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
5018 
 
5019 40 unneback 
`define MODULE cnt_shreg_ce_clear
5020 42 unneback 
`BASE`MODULE # ( .length(16))
5021 40 unneback 
`undef MODULE
5022 12 unneback 
    cnt1 (
5023 
        .cke(wbm_ack_i),
5024 
        .clear(wbm_eoc),
5025 
        .q(wbm_count),
5026 
        .rst(wbm_rst),
5027 
        .clk(wbm_clk));
5028 
 
5029 33 unneback 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
5030 
assign wbm_stb_o = (wbm==wbm_data);
5031 12 unneback 
 
5032 
always @ (posedge wbm_clk or posedge wbm_rst)
5033 
if (wbm_rst)
5034 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
5035 
else begin
5036 
        if (wbm==wbm_adr0 & !b_fifo_empty)
5037 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
5038 
        else if (wbm_eoc_alert & wbm_ack_i)
5039 
                wbm_cti_o <= endofburst;
5040 
end
5041 
 
5042 
//async_fifo_dw_simplex_top
5043 40 unneback 
`define MODULE fifo_2r2w_async_simplex
5044 
`BASE`MODULE
5045 
`undef MODULE
5046 12 unneback 
# ( .data_width(36), .addr_width(addr_width))
5047 
fifo (
5048 
    // a side
5049 
    .a_d(a_d),
5050 
    .a_wr(a_wr),
5051 
    .a_fifo_full(a_fifo_full),
5052 
    .a_q(a_q),
5053 
    .a_rd(a_rd),
5054 
    .a_fifo_empty(a_fifo_empty),
5055 
    .a_clk(wbs_clk),
5056 
    .a_rst(wbs_rst),
5057 
    // b side
5058 
    .b_d(b_d),
5059 
    .b_wr(b_wr),
5060 
    .b_fifo_full(b_fifo_full),
5061 
    .b_q(b_q),
5062 
    .b_rd(b_rd),
5063 
    .b_fifo_empty(b_fifo_empty),
5064 
    .b_clk(wbm_clk),
5065 
    .b_rst(wbm_rst)
5066 
    );
5067 
 
5068 
endmodule
5069 40 unneback 
`undef WE
5070 
`undef BTE
5071 
`undef CTI
5072 
`endif
5073 17 unneback 
 
5074 75 unneback 
`ifdef WB3AVALON_BRIDGE
5075 
`define MODULE wb3avalon_bridge
5076 
module `BASE`MODULE (
5077 
`undef MODULE
5078 
        // wishbone slave side
5079 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5080 77 unneback 
        // avalon master side
5081 75 unneback 
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
5082 
 
5083 85 unneback 
parameter linewrapburst = 1'b0;
5084 
 
5085 75 unneback 
input [31:0] wbs_dat_i;
5086 
input [31:2] wbs_adr_i;
5087 
input [3:0]  wbs_sel_i;
5088 
input [1:0]  wbs_bte_i;
5089 
input [2:0]  wbs_cti_i;
5090 83 unneback 
input wbs_we_i;
5091 
input wbs_cyc_i;
5092 
input wbs_stb_i;
5093 75 unneback 
output [31:0] wbs_dat_o;
5094 
output wbs_ack_o;
5095 
input wbs_clk, wbs_rst;
5096 
 
5097 
input [31:0] readdata;
5098 
output [31:0] writedata;
5099 
output [31:2] address;
5100 
output [3:0]  be;
5101 
output write;
5102 81 unneback 
output read;
5103 75 unneback 
output beginbursttransfer;
5104 
output [3:0] burstcount;
5105 
input readdatavalid;
5106 
input waitrequest;
5107 
input clk;
5108 
input rst;
5109 
 
5110 
wire [1:0] wbm_bte_o;
5111 
wire [2:0] wbm_cti_o;
5112 
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
5113 
reg last_cyc;
5114 79 unneback 
reg [3:0] counter;
5115 82 unneback 
reg read_busy;
5116 75 unneback 
 
5117 
always @ (posedge clk or posedge rst)
5118 
if (rst)
5119 
    last_cyc <= 1'b0;
5120 
else
5121 
    last_cyc <= wbm_cyc_o;
5122 
 
5123 79 unneback 
always @ (posedge clk or posedge rst)
5124 
if (rst)
5125 82 unneback 
    read_busy <= 1'b0;
5126 79 unneback 
else
5127 82 unneback 
    if (read & !waitrequest)
5128 
        read_busy <= 1'b1;
5129 
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
5130 
        read_busy <= 1'b0;
5131 
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
5132 81 unneback 
 
5133 75 unneback 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
5134 
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
5135 
                    (wbm_bte_o==2'b10) ? 4'd8 :
5136 78 unneback 
                    (wbm_bte_o==2'b11) ? 4'd16:
5137 
                    4'd1;
5138 82 unneback 
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
5139 75 unneback 
 
5140 79 unneback 
always @ (posedge clk or posedge rst)
5141 
if (rst) begin
5142 
    counter <= 4'd0;
5143 
end else
5144 80 unneback 
    if (wbm_we_o) begin
5145 
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
5146 85 unneback 
            counter <= burstcount -4'd1;
5147 80 unneback 
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
5148 
            counter <= burstcount;
5149 
        end else if (!waitrequest & wbm_stb_o) begin
5150 
            counter <= counter - 4'd1;
5151 
        end
5152 82 unneback 
    end
5153 81 unneback 
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
5154 79 unneback 
 
5155 75 unneback 
`define MODULE wb3wb3_bridge
5156 77 unneback 
`BASE`MODULE wbwb3inst (
5157 75 unneback 
`undef MODULE
5158 
    // wishbone slave side
5159 
    .wbs_dat_i(wbs_dat_i),
5160 
    .wbs_adr_i(wbs_adr_i),
5161 
    .wbs_sel_i(wbs_sel_i),
5162 
    .wbs_bte_i(wbs_bte_i),
5163 
    .wbs_cti_i(wbs_cti_i),
5164 
    .wbs_we_i(wbs_we_i),
5165 
    .wbs_cyc_i(wbs_cyc_i),
5166 
    .wbs_stb_i(wbs_stb_i),
5167 
    .wbs_dat_o(wbs_dat_o),
5168 
    .wbs_ack_o(wbs_ack_o),
5169 
    .wbs_clk(wbs_clk),
5170 
    .wbs_rst(wbs_rst),
5171 
    // wishbone master side
5172 
    .wbm_dat_o(writedata),
5173 78 unneback 
    .wbm_adr_o(address),
5174 75 unneback 
    .wbm_sel_o(be),
5175 
    .wbm_bte_o(wbm_bte_o),
5176 
    .wbm_cti_o(wbm_cti_o),
5177 
    .wbm_we_o(wbm_we_o),
5178 
    .wbm_cyc_o(wbm_cyc_o),
5179 
    .wbm_stb_o(wbm_stb_o),
5180 
    .wbm_dat_i(readdata),
5181 
    .wbm_ack_i(wbm_ack_i),
5182 
    .wbm_clk(clk),
5183 
    .wbm_rst(rst));
5184 
 
5185 
 
5186 
endmodule
5187 
`endif
5188 
 
5189 40 unneback 
`ifdef WB3_ARBITER_TYPE1
5190 
`define MODULE wb3_arbiter_type1
5191 42 unneback 
module `BASE`MODULE (
5192 40 unneback 
`undef MODULE
5193 39 unneback 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5194 
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
5195 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5196 
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
5197 
    wb_clk, wb_rst
5198 
);
5199 
 
5200 
parameter nr_of_ports = 3;
5201 
parameter adr_size = 26;
5202 
parameter adr_lo   = 2;
5203 
parameter dat_size = 32;
5204 
parameter sel_size = dat_size/8;
5205 
 
5206 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
5207 
localparam dw = dat_size * nr_of_ports;
5208 
localparam sw = sel_size * nr_of_ports;
5209 
localparam cw = 3 * nr_of_ports;
5210 
localparam bw = 2 * nr_of_ports;
5211 
 
5212 
input  [dw-1:0] wbm_dat_o;
5213 
input  [aw-1:0] wbm_adr_o;
5214 
input  [sw-1:0] wbm_sel_o;
5215 
input  [cw-1:0] wbm_cti_o;
5216 
input  [bw-1:0] wbm_bte_o;
5217 
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
5218 
output [dw-1:0] wbm_dat_i;
5219 
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
5220 
 
5221 
output [dat_size-1:0] wbs_dat_i;
5222 
output [adr_size-1:adr_lo] wbs_adr_i;
5223 
output [sel_size-1:0] wbs_sel_i;
5224 
output [2:0] wbs_cti_i;
5225 
output [1:0] wbs_bte_i;
5226 
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
5227 
input  [dat_size-1:0] wbs_dat_o;
5228 
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
5229 
 
5230 
input wb_clk, wb_rst;
5231 
 
5232 44 unneback 
reg  [nr_of_ports-1:0] select;
5233 39 unneback 
wire [nr_of_ports-1:0] state;
5234 
wire [nr_of_ports-1:0] eoc; // end-of-cycle
5235 
wire [nr_of_ports-1:0] sel;
5236 
wire idle;
5237 
 
5238 
genvar i;
5239 
 
5240 
assign idle = !(|state);
5241 
 
5242 
generate
5243 
if (nr_of_ports == 2) begin
5244 
 
5245 
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
5246 
 
5247 
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5248 
 
5249 44 unneback 
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5250 
 
5251 
    always @ (idle or wbm_cyc_o)
5252 
    if (idle)
5253 
        casex (wbm_cyc_o)
5254 
        2'b1x : select = 2'b10;
5255 
        2'b01 : select = 2'b01;
5256 
        default : select = {nr_of_ports{1'b0}};
5257 
        endcase
5258 
    else
5259 
        select = {nr_of_ports{1'b0}};
5260 
 
5261 39 unneback 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5262 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5263 
 
5264 
end
5265 
endgenerate
5266 
 
5267 
generate
5268 
if (nr_of_ports == 3) begin
5269 
 
5270 
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5271 
 
5272 
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5273 
 
5274 44 unneback 
    always @ (idle or wbm_cyc_o)
5275 
    if (idle)
5276 
        casex (wbm_cyc_o)
5277 
        3'b1xx : select = 3'b100;
5278 
        3'b01x : select = 3'b010;
5279 
        3'b001 : select = 3'b001;
5280 
        default : select = {nr_of_ports{1'b0}};
5281 
        endcase
5282 
    else
5283 
        select = {nr_of_ports{1'b0}};
5284 
 
5285 
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5286 39 unneback 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5287 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5288 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5289 
 
5290 
end
5291 
endgenerate
5292 
 
5293 
generate
5294 44 unneback 
if (nr_of_ports == 4) begin
5295 
 
5296 
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5297 
 
5298 
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5299 
 
5300 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5301 
 
5302 
    always @ (idle or wbm_cyc_o)
5303 
    if (idle)
5304 
        casex (wbm_cyc_o)
5305 
        4'b1xxx : select = 4'b1000;
5306 
        4'b01xx : select = 4'b0100;
5307 
        4'b001x : select = 4'b0010;
5308 
        4'b0001 : select = 4'b0001;
5309 
        default : select = {nr_of_ports{1'b0}};
5310 
        endcase
5311 
    else
5312 
        select = {nr_of_ports{1'b0}};
5313 
 
5314 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5315 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5316 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5317 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5318 
 
5319 
end
5320 
endgenerate
5321 
 
5322 
generate
5323 
if (nr_of_ports == 5) begin
5324 
 
5325 
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5326 
 
5327 
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5328 
 
5329 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5330 
 
5331 
    always @ (idle or wbm_cyc_o)
5332 
    if (idle)
5333 
        casex (wbm_cyc_o)
5334 
        5'b1xxxx : select = 5'b10000;
5335 
        5'b01xxx : select = 5'b01000;
5336 
        5'b001xx : select = 5'b00100;
5337 
        5'b0001x : select = 5'b00010;
5338 
        5'b00001 : select = 5'b00001;
5339 
        default : select = {nr_of_ports{1'b0}};
5340 
        endcase
5341 
    else
5342 
        select = {nr_of_ports{1'b0}};
5343 
 
5344 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5345 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5346 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5347 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5348 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5349 
 
5350 
end
5351 
endgenerate
5352 
 
5353 
generate
5354 67 unneback 
if (nr_of_ports == 6) begin
5355 
 
5356 
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5357 
 
5358 
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5359 
 
5360 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5361 
 
5362 
    always @ (idle or wbm_cyc_o)
5363 
    if (idle)
5364 
        casex (wbm_cyc_o)
5365 
        6'b1xxxxx : select = 6'b100000;
5366 
        6'b01xxxx : select = 6'b010000;
5367 
        6'b001xxx : select = 6'b001000;
5368 
        6'b0001xx : select = 6'b000100;
5369 
        6'b00001x : select = 6'b000010;
5370 
        6'b000001 : select = 6'b000001;
5371 
        default : select = {nr_of_ports{1'b0}};
5372 
        endcase
5373 
    else
5374 
        select = {nr_of_ports{1'b0}};
5375 
 
5376 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5377 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5378 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5379 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5380 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5381 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5382 
 
5383 
end
5384 
endgenerate
5385 
 
5386 
generate
5387 
if (nr_of_ports == 7) begin
5388 
 
5389 
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5390 
 
5391 
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5392 
 
5393 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5394 
 
5395 
    always @ (idle or wbm_cyc_o)
5396 
    if (idle)
5397 
        casex (wbm_cyc_o)
5398 
        7'b1xxxxxx : select = 7'b1000000;
5399 
        7'b01xxxxx : select = 7'b0100000;
5400 
        7'b001xxxx : select = 7'b0010000;
5401 
        7'b0001xxx : select = 7'b0001000;
5402 
        7'b00001xx : select = 7'b0000100;
5403 
        7'b000001x : select = 7'b0000010;
5404 
        7'b0000001 : select = 7'b0000001;
5405 
        default : select = {nr_of_ports{1'b0}};
5406 
        endcase
5407 
    else
5408 
        select = {nr_of_ports{1'b0}};
5409 
 
5410 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5411 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5412 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5413 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5414 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5415 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5416 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5417 
 
5418 
end
5419 
endgenerate
5420 
 
5421 
generate
5422 
if (nr_of_ports == 8) begin
5423 
 
5424 
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5425 
 
5426 
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5427 
 
5428 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5429 
 
5430 
    always @ (idle or wbm_cyc_o)
5431 
    if (idle)
5432 
        casex (wbm_cyc_o)
5433 
        8'b1xxxxxxx : select = 8'b10000000;
5434 
        8'b01xxxxxx : select = 8'b01000000;
5435 
        8'b001xxxxx : select = 8'b00100000;
5436 
        8'b0001xxxx : select = 8'b00010000;
5437 
        8'b00001xxx : select = 8'b00001000;
5438 
        8'b000001xx : select = 8'b00000100;
5439 
        8'b0000001x : select = 8'b00000010;
5440 
        8'b00000001 : select = 8'b00000001;
5441 
        default : select = {nr_of_ports{1'b0}};
5442 
        endcase
5443 
    else
5444 
        select = {nr_of_ports{1'b0}};
5445 
 
5446 
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
5447 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5448 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5449 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5450 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5451 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5452 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5453 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5454 
 
5455 
end
5456 
endgenerate
5457 
 
5458 
generate
5459 63 unneback 
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
5460 42 unneback 
`define MODULE spr
5461 
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
5462 
`undef MODULE
5463 39 unneback 
end
5464 
endgenerate
5465 
 
5466 
    assign sel = select | state;
5467 
 
5468 40 unneback 
`define MODULE mux_andor
5469 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
5470 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
5471 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
5472 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
5473 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
5474 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
5475 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
5476 
`undef MODULE
5477 39 unneback 
    assign wbs_cyc_i = |sel;
5478 
 
5479 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
5480 
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
5481 
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
5482 
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
5483 
 
5484 
endmodule
5485 40 unneback 
`endif
5486 39 unneback 
 
5487 60 unneback 
`ifdef WB_B3_RAM_BE
5488 49 unneback 
// WB RAM with byte enable
5489 59 unneback 
`define MODULE wb_b3_ram_be
5490 
module `BASE`MODULE (
5491 
`undef MODULE
5492 69 unneback 
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5493 
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
5494 59 unneback 
 
5495 68 unneback 
parameter adr_size = 16;
5496 85 unneback 
parameter mem_size = 1<<adr_size;
5497 60 unneback 
parameter dat_size = 32;
5498 83 unneback 
parameter max_burst_width = 4;
5499 60 unneback 
parameter memory_init = 1;
5500 
parameter memory_file = "vl_ram.vmem";
5501 59 unneback 
 
5502 85 unneback 
localparam aw = (adr_size);
5503 69 unneback 
localparam dw = dat_size;
5504 
localparam sw = dat_size/8;
5505 
localparam cw = 3;
5506 
localparam bw = 2;
5507 60 unneback 
 
5508 70 unneback 
input [dw-1:0] wbs_dat_i;
5509 
input [aw-1:0] wbs_adr_i;
5510 
input [cw-1:0] wbs_cti_i;
5511 
input [bw-1:0] wbs_bte_i;
5512 
input [sw-1:0] wbs_sel_i;
5513 
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5514 
output [dw-1:0] wbs_dat_o;
5515 
output wbs_ack_o;
5516 71 unneback 
input wb_clk, wb_rst;
5517 59 unneback 
 
5518 83 unneback 
wire [aw-1:0] adr;
5519 59 unneback 
 
5520 60 unneback 
`define MODULE ram_be
5521 
`BASE`MODULE # (
5522 
    .data_width(dat_size),
5523 83 unneback 
    .addr_width(aw),
5524 69 unneback 
    .mem_size(mem_size),
5525 68 unneback 
    .memory_init(memory_init),
5526 
    .memory_file(memory_file))
5527 60 unneback 
ram0(
5528 
`undef MODULE
5529 
    .d(wbs_dat_i),
5530 83 unneback 
    .adr(adr),
5531 60 unneback 
    .be(wbs_sel_i),
5532 86 unneback 
    .we(wbs_we_i & wbs_ack_o),
5533 60 unneback 
    .q(wbs_dat_o),
5534 
    .clk(wb_clk)
5535 
);
5536 
 
5537 83 unneback 
`define MODULE wb_adr_inc
5538 
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
5539 
    .cyc_i(wbs_cyc_i),
5540 
    .stb_i(wbs_stb_i),
5541 
    .cti_i(wbs_cti_i),
5542 
    .bte_i(wbs_bte_i),
5543 
    .adr_i(wbs_adr_i),
5544 85 unneback 
    .we_i(wbs_we_i),
5545 83 unneback 
    .ack_o(wbs_ack_o),
5546 
    .adr_o(adr),
5547 
    .clk(wb_clk),
5548 
    .rst(wb_rst));
5549 
`undef MODULE
5550 60 unneback 
 
5551 59 unneback 
endmodule
5552 
`endif
5553 
 
5554 
`ifdef WB_B4_RAM_BE
5555 
// WB RAM with byte enable
5556 49 unneback 
`define MODULE wb_b4_ram_be
5557 
module `BASE`MODULE (
5558 
`undef MODULE
5559 
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
5560 52 unneback 
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
5561 49 unneback 
 
5562 
    parameter dat_width = 32;
5563 
    parameter adr_width = 8;
5564 
 
5565 
input [dat_width-1:0] wb_dat_i;
5566 
input [adr_width-1:0] wb_adr_i;
5567 
input [dat_width/8-1:0] wb_sel_i;
5568 
input wb_we_i, wb_stb_i, wb_cyc_i;
5569 
output [dat_width-1:0] wb_dat_o;
5570 51 unneback 
reg [dat_width-1:0] wb_dat_o;
5571 52 unneback 
output wb_stall_o;
5572 49 unneback 
output wb_ack_o;
5573 
reg wb_ack_o;
5574 
input wb_clk, wb_rst;
5575 
 
5576 56 unneback 
wire [dat_width/8-1:0] cke;
5577 
 
5578 49 unneback 
generate
5579 
if (dat_width==32) begin
5580 51 unneback 
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
5581 
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
5582 
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
5583 
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
5584 56 unneback 
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
5585 49 unneback 
    always @ (posedge wb_clk)
5586 
    begin
5587 56 unneback 
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
5588 
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
5589 
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
5590 
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
5591 49 unneback 
    end
5592 59 unneback 
    always @ (posedge wb_clk or posedge wb_rst)
5593 
    begin
5594 
        if (wb_rst)
5595 
            wb_dat_o <= 32'h0;
5596 
        else
5597 
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
5598 
    end
5599 49 unneback 
end
5600 
endgenerate
5601 
 
5602 52 unneback 
always @ (posedge wb_clk or posedge wb_rst)
5603 55 unneback 
if (wb_rst)
5604 52 unneback 
    wb_ack_o <= 1'b0;
5605 
else
5606 54 unneback 
    wb_ack_o <= wb_stb_i & wb_cyc_i;
5607 52 unneback 
 
5608 
assign wb_stall_o = 1'b0;
5609 
 
5610 49 unneback 
endmodule
5611 
`endif
5612 
 
5613 48 unneback 
`ifdef WB_B4_ROM
5614 
// WB ROM
5615 
`define MODULE wb_b4_rom
5616 
module `BASE`MODULE (
5617 
`undef MODULE
5618 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5619 
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
5620 
 
5621 
    parameter dat_width = 32;
5622 
    parameter dat_default = 32'h15000000;
5623 
    parameter adr_width = 32;
5624 
 
5625 
/*
5626 
`ifndef ROM
5627 
`define ROM "rom.v"
5628 
`endif
5629 
*/
5630 
    input [adr_width-1:2]   wb_adr_i;
5631 
    input                   wb_stb_i;
5632 
    input                   wb_cyc_i;
5633 
    output [dat_width-1:0]  wb_dat_o;
5634 
    reg [dat_width-1:0]     wb_dat_o;
5635 
    output                  wb_ack_o;
5636 
    reg                     wb_ack_o;
5637 
    output                  stall_o;
5638 
    input                   wb_clk;
5639 
    input                   wb_rst;
5640 
 
5641 
always @ (posedge wb_clk or posedge wb_rst)
5642 
    if (wb_rst)
5643 
        wb_dat_o <= {dat_width{1'b0}};
5644 
    else
5645 
         case (wb_adr_i[adr_width-1:2])
5646 
`ifdef ROM
5647 
`include `ROM
5648 
`endif
5649 
           default:
5650 
             wb_dat_o <= dat_default;
5651 
 
5652 
         endcase // case (wb_adr_i)
5653 
 
5654 
 
5655 
always @ (posedge wb_clk or posedge wb_rst)
5656 
    if (wb_rst)
5657 
        wb_ack_o <= 1'b0;
5658 
    else
5659 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
5660 
 
5661 
assign stall_o = 1'b0;
5662 
 
5663 
endmodule
5664 
`endif
5665 
 
5666 
 
5667 40 unneback 
`ifdef WB_BOOT_ROM
5668 17 unneback 
// WB ROM
5669 40 unneback 
`define MODULE wb_boot_rom
5670 
module `BASE`MODULE (
5671 
`undef MODULE
5672 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5673 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
5674 17 unneback 
 
5675 18 unneback 
    parameter adr_hi = 31;
5676 
    parameter adr_lo = 28;
5677 
    parameter adr_sel = 4'hf;
5678 
    parameter addr_width = 5;
5679 33 unneback 
/*
5680 17 unneback 
`ifndef BOOT_ROM
5681 
`define BOOT_ROM "boot_rom.v"
5682 
`endif
5683 33 unneback 
*/
5684 18 unneback 
    input [adr_hi:2]    wb_adr_i;
5685 
    input               wb_stb_i;
5686 
    input               wb_cyc_i;
5687 
    output [31:0]        wb_dat_o;
5688 
    output              wb_ack_o;
5689 
    output              hit_o;
5690 
    input               wb_clk;
5691 
    input               wb_rst;
5692 
 
5693 
    wire hit;
5694 
    reg [31:0] wb_dat;
5695 
    reg wb_ack;
5696 
 
5697 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
5698 17 unneback 
 
5699 
always @ (posedge wb_clk or posedge wb_rst)
5700 
    if (wb_rst)
5701 18 unneback 
        wb_dat <= 32'h15000000;
5702 17 unneback 
    else
5703 18 unneback 
         case (wb_adr_i[addr_width-1:2])
5704 33 unneback 
`ifdef BOOT_ROM
5705 17 unneback 
`include `BOOT_ROM
5706 33 unneback 
`endif
5707 17 unneback 
           /*
5708 
            // Zero r0 and jump to 0x00000100
5709 18 unneback 
 
5710 
            1 : wb_dat <= 32'hA8200000;
5711 
            2 : wb_dat <= 32'hA8C00100;
5712 
            3 : wb_dat <= 32'h44003000;
5713 
            4 : wb_dat <= 32'h15000000;
5714 17 unneback 
            */
5715 
           default:
5716 18 unneback 
             wb_dat <= 32'h00000000;
5717 17 unneback 
 
5718 
         endcase // case (wb_adr_i)
5719 
 
5720 
 
5721 
always @ (posedge wb_clk or posedge wb_rst)
5722 
    if (wb_rst)
5723 18 unneback 
        wb_ack <= 1'b0;
5724 17 unneback 
    else
5725 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
5726 17 unneback 
 
5727 18 unneback 
assign hit_o = hit;
5728 
assign wb_dat_o = wb_dat & {32{wb_ack}};
5729 
assign wb_ack_o = wb_ack;
5730 
 
5731 17 unneback 
endmodule
5732 40 unneback 
`endif
5733 32 unneback 
 
5734 92 unneback 
`ifdef WB_B3_DPRAM
5735 
`define MODULE wb_b3_dpram
5736 40 unneback 
module `BASE`MODULE (
5737 
`undef MODULE
5738 32 unneback 
        // wishbone slave side a
5739 92 unneback 
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
5740 32 unneback 
        wbsa_clk, wbsa_rst,
5741 92 unneback 
        // wishbone slave side b
5742 
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
5743 32 unneback 
        wbsb_clk, wbsb_rst);
5744 
 
5745 92 unneback 
parameter data_width_a = 32;
5746 
parameter data_width_b = data_width_a;
5747 
parameter addr_width_a = 8;
5748 
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
5749 
   parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
5750 
parameter max_burst_width_a = 4;
5751 
parameter max_burst_width_b = max_burst_width_a;
5752 32 unneback 
 
5753 92 unneback 
input [data_width_a-1:0] wbsa_dat_i;
5754 
input [addr_width_a-1:0] wbsa_adr_i;
5755 
input [data_width_a/8-1:0] wbsa_sel_i;
5756 
input [2:0] wbsa_cti_i;
5757 
input [1:0] wbsa_bte_i;
5758 32 unneback 
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
5759 92 unneback 
output [data_width_a-1:0] wbsa_dat_o;
5760 32 unneback 
output wbsa_ack_o;
5761 
input wbsa_clk, wbsa_rst;
5762 
 
5763 92 unneback 
input [data_width_b-1:0] wbsb_dat_i;
5764 
input [addr_width_b-1:0] wbsb_adr_i;
5765 
input [data_width_b/8-1:0] wbsb_sel_i;
5766 
input [2:0] wbsb_cti_i;
5767 
input [1:0] wbsb_bte_i;
5768 32 unneback 
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
5769 92 unneback 
output [data_width_b-1:0] wbsb_dat_o;
5770 32 unneback 
output wbsb_ack_o;
5771 
input wbsb_clk, wbsb_rst;
5772 
 
5773 92 unneback 
wire [addr_width_a-1:0] adr_a;
5774 
wire [addr_width_b-1:0] adr_b;
5775 32 unneback 
 
5776 92 unneback 
`define MODULE wb_adr_inc
5777 
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
5778 
    .cyc_i(wbsa_cyc_i),
5779 
    .stb_i(wbsa_stb_i),
5780 
    .cti_i(wbsa_cti_i),
5781 
    .bte_i(wbsa_bte_i),
5782 
    .adr_i(wbsa_adr_i),
5783 
    .we_i(wbsa_we_i),
5784 
    .ack_o(wbsa_ack_o),
5785 
    .adr_o(adr_a),
5786 
    .clk(wbsa_clk),
5787 
    .rst(wbsa_rst));
5788 
 
5789 
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
5790 
    .cyc_i(wbsb_cyc_i),
5791 
    .stb_i(wbsb_stb_i),
5792 
    .cti_i(wbsb_cti_i),
5793 
    .bte_i(wbsb_bte_i),
5794 
    .adr_i(wbsb_adr_i),
5795 
    .we_i(wbsb_we_i),
5796 
    .ack_o(wbsb_ack_o),
5797 
    .adr_o(adr_b),
5798 
    .clk(wbsb_clk),
5799 
    .rst(wbsb_rst));
5800 40 unneback 
`undef MODULE
5801 92 unneback 
 
5802 
`define MODULE dpram_be_2r2w
5803 
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
5804 
`undef MODULE
5805 
ram_i (
5806 32 unneback 
    .d_a(wbsa_dat_i),
5807 92 unneback 
    .q_a(wbsa_dat_o),
5808 
    .adr_a(adr_a),
5809 
    .be_a(wbsa_sel_i),
5810 
    .we_a(wbsa_we_i & wbsa_ack_o),
5811 32 unneback 
    .clk_a(wbsa_clk),
5812 
    .d_b(wbsb_dat_i),
5813 92 unneback 
    .q_b(wbsb_dat_o),
5814 
    .adr_b(adr_b),
5815 
    .be_b(wbsb_sel_i),
5816 
    .we_b(wbsb_we_i & wbsb_ack_o),
5817 32 unneback 
    .clk_b(wbsb_clk) );
5818 
 
5819 
endmodule
5820 40 unneback 
`endif
5821 94 unneback 
 
5822 18 unneback 
//////////////////////////////////////////////////////////////////////
5823 
////                                                              ////
5824 
////  Arithmetic functions                                        ////
5825 
////                                                              ////
5826 
////  Description                                                 ////
5827 
////  Arithmetic functions for ALU and DSP                        ////
5828 
////                                                              ////
5829 
////                                                              ////
5830 
////  To Do:                                                      ////
5831 
////   -                                                          ////
5832 
////                                                              ////
5833 
////  Author(s):                                                  ////
5834 
////      - Michael Unneback, unneback@opencores.org              ////
5835 
////        ORSoC AB                                              ////
5836 
////                                                              ////
5837 
//////////////////////////////////////////////////////////////////////
5838 
////                                                              ////
5839 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
5840 
////                                                              ////
5841 
//// This source file may be used and distributed without         ////
5842 
//// restriction provided that this copyright statement is not    ////
5843 
//// removed from the file and that any derivative work contains  ////
5844 
//// the original copyright notice and the associated disclaimer. ////
5845 
////                                                              ////
5846 
//// This source file is free software; you can redistribute it   ////
5847 
//// and/or modify it under the terms of the GNU Lesser General   ////
5848 
//// Public License as published by the Free Software Foundation; ////
5849 
//// either version 2.1 of the License, or (at your option) any   ////
5850 
//// later version.                                               ////
5851 
////                                                              ////
5852 
//// This source is distributed in the hope that it will be       ////
5853 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
5854 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
5855 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
5856 
//// details.                                                     ////
5857 
////                                                              ////
5858 
//// You should have received a copy of the GNU Lesser General    ////
5859 
//// Public License along with this source; if not, download it   ////
5860 
//// from http://www.opencores.org/lgpl.shtml                     ////
5861 
////                                                              ////
5862 
//////////////////////////////////////////////////////////////////////
5863 
 
5864 40 unneback 
`ifdef MULTS
5865 18 unneback 
// signed multiplication
5866 40 unneback 
`define MODULE mults
5867 
module `BASE`MODULE (a,b,p);
5868 
`undef MODULE
5869 18 unneback 
parameter operand_a_width = 18;
5870 
parameter operand_b_width = 18;
5871 
parameter result_hi = 35;
5872 
parameter result_lo = 0;
5873 
input [operand_a_width-1:0] a;
5874 
input [operand_b_width-1:0] b;
5875 
output [result_hi:result_lo] p;
5876 
wire signed [operand_a_width-1:0] ai;
5877 
wire signed [operand_b_width-1:0] bi;
5878 
wire signed [operand_a_width+operand_b_width-1:0] result;
5879 
 
5880 
    assign ai = a;
5881 
    assign bi = b;
5882 
    assign result = ai * bi;
5883 
    assign p = result[result_hi:result_lo];
5884 
 
5885 
endmodule
5886 40 unneback 
`endif
5887 
`ifdef MULTS18X18
5888 
`define MODULE mults18x18
5889 
module `BASE`MODULE (a,b,p);
5890 
`undef MODULE
5891 18 unneback 
input [17:0] a,b;
5892 
output [35:0] p;
5893 
vl_mult
5894 
    # (.operand_a_width(18), .operand_b_width(18))
5895 
    mult0 (.a(a), .b(b), .p(p));
5896 
endmodule
5897 40 unneback 
`endif
5898 18 unneback 
 
5899 40 unneback 
`ifdef MULT
5900 
`define MODULE mult
5901 18 unneback 
// unsigned multiplication
5902 40 unneback 
module `BASE`MODULE (a,b,p);
5903 
`undef MODULE
5904 18 unneback 
parameter operand_a_width = 18;
5905 
parameter operand_b_width = 18;
5906 
parameter result_hi = 35;
5907 
parameter result_lo = 0;
5908 
input [operand_a_width-1:0] a;
5909 
input [operand_b_width-1:0] b;
5910 
output [result_hi:result_hi] p;
5911 
 
5912 
wire [operand_a_width+operand_b_width-1:0] result;
5913 
 
5914 
    assign result = a * b;
5915 
    assign p = result[result_hi:result_lo];
5916 
 
5917 
endmodule
5918 40 unneback 
`endif
5919 18 unneback 
 
5920 40 unneback 
`ifdef SHIFT_UNIT_32
5921 
`define MODULE shift_unit_32
5922 18 unneback 
// shift unit
5923 
// supporting the following shift functions
5924 
//   SLL
5925 
//   SRL
5926 
//   SRA
5927 
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
5928 40 unneback 
module `BASE`MODULE( din, s, dout, opcode);
5929 
`undef MODULE
5930 18 unneback 
input [31:0] din; // data in operand
5931 
input [4:0] s; // shift operand
5932 
input [1:0] opcode;
5933 
output [31:0] dout;
5934 
 
5935 
parameter opcode_sll = 2'b00;
5936 
//parameter opcode_srl = 2'b01;
5937 
parameter opcode_sra = 2'b10;
5938 
//parameter opcode_ror = 2'b11;
5939 
 
5940 
wire sll, sra;
5941 
assign sll = opcode == opcode_sll;
5942 
assign sra = opcode == opcode_sra;
5943 
 
5944 
wire [15:1] s1;
5945 
wire [3:0] sign;
5946 
wire [7:0] tmp [0:3];
5947 
 
5948 
// first stage is multiplier based
5949 
// shift operand as fractional 8.7
5950 
assign s1[15] = sll & s[2:0]==3'd7;
5951 
assign s1[14] = sll & s[2:0]==3'd6;
5952 
assign s1[13] = sll & s[2:0]==3'd5;
5953 
assign s1[12] = sll & s[2:0]==3'd4;
5954 
assign s1[11] = sll & s[2:0]==3'd3;
5955 
assign s1[10] = sll & s[2:0]==3'd2;
5956 
assign s1[ 9] = sll & s[2:0]==3'd1;
5957 
assign s1[ 8] = s[2:0]==3'd0;
5958 
assign s1[ 7] = !sll & s[2:0]==3'd1;
5959 
assign s1[ 6] = !sll & s[2:0]==3'd2;
5960 
assign s1[ 5] = !sll & s[2:0]==3'd3;
5961 
assign s1[ 4] = !sll & s[2:0]==3'd4;
5962 
assign s1[ 3] = !sll & s[2:0]==3'd5;
5963 
assign s1[ 2] = !sll & s[2:0]==3'd6;
5964 
assign s1[ 1] = !sll & s[2:0]==3'd7;
5965 
 
5966 
assign sign[3] = din[31] & sra;
5967 
assign sign[2] = sign[3] & (&din[31:24]);
5968 
assign sign[1] = sign[2] & (&din[23:16]);
5969 
assign sign[0] = sign[1] & (&din[15:8]);
5970 40 unneback 
`define MODULE mults
5971 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
5972 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
5973 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
5974 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
5975 
`undef MODULE
5976 18 unneback 
// second stage is multiplexer based
5977 
// shift on byte level
5978 
 
5979 
// mux byte 3
5980 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
5981 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
5982 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
5983 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
5984 
                     {8{sign[3]}};
5985 
 
5986 
// mux byte 2
5987 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
5988 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
5989 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
5990 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5991 
                     (s[4:3]==2'b01) ? tmp[3] :
5992 
                     {8{sign[3]}};
5993 
 
5994 
// mux byte 1
5995 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
5996 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
5997 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
5998 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5999 
                     (s[4:3]==2'b01) ? tmp[2] :
6000 
                     (s[4:3]==2'b10) ? tmp[3] :
6001 
                     {8{sign[3]}};
6002 
 
6003 
// mux byte 0
6004 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
6005 
                     (sll) ?  {8{1'b0}}:
6006 
                     (s[4:3]==2'b01) ? tmp[1] :
6007 
                     (s[4:3]==2'b10) ? tmp[2] :
6008 
                     tmp[3];
6009 
 
6010 
endmodule
6011 40 unneback 
`endif
6012 18 unneback 
 
6013 40 unneback 
`ifdef LOGIC_UNIT
6014 18 unneback 
// logic unit
6015 
// supporting the following logic functions
6016 
//    a and b
6017 
//    a or  b
6018 
//    a xor b
6019 
//    not b
6020 40 unneback 
`define MODULE logic_unit
6021 
module `BASE`MODULE( a, b, result, opcode);
6022 
`undef MODULE
6023 18 unneback 
parameter width = 32;
6024 
parameter opcode_and = 2'b00;
6025 
parameter opcode_or  = 2'b01;
6026 
parameter opcode_xor = 2'b10;
6027 
input [width-1:0] a,b;
6028 
output [width-1:0] result;
6029 
input [1:0] opcode;
6030 
 
6031 
assign result = (opcode==opcode_and) ? a & b :
6032 
                (opcode==opcode_or)  ? a | b :
6033 
                (opcode==opcode_xor) ? a ^ b :
6034 
                b;
6035 
 
6036 
endmodule
6037 48 unneback 
`endif
6038 18 unneback 
 
6039 48 unneback 
`ifdef ARITH_UNIT
6040 
`define MODULE arith_unit
6041 
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
6042 
`undef MODULE
6043 18 unneback 
parameter width = 32;
6044 
parameter opcode_add = 1'b0;
6045 
parameter opcode_sub = 1'b1;
6046 
input [width-1:0] a,b;
6047 
input c_in, add_sub, sign;
6048 
output [width-1:0] result;
6049 
output c_out, z, ovfl;
6050 
 
6051 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
6052 
assign z = (result=={width{1'b0}});
6053 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
6054 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
6055 
endmodule
6056 40 unneback 
`endif
6057 48 unneback 
 
6058 
`ifdef COUNT_UNIT
6059 
`define MODULE count_unit
6060 
module `BASE`MODULE (din, dout, opcode);
6061 
`undef MODULE
6062 
parameter width = 32;
6063 
input [width-1:0] din;
6064 
output [width-1:0] dout;
6065 
input opcode;
6066 
 
6067 
integer i;
6068 58 unneback 
wire [width/32+4:0] ff1, fl1;
6069 48 unneback 
 
6070 57 unneback 
/*
6071 48 unneback 
always @(din) begin
6072 
    ff1 = 0; i = 0;
6073 
    while (din[i] == 0 && i < width) begin // complex condition
6074 
        ff1 = ff1 + 1;
6075 
        i = i + 1;
6076 
    end
6077 
end
6078 
 
6079 
always @(din) begin
6080 
    fl1 = width; i = width-1;
6081 
    while (din[i] == 0 && i >= width) begin // complex condition
6082 
        fl1 = fl1 - 1;
6083 
        i = i - 1;
6084 
    end
6085 
end
6086 57 unneback 
*/
6087 48 unneback 
 
6088 
generate
6089 
if (width==32) begin
6090 57 unneback 
 
6091 
    assign ff1 = din[0] ? 6'd1 :
6092 
                 din[1] ? 6'd2 :
6093 
                 din[2] ? 6'd3 :
6094 
                 din[3] ? 6'd4 :
6095 
                 din[4] ? 6'd5 :
6096 
                 din[5] ? 6'd6 :
6097 
                 din[6] ? 6'd7 :
6098 
                 din[7] ? 6'd8 :
6099 
                 din[8] ? 6'd9 :
6100 
                 din[9] ? 6'd10 :
6101 
                 din[10] ? 6'd11 :
6102 
                 din[11] ? 6'd12 :
6103 
                 din[12] ? 6'd13 :
6104 
                 din[13] ? 6'd14 :
6105 
                 din[14] ? 6'd15 :
6106 
                 din[15] ? 6'd16 :
6107 
                 din[16] ? 6'd17 :
6108 
                 din[17] ? 6'd18 :
6109 
                 din[18] ? 6'd19 :
6110 
                 din[19] ? 6'd20 :
6111 
                 din[20] ? 6'd21 :
6112 
                 din[21] ? 6'd22 :
6113 
                 din[22] ? 6'd23 :
6114 
                 din[23] ? 6'd24 :
6115 
                 din[24] ? 6'd25 :
6116 
                 din[25] ? 6'd26 :
6117 
                 din[26] ? 6'd27 :
6118 
                 din[27] ? 6'd28 :
6119 
                 din[28] ? 6'd29 :
6120 
                 din[29] ? 6'd30 :
6121 
                 din[30] ? 6'd31 :
6122 
                 din[31] ? 6'd32 :
6123 
                 6'd0;
6124 
 
6125 
    assign fl1 = din[31] ? 6'd32 :
6126 
                 din[30] ? 6'd31 :
6127 
                 din[29] ? 6'd30 :
6128 
                 din[28] ? 6'd29 :
6129 
                 din[27] ? 6'd28 :
6130 
                 din[26] ? 6'd27 :
6131 
                 din[25] ? 6'd26 :
6132 
                 din[24] ? 6'd25 :
6133 
                 din[23] ? 6'd24 :
6134 
                 din[22] ? 6'd23 :
6135 
                 din[21] ? 6'd22 :
6136 
                 din[20] ? 6'd21 :
6137 
                 din[19] ? 6'd20 :
6138 
                 din[18] ? 6'd19 :
6139 
                 din[17] ? 6'd18 :
6140 
                 din[16] ? 6'd17 :
6141 
                 din[15] ? 6'd16 :
6142 
                 din[14] ? 6'd15 :
6143 
                 din[13] ? 6'd14 :
6144 
                 din[12] ? 6'd13 :
6145 
                 din[11] ? 6'd12 :
6146 
                 din[10] ? 6'd11 :
6147 
                 din[9] ? 6'd10 :
6148 
                 din[8] ? 6'd9 :
6149 
                 din[7] ? 6'd8 :
6150 
                 din[6] ? 6'd7 :
6151 
                 din[5] ? 6'd6 :
6152 
                 din[4] ? 6'd5 :
6153 
                 din[3] ? 6'd4 :
6154 
                 din[2] ? 6'd3 :
6155 
                 din[1] ? 6'd2 :
6156 
                 din[0] ? 6'd1 :
6157 
                 6'd0;
6158 
 
6159 
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
6160 48 unneback 
end
6161 
endgenerate
6162 57 unneback 
 
6163 48 unneback 
generate
6164 
if (width==64) begin
6165 57 unneback 
    assign ff1 = 7'd0;
6166 
    assign fl1 = 7'd0;
6167 
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
6168 48 unneback 
end
6169 
endgenerate
6170 
 
6171 
endmodule
6172 
`endif
6173 
 
6174 
`ifdef EXT_UNIT
6175 
`define MODULE ext_unit
6176 
module `BASE`MODULE ( a, b, F, result, opcode);
6177 
`undef MODULE
6178 
parameter width = 32;
6179 
input [width-1:0] a, b;
6180 
input F;
6181 
output reg [width-1:0] result;
6182 
input [2:0] opcode;
6183 
 
6184 
generate
6185 
if (width==32) begin
6186 
always @ (a or b or F or opcode)
6187 
begin
6188 
    case (opcode)
6189 
    3'b000: result = {{24{1'b0}},a[7:0]};
6190 
    3'b001: result = {{24{a[7]}},a[7:0]};
6191 
    3'b010: result = {{16{1'b0}},a[7:0]};
6192 
    3'b011: result = {{16{a[15]}},a[15:0]};
6193 
    3'b110: result = (F) ? a : b;
6194 
    default: result = {b[15:0],16'h0000};
6195 
    endcase
6196 
end
6197 
end
6198 
endgenerate
6199 
 
6200 
generate
6201 
if (width==64) begin
6202 
always @ (a or b or F or opcode)
6203 
begin
6204 
    case (opcode)
6205 
    3'b000: result = {{56{1'b0}},a[7:0]};
6206 
    3'b001: result = {{56{a[7]}},a[7:0]};
6207 
    3'b010: result = {{48{1'b0}},a[7:0]};
6208 
    3'b011: result = {{48{a[15]}},a[15:0]};
6209 57 unneback 
    3'b110: result = (F) ? a : b;
6210 48 unneback 
    default: result = {32'h00000000,b[15:0],16'h0000};
6211 
    endcase
6212 
end
6213 
end
6214 
endgenerate
6215 
endmodule
6216 
`endif

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