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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 97

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 40 unneback
`ifdef ALL
14
 
15
`define GBUF
16
`define SYNC_RST
17
`define PLL
18
 
19
`define MULTS
20
`define MULTS18X18
21
`define MULT
22
`define SHIFT_UNIT_32
23
`define LOGIC_UNIT
24
 
25
`define CNT_SHREG_WRAP
26
`define CNT_SHREG_CE_WRAP
27
`define CNT_SHREG_CE_CLEAR
28
`define CNT_SHREG_CE_CLEAR_WRAP
29
 
30
`define MUX_ANDOR
31
`define MUX2_ANDOR
32
`define MUX3_ANDOR
33
`define MUX4_ANDOR
34
`define MUX5_ANDOR
35
`define MUX6_ANDOR
36 43 unneback
`define PARITY
37 40 unneback
 
38
`define ROM_INIT
39
`define RAM
40
`define RAM_BE
41
`define DPRAM_1R1W
42
`define DPRAM_2R1W
43
`define DPRAM_2R2W
44 75 unneback
`define DPRAM_BE_2R2W
45 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
46
`define FIFO_2R2W_SYNC_SIMPLEX
47
`define FIFO_CMP_ASYNC
48
`define FIFO_1R1W_ASYNC
49
`define FIFO_2R2W_ASYNC
50
`define FIFO_2R2W_ASYNC_SIMPLEX
51 48 unneback
`define REG_FILE
52 40 unneback
 
53
`define DFF
54
`define DFF_ARRAY
55
`define DFF_CE
56
`define DFF_CE_CLEAR
57
`define DF_CE_SET
58
`define SPR
59
`define SRP
60
`define DFF_SR
61
`define LATCH
62
`define SHREG
63
`define SHREG_CE
64
`define DELAY
65
`define DELAY_EMPTYFLAG
66 94 unneback
`define PULSE2TOGGLE
67
`define TOGGLE2PULSE
68
`define SYNCHRONIZER
69
`define CDC
70 40 unneback
 
71 75 unneback
`define WB3AVALON_BRIDGE
72 40 unneback
`define WB3WB3_BRIDGE
73
`define WB3_ARBITER_TYPE1
74 83 unneback
`define WB_ADR_INC
75 59 unneback
`define WB_B3_RAM_BE
76 49 unneback
`define WB_B4_RAM_BE
77 48 unneback
`define WB_B4_ROM
78 40 unneback
`define WB_BOOT_ROM
79
`define WB_DPRAM
80 97 unneback
`define WBB3_WBB4_CACHE
81 40 unneback
 
82 44 unneback
`define IO_DFF_OE
83
`define O_DFF
84
 
85 40 unneback
`endif
86
 
87
`ifdef PLL
88
`ifndef SYNC_RST
89
`define SYNC_RST
90
`endif
91
`endif
92
 
93
`ifdef SYNC_RST
94
`ifndef GBUF
95
`define GBUF
96
`endif
97
`endif
98
 
99 94 unneback
`ifdef CDC
100
`ifndef PULSE2TOGGLE
101
`define PULSE2TOGGLE
102
`endif
103
`ifndef TOGGLE2PULSE
104
`define TOGGLE2PULSE
105
`endif
106
`ifndef SYNCHRONIZER
107
`define SYNCHRONIZER
108
`endif
109
`endif
110
 
111 92 unneback
`ifdef WB_B3_DPRAM
112
`ifndef WB_ADR_INC
113
`define WB_ADR_INC
114 40 unneback
`endif
115 92 unneback
`ifndef DPRAM_BE_2R2W
116
`define DPRAM_BE_2R2W
117 40 unneback
`endif
118
`endif
119
 
120 62 unneback
`ifdef WB_B3_RAM_BE
121 83 unneback
`ifndef WB_ADR_INC
122
`define WB_ADR_INC
123 62 unneback
`endif
124
`ifndef RAM_BE
125
`define RAM_BE
126
`endif
127
`endif
128
 
129 40 unneback
`ifdef WB3_ARBITER_TYPE1
130 42 unneback
`ifndef SPR
131
`define SPR
132
`endif
133 40 unneback
`ifndef MUX_ANDOR
134
`define MUX_ANDOR
135
`endif
136
`endif
137
 
138 76 unneback
`ifdef WB3AVALON_BRIDGE
139
`ifndef WB3WB3_BRIDGE
140
`define WB3WB3_BRIDGE
141
`endif
142
`endif
143
 
144 40 unneback
`ifdef WB3WB3_BRIDGE
145
`ifndef CNT_SHREG_CE_CLEAR
146
`define CNT_SHREG_CE_CLEAR
147
`endif
148
`ifndef DFF
149
`define DFF
150
`endif
151
`ifndef DFF_CE
152
`define DFF_CE
153
`endif
154
`ifndef CNT_SHREG_CE_CLEAR
155
`define CNT_SHREG_CE_CLEAR
156
`endif
157
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
158
`define FIFO_2R2W_ASYNC_SIMPLEX
159
`endif
160
`endif
161
 
162 97 unneback
 `ifdef WBB3_WBB4_CACHE
163
 `ifndef RAM
164
 `define RAM
165
 `endif
166
 `ifndef WB_ADR_INC
167
 `define WB_ADR_INC
168
 `endif
169
 `ifndef dpram_be_2r2w
170
 `define DPRAM_BE_2R2W
171
 `endif
172
 `endif
173
 
174 40 unneback
`ifdef MULTS18X18
175
`ifndef MULTS
176
`define MULTS
177
`endif
178
`endif
179
 
180
`ifdef SHIFT_UNIT_32
181
`ifndef MULTS
182
`define MULTS
183
`endif
184
`endif
185
 
186
`ifdef MUX2_ANDOR
187
`ifndef MUX_ANDOR
188
`define MUX_ANDOR
189
`endif
190
`endif
191
 
192
`ifdef MUX3_ANDOR
193
`ifndef MUX_ANDOR
194
`define MUX_ANDOR
195
`endif
196
`endif
197
 
198
`ifdef MUX4_ANDOR
199
`ifndef MUX_ANDOR
200
`define MUX_ANDOR
201
`endif
202
`endif
203
 
204
`ifdef MUX5_ANDOR
205
`ifndef MUX_ANDOR
206
`define MUX_ANDOR
207
`endif
208
`endif
209
 
210
`ifdef MUX6_ANDOR
211
`ifndef MUX_ANDOR
212
`define MUX_ANDOR
213
`endif
214
`endif
215
 
216
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
217
`ifndef CNT_BIN_CE
218
`define CNT_BIN_CE
219
`endif
220
`ifndef DPRAM_1R1W
221
`define DPRAM_1R1W
222
`endif
223
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
224
`define CNT_BIN_CE_REW_Q_ZQ_L1
225
`endif
226
`endif
227
 
228
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
229
`ifndef CNT_LFSR_CE
230
`define CNT_LFSR_CE
231
`endif
232
`ifndef DPRAM_2R2W
233
`define DPRAM_2R2W
234
`endif
235
`ifndef CNT_BIN_CE_REW_ZQ_L1
236
`define CNT_BIN_CE_REW_ZQ_L1
237
`endif
238
`endif
239
 
240
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
241
`ifndef CNT_GRAY_CE_BIN
242
`define CNT_GRAY_CE_BIN
243
`endif
244
`ifndef DPRAM_2R2W
245
`define DPRAM_2R2W
246
`endif
247
`ifndef FIFO_CMP_ASYNC
248
`define FIFO_CMP_ASYNC
249
`endif
250
`endif
251
 
252
`ifdef FIFO_2R2W_ASYNC
253
`ifndef FIFO_1R1W_ASYNC
254
`define FIFO_1R1W_ASYNC
255
`endif
256
`endif
257
 
258
`ifdef FIFO_1R1W_ASYNC
259
`ifndef CNT_GRAY_CE_BIN
260
`define CNT_GRAY_CE_BIN
261
`endif
262
`ifndef DPRAM_1R1W
263
`define DPRAM_1R1W
264
`endif
265
`ifndef FIFO_CMP_ASYNC
266
`define FIFO_CMP_ASYNC
267
`endif
268
`endif
269
 
270
`ifdef FIFO_CMP_ASYNC
271
`ifndef DFF_SR
272
`define DFF_SR
273
`endif
274
`ifndef DFF
275
`define DFF
276
`endif
277
`endif
278 48 unneback
 
279
`ifdef REG_FILE
280
`ifndef DPRAM_1R1W
281
`define DPRAM_1R1W
282
`endif
283
`endif
284 97 unneback
 
285
// size to width
286
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
287 62 unneback
//////////////////////////////////////////////////////////////////////
288 6 unneback
////                                                              ////
289
////  Versatile library, clock and reset                          ////
290
////                                                              ////
291
////  Description                                                 ////
292
////  Logic related to clock and reset                            ////
293
////                                                              ////
294
////                                                              ////
295
////  To Do:                                                      ////
296
////   - add more different registers                             ////
297
////                                                              ////
298
////  Author(s):                                                  ////
299
////      - Michael Unneback, unneback@opencores.org              ////
300
////        ORSoC AB                                              ////
301
////                                                              ////
302
//////////////////////////////////////////////////////////////////////
303
////                                                              ////
304
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
305
////                                                              ////
306
//// This source file may be used and distributed without         ////
307
//// restriction provided that this copyright statement is not    ////
308
//// removed from the file and that any derivative work contains  ////
309
//// the original copyright notice and the associated disclaimer. ////
310
////                                                              ////
311
//// This source file is free software; you can redistribute it   ////
312
//// and/or modify it under the terms of the GNU Lesser General   ////
313
//// Public License as published by the Free Software Foundation; ////
314
//// either version 2.1 of the License, or (at your option) any   ////
315
//// later version.                                               ////
316
////                                                              ////
317
//// This source is distributed in the hope that it will be       ////
318
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
319
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
320
//// PURPOSE.  See the GNU Lesser General Public License for more ////
321
//// details.                                                     ////
322
////                                                              ////
323
//// You should have received a copy of the GNU Lesser General    ////
324
//// Public License along with this source; if not, download it   ////
325
//// from http://www.opencores.org/lgpl.shtml                     ////
326
////                                                              ////
327
//////////////////////////////////////////////////////////////////////
328
 
329 48 unneback
`ifdef ACTEL
330
`ifdef GBUF
331
`timescale 1 ns/100 ps
332 6 unneback
// Global buffer
333
// usage:
334
// use to enable global buffers for high fan out signals such as clock and reset
335
// Version: 8.4 8.4.0.33
336
module gbuf(GL,CLK);
337
output GL;
338
input  CLK;
339
 
340
    wire GND;
341
 
342
    GND GND_1_net(.Y(GND));
343
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
344
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
345
 
346
endmodule
347
`timescale 1 ns/1 ns
348 40 unneback
`define MODULE gbuf
349
module `BASE`MODULE ( i, o);
350
`undef MODULE
351 6 unneback
input i;
352
output o;
353
`ifdef SIM_GBUF
354
assign o=i;
355
`else
356
gbuf gbuf_i0 ( .CLK(i), .GL(o));
357
`endif
358
endmodule
359 40 unneback
`endif
360 33 unneback
 
361 6 unneback
`else
362 33 unneback
 
363 40 unneback
`ifdef ALTERA
364
`ifdef GBUF
365 21 unneback
//altera
366 40 unneback
`define MODULE gbuf
367
module `BASE`MODULE ( i, o);
368
`undef MODULE
369 33 unneback
input i;
370
output o;
371
assign o = i;
372
endmodule
373 40 unneback
`endif
374 33 unneback
 
375 6 unneback
`else
376
 
377 40 unneback
`ifdef GBUF
378 6 unneback
`timescale 1 ns/100 ps
379 40 unneback
`define MODULE
380
module `BASE`MODULE ( i, o);
381
`undef MODULE
382 6 unneback
input i;
383
output o;
384
assign o = i;
385
endmodule
386 40 unneback
`endif
387 6 unneback
`endif // ALTERA
388
`endif //ACTEL
389
 
390 40 unneback
`ifdef SYNC_RST
391 6 unneback
// sync reset
392 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
393 6 unneback
// output active high global reset sync with two DFFs 
394
`timescale 1 ns/100 ps
395 40 unneback
`define MODULE sync_rst
396
module `BASE`MODULE ( rst_n_i, rst_o, clk);
397
`undef MODULE
398 6 unneback
input rst_n_i, clk;
399
output rst_o;
400 18 unneback
reg [1:0] tmp;
401 6 unneback
always @ (posedge clk or negedge rst_n_i)
402
if (!rst_n_i)
403 17 unneback
        tmp <= 2'b11;
404 6 unneback
else
405 33 unneback
        tmp <= {1'b0,tmp[1]};
406 40 unneback
`define MODULE gbuf
407
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
408
`undef MODULE
409 6 unneback
endmodule
410 40 unneback
`endif
411 6 unneback
 
412 40 unneback
`ifdef PLL
413 6 unneback
// vl_pll
414
`ifdef ACTEL
415 32 unneback
///////////////////////////////////////////////////////////////////////////////
416 17 unneback
`timescale 1 ps/1 ps
417 40 unneback
`define MODULE pll
418
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
419
`undef MODULE
420 6 unneback
parameter index = 0;
421
parameter number_of_clk = 1;
422 17 unneback
parameter period_time_0 = 20000;
423
parameter period_time_1 = 20000;
424
parameter period_time_2 = 20000;
425
parameter lock_delay = 2000000;
426 6 unneback
input clk_i, rst_n_i;
427
output lock;
428
output reg [0:number_of_clk-1] clk_o;
429
output [0:number_of_clk-1] rst_o;
430
 
431
`ifdef SIM_PLL
432
 
433
always
434
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
435
 
436
generate if (number_of_clk > 1)
437
always
438
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
439
endgenerate
440
 
441
generate if (number_of_clk > 2)
442
always
443
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
444
endgenerate
445
 
446
genvar i;
447
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
448
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
449
end
450
endgenerate
451
 
452
assign #lock_delay lock = rst_n_i;
453
 
454
endmodule
455
`else
456
generate if (number_of_clk==1 & index==0) begin
457
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
458
end
459
endgenerate // index==0
460
generate if (number_of_clk==1 & index==1) begin
461
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
462
end
463
endgenerate // index==1
464
generate if (number_of_clk==1 & index==2) begin
465
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
466
end
467
endgenerate // index==2
468
generate if (number_of_clk==1 & index==3) begin
469
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
470
end
471
endgenerate // index==0
472
 
473
generate if (number_of_clk==2 & index==0) begin
474
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
475
end
476
endgenerate // index==0
477
generate if (number_of_clk==2 & index==1) begin
478
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
479
end
480
endgenerate // index==1
481
generate if (number_of_clk==2 & index==2) begin
482
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
483
end
484
endgenerate // index==2
485
generate if (number_of_clk==2 & index==3) begin
486
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
487
end
488
endgenerate // index==0
489
 
490
generate if (number_of_clk==3 & index==0) begin
491
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
492
end
493
endgenerate // index==0
494
generate if (number_of_clk==3 & index==1) begin
495
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
496
end
497
endgenerate // index==1
498
generate if (number_of_clk==3 & index==2) begin
499
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
500
end
501
endgenerate // index==2
502
generate if (number_of_clk==3 & index==3) begin
503
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
504
end
505
endgenerate // index==0
506
 
507
genvar i;
508
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
509 40 unneback
`define MODULE sync_rst
510
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
511
`undef MODULE
512 6 unneback
end
513
endgenerate
514
endmodule
515
`endif
516 32 unneback
///////////////////////////////////////////////////////////////////////////////
517 6 unneback
 
518
`else
519
 
520 32 unneback
///////////////////////////////////////////////////////////////////////////////
521 6 unneback
`ifdef ALTERA
522
 
523 32 unneback
`timescale 1 ps/1 ps
524 40 unneback
`define MODULE pll
525
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
526
`undef MODULE
527 32 unneback
parameter index = 0;
528
parameter number_of_clk = 1;
529
parameter period_time_0 = 20000;
530
parameter period_time_1 = 20000;
531
parameter period_time_2 = 20000;
532
parameter period_time_3 = 20000;
533
parameter period_time_4 = 20000;
534
parameter lock_delay = 2000000;
535
input clk_i, rst_n_i;
536
output lock;
537
output reg [0:number_of_clk-1] clk_o;
538
output [0:number_of_clk-1] rst_o;
539
 
540
`ifdef SIM_PLL
541
 
542
always
543
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
544
 
545
generate if (number_of_clk > 1)
546
always
547
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
548
endgenerate
549
 
550
generate if (number_of_clk > 2)
551
always
552
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
553
endgenerate
554
 
555 33 unneback
generate if (number_of_clk > 3)
556 32 unneback
always
557
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
558
endgenerate
559
 
560 33 unneback
generate if (number_of_clk > 4)
561 32 unneback
always
562
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
563
endgenerate
564
 
565
genvar i;
566
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
567
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
568
end
569
endgenerate
570
 
571 33 unneback
//assign #lock_delay lock = rst_n_i;
572
assign lock = rst_n_i;
573 32 unneback
 
574
endmodule
575 6 unneback
`else
576
 
577 33 unneback
`ifdef VL_PLL0
578
`ifdef VL_PLL0_CLK1
579
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
580
`endif
581
`ifdef VL_PLL0_CLK2
582
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
583
`endif
584
`ifdef VL_PLL0_CLK3
585
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
586
`endif
587
`ifdef VL_PLL0_CLK4
588
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
589
`endif
590
`ifdef VL_PLL0_CLK5
591
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
592
`endif
593
`endif
594 32 unneback
 
595 33 unneback
`ifdef VL_PLL1
596
`ifdef VL_PLL1_CLK1
597
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
598
`endif
599
`ifdef VL_PLL1_CLK2
600
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
601
`endif
602
`ifdef VL_PLL1_CLK3
603
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
604
`endif
605
`ifdef VL_PLL1_CLK4
606
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
607
`endif
608
`ifdef VL_PLL1_CLK5
609
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
610
`endif
611
`endif
612 32 unneback
 
613 33 unneback
`ifdef VL_PLL2
614
`ifdef VL_PLL2_CLK1
615
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
616
`endif
617
`ifdef VL_PLL2_CLK2
618
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
619
`endif
620
`ifdef VL_PLL2_CLK3
621
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
622
`endif
623
`ifdef VL_PLL2_CLK4
624
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
625
`endif
626
`ifdef VL_PLL2_CLK5
627
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
628
`endif
629
`endif
630 32 unneback
 
631 33 unneback
`ifdef VL_PLL3
632
`ifdef VL_PLL3_CLK1
633
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
634
`endif
635
`ifdef VL_PLL3_CLK2
636
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
637
`endif
638
`ifdef VL_PLL3_CLK3
639
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
640
`endif
641
`ifdef VL_PLL3_CLK4
642
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
643
`endif
644
`ifdef VL_PLL3_CLK5
645
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
646
`endif
647
`endif
648 32 unneback
 
649
genvar i;
650
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
651 40 unneback
`define MODULE sync_rst
652
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
653
`undef MODULE
654 32 unneback
end
655
endgenerate
656
endmodule
657
`endif
658
///////////////////////////////////////////////////////////////////////////////
659
 
660
`else
661
 
662 6 unneback
// generic PLL
663 17 unneback
`timescale 1 ps/1 ps
664 40 unneback
`define MODULE pll
665
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
666
`undef MODULE
667 6 unneback
parameter index = 0;
668
parameter number_of_clk = 1;
669 17 unneback
parameter period_time_0 = 20000;
670
parameter period_time_1 = 20000;
671
parameter period_time_2 = 20000;
672 6 unneback
parameter lock_delay = 2000;
673
input clk_i, rst_n_i;
674
output lock;
675
output reg [0:number_of_clk-1] clk_o;
676
output [0:number_of_clk-1] rst_o;
677
 
678
always
679
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
680
 
681
generate if (number_of_clk > 1)
682
always
683
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
684
endgenerate
685
 
686
generate if (number_of_clk > 2)
687
always
688
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
689
endgenerate
690
 
691
genvar i;
692
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
693 40 unneback
`define MODULE sync_rst
694
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
695
`undef MODULE
696 6 unneback
end
697
endgenerate
698
 
699
assign #lock_delay lock = rst_n_i;
700
 
701
endmodule
702
 
703
`endif //altera
704 17 unneback
`endif //actel
705 40 unneback
`undef MODULE
706
`endif//////////////////////////////////////////////////////////////////////
707 6 unneback
////                                                              ////
708
////  Versatile library, registers                                ////
709
////                                                              ////
710
////  Description                                                 ////
711
////  Different type of registers                                 ////
712
////                                                              ////
713
////                                                              ////
714
////  To Do:                                                      ////
715
////   - add more different registers                             ////
716
////                                                              ////
717
////  Author(s):                                                  ////
718
////      - Michael Unneback, unneback@opencores.org              ////
719
////        ORSoC AB                                              ////
720
////                                                              ////
721
//////////////////////////////////////////////////////////////////////
722
////                                                              ////
723
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
724
////                                                              ////
725
//// This source file may be used and distributed without         ////
726
//// restriction provided that this copyright statement is not    ////
727
//// removed from the file and that any derivative work contains  ////
728
//// the original copyright notice and the associated disclaimer. ////
729
////                                                              ////
730
//// This source file is free software; you can redistribute it   ////
731
//// and/or modify it under the terms of the GNU Lesser General   ////
732
//// Public License as published by the Free Software Foundation; ////
733
//// either version 2.1 of the License, or (at your option) any   ////
734
//// later version.                                               ////
735
////                                                              ////
736
//// This source is distributed in the hope that it will be       ////
737
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
738
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
739
//// PURPOSE.  See the GNU Lesser General Public License for more ////
740
//// details.                                                     ////
741
////                                                              ////
742
//// You should have received a copy of the GNU Lesser General    ////
743
//// Public License along with this source; if not, download it   ////
744
//// from http://www.opencores.org/lgpl.shtml                     ////
745
////                                                              ////
746
//////////////////////////////////////////////////////////////////////
747
 
748 40 unneback
`ifdef DFF
749
`define MODULE dff
750
module `BASE`MODULE ( d, q, clk, rst);
751
`undef MODULE
752 6 unneback
        parameter width = 1;
753
        parameter reset_value = 0;
754
 
755
        input [width-1:0] d;
756
        input clk, rst;
757
        output reg [width-1:0] q;
758
 
759
        always @ (posedge clk or posedge rst)
760
        if (rst)
761
                q <= reset_value;
762
        else
763
                q <= d;
764
 
765
endmodule
766 40 unneback
`endif
767 6 unneback
 
768 40 unneback
`ifdef DFF_ARRAY
769
`define MODULE dff_array
770
module `BASE`MODULE ( d, q, clk, rst);
771
`undef MODULE
772 6 unneback
 
773
        parameter width = 1;
774
        parameter depth = 2;
775
        parameter reset_value = 1'b0;
776
 
777
        input [width-1:0] d;
778
        input clk, rst;
779
        output [width-1:0] q;
780
        reg  [0:depth-1] q_tmp [width-1:0];
781
        integer i;
782
        always @ (posedge clk or posedge rst)
783
        if (rst) begin
784
            for (i=0;i<depth;i=i+1)
785
                q_tmp[i] <= {width{reset_value}};
786
        end else begin
787
            q_tmp[0] <= d;
788
            for (i=1;i<depth;i=i+1)
789
                q_tmp[i] <= q_tmp[i-1];
790
        end
791
 
792
    assign q = q_tmp[depth-1];
793
 
794
endmodule
795 40 unneback
`endif
796 6 unneback
 
797 40 unneback
`ifdef DFF_CE
798
`define MODULE dff_ce
799
module `BASE`MODULE ( d, ce, q, clk, rst);
800
`undef MODULE
801 6 unneback
 
802
        parameter width = 1;
803
        parameter reset_value = 0;
804
 
805
        input [width-1:0] d;
806
        input ce, clk, rst;
807
        output reg [width-1:0] q;
808
 
809
        always @ (posedge clk or posedge rst)
810
        if (rst)
811
                q <= reset_value;
812
        else
813
                if (ce)
814
                        q <= d;
815
 
816
endmodule
817 40 unneback
`endif
818 6 unneback
 
819 40 unneback
`ifdef DFF_CE_CLEAR
820
`define MODULE dff_ce_clear
821
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
822
`undef MODULE
823 8 unneback
 
824
        parameter width = 1;
825
        parameter reset_value = 0;
826
 
827
        input [width-1:0] d;
828 10 unneback
        input ce, clear, clk, rst;
829 8 unneback
        output reg [width-1:0] q;
830
 
831
        always @ (posedge clk or posedge rst)
832
        if (rst)
833
            q <= reset_value;
834
        else
835
            if (ce)
836
                if (clear)
837
                    q <= {width{1'b0}};
838
                else
839
                    q <= d;
840
 
841
endmodule
842 40 unneback
`endif
843 8 unneback
 
844 40 unneback
`ifdef DF_CE_SET
845
`define MODULE dff_ce_set
846
module `BASE`MODULE ( d, ce, set, q, clk, rst);
847
`undef MODULE
848 24 unneback
 
849
        parameter width = 1;
850
        parameter reset_value = 0;
851
 
852
        input [width-1:0] d;
853
        input ce, set, clk, rst;
854
        output reg [width-1:0] q;
855
 
856
        always @ (posedge clk or posedge rst)
857
        if (rst)
858
            q <= reset_value;
859
        else
860
            if (ce)
861
                if (set)
862
                    q <= {width{1'b1}};
863
                else
864
                    q <= d;
865
 
866
endmodule
867 40 unneback
`endif
868 24 unneback
 
869 40 unneback
`ifdef SPR
870
`define MODULE spr
871
module `BASE`MODULE ( sp, r, q, clk, rst);
872
`undef MODULE
873
 
874 64 unneback
        //parameter width = 1;
875
        parameter reset_value = 1'b0;
876 29 unneback
 
877
        input sp, r;
878
        output reg q;
879
        input clk, rst;
880
 
881
        always @ (posedge clk or posedge rst)
882
        if (rst)
883
            q <= reset_value;
884
        else
885
            if (sp)
886
                q <= 1'b1;
887
            else if (r)
888
                q <= 1'b0;
889
 
890
endmodule
891 40 unneback
`endif
892 29 unneback
 
893 40 unneback
`ifdef SRP
894
`define MODULE srp
895
module `BASE`MODULE ( s, rp, q, clk, rst);
896
`undef MODULE
897
 
898 29 unneback
        parameter width = 1;
899
        parameter reset_value = 0;
900
 
901
        input s, rp;
902
        output reg q;
903
        input clk, rst;
904
 
905
        always @ (posedge clk or posedge rst)
906
        if (rst)
907
            q <= reset_value;
908
        else
909
            if (rp)
910
                q <= 1'b0;
911
            else if (s)
912
                q <= 1'b1;
913
 
914
endmodule
915 40 unneback
`endif
916 29 unneback
 
917 40 unneback
`ifdef ALTERA
918 29 unneback
 
919 40 unneback
`ifdef DFF_SR
920 6 unneback
// megafunction wizard: %LPM_FF%
921
// GENERATION: STANDARD
922
// VERSION: WM1.0
923
// MODULE: lpm_ff 
924
 
925
// ============================================================
926
// File Name: dff_sr.v
927
// Megafunction Name(s):
928
//                      lpm_ff
929
//
930
// Simulation Library Files(s):
931
//                      lpm
932
// ============================================================
933
// ************************************************************
934
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
935
//
936
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
937
// ************************************************************
938
 
939
 
940
//Copyright (C) 1991-2010 Altera Corporation
941
//Your use of Altera Corporation's design tools, logic functions 
942
//and other software and tools, and its AMPP partner logic 
943
//functions, and any output files from any of the foregoing 
944
//(including device programming or simulation files), and any 
945
//associated documentation or information are expressly subject 
946
//to the terms and conditions of the Altera Program License 
947
//Subscription Agreement, Altera MegaCore Function License 
948
//Agreement, or other applicable license agreement, including, 
949
//without limitation, that your use is for the sole purpose of 
950
//programming logic devices manufactured by Altera and sold by 
951
//Altera or its authorized distributors.  Please refer to the 
952
//applicable agreement for further details.
953
 
954
 
955
// synopsys translate_off
956
`timescale 1 ps / 1 ps
957
// synopsys translate_on
958 40 unneback
`define MODULE dff_sr
959
module `BASE`MODULE (
960
`undef MODULE
961
 
962 6 unneback
        aclr,
963
        aset,
964
        clock,
965
        data,
966
        q);
967
 
968
        input     aclr;
969
        input     aset;
970
        input     clock;
971
        input     data;
972
        output    q;
973
 
974
        wire [0:0] sub_wire0;
975
        wire [0:0] sub_wire1 = sub_wire0[0:0];
976
        wire  q = sub_wire1;
977
        wire  sub_wire2 = data;
978
        wire  sub_wire3 = sub_wire2;
979
 
980
        lpm_ff  lpm_ff_component (
981
                                .aclr (aclr),
982
                                .clock (clock),
983
                                .data (sub_wire3),
984
                                .aset (aset),
985
                                .q (sub_wire0)
986
                                // synopsys translate_off
987
                                ,
988
                                .aload (),
989
                                .enable (),
990
                                .sclr (),
991
                                .sload (),
992
                                .sset ()
993
                                // synopsys translate_on
994
                                );
995
        defparam
996
                lpm_ff_component.lpm_fftype = "DFF",
997
                lpm_ff_component.lpm_type = "LPM_FF",
998
                lpm_ff_component.lpm_width = 1;
999
 
1000
 
1001
endmodule
1002
 
1003
// ============================================================
1004
// CNX file retrieval info
1005
// ============================================================
1006
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1007
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1008
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1009
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1010
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1011
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1012
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1013
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1014
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1015
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1016
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1017
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1018
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1019
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1020
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1021
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1022
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1023
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1024
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1025
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1026
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1027
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1028
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1029
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1030
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1031
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1032
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1033
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1034
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1035
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1036
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1037
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1038
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1039
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1040
// Retrieval info: LIB_FILE: lpm
1041 40 unneback
`endif
1042 6 unneback
 
1043
`else
1044
 
1045 40 unneback
`ifdef DFF_SR
1046
`define MODULE dff_sr
1047
module `BASE`MODULE ( aclr, aset, clock, data, q);
1048
`undef MODULE
1049 6 unneback
 
1050
    input         aclr;
1051
    input         aset;
1052
    input         clock;
1053
    input         data;
1054
    output reg    q;
1055
 
1056
   always @ (posedge clock or posedge aclr or posedge aset)
1057
     if (aclr)
1058
       q <= 1'b0;
1059
     else if (aset)
1060
       q <= 1'b1;
1061
     else
1062
       q <= data;
1063
 
1064
endmodule
1065 40 unneback
`endif
1066 6 unneback
 
1067
`endif
1068
 
1069
// LATCH
1070
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1071
`ifdef ALTERA
1072 40 unneback
 
1073
`ifdef LATCH
1074
`define MODULE latch
1075
module `BASE`MODULE ( d, le, q, clk);
1076
`undef MODULE
1077 6 unneback
input d, le;
1078
output q;
1079
input clk;
1080
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1081
endmodule
1082 40 unneback
`endif
1083
 
1084 6 unneback
`else
1085 40 unneback
 
1086
`ifdef LATCH
1087
`define MODULE latch
1088
module `BASE`MODULE ( d, le, q, clk);
1089
`undef MODULE
1090 6 unneback
input d, le;
1091 48 unneback
input clk;
1092
always @ (le or d)
1093 60 unneback
if (le)
1094 48 unneback
    d <= q;
1095 6 unneback
endmodule
1096 15 unneback
`endif
1097
 
1098 40 unneback
`endif
1099
 
1100
`ifdef SHREG
1101
`define MODULE shreg
1102
module `BASE`MODULE ( d, q, clk, rst);
1103
`undef MODULE
1104
 
1105 17 unneback
parameter depth = 10;
1106
input d;
1107
output q;
1108
input clk, rst;
1109
 
1110
reg [1:depth] dffs;
1111
 
1112
always @ (posedge clk or posedge rst)
1113
if (rst)
1114
    dffs <= {depth{1'b0}};
1115
else
1116
    dffs <= {d,dffs[1:depth-1]};
1117
assign q = dffs[depth];
1118
endmodule
1119 40 unneback
`endif
1120 17 unneback
 
1121 40 unneback
`ifdef SHREG_CE
1122
`define MODULE shreg_ce
1123
module `BASE`MODULE ( d, ce, q, clk, rst);
1124
`undef MODULE
1125 17 unneback
parameter depth = 10;
1126
input d, ce;
1127
output q;
1128
input clk, rst;
1129
 
1130
reg [1:depth] dffs;
1131
 
1132
always @ (posedge clk or posedge rst)
1133
if (rst)
1134
    dffs <= {depth{1'b0}};
1135
else
1136
    if (ce)
1137
        dffs <= {d,dffs[1:depth-1]};
1138
assign q = dffs[depth];
1139
endmodule
1140 40 unneback
`endif
1141 17 unneback
 
1142 40 unneback
`ifdef DELAY
1143
`define MODULE delay
1144
module `BASE`MODULE ( d, q, clk, rst);
1145
`undef MODULE
1146 15 unneback
parameter depth = 10;
1147
input d;
1148
output q;
1149
input clk, rst;
1150
 
1151
reg [1:depth] dffs;
1152
 
1153
always @ (posedge clk or posedge rst)
1154
if (rst)
1155
    dffs <= {depth{1'b0}};
1156
else
1157
    dffs <= {d,dffs[1:depth-1]};
1158
assign q = dffs[depth];
1159 17 unneback
endmodule
1160 40 unneback
`endif
1161 17 unneback
 
1162 40 unneback
`ifdef DELAY_EMPTYFLAG
1163
`define MODULE delay_emptyflag
1164 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1165 40 unneback
`undef MODULE
1166 17 unneback
parameter depth = 10;
1167
input d;
1168
output q, emptyflag;
1169
input clk, rst;
1170
 
1171
reg [1:depth] dffs;
1172
 
1173
always @ (posedge clk or posedge rst)
1174
if (rst)
1175
    dffs <= {depth{1'b0}};
1176
else
1177
    dffs <= {d,dffs[1:depth-1]};
1178
assign q = dffs[depth];
1179
assign emptyflag = !(|dffs);
1180
endmodule
1181 40 unneback
`endif
1182 75 unneback
 
1183 94 unneback
`ifdef PULSE2TOGGLE
1184
`define MODULE pules2toggle
1185
module `BASE`MODULE ( pl, q, clk, rst)
1186 75 unneback
`undef MODULE
1187 94 unneback
input pl;
1188
output q;
1189
input clk, rst;
1190
input
1191
always @ (posedge clk or posedge rst)
1192 75 unneback
if (rst)
1193 94 unneback
    q <= 1'b0;
1194 75 unneback
else
1195 94 unneback
    q <= pl ^ q;
1196
endmodule
1197
`endif
1198 75 unneback
 
1199 94 unneback
`ifdef TOGGLE2PULSE
1200
`define MODULE toggle2pulse;
1201
module `BASE`MODULE (d, pl, clk, rst);
1202 97 unneback
`undef MODULE
1203 94 unneback
input d;
1204
output pl;
1205
input clk, rst;
1206
reg dff;
1207
always @ (posedge clk or posedge rst)
1208
if (rst)
1209
    dff <= 1'b0;
1210 75 unneback
else
1211 94 unneback
    dff <= d;
1212
assign d ^ dff;
1213
endmodule
1214
`endif
1215 75 unneback
 
1216 94 unneback
`ifdef SYNCHRONIZER
1217
`define MODULE synchronizer
1218
module `BASE`MODULE (d, q, clk, rst);
1219
`undef MODULE
1220
input d;
1221
output reg q;
1222
output clk, rst;
1223
reg dff;
1224
always @ (posedge clk or posedge rst)
1225
if (rst)
1226
    {dff,q} <= 2'b00;
1227 75 unneback
else
1228 94 unneback
    {dff,q} <= {d,dff};
1229
endmodule
1230
`endif
1231 75 unneback
 
1232 94 unneback
`ifdef CDC
1233
`define MODULE cdc
1234 97 unneback
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1235 94 unneback
`undef MODULE
1236
input start_pl;
1237
output take_it_pl;
1238
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1239
output got_it_pl;
1240
input clk_src, rst_src;
1241
input clk_dst, rst_dst;
1242
wire take_it_tg, take_it_tg_sync;
1243
wire got_it_tg, got_it_tg_sync;
1244
// src -> dst
1245
`define MODULE pulse2toggle
1246
`BASE`MODULE p2t0 (
1247
`undef MODULE
1248
    .pl(start_pl),
1249
    .q(take_it_tg),
1250
    .clk(clk_src),
1251
    .rst(rst_src));
1252 75 unneback
 
1253 94 unneback
`define MODULE synchronizer
1254
`BASE`MODULE sync0 (
1255
`undef MODULE
1256
    .d(take_it_tg),
1257
    .q(take_it_tg_sync),
1258
    .clk(clk_dst),
1259
    .rst(rst_dst));
1260
 
1261
`define MODULE toggle2pulse
1262
`BASE`MODULE t2p0 (
1263
`undef MODULE
1264
    .d(take_it_sync),
1265
    .pl(take_it_pl),
1266
    .clk(clk_dst),
1267
    .rst(rst_dst));
1268
 
1269
// dst -> src
1270
`define MODULE pulse2toggle
1271
`BASE`MODULE p2t0 (
1272
`undef MODULE
1273
    .pl(take_it_grant_pl),
1274
    .q(got_it_tg),
1275
    .clk(clk_dst),
1276
    .rst(rst_dst));
1277
 
1278
`define MODULE synchronizer
1279
`BASE`MODULE sync1 (
1280
`undef MODULE
1281
    .d(got_it_tg),
1282
    .q(got_it_tg_sync),
1283
    .clk(clk_src),
1284
    .rst(rst_src));
1285
 
1286
`define MODULE toggle2pulse
1287
`BASE`MODULE t2p1 (
1288
`undef MODULE
1289
    .d(take_it_grant_tg_sync),
1290
    .pl(got_it_pl),
1291
    .clk(clk_src),
1292
    .rst(rst_src));
1293
 
1294 75 unneback
endmodule
1295
`endif
1296 17 unneback
//////////////////////////////////////////////////////////////////////
1297 6 unneback
////                                                              ////
1298 18 unneback
////  Logic functions                                             ////
1299
////                                                              ////
1300
////  Description                                                 ////
1301
////  Logic functions such as multiplexers                        ////
1302
////                                                              ////
1303
////                                                              ////
1304
////  To Do:                                                      ////
1305
////   -                                                          ////
1306
////                                                              ////
1307
////  Author(s):                                                  ////
1308
////      - Michael Unneback, unneback@opencores.org              ////
1309
////        ORSoC AB                                              ////
1310
////                                                              ////
1311
//////////////////////////////////////////////////////////////////////
1312
////                                                              ////
1313
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1314
////                                                              ////
1315
//// This source file may be used and distributed without         ////
1316
//// restriction provided that this copyright statement is not    ////
1317
//// removed from the file and that any derivative work contains  ////
1318
//// the original copyright notice and the associated disclaimer. ////
1319
////                                                              ////
1320
//// This source file is free software; you can redistribute it   ////
1321
//// and/or modify it under the terms of the GNU Lesser General   ////
1322
//// Public License as published by the Free Software Foundation; ////
1323
//// either version 2.1 of the License, or (at your option) any   ////
1324
//// later version.                                               ////
1325
////                                                              ////
1326
//// This source is distributed in the hope that it will be       ////
1327
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1328
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1329
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1330
//// details.                                                     ////
1331
////                                                              ////
1332
//// You should have received a copy of the GNU Lesser General    ////
1333
//// Public License along with this source; if not, download it   ////
1334
//// from http://www.opencores.org/lgpl.shtml                     ////
1335
////                                                              ////
1336
//////////////////////////////////////////////////////////////////////
1337 40 unneback
`ifdef MUX_ANDOR
1338
`define MODULE mux_andor
1339
module `BASE`MODULE ( a, sel, dout);
1340
`undef MODULE
1341 36 unneback
 
1342
parameter width = 32;
1343
parameter nr_of_ports = 4;
1344
 
1345
input [nr_of_ports*width-1:0] a;
1346
input [nr_of_ports-1:0] sel;
1347
output reg [width-1:0] dout;
1348
 
1349 38 unneback
integer i,j;
1350
 
1351 36 unneback
always @ (a, sel)
1352
begin
1353
    dout = a[width-1:0] & {width{sel[0]}};
1354 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1355
        for (j=0;j<width;j=j+1)
1356
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1357 36 unneback
end
1358
 
1359
endmodule
1360 40 unneback
`endif
1361 36 unneback
 
1362 40 unneback
`ifdef MUX2_ANDOR
1363
`define MODULE mux2_andor
1364
module `BASE`MODULE ( a1, a0, sel, dout);
1365
`undef MODULE
1366 18 unneback
 
1367 34 unneback
parameter width = 32;
1368 35 unneback
localparam nr_of_ports = 2;
1369 34 unneback
input [width-1:0] a1, a0;
1370
input [nr_of_ports-1:0] sel;
1371
output [width-1:0] dout;
1372
 
1373 40 unneback
`define MODULE mux_andor
1374
`BASE`MODULE
1375 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1376 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1377 40 unneback
`undef MODULE
1378
 
1379 34 unneback
endmodule
1380 40 unneback
`endif
1381 34 unneback
 
1382 40 unneback
`ifdef MUX3_ANDOR
1383
`define MODULE mux3_andor
1384
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1385
`undef MODULE
1386 34 unneback
 
1387
parameter width = 32;
1388 35 unneback
localparam nr_of_ports = 3;
1389 34 unneback
input [width-1:0] a2, a1, a0;
1390
input [nr_of_ports-1:0] sel;
1391
output [width-1:0] dout;
1392
 
1393 40 unneback
`define MODULE mux_andor
1394
`BASE`MODULE
1395 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1396 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1397 40 unneback
`undef MODULE
1398 34 unneback
endmodule
1399 40 unneback
`endif
1400 34 unneback
 
1401 40 unneback
`ifdef MUX4_ANDOR
1402
`define MODULE mux4_andor
1403
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1404
`undef MODULE
1405 18 unneback
 
1406
parameter width = 32;
1407 35 unneback
localparam nr_of_ports = 4;
1408 18 unneback
input [width-1:0] a3, a2, a1, a0;
1409
input [nr_of_ports-1:0] sel;
1410 22 unneback
output [width-1:0] dout;
1411 18 unneback
 
1412 40 unneback
`define MODULE mux_andor
1413
`BASE`MODULE
1414 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1415 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1416 40 unneback
`undef MODULE
1417 18 unneback
 
1418
endmodule
1419 40 unneback
`endif
1420 18 unneback
 
1421 40 unneback
`ifdef MUX5_ANDOR
1422
`define MODULE mux5_andor
1423
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1424
`undef MODULE
1425 18 unneback
 
1426
parameter width = 32;
1427 35 unneback
localparam nr_of_ports = 5;
1428 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1429
input [nr_of_ports-1:0] sel;
1430 22 unneback
output [width-1:0] dout;
1431 18 unneback
 
1432 40 unneback
`define MODULE mux_andor
1433
`BASE`MODULE
1434 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1435 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1436 40 unneback
`undef MODULE
1437 18 unneback
 
1438
endmodule
1439 40 unneback
`endif
1440 18 unneback
 
1441 40 unneback
`ifdef MUX6_ANDOR
1442
`define MODULE mux6_andor
1443
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1444
`undef MODULE
1445 18 unneback
 
1446
parameter width = 32;
1447 35 unneback
localparam nr_of_ports = 6;
1448 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1449
input [nr_of_ports-1:0] sel;
1450 22 unneback
output [width-1:0] dout;
1451 18 unneback
 
1452 40 unneback
`define MODULE mux_andor
1453
`BASE`MODULE
1454 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1455 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1456 40 unneback
`undef MODULE
1457 18 unneback
 
1458
endmodule
1459 40 unneback
`endif
1460 43 unneback
 
1461
`ifdef PARITY
1462
 
1463
`define MODULE parity_generate
1464
module `BASE`MODULE (data, parity);
1465
`undef MODULE
1466
parameter word_size = 32;
1467
parameter chunk_size = 8;
1468
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1469
input [word_size-1:0] data;
1470
output reg [word_size/chunk_size-1:0] parity;
1471
integer i,j;
1472
always @ (data)
1473
for (i=0;i<word_size/chunk_size;i=i+1) begin
1474
    parity[i] = parity_type;
1475
    for (j=0;j<chunk_size;j=j+1) begin
1476 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1477 43 unneback
    end
1478
end
1479
endmodule
1480
 
1481
`define MODULE parity_check
1482
module `BASE`MODULE( data, parity, parity_error);
1483
`undef MODULE
1484
parameter word_size = 32;
1485
parameter chunk_size = 8;
1486
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1487
input [word_size-1:0] data;
1488
input [word_size/chunk_size-1:0] parity;
1489
output parity_error;
1490 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1491 43 unneback
integer i,j;
1492
always @ (data or parity)
1493
for (i=0;i<word_size/chunk_size;i=i+1) begin
1494
    error_flag[i] = parity[i] ^ parity_type;
1495
    for (j=0;j<chunk_size;j=j+1) begin
1496 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1497 43 unneback
    end
1498
end
1499
assign parity_error = |error_flag;
1500
endmodule
1501
 
1502 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1503
////                                                              ////
1504
////  IO functions                                                ////
1505
////                                                              ////
1506
////  Description                                                 ////
1507
////  IO functions such as IOB flip-flops                         ////
1508
////                                                              ////
1509
////                                                              ////
1510
////  To Do:                                                      ////
1511
////   -                                                          ////
1512
////                                                              ////
1513
////  Author(s):                                                  ////
1514
////      - Michael Unneback, unneback@opencores.org              ////
1515
////        ORSoC AB                                              ////
1516
////                                                              ////
1517 18 unneback
//////////////////////////////////////////////////////////////////////
1518
////                                                              ////
1519 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1520
////                                                              ////
1521
//// This source file may be used and distributed without         ////
1522
//// restriction provided that this copyright statement is not    ////
1523
//// removed from the file and that any derivative work contains  ////
1524
//// the original copyright notice and the associated disclaimer. ////
1525
////                                                              ////
1526
//// This source file is free software; you can redistribute it   ////
1527
//// and/or modify it under the terms of the GNU Lesser General   ////
1528
//// Public License as published by the Free Software Foundation; ////
1529
//// either version 2.1 of the License, or (at your option) any   ////
1530
//// later version.                                               ////
1531
////                                                              ////
1532
//// This source is distributed in the hope that it will be       ////
1533
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1534
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1535
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1536
//// details.                                                     ////
1537
////                                                              ////
1538
//// You should have received a copy of the GNU Lesser General    ////
1539
//// Public License along with this source; if not, download it   ////
1540
//// from http://www.opencores.org/lgpl.shtml                     ////
1541
////                                                              ////
1542
//////////////////////////////////////////////////////////////////////
1543 45 unneback
`timescale 1ns/1ns
1544 44 unneback
`ifdef O_DFF
1545
`define MODULE o_dff
1546
module `BASE`MODULE (d_i, o_pad, clk, rst);
1547
`undef MODULE
1548
parameter width = 1;
1549 45 unneback
parameter reset_value = {width{1'b0}};
1550
input  [width-1:0]  d_i;
1551 44 unneback
output [width-1:0] o_pad;
1552
input clk, rst;
1553
wire [width-1:0] d_i_int `SYN_KEEP;
1554 45 unneback
reg  [width-1:0] o_pad_int;
1555 44 unneback
assign d_i_int = d_i;
1556
genvar i;
1557 45 unneback
generate
1558 44 unneback
for (i=0;i<width;i=i+1) begin
1559
    always @ (posedge clk or posedge rst)
1560
    if (rst)
1561 45 unneback
        o_pad_int[i] <= reset_value[i];
1562 44 unneback
    else
1563 45 unneback
        o_pad_int[i] <= d_i_int[i];
1564
    assign #1 o_pad[i] = o_pad_int[i];
1565 44 unneback
end
1566
endgenerate
1567
endmodule
1568
`endif
1569
 
1570 45 unneback
`timescale 1ns/1ns
1571 44 unneback
`ifdef IO_DFF_OE
1572
`define MODULE io_dff_oe
1573
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1574
`undef MODULE
1575
parameter width = 1;
1576
input  [width-1:0] d_o;
1577
output reg [width-1:0] d_i;
1578
input oe;
1579
inout [width-1:0] io_pad;
1580
input clk, rst;
1581
wire [width-1:0] oe_d `SYN_KEEP;
1582
reg [width-1:0] oe_q;
1583
reg [width-1:0] d_o_q;
1584
assign oe_d = {width{oe}};
1585
genvar i;
1586
generate
1587
for (i=0;i<width;i=i+1) begin
1588
    always @ (posedge clk or posedge rst)
1589
    if (rst)
1590
        oe_q[i] <= 1'b0;
1591
    else
1592
        oe_q[i] <= oe_d[i];
1593
    always @ (posedge clk or posedge rst)
1594
    if (rst)
1595
        d_o_q[i] <= 1'b0;
1596
    else
1597
        d_o_q[i] <= d_o[i];
1598
    always @ (posedge clk or posedge rst)
1599
    if (rst)
1600
        d_i[i] <= 1'b0;
1601
    else
1602
        d_i[i] <= io_pad[i];
1603 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1604 44 unneback
end
1605
endgenerate
1606
endmodule
1607
`endif
1608
`ifdef CNT_BIN
1609
//////////////////////////////////////////////////////////////////////
1610
////                                                              ////
1611 6 unneback
////  Versatile counter                                           ////
1612
////                                                              ////
1613
////  Description                                                 ////
1614
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1615
////  counter                                                     ////
1616
////                                                              ////
1617
////  To Do:                                                      ////
1618
////   - add LFSR with more taps                                  ////
1619
////                                                              ////
1620
////  Author(s):                                                  ////
1621
////      - Michael Unneback, unneback@opencores.org              ////
1622
////        ORSoC AB                                              ////
1623
////                                                              ////
1624
//////////////////////////////////////////////////////////////////////
1625
////                                                              ////
1626
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1627
////                                                              ////
1628
//// This source file may be used and distributed without         ////
1629
//// restriction provided that this copyright statement is not    ////
1630
//// removed from the file and that any derivative work contains  ////
1631
//// the original copyright notice and the associated disclaimer. ////
1632
////                                                              ////
1633
//// This source file is free software; you can redistribute it   ////
1634
//// and/or modify it under the terms of the GNU Lesser General   ////
1635
//// Public License as published by the Free Software Foundation; ////
1636
//// either version 2.1 of the License, or (at your option) any   ////
1637
//// later version.                                               ////
1638
////                                                              ////
1639
//// This source is distributed in the hope that it will be       ////
1640
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1641
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1642
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1643
//// details.                                                     ////
1644
////                                                              ////
1645
//// You should have received a copy of the GNU Lesser General    ////
1646
//// Public License along with this source; if not, download it   ////
1647
//// from http://www.opencores.org/lgpl.shtml                     ////
1648
////                                                              ////
1649
//////////////////////////////////////////////////////////////////////
1650
 
1651
// binary counter
1652 22 unneback
 
1653 40 unneback
`define MODULE cnt_bin
1654
module `BASE`MODULE (
1655
`undef MODULE
1656
 q, rst, clk);
1657
 
1658 22 unneback
   parameter length = 4;
1659
   output [length:1] q;
1660
   input rst;
1661
   input clk;
1662
 
1663
   parameter clear_value = 0;
1664
   parameter set_value = 1;
1665
   parameter wrap_value = 0;
1666
   parameter level1_value = 15;
1667
 
1668
   reg  [length:1] qi;
1669
   wire [length:1] q_next;
1670
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1671
 
1672
   always @ (posedge clk or posedge rst)
1673
     if (rst)
1674
       qi <= {length{1'b0}};
1675
     else
1676
       qi <= q_next;
1677
 
1678
   assign q = qi;
1679
 
1680
endmodule
1681 40 unneback
`endif
1682
`ifdef CNT_BIN_CLEAR
1683 22 unneback
//////////////////////////////////////////////////////////////////////
1684
////                                                              ////
1685
////  Versatile counter                                           ////
1686
////                                                              ////
1687
////  Description                                                 ////
1688
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1689
////  counter                                                     ////
1690
////                                                              ////
1691
////  To Do:                                                      ////
1692
////   - add LFSR with more taps                                  ////
1693
////                                                              ////
1694
////  Author(s):                                                  ////
1695
////      - Michael Unneback, unneback@opencores.org              ////
1696
////        ORSoC AB                                              ////
1697
////                                                              ////
1698
//////////////////////////////////////////////////////////////////////
1699
////                                                              ////
1700
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1701
////                                                              ////
1702
//// This source file may be used and distributed without         ////
1703
//// restriction provided that this copyright statement is not    ////
1704
//// removed from the file and that any derivative work contains  ////
1705
//// the original copyright notice and the associated disclaimer. ////
1706
////                                                              ////
1707
//// This source file is free software; you can redistribute it   ////
1708
//// and/or modify it under the terms of the GNU Lesser General   ////
1709
//// Public License as published by the Free Software Foundation; ////
1710
//// either version 2.1 of the License, or (at your option) any   ////
1711
//// later version.                                               ////
1712
////                                                              ////
1713
//// This source is distributed in the hope that it will be       ////
1714
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1715
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1716
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1717
//// details.                                                     ////
1718
////                                                              ////
1719
//// You should have received a copy of the GNU Lesser General    ////
1720
//// Public License along with this source; if not, download it   ////
1721
//// from http://www.opencores.org/lgpl.shtml                     ////
1722
////                                                              ////
1723
//////////////////////////////////////////////////////////////////////
1724
 
1725
// binary counter
1726
 
1727 40 unneback
`define MODULE cnt_bin_clear
1728
module `BASE`MODULE (
1729
`undef MODULE
1730
 clear, q, rst, clk);
1731
 
1732 22 unneback
   parameter length = 4;
1733
   input clear;
1734
   output [length:1] q;
1735
   input rst;
1736
   input clk;
1737
 
1738
   parameter clear_value = 0;
1739
   parameter set_value = 1;
1740
   parameter wrap_value = 0;
1741
   parameter level1_value = 15;
1742
 
1743
   reg  [length:1] qi;
1744
   wire [length:1] q_next;
1745
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1746
 
1747
   always @ (posedge clk or posedge rst)
1748
     if (rst)
1749
       qi <= {length{1'b0}};
1750
     else
1751
       qi <= q_next;
1752
 
1753
   assign q = qi;
1754
 
1755
endmodule
1756 40 unneback
`endif
1757
`ifdef CNT_BIN_CE
1758 22 unneback
//////////////////////////////////////////////////////////////////////
1759
////                                                              ////
1760
////  Versatile counter                                           ////
1761
////                                                              ////
1762
////  Description                                                 ////
1763
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1764
////  counter                                                     ////
1765
////                                                              ////
1766
////  To Do:                                                      ////
1767
////   - add LFSR with more taps                                  ////
1768
////                                                              ////
1769
////  Author(s):                                                  ////
1770
////      - Michael Unneback, unneback@opencores.org              ////
1771
////        ORSoC AB                                              ////
1772
////                                                              ////
1773
//////////////////////////////////////////////////////////////////////
1774
////                                                              ////
1775
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1776
////                                                              ////
1777
//// This source file may be used and distributed without         ////
1778
//// restriction provided that this copyright statement is not    ////
1779
//// removed from the file and that any derivative work contains  ////
1780
//// the original copyright notice and the associated disclaimer. ////
1781
////                                                              ////
1782
//// This source file is free software; you can redistribute it   ////
1783
//// and/or modify it under the terms of the GNU Lesser General   ////
1784
//// Public License as published by the Free Software Foundation; ////
1785
//// either version 2.1 of the License, or (at your option) any   ////
1786
//// later version.                                               ////
1787
////                                                              ////
1788
//// This source is distributed in the hope that it will be       ////
1789
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1790
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1791
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1792
//// details.                                                     ////
1793
////                                                              ////
1794
//// You should have received a copy of the GNU Lesser General    ////
1795
//// Public License along with this source; if not, download it   ////
1796
//// from http://www.opencores.org/lgpl.shtml                     ////
1797
////                                                              ////
1798
//////////////////////////////////////////////////////////////////////
1799
 
1800
// binary counter
1801 6 unneback
 
1802 40 unneback
`define MODULE cnt_bin_ce
1803
module `BASE`MODULE (
1804
`undef MODULE
1805
 cke, q, rst, clk);
1806
 
1807 6 unneback
   parameter length = 4;
1808
   input cke;
1809
   output [length:1] q;
1810
   input rst;
1811
   input clk;
1812
 
1813
   parameter clear_value = 0;
1814
   parameter set_value = 1;
1815
   parameter wrap_value = 0;
1816
   parameter level1_value = 15;
1817
 
1818
   reg  [length:1] qi;
1819
   wire [length:1] q_next;
1820
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1821
 
1822
   always @ (posedge clk or posedge rst)
1823
     if (rst)
1824
       qi <= {length{1'b0}};
1825
     else
1826
     if (cke)
1827
       qi <= q_next;
1828
 
1829
   assign q = qi;
1830
 
1831
endmodule
1832 40 unneback
`endif
1833
`ifdef CNT_BIN_CE_CLEAR
1834 6 unneback
//////////////////////////////////////////////////////////////////////
1835
////                                                              ////
1836
////  Versatile counter                                           ////
1837
////                                                              ////
1838
////  Description                                                 ////
1839
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1840
////  counter                                                     ////
1841
////                                                              ////
1842
////  To Do:                                                      ////
1843
////   - add LFSR with more taps                                  ////
1844
////                                                              ////
1845
////  Author(s):                                                  ////
1846
////      - Michael Unneback, unneback@opencores.org              ////
1847
////        ORSoC AB                                              ////
1848
////                                                              ////
1849
//////////////////////////////////////////////////////////////////////
1850
////                                                              ////
1851
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1852
////                                                              ////
1853
//// This source file may be used and distributed without         ////
1854
//// restriction provided that this copyright statement is not    ////
1855
//// removed from the file and that any derivative work contains  ////
1856
//// the original copyright notice and the associated disclaimer. ////
1857
////                                                              ////
1858
//// This source file is free software; you can redistribute it   ////
1859
//// and/or modify it under the terms of the GNU Lesser General   ////
1860
//// Public License as published by the Free Software Foundation; ////
1861
//// either version 2.1 of the License, or (at your option) any   ////
1862
//// later version.                                               ////
1863
////                                                              ////
1864
//// This source is distributed in the hope that it will be       ////
1865
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1866
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1867
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1868
//// details.                                                     ////
1869
////                                                              ////
1870
//// You should have received a copy of the GNU Lesser General    ////
1871
//// Public License along with this source; if not, download it   ////
1872
//// from http://www.opencores.org/lgpl.shtml                     ////
1873
////                                                              ////
1874
//////////////////////////////////////////////////////////////////////
1875
 
1876
// binary counter
1877
 
1878 40 unneback
`define MODULE cnt_bin_ce_clear
1879
module `BASE`MODULE (
1880
`undef MODULE
1881
 clear, cke, q, rst, clk);
1882
 
1883 6 unneback
   parameter length = 4;
1884
   input clear;
1885
   input cke;
1886
   output [length:1] q;
1887
   input rst;
1888
   input clk;
1889
 
1890
   parameter clear_value = 0;
1891
   parameter set_value = 1;
1892
   parameter wrap_value = 0;
1893
   parameter level1_value = 15;
1894
 
1895
   reg  [length:1] qi;
1896
   wire [length:1] q_next;
1897
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1898
 
1899
   always @ (posedge clk or posedge rst)
1900
     if (rst)
1901
       qi <= {length{1'b0}};
1902
     else
1903
     if (cke)
1904
       qi <= q_next;
1905
 
1906
   assign q = qi;
1907
 
1908
endmodule
1909 40 unneback
`endif
1910
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1911 6 unneback
//////////////////////////////////////////////////////////////////////
1912
////                                                              ////
1913
////  Versatile counter                                           ////
1914
////                                                              ////
1915
////  Description                                                 ////
1916
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1917
////  counter                                                     ////
1918
////                                                              ////
1919
////  To Do:                                                      ////
1920
////   - add LFSR with more taps                                  ////
1921
////                                                              ////
1922
////  Author(s):                                                  ////
1923
////      - Michael Unneback, unneback@opencores.org              ////
1924
////        ORSoC AB                                              ////
1925
////                                                              ////
1926
//////////////////////////////////////////////////////////////////////
1927
////                                                              ////
1928
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1929
////                                                              ////
1930
//// This source file may be used and distributed without         ////
1931
//// restriction provided that this copyright statement is not    ////
1932
//// removed from the file and that any derivative work contains  ////
1933
//// the original copyright notice and the associated disclaimer. ////
1934
////                                                              ////
1935
//// This source file is free software; you can redistribute it   ////
1936
//// and/or modify it under the terms of the GNU Lesser General   ////
1937
//// Public License as published by the Free Software Foundation; ////
1938
//// either version 2.1 of the License, or (at your option) any   ////
1939
//// later version.                                               ////
1940
////                                                              ////
1941
//// This source is distributed in the hope that it will be       ////
1942
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1943
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1944
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1945
//// details.                                                     ////
1946
////                                                              ////
1947
//// You should have received a copy of the GNU Lesser General    ////
1948
//// Public License along with this source; if not, download it   ////
1949
//// from http://www.opencores.org/lgpl.shtml                     ////
1950
////                                                              ////
1951
//////////////////////////////////////////////////////////////////////
1952
 
1953
// binary counter
1954 29 unneback
 
1955 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1956
module `BASE`MODULE (
1957
`undef MODULE
1958
 clear, cke, q, level1, level2, rst, clk);
1959
 
1960 29 unneback
   parameter length = 4;
1961
   input clear;
1962
   input cke;
1963
   output [length:1] q;
1964
   output reg level1;
1965
   output reg level2;
1966
   input rst;
1967
   input clk;
1968
 
1969
   parameter clear_value = 0;
1970
   parameter set_value = 1;
1971 30 unneback
   parameter wrap_value = 15;
1972
   parameter level1_value = 8;
1973
   parameter level2_value = 15;
1974 29 unneback
 
1975
   wire rew;
1976 30 unneback
   assign rew = 1'b0;
1977 29 unneback
   reg  [length:1] qi;
1978
   wire [length:1] q_next;
1979
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1980
 
1981
   always @ (posedge clk or posedge rst)
1982
     if (rst)
1983
       qi <= {length{1'b0}};
1984
     else
1985
     if (cke)
1986
       qi <= q_next;
1987
 
1988
   assign q = qi;
1989
 
1990
 
1991
    always @ (posedge clk or posedge rst)
1992
    if (rst)
1993
        level1 <= 1'b0;
1994
    else
1995
    if (cke)
1996
    if (clear)
1997
        level1 <= 1'b0;
1998
    else if (q_next == level1_value)
1999
        level1 <= 1'b1;
2000
    else if (qi == level1_value & rew)
2001
        level1 <= 1'b0;
2002
 
2003
    always @ (posedge clk or posedge rst)
2004
    if (rst)
2005
        level2 <= 1'b0;
2006
    else
2007
    if (cke)
2008
    if (clear)
2009
        level2 <= 1'b0;
2010
    else if (q_next == level2_value)
2011
        level2 <= 1'b1;
2012
    else if (qi == level2_value & rew)
2013
        level2 <= 1'b0;
2014
endmodule
2015 40 unneback
`endif
2016
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2017 29 unneback
//////////////////////////////////////////////////////////////////////
2018
////                                                              ////
2019
////  Versatile counter                                           ////
2020
////                                                              ////
2021
////  Description                                                 ////
2022
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2023
////  counter                                                     ////
2024
////                                                              ////
2025
////  To Do:                                                      ////
2026
////   - add LFSR with more taps                                  ////
2027
////                                                              ////
2028
////  Author(s):                                                  ////
2029
////      - Michael Unneback, unneback@opencores.org              ////
2030
////        ORSoC AB                                              ////
2031
////                                                              ////
2032
//////////////////////////////////////////////////////////////////////
2033
////                                                              ////
2034
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2035
////                                                              ////
2036
//// This source file may be used and distributed without         ////
2037
//// restriction provided that this copyright statement is not    ////
2038
//// removed from the file and that any derivative work contains  ////
2039
//// the original copyright notice and the associated disclaimer. ////
2040
////                                                              ////
2041
//// This source file is free software; you can redistribute it   ////
2042
//// and/or modify it under the terms of the GNU Lesser General   ////
2043
//// Public License as published by the Free Software Foundation; ////
2044
//// either version 2.1 of the License, or (at your option) any   ////
2045
//// later version.                                               ////
2046
////                                                              ////
2047
//// This source is distributed in the hope that it will be       ////
2048
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2049
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2050
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2051
//// details.                                                     ////
2052
////                                                              ////
2053
//// You should have received a copy of the GNU Lesser General    ////
2054
//// Public License along with this source; if not, download it   ////
2055
//// from http://www.opencores.org/lgpl.shtml                     ////
2056
////                                                              ////
2057
//////////////////////////////////////////////////////////////////////
2058
 
2059
// binary counter
2060 6 unneback
 
2061 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2062
module `BASE`MODULE (
2063
`undef MODULE
2064
 clear, set, cke, rew, q, rst, clk);
2065
 
2066 6 unneback
   parameter length = 4;
2067
   input clear;
2068
   input set;
2069
   input cke;
2070
   input rew;
2071
   output [length:1] q;
2072
   input rst;
2073
   input clk;
2074
 
2075
   parameter clear_value = 0;
2076
   parameter set_value = 1;
2077
   parameter wrap_value = 0;
2078
   parameter level1_value = 15;
2079
 
2080
   reg  [length:1] qi;
2081
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2082
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2083
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2084
   assign q_next = rew ? q_next_rew : q_next_fw;
2085
 
2086
   always @ (posedge clk or posedge rst)
2087
     if (rst)
2088
       qi <= {length{1'b0}};
2089
     else
2090
     if (cke)
2091
       qi <= q_next;
2092
 
2093
   assign q = qi;
2094
 
2095
endmodule
2096 40 unneback
`endif
2097
`ifdef CNT_BIN_CE_REW_L1
2098 6 unneback
//////////////////////////////////////////////////////////////////////
2099
////                                                              ////
2100
////  Versatile counter                                           ////
2101
////                                                              ////
2102
////  Description                                                 ////
2103
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2104
////  counter                                                     ////
2105
////                                                              ////
2106
////  To Do:                                                      ////
2107
////   - add LFSR with more taps                                  ////
2108
////                                                              ////
2109
////  Author(s):                                                  ////
2110
////      - Michael Unneback, unneback@opencores.org              ////
2111
////        ORSoC AB                                              ////
2112
////                                                              ////
2113
//////////////////////////////////////////////////////////////////////
2114
////                                                              ////
2115
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2116
////                                                              ////
2117
//// This source file may be used and distributed without         ////
2118
//// restriction provided that this copyright statement is not    ////
2119
//// removed from the file and that any derivative work contains  ////
2120
//// the original copyright notice and the associated disclaimer. ////
2121
////                                                              ////
2122
//// This source file is free software; you can redistribute it   ////
2123
//// and/or modify it under the terms of the GNU Lesser General   ////
2124
//// Public License as published by the Free Software Foundation; ////
2125
//// either version 2.1 of the License, or (at your option) any   ////
2126
//// later version.                                               ////
2127
////                                                              ////
2128
//// This source is distributed in the hope that it will be       ////
2129
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2130
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2131
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2132
//// details.                                                     ////
2133
////                                                              ////
2134
//// You should have received a copy of the GNU Lesser General    ////
2135
//// Public License along with this source; if not, download it   ////
2136
//// from http://www.opencores.org/lgpl.shtml                     ////
2137
////                                                              ////
2138
//////////////////////////////////////////////////////////////////////
2139
 
2140
// binary counter
2141
 
2142 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2143
module `BASE`MODULE (
2144
`undef MODULE
2145
 cke, rew, level1, rst, clk);
2146
 
2147 6 unneback
   parameter length = 4;
2148
   input cke;
2149
   input rew;
2150
   output reg level1;
2151
   input rst;
2152
   input clk;
2153
 
2154
   parameter clear_value = 0;
2155
   parameter set_value = 1;
2156
   parameter wrap_value = 1;
2157
   parameter level1_value = 15;
2158
 
2159 29 unneback
   wire clear;
2160 30 unneback
   assign clear = 1'b0;
2161 6 unneback
   reg  [length:1] qi;
2162
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2163
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2164
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2165
   assign q_next = rew ? q_next_rew : q_next_fw;
2166
 
2167
   always @ (posedge clk or posedge rst)
2168
     if (rst)
2169
       qi <= {length{1'b0}};
2170
     else
2171
     if (cke)
2172
       qi <= q_next;
2173
 
2174
 
2175
 
2176
    always @ (posedge clk or posedge rst)
2177
    if (rst)
2178
        level1 <= 1'b0;
2179
    else
2180
    if (cke)
2181 29 unneback
    if (clear)
2182
        level1 <= 1'b0;
2183
    else if (q_next == level1_value)
2184 6 unneback
        level1 <= 1'b1;
2185
    else if (qi == level1_value & rew)
2186
        level1 <= 1'b0;
2187
endmodule
2188 40 unneback
`endif
2189
`ifdef CNT_BIN_CE_REW_ZQ_L1
2190 6 unneback
//////////////////////////////////////////////////////////////////////
2191
////                                                              ////
2192
////  Versatile counter                                           ////
2193
////                                                              ////
2194
////  Description                                                 ////
2195
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2196
////  counter                                                     ////
2197
////                                                              ////
2198
////  To Do:                                                      ////
2199
////   - add LFSR with more taps                                  ////
2200
////                                                              ////
2201
////  Author(s):                                                  ////
2202
////      - Michael Unneback, unneback@opencores.org              ////
2203
////        ORSoC AB                                              ////
2204
////                                                              ////
2205
//////////////////////////////////////////////////////////////////////
2206
////                                                              ////
2207
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2208
////                                                              ////
2209
//// This source file may be used and distributed without         ////
2210
//// restriction provided that this copyright statement is not    ////
2211
//// removed from the file and that any derivative work contains  ////
2212
//// the original copyright notice and the associated disclaimer. ////
2213
////                                                              ////
2214
//// This source file is free software; you can redistribute it   ////
2215
//// and/or modify it under the terms of the GNU Lesser General   ////
2216
//// Public License as published by the Free Software Foundation; ////
2217
//// either version 2.1 of the License, or (at your option) any   ////
2218
//// later version.                                               ////
2219
////                                                              ////
2220
//// This source is distributed in the hope that it will be       ////
2221
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2222
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2223
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2224
//// details.                                                     ////
2225
////                                                              ////
2226
//// You should have received a copy of the GNU Lesser General    ////
2227
//// Public License along with this source; if not, download it   ////
2228
//// from http://www.opencores.org/lgpl.shtml                     ////
2229
////                                                              ////
2230
//////////////////////////////////////////////////////////////////////
2231
 
2232 25 unneback
// binary counter
2233
 
2234 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2235
module `BASE`MODULE (
2236
`undef MODULE
2237
 cke, rew, zq, level1, rst, clk);
2238
 
2239 25 unneback
   parameter length = 4;
2240
   input cke;
2241
   input rew;
2242
   output reg zq;
2243
   output reg level1;
2244
   input rst;
2245
   input clk;
2246
 
2247
   parameter clear_value = 0;
2248
   parameter set_value = 1;
2249
   parameter wrap_value = 1;
2250
   parameter level1_value = 15;
2251
 
2252 29 unneback
   wire clear;
2253 30 unneback
   assign clear = 1'b0;
2254 25 unneback
   reg  [length:1] qi;
2255
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2256
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2257
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2258
   assign q_next = rew ? q_next_rew : q_next_fw;
2259
 
2260
   always @ (posedge clk or posedge rst)
2261
     if (rst)
2262
       qi <= {length{1'b0}};
2263
     else
2264
     if (cke)
2265
       qi <= q_next;
2266
 
2267
 
2268
 
2269
   always @ (posedge clk or posedge rst)
2270
     if (rst)
2271
       zq <= 1'b1;
2272
     else
2273
     if (cke)
2274
       zq <= q_next == {length{1'b0}};
2275
 
2276
    always @ (posedge clk or posedge rst)
2277
    if (rst)
2278
        level1 <= 1'b0;
2279
    else
2280
    if (cke)
2281 29 unneback
    if (clear)
2282
        level1 <= 1'b0;
2283
    else if (q_next == level1_value)
2284 25 unneback
        level1 <= 1'b1;
2285
    else if (qi == level1_value & rew)
2286
        level1 <= 1'b0;
2287
endmodule
2288 40 unneback
`endif
2289
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2290 25 unneback
//////////////////////////////////////////////////////////////////////
2291
////                                                              ////
2292
////  Versatile counter                                           ////
2293
////                                                              ////
2294
////  Description                                                 ////
2295
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2296
////  counter                                                     ////
2297
////                                                              ////
2298
////  To Do:                                                      ////
2299
////   - add LFSR with more taps                                  ////
2300
////                                                              ////
2301
////  Author(s):                                                  ////
2302
////      - Michael Unneback, unneback@opencores.org              ////
2303
////        ORSoC AB                                              ////
2304
////                                                              ////
2305
//////////////////////////////////////////////////////////////////////
2306
////                                                              ////
2307
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2308
////                                                              ////
2309
//// This source file may be used and distributed without         ////
2310
//// restriction provided that this copyright statement is not    ////
2311
//// removed from the file and that any derivative work contains  ////
2312
//// the original copyright notice and the associated disclaimer. ////
2313
////                                                              ////
2314
//// This source file is free software; you can redistribute it   ////
2315
//// and/or modify it under the terms of the GNU Lesser General   ////
2316
//// Public License as published by the Free Software Foundation; ////
2317
//// either version 2.1 of the License, or (at your option) any   ////
2318
//// later version.                                               ////
2319
////                                                              ////
2320
//// This source is distributed in the hope that it will be       ////
2321
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2322
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2323
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2324
//// details.                                                     ////
2325
////                                                              ////
2326
//// You should have received a copy of the GNU Lesser General    ////
2327
//// Public License along with this source; if not, download it   ////
2328
//// from http://www.opencores.org/lgpl.shtml                     ////
2329
////                                                              ////
2330
//////////////////////////////////////////////////////////////////////
2331
 
2332
// binary counter
2333
 
2334 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2335
module `BASE`MODULE (
2336
`undef MODULE
2337
 cke, rew, q, zq, level1, rst, clk);
2338
 
2339 25 unneback
   parameter length = 4;
2340
   input cke;
2341
   input rew;
2342
   output [length:1] q;
2343
   output reg zq;
2344
   output reg level1;
2345
   input rst;
2346
   input clk;
2347
 
2348
   parameter clear_value = 0;
2349
   parameter set_value = 1;
2350
   parameter wrap_value = 1;
2351
   parameter level1_value = 15;
2352
 
2353 29 unneback
   wire clear;
2354 30 unneback
   assign clear = 1'b0;
2355 25 unneback
   reg  [length:1] qi;
2356
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2357
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2358
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2359
   assign q_next = rew ? q_next_rew : q_next_fw;
2360
 
2361
   always @ (posedge clk or posedge rst)
2362
     if (rst)
2363
       qi <= {length{1'b0}};
2364
     else
2365
     if (cke)
2366
       qi <= q_next;
2367
 
2368
   assign q = qi;
2369
 
2370
 
2371
   always @ (posedge clk or posedge rst)
2372
     if (rst)
2373
       zq <= 1'b1;
2374
     else
2375
     if (cke)
2376
       zq <= q_next == {length{1'b0}};
2377
 
2378
    always @ (posedge clk or posedge rst)
2379
    if (rst)
2380
        level1 <= 1'b0;
2381
    else
2382
    if (cke)
2383 29 unneback
    if (clear)
2384
        level1 <= 1'b0;
2385
    else if (q_next == level1_value)
2386 25 unneback
        level1 <= 1'b1;
2387
    else if (qi == level1_value & rew)
2388
        level1 <= 1'b0;
2389
endmodule
2390 40 unneback
`endif
2391
`ifdef CNT_LFSR_ZQ
2392 25 unneback
//////////////////////////////////////////////////////////////////////
2393
////                                                              ////
2394
////  Versatile counter                                           ////
2395
////                                                              ////
2396
////  Description                                                 ////
2397
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2398
////  counter                                                     ////
2399
////                                                              ////
2400
////  To Do:                                                      ////
2401
////   - add LFSR with more taps                                  ////
2402
////                                                              ////
2403
////  Author(s):                                                  ////
2404
////      - Michael Unneback, unneback@opencores.org              ////
2405
////        ORSoC AB                                              ////
2406
////                                                              ////
2407
//////////////////////////////////////////////////////////////////////
2408
////                                                              ////
2409
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2410
////                                                              ////
2411
//// This source file may be used and distributed without         ////
2412
//// restriction provided that this copyright statement is not    ////
2413
//// removed from the file and that any derivative work contains  ////
2414
//// the original copyright notice and the associated disclaimer. ////
2415
////                                                              ////
2416
//// This source file is free software; you can redistribute it   ////
2417
//// and/or modify it under the terms of the GNU Lesser General   ////
2418
//// Public License as published by the Free Software Foundation; ////
2419
//// either version 2.1 of the License, or (at your option) any   ////
2420
//// later version.                                               ////
2421
////                                                              ////
2422
//// This source is distributed in the hope that it will be       ////
2423
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2424
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2425
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2426
//// details.                                                     ////
2427
////                                                              ////
2428
//// You should have received a copy of the GNU Lesser General    ////
2429
//// Public License along with this source; if not, download it   ////
2430
//// from http://www.opencores.org/lgpl.shtml                     ////
2431
////                                                              ////
2432
//////////////////////////////////////////////////////////////////////
2433
 
2434 6 unneback
// LFSR counter
2435
 
2436 40 unneback
`define MODULE cnt_lfsr_zq
2437
module `BASE`MODULE (
2438
`undef MODULE
2439
 zq, rst, clk);
2440
 
2441 6 unneback
   parameter length = 4;
2442
   output reg zq;
2443
   input rst;
2444
   input clk;
2445
 
2446
   parameter clear_value = 0;
2447
   parameter set_value = 1;
2448
   parameter wrap_value = 8;
2449
   parameter level1_value = 15;
2450
 
2451
   reg  [length:1] qi;
2452
   reg lfsr_fb;
2453
   wire [length:1] q_next;
2454
   reg [32:1] polynom;
2455
   integer i;
2456
 
2457
   always @ (qi)
2458
   begin
2459
        case (length)
2460
         2: polynom = 32'b11;                               // 0x3
2461
         3: polynom = 32'b110;                              // 0x6
2462
         4: polynom = 32'b1100;                             // 0xC
2463
         5: polynom = 32'b10100;                            // 0x14
2464
         6: polynom = 32'b110000;                           // 0x30
2465
         7: polynom = 32'b1100000;                          // 0x60
2466
         8: polynom = 32'b10111000;                         // 0xb8
2467
         9: polynom = 32'b100010000;                        // 0x110
2468
        10: polynom = 32'b1001000000;                       // 0x240
2469
        11: polynom = 32'b10100000000;                      // 0x500
2470
        12: polynom = 32'b100000101001;                     // 0x829
2471
        13: polynom = 32'b1000000001100;                    // 0x100C
2472
        14: polynom = 32'b10000000010101;                   // 0x2015
2473
        15: polynom = 32'b110000000000000;                  // 0x6000
2474
        16: polynom = 32'b1101000000001000;                 // 0xD008
2475
        17: polynom = 32'b10010000000000000;                // 0x12000
2476
        18: polynom = 32'b100000010000000000;               // 0x20400
2477
        19: polynom = 32'b1000000000000100011;              // 0x40023
2478 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2479 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2480
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2481
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2482
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2483
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2484
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2485
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2486
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2487
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2488
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2489
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2490
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2491
        default: polynom = 32'b0;
2492
        endcase
2493
        lfsr_fb = qi[length];
2494
        for (i=length-1; i>=1; i=i-1) begin
2495
            if (polynom[i])
2496
                lfsr_fb = lfsr_fb  ~^ qi[i];
2497
        end
2498
    end
2499
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2500
 
2501
   always @ (posedge clk or posedge rst)
2502
     if (rst)
2503
       qi <= {length{1'b0}};
2504
     else
2505
       qi <= q_next;
2506
 
2507
 
2508
 
2509
   always @ (posedge clk or posedge rst)
2510
     if (rst)
2511
       zq <= 1'b1;
2512
     else
2513
       zq <= q_next == {length{1'b0}};
2514
endmodule
2515 40 unneback
`endif
2516 75 unneback
`ifdef CNT_LFSR_CE
2517
//////////////////////////////////////////////////////////////////////
2518
////                                                              ////
2519
////  Versatile counter                                           ////
2520
////                                                              ////
2521
////  Description                                                 ////
2522
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2523
////  counter                                                     ////
2524
////                                                              ////
2525
////  To Do:                                                      ////
2526
////   - add LFSR with more taps                                  ////
2527
////                                                              ////
2528
////  Author(s):                                                  ////
2529
////      - Michael Unneback, unneback@opencores.org              ////
2530
////        ORSoC AB                                              ////
2531
////                                                              ////
2532
//////////////////////////////////////////////////////////////////////
2533
////                                                              ////
2534
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2535
////                                                              ////
2536
//// This source file may be used and distributed without         ////
2537
//// restriction provided that this copyright statement is not    ////
2538
//// removed from the file and that any derivative work contains  ////
2539
//// the original copyright notice and the associated disclaimer. ////
2540
////                                                              ////
2541
//// This source file is free software; you can redistribute it   ////
2542
//// and/or modify it under the terms of the GNU Lesser General   ////
2543
//// Public License as published by the Free Software Foundation; ////
2544
//// either version 2.1 of the License, or (at your option) any   ////
2545
//// later version.                                               ////
2546
////                                                              ////
2547
//// This source is distributed in the hope that it will be       ////
2548
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2549
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2550
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2551
//// details.                                                     ////
2552
////                                                              ////
2553
//// You should have received a copy of the GNU Lesser General    ////
2554
//// Public License along with this source; if not, download it   ////
2555
//// from http://www.opencores.org/lgpl.shtml                     ////
2556
////                                                              ////
2557
//////////////////////////////////////////////////////////////////////
2558
 
2559
// LFSR counter
2560
 
2561
`define MODULE cnt_lfsr_ce
2562
module `BASE`MODULE (
2563
`undef MODULE
2564
 cke, zq, rst, clk);
2565
 
2566
   parameter length = 4;
2567
   input cke;
2568
   output reg zq;
2569
   input rst;
2570
   input clk;
2571
 
2572
   parameter clear_value = 0;
2573
   parameter set_value = 1;
2574
   parameter wrap_value = 0;
2575
   parameter level1_value = 15;
2576
 
2577
   reg  [length:1] qi;
2578
   reg lfsr_fb;
2579
   wire [length:1] q_next;
2580
   reg [32:1] polynom;
2581
   integer i;
2582
 
2583
   always @ (qi)
2584
   begin
2585
        case (length)
2586
         2: polynom = 32'b11;                               // 0x3
2587
         3: polynom = 32'b110;                              // 0x6
2588
         4: polynom = 32'b1100;                             // 0xC
2589
         5: polynom = 32'b10100;                            // 0x14
2590
         6: polynom = 32'b110000;                           // 0x30
2591
         7: polynom = 32'b1100000;                          // 0x60
2592
         8: polynom = 32'b10111000;                         // 0xb8
2593
         9: polynom = 32'b100010000;                        // 0x110
2594
        10: polynom = 32'b1001000000;                       // 0x240
2595
        11: polynom = 32'b10100000000;                      // 0x500
2596
        12: polynom = 32'b100000101001;                     // 0x829
2597
        13: polynom = 32'b1000000001100;                    // 0x100C
2598
        14: polynom = 32'b10000000010101;                   // 0x2015
2599
        15: polynom = 32'b110000000000000;                  // 0x6000
2600
        16: polynom = 32'b1101000000001000;                 // 0xD008
2601
        17: polynom = 32'b10010000000000000;                // 0x12000
2602
        18: polynom = 32'b100000010000000000;               // 0x20400
2603
        19: polynom = 32'b1000000000000100011;              // 0x40023
2604
        20: polynom = 32'b10010000000000000000;             // 0x90000
2605
        21: polynom = 32'b101000000000000000000;            // 0x140000
2606
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2607
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2608
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2609
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2610
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2611
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2612
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2613
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2614
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2615
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2616
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2617
        default: polynom = 32'b0;
2618
        endcase
2619
        lfsr_fb = qi[length];
2620
        for (i=length-1; i>=1; i=i-1) begin
2621
            if (polynom[i])
2622
                lfsr_fb = lfsr_fb  ~^ qi[i];
2623
        end
2624
    end
2625
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2626
 
2627
   always @ (posedge clk or posedge rst)
2628
     if (rst)
2629
       qi <= {length{1'b0}};
2630
     else
2631
     if (cke)
2632
       qi <= q_next;
2633
 
2634
 
2635
 
2636
   always @ (posedge clk or posedge rst)
2637
     if (rst)
2638
       zq <= 1'b1;
2639
     else
2640
     if (cke)
2641
       zq <= q_next == {length{1'b0}};
2642
endmodule
2643
`endif
2644 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2645 6 unneback
//////////////////////////////////////////////////////////////////////
2646
////                                                              ////
2647
////  Versatile counter                                           ////
2648
////                                                              ////
2649
////  Description                                                 ////
2650
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2651
////  counter                                                     ////
2652
////                                                              ////
2653
////  To Do:                                                      ////
2654
////   - add LFSR with more taps                                  ////
2655
////                                                              ////
2656
////  Author(s):                                                  ////
2657
////      - Michael Unneback, unneback@opencores.org              ////
2658
////        ORSoC AB                                              ////
2659
////                                                              ////
2660
//////////////////////////////////////////////////////////////////////
2661
////                                                              ////
2662
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2663
////                                                              ////
2664
//// This source file may be used and distributed without         ////
2665
//// restriction provided that this copyright statement is not    ////
2666
//// removed from the file and that any derivative work contains  ////
2667
//// the original copyright notice and the associated disclaimer. ////
2668
////                                                              ////
2669
//// This source file is free software; you can redistribute it   ////
2670
//// and/or modify it under the terms of the GNU Lesser General   ////
2671
//// Public License as published by the Free Software Foundation; ////
2672
//// either version 2.1 of the License, or (at your option) any   ////
2673
//// later version.                                               ////
2674
////                                                              ////
2675
//// This source is distributed in the hope that it will be       ////
2676
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2677
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2678
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2679
//// details.                                                     ////
2680
////                                                              ////
2681
//// You should have received a copy of the GNU Lesser General    ////
2682
//// Public License along with this source; if not, download it   ////
2683
//// from http://www.opencores.org/lgpl.shtml                     ////
2684
////                                                              ////
2685
//////////////////////////////////////////////////////////////////////
2686
 
2687
// LFSR counter
2688
 
2689 40 unneback
`define MODULE cnt_lfsr_ce_zq
2690
module `BASE`MODULE (
2691
`undef MODULE
2692
 cke, zq, rst, clk);
2693
 
2694 6 unneback
   parameter length = 4;
2695
   input cke;
2696
   output reg zq;
2697
   input rst;
2698
   input clk;
2699
 
2700
   parameter clear_value = 0;
2701
   parameter set_value = 1;
2702
   parameter wrap_value = 8;
2703
   parameter level1_value = 15;
2704
 
2705
   reg  [length:1] qi;
2706
   reg lfsr_fb;
2707
   wire [length:1] q_next;
2708
   reg [32:1] polynom;
2709
   integer i;
2710
 
2711
   always @ (qi)
2712
   begin
2713
        case (length)
2714
         2: polynom = 32'b11;                               // 0x3
2715
         3: polynom = 32'b110;                              // 0x6
2716
         4: polynom = 32'b1100;                             // 0xC
2717
         5: polynom = 32'b10100;                            // 0x14
2718
         6: polynom = 32'b110000;                           // 0x30
2719
         7: polynom = 32'b1100000;                          // 0x60
2720
         8: polynom = 32'b10111000;                         // 0xb8
2721
         9: polynom = 32'b100010000;                        // 0x110
2722
        10: polynom = 32'b1001000000;                       // 0x240
2723
        11: polynom = 32'b10100000000;                      // 0x500
2724
        12: polynom = 32'b100000101001;                     // 0x829
2725
        13: polynom = 32'b1000000001100;                    // 0x100C
2726
        14: polynom = 32'b10000000010101;                   // 0x2015
2727
        15: polynom = 32'b110000000000000;                  // 0x6000
2728
        16: polynom = 32'b1101000000001000;                 // 0xD008
2729
        17: polynom = 32'b10010000000000000;                // 0x12000
2730
        18: polynom = 32'b100000010000000000;               // 0x20400
2731
        19: polynom = 32'b1000000000000100011;              // 0x40023
2732 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2733 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2734
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2735
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2736
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2737
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2738
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2739
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2740
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2741
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2742
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2743
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2744
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2745
        default: polynom = 32'b0;
2746
        endcase
2747
        lfsr_fb = qi[length];
2748
        for (i=length-1; i>=1; i=i-1) begin
2749
            if (polynom[i])
2750
                lfsr_fb = lfsr_fb  ~^ qi[i];
2751
        end
2752
    end
2753
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2754
 
2755
   always @ (posedge clk or posedge rst)
2756
     if (rst)
2757
       qi <= {length{1'b0}};
2758
     else
2759
     if (cke)
2760
       qi <= q_next;
2761
 
2762
 
2763
 
2764
   always @ (posedge clk or posedge rst)
2765
     if (rst)
2766
       zq <= 1'b1;
2767
     else
2768
     if (cke)
2769
       zq <= q_next == {length{1'b0}};
2770
endmodule
2771 40 unneback
`endif
2772
`ifdef CNT_LFSR_CE_Q
2773 6 unneback
//////////////////////////////////////////////////////////////////////
2774
////                                                              ////
2775
////  Versatile counter                                           ////
2776
////                                                              ////
2777
////  Description                                                 ////
2778
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2779
////  counter                                                     ////
2780
////                                                              ////
2781
////  To Do:                                                      ////
2782
////   - add LFSR with more taps                                  ////
2783
////                                                              ////
2784
////  Author(s):                                                  ////
2785
////      - Michael Unneback, unneback@opencores.org              ////
2786
////        ORSoC AB                                              ////
2787
////                                                              ////
2788
//////////////////////////////////////////////////////////////////////
2789
////                                                              ////
2790
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2791
////                                                              ////
2792
//// This source file may be used and distributed without         ////
2793
//// restriction provided that this copyright statement is not    ////
2794
//// removed from the file and that any derivative work contains  ////
2795
//// the original copyright notice and the associated disclaimer. ////
2796
////                                                              ////
2797
//// This source file is free software; you can redistribute it   ////
2798
//// and/or modify it under the terms of the GNU Lesser General   ////
2799
//// Public License as published by the Free Software Foundation; ////
2800
//// either version 2.1 of the License, or (at your option) any   ////
2801
//// later version.                                               ////
2802
////                                                              ////
2803
//// This source is distributed in the hope that it will be       ////
2804
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2805
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2806
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2807
//// details.                                                     ////
2808
////                                                              ////
2809
//// You should have received a copy of the GNU Lesser General    ////
2810
//// Public License along with this source; if not, download it   ////
2811
//// from http://www.opencores.org/lgpl.shtml                     ////
2812
////                                                              ////
2813
//////////////////////////////////////////////////////////////////////
2814 22 unneback
 
2815
// LFSR counter
2816 27 unneback
 
2817 40 unneback
`define MODULE cnt_lfsr_ce_q
2818
module `BASE`MODULE (
2819
`undef MODULE
2820
 cke, q, rst, clk);
2821
 
2822 27 unneback
   parameter length = 4;
2823
   input cke;
2824
   output [length:1] q;
2825
   input rst;
2826
   input clk;
2827
 
2828
   parameter clear_value = 0;
2829
   parameter set_value = 1;
2830
   parameter wrap_value = 8;
2831
   parameter level1_value = 15;
2832
 
2833
   reg  [length:1] qi;
2834
   reg lfsr_fb;
2835
   wire [length:1] q_next;
2836
   reg [32:1] polynom;
2837
   integer i;
2838
 
2839