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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 97

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 40 unneback 
`ifdef ALL
14 
 
15 
`define GBUF
16 
`define SYNC_RST
17 
`define PLL
18 
 
19 
`define MULTS
20 
`define MULTS18X18
21 
`define MULT
22 
`define SHIFT_UNIT_32
23 
`define LOGIC_UNIT
24 
 
25 
`define CNT_SHREG_WRAP
26 
`define CNT_SHREG_CE_WRAP
27 
`define CNT_SHREG_CE_CLEAR
28 
`define CNT_SHREG_CE_CLEAR_WRAP
29 
 
30 
`define MUX_ANDOR
31 
`define MUX2_ANDOR
32 
`define MUX3_ANDOR
33 
`define MUX4_ANDOR
34 
`define MUX5_ANDOR
35 
`define MUX6_ANDOR
36 43 unneback 
`define PARITY
37 40 unneback 
 
38 
`define ROM_INIT
39 
`define RAM
40 
`define RAM_BE
41 
`define DPRAM_1R1W
42 
`define DPRAM_2R1W
43 
`define DPRAM_2R2W
44 75 unneback 
`define DPRAM_BE_2R2W
45 40 unneback 
`define FIFO_1R1W_FILL_LEVEL_SYNC
46 
`define FIFO_2R2W_SYNC_SIMPLEX
47 
`define FIFO_CMP_ASYNC
48 
`define FIFO_1R1W_ASYNC
49 
`define FIFO_2R2W_ASYNC
50 
`define FIFO_2R2W_ASYNC_SIMPLEX
51 48 unneback 
`define REG_FILE
52 40 unneback 
 
53 
`define DFF
54 
`define DFF_ARRAY
55 
`define DFF_CE
56 
`define DFF_CE_CLEAR
57 
`define DF_CE_SET
58 
`define SPR
59 
`define SRP
60 
`define DFF_SR
61 
`define LATCH
62 
`define SHREG
63 
`define SHREG_CE
64 
`define DELAY
65 
`define DELAY_EMPTYFLAG
66 94 unneback 
`define PULSE2TOGGLE
67 
`define TOGGLE2PULSE
68 
`define SYNCHRONIZER
69 
`define CDC
70 40 unneback 
 
71 75 unneback 
`define WB3AVALON_BRIDGE
72 40 unneback 
`define WB3WB3_BRIDGE
73 
`define WB3_ARBITER_TYPE1
74 83 unneback 
`define WB_ADR_INC
75 59 unneback 
`define WB_B3_RAM_BE
76 49 unneback 
`define WB_B4_RAM_BE
77 48 unneback 
`define WB_B4_ROM
78 40 unneback 
`define WB_BOOT_ROM
79 
`define WB_DPRAM
80 97 unneback 
`define WBB3_WBB4_CACHE
81 40 unneback 
 
82 44 unneback 
`define IO_DFF_OE
83 
`define O_DFF
84 
 
85 40 unneback 
`endif
86 
 
87 
`ifdef PLL
88 
`ifndef SYNC_RST
89 
`define SYNC_RST
90 
`endif
91 
`endif
92 
 
93 
`ifdef SYNC_RST
94 
`ifndef GBUF
95 
`define GBUF
96 
`endif
97 
`endif
98 
 
99 94 unneback 
`ifdef CDC
100 
`ifndef PULSE2TOGGLE
101 
`define PULSE2TOGGLE
102 
`endif
103 
`ifndef TOGGLE2PULSE
104 
`define TOGGLE2PULSE
105 
`endif
106 
`ifndef SYNCHRONIZER
107 
`define SYNCHRONIZER
108 
`endif
109 
`endif
110 
 
111 92 unneback 
`ifdef WB_B3_DPRAM
112 
`ifndef WB_ADR_INC
113 
`define WB_ADR_INC
114 40 unneback 
`endif
115 92 unneback 
`ifndef DPRAM_BE_2R2W
116 
`define DPRAM_BE_2R2W
117 40 unneback 
`endif
118 
`endif
119 
 
120 62 unneback 
`ifdef WB_B3_RAM_BE
121 83 unneback 
`ifndef WB_ADR_INC
122 
`define WB_ADR_INC
123 62 unneback 
`endif
124 
`ifndef RAM_BE
125 
`define RAM_BE
126 
`endif
127 
`endif
128 
 
129 40 unneback 
`ifdef WB3_ARBITER_TYPE1
130 42 unneback 
`ifndef SPR
131 
`define SPR
132 
`endif
133 40 unneback 
`ifndef MUX_ANDOR
134 
`define MUX_ANDOR
135 
`endif
136 
`endif
137 
 
138 76 unneback 
`ifdef WB3AVALON_BRIDGE
139 
`ifndef WB3WB3_BRIDGE
140 
`define WB3WB3_BRIDGE
141 
`endif
142 
`endif
143 
 
144 40 unneback 
`ifdef WB3WB3_BRIDGE
145 
`ifndef CNT_SHREG_CE_CLEAR
146 
`define CNT_SHREG_CE_CLEAR
147 
`endif
148 
`ifndef DFF
149 
`define DFF
150 
`endif
151 
`ifndef DFF_CE
152 
`define DFF_CE
153 
`endif
154 
`ifndef CNT_SHREG_CE_CLEAR
155 
`define CNT_SHREG_CE_CLEAR
156 
`endif
157 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
158 
`define FIFO_2R2W_ASYNC_SIMPLEX
159 
`endif
160 
`endif
161 
 
162 97 unneback 
 `ifdef WBB3_WBB4_CACHE
163 
 `ifndef RAM
164 
 `define RAM
165 
 `endif
166 
 `ifndef WB_ADR_INC
167 
 `define WB_ADR_INC
168 
 `endif
169 
 `ifndef dpram_be_2r2w
170 
 `define DPRAM_BE_2R2W
171 
 `endif
172 
 `endif
173 
 
174 40 unneback 
`ifdef MULTS18X18
175 
`ifndef MULTS
176 
`define MULTS
177 
`endif
178 
`endif
179 
 
180 
`ifdef SHIFT_UNIT_32
181 
`ifndef MULTS
182 
`define MULTS
183 
`endif
184 
`endif
185 
 
186 
`ifdef MUX2_ANDOR
187 
`ifndef MUX_ANDOR
188 
`define MUX_ANDOR
189 
`endif
190 
`endif
191 
 
192 
`ifdef MUX3_ANDOR
193 
`ifndef MUX_ANDOR
194 
`define MUX_ANDOR
195 
`endif
196 
`endif
197 
 
198 
`ifdef MUX4_ANDOR
199 
`ifndef MUX_ANDOR
200 
`define MUX_ANDOR
201 
`endif
202 
`endif
203 
 
204 
`ifdef MUX5_ANDOR
205 
`ifndef MUX_ANDOR
206 
`define MUX_ANDOR
207 
`endif
208 
`endif
209 
 
210 
`ifdef MUX6_ANDOR
211 
`ifndef MUX_ANDOR
212 
`define MUX_ANDOR
213 
`endif
214 
`endif
215 
 
216 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
217 
`ifndef CNT_BIN_CE
218 
`define CNT_BIN_CE
219 
`endif
220 
`ifndef DPRAM_1R1W
221 
`define DPRAM_1R1W
222 
`endif
223 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
224 
`define CNT_BIN_CE_REW_Q_ZQ_L1
225 
`endif
226 
`endif
227 
 
228 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
229 
`ifndef CNT_LFSR_CE
230 
`define CNT_LFSR_CE
231 
`endif
232 
`ifndef DPRAM_2R2W
233 
`define DPRAM_2R2W
234 
`endif
235 
`ifndef CNT_BIN_CE_REW_ZQ_L1
236 
`define CNT_BIN_CE_REW_ZQ_L1
237 
`endif
238 
`endif
239 
 
240 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
241 
`ifndef CNT_GRAY_CE_BIN
242 
`define CNT_GRAY_CE_BIN
243 
`endif
244 
`ifndef DPRAM_2R2W
245 
`define DPRAM_2R2W
246 
`endif
247 
`ifndef FIFO_CMP_ASYNC
248 
`define FIFO_CMP_ASYNC
249 
`endif
250 
`endif
251 
 
252 
`ifdef FIFO_2R2W_ASYNC
253 
`ifndef FIFO_1R1W_ASYNC
254 
`define FIFO_1R1W_ASYNC
255 
`endif
256 
`endif
257 
 
258 
`ifdef FIFO_1R1W_ASYNC
259 
`ifndef CNT_GRAY_CE_BIN
260 
`define CNT_GRAY_CE_BIN
261 
`endif
262 
`ifndef DPRAM_1R1W
263 
`define DPRAM_1R1W
264 
`endif
265 
`ifndef FIFO_CMP_ASYNC
266 
`define FIFO_CMP_ASYNC
267 
`endif
268 
`endif
269 
 
270 
`ifdef FIFO_CMP_ASYNC
271 
`ifndef DFF_SR
272 
`define DFF_SR
273 
`endif
274 
`ifndef DFF
275 
`define DFF
276 
`endif
277 
`endif
278 48 unneback 
 
279 
`ifdef REG_FILE
280 
`ifndef DPRAM_1R1W
281 
`define DPRAM_1R1W
282 
`endif
283 
`endif
284 97 unneback 
 
285 
// size to width
286 
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
287 62 unneback 
//////////////////////////////////////////////////////////////////////
288 6 unneback 
////                                                              ////
289 
////  Versatile library, clock and reset                          ////
290 
////                                                              ////
291 
////  Description                                                 ////
292 
////  Logic related to clock and reset                            ////
293 
////                                                              ////
294 
////                                                              ////
295 
////  To Do:                                                      ////
296 
////   - add more different registers                             ////
297 
////                                                              ////
298 
////  Author(s):                                                  ////
299 
////      - Michael Unneback, unneback@opencores.org              ////
300 
////        ORSoC AB                                              ////
301 
////                                                              ////
302 
//////////////////////////////////////////////////////////////////////
303 
////                                                              ////
304 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
305 
////                                                              ////
306 
//// This source file may be used and distributed without         ////
307 
//// restriction provided that this copyright statement is not    ////
308 
//// removed from the file and that any derivative work contains  ////
309 
//// the original copyright notice and the associated disclaimer. ////
310 
////                                                              ////
311 
//// This source file is free software; you can redistribute it   ////
312 
//// and/or modify it under the terms of the GNU Lesser General   ////
313 
//// Public License as published by the Free Software Foundation; ////
314 
//// either version 2.1 of the License, or (at your option) any   ////
315 
//// later version.                                               ////
316 
////                                                              ////
317 
//// This source is distributed in the hope that it will be       ////
318 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
319 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
320 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
321 
//// details.                                                     ////
322 
////                                                              ////
323 
//// You should have received a copy of the GNU Lesser General    ////
324 
//// Public License along with this source; if not, download it   ////
325 
//// from http://www.opencores.org/lgpl.shtml                     ////
326 
////                                                              ////
327 
//////////////////////////////////////////////////////////////////////
328 
 
329 48 unneback 
`ifdef ACTEL
330 
`ifdef GBUF
331 
`timescale 1 ns/100 ps
332 6 unneback 
// Global buffer
333 
// usage:
334 
// use to enable global buffers for high fan out signals such as clock and reset
335 
// Version: 8.4 8.4.0.33
336 
module gbuf(GL,CLK);
337 
output GL;
338 
input  CLK;
339 
 
340 
    wire GND;
341 
 
342 
    GND GND_1_net(.Y(GND));
343 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
344 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
345 
 
346 
endmodule
347 
`timescale 1 ns/1 ns
348 40 unneback 
`define MODULE gbuf
349 
module `BASE`MODULE ( i, o);
350 
`undef MODULE
351 6 unneback 
input i;
352 
output o;
353 
`ifdef SIM_GBUF
354 
assign o=i;
355 
`else
356 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
357 
`endif
358 
endmodule
359 40 unneback 
`endif
360 33 unneback 
 
361 6 unneback 
`else
362 33 unneback 
 
363 40 unneback 
`ifdef ALTERA
364 
`ifdef GBUF
365 21 unneback 
//altera
366 40 unneback 
`define MODULE gbuf
367 
module `BASE`MODULE ( i, o);
368 
`undef MODULE
369 33 unneback 
input i;
370 
output o;
371 
assign o = i;
372 
endmodule
373 40 unneback 
`endif
374 33 unneback 
 
375 6 unneback 
`else
376 
 
377 40 unneback 
`ifdef GBUF
378 6 unneback 
`timescale 1 ns/100 ps
379 40 unneback 
`define MODULE
380 
module `BASE`MODULE ( i, o);
381 
`undef MODULE
382 6 unneback 
input i;
383 
output o;
384 
assign o = i;
385 
endmodule
386 40 unneback 
`endif
387 6 unneback 
`endif // ALTERA
388 
`endif //ACTEL
389 
 
390 40 unneback 
`ifdef SYNC_RST
391 6 unneback 
// sync reset
392 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
393 6 unneback 
// output active high global reset sync with two DFFs
394 
`timescale 1 ns/100 ps
395 40 unneback 
`define MODULE sync_rst
396 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
397 
`undef MODULE
398 6 unneback 
input rst_n_i, clk;
399 
output rst_o;
400 18 unneback 
reg [1:0] tmp;
401 6 unneback 
always @ (posedge clk or negedge rst_n_i)
402 
if (!rst_n_i)
403 17 unneback 
        tmp <= 2'b11;
404 6 unneback 
else
405 33 unneback 
        tmp <= {1'b0,tmp[1]};
406 40 unneback 
`define MODULE gbuf
407 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
408 
`undef MODULE
409 6 unneback 
endmodule
410 40 unneback 
`endif
411 6 unneback 
 
412 40 unneback 
`ifdef PLL
413 6 unneback 
// vl_pll
414 
`ifdef ACTEL
415 32 unneback 
///////////////////////////////////////////////////////////////////////////////
416 17 unneback 
`timescale 1 ps/1 ps
417 40 unneback 
`define MODULE pll
418 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
419 
`undef MODULE
420 6 unneback 
parameter index = 0;
421 
parameter number_of_clk = 1;
422 17 unneback 
parameter period_time_0 = 20000;
423 
parameter period_time_1 = 20000;
424 
parameter period_time_2 = 20000;
425 
parameter lock_delay = 2000000;
426 6 unneback 
input clk_i, rst_n_i;
427 
output lock;
428 
output reg [0:number_of_clk-1] clk_o;
429 
output [0:number_of_clk-1] rst_o;
430 
 
431 
`ifdef SIM_PLL
432 
 
433 
always
434 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
435 
 
436 
generate if (number_of_clk > 1)
437 
always
438 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
439 
endgenerate
440 
 
441 
generate if (number_of_clk > 2)
442 
always
443 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
444 
endgenerate
445 
 
446 
genvar i;
447 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
448 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
449 
end
450 
endgenerate
451 
 
452 
assign #lock_delay lock = rst_n_i;
453 
 
454 
endmodule
455 
`else
456 
generate if (number_of_clk==1 & index==0) begin
457 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
458 
end
459 
endgenerate // index==0
460 
generate if (number_of_clk==1 & index==1) begin
461 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
462 
end
463 
endgenerate // index==1
464 
generate if (number_of_clk==1 & index==2) begin
465 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
466 
end
467 
endgenerate // index==2
468 
generate if (number_of_clk==1 & index==3) begin
469 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
470 
end
471 
endgenerate // index==0
472 
 
473 
generate if (number_of_clk==2 & index==0) begin
474 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
475 
end
476 
endgenerate // index==0
477 
generate if (number_of_clk==2 & index==1) begin
478 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
479 
end
480 
endgenerate // index==1
481 
generate if (number_of_clk==2 & index==2) begin
482 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
483 
end
484 
endgenerate // index==2
485 
generate if (number_of_clk==2 & index==3) begin
486 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
487 
end
488 
endgenerate // index==0
489 
 
490 
generate if (number_of_clk==3 & index==0) begin
491 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
492 
end
493 
endgenerate // index==0
494 
generate if (number_of_clk==3 & index==1) begin
495 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
496 
end
497 
endgenerate // index==1
498 
generate if (number_of_clk==3 & index==2) begin
499 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
500 
end
501 
endgenerate // index==2
502 
generate if (number_of_clk==3 & index==3) begin
503 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
504 
end
505 
endgenerate // index==0
506 
 
507 
genvar i;
508 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
509 40 unneback 
`define MODULE sync_rst
510 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
511 
`undef MODULE
512 6 unneback 
end
513 
endgenerate
514 
endmodule
515 
`endif
516 32 unneback 
///////////////////////////////////////////////////////////////////////////////
517 6 unneback 
 
518 
`else
519 
 
520 32 unneback 
///////////////////////////////////////////////////////////////////////////////
521 6 unneback 
`ifdef ALTERA
522 
 
523 32 unneback 
`timescale 1 ps/1 ps
524 40 unneback 
`define MODULE pll
525 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
526 
`undef MODULE
527 32 unneback 
parameter index = 0;
528 
parameter number_of_clk = 1;
529 
parameter period_time_0 = 20000;
530 
parameter period_time_1 = 20000;
531 
parameter period_time_2 = 20000;
532 
parameter period_time_3 = 20000;
533 
parameter period_time_4 = 20000;
534 
parameter lock_delay = 2000000;
535 
input clk_i, rst_n_i;
536 
output lock;
537 
output reg [0:number_of_clk-1] clk_o;
538 
output [0:number_of_clk-1] rst_o;
539 
 
540 
`ifdef SIM_PLL
541 
 
542 
always
543 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
544 
 
545 
generate if (number_of_clk > 1)
546 
always
547 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
548 
endgenerate
549 
 
550 
generate if (number_of_clk > 2)
551 
always
552 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
553 
endgenerate
554 
 
555 33 unneback 
generate if (number_of_clk > 3)
556 32 unneback 
always
557 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
558 
endgenerate
559 
 
560 33 unneback 
generate if (number_of_clk > 4)
561 32 unneback 
always
562 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
563 
endgenerate
564 
 
565 
genvar i;
566 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
567 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
568 
end
569 
endgenerate
570 
 
571 33 unneback 
//assign #lock_delay lock = rst_n_i;
572 
assign lock = rst_n_i;
573 32 unneback 
 
574 
endmodule
575 6 unneback 
`else
576 
 
577 33 unneback 
`ifdef VL_PLL0
578 
`ifdef VL_PLL0_CLK1
579 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
580 
`endif
581 
`ifdef VL_PLL0_CLK2
582 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
583 
`endif
584 
`ifdef VL_PLL0_CLK3
585 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
586 
`endif
587 
`ifdef VL_PLL0_CLK4
588 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
589 
`endif
590 
`ifdef VL_PLL0_CLK5
591 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
592 
`endif
593 
`endif
594 32 unneback 
 
595 33 unneback 
`ifdef VL_PLL1
596 
`ifdef VL_PLL1_CLK1
597 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
598 
`endif
599 
`ifdef VL_PLL1_CLK2
600 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
601 
`endif
602 
`ifdef VL_PLL1_CLK3
603 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
604 
`endif
605 
`ifdef VL_PLL1_CLK4
606 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
607 
`endif
608 
`ifdef VL_PLL1_CLK5
609 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
610 
`endif
611 
`endif
612 32 unneback 
 
613 33 unneback 
`ifdef VL_PLL2
614 
`ifdef VL_PLL2_CLK1
615 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
616 
`endif
617 
`ifdef VL_PLL2_CLK2
618 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
619 
`endif
620 
`ifdef VL_PLL2_CLK3
621 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
622 
`endif
623 
`ifdef VL_PLL2_CLK4
624 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
625 
`endif
626 
`ifdef VL_PLL2_CLK5
627 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
628 
`endif
629 
`endif
630 32 unneback 
 
631 33 unneback 
`ifdef VL_PLL3
632 
`ifdef VL_PLL3_CLK1
633 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
634 
`endif
635 
`ifdef VL_PLL3_CLK2
636 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
637 
`endif
638 
`ifdef VL_PLL3_CLK3
639 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
640 
`endif
641 
`ifdef VL_PLL3_CLK4
642 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
643 
`endif
644 
`ifdef VL_PLL3_CLK5
645 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
646 
`endif
647 
`endif
648 32 unneback 
 
649 
genvar i;
650 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
651 40 unneback 
`define MODULE sync_rst
652 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
653 
`undef MODULE
654 32 unneback 
end
655 
endgenerate
656 
endmodule
657 
`endif
658 
///////////////////////////////////////////////////////////////////////////////
659 
 
660 
`else
661 
 
662 6 unneback 
// generic PLL
663 17 unneback 
`timescale 1 ps/1 ps
664 40 unneback 
`define MODULE pll
665 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
666 
`undef MODULE
667 6 unneback 
parameter index = 0;
668 
parameter number_of_clk = 1;
669 17 unneback 
parameter period_time_0 = 20000;
670 
parameter period_time_1 = 20000;
671 
parameter period_time_2 = 20000;
672 6 unneback 
parameter lock_delay = 2000;
673 
input clk_i, rst_n_i;
674 
output lock;
675 
output reg [0:number_of_clk-1] clk_o;
676 
output [0:number_of_clk-1] rst_o;
677 
 
678 
always
679 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
680 
 
681 
generate if (number_of_clk > 1)
682 
always
683 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
684 
endgenerate
685 
 
686 
generate if (number_of_clk > 2)
687 
always
688 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
689 
endgenerate
690 
 
691 
genvar i;
692 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
693 40 unneback 
`define MODULE sync_rst
694 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
695 
`undef MODULE
696 6 unneback 
end
697 
endgenerate
698 
 
699 
assign #lock_delay lock = rst_n_i;
700 
 
701 
endmodule
702 
 
703 
`endif //altera
704 17 unneback 
`endif //actel
705 40 unneback 
`undef MODULE
706 
`endif//////////////////////////////////////////////////////////////////////
707 6 unneback 
////                                                              ////
708 
////  Versatile library, registers                                ////
709 
////                                                              ////
710 
////  Description                                                 ////
711 
////  Different type of registers                                 ////
712 
////                                                              ////
713 
////                                                              ////
714 
////  To Do:                                                      ////
715 
////   - add more different registers                             ////
716 
////                                                              ////
717 
////  Author(s):                                                  ////
718 
////      - Michael Unneback, unneback@opencores.org              ////
719 
////        ORSoC AB                                              ////
720 
////                                                              ////
721 
//////////////////////////////////////////////////////////////////////
722 
////                                                              ////
723 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
724 
////                                                              ////
725 
//// This source file may be used and distributed without         ////
726 
//// restriction provided that this copyright statement is not    ////
727 
//// removed from the file and that any derivative work contains  ////
728 
//// the original copyright notice and the associated disclaimer. ////
729 
////                                                              ////
730 
//// This source file is free software; you can redistribute it   ////
731 
//// and/or modify it under the terms of the GNU Lesser General   ////
732 
//// Public License as published by the Free Software Foundation; ////
733 
//// either version 2.1 of the License, or (at your option) any   ////
734 
//// later version.                                               ////
735 
////                                                              ////
736 
//// This source is distributed in the hope that it will be       ////
737 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
738 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
739 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
740 
//// details.                                                     ////
741 
////                                                              ////
742 
//// You should have received a copy of the GNU Lesser General    ////
743 
//// Public License along with this source; if not, download it   ////
744 
//// from http://www.opencores.org/lgpl.shtml                     ////
745 
////                                                              ////
746 
//////////////////////////////////////////////////////////////////////
747 
 
748 40 unneback 
`ifdef DFF
749 
`define MODULE dff
750 
module `BASE`MODULE ( d, q, clk, rst);
751 
`undef MODULE
752 6 unneback 
        parameter width = 1;
753 
        parameter reset_value = 0;
754 
 
755 
        input [width-1:0] d;
756 
        input clk, rst;
757 
        output reg [width-1:0] q;
758 
 
759 
        always @ (posedge clk or posedge rst)
760 
        if (rst)
761 
                q <= reset_value;
762 
        else
763 
                q <= d;
764 
 
765 
endmodule
766 40 unneback 
`endif
767 6 unneback 
 
768 40 unneback 
`ifdef DFF_ARRAY
769 
`define MODULE dff_array
770 
module `BASE`MODULE ( d, q, clk, rst);
771 
`undef MODULE
772 6 unneback 
 
773 
        parameter width = 1;
774 
        parameter depth = 2;
775 
        parameter reset_value = 1'b0;
776 
 
777 
        input [width-1:0] d;
778 
        input clk, rst;
779 
        output [width-1:0] q;
780 
        reg  [0:depth-1] q_tmp [width-1:0];
781 
        integer i;
782 
        always @ (posedge clk or posedge rst)
783 
        if (rst) begin
784 
            for (i=0;i<depth;i=i+1)
785 
                q_tmp[i] <= {width{reset_value}};
786 
        end else begin
787 
            q_tmp[0] <= d;
788 
            for (i=1;i<depth;i=i+1)
789 
                q_tmp[i] <= q_tmp[i-1];
790 
        end
791 
 
792 
    assign q = q_tmp[depth-1];
793 
 
794 
endmodule
795 40 unneback 
`endif
796 6 unneback 
 
797 40 unneback 
`ifdef DFF_CE
798 
`define MODULE dff_ce
799 
module `BASE`MODULE ( d, ce, q, clk, rst);
800 
`undef MODULE
801 6 unneback 
 
802 
        parameter width = 1;
803 
        parameter reset_value = 0;
804 
 
805 
        input [width-1:0] d;
806 
        input ce, clk, rst;
807 
        output reg [width-1:0] q;
808 
 
809 
        always @ (posedge clk or posedge rst)
810 
        if (rst)
811 
                q <= reset_value;
812 
        else
813 
                if (ce)
814 
                        q <= d;
815 
 
816 
endmodule
817 40 unneback 
`endif
818 6 unneback 
 
819 40 unneback 
`ifdef DFF_CE_CLEAR
820 
`define MODULE dff_ce_clear
821 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
822 
`undef MODULE
823 8 unneback 
 
824 
        parameter width = 1;
825 
        parameter reset_value = 0;
826 
 
827 
        input [width-1:0] d;
828 10 unneback 
        input ce, clear, clk, rst;
829 8 unneback 
        output reg [width-1:0] q;
830 
 
831 
        always @ (posedge clk or posedge rst)
832 
        if (rst)
833 
            q <= reset_value;
834 
        else
835 
            if (ce)
836 
                if (clear)
837 
                    q <= {width{1'b0}};
838 
                else
839 
                    q <= d;
840 
 
841 
endmodule
842 40 unneback 
`endif
843 8 unneback 
 
844 40 unneback 
`ifdef DF_CE_SET
845 
`define MODULE dff_ce_set
846 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
847 
`undef MODULE
848 24 unneback 
 
849 
        parameter width = 1;
850 
        parameter reset_value = 0;
851 
 
852 
        input [width-1:0] d;
853 
        input ce, set, clk, rst;
854 
        output reg [width-1:0] q;
855 
 
856 
        always @ (posedge clk or posedge rst)
857 
        if (rst)
858 
            q <= reset_value;
859 
        else
860 
            if (ce)
861 
                if (set)
862 
                    q <= {width{1'b1}};
863 
                else
864 
                    q <= d;
865 
 
866 
endmodule
867 40 unneback 
`endif
868 24 unneback 
 
869 40 unneback 
`ifdef SPR
870 
`define MODULE spr
871 
module `BASE`MODULE ( sp, r, q, clk, rst);
872 
`undef MODULE
873 
 
874 64 unneback 
        //parameter width = 1;
875 
        parameter reset_value = 1'b0;
876 29 unneback 
 
877 
        input sp, r;
878 
        output reg q;
879 
        input clk, rst;
880 
 
881 
        always @ (posedge clk or posedge rst)
882 
        if (rst)
883 
            q <= reset_value;
884 
        else
885 
            if (sp)
886 
                q <= 1'b1;
887 
            else if (r)
888 
                q <= 1'b0;
889 
 
890 
endmodule
891 40 unneback 
`endif
892 29 unneback 
 
893 40 unneback 
`ifdef SRP
894 
`define MODULE srp
895 
module `BASE`MODULE ( s, rp, q, clk, rst);
896 
`undef MODULE
897 
 
898 29 unneback 
        parameter width = 1;
899 
        parameter reset_value = 0;
900 
 
901 
        input s, rp;
902 
        output reg q;
903 
        input clk, rst;
904 
 
905 
        always @ (posedge clk or posedge rst)
906 
        if (rst)
907 
            q <= reset_value;
908 
        else
909 
            if (rp)
910 
                q <= 1'b0;
911 
            else if (s)
912 
                q <= 1'b1;
913 
 
914 
endmodule
915 40 unneback 
`endif
916 29 unneback 
 
917 40 unneback 
`ifdef ALTERA
918 29 unneback 
 
919 40 unneback 
`ifdef DFF_SR
920 6 unneback 
// megafunction wizard: %LPM_FF%
921 
// GENERATION: STANDARD
922 
// VERSION: WM1.0
923 
// MODULE: lpm_ff
924 
 
925 
// ============================================================
926 
// File Name: dff_sr.v
927 
// Megafunction Name(s):
928 
//                      lpm_ff
929 
//
930 
// Simulation Library Files(s):
931 
//                      lpm
932 
// ============================================================
933 
// ************************************************************
934 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
935 
//
936 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
937 
// ************************************************************
938 
 
939 
 
940 
//Copyright (C) 1991-2010 Altera Corporation
941 
//Your use of Altera Corporation's design tools, logic functions
942 
//and other software and tools, and its AMPP partner logic
943 
//functions, and any output files from any of the foregoing
944 
//(including device programming or simulation files), and any
945 
//associated documentation or information are expressly subject
946 
//to the terms and conditions of the Altera Program License
947 
//Subscription Agreement, Altera MegaCore Function License
948 
//Agreement, or other applicable license agreement, including,
949 
//without limitation, that your use is for the sole purpose of
950 
//programming logic devices manufactured by Altera and sold by
951 
//Altera or its authorized distributors.  Please refer to the
952 
//applicable agreement for further details.
953 
 
954 
 
955 
// synopsys translate_off
956 
`timescale 1 ps / 1 ps
957 
// synopsys translate_on
958 40 unneback 
`define MODULE dff_sr
959 
module `BASE`MODULE (
960 
`undef MODULE
961 
 
962 6 unneback 
        aclr,
963 
        aset,
964 
        clock,
965 
        data,
966 
        q);
967 
 
968 
        input     aclr;
969 
        input     aset;
970 
        input     clock;
971 
        input     data;
972 
        output    q;
973 
 
974 
        wire [0:0] sub_wire0;
975 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
976 
        wire  q = sub_wire1;
977 
        wire  sub_wire2 = data;
978 
        wire  sub_wire3 = sub_wire2;
979 
 
980 
        lpm_ff  lpm_ff_component (
981 
                                .aclr (aclr),
982 
                                .clock (clock),
983 
                                .data (sub_wire3),
984 
                                .aset (aset),
985 
                                .q (sub_wire0)
986 
                                // synopsys translate_off
987 
                                ,
988 
                                .aload (),
989 
                                .enable (),
990 
                                .sclr (),
991 
                                .sload (),
992 
                                .sset ()
993 
                                // synopsys translate_on
994 
                                );
995 
        defparam
996 
                lpm_ff_component.lpm_fftype = "DFF",
997 
                lpm_ff_component.lpm_type = "LPM_FF",
998 
                lpm_ff_component.lpm_width = 1;
999 
 
1000 
 
1001 
endmodule
1002 
 
1003 
// ============================================================
1004 
// CNX file retrieval info
1005 
// ============================================================
1006 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1007 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1008 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1009 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1010 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1011 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1012 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1013 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1014 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1015 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1016 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1017 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1018 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1019 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1020 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1021 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1022 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1023 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1024 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1025 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1026 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1027 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1028 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1029 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1030 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1031 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1032 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1033 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1034 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1035 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1036 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1037 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1038 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1039 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1040 
// Retrieval info: LIB_FILE: lpm
1041 40 unneback 
`endif
1042 6 unneback 
 
1043 
`else
1044 
 
1045 40 unneback 
`ifdef DFF_SR
1046 
`define MODULE dff_sr
1047 
module `BASE`MODULE ( aclr, aset, clock, data, q);
1048 
`undef MODULE
1049 6 unneback 
 
1050 
    input         aclr;
1051 
    input         aset;
1052 
    input         clock;
1053 
    input         data;
1054 
    output reg    q;
1055 
 
1056 
   always @ (posedge clock or posedge aclr or posedge aset)
1057 
     if (aclr)
1058 
       q <= 1'b0;
1059 
     else if (aset)
1060 
       q <= 1'b1;
1061 
     else
1062 
       q <= data;
1063 
 
1064 
endmodule
1065 40 unneback 
`endif
1066 6 unneback 
 
1067 
`endif
1068 
 
1069 
// LATCH
1070 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1071 
`ifdef ALTERA
1072 40 unneback 
 
1073 
`ifdef LATCH
1074 
`define MODULE latch
1075 
module `BASE`MODULE ( d, le, q, clk);
1076 
`undef MODULE
1077 6 unneback 
input d, le;
1078 
output q;
1079 
input clk;
1080 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1081 
endmodule
1082 40 unneback 
`endif
1083 
 
1084 6 unneback 
`else
1085 40 unneback 
 
1086 
`ifdef LATCH
1087 
`define MODULE latch
1088 
module `BASE`MODULE ( d, le, q, clk);
1089 
`undef MODULE
1090 6 unneback 
input d, le;
1091 48 unneback 
input clk;
1092 
always @ (le or d)
1093 60 unneback 
if (le)
1094 48 unneback 
    d <= q;
1095 6 unneback 
endmodule
1096 15 unneback 
`endif
1097 
 
1098 40 unneback 
`endif
1099 
 
1100 
`ifdef SHREG
1101 
`define MODULE shreg
1102 
module `BASE`MODULE ( d, q, clk, rst);
1103 
`undef MODULE
1104 
 
1105 17 unneback 
parameter depth = 10;
1106 
input d;
1107 
output q;
1108 
input clk, rst;
1109 
 
1110 
reg [1:depth] dffs;
1111 
 
1112 
always @ (posedge clk or posedge rst)
1113 
if (rst)
1114 
    dffs <= {depth{1'b0}};
1115 
else
1116 
    dffs <= {d,dffs[1:depth-1]};
1117 
assign q = dffs[depth];
1118 
endmodule
1119 40 unneback 
`endif
1120 17 unneback 
 
1121 40 unneback 
`ifdef SHREG_CE
1122 
`define MODULE shreg_ce
1123 
module `BASE`MODULE ( d, ce, q, clk, rst);
1124 
`undef MODULE
1125 17 unneback 
parameter depth = 10;
1126 
input d, ce;
1127 
output q;
1128 
input clk, rst;
1129 
 
1130 
reg [1:depth] dffs;
1131 
 
1132 
always @ (posedge clk or posedge rst)
1133 
if (rst)
1134 
    dffs <= {depth{1'b0}};
1135 
else
1136 
    if (ce)
1137 
        dffs <= {d,dffs[1:depth-1]};
1138 
assign q = dffs[depth];
1139 
endmodule
1140 40 unneback 
`endif
1141 17 unneback 
 
1142 40 unneback 
`ifdef DELAY
1143 
`define MODULE delay
1144 
module `BASE`MODULE ( d, q, clk, rst);
1145 
`undef MODULE
1146 15 unneback 
parameter depth = 10;
1147 
input d;
1148 
output q;
1149 
input clk, rst;
1150 
 
1151 
reg [1:depth] dffs;
1152 
 
1153 
always @ (posedge clk or posedge rst)
1154 
if (rst)
1155 
    dffs <= {depth{1'b0}};
1156 
else
1157 
    dffs <= {d,dffs[1:depth-1]};
1158 
assign q = dffs[depth];
1159 17 unneback 
endmodule
1160 40 unneback 
`endif
1161 17 unneback 
 
1162 40 unneback 
`ifdef DELAY_EMPTYFLAG
1163 
`define MODULE delay_emptyflag
1164 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1165 40 unneback 
`undef MODULE
1166 17 unneback 
parameter depth = 10;
1167 
input d;
1168 
output q, emptyflag;
1169 
input clk, rst;
1170 
 
1171 
reg [1:depth] dffs;
1172 
 
1173 
always @ (posedge clk or posedge rst)
1174 
if (rst)
1175 
    dffs <= {depth{1'b0}};
1176 
else
1177 
    dffs <= {d,dffs[1:depth-1]};
1178 
assign q = dffs[depth];
1179 
assign emptyflag = !(|dffs);
1180 
endmodule
1181 40 unneback 
`endif
1182 75 unneback 
 
1183 94 unneback 
`ifdef PULSE2TOGGLE
1184 
`define MODULE pules2toggle
1185 
module `BASE`MODULE ( pl, q, clk, rst)
1186 75 unneback 
`undef MODULE
1187 94 unneback 
input pl;
1188 
output q;
1189 
input clk, rst;
1190 
input
1191 
always @ (posedge clk or posedge rst)
1192 75 unneback 
if (rst)
1193 94 unneback 
    q <= 1'b0;
1194 75 unneback 
else
1195 94 unneback 
    q <= pl ^ q;
1196 
endmodule
1197 
`endif
1198 75 unneback 
 
1199 94 unneback 
`ifdef TOGGLE2PULSE
1200 
`define MODULE toggle2pulse;
1201 
module `BASE`MODULE (d, pl, clk, rst);
1202 97 unneback 
`undef MODULE
1203 94 unneback 
input d;
1204 
output pl;
1205 
input clk, rst;
1206 
reg dff;
1207 
always @ (posedge clk or posedge rst)
1208 
if (rst)
1209 
    dff <= 1'b0;
1210 75 unneback 
else
1211 94 unneback 
    dff <= d;
1212 
assign d ^ dff;
1213 
endmodule
1214 
`endif
1215 75 unneback 
 
1216 94 unneback 
`ifdef SYNCHRONIZER
1217 
`define MODULE synchronizer
1218 
module `BASE`MODULE (d, q, clk, rst);
1219 
`undef MODULE
1220 
input d;
1221 
output reg q;
1222 
output clk, rst;
1223 
reg dff;
1224 
always @ (posedge clk or posedge rst)
1225 
if (rst)
1226 
    {dff,q} <= 2'b00;
1227 75 unneback 
else
1228 94 unneback 
    {dff,q} <= {d,dff};
1229 
endmodule
1230 
`endif
1231 75 unneback 
 
1232 94 unneback 
`ifdef CDC
1233 
`define MODULE cdc
1234 97 unneback 
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1235 94 unneback 
`undef MODULE
1236 
input start_pl;
1237 
output take_it_pl;
1238 
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1239 
output got_it_pl;
1240 
input clk_src, rst_src;
1241 
input clk_dst, rst_dst;
1242 
wire take_it_tg, take_it_tg_sync;
1243 
wire got_it_tg, got_it_tg_sync;
1244 
// src -> dst
1245 
`define MODULE pulse2toggle
1246 
`BASE`MODULE p2t0 (
1247 
`undef MODULE
1248 
    .pl(start_pl),
1249 
    .q(take_it_tg),
1250 
    .clk(clk_src),
1251 
    .rst(rst_src));
1252 75 unneback 
 
1253 94 unneback 
`define MODULE synchronizer
1254 
`BASE`MODULE sync0 (
1255 
`undef MODULE
1256 
    .d(take_it_tg),
1257 
    .q(take_it_tg_sync),
1258 
    .clk(clk_dst),
1259 
    .rst(rst_dst));
1260 
 
1261 
`define MODULE toggle2pulse
1262 
`BASE`MODULE t2p0 (
1263 
`undef MODULE
1264 
    .d(take_it_sync),
1265 
    .pl(take_it_pl),
1266 
    .clk(clk_dst),
1267 
    .rst(rst_dst));
1268 
 
1269 
// dst -> src
1270 
`define MODULE pulse2toggle
1271 
`BASE`MODULE p2t0 (
1272 
`undef MODULE
1273 
    .pl(take_it_grant_pl),
1274 
    .q(got_it_tg),
1275 
    .clk(clk_dst),
1276 
    .rst(rst_dst));
1277 
 
1278 
`define MODULE synchronizer
1279 
`BASE`MODULE sync1 (
1280 
`undef MODULE
1281 
    .d(got_it_tg),
1282 
    .q(got_it_tg_sync),
1283 
    .clk(clk_src),
1284 
    .rst(rst_src));
1285 
 
1286 
`define MODULE toggle2pulse
1287 
`BASE`MODULE t2p1 (
1288 
`undef MODULE
1289 
    .d(take_it_grant_tg_sync),
1290 
    .pl(got_it_pl),
1291 
    .clk(clk_src),
1292 
    .rst(rst_src));
1293 
 
1294 75 unneback 
endmodule
1295 
`endif
1296 17 unneback 
//////////////////////////////////////////////////////////////////////
1297 6 unneback 
////                                                              ////
1298 18 unneback 
////  Logic functions                                             ////
1299 
////                                                              ////
1300 
////  Description                                                 ////
1301 
////  Logic functions such as multiplexers                        ////
1302 
////                                                              ////
1303 
////                                                              ////
1304 
////  To Do:                                                      ////
1305 
////   -                                                          ////
1306 
////                                                              ////
1307 
////  Author(s):                                                  ////
1308 
////      - Michael Unneback, unneback@opencores.org              ////
1309 
////        ORSoC AB                                              ////
1310 
////                                                              ////
1311 
//////////////////////////////////////////////////////////////////////
1312 
////                                                              ////
1313 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1314 
////                                                              ////
1315 
//// This source file may be used and distributed without         ////
1316 
//// restriction provided that this copyright statement is not    ////
1317 
//// removed from the file and that any derivative work contains  ////
1318 
//// the original copyright notice and the associated disclaimer. ////
1319 
////                                                              ////
1320 
//// This source file is free software; you can redistribute it   ////
1321 
//// and/or modify it under the terms of the GNU Lesser General   ////
1322 
//// Public License as published by the Free Software Foundation; ////
1323 
//// either version 2.1 of the License, or (at your option) any   ////
1324 
//// later version.                                               ////
1325 
////                                                              ////
1326 
//// This source is distributed in the hope that it will be       ////
1327 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1328 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1329 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1330 
//// details.                                                     ////
1331 
////                                                              ////
1332 
//// You should have received a copy of the GNU Lesser General    ////
1333 
//// Public License along with this source; if not, download it   ////
1334 
//// from http://www.opencores.org/lgpl.shtml                     ////
1335 
////                                                              ////
1336 
//////////////////////////////////////////////////////////////////////
1337 40 unneback 
`ifdef MUX_ANDOR
1338 
`define MODULE mux_andor
1339 
module `BASE`MODULE ( a, sel, dout);
1340 
`undef MODULE
1341 36 unneback 
 
1342 
parameter width = 32;
1343 
parameter nr_of_ports = 4;
1344 
 
1345 
input [nr_of_ports*width-1:0] a;
1346 
input [nr_of_ports-1:0] sel;
1347 
output reg [width-1:0] dout;
1348 
 
1349 38 unneback 
integer i,j;
1350 
 
1351 36 unneback 
always @ (a, sel)
1352 
begin
1353 
    dout = a[width-1:0] & {width{sel[0]}};
1354 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1355 
        for (j=0;j<width;j=j+1)
1356 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1357 36 unneback 
end
1358 
 
1359 
endmodule
1360 40 unneback 
`endif
1361 36 unneback 
 
1362 40 unneback 
`ifdef MUX2_ANDOR
1363 
`define MODULE mux2_andor
1364 
module `BASE`MODULE ( a1, a0, sel, dout);
1365 
`undef MODULE
1366 18 unneback 
 
1367 34 unneback 
parameter width = 32;
1368 35 unneback 
localparam nr_of_ports = 2;
1369 34 unneback 
input [width-1:0] a1, a0;
1370 
input [nr_of_ports-1:0] sel;
1371 
output [width-1:0] dout;
1372 
 
1373 40 unneback 
`define MODULE mux_andor
1374 
`BASE`MODULE
1375 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1376 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1377 40 unneback 
`undef MODULE
1378 
 
1379 34 unneback 
endmodule
1380 40 unneback 
`endif
1381 34 unneback 
 
1382 40 unneback 
`ifdef MUX3_ANDOR
1383 
`define MODULE mux3_andor
1384 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1385 
`undef MODULE
1386 34 unneback 
 
1387 
parameter width = 32;
1388 35 unneback 
localparam nr_of_ports = 3;
1389 34 unneback 
input [width-1:0] a2, a1, a0;
1390 
input [nr_of_ports-1:0] sel;
1391 
output [width-1:0] dout;
1392 
 
1393 40 unneback 
`define MODULE mux_andor
1394 
`BASE`MODULE
1395 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1396 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1397 40 unneback 
`undef MODULE
1398 34 unneback 
endmodule
1399 40 unneback 
`endif
1400 34 unneback 
 
1401 40 unneback 
`ifdef MUX4_ANDOR
1402 
`define MODULE mux4_andor
1403 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1404 
`undef MODULE
1405 18 unneback 
 
1406 
parameter width = 32;
1407 35 unneback 
localparam nr_of_ports = 4;
1408 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1409 
input [nr_of_ports-1:0] sel;
1410 22 unneback 
output [width-1:0] dout;
1411 18 unneback 
 
1412 40 unneback 
`define MODULE mux_andor
1413 
`BASE`MODULE
1414 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1415 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1416 40 unneback 
`undef MODULE
1417 18 unneback 
 
1418 
endmodule
1419 40 unneback 
`endif
1420 18 unneback 
 
1421 40 unneback 
`ifdef MUX5_ANDOR
1422 
`define MODULE mux5_andor
1423 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1424 
`undef MODULE
1425 18 unneback 
 
1426 
parameter width = 32;
1427 35 unneback 
localparam nr_of_ports = 5;
1428 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1429 
input [nr_of_ports-1:0] sel;
1430 22 unneback 
output [width-1:0] dout;
1431 18 unneback 
 
1432 40 unneback 
`define MODULE mux_andor
1433 
`BASE`MODULE
1434 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1435 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1436 40 unneback 
`undef MODULE
1437 18 unneback 
 
1438 
endmodule
1439 40 unneback 
`endif
1440 18 unneback 
 
1441 40 unneback 
`ifdef MUX6_ANDOR
1442 
`define MODULE mux6_andor
1443 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1444 
`undef MODULE
1445 18 unneback 
 
1446 
parameter width = 32;
1447 35 unneback 
localparam nr_of_ports = 6;
1448 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1449 
input [nr_of_ports-1:0] sel;
1450 22 unneback 
output [width-1:0] dout;
1451 18 unneback 
 
1452 40 unneback 
`define MODULE mux_andor
1453 
`BASE`MODULE
1454 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1455 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1456 40 unneback 
`undef MODULE
1457 18 unneback 
 
1458 
endmodule
1459 40 unneback 
`endif
1460 43 unneback 
 
1461 
`ifdef PARITY
1462 
 
1463 
`define MODULE parity_generate
1464 
module `BASE`MODULE (data, parity);
1465 
`undef MODULE
1466 
parameter word_size = 32;
1467 
parameter chunk_size = 8;
1468 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1469 
input [word_size-1:0] data;
1470 
output reg [word_size/chunk_size-1:0] parity;
1471 
integer i,j;
1472 
always @ (data)
1473 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1474 
    parity[i] = parity_type;
1475 
    for (j=0;j<chunk_size;j=j+1) begin
1476 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1477 43 unneback 
    end
1478 
end
1479 
endmodule
1480 
 
1481 
`define MODULE parity_check
1482 
module `BASE`MODULE( data, parity, parity_error);
1483 
`undef MODULE
1484 
parameter word_size = 32;
1485 
parameter chunk_size = 8;
1486 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1487 
input [word_size-1:0] data;
1488 
input [word_size/chunk_size-1:0] parity;
1489 
output parity_error;
1490 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1491 43 unneback 
integer i,j;
1492 
always @ (data or parity)
1493 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1494 
    error_flag[i] = parity[i] ^ parity_type;
1495 
    for (j=0;j<chunk_size;j=j+1) begin
1496 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1497 43 unneback 
    end
1498 
end
1499 
assign parity_error = |error_flag;
1500 
endmodule
1501 
 
1502 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1503 
////                                                              ////
1504 
////  IO functions                                                ////
1505 
////                                                              ////
1506 
////  Description                                                 ////
1507 
////  IO functions such as IOB flip-flops                         ////
1508 
////                                                              ////
1509 
////                                                              ////
1510 
////  To Do:                                                      ////
1511 
////   -                                                          ////
1512 
////                                                              ////
1513 
////  Author(s):                                                  ////
1514 
////      - Michael Unneback, unneback@opencores.org              ////
1515 
////        ORSoC AB                                              ////
1516 
////                                                              ////
1517 18 unneback 
//////////////////////////////////////////////////////////////////////
1518 
////                                                              ////
1519 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1520 
////                                                              ////
1521 
//// This source file may be used and distributed without         ////
1522 
//// restriction provided that this copyright statement is not    ////
1523 
//// removed from the file and that any derivative work contains  ////
1524 
//// the original copyright notice and the associated disclaimer. ////
1525 
////                                                              ////
1526 
//// This source file is free software; you can redistribute it   ////
1527 
//// and/or modify it under the terms of the GNU Lesser General   ////
1528 
//// Public License as published by the Free Software Foundation; ////
1529 
//// either version 2.1 of the License, or (at your option) any   ////
1530 
//// later version.                                               ////
1531 
////                                                              ////
1532 
//// This source is distributed in the hope that it will be       ////
1533 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1534 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1535 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1536 
//// details.                                                     ////
1537 
////                                                              ////
1538 
//// You should have received a copy of the GNU Lesser General    ////
1539 
//// Public License along with this source; if not, download it   ////
1540 
//// from http://www.opencores.org/lgpl.shtml                     ////
1541 
////                                                              ////
1542 
//////////////////////////////////////////////////////////////////////
1543 45 unneback 
`timescale 1ns/1ns
1544 44 unneback 
`ifdef O_DFF
1545 
`define MODULE o_dff
1546 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1547 
`undef MODULE
1548 
parameter width = 1;
1549 45 unneback 
parameter reset_value = {width{1'b0}};
1550 
input  [width-1:0]  d_i;
1551 44 unneback 
output [width-1:0] o_pad;
1552 
input clk, rst;
1553 
wire [width-1:0] d_i_int `SYN_KEEP;
1554 45 unneback 
reg  [width-1:0] o_pad_int;
1555 44 unneback 
assign d_i_int = d_i;
1556 
genvar i;
1557 45 unneback 
generate
1558 44 unneback 
for (i=0;i<width;i=i+1) begin
1559 
    always @ (posedge clk or posedge rst)
1560 
    if (rst)
1561 45 unneback 
        o_pad_int[i] <= reset_value[i];
1562 44 unneback 
    else
1563 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1564 
    assign #1 o_pad[i] = o_pad_int[i];
1565 44 unneback 
end
1566 
endgenerate
1567 
endmodule
1568 
`endif
1569 
 
1570 45 unneback 
`timescale 1ns/1ns
1571 44 unneback 
`ifdef IO_DFF_OE
1572 
`define MODULE io_dff_oe
1573 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1574 
`undef MODULE
1575 
parameter width = 1;
1576 
input  [width-1:0] d_o;
1577 
output reg [width-1:0] d_i;
1578 
input oe;
1579 
inout [width-1:0] io_pad;
1580 
input clk, rst;
1581 
wire [width-1:0] oe_d `SYN_KEEP;
1582 
reg [width-1:0] oe_q;
1583 
reg [width-1:0] d_o_q;
1584 
assign oe_d = {width{oe}};
1585 
genvar i;
1586 
generate
1587 
for (i=0;i<width;i=i+1) begin
1588 
    always @ (posedge clk or posedge rst)
1589 
    if (rst)
1590 
        oe_q[i] <= 1'b0;
1591 
    else
1592 
        oe_q[i] <= oe_d[i];
1593 
    always @ (posedge clk or posedge rst)
1594 
    if (rst)
1595 
        d_o_q[i] <= 1'b0;
1596 
    else
1597 
        d_o_q[i] <= d_o[i];
1598 
    always @ (posedge clk or posedge rst)
1599 
    if (rst)
1600 
        d_i[i] <= 1'b0;
1601 
    else
1602 
        d_i[i] <= io_pad[i];
1603 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1604 44 unneback 
end
1605 
endgenerate
1606 
endmodule
1607 
`endif
1608 
`ifdef CNT_BIN
1609 
//////////////////////////////////////////////////////////////////////
1610 
////                                                              ////
1611 6 unneback 
////  Versatile counter                                           ////
1612 
////                                                              ////
1613 
////  Description                                                 ////
1614 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1615 
////  counter                                                     ////
1616 
////                                                              ////
1617 
////  To Do:                                                      ////
1618 
////   - add LFSR with more taps                                  ////
1619 
////                                                              ////
1620 
////  Author(s):                                                  ////
1621 
////      - Michael Unneback, unneback@opencores.org              ////
1622 
////        ORSoC AB                                              ////
1623 
////                                                              ////
1624 
//////////////////////////////////////////////////////////////////////
1625 
////                                                              ////
1626 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1627 
////                                                              ////
1628 
//// This source file may be used and distributed without         ////
1629 
//// restriction provided that this copyright statement is not    ////
1630 
//// removed from the file and that any derivative work contains  ////
1631 
//// the original copyright notice and the associated disclaimer. ////
1632 
////                                                              ////
1633 
//// This source file is free software; you can redistribute it   ////
1634 
//// and/or modify it under the terms of the GNU Lesser General   ////
1635 
//// Public License as published by the Free Software Foundation; ////
1636 
//// either version 2.1 of the License, or (at your option) any   ////
1637 
//// later version.                                               ////
1638 
////                                                              ////
1639 
//// This source is distributed in the hope that it will be       ////
1640 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1641 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1642 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1643 
//// details.                                                     ////
1644 
////                                                              ////
1645 
//// You should have received a copy of the GNU Lesser General    ////
1646 
//// Public License along with this source; if not, download it   ////
1647 
//// from http://www.opencores.org/lgpl.shtml                     ////
1648 
////                                                              ////
1649 
//////////////////////////////////////////////////////////////////////
1650 
 
1651 
// binary counter
1652 22 unneback 
 
1653 40 unneback 
`define MODULE cnt_bin
1654 
module `BASE`MODULE (
1655 
`undef MODULE
1656 
 q, rst, clk);
1657 
 
1658 22 unneback 
   parameter length = 4;
1659 
   output [length:1] q;
1660 
   input rst;
1661 
   input clk;
1662 
 
1663 
   parameter clear_value = 0;
1664 
   parameter set_value = 1;
1665 
   parameter wrap_value = 0;
1666 
   parameter level1_value = 15;
1667 
 
1668 
   reg  [length:1] qi;
1669 
   wire [length:1] q_next;
1670 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1671 
 
1672 
   always @ (posedge clk or posedge rst)
1673 
     if (rst)
1674 
       qi <= {length{1'b0}};
1675 
     else
1676 
       qi <= q_next;
1677 
 
1678 
   assign q = qi;
1679 
 
1680 
endmodule
1681 40 unneback 
`endif
1682 
`ifdef CNT_BIN_CLEAR
1683 22 unneback 
//////////////////////////////////////////////////////////////////////
1684 
////                                                              ////
1685 
////  Versatile counter                                           ////
1686 
////                                                              ////
1687 
////  Description                                                 ////
1688 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1689 
////  counter                                                     ////
1690 
////                                                              ////
1691 
////  To Do:                                                      ////
1692 
////   - add LFSR with more taps                                  ////
1693 
////                                                              ////
1694 
////  Author(s):                                                  ////
1695 
////      - Michael Unneback, unneback@opencores.org              ////
1696 
////        ORSoC AB                                              ////
1697 
////                                                              ////
1698 
//////////////////////////////////////////////////////////////////////
1699 
////                                                              ////
1700 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1701 
////                                                              ////
1702 
//// This source file may be used and distributed without         ////
1703 
//// restriction provided that this copyright statement is not    ////
1704 
//// removed from the file and that any derivative work contains  ////
1705 
//// the original copyright notice and the associated disclaimer. ////
1706 
////                                                              ////
1707 
//// This source file is free software; you can redistribute it   ////
1708 
//// and/or modify it under the terms of the GNU Lesser General   ////
1709 
//// Public License as published by the Free Software Foundation; ////
1710 
//// either version 2.1 of the License, or (at your option) any   ////
1711 
//// later version.                                               ////
1712 
////                                                              ////
1713 
//// This source is distributed in the hope that it will be       ////
1714 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1715 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1716 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1717 
//// details.                                                     ////
1718 
////                                                              ////
1719 
//// You should have received a copy of the GNU Lesser General    ////
1720 
//// Public License along with this source; if not, download it   ////
1721 
//// from http://www.opencores.org/lgpl.shtml                     ////
1722 
////                                                              ////
1723 
//////////////////////////////////////////////////////////////////////
1724 
 
1725 
// binary counter
1726 
 
1727 40 unneback 
`define MODULE cnt_bin_clear
1728 
module `BASE`MODULE (
1729 
`undef MODULE
1730 
 clear, q, rst, clk);
1731 
 
1732 22 unneback 
   parameter length = 4;
1733 
   input clear;
1734 
   output [length:1] q;
1735 
   input rst;
1736 
   input clk;
1737 
 
1738 
   parameter clear_value = 0;
1739 
   parameter set_value = 1;
1740 
   parameter wrap_value = 0;
1741 
   parameter level1_value = 15;
1742 
 
1743 
   reg  [length:1] qi;
1744 
   wire [length:1] q_next;
1745 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1746 
 
1747 
   always @ (posedge clk or posedge rst)
1748 
     if (rst)
1749 
       qi <= {length{1'b0}};
1750 
     else
1751 
       qi <= q_next;
1752 
 
1753 
   assign q = qi;
1754 
 
1755 
endmodule
1756 40 unneback 
`endif
1757 
`ifdef CNT_BIN_CE
1758 22 unneback 
//////////////////////////////////////////////////////////////////////
1759 
////                                                              ////
1760 
////  Versatile counter                                           ////
1761 
////                                                              ////
1762 
////  Description                                                 ////
1763 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1764 
////  counter                                                     ////
1765 
////                                                              ////
1766 
////  To Do:                                                      ////
1767 
////   - add LFSR with more taps                                  ////
1768 
////                                                              ////
1769 
////  Author(s):                                                  ////
1770 
////      - Michael Unneback, unneback@opencores.org              ////
1771 
////        ORSoC AB                                              ////
1772 
////                                                              ////
1773 
//////////////////////////////////////////////////////////////////////
1774 
////                                                              ////
1775 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1776 
////                                                              ////
1777 
//// This source file may be used and distributed without         ////
1778 
//// restriction provided that this copyright statement is not    ////
1779 
//// removed from the file and that any derivative work contains  ////
1780 
//// the original copyright notice and the associated disclaimer. ////
1781 
////                                                              ////
1782 
//// This source file is free software; you can redistribute it   ////
1783 
//// and/or modify it under the terms of the GNU Lesser General   ////
1784 
//// Public License as published by the Free Software Foundation; ////
1785 
//// either version 2.1 of the License, or (at your option) any   ////
1786 
//// later version.                                               ////
1787 
////                                                              ////
1788 
//// This source is distributed in the hope that it will be       ////
1789 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1790 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1791 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1792 
//// details.                                                     ////
1793 
////                                                              ////
1794 
//// You should have received a copy of the GNU Lesser General    ////
1795 
//// Public License along with this source; if not, download it   ////
1796 
//// from http://www.opencores.org/lgpl.shtml                     ////
1797 
////                                                              ////
1798 
//////////////////////////////////////////////////////////////////////
1799 
 
1800 
// binary counter
1801 6 unneback 
 
1802 40 unneback 
`define MODULE cnt_bin_ce
1803 
module `BASE`MODULE (
1804 
`undef MODULE
1805 
 cke, q, rst, clk);
1806 
 
1807 6 unneback 
   parameter length = 4;
1808 
   input cke;
1809 
   output [length:1] q;
1810 
   input rst;
1811 
   input clk;
1812 
 
1813 
   parameter clear_value = 0;
1814 
   parameter set_value = 1;
1815 
   parameter wrap_value = 0;
1816 
   parameter level1_value = 15;
1817 
 
1818 
   reg  [length:1] qi;
1819 
   wire [length:1] q_next;
1820 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1821 
 
1822 
   always @ (posedge clk or posedge rst)
1823 
     if (rst)
1824 
       qi <= {length{1'b0}};
1825 
     else
1826 
     if (cke)
1827 
       qi <= q_next;
1828 
 
1829 
   assign q = qi;
1830 
 
1831 
endmodule
1832 40 unneback 
`endif
1833 
`ifdef CNT_BIN_CE_CLEAR
1834 6 unneback 
//////////////////////////////////////////////////////////////////////
1835 
////                                                              ////
1836 
////  Versatile counter                                           ////
1837 
////                                                              ////
1838 
////  Description                                                 ////
1839 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1840 
////  counter                                                     ////
1841 
////                                                              ////
1842 
////  To Do:                                                      ////
1843 
////   - add LFSR with more taps                                  ////
1844 
////                                                              ////
1845 
////  Author(s):                                                  ////
1846 
////      - Michael Unneback, unneback@opencores.org              ////
1847 
////        ORSoC AB                                              ////
1848 
////                                                              ////
1849 
//////////////////////////////////////////////////////////////////////
1850 
////                                                              ////
1851 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1852 
////                                                              ////
1853 
//// This source file may be used and distributed without         ////
1854 
//// restriction provided that this copyright statement is not    ////
1855 
//// removed from the file and that any derivative work contains  ////
1856 
//// the original copyright notice and the associated disclaimer. ////
1857 
////                                                              ////
1858 
//// This source file is free software; you can redistribute it   ////
1859 
//// and/or modify it under the terms of the GNU Lesser General   ////
1860 
//// Public License as published by the Free Software Foundation; ////
1861 
//// either version 2.1 of the License, or (at your option) any   ////
1862 
//// later version.                                               ////
1863 
////                                                              ////
1864 
//// This source is distributed in the hope that it will be       ////
1865 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1866 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1867 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1868 
//// details.                                                     ////
1869 
////                                                              ////
1870 
//// You should have received a copy of the GNU Lesser General    ////
1871 
//// Public License along with this source; if not, download it   ////
1872 
//// from http://www.opencores.org/lgpl.shtml                     ////
1873 
////                                                              ////
1874 
//////////////////////////////////////////////////////////////////////
1875 
 
1876 
// binary counter
1877 
 
1878 40 unneback 
`define MODULE cnt_bin_ce_clear
1879 
module `BASE`MODULE (
1880 
`undef MODULE
1881 
 clear, cke, q, rst, clk);
1882 
 
1883 6 unneback 
   parameter length = 4;
1884 
   input clear;
1885 
   input cke;
1886 
   output [length:1] q;
1887 
   input rst;
1888 
   input clk;
1889 
 
1890 
   parameter clear_value = 0;
1891 
   parameter set_value = 1;
1892 
   parameter wrap_value = 0;
1893 
   parameter level1_value = 15;
1894 
 
1895 
   reg  [length:1] qi;
1896 
   wire [length:1] q_next;
1897 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1898 
 
1899 
   always @ (posedge clk or posedge rst)
1900 
     if (rst)
1901 
       qi <= {length{1'b0}};
1902 
     else
1903 
     if (cke)
1904 
       qi <= q_next;
1905 
 
1906 
   assign q = qi;
1907 
 
1908 
endmodule
1909 40 unneback 
`endif
1910 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1911 6 unneback 
//////////////////////////////////////////////////////////////////////
1912 
////                                                              ////
1913 
////  Versatile counter                                           ////
1914 
////                                                              ////
1915 
////  Description                                                 ////
1916 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1917 
////  counter                                                     ////
1918 
////                                                              ////
1919 
////  To Do:                                                      ////
1920 
////   - add LFSR with more taps                                  ////
1921 
////                                                              ////
1922 
////  Author(s):                                                  ////
1923 
////      - Michael Unneback, unneback@opencores.org              ////
1924 
////        ORSoC AB                                              ////
1925 
////                                                              ////
1926 
//////////////////////////////////////////////////////////////////////
1927 
////                                                              ////
1928 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1929 
////                                                              ////
1930 
//// This source file may be used and distributed without         ////
1931 
//// restriction provided that this copyright statement is not    ////
1932 
//// removed from the file and that any derivative work contains  ////
1933 
//// the original copyright notice and the associated disclaimer. ////
1934 
////                                                              ////
1935 
//// This source file is free software; you can redistribute it   ////
1936 
//// and/or modify it under the terms of the GNU Lesser General   ////
1937 
//// Public License as published by the Free Software Foundation; ////
1938 
//// either version 2.1 of the License, or (at your option) any   ////
1939 
//// later version.                                               ////
1940 
////                                                              ////
1941 
//// This source is distributed in the hope that it will be       ////
1942 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1943 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1944 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1945 
//// details.                                                     ////
1946 
////                                                              ////
1947 
//// You should have received a copy of the GNU Lesser General    ////
1948 
//// Public License along with this source; if not, download it   ////
1949 
//// from http://www.opencores.org/lgpl.shtml                     ////
1950 
////                                                              ////
1951 
//////////////////////////////////////////////////////////////////////
1952 
 
1953 
// binary counter
1954 29 unneback 
 
1955 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1956 
module `BASE`MODULE (
1957 
`undef MODULE
1958 
 clear, cke, q, level1, level2, rst, clk);
1959 
 
1960 29 unneback 
   parameter length = 4;
1961 
   input clear;
1962 
   input cke;
1963 
   output [length:1] q;
1964 
   output reg level1;
1965 
   output reg level2;
1966 
   input rst;
1967 
   input clk;
1968 
 
1969 
   parameter clear_value = 0;
1970 
   parameter set_value = 1;
1971 30 unneback 
   parameter wrap_value = 15;
1972 
   parameter level1_value = 8;
1973 
   parameter level2_value = 15;
1974 29 unneback 
 
1975 
   wire rew;
1976 30 unneback 
   assign rew = 1'b0;
1977 29 unneback 
   reg  [length:1] qi;
1978 
   wire [length:1] q_next;
1979 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1980 
 
1981 
   always @ (posedge clk or posedge rst)
1982 
     if (rst)
1983 
       qi <= {length{1'b0}};
1984 
     else
1985 
     if (cke)
1986 
       qi <= q_next;
1987 
 
1988 
   assign q = qi;
1989 
 
1990 
 
1991 
    always @ (posedge clk or posedge rst)
1992 
    if (rst)
1993 
        level1 <= 1'b0;
1994 
    else
1995 
    if (cke)
1996 
    if (clear)
1997 
        level1 <= 1'b0;
1998 
    else if (q_next == level1_value)
1999 
        level1 <= 1'b1;
2000 
    else if (qi == level1_value & rew)
2001 
        level1 <= 1'b0;
2002 
 
2003 
    always @ (posedge clk or posedge rst)
2004 
    if (rst)
2005 
        level2 <= 1'b0;
2006 
    else
2007 
    if (cke)
2008 
    if (clear)
2009 
        level2 <= 1'b0;
2010 
    else if (q_next == level2_value)
2011 
        level2 <= 1'b1;
2012 
    else if (qi == level2_value & rew)
2013 
        level2 <= 1'b0;
2014 
endmodule
2015 40 unneback 
`endif
2016 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2017 29 unneback 
//////////////////////////////////////////////////////////////////////
2018 
////                                                              ////
2019 
////  Versatile counter                                           ////
2020 
////                                                              ////
2021 
////  Description                                                 ////
2022 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2023 
////  counter                                                     ////
2024 
////                                                              ////
2025 
////  To Do:                                                      ////
2026 
////   - add LFSR with more taps                                  ////
2027 
////                                                              ////
2028 
////  Author(s):                                                  ////
2029 
////      - Michael Unneback, unneback@opencores.org              ////
2030 
////        ORSoC AB                                              ////
2031 
////                                                              ////
2032 
//////////////////////////////////////////////////////////////////////
2033 
////                                                              ////
2034 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2035 
////                                                              ////
2036 
//// This source file may be used and distributed without         ////
2037 
//// restriction provided that this copyright statement is not    ////
2038 
//// removed from the file and that any derivative work contains  ////
2039 
//// the original copyright notice and the associated disclaimer. ////
2040 
////                                                              ////
2041 
//// This source file is free software; you can redistribute it   ////
2042 
//// and/or modify it under the terms of the GNU Lesser General   ////
2043 
//// Public License as published by the Free Software Foundation; ////
2044 
//// either version 2.1 of the License, or (at your option) any   ////
2045 
//// later version.                                               ////
2046 
////                                                              ////
2047 
//// This source is distributed in the hope that it will be       ////
2048 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2049 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2050 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2051 
//// details.                                                     ////
2052 
////                                                              ////
2053 
//// You should have received a copy of the GNU Lesser General    ////
2054 
//// Public License along with this source; if not, download it   ////
2055 
//// from http://www.opencores.org/lgpl.shtml                     ////
2056 
////                                                              ////
2057 
//////////////////////////////////////////////////////////////////////
2058 
 
2059 
// binary counter
2060 6 unneback 
 
2061 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
2062 
module `BASE`MODULE (
2063 
`undef MODULE
2064 
 clear, set, cke, rew, q, rst, clk);
2065 
 
2066 6 unneback 
   parameter length = 4;
2067 
   input clear;
2068 
   input set;
2069 
   input cke;
2070 
   input rew;
2071 
   output [length:1] q;
2072 
   input rst;
2073 
   input clk;
2074 
 
2075 
   parameter clear_value = 0;
2076 
   parameter set_value = 1;
2077 
   parameter wrap_value = 0;
2078 
   parameter level1_value = 15;
2079 
 
2080 
   reg  [length:1] qi;
2081 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2082 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2083 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2084 
   assign q_next = rew ? q_next_rew : q_next_fw;
2085 
 
2086 
   always @ (posedge clk or posedge rst)
2087 
     if (rst)
2088 
       qi <= {length{1'b0}};
2089 
     else
2090 
     if (cke)
2091 
       qi <= q_next;
2092 
 
2093 
   assign q = qi;
2094 
 
2095 
endmodule
2096 40 unneback 
`endif
2097 
`ifdef CNT_BIN_CE_REW_L1
2098 6 unneback 
//////////////////////////////////////////////////////////////////////
2099 
////                                                              ////
2100 
////  Versatile counter                                           ////
2101 
////                                                              ////
2102 
////  Description                                                 ////
2103 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2104 
////  counter                                                     ////
2105 
////                                                              ////
2106 
////  To Do:                                                      ////
2107 
////   - add LFSR with more taps                                  ////
2108 
////                                                              ////
2109 
////  Author(s):                                                  ////
2110 
////      - Michael Unneback, unneback@opencores.org              ////
2111 
////        ORSoC AB                                              ////
2112 
////                                                              ////
2113 
//////////////////////////////////////////////////////////////////////
2114 
////                                                              ////
2115 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2116 
////                                                              ////
2117 
//// This source file may be used and distributed without         ////
2118 
//// restriction provided that this copyright statement is not    ////
2119 
//// removed from the file and that any derivative work contains  ////
2120 
//// the original copyright notice and the associated disclaimer. ////
2121 
////                                                              ////
2122 
//// This source file is free software; you can redistribute it   ////
2123 
//// and/or modify it under the terms of the GNU Lesser General   ////
2124 
//// Public License as published by the Free Software Foundation; ////
2125 
//// either version 2.1 of the License, or (at your option) any   ////
2126 
//// later version.                                               ////
2127 
////                                                              ////
2128 
//// This source is distributed in the hope that it will be       ////
2129 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2130 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2131 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2132 
//// details.                                                     ////
2133 
////                                                              ////
2134 
//// You should have received a copy of the GNU Lesser General    ////
2135 
//// Public License along with this source; if not, download it   ////
2136 
//// from http://www.opencores.org/lgpl.shtml                     ////
2137 
////                                                              ////
2138 
//////////////////////////////////////////////////////////////////////
2139 
 
2140 
// binary counter
2141 
 
2142 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
2143 
module `BASE`MODULE (
2144 
`undef MODULE
2145 
 cke, rew, level1, rst, clk);
2146 
 
2147 6 unneback 
   parameter length = 4;
2148 
   input cke;
2149 
   input rew;
2150 
   output reg level1;
2151 
   input rst;
2152 
   input clk;
2153 
 
2154 
   parameter clear_value = 0;
2155 
   parameter set_value = 1;
2156 
   parameter wrap_value = 1;
2157 
   parameter level1_value = 15;
2158 
 
2159 29 unneback 
   wire clear;
2160 30 unneback 
   assign clear = 1'b0;
2161 6 unneback 
   reg  [length:1] qi;
2162 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2163 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2164 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2165 
   assign q_next = rew ? q_next_rew : q_next_fw;
2166 
 
2167 
   always @ (posedge clk or posedge rst)
2168 
     if (rst)
2169 
       qi <= {length{1'b0}};
2170 
     else
2171 
     if (cke)
2172 
       qi <= q_next;
2173 
 
2174 
 
2175 
 
2176 
    always @ (posedge clk or posedge rst)
2177 
    if (rst)
2178 
        level1 <= 1'b0;
2179 
    else
2180 
    if (cke)
2181 29 unneback 
    if (clear)
2182 
        level1 <= 1'b0;
2183 
    else if (q_next == level1_value)
2184 6 unneback 
        level1 <= 1'b1;
2185 
    else if (qi == level1_value & rew)
2186 
        level1 <= 1'b0;
2187 
endmodule
2188 40 unneback 
`endif
2189 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2190 6 unneback 
//////////////////////////////////////////////////////////////////////
2191 
////                                                              ////
2192 
////  Versatile counter                                           ////
2193 
////                                                              ////
2194 
////  Description                                                 ////
2195 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2196 
////  counter                                                     ////
2197 
////                                                              ////
2198 
////  To Do:                                                      ////
2199 
////   - add LFSR with more taps                                  ////
2200 
////                                                              ////
2201 
////  Author(s):                                                  ////
2202 
////      - Michael Unneback, unneback@opencores.org              ////
2203 
////        ORSoC AB                                              ////
2204 
////                                                              ////
2205 
//////////////////////////////////////////////////////////////////////
2206 
////                                                              ////
2207 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2208 
////                                                              ////
2209 
//// This source file may be used and distributed without         ////
2210 
//// restriction provided that this copyright statement is not    ////
2211 
//// removed from the file and that any derivative work contains  ////
2212 
//// the original copyright notice and the associated disclaimer. ////
2213 
////                                                              ////
2214 
//// This source file is free software; you can redistribute it   ////
2215 
//// and/or modify it under the terms of the GNU Lesser General   ////
2216 
//// Public License as published by the Free Software Foundation; ////
2217 
//// either version 2.1 of the License, or (at your option) any   ////
2218 
//// later version.                                               ////
2219 
////                                                              ////
2220 
//// This source is distributed in the hope that it will be       ////
2221 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2222 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2223 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2224 
//// details.                                                     ////
2225 
////                                                              ////
2226 
//// You should have received a copy of the GNU Lesser General    ////
2227 
//// Public License along with this source; if not, download it   ////
2228 
//// from http://www.opencores.org/lgpl.shtml                     ////
2229 
////                                                              ////
2230 
//////////////////////////////////////////////////////////////////////
2231 
 
2232 25 unneback 
// binary counter
2233 
 
2234 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2235 
module `BASE`MODULE (
2236 
`undef MODULE
2237 
 cke, rew, zq, level1, rst, clk);
2238 
 
2239 25 unneback 
   parameter length = 4;
2240 
   input cke;
2241 
   input rew;
2242 
   output reg zq;
2243 
   output reg level1;
2244 
   input rst;
2245 
   input clk;
2246 
 
2247 
   parameter clear_value = 0;
2248 
   parameter set_value = 1;
2249 
   parameter wrap_value = 1;
2250 
   parameter level1_value = 15;
2251 
 
2252 29 unneback 
   wire clear;
2253 30 unneback 
   assign clear = 1'b0;
2254 25 unneback 
   reg  [length:1] qi;
2255 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2256 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2257 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2258 
   assign q_next = rew ? q_next_rew : q_next_fw;
2259 
 
2260 
   always @ (posedge clk or posedge rst)
2261 
     if (rst)
2262 
       qi <= {length{1'b0}};
2263 
     else
2264 
     if (cke)
2265 
       qi <= q_next;
2266 
 
2267 
 
2268 
 
2269 
   always @ (posedge clk or posedge rst)
2270 
     if (rst)
2271 
       zq <= 1'b1;
2272 
     else
2273 
     if (cke)
2274 
       zq <= q_next == {length{1'b0}};
2275 
 
2276 
    always @ (posedge clk or posedge rst)
2277 
    if (rst)
2278 
        level1 <= 1'b0;
2279 
    else
2280 
    if (cke)
2281 29 unneback 
    if (clear)
2282 
        level1 <= 1'b0;
2283 
    else if (q_next == level1_value)
2284 25 unneback 
        level1 <= 1'b1;
2285 
    else if (qi == level1_value & rew)
2286 
        level1 <= 1'b0;
2287 
endmodule
2288 40 unneback 
`endif
2289 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2290 25 unneback 
//////////////////////////////////////////////////////////////////////
2291 
////                                                              ////
2292 
////  Versatile counter                                           ////
2293 
////                                                              ////
2294 
////  Description                                                 ////
2295 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2296 
////  counter                                                     ////
2297 
////                                                              ////
2298 
////  To Do:                                                      ////
2299 
////   - add LFSR with more taps                                  ////
2300 
////                                                              ////
2301 
////  Author(s):                                                  ////
2302 
////      - Michael Unneback, unneback@opencores.org              ////
2303 
////        ORSoC AB                                              ////
2304 
////                                                              ////
2305 
//////////////////////////////////////////////////////////////////////
2306 
////                                                              ////
2307 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2308 
////                                                              ////
2309 
//// This source file may be used and distributed without         ////
2310 
//// restriction provided that this copyright statement is not    ////
2311 
//// removed from the file and that any derivative work contains  ////
2312 
//// the original copyright notice and the associated disclaimer. ////
2313 
////                                                              ////
2314 
//// This source file is free software; you can redistribute it   ////
2315 
//// and/or modify it under the terms of the GNU Lesser General   ////
2316 
//// Public License as published by the Free Software Foundation; ////
2317 
//// either version 2.1 of the License, or (at your option) any   ////
2318 
//// later version.                                               ////
2319 
////                                                              ////
2320 
//// This source is distributed in the hope that it will be       ////
2321 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2322 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2323 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2324 
//// details.                                                     ////
2325 
////                                                              ////
2326 
//// You should have received a copy of the GNU Lesser General    ////
2327 
//// Public License along with this source; if not, download it   ////
2328 
//// from http://www.opencores.org/lgpl.shtml                     ////
2329 
////                                                              ////
2330 
//////////////////////////////////////////////////////////////////////
2331 
 
2332 
// binary counter
2333 
 
2334 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2335 
module `BASE`MODULE (
2336 
`undef MODULE
2337 
 cke, rew, q, zq, level1, rst, clk);
2338 
 
2339 25 unneback 
   parameter length = 4;
2340 
   input cke;
2341 
   input rew;
2342 
   output [length:1] q;
2343 
   output reg zq;
2344 
   output reg level1;
2345 
   input rst;
2346 
   input clk;
2347 
 
2348 
   parameter clear_value = 0;
2349 
   parameter set_value = 1;
2350 
   parameter wrap_value = 1;
2351 
   parameter level1_value = 15;
2352 
 
2353 29 unneback 
   wire clear;
2354 30 unneback 
   assign clear = 1'b0;
2355 25 unneback 
   reg  [length:1] qi;
2356 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2357 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2358 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2359 
   assign q_next = rew ? q_next_rew : q_next_fw;
2360 
 
2361 
   always @ (posedge clk or posedge rst)
2362 
     if (rst)
2363 
       qi <= {length{1'b0}};
2364 
     else
2365 
     if (cke)
2366 
       qi <= q_next;
2367 
 
2368 
   assign q = qi;
2369 
 
2370 
 
2371 
   always @ (posedge clk or posedge rst)
2372 
     if (rst)
2373 
       zq <= 1'b1;
2374 
     else
2375 
     if (cke)
2376 
       zq <= q_next == {length{1'b0}};
2377 
 
2378 
    always @ (posedge clk or posedge rst)
2379 
    if (rst)
2380 
        level1 <= 1'b0;
2381 
    else
2382 
    if (cke)
2383 29 unneback 
    if (clear)
2384 
        level1 <= 1'b0;
2385 
    else if (q_next == level1_value)
2386 25 unneback 
        level1 <= 1'b1;
2387 
    else if (qi == level1_value & rew)
2388 
        level1 <= 1'b0;
2389 
endmodule
2390 40 unneback 
`endif
2391 
`ifdef CNT_LFSR_ZQ
2392 25 unneback 
//////////////////////////////////////////////////////////////////////
2393 
////                                                              ////
2394 
////  Versatile counter                                           ////
2395 
////                                                              ////
2396 
////  Description                                                 ////
2397 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2398 
////  counter                                                     ////
2399 
////                                                              ////
2400 
////  To Do:                                                      ////
2401 
////   - add LFSR with more taps                                  ////
2402 
////                                                              ////
2403 
////  Author(s):                                                  ////
2404 
////      - Michael Unneback, unneback@opencores.org              ////
2405 
////        ORSoC AB                                              ////
2406 
////                                                              ////
2407 
//////////////////////////////////////////////////////////////////////
2408 
////                                                              ////
2409 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2410 
////                                                              ////
2411 
//// This source file may be used and distributed without         ////
2412 
//// restriction provided that this copyright statement is not    ////
2413 
//// removed from the file and that any derivative work contains  ////
2414 
//// the original copyright notice and the associated disclaimer. ////
2415 
////                                                              ////
2416 
//// This source file is free software; you can redistribute it   ////
2417 
//// and/or modify it under the terms of the GNU Lesser General   ////
2418 
//// Public License as published by the Free Software Foundation; ////
2419 
//// either version 2.1 of the License, or (at your option) any   ////
2420 
//// later version.                                               ////
2421 
////                                                              ////
2422 
//// This source is distributed in the hope that it will be       ////
2423 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2424 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2425 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2426 
//// details.                                                     ////
2427 
////                                                              ////
2428 
//// You should have received a copy of the GNU Lesser General    ////
2429 
//// Public License along with this source; if not, download it   ////
2430 
//// from http://www.opencores.org/lgpl.shtml                     ////
2431 
////                                                              ////
2432 
//////////////////////////////////////////////////////////////////////
2433 
 
2434 6 unneback 
// LFSR counter
2435 
 
2436 40 unneback 
`define MODULE cnt_lfsr_zq
2437 
module `BASE`MODULE (
2438 
`undef MODULE
2439 
 zq, rst, clk);
2440 
 
2441 6 unneback 
   parameter length = 4;
2442 
   output reg zq;
2443 
   input rst;
2444 
   input clk;
2445 
 
2446 
   parameter clear_value = 0;
2447 
   parameter set_value = 1;
2448 
   parameter wrap_value = 8;
2449 
   parameter level1_value = 15;
2450 
 
2451 
   reg  [length:1] qi;
2452 
   reg lfsr_fb;
2453 
   wire [length:1] q_next;
2454 
   reg [32:1] polynom;
2455 
   integer i;
2456 
 
2457 
   always @ (qi)
2458 
   begin
2459 
        case (length)
2460 
         2: polynom = 32'b11;                               // 0x3
2461 
         3: polynom = 32'b110;                              // 0x6
2462 
         4: polynom = 32'b1100;                             // 0xC
2463 
         5: polynom = 32'b10100;                            // 0x14
2464 
         6: polynom = 32'b110000;                           // 0x30
2465 
         7: polynom = 32'b1100000;                          // 0x60
2466 
         8: polynom = 32'b10111000;                         // 0xb8
2467 
         9: polynom = 32'b100010000;                        // 0x110
2468 
        10: polynom = 32'b1001000000;                       // 0x240
2469 
        11: polynom = 32'b10100000000;                      // 0x500
2470 
        12: polynom = 32'b100000101001;                     // 0x829
2471 
        13: polynom = 32'b1000000001100;                    // 0x100C
2472 
        14: polynom = 32'b10000000010101;                   // 0x2015
2473 
        15: polynom = 32'b110000000000000;                  // 0x6000
2474 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2475 
        17: polynom = 32'b10010000000000000;                // 0x12000
2476 
        18: polynom = 32'b100000010000000000;               // 0x20400
2477 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2478 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2479 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2480 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2481 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2482 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2483 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2484 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2485 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2486 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2487 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2488 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2489 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2490 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2491 
        default: polynom = 32'b0;
2492 
        endcase
2493 
        lfsr_fb = qi[length];
2494 
        for (i=length-1; i>=1; i=i-1) begin
2495 
            if (polynom[i])
2496 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2497 
        end
2498 
    end
2499 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2500 
 
2501 
   always @ (posedge clk or posedge rst)
2502 
     if (rst)
2503 
       qi <= {length{1'b0}};
2504 
     else
2505 
       qi <= q_next;
2506 
 
2507 
 
2508 
 
2509 
   always @ (posedge clk or posedge rst)
2510 
     if (rst)
2511 
       zq <= 1'b1;
2512 
     else
2513 
       zq <= q_next == {length{1'b0}};
2514 
endmodule
2515 40 unneback 
`endif
2516 75 unneback 
`ifdef CNT_LFSR_CE
2517 
//////////////////////////////////////////////////////////////////////
2518 
////                                                              ////
2519 
////  Versatile counter                                           ////
2520 
////                                                              ////
2521 
////  Description                                                 ////
2522 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2523 
////  counter                                                     ////
2524 
////                                                              ////
2525 
////  To Do:                                                      ////
2526 
////   - add LFSR with more taps                                  ////
2527 
////                                                              ////
2528 
////  Author(s):                                                  ////
2529 
////      - Michael Unneback, unneback@opencores.org              ////
2530 
////        ORSoC AB                                              ////
2531 
////                                                              ////
2532 
//////////////////////////////////////////////////////////////////////
2533 
////                                                              ////
2534 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2535 
////                                                              ////
2536 
//// This source file may be used and distributed without         ////
2537 
//// restriction provided that this copyright statement is not    ////
2538 
//// removed from the file and that any derivative work contains  ////
2539 
//// the original copyright notice and the associated disclaimer. ////
2540 
////                                                              ////
2541 
//// This source file is free software; you can redistribute it   ////
2542 
//// and/or modify it under the terms of the GNU Lesser General   ////
2543 
//// Public License as published by the Free Software Foundation; ////
2544 
//// either version 2.1 of the License, or (at your option) any   ////
2545 
//// later version.                                               ////
2546 
////                                                              ////
2547 
//// This source is distributed in the hope that it will be       ////
2548 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2549 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2550 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2551 
//// details.                                                     ////
2552 
////                                                              ////
2553 
//// You should have received a copy of the GNU Lesser General    ////
2554 
//// Public License along with this source; if not, download it   ////
2555 
//// from http://www.opencores.org/lgpl.shtml                     ////
2556 
////                                                              ////
2557 
//////////////////////////////////////////////////////////////////////
2558 
 
2559 
// LFSR counter
2560 
 
2561 
`define MODULE cnt_lfsr_ce
2562 
module `BASE`MODULE (
2563 
`undef MODULE
2564 
 cke, zq, rst, clk);
2565 
 
2566 
   parameter length = 4;
2567 
   input cke;
2568 
   output reg zq;
2569 
   input rst;
2570 
   input clk;
2571 
 
2572 
   parameter clear_value = 0;
2573 
   parameter set_value = 1;
2574 
   parameter wrap_value = 0;
2575 
   parameter level1_value = 15;
2576 
 
2577 
   reg  [length:1] qi;
2578 
   reg lfsr_fb;
2579 
   wire [length:1] q_next;
2580 
   reg [32:1] polynom;
2581 
   integer i;
2582 
 
2583 
   always @ (qi)
2584 
   begin
2585 
        case (length)
2586 
         2: polynom = 32'b11;                               // 0x3
2587 
         3: polynom = 32'b110;                              // 0x6
2588 
         4: polynom = 32'b1100;                             // 0xC
2589 
         5: polynom = 32'b10100;                            // 0x14
2590 
         6: polynom = 32'b110000;                           // 0x30
2591 
         7: polynom = 32'b1100000;                          // 0x60
2592 
         8: polynom = 32'b10111000;                         // 0xb8
2593 
         9: polynom = 32'b100010000;                        // 0x110
2594 
        10: polynom = 32'b1001000000;                       // 0x240
2595 
        11: polynom = 32'b10100000000;                      // 0x500
2596 
        12: polynom = 32'b100000101001;                     // 0x829
2597 
        13: polynom = 32'b1000000001100;                    // 0x100C
2598 
        14: polynom = 32'b10000000010101;                   // 0x2015
2599 
        15: polynom = 32'b110000000000000;                  // 0x6000
2600 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2601 
        17: polynom = 32'b10010000000000000;                // 0x12000
2602 
        18: polynom = 32'b100000010000000000;               // 0x20400
2603 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2604 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2605 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2606 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2607 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2608 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2609 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2610 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2611 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2612 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2613 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2614 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2615 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2616 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2617 
        default: polynom = 32'b0;
2618 
        endcase
2619 
        lfsr_fb = qi[length];
2620 
        for (i=length-1; i>=1; i=i-1) begin
2621 
            if (polynom[i])
2622 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2623 
        end
2624 
    end
2625 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2626 
 
2627 
   always @ (posedge clk or posedge rst)
2628 
     if (rst)
2629 
       qi <= {length{1'b0}};
2630 
     else
2631 
     if (cke)
2632 
       qi <= q_next;
2633 
 
2634 
 
2635 
 
2636 
   always @ (posedge clk or posedge rst)
2637 
     if (rst)
2638 
       zq <= 1'b1;
2639 
     else
2640 
     if (cke)
2641 
       zq <= q_next == {length{1'b0}};
2642 
endmodule
2643 
`endif
2644 40 unneback 
`ifdef CNT_LFSR_CE_ZQ
2645 6 unneback 
//////////////////////////////////////////////////////////////////////
2646 
////                                                              ////
2647 
////  Versatile counter                                           ////
2648 
////                                                              ////
2649 
////  Description                                                 ////
2650 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2651 
////  counter                                                     ////
2652 
////                                                              ////
2653 
////  To Do:                                                      ////
2654 
////   - add LFSR with more taps                                  ////
2655 
////                                                              ////
2656 
////  Author(s):                                                  ////
2657 
////      - Michael Unneback, unneback@opencores.org              ////
2658 
////        ORSoC AB                                              ////
2659 
////                                                              ////
2660 
//////////////////////////////////////////////////////////////////////
2661 
////                                                              ////
2662 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2663 
////                                                              ////
2664 
//// This source file may be used and distributed without         ////
2665 
//// restriction provided that this copyright statement is not    ////
2666 
//// removed from the file and that any derivative work contains  ////
2667 
//// the original copyright notice and the associated disclaimer. ////
2668 
////                                                              ////
2669 
//// This source file is free software; you can redistribute it   ////
2670 
//// and/or modify it under the terms of the GNU Lesser General   ////
2671 
//// Public License as published by the Free Software Foundation; ////
2672 
//// either version 2.1 of the License, or (at your option) any   ////
2673 
//// later version.                                               ////
2674 
////                                                              ////
2675 
//// This source is distributed in the hope that it will be       ////
2676 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2677 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2678 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2679 
//// details.                                                     ////
2680 
////                                                              ////
2681 
//// You should have received a copy of the GNU Lesser General    ////
2682 
//// Public License along with this source; if not, download it   ////
2683 
//// from http://www.opencores.org/lgpl.shtml                     ////
2684 
////                                                              ////
2685 
//////////////////////////////////////////////////////////////////////
2686 
 
2687 
// LFSR counter
2688 
 
2689 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2690 
module `BASE`MODULE (
2691 
`undef MODULE
2692 
 cke, zq, rst, clk);
2693 
 
2694 6 unneback 
   parameter length = 4;
2695 
   input cke;
2696 
   output reg zq;
2697 
   input rst;
2698 
   input clk;
2699 
 
2700 
   parameter clear_value = 0;
2701 
   parameter set_value = 1;
2702 
   parameter wrap_value = 8;
2703 
   parameter level1_value = 15;
2704 
 
2705 
   reg  [length:1] qi;
2706 
   reg lfsr_fb;
2707 
   wire [length:1] q_next;
2708 
   reg [32:1] polynom;
2709 
   integer i;
2710 
 
2711 
   always @ (qi)
2712 
   begin
2713 
        case (length)
2714 
         2: polynom = 32'b11;                               // 0x3
2715 
         3: polynom = 32'b110;                              // 0x6
2716 
         4: polynom = 32'b1100;                             // 0xC
2717 
         5: polynom = 32'b10100;                            // 0x14
2718 
         6: polynom = 32'b110000;                           // 0x30
2719 
         7: polynom = 32'b1100000;                          // 0x60
2720 
         8: polynom = 32'b10111000;                         // 0xb8
2721 
         9: polynom = 32'b100010000;                        // 0x110
2722 
        10: polynom = 32'b1001000000;                       // 0x240
2723 
        11: polynom = 32'b10100000000;                      // 0x500
2724 
        12: polynom = 32'b100000101001;                     // 0x829
2725 
        13: polynom = 32'b1000000001100;                    // 0x100C
2726 
        14: polynom = 32'b10000000010101;                   // 0x2015
2727 
        15: polynom = 32'b110000000000000;                  // 0x6000
2728 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2729 
        17: polynom = 32'b10010000000000000;                // 0x12000
2730 
        18: polynom = 32'b100000010000000000;               // 0x20400
2731 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2732 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2733 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2734 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2735 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2736 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2737 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2738 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2739 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2740 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2741 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2742 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2743 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2744 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2745 
        default: polynom = 32'b0;
2746 
        endcase
2747 
        lfsr_fb = qi[length];
2748 
        for (i=length-1; i>=1; i=i-1) begin
2749 
            if (polynom[i])
2750 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2751 
        end
2752 
    end
2753 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2754 
 
2755 
   always @ (posedge clk or posedge rst)
2756 
     if (rst)
2757 
       qi <= {length{1'b0}};
2758 
     else
2759 
     if (cke)
2760 
       qi <= q_next;
2761 
 
2762 
 
2763 
 
2764 
   always @ (posedge clk or posedge rst)
2765 
     if (rst)
2766 
       zq <= 1'b1;
2767 
     else
2768 
     if (cke)
2769 
       zq <= q_next == {length{1'b0}};
2770 
endmodule
2771 40 unneback 
`endif
2772 
`ifdef CNT_LFSR_CE_Q
2773 6 unneback 
//////////////////////////////////////////////////////////////////////
2774 
////                                                              ////
2775 
////  Versatile counter                                           ////
2776 
////                                                              ////
2777 
////  Description                                                 ////
2778 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2779 
////  counter                                                     ////
2780 
////                                                              ////
2781 
////  To Do:                                                      ////
2782 
////   - add LFSR with more taps                                  ////
2783 
////                                                              ////
2784 
////  Author(s):                                                  ////
2785 
////      - Michael Unneback, unneback@opencores.org              ////
2786 
////        ORSoC AB                                              ////
2787 
////                                                              ////
2788 
//////////////////////////////////////////////////////////////////////
2789 
////                                                              ////
2790 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2791 
////                                                              ////
2792 
//// This source file may be used and distributed without         ////
2793 
//// restriction provided that this copyright statement is not    ////
2794 
//// removed from the file and that any derivative work contains  ////
2795 
//// the original copyright notice and the associated disclaimer. ////
2796 
////                                                              ////
2797 
//// This source file is free software; you can redistribute it   ////
2798 
//// and/or modify it under the terms of the GNU Lesser General   ////
2799 
//// Public License as published by the Free Software Foundation; ////
2800 
//// either version 2.1 of the License, or (at your option) any   ////
2801 
//// later version.                                               ////
2802 
////                                                              ////
2803 
//// This source is distributed in the hope that it will be       ////
2804 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2805 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2806 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2807 
//// details.                                                     ////
2808 
////                                                              ////
2809 
//// You should have received a copy of the GNU Lesser General    ////
2810 
//// Public License along with this source; if not, download it   ////
2811 
//// from http://www.opencores.org/lgpl.shtml                     ////
2812 
////                                                              ////
2813 
//////////////////////////////////////////////////////////////////////
2814 22 unneback 
 
2815 
// LFSR counter
2816 27 unneback 
 
2817 40 unneback 
`define MODULE cnt_lfsr_ce_q
2818 
module `BASE`MODULE (
2819 
`undef MODULE
2820 
 cke, q, rst, clk);
2821 
 
2822 27 unneback 
   parameter length = 4;
2823 
   input cke;
2824 
   output [length:1] q;
2825 
   input rst;
2826 
   input clk;
2827 
 
2828 
   parameter clear_value = 0;
2829 
   parameter set_value = 1;
2830 
   parameter wrap_value = 8;
2831 
   parameter level1_value = 15;
2832 
 
2833 
   reg  [length:1] qi;
2834 
   reg lfsr_fb;
2835 
   wire [length:1] q_next;
2836 
   reg [32:1] polynom;
2837 
   integer i;
2838 
 
2839 
   always @ (qi)
2840 
   begin
2841 
        case (length)
2842 
         2: polynom = 32'b11;                               // 0x3
2843 
         3: polynom = 32'b110;                              // 0x6
2844 
         4: polynom = 32'b1100;                             // 0xC
2845 
         5: polynom = 32'b10100;                            // 0x14
2846 
         6: polynom = 32'b110000;                           // 0x30
2847 
         7: polynom = 32'b1100000;                          // 0x60
2848 
         8: polynom = 32'b10111000;                         // 0xb8
2849 
         9: polynom = 32'b100010000;                        // 0x110
2850 
        10: polynom = 32'b1001000000;                       // 0x240
2851 
        11: polynom = 32'b10100000000;                      // 0x500
2852 
        12: polynom = 32'b100000101001;                     // 0x829
2853 
        13: polynom = 32'b1000000001100;                    // 0x100C
2854 
        14: polynom = 32'b10000000010101;                   // 0x2015
2855 
        15: polynom = 32'b110000000000000;                  // 0x6000
2856 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2857 
        17: polynom = 32'b10010000000000000;                // 0x12000
2858 
        18: polynom = 32'b100000010000000000;               // 0x20400
2859 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2860 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2861 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2862 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2863 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2864 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2865 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2866 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2867 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2868 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2869 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2870 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2871 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2872 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2873 
        default: polynom = 32'b0;
2874 
        endcase
2875 
        lfsr_fb = qi[length];
2876 
        for (i=length-1; i>=1; i=i-1) begin
2877 
            if (polynom[i])
2878 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2879 
        end
2880 
    end
2881 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2882 
 
2883 
   always @ (posedge clk or posedge rst)
2884 
     if (rst)
2885 
       qi <= {length{1'b0}};
2886 
     else
2887 
     if (cke)
2888 
       qi <= q_next;
2889 
 
2890 
   assign q = qi;
2891 
 
2892 
endmodule
2893 40 unneback 
`endif
2894 
`ifdef CNT_LFSR_CE_CLEAR_Q
2895 27 unneback 
//////////////////////////////////////////////////////////////////////
2896 
////                                                              ////
2897 
////  Versatile counter                                           ////
2898 
////                                                              ////
2899 
////  Description                                                 ////
2900 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2901 
////  counter                                                     ////
2902 
////                                                              ////
2903 
////  To Do:                                                      ////
2904 
////   - add LFSR with more taps                                  ////
2905 
////                                                              ////
2906 
////  Author(s):                                                  ////
2907 
////      - Michael Unneback, unneback@opencores.org              ////
2908 
////        ORSoC AB                                              ////
2909 
////                                                              ////
2910 
//////////////////////////////////////////////////////////////////////
2911 
////                                                              ////
2912 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2913 
////                                                              ////
2914 
//// This source file may be used and distributed without         ////
2915 
//// restriction provided that this copyright statement is not    ////
2916 
//// removed from the file and that any derivative work contains  ////
2917 
//// the original copyright notice and the associated disclaimer. ////
2918 
////                                                              ////
2919 
//// This source file is free software; you can redistribute it   ////
2920 
//// and/or modify it under the terms of the GNU Lesser General   ////
2921 
//// Public License as published by the Free Software Foundation; ////
2922 
//// either version 2.1 of the License, or (at your option) any   ////
2923 
//// later version.                                               ////
2924 
////                                                              ////
2925 
//// This source is distributed in the hope that it will be       ////
2926 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2927 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2928 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2929 
//// details.                                                     ////
2930 
////                                                              ////
2931 
//// You should have received a copy of the GNU Lesser General    ////
2932 
//// Public License along with this source; if not, download it   ////
2933 
//// from http://www.opencores.org/lgpl.shtml                     ////
2934 
////                                                              ////
2935 
//////////////////////////////////////////////////////////////////////
2936 
 
2937 
// LFSR counter
2938 
 
2939 40 unneback 
`define MODULE cnt_lfsr_ce_clear_q
2940 
module `BASE`MODULE (
2941 
`undef MODULE
2942 
 clear, cke, q, rst, clk);
2943 
 
2944 27 unneback 
   parameter length = 4;
2945 
   input clear;
2946 
   input cke;
2947 
   output [length:1] q;
2948 
   input rst;
2949 
   input clk;
2950 
 
2951 
   parameter clear_value = 0;
2952 
   parameter set_value = 1;
2953 
   parameter wrap_value = 8;
2954 
   parameter level1_value = 15;
2955 
 
2956 
   reg  [length:1] qi;
2957 
   reg lfsr_fb;
2958 
   wire [length:1] q_next;
2959 
   reg [32:1] polynom;
2960 
   integer i;
2961 
 
2962 
   always @ (qi)
2963 
   begin
2964 
        case (length)
2965 
         2: polynom = 32'b11;                               // 0x3
2966 
         3: polynom = 32'b110;                              // 0x6
2967 
         4: polynom = 32'b1100;                             // 0xC
2968 
         5: polynom = 32'b10100;                            // 0x14
2969 
         6: polynom = 32'b110000;                           // 0x30
2970 
         7: polynom = 32'b1100000;                          // 0x60
2971 
         8: polynom = 32'b10111000;                         // 0xb8
2972 
         9: polynom = 32'b100010000;                        // 0x110
2973 
        10: polynom = 32'b1001000000;                       // 0x240
2974 
        11: polynom = 32'b10100000000;                      // 0x500
2975 
        12: polynom = 32'b100000101001;                     // 0x829
2976 
        13: polynom = 32'b1000000001100;                    // 0x100C
2977 
        14: polynom = 32'b10000000010101;                   // 0x2015
2978 
        15: polynom = 32'b110000000000000;                  // 0x6000
2979 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2980 
        17: polynom = 32'b10010000000000000;                // 0x12000
2981 
        18: polynom = 32'b100000010000000000;               // 0x20400
2982 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2983 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2984 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2985 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2986 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2987 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2988 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2989 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2990 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2991 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2992 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2993 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2994 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2995 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2996 
        default: polynom = 32'b0;
2997 
        endcase
2998 
        lfsr_fb = qi[length];
2999 
        for (i=length-1; i>=1; i=i-1) begin
3000 
            if (polynom[i])
3001 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3002 
        end
3003 
    end
3004 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3005 
 
3006 
   always @ (posedge clk or posedge rst)
3007 
     if (rst)
3008 
       qi <= {length{1'b0}};
3009 
     else
3010 
     if (cke)
3011 
       qi <= q_next;
3012 
 
3013 
   assign q = qi;
3014 
 
3015 
endmodule
3016 40 unneback 
`endif
3017 
`ifdef CNT_LFSR_CE_Q_ZQ
3018 27 unneback 
//////////////////////////////////////////////////////////////////////
3019 
////                                                              ////
3020 
////  Versatile counter                                           ////
3021 
////                                                              ////
3022 
////  Description                                                 ////
3023 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3024 
////  counter                                                     ////
3025 
////                                                              ////
3026 
////  To Do:                                                      ////
3027 
////   - add LFSR with more taps                                  ////
3028 
////                                                              ////
3029 
////  Author(s):                                                  ////
3030 
////      - Michael Unneback, unneback@opencores.org              ////
3031 
////        ORSoC AB                                              ////
3032 
////                                                              ////
3033 
//////////////////////////////////////////////////////////////////////
3034 
////                                                              ////
3035 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3036 
////                                                              ////
3037 
//// This source file may be used and distributed without         ////
3038 
//// restriction provided that this copyright statement is not    ////
3039 
//// removed from the file and that any derivative work contains  ////
3040 
//// the original copyright notice and the associated disclaimer. ////
3041 
////                                                              ////
3042 
//// This source file is free software; you can redistribute it   ////
3043 
//// and/or modify it under the terms of the GNU Lesser General   ////
3044 
//// Public License as published by the Free Software Foundation; ////
3045 
//// either version 2.1 of the License, or (at your option) any   ////
3046 
//// later version.                                               ////
3047 
////                                                              ////
3048 
//// This source is distributed in the hope that it will be       ////
3049 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3050 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3051 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3052 
//// details.                                                     ////
3053 
////                                                              ////
3054 
//// You should have received a copy of the GNU Lesser General    ////
3055 
//// Public License along with this source; if not, download it   ////
3056 
//// from http://www.opencores.org/lgpl.shtml                     ////
3057 
////                                                              ////
3058 
//////////////////////////////////////////////////////////////////////
3059 
 
3060 
// LFSR counter
3061 22 unneback 
 
3062 40 unneback 
`define MODULE cnt_lfsr_ce_q_zq
3063 
module `BASE`MODULE (
3064 
`undef MODULE
3065 
 cke, q, zq, rst, clk);
3066 
 
3067 22 unneback 
   parameter length = 4;
3068 
   input cke;
3069 
   output [length:1] q;
3070 
   output reg zq;
3071 
   input rst;
3072 
   input clk;
3073 
 
3074 
   parameter clear_value = 0;
3075 
   parameter set_value = 1;
3076 
   parameter wrap_value = 8;
3077 
   parameter level1_value = 15;
3078 
 
3079 
   reg  [length:1] qi;
3080 
   reg lfsr_fb;
3081 
   wire [length:1] q_next;
3082 
   reg [32:1] polynom;
3083 
   integer i;
3084 
 
3085 
   always @ (qi)
3086 
   begin
3087 
        case (length)
3088 
         2: polynom = 32'b11;                               // 0x3
3089 
         3: polynom = 32'b110;                              // 0x6
3090 
         4: polynom = 32'b1100;                             // 0xC
3091 
         5: polynom = 32'b10100;                            // 0x14
3092 
         6: polynom = 32'b110000;                           // 0x30
3093 
         7: polynom = 32'b1100000;                          // 0x60
3094 
         8: polynom = 32'b10111000;                         // 0xb8
3095 
         9: polynom = 32'b100010000;                        // 0x110
3096 
        10: polynom = 32'b1001000000;                       // 0x240
3097 
        11: polynom = 32'b10100000000;                      // 0x500
3098 
        12: polynom = 32'b100000101001;                     // 0x829
3099 
        13: polynom = 32'b1000000001100;                    // 0x100C
3100 
        14: polynom = 32'b10000000010101;                   // 0x2015
3101 
        15: polynom = 32'b110000000000000;                  // 0x6000
3102 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3103 
        17: polynom = 32'b10010000000000000;                // 0x12000
3104 
        18: polynom = 32'b100000010000000000;               // 0x20400
3105 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3106 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3107 22 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3108 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3109 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3110 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3111 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3112 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3113 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3114 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3115 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3116 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3117 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3118 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3119 
        default: polynom = 32'b0;
3120 
        endcase
3121 
        lfsr_fb = qi[length];
3122 
        for (i=length-1; i>=1; i=i-1) begin
3123 
            if (polynom[i])
3124 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3125 
        end
3126 
    end
3127 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3128 
 
3129 
   always @ (posedge clk or posedge rst)
3130 
     if (rst)
3131 
       qi <= {length{1'b0}};
3132 
     else
3133 
     if (cke)
3134 
       qi <= q_next;
3135 
 
3136 
   assign q = qi;
3137 
 
3138 
 
3139 
   always @ (posedge clk or posedge rst)
3140 
     if (rst)
3141 
       zq <= 1'b1;
3142 
     else
3143 
     if (cke)
3144 
       zq <= q_next == {length{1'b0}};
3145 
endmodule
3146 40 unneback 
`endif
3147 
`ifdef CNT_LFSR_CE_REW_L1
3148 22 unneback 
//////////////////////////////////////////////////////////////////////
3149 
////                                                              ////
3150 
////  Versatile counter                                           ////
3151 
////                                                              ////
3152 
////  Description                                                 ////
3153 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3154 
////  counter                                                     ////
3155 
////                                                              ////
3156 
////  To Do:                                                      ////
3157 
////   - add LFSR with more taps                                  ////
3158 
////                                                              ////
3159 
////  Author(s):                                                  ////
3160 
////      - Michael Unneback, unneback@opencores.org              ////
3161 
////        ORSoC AB                                              ////
3162 
////                                                              ////
3163 
//////////////////////////////////////////////////////////////////////
3164 
////                                                              ////
3165 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3166 
////                                                              ////
3167 
//// This source file may be used and distributed without         ////
3168 
//// restriction provided that this copyright statement is not    ////
3169 
//// removed from the file and that any derivative work contains  ////
3170 
//// the original copyright notice and the associated disclaimer. ////
3171 
////                                                              ////
3172 
//// This source file is free software; you can redistribute it   ////
3173 
//// and/or modify it under the terms of the GNU Lesser General   ////
3174 
//// Public License as published by the Free Software Foundation; ////
3175 
//// either version 2.1 of the License, or (at your option) any   ////
3176 
//// later version.                                               ////
3177 
////                                                              ////
3178 
//// This source is distributed in the hope that it will be       ////
3179 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3180 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3181 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3182 
//// details.                                                     ////
3183 
////                                                              ////
3184 
//// You should have received a copy of the GNU Lesser General    ////
3185 
//// Public License along with this source; if not, download it   ////
3186 
//// from http://www.opencores.org/lgpl.shtml                     ////
3187 
////                                                              ////
3188 
//////////////////////////////////////////////////////////////////////
3189 6 unneback 
 
3190 
// LFSR counter
3191 
 
3192 40 unneback 
`define MODULE cnt_lfsr_ce_rew_l1
3193 
module `BASE`MODULE (
3194 
`undef MODULE
3195 
 cke, rew, level1, rst, clk);
3196 
 
3197 6 unneback 
   parameter length = 4;
3198 
   input cke;
3199 
   input rew;
3200 
   output reg level1;
3201 
   input rst;
3202 
   input clk;
3203 
 
3204 
   parameter clear_value = 0;
3205 
   parameter set_value = 1;
3206 
   parameter wrap_value = 8;
3207 
   parameter level1_value = 15;
3208 
 
3209 29 unneback 
   wire clear;
3210 30 unneback 
   assign clear = 1'b0;
3211 6 unneback 
   reg  [length:1] qi;
3212 
   reg lfsr_fb, lfsr_fb_rew;
3213 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
3214 
   reg [32:1] polynom_rew;
3215 
   integer j;
3216 
   reg [32:1] polynom;
3217 
   integer i;
3218 
 
3219 
   always @ (qi)
3220 
   begin
3221 
        case (length)
3222 
         2: polynom = 32'b11;                               // 0x3
3223 
         3: polynom = 32'b110;                              // 0x6
3224 
         4: polynom = 32'b1100;                             // 0xC
3225 
         5: polynom = 32'b10100;                            // 0x14
3226 
         6: polynom = 32'b110000;                           // 0x30
3227 
         7: polynom = 32'b1100000;                          // 0x60
3228 
         8: polynom = 32'b10111000;                         // 0xb8
3229 
         9: polynom = 32'b100010000;                        // 0x110
3230 
        10: polynom = 32'b1001000000;                       // 0x240
3231 
        11: polynom = 32'b10100000000;                      // 0x500
3232 
        12: polynom = 32'b100000101001;                     // 0x829
3233 
        13: polynom = 32'b1000000001100;                    // 0x100C
3234 
        14: polynom = 32'b10000000010101;                   // 0x2015
3235 
        15: polynom = 32'b110000000000000;                  // 0x6000
3236 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3237 
        17: polynom = 32'b10010000000000000;                // 0x12000
3238 
        18: polynom = 32'b100000010000000000;               // 0x20400
3239 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3240 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3241 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3242 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3243 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3244 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3245 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3246 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3247 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3248 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3249 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3250 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3251 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3252 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3253 
        default: polynom = 32'b0;
3254 
        endcase
3255 
        lfsr_fb = qi[length];
3256 
        for (i=length-1; i>=1; i=i-1) begin
3257 
            if (polynom[i])
3258 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3259 
        end
3260 
    end
3261 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3262 
   always @ (qi)
3263 
   begin
3264 
        case (length)
3265 
         2: polynom_rew = 32'b11;
3266 
         3: polynom_rew = 32'b110;
3267 
         4: polynom_rew = 32'b1100;
3268 
         5: polynom_rew = 32'b10100;
3269 
         6: polynom_rew = 32'b110000;
3270 
         7: polynom_rew = 32'b1100000;
3271 
         8: polynom_rew = 32'b10111000;
3272 
         9: polynom_rew = 32'b100010000;
3273 
        10: polynom_rew = 32'b1001000000;
3274 
        11: polynom_rew = 32'b10100000000;
3275 
        12: polynom_rew = 32'b100000101001;
3276 
        13: polynom_rew = 32'b1000000001100;
3277 
        14: polynom_rew = 32'b10000000010101;
3278 
        15: polynom_rew = 32'b110000000000000;
3279 
        16: polynom_rew = 32'b1101000000001000;
3280 
        17: polynom_rew = 32'b10010000000000000;
3281 
        18: polynom_rew = 32'b100000010000000000;
3282 
        19: polynom_rew = 32'b1000000000000100011;
3283 
        20: polynom_rew = 32'b10000010000000000000;
3284 
        21: polynom_rew = 32'b101000000000000000000;
3285 
        22: polynom_rew = 32'b1100000000000000000000;
3286 
        23: polynom_rew = 32'b10000100000000000000000;
3287 
        24: polynom_rew = 32'b111000010000000000000000;
3288 
        25: polynom_rew = 32'b1001000000000000000000000;
3289 
        26: polynom_rew = 32'b10000000000000000000100011;
3290 
        27: polynom_rew = 32'b100000000000000000000010011;
3291 
        28: polynom_rew = 32'b1100100000000000000000000000;
3292 
        29: polynom_rew = 32'b10100000000000000000000000000;
3293 
        30: polynom_rew = 32'b100000000000000000000000101001;
3294 
        31: polynom_rew = 32'b1001000000000000000000000000000;
3295 
        32: polynom_rew = 32'b10000000001000000000000000000011;
3296 
        default: polynom_rew = 32'b0;
3297 
        endcase
3298 
        // rotate left
3299 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3300 
        lfsr_fb_rew = qi[length];
3301 
        for (i=length-1; i>=1; i=i-1) begin
3302 
            if (polynom_rew[i])
3303 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3304 
        end
3305 
    end
3306 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3307 
   assign q_next = rew ? q_next_rew : q_next_fw;
3308 
 
3309 
   always @ (posedge clk or posedge rst)
3310 
     if (rst)
3311 
       qi <= {length{1'b0}};
3312 
     else
3313 
     if (cke)
3314 
       qi <= q_next;
3315 
 
3316 
 
3317 
 
3318 
    always @ (posedge clk or posedge rst)
3319 
    if (rst)
3320 
        level1 <= 1'b0;
3321 
    else
3322 
    if (cke)
3323 29 unneback 
    if (clear)
3324 
        level1 <= 1'b0;
3325 
    else if (q_next == level1_value)
3326 6 unneback 
        level1 <= 1'b1;
3327 
    else if (qi == level1_value & rew)
3328 
        level1 <= 1'b0;
3329 
endmodule
3330 40 unneback 
`endif
3331 
`ifdef CNT_GRAY
3332 6 unneback 
//////////////////////////////////////////////////////////////////////
3333 
////                                                              ////
3334 
////  Versatile counter                                           ////
3335 
////                                                              ////
3336 
////  Description                                                 ////
3337 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3338 
////  counter                                                     ////
3339 
////                                                              ////
3340 
////  To Do:                                                      ////
3341 
////   - add LFSR with more taps                                  ////
3342 
////                                                              ////
3343 
////  Author(s):                                                  ////
3344 
////      - Michael Unneback, unneback@opencores.org              ////
3345 
////        ORSoC AB                                              ////
3346 
////                                                              ////
3347 
//////////////////////////////////////////////////////////////////////
3348 
////                                                              ////
3349 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3350 
////                                                              ////
3351 
//// This source file may be used and distributed without         ////
3352 
//// restriction provided that this copyright statement is not    ////
3353 
//// removed from the file and that any derivative work contains  ////
3354 
//// the original copyright notice and the associated disclaimer. ////
3355 
////                                                              ////
3356 
//// This source file is free software; you can redistribute it   ////
3357 
//// and/or modify it under the terms of the GNU Lesser General   ////
3358 
//// Public License as published by the Free Software Foundation; ////
3359 
//// either version 2.1 of the License, or (at your option) any   ////
3360 
//// later version.                                               ////
3361 
////                                                              ////
3362 
//// This source is distributed in the hope that it will be       ////
3363 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3364 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3365 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3366 
//// details.                                                     ////
3367 
////                                                              ////
3368 
//// You should have received a copy of the GNU Lesser General    ////
3369 
//// Public License along with this source; if not, download it   ////
3370 
//// from http://www.opencores.org/lgpl.shtml                     ////
3371 
////                                                              ////
3372 
//////////////////////////////////////////////////////////////////////
3373 
 
3374 
// GRAY counter
3375 
 
3376 40 unneback 
`define MODULE cnt_gray
3377 
module `BASE`MODULE (
3378 
`undef MODULE
3379 
 q, rst, clk);
3380 
 
3381 6 unneback 
   parameter length = 4;
3382 
   output reg [length:1] q;
3383 
   input rst;
3384 
   input clk;
3385 
 
3386 
   parameter clear_value = 0;
3387 
   parameter set_value = 1;
3388 
   parameter wrap_value = 8;
3389 
   parameter level1_value = 15;
3390 
 
3391 
   reg  [length:1] qi;
3392 
   wire [length:1] q_next;
3393 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3394 
 
3395 
   always @ (posedge clk or posedge rst)
3396 
     if (rst)
3397 
       qi <= {length{1'b0}};
3398 
     else
3399 
       qi <= q_next;
3400 
 
3401 
   always @ (posedge clk or posedge rst)
3402 
     if (rst)
3403 
       q <= {length{1'b0}};
3404 
     else
3405 
         q <= (q_next>>1) ^ q_next;
3406 
 
3407 
endmodule
3408 40 unneback 
`endif
3409 
`ifdef CNT_GRAY_CE
3410 6 unneback 
//////////////////////////////////////////////////////////////////////
3411 
////                                                              ////
3412 
////  Versatile counter                                           ////
3413 
////                                                              ////
3414 
////  Description                                                 ////
3415 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3416 
////  counter                                                     ////
3417 
////                                                              ////
3418 
////  To Do:                                                      ////
3419 
////   - add LFSR with more taps                                  ////
3420 
////                                                              ////
3421 
////  Author(s):                                                  ////
3422 
////      - Michael Unneback, unneback@opencores.org              ////
3423 
////        ORSoC AB                                              ////
3424 
////                                                              ////
3425 
//////////////////////////////////////////////////////////////////////
3426 
////                                                              ////
3427 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3428 
////                                                              ////
3429 
//// This source file may be used and distributed without         ////
3430 
//// restriction provided that this copyright statement is not    ////
3431 
//// removed from the file and that any derivative work contains  ////
3432 
//// the original copyright notice and the associated disclaimer. ////
3433 
////                                                              ////
3434 
//// This source file is free software; you can redistribute it   ////
3435 
//// and/or modify it under the terms of the GNU Lesser General   ////
3436 
//// Public License as published by the Free Software Foundation; ////
3437 
//// either version 2.1 of the License, or (at your option) any   ////
3438 
//// later version.                                               ////
3439 
////                                                              ////
3440 
//// This source is distributed in the hope that it will be       ////
3441 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3442 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3443 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3444 
//// details.                                                     ////
3445 
////                                                              ////
3446 
//// You should have received a copy of the GNU Lesser General    ////
3447 
//// Public License along with this source; if not, download it   ////
3448 
//// from http://www.opencores.org/lgpl.shtml                     ////
3449 
////                                                              ////
3450 
//////////////////////////////////////////////////////////////////////
3451 
 
3452 
// GRAY counter
3453 
 
3454 40 unneback 
`define MODULE cnt_gray_ce
3455 
module `BASE`MODULE (
3456 
`undef MODULE
3457 
 cke, q, rst, clk);
3458 
 
3459 6 unneback 
   parameter length = 4;
3460 
   input cke;
3461 
   output reg [length:1] q;
3462 
   input rst;
3463 
   input clk;
3464 
 
3465 
   parameter clear_value = 0;
3466 
   parameter set_value = 1;
3467 
   parameter wrap_value = 8;
3468 
   parameter level1_value = 15;
3469 
 
3470 
   reg  [length:1] qi;
3471 
   wire [length:1] q_next;
3472 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3473 
 
3474 
   always @ (posedge clk or posedge rst)
3475 
     if (rst)
3476 
       qi <= {length{1'b0}};
3477 
     else
3478 
     if (cke)
3479 
       qi <= q_next;
3480 
 
3481 
   always @ (posedge clk or posedge rst)
3482 
     if (rst)
3483 
       q <= {length{1'b0}};
3484 
     else
3485 
       if (cke)
3486 
         q <= (q_next>>1) ^ q_next;
3487 
 
3488 
endmodule
3489 40 unneback 
`endif
3490 
`ifdef CNT_GRAY_CE_BIN
3491 6 unneback 
//////////////////////////////////////////////////////////////////////
3492 
////                                                              ////
3493 
////  Versatile counter                                           ////
3494 
////                                                              ////
3495 
////  Description                                                 ////
3496 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3497 
////  counter                                                     ////
3498 
////                                                              ////
3499 
////  To Do:                                                      ////
3500 
////   - add LFSR with more taps                                  ////
3501 
////                                                              ////
3502 
////  Author(s):                                                  ////
3503 
////      - Michael Unneback, unneback@opencores.org              ////
3504 
////        ORSoC AB                                              ////
3505 
////                                                              ////
3506 
//////////////////////////////////////////////////////////////////////
3507 
////                                                              ////
3508 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3509 
////                                                              ////
3510 
//// This source file may be used and distributed without         ////
3511 
//// restriction provided that this copyright statement is not    ////
3512 
//// removed from the file and that any derivative work contains  ////
3513 
//// the original copyright notice and the associated disclaimer. ////
3514 
////                                                              ////
3515 
//// This source file is free software; you can redistribute it   ////
3516 
//// and/or modify it under the terms of the GNU Lesser General   ////
3517 
//// Public License as published by the Free Software Foundation; ////
3518 
//// either version 2.1 of the License, or (at your option) any   ////
3519 
//// later version.                                               ////
3520 
////                                                              ////
3521 
//// This source is distributed in the hope that it will be       ////
3522 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3523 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3524 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3525 
//// details.                                                     ////
3526 
////                                                              ////
3527 
//// You should have received a copy of the GNU Lesser General    ////
3528 
//// Public License along with this source; if not, download it   ////
3529 
//// from http://www.opencores.org/lgpl.shtml                     ////
3530 
////                                                              ////
3531 
//////////////////////////////////////////////////////////////////////
3532 
 
3533 
// GRAY counter
3534 
 
3535 40 unneback 
`define MODULE cnt_gray_ce_bin
3536 
module `BASE`MODULE (
3537 
`undef MODULE
3538 
 cke, q, q_bin, rst, clk);
3539 
 
3540 6 unneback 
   parameter length = 4;
3541 
   input cke;
3542 
   output reg [length:1] q;
3543 
   output [length:1] q_bin;
3544 
   input rst;
3545 
   input clk;
3546 
 
3547 
   parameter clear_value = 0;
3548 
   parameter set_value = 1;
3549 
   parameter wrap_value = 8;
3550 
   parameter level1_value = 15;
3551 
 
3552 
   reg  [length:1] qi;
3553 
   wire [length:1] q_next;
3554 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3555 
 
3556 
   always @ (posedge clk or posedge rst)
3557 
     if (rst)
3558 
       qi <= {length{1'b0}};
3559 
     else
3560 
     if (cke)
3561 
       qi <= q_next;
3562 
 
3563 
   always @ (posedge clk or posedge rst)
3564 
     if (rst)
3565 
       q <= {length{1'b0}};
3566 
     else
3567 
       if (cke)
3568 
         q <= (q_next>>1) ^ q_next;
3569 
 
3570 
   assign q_bin = qi;
3571 
 
3572 
endmodule
3573 40 unneback 
`endif
3574 6 unneback 
//////////////////////////////////////////////////////////////////////
3575 
////                                                              ////
3576 
////  Versatile library, counters                                 ////
3577 
////                                                              ////
3578 
////  Description                                                 ////
3579 
////  counters                                                    ////
3580 
////                                                              ////
3581 
////                                                              ////
3582 
////  To Do:                                                      ////
3583 
////   - add more counters                                        ////
3584 
////                                                              ////
3585 
////  Author(s):                                                  ////
3586 
////      - Michael Unneback, unneback@opencores.org              ////
3587 
////        ORSoC AB                                              ////
3588 
////                                                              ////
3589 
//////////////////////////////////////////////////////////////////////
3590 
////                                                              ////
3591 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3592 
////                                                              ////
3593 
//// This source file may be used and distributed without         ////
3594 
//// restriction provided that this copyright statement is not    ////
3595 
//// removed from the file and that any derivative work contains  ////
3596 
//// the original copyright notice and the associated disclaimer. ////
3597 
////                                                              ////
3598 
//// This source file is free software; you can redistribute it   ////
3599 
//// and/or modify it under the terms of the GNU Lesser General   ////
3600 
//// Public License as published by the Free Software Foundation; ////
3601 
//// either version 2.1 of the License, or (at your option) any   ////
3602 
//// later version.                                               ////
3603 
////                                                              ////
3604 
//// This source is distributed in the hope that it will be       ////
3605 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3606 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3607 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3608 
//// details.                                                     ////
3609 
////                                                              ////
3610 
//// You should have received a copy of the GNU Lesser General    ////
3611 
//// Public License along with this source; if not, download it   ////
3612 
//// from http://www.opencores.org/lgpl.shtml                     ////
3613 
////                                                              ////
3614 
//////////////////////////////////////////////////////////////////////
3615 
 
3616 40 unneback 
`ifdef CNT_SHREG_WRAP
3617 
`define MODULE cnt_shreg_wrap
3618 
module `BASE`MODULE ( q, rst, clk);
3619 
`undef MODULE
3620 6 unneback 
 
3621 
   parameter length = 4;
3622 
   output reg [0:length-1] q;
3623 
   input rst;
3624 
   input clk;
3625 
 
3626 
    always @ (posedge clk or posedge rst)
3627 
    if (rst)
3628 
        q <= {1'b1,{length-1{1'b0}}};
3629 
    else
3630 
        q <= {q[length-1],q[0:length-2]};
3631 
 
3632 
endmodule
3633 40 unneback 
`endif
3634 6 unneback 
 
3635 40 unneback 
`ifdef CNT_SHREG_CE_WRAP
3636 
`define MODULE cnt_shreg_ce_wrap
3637 
module `BASE`MODULE ( cke, q, rst, clk);
3638 
`undef MODULE
3639 6 unneback 
 
3640 
   parameter length = 4;
3641 
   input cke;
3642 
   output reg [0:length-1] q;
3643 
   input rst;
3644 
   input clk;
3645 
 
3646 
    always @ (posedge clk or posedge rst)
3647 
    if (rst)
3648 
        q <= {1'b1,{length-1{1'b0}}};
3649 
    else
3650 
        if (cke)
3651 
            q <= {q[length-1],q[0:length-2]};
3652 
 
3653 
endmodule
3654 40 unneback 
`endif
3655 6 unneback 
 
3656 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR
3657 
`define MODULE cnt_shreg_ce_clear
3658 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3659 
`undef MODULE
3660 6 unneback 
 
3661 
   parameter length = 4;
3662 
   input cke, clear;
3663 
   output reg [0:length-1] q;
3664 
   input rst;
3665 
   input clk;
3666 
 
3667 
    always @ (posedge clk or posedge rst)
3668 
    if (rst)
3669 
        q <= {1'b1,{length-1{1'b0}}};
3670 
    else
3671 
        if (cke)
3672 
            if (clear)
3673 
                q <= {1'b1,{length-1{1'b0}}};
3674 
            else
3675 
                q <= q >> 1;
3676 
 
3677 
endmodule
3678 40 unneback 
`endif
3679 6 unneback 
 
3680 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3681 
`define MODULE cnt_shreg_ce_clear_wrap
3682 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3683 
`undef MODULE
3684 6 unneback 
 
3685 
   parameter length = 4;
3686 
   input cke, clear;
3687 
   output reg [0:length-1] q;
3688 
   input rst;
3689 
   input clk;
3690 
 
3691 
    always @ (posedge clk or posedge rst)
3692 
    if (rst)
3693 
        q <= {1'b1,{length-1{1'b0}}};
3694 
    else
3695 
        if (cke)
3696 
            if (clear)
3697 
                q <= {1'b1,{length-1{1'b0}}};
3698 
            else
3699 
            q <= {q[length-1],q[0:length-2]};
3700 
 
3701 
endmodule
3702 40 unneback 
`endif
3703 6 unneback 
//////////////////////////////////////////////////////////////////////
3704 
////                                                              ////
3705 
////  Versatile library, memories                                 ////
3706 
////                                                              ////
3707 
////  Description                                                 ////
3708 
////  memories                                                    ////
3709 
////                                                              ////
3710 
////                                                              ////
3711 
////  To Do:                                                      ////
3712 
////   - add more memory types                                    ////
3713 
////                                                              ////
3714 
////  Author(s):                                                  ////
3715 
////      - Michael Unneback, unneback@opencores.org              ////
3716 
////        ORSoC AB                                              ////
3717 
////                                                              ////
3718 
//////////////////////////////////////////////////////////////////////
3719 
////                                                              ////
3720 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3721 
////                                                              ////
3722 
//// This source file may be used and distributed without         ////
3723 
//// restriction provided that this copyright statement is not    ////
3724 
//// removed from the file and that any derivative work contains  ////
3725 
//// the original copyright notice and the associated disclaimer. ////
3726 
////                                                              ////
3727 
//// This source file is free software; you can redistribute it   ////
3728 
//// and/or modify it under the terms of the GNU Lesser General   ////
3729 
//// Public License as published by the Free Software Foundation; ////
3730 
//// either version 2.1 of the License, or (at your option) any   ////
3731 
//// later version.                                               ////
3732 
////                                                              ////
3733 
//// This source is distributed in the hope that it will be       ////
3734 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3735 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3736 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3737 
//// details.                                                     ////
3738 
////                                                              ////
3739 
//// You should have received a copy of the GNU Lesser General    ////
3740 
//// Public License along with this source; if not, download it   ////
3741 
//// from http://www.opencores.org/lgpl.shtml                     ////
3742 
////                                                              ////
3743 
//////////////////////////////////////////////////////////////////////
3744 
 
3745 40 unneback 
`ifdef ROM_INIT
3746 6 unneback 
/// ROM
3747 40 unneback 
`define MODULE rom_init
3748 
module `BASE`MODULE ( adr, q, clk);
3749 
`undef MODULE
3750 6 unneback 
 
3751 7 unneback 
   parameter data_width = 32;
3752 
   parameter addr_width = 8;
3753 75 unneback 
   parameter mem_size = 1<<addr_width;
3754 7 unneback 
   input [(addr_width-1):0]       adr;
3755 
   output reg [(data_width-1):0] q;
3756 
   input                         clk;
3757 75 unneback 
   reg [data_width-1:0] rom [mem_size-1:0];
3758 7 unneback 
   parameter memory_file = "vl_rom.vmem";
3759 
   initial
3760 
     begin
3761 
        $readmemh(memory_file, rom);
3762 
     end
3763 
 
3764 
   always @ (posedge clk)
3765 
     q <= rom[adr];
3766 6 unneback 
 
3767 7 unneback 
endmodule
3768 40 unneback 
`endif
3769 7 unneback 
 
3770 40 unneback 
`ifdef RAM
3771 
`define MODULE ram
3772 6 unneback 
// Single port RAM
3773 40 unneback 
module `BASE`MODULE ( d, adr, we, q, clk);
3774 
`undef MODULE
3775 6 unneback 
 
3776 
   parameter data_width = 32;
3777 
   parameter addr_width = 8;
3778 75 unneback 
   parameter mem_size = 1<<addr_width;
3779 6 unneback 
   input [(data_width-1):0]      d;
3780 
   input [(addr_width-1):0]       adr;
3781 
   input                         we;
3782 7 unneback 
   output reg [(data_width-1):0] q;
3783 6 unneback 
   input                         clk;
3784 75 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0];
3785 7 unneback 
   parameter init = 0;
3786 
   parameter memory_file = "vl_ram.vmem";
3787 
   generate if (init) begin : init_mem
3788 
   initial
3789 
     begin
3790 
        $readmemh(memory_file, ram);
3791 
     end
3792 
   end
3793 
   endgenerate
3794 
 
3795 6 unneback 
   always @ (posedge clk)
3796 
   begin
3797 
   if (we)
3798 
     ram[adr] <= d;
3799 
   q <= ram[adr];
3800 
   end
3801 
 
3802 
endmodule
3803 40 unneback 
`endif
3804 6 unneback 
 
3805 40 unneback 
`ifdef RAM_BE
3806 
`define MODULE ram_be
3807 91 unneback 
module `BASE`MODULE ( d, adr, be, we, q, clk);
3808 40 unneback 
`undef MODULE
3809 
 
3810 7 unneback 
   parameter data_width = 32;
3811 72 unneback 
   parameter addr_width = 6;
3812 75 unneback 
   parameter mem_size = 1<<addr_width;
3813 7 unneback 
   input [(data_width-1):0]      d;
3814 
   input [(addr_width-1):0]       adr;
3815 73 unneback 
   input [(data_width/8)-1:0]    be;
3816 7 unneback 
   input                         we;
3817 
   output reg [(data_width-1):0] q;
3818 
   input                         clk;
3819 
 
3820 85 unneback 
 
3821 65 unneback 
`ifdef SYSTEMVERILOG
3822 95 unneback 
    // use a multi-dimensional packed array
3823 
    //t o model individual bytes within the word
3824 
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
3825 65 unneback 
`else
3826 85 unneback 
    reg [data_width-1:0] ram [mem_size-1:0];
3827 
    wire [data_width/8-1:0] cke;
3828 65 unneback 
`endif
3829 
 
3830 60 unneback 
   parameter memory_init = 0;
3831 7 unneback 
   parameter memory_file = "vl_ram.vmem";
3832 60 unneback 
   generate if (memory_init) begin : init_mem
3833 7 unneback 
   initial
3834 
     begin
3835 
        $readmemh(memory_file, ram);
3836 
     end
3837 
   end
3838 
   endgenerate
3839 
 
3840 60 unneback 
`ifdef SYSTEMVERILOG
3841 
 
3842 
always_ff@(posedge clk)
3843 
begin
3844 95 unneback 
    if(we) begin
3845 86 unneback 
        if(be[3]) ram[adr][3] <= d[31:24];
3846 
        if(be[2]) ram[adr][2] <= d[23:16];
3847 
        if(be[1]) ram[adr][1] <= d[15:8];
3848 
        if(be[0]) ram[adr][0] <= d[7:0];
3849 60 unneback 
    end
3850 90 unneback 
        q <= ram[adr];
3851 60 unneback 
end
3852 
 
3853 
`else
3854 
 
3855 85 unneback 
assign cke = {data_width/8{we}} & be;
3856 7 unneback 
   genvar i;
3857 85 unneback 
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
3858 7 unneback 
      always @ (posedge clk)
3859 85 unneback 
      if (cke[i])
3860 7 unneback 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3861 
   end
3862 
   endgenerate
3863 
 
3864 
   always @ (posedge clk)
3865 
      q <= ram[adr];
3866 
 
3867 60 unneback 
`endif
3868 
 
3869 93 unneback 
`ifdef verilator
3870 85 unneback 
   // Function to access RAM (for use by Verilator).
3871 
   function [31:0] get_mem;
3872 
      // verilator public
3873 90 unneback 
      input [addr_width-1:0]             addr;
3874 85 unneback 
      get_mem = ram[addr];
3875 
   endfunction // get_mem
3876 
 
3877 
   // Function to write RAM (for use by Verilator).
3878 
   function set_mem;
3879 
      // verilator public
3880 90 unneback 
      input [addr_width-1:0]             addr;
3881 
      input [data_width-1:0]             data;
3882 85 unneback 
      ram[addr] = data;
3883 
   endfunction // set_mem
3884 93 unneback 
`endif
3885 85 unneback 
 
3886 7 unneback 
endmodule
3887 40 unneback 
`endif
3888 7 unneback 
 
3889 6 unneback 
`ifdef ACTEL
3890 48 unneback 
        // ACTEL FPGA should not use logic to handle rw collision
3891 6 unneback 
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
3892 
`else
3893 
        `define SYN
3894 
`endif
3895 
 
3896 40 unneback 
`ifdef DPRAM_1R1W
3897 
`define MODULE dpram_1r1w
3898 
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3899 
`undef MODULE
3900 6 unneback 
   parameter data_width = 32;
3901 
   parameter addr_width = 8;
3902 75 unneback 
   parameter mem_size = 1<<addr_width;
3903 6 unneback 
   input [(data_width-1):0]      d_a;
3904 
   input [(addr_width-1):0]       adr_a;
3905 
   input [(addr_width-1):0]       adr_b;
3906 
   input                         we_a;
3907 
   output [(data_width-1):0]      q_b;
3908 
   input                         clk_a, clk_b;
3909 
   reg [(addr_width-1):0]         adr_b_reg;
3910 75 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
3911 7 unneback 
 
3912 
   parameter init = 0;
3913 
   parameter memory_file = "vl_ram.vmem";
3914 
   generate if (init) begin : init_mem
3915 
   initial
3916 
     begin
3917 
        $readmemh(memory_file, ram);
3918 
     end
3919 
   end
3920 
   endgenerate
3921 
 
3922 6 unneback 
   always @ (posedge clk_a)
3923 
   if (we_a)
3924 
     ram[adr_a] <= d_a;
3925 
   always @ (posedge clk_b)
3926 
   adr_b_reg <= adr_b;
3927 
   assign q_b = ram[adr_b_reg];
3928 40 unneback 
 
3929 6 unneback 
endmodule
3930 40 unneback 
`endif
3931 6 unneback 
 
3932 40 unneback 
`ifdef DPRAM_2R1W
3933 
`define MODULE dpram_2r1w
3934 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3935 
`undef MODULE
3936 
 
3937 6 unneback 
   parameter data_width = 32;
3938 
   parameter addr_width = 8;
3939 75 unneback 
   parameter mem_size = 1<<addr_width;
3940 6 unneback 
   input [(data_width-1):0]      d_a;
3941 
   input [(addr_width-1):0]       adr_a;
3942 
   input [(addr_width-1):0]       adr_b;
3943 
   input                         we_a;
3944 
   output [(data_width-1):0]      q_b;
3945 
   output reg [(data_width-1):0] q_a;
3946 
   input                         clk_a, clk_b;
3947 
   reg [(data_width-1):0]         q_b;
3948 75 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
3949 7 unneback 
 
3950 
   parameter init = 0;
3951 
   parameter memory_file = "vl_ram.vmem";
3952 
   generate if (init) begin : init_mem
3953 
   initial
3954 
     begin
3955 
        $readmemh(memory_file, ram);
3956 
     end
3957 
   end
3958 
   endgenerate
3959 
 
3960 6 unneback 
   always @ (posedge clk_a)
3961 
     begin
3962 
        q_a <= ram[adr_a];
3963 
        if (we_a)
3964 
             ram[adr_a] <= d_a;
3965 
     end
3966 
   always @ (posedge clk_b)
3967 
          q_b <= ram[adr_b];
3968 
endmodule
3969 40 unneback 
`endif
3970 6 unneback 
 
3971 40 unneback 
`ifdef DPRAM_2R2W
3972 
`define MODULE dpram_2r2w
3973 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3974 
`undef MODULE
3975 
 
3976 6 unneback 
   parameter data_width = 32;
3977 
   parameter addr_width = 8;
3978 75 unneback 
   parameter mem_size = 1<<addr_width;
3979 6 unneback 
   input [(data_width-1):0]      d_a;
3980 
   input [(addr_width-1):0]       adr_a;
3981 
   input [(addr_width-1):0]       adr_b;
3982 
   input                         we_a;
3983 
   output [(data_width-1):0]      q_b;
3984 
   input [(data_width-1):0]       d_b;
3985 
   output reg [(data_width-1):0] q_a;
3986 
   input                         we_b;
3987 
   input                         clk_a, clk_b;
3988 
   reg [(data_width-1):0]         q_b;
3989 75 unneback 
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
3990 7 unneback 
 
3991 
   parameter init = 0;
3992 
   parameter memory_file = "vl_ram.vmem";
3993 
   generate if (init) begin : init_mem
3994 
   initial
3995 
     begin
3996 
        $readmemh(memory_file, ram);
3997 
     end
3998 
   end
3999 
   endgenerate
4000 
 
4001 6 unneback 
   always @ (posedge clk_a)
4002 
     begin
4003 
        q_a <= ram[adr_a];
4004 
        if (we_a)
4005 
             ram[adr_a] <= d_a;
4006 
     end
4007 
   always @ (posedge clk_b)
4008 
     begin
4009 
        q_b <= ram[adr_b];
4010 
        if (we_b)
4011 
          ram[adr_b] <= d_b;
4012 
     end
4013 
endmodule
4014 40 unneback 
`endif
4015 6 unneback 
 
4016 83 unneback 
 
4017 75 unneback 
`ifdef DPRAM_BE_2R2W
4018 
`define MODULE dpram_be_2r2w
4019 92 unneback 
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
4020 75 unneback 
`undef MODULE
4021 
 
4022 
   parameter a_data_width = 32;
4023 
   parameter a_addr_width = 8;
4024 95 unneback 
   parameter b_data_width = 64; //a_data_width;
4025 91 unneback 
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
4026 95 unneback 
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
4027 
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
4028 91 unneback 
 
4029 95 unneback 
   parameter init = 0;
4030 
   parameter memory_file = "vl_ram.vmem";
4031 
 
4032 75 unneback 
   input [(a_data_width-1):0]      d_a;
4033 91 unneback 
   input [(a_addr_width-1):0]       adr_a;
4034 
   input [(a_data_width/8-1):0]    be_a;
4035 
   input                           we_a;
4036 75 unneback 
   output reg [(a_data_width-1):0] q_a;
4037 91 unneback 
   input [(b_data_width-1):0]       d_b;
4038 
   input [(b_addr_width-1):0]       adr_b;
4039 92 unneback 
   input [(b_data_width/8-1):0]    be_b;
4040 
   input                           we_b;
4041 
   output reg [(b_data_width-1):0]          q_b;
4042 91 unneback 
   input                           clk_a, clk_b;
4043 75 unneback 
 
4044 91 unneback 
`ifdef SYSTEMVERILOG
4045 
// use a multi-dimensional packed array
4046 
//to model individual bytes within the word
4047 
 
4048 75 unneback 
generate
4049 91 unneback 
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
4050 75 unneback 
 
4051 95 unneback 
    logic [0:3][7:0] ram [0:mem_size-1];
4052 
 
4053 
    initial
4054 
        if (init)
4055 
            $readmemh(memory_file, ram);
4056 91 unneback 
 
4057 
    always_ff@(posedge clk_a)
4058 
    begin
4059 
        if(we_a) begin
4060 
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
4061 
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
4062 
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
4063 
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
4064 
        end
4065 
    end
4066 
 
4067 92 unneback 
    always@(posedge clk_a)
4068 
        q_a = ram[adr_a];
4069 91 unneback 
 
4070 
    always_ff@(posedge clk_b)
4071 92 unneback 
    begin
4072 
        if(we_b) begin
4073 
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
4074 
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
4075 
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
4076 
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
4077 
        end
4078 
    end
4079 91 unneback 
 
4080 92 unneback 
    always@(posedge clk_b)
4081 
        q_b = ram[adr_b];
4082 91 unneback 
 
4083 75 unneback 
end
4084 
endgenerate
4085 
 
4086 95 unneback 
generate
4087 
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
4088 
 
4089 
    logic [0:7][7:0] ram [0:mem_size-1];
4090 
 
4091 
    initial
4092 
        if (init)
4093 
            $readmemh(memory_file, ram);
4094 
 
4095 
    always_ff@(posedge clk_a)
4096 
    begin
4097 
        if(we_a) begin
4098 
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
4099 
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
4100 
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
4101 
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
4102 
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
4103 
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
4104 
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
4105 
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
4106 
        end
4107 
    end
4108 
 
4109 
    always@(posedge clk_a)
4110 
        q_a = ram[adr_a];
4111 
 
4112 
    always_ff@(posedge clk_b)
4113 
    begin
4114 
        if(we_b) begin
4115 
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
4116 
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
4117 
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
4118 
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
4119 
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
4120 
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
4121 
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
4122 
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
4123 
        end
4124 
    end
4125 
 
4126 
    always@(posedge clk_b)
4127 
        q_b = ram[adr_b];
4128 
 
4129 
end
4130 
endgenerate
4131 
 
4132 
generate
4133 
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
4134 
logic [31:0] temp;
4135 
`define MODULE dpram_be_2r2w
4136 
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
4137 
`undef MODULE
4138 
dpram6464 (
4139 
    .d_a(d_a),
4140 
    .q_a(q_a),
4141 
    .adr_a(adr_a),
4142 
    .be_a(be_a),
4143 
    .we_a(we_a),
4144 
    .clk_a(clk_a),
4145 
    .d_b({d_b,d_b}),
4146 
    .q_b(temp),
4147 
    .adr_b(adr_b),
4148 
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
4149 
    .we_b(we_b),
4150 
    .clk_b(clk_b)
4151 
);
4152 
 
4153 
always_comb
4154 
    if (adr_b[0])
4155 
        q_b = temp[31:16];
4156 
    else
4157 
        q_b = temp[15:0];
4158 
 
4159 
end
4160 
endgenerate
4161 
 
4162 
generate
4163 
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
4164 
logic [63:0] temp;
4165 
`define MODULE dpram_be_2r2w
4166 
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
4167 
`undef MODULE
4168 
dpram6464 (
4169 
    .d_a({d_a,d_a}),
4170 
    .q_a(temp),
4171 
    .adr_a(adr_a[a_addr_width-1:1]),
4172 
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
4173 
    .we_a(we_a),
4174 
    .clk_a(clk_a),
4175 
    .d_b(d_b),
4176 
    .q_b(q_b),
4177 
    .adr_b(adr_b),
4178 
    .be_b(be_b),
4179 
    .we_b(we_b),
4180 
    .clk_b(clk_b)
4181 
);
4182 
 
4183 
always_comb
4184 
    if (adr_a[0])
4185 
        q_a = temp[63:32];
4186 
    else
4187 
        q_a = temp[31:0];
4188 
 
4189 
end
4190 
endgenerate
4191 
 
4192 91 unneback 
`else
4193 92 unneback 
    // This modules requires SystemVerilog
4194 91 unneback 
`endif
4195 75 unneback 
endmodule
4196 
`endif
4197 
 
4198 91 unneback 
`ifdef CAM
4199 6 unneback 
// Content addresable memory, CAM
4200 91 unneback 
`endif
4201 6 unneback 
 
4202 40 unneback 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
4203 6 unneback 
// FIFO
4204 40 unneback 
`define MODULE fifo_1r1w_fill_level_sync
4205 
module `BASE`MODULE (
4206 
`undef MODULE
4207 25 unneback 
    d, wr, fifo_full,
4208 
    q, rd, fifo_empty,
4209 
    fill_level,
4210 
    clk, rst
4211 
    );
4212 
 
4213 
parameter data_width = 18;
4214 
parameter addr_width = 4;
4215 6 unneback 
 
4216 25 unneback 
// write side
4217 
input  [data_width-1:0] d;
4218 
input                   wr;
4219 
output                  fifo_full;
4220 
// read side
4221 
output [data_width-1:0] q;
4222 
input                   rd;
4223 
output                  fifo_empty;
4224 
// common
4225 
output [addr_width:0]   fill_level;
4226 
input rst, clk;
4227 
 
4228 
wire [addr_width:1] wadr, radr;
4229 
 
4230 40 unneback 
`define MODULE cnt_bin_ce
4231 
`BASE`MODULE
4232 25 unneback 
    # ( .length(addr_width))
4233 
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
4234 40 unneback 
`BASE`MODULE
4235 25 unneback 
    # (.length(addr_width))
4236 
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
4237 40 unneback 
`undef MODULE
4238 25 unneback 
 
4239 40 unneback 
`define MODULE dpram_1r1w
4240 
`BASE`MODULE
4241 25 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4242 
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
4243 40 unneback 
`undef MODULE
4244 25 unneback 
 
4245 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
4246 
`BASE`MODULE
4247 27 unneback 
    # (.length(addr_width+1), .level1_value(1<<addr_width))
4248 25 unneback 
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
4249 40 unneback 
`undef MODULE
4250 25 unneback 
endmodule
4251 40 unneback 
`endif
4252 25 unneback 
 
4253 40 unneback 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
4254 27 unneback 
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
4255 
// RAM is supposed to be larger than the two FIFOs
4256 
// LFSR counters used adr pointers
4257 40 unneback 
`define MODULE fifo_2r2w_sync_simplex
4258 
module `BASE`MODULE (
4259 
`undef MODULE
4260 27 unneback 
    // a side
4261 
    a_d, a_wr, a_fifo_full,
4262 
    a_q, a_rd, a_fifo_empty,
4263 
    a_fill_level,
4264 
    // b side
4265 
    b_d, b_wr, b_fifo_full,
4266 
    b_q, b_rd, b_fifo_empty,
4267 
    b_fill_level,
4268 
    // common
4269 
    clk, rst
4270 
    );
4271 
parameter data_width = 8;
4272 
parameter addr_width = 5;
4273 
parameter fifo_full_level = (1<<addr_width)-1;
4274 
 
4275 
// a side
4276 
input  [data_width-1:0] a_d;
4277 
input                   a_wr;
4278 
output                  a_fifo_full;
4279 
output [data_width-1:0] a_q;
4280 
input                   a_rd;
4281 
output                  a_fifo_empty;
4282 
output [addr_width-1:0] a_fill_level;
4283 
 
4284 
// b side
4285 
input  [data_width-1:0] b_d;
4286 
input                   b_wr;
4287 
output                  b_fifo_full;
4288 
output [data_width-1:0] b_q;
4289 
input                   b_rd;
4290 
output                  b_fifo_empty;
4291 
output [addr_width-1:0] b_fill_level;
4292 
 
4293 
input                   clk;
4294 
input                   rst;
4295 
 
4296 
// adr_gen
4297 
wire [addr_width:1] a_wadr, a_radr;
4298 
wire [addr_width:1] b_wadr, b_radr;
4299 
// dpram
4300 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4301 
 
4302 40 unneback 
`define MODULE cnt_lfsr_ce
4303 
`BASE`MODULE
4304 27 unneback 
    # ( .length(addr_width))
4305 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
4306 
 
4307 40 unneback 
`BASE`MODULE
4308 27 unneback 
    # (.length(addr_width))
4309 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
4310 
 
4311 40 unneback 
`BASE`MODULE
4312 27 unneback 
    # ( .length(addr_width))
4313 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
4314 
 
4315 40 unneback 
`BASE`MODULE
4316 27 unneback 
    # (.length(addr_width))
4317 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
4318 40 unneback 
`undef MODULE
4319 27 unneback 
 
4320 
// mux read or write adr to DPRAM
4321 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
4322 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
4323 
 
4324 40 unneback 
`define MODULE dpram_2r2w
4325 
`BASE`MODULE
4326 27 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4327 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4328 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4329 40 unneback 
`undef MODULE
4330 
 
4331 
`define MODULE cnt_bin_ce_rew_zq_l1
4332 
`BASE`MODULE
4333 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4334 27 unneback 
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
4335 
 
4336 40 unneback 
`BASE`MODULE
4337 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4338 27 unneback 
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
4339 40 unneback 
`undef MODULE
4340 27 unneback 
 
4341 
endmodule
4342 40 unneback 
`endif
4343 27 unneback 
 
4344 40 unneback 
`ifdef FIFO_CMP_ASYNC
4345 
`define MODULE fifo_cmp_async
4346 
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
4347 
`undef MODULE
4348 6 unneback 
 
4349 11 unneback 
   parameter addr_width = 4;
4350 
   parameter N = addr_width-1;
4351 6 unneback 
 
4352 
   parameter Q1 = 2'b00;
4353 
   parameter Q2 = 2'b01;
4354 
   parameter Q3 = 2'b11;
4355 
   parameter Q4 = 2'b10;
4356 
 
4357 
   parameter going_empty = 1'b0;
4358 
   parameter going_full  = 1'b1;
4359 
 
4360 
   input [N:0]  wptr, rptr;
4361 14 unneback 
   output       fifo_empty;
4362 6 unneback 
   output       fifo_full;
4363 
   input        wclk, rclk, rst;
4364 
 
4365 
`ifndef GENERATE_DIRECTION_AS_LATCH
4366 
   wire direction;
4367 
`endif
4368 
`ifdef GENERATE_DIRECTION_AS_LATCH
4369 
   reg direction;
4370 
`endif
4371 
   reg  direction_set, direction_clr;
4372 
 
4373 
   wire async_empty, async_full;
4374 
   wire fifo_full2;
4375 14 unneback 
   wire fifo_empty2;
4376 6 unneback 
 
4377 
   // direction_set
4378 
   always @ (wptr[N:N-1] or rptr[N:N-1])
4379 
     case ({wptr[N:N-1],rptr[N:N-1]})
4380 
       {Q1,Q2} : direction_set <= 1'b1;
4381 
       {Q2,Q3} : direction_set <= 1'b1;
4382 
       {Q3,Q4} : direction_set <= 1'b1;
4383 
       {Q4,Q1} : direction_set <= 1'b1;
4384 
       default : direction_set <= 1'b0;
4385 
     endcase
4386 
 
4387 
   // direction_clear
4388 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
4389 
     if (rst)
4390 
       direction_clr <= 1'b1;
4391 
     else
4392 
       case ({wptr[N:N-1],rptr[N:N-1]})
4393 
         {Q2,Q1} : direction_clr <= 1'b1;
4394 
         {Q3,Q2} : direction_clr <= 1'b1;
4395 
         {Q4,Q3} : direction_clr <= 1'b1;
4396 
         {Q1,Q4} : direction_clr <= 1'b1;
4397 
         default : direction_clr <= 1'b0;
4398 
       endcase
4399 
 
4400 40 unneback 
`define MODULE dff_sr
4401 6 unneback 
`ifndef GENERATE_DIRECTION_AS_LATCH
4402 40 unneback 
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
4403 6 unneback 
`endif
4404 
 
4405 
`ifdef GENERATE_DIRECTION_AS_LATCH
4406 
   always @ (posedge direction_set or posedge direction_clr)
4407 
     if (direction_clr)
4408 
       direction <= going_empty;
4409 
     else
4410 
       direction <= going_full;
4411 
`endif
4412 
 
4413 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
4414 
   assign async_full  = (wptr == rptr) && (direction==going_full);
4415 
 
4416 40 unneback 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
4417 
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
4418 
`undef MODULE
4419 6 unneback 
 
4420 
/*
4421 
   always @ (posedge wclk or posedge rst or posedge async_full)
4422 
     if (rst)
4423 
       {fifo_full, fifo_full2} <= 2'b00;
4424 
     else if (async_full)
4425 
       {fifo_full, fifo_full2} <= 2'b11;
4426 
     else
4427 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
4428 
*/
4429 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
4430 6 unneback 
     if (async_empty)
4431 
       {fifo_empty, fifo_empty2} <= 2'b11;
4432 
     else
4433 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
4434 40 unneback 
`define MODULE dff
4435 
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
4436 
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
4437 
`undef MODULE
4438 27 unneback 
endmodule // async_compb
4439 40 unneback 
`endif
4440 6 unneback 
 
4441 40 unneback 
`ifdef FIFO_1R1W_ASYNC
4442 
`define MODULE fifo_1r1w_async
4443 
module `BASE`MODULE (
4444 
`undef MODULE
4445 6 unneback 
    d, wr, fifo_full, wr_clk, wr_rst,
4446 
    q, rd, fifo_empty, rd_clk, rd_rst
4447 
    );
4448 
 
4449 
parameter data_width = 18;
4450 
parameter addr_width = 4;
4451 
 
4452 
// write side
4453 
input  [data_width-1:0] d;
4454 
input                   wr;
4455 
output                  fifo_full;
4456 
input                   wr_clk;
4457 
input                   wr_rst;
4458 
// read side
4459 
output [data_width-1:0] q;
4460 
input                   rd;
4461 
output                  fifo_empty;
4462 
input                   rd_clk;
4463 
input                   rd_rst;
4464 
 
4465 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
4466 23 unneback 
 
4467 40 unneback 
`define MODULE cnt_gray_ce_bin
4468 
`BASE`MODULE
4469 6 unneback 
    # ( .length(addr_width))
4470 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
4471 
 
4472 40 unneback 
`BASE`MODULE
4473 6 unneback 
    # (.length(addr_width))
4474 23 unneback 
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
4475 40 unneback 
`undef MODULE
4476 6 unneback 
 
4477 40 unneback 
`define MODULE dpram_1r1w
4478 
`BASE`MODULE
4479 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4480 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
4481 40 unneback 
`undef MODULE
4482 6 unneback 
 
4483 40 unneback 
`define MODULE fifo_cmp_async
4484 
`BASE`MODULE
4485 6 unneback 
    # (.addr_width(addr_width))
4486 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
4487 40 unneback 
`undef MODULE
4488 6 unneback 
 
4489 
endmodule
4490 40 unneback 
`endif
4491 6 unneback 
 
4492 40 unneback 
`ifdef FIFO_2R2W_ASYNC
4493 
`define MODULE fifo_2r2w_async
4494 
module `BASE`MODULE (
4495 
`undef MODULE
4496 6 unneback 
    // a side
4497 
    a_d, a_wr, a_fifo_full,
4498 
    a_q, a_rd, a_fifo_empty,
4499 
    a_clk, a_rst,
4500 
    // b side
4501 
    b_d, b_wr, b_fifo_full,
4502 
    b_q, b_rd, b_fifo_empty,
4503 
    b_clk, b_rst
4504 
    );
4505 
 
4506 
parameter data_width = 18;
4507 
parameter addr_width = 4;
4508 
 
4509 
// a side
4510 
input  [data_width-1:0] a_d;
4511 
input                   a_wr;
4512 
output                  a_fifo_full;
4513 
output [data_width-1:0] a_q;
4514 
input                   a_rd;
4515 
output                  a_fifo_empty;
4516 
input                   a_clk;
4517 
input                   a_rst;
4518 
 
4519 
// b side
4520 
input  [data_width-1:0] b_d;
4521 
input                   b_wr;
4522 
output                  b_fifo_full;
4523 
output [data_width-1:0] b_q;
4524 
input                   b_rd;
4525 
output                  b_fifo_empty;
4526 
input                   b_clk;
4527 
input                   b_rst;
4528 
 
4529 40 unneback 
`define MODULE fifo_1r1w_async
4530 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4531 6 unneback 
vl_fifo_1r1w_async_a (
4532 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4533 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4534 
    );
4535 
 
4536 40 unneback 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4537 6 unneback 
vl_fifo_1r1w_async_b (
4538 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4539 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4540 
    );
4541 40 unneback 
`undef MODULE
4542 
 
4543 6 unneback 
endmodule
4544 40 unneback 
`endif
4545 6 unneback 
 
4546 40 unneback 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4547 
`define MODULE fifo_2r2w_async_simplex
4548 
module `BASE`MODULE (
4549 
`undef MODULE
4550 6 unneback 
    // a side
4551 
    a_d, a_wr, a_fifo_full,
4552 
    a_q, a_rd, a_fifo_empty,
4553 
    a_clk, a_rst,
4554 
    // b side
4555 
    b_d, b_wr, b_fifo_full,
4556 
    b_q, b_rd, b_fifo_empty,
4557 
    b_clk, b_rst
4558 
    );
4559 
 
4560 
parameter data_width = 18;
4561 
parameter addr_width = 4;
4562 
 
4563 
// a side
4564 
input  [data_width-1:0] a_d;
4565 
input                   a_wr;
4566 
output                  a_fifo_full;
4567 
output [data_width-1:0] a_q;
4568 
input                   a_rd;
4569 
output                  a_fifo_empty;
4570 
input                   a_clk;
4571 
input                   a_rst;
4572 
 
4573 
// b side
4574 
input  [data_width-1:0] b_d;
4575 
input                   b_wr;
4576 
output                  b_fifo_full;
4577 
output [data_width-1:0] b_q;
4578 
input                   b_rd;
4579 
output                  b_fifo_empty;
4580 
input                   b_clk;
4581 
input                   b_rst;
4582 
 
4583 
// adr_gen
4584 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4585 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4586 
// dpram
4587 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4588 
 
4589 40 unneback 
`define MODULE cnt_gray_ce_bin
4590 
`BASE`MODULE
4591 6 unneback 
    # ( .length(addr_width))
4592 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4593 
 
4594 40 unneback 
`BASE`MODULE
4595 6 unneback 
    # (.length(addr_width))
4596 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4597 
 
4598 40 unneback 
`BASE`MODULE
4599 6 unneback 
    # ( .length(addr_width))
4600 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4601 
 
4602 40 unneback 
`BASE`MODULE
4603 6 unneback 
    # (.length(addr_width))
4604 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4605 40 unneback 
`undef MODULE
4606 6 unneback 
 
4607 
// mux read or write adr to DPRAM
4608 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4609 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4610 
 
4611 40 unneback 
`define MODULE dpram_2r2w
4612 
`BASE`MODULE
4613 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4614 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4615 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4616 40 unneback 
`undef MODULE
4617 6 unneback 
 
4618 40 unneback 
`define MODULE fifo_cmp_async
4619 
`BASE`MODULE
4620 6 unneback 
    # (.addr_width(addr_width))
4621 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4622 
 
4623 40 unneback 
`BASE`MODULE
4624 6 unneback 
    # (.addr_width(addr_width))
4625 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4626 40 unneback 
`undef MODULE
4627 6 unneback 
 
4628 
endmodule
4629 40 unneback 
`endif
4630 48 unneback 
 
4631 
`ifdef REG_FILE
4632 
`define MODULE reg_file
4633 
module `BASE`MODULE (
4634 
`undef MODULE
4635 
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4636 
);
4637 
parameter data_width = 32;
4638 
parameter addr_width = 5;
4639 
input [addr_width-1:0] a1, a2, a3;
4640 
input [data_width-1:0] wd3;
4641 
input we3;
4642 
output [data_width-1:0] rd1, rd2;
4643 
input clk;
4644 
 
4645 
`ifdef ACTEL
4646 
reg [data_width-1:0] wd3_reg;
4647 
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4648 
reg we3_reg;
4649 
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
4650 
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
4651 
always @ (posedge clk or posedge rst)
4652 
if (rst)
4653 
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4654 
else
4655 
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4656 
 
4657 
    always @ (negedge clk)
4658 
    if (we3_reg)
4659 
        ram1[a3_reg] <= wd3;
4660 
    always @ (posedge clk)
4661 
        a1_reg <= a1;
4662 
    assign rd1 = ram1[a1_reg];
4663 
 
4664 
    always @ (negedge clk)
4665 
    if (we3_reg)
4666 
        ram2[a3_reg] <= wd3;
4667 
    always @ (posedge clk)
4668 
        a2_reg <= a2;
4669 
    assign rd2 = ram2[a2_reg];
4670 
 
4671 
`else
4672 
 
4673 
`define MODULE dpram_1r1w
4674 
`BASE`MODULE
4675 
    # ( .data_width(data_width), .addr_width(addr_width))
4676 
    ram1 (
4677 
        .d_a(wd3),
4678 
        .adr_a(a3),
4679 
        .we_a(we3),
4680 
        .clk_a(clk),
4681 
        .q_b(rd1),
4682 
        .adr_b(a1),
4683 
        .clk_b(clk) );
4684 
 
4685 
`BASE`MODULE
4686 
    # ( .data_width(data_width), .addr_width(addr_width))
4687 
    ram2 (
4688 
        .d_a(wd3),
4689 
        .adr_a(a3),
4690 
        .we_a(we3),
4691 
        .clk_a(clk),
4692 
        .q_b(rd2),
4693 
        .adr_b(a2),
4694 
        .clk_b(clk) );
4695 
`undef MODULE
4696 
 
4697 
`endif
4698 
 
4699 
endmodule
4700 
`endif
4701 12 unneback 
//////////////////////////////////////////////////////////////////////
4702 
////                                                              ////
4703 
////  Versatile library, wishbone stuff                           ////
4704 
////                                                              ////
4705 
////  Description                                                 ////
4706 
////  Wishbone compliant modules                                  ////
4707 
////                                                              ////
4708 
////                                                              ////
4709 
////  To Do:                                                      ////
4710 
////   -                                                          ////
4711 
////                                                              ////
4712 
////  Author(s):                                                  ////
4713 
////      - Michael Unneback, unneback@opencores.org              ////
4714 
////        ORSoC AB                                              ////
4715 
////                                                              ////
4716 
//////////////////////////////////////////////////////////////////////
4717 
////                                                              ////
4718 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4719 
////                                                              ////
4720 
//// This source file may be used and distributed without         ////
4721 
//// restriction provided that this copyright statement is not    ////
4722 
//// removed from the file and that any derivative work contains  ////
4723 
//// the original copyright notice and the associated disclaimer. ////
4724 
////                                                              ////
4725 
//// This source file is free software; you can redistribute it   ////
4726 
//// and/or modify it under the terms of the GNU Lesser General   ////
4727 
//// Public License as published by the Free Software Foundation; ////
4728 
//// either version 2.1 of the License, or (at your option) any   ////
4729 
//// later version.                                               ////
4730 
////                                                              ////
4731 
//// This source is distributed in the hope that it will be       ////
4732 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4733 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4734 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4735 
//// details.                                                     ////
4736 
////                                                              ////
4737 
//// You should have received a copy of the GNU Lesser General    ////
4738 
//// Public License along with this source; if not, download it   ////
4739 
//// from http://www.opencores.org/lgpl.shtml                     ////
4740 
////                                                              ////
4741 
//////////////////////////////////////////////////////////////////////
4742 
 
4743 75 unneback 
`ifdef WB_ADR_INC
4744 
// async wb3 - wb3 bridge
4745 
`timescale 1ns/1ns
4746 
`define MODULE wb_adr_inc
4747 85 unneback 
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
4748 75 unneback 
`undef MODULE
4749 83 unneback 
parameter adr_width = 10;
4750 
parameter max_burst_width = 4;
4751 85 unneback 
input cyc_i, stb_i, we_i;
4752 83 unneback 
input [2:0] cti_i;
4753 
input [1:0] bte_i;
4754 
input [adr_width-1:0] adr_i;
4755 
output [adr_width-1:0] adr_o;
4756 
output ack_o;
4757 
input clk, rst;
4758 75 unneback 
 
4759 83 unneback 
reg [adr_width-1:0] adr;
4760 90 unneback 
wire [max_burst_width-1:0] to_adr;
4761 91 unneback 
reg [max_burst_width-1:0] last_adr;
4762 92 unneback 
reg last_cycle;
4763 
localparam idle_or_eoc = 1'b0;
4764 
localparam cyc_or_ws   = 1'b1;
4765 90 unneback 
 
4766 91 unneback 
always @ (posedge clk or posedge rst)
4767 
if (rst)
4768 
    last_adr <= {max_burst_width{1'b0}};
4769 
else
4770 
    if (stb_i)
4771 92 unneback 
        last_adr <=adr_o[max_burst_width-1:0];
4772 91 unneback 
 
4773 83 unneback 
generate
4774 
if (max_burst_width==0) begin : inst_0
4775 97 unneback 
 
4776 
        reg ack_o;
4777 
        assign adr_o = adr_i;
4778 
        always @ (posedge clk or posedge rst)
4779 
        if (rst)
4780 
            ack_o <= 1'b0;
4781 
        else
4782 
            ack_o <= cyc_i & stb_i & !ack_o;
4783 
 
4784 83 unneback 
end else begin
4785 
 
4786 
    always @ (posedge clk or posedge rst)
4787 
    if (rst)
4788 92 unneback 
        last_cycle <= idle_or_eoc;
4789 83 unneback 
    else
4790 92 unneback 
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
4791 
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
4792 
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
4793 
                      cyc_or_ws; // cyc
4794 
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
4795 85 unneback 
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
4796 91 unneback 
                                        (!stb_i) ? last_adr :
4797 92 unneback 
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
4798 85 unneback 
                                        adr[max_burst_width-1:0];
4799 92 unneback 
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
4800 97 unneback 
 
4801 83 unneback 
end
4802 
endgenerate
4803 
 
4804 
generate
4805 
if (max_burst_width==2) begin : inst_2
4806 
    always @ (posedge clk or posedge rst)
4807 
    if (rst)
4808 
        adr <= 2'h0;
4809 
    else
4810 
        if (cyc_i & stb_i)
4811 
            adr[1:0] <= to_adr[1:0] + 2'd1;
4812 75 unneback 
        else
4813 83 unneback 
            adr <= to_adr[1:0];
4814 
end
4815 
endgenerate
4816 
 
4817 
generate
4818 
if (max_burst_width==3) begin : inst_3
4819 
    always @ (posedge clk or posedge rst)
4820 
    if (rst)
4821 
        adr <= 3'h0;
4822 
    else
4823 
        if (cyc_i & stb_i)
4824 
            case (bte_i)
4825 
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
4826 
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
4827 75 unneback 
            endcase
4828 83 unneback 
        else
4829 
            adr <= to_adr[2:0];
4830 
end
4831 
endgenerate
4832 
 
4833 
generate
4834 
if (max_burst_width==4) begin : inst_4
4835 
    always @ (posedge clk or posedge rst)
4836 
    if (rst)
4837 
        adr <= 4'h0;
4838 
    else
4839 91 unneback 
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
4840 83 unneback 
            case (bte_i)
4841 
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
4842 
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
4843 
            default: adr[3:0] <= to_adr + 4'd1;
4844 
            endcase
4845 
        else
4846 
            adr <= to_adr[3:0];
4847 
end
4848 
endgenerate
4849 
 
4850 
generate
4851 
if (adr_width > max_burst_width) begin : pass_through
4852 
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
4853 
end
4854 
endgenerate
4855 
 
4856 
endmodule
4857 75 unneback 
`endif
4858 
 
4859 40 unneback 
`ifdef WB3WB3_BRIDGE
4860 12 unneback 
// async wb3 - wb3 bridge
4861 
`timescale 1ns/1ns
4862 40 unneback 
`define MODULE wb3wb3_bridge
4863 
module `BASE`MODULE (
4864 
`undef MODULE
4865 12 unneback 
        // wishbone slave side
4866 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4867 
        // wishbone master side
4868 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4869 
 
4870 95 unneback 
parameter style = "FIFO"; // valid: simple, FIFO
4871 
parameter addr_width = 4;
4872 
 
4873 12 unneback 
input [31:0] wbs_dat_i;
4874 
input [31:2] wbs_adr_i;
4875 
input [3:0]  wbs_sel_i;
4876 
input [1:0]  wbs_bte_i;
4877 
input [2:0]  wbs_cti_i;
4878 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4879 
output [31:0] wbs_dat_o;
4880 14 unneback 
output wbs_ack_o;
4881 12 unneback 
input wbs_clk, wbs_rst;
4882 
 
4883 
output [31:0] wbm_dat_o;
4884 
output reg [31:2] wbm_adr_o;
4885 
output [3:0]  wbm_sel_o;
4886 
output reg [1:0]  wbm_bte_o;
4887 
output reg [2:0]  wbm_cti_o;
4888 14 unneback 
output reg wbm_we_o;
4889 
output wbm_cyc_o;
4890 12 unneback 
output wbm_stb_o;
4891 
input [31:0]  wbm_dat_i;
4892 
input wbm_ack_i;
4893 
input wbm_clk, wbm_rst;
4894 
 
4895 
// bte
4896 
parameter linear       = 2'b00;
4897 
parameter wrap4        = 2'b01;
4898 
parameter wrap8        = 2'b10;
4899 
parameter wrap16       = 2'b11;
4900 
// cti
4901 
parameter classic      = 3'b000;
4902 
parameter incburst     = 3'b010;
4903 
parameter endofburst   = 3'b111;
4904 
 
4905 95 unneback 
localparam wbs_adr  = 1'b0;
4906 
localparam wbs_data = 1'b1;
4907 12 unneback 
 
4908 95 unneback 
localparam wbm_adr0      = 2'b00;
4909 
localparam wbm_adr1      = 2'b01;
4910 
localparam wbm_data      = 2'b10;
4911 
localparam wbm_data_wait = 2'b11;
4912 12 unneback 
 
4913 
reg [1:0] wbs_bte_reg;
4914 
reg wbs;
4915 
wire wbs_eoc_alert, wbm_eoc_alert;
4916 
reg wbs_eoc, wbm_eoc;
4917 
reg [1:0] wbm;
4918 
 
4919 14 unneback 
wire [1:16] wbs_count, wbm_count;
4920 12 unneback 
 
4921 
wire [35:0] a_d, a_q, b_d, b_q;
4922 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4923 
reg a_rd_reg;
4924 
wire b_rd_adr, b_rd_data;
4925 14 unneback 
wire b_rd_data_reg;
4926 
wire [35:0] temp;
4927 12 unneback 
 
4928 
`define WE 5
4929 
`define BTE 4:3
4930 
`define CTI 2:0
4931 
 
4932 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4933 
always @ (posedge wbs_clk or posedge wbs_rst)
4934 
if (wbs_rst)
4935 
        wbs_eoc <= 1'b0;
4936 
else
4937 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4938 78 unneback 
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
4939 12 unneback 
        else if (wbs_eoc_alert & (a_rd | a_wr))
4940 
                wbs_eoc <= 1'b1;
4941 
 
4942 40 unneback 
`define MODULE cnt_shreg_ce_clear
4943 
`BASE`MODULE # ( .length(16))
4944 
`undef MODULE
4945 12 unneback 
    cnt0 (
4946 
        .cke(wbs_ack_o),
4947 
        .clear(wbs_eoc),
4948 
        .q(wbs_count),
4949 
        .rst(wbs_rst),
4950 
        .clk(wbs_clk));
4951 
 
4952 
always @ (posedge wbs_clk or posedge wbs_rst)
4953 
if (wbs_rst)
4954 
        wbs <= wbs_adr;
4955 
else
4956 75 unneback 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
4957 12 unneback 
                wbs <= wbs_data;
4958 
        else if (wbs_eoc & wbs_ack_o)
4959 
                wbs <= wbs_adr;
4960 
 
4961 
// wbs FIFO
4962 75 unneback 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
4963 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
4964 12 unneback 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4965 
              1'b0;
4966 
assign a_rd = !a_fifo_empty;
4967 
always @ (posedge wbs_clk or posedge wbs_rst)
4968 
if (wbs_rst)
4969 
        a_rd_reg <= 1'b0;
4970 
else
4971 
        a_rd_reg <= a_rd;
4972 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4973 
 
4974 
assign wbs_dat_o = a_q[35:4];
4975 
 
4976 
always @ (posedge wbs_clk or posedge wbs_rst)
4977 
if (wbs_rst)
4978 13 unneback 
        wbs_bte_reg <= 2'b00;
4979 12 unneback 
else
4980 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
4981 12 unneback 
 
4982 
// wbm FIFO
4983 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4984 
always @ (posedge wbm_clk or posedge wbm_rst)
4985 
if (wbm_rst)
4986 
        wbm_eoc <= 1'b0;
4987 
else
4988 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4989 
                wbm_eoc <= b_q[`BTE] == linear;
4990 
        else if (wbm_eoc_alert & wbm_ack_i)
4991 
                wbm_eoc <= 1'b1;
4992 
 
4993 
always @ (posedge wbm_clk or posedge wbm_rst)
4994 
if (wbm_rst)
4995 
        wbm <= wbm_adr0;
4996 
else
4997 33 unneback 
/*
4998 12 unneback 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
4999 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
5000 
        (wbm==wbm_adr1 & !wbm_we_o) |
5001 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
5002 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
5003 33 unneback 
*/
5004 
    case (wbm)
5005 
    wbm_adr0:
5006 
        if (!b_fifo_empty)
5007 
            wbm <= wbm_adr1;
5008 
    wbm_adr1:
5009 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
5010 
            wbm <= wbm_data;
5011 
    wbm_data:
5012 
        if (wbm_ack_i & wbm_eoc)
5013 
            wbm <= wbm_adr0;
5014 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
5015 
            wbm <= wbm_data_wait;
5016 
    wbm_data_wait:
5017 
        if (!b_fifo_empty)
5018 
            wbm <= wbm_data;
5019 
    endcase
5020 12 unneback 
 
5021 
assign b_d = {wbm_dat_i,4'b1111};
5022 
assign b_wr = !wbm_we_o & wbm_ack_i;
5023 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
5024 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
5025 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
5026 33 unneback 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
5027 12 unneback 
                   1'b0;
5028 
assign b_rd = b_rd_adr | b_rd_data;
5029 
 
5030 40 unneback 
`define MODULE dff
5031 
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
5032 
`undef MODULE
5033 
`define MODULE dff_ce
5034 
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
5035 
`undef MODULE
5036 12 unneback 
 
5037 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
5038 
 
5039 40 unneback 
`define MODULE cnt_shreg_ce_clear
5040 42 unneback 
`BASE`MODULE # ( .length(16))
5041 40 unneback 
`undef MODULE
5042 12 unneback 
    cnt1 (
5043 
        .cke(wbm_ack_i),
5044 
        .clear(wbm_eoc),
5045 
        .q(wbm_count),
5046 
        .rst(wbm_rst),
5047 
        .clk(wbm_clk));
5048 
 
5049 33 unneback 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
5050 
assign wbm_stb_o = (wbm==wbm_data);
5051 12 unneback 
 
5052 
always @ (posedge wbm_clk or posedge wbm_rst)
5053 
if (wbm_rst)
5054 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
5055 
else begin
5056 
        if (wbm==wbm_adr0 & !b_fifo_empty)
5057 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
5058 
        else if (wbm_eoc_alert & wbm_ack_i)
5059 
                wbm_cti_o <= endofburst;
5060 
end
5061 
 
5062 
//async_fifo_dw_simplex_top
5063 40 unneback 
`define MODULE fifo_2r2w_async_simplex
5064 
`BASE`MODULE
5065 
`undef MODULE
5066 12 unneback 
# ( .data_width(36), .addr_width(addr_width))
5067 
fifo (
5068 
    // a side
5069 
    .a_d(a_d),
5070 
    .a_wr(a_wr),
5071 
    .a_fifo_full(a_fifo_full),
5072 
    .a_q(a_q),
5073 
    .a_rd(a_rd),
5074 
    .a_fifo_empty(a_fifo_empty),
5075 
    .a_clk(wbs_clk),
5076 
    .a_rst(wbs_rst),
5077 
    // b side
5078 
    .b_d(b_d),
5079 
    .b_wr(b_wr),
5080 
    .b_fifo_full(b_fifo_full),
5081 
    .b_q(b_q),
5082 
    .b_rd(b_rd),
5083 
    .b_fifo_empty(b_fifo_empty),
5084 
    .b_clk(wbm_clk),
5085 
    .b_rst(wbm_rst)
5086 
    );
5087 
 
5088 
endmodule
5089 40 unneback 
`undef WE
5090 
`undef BTE
5091 
`undef CTI
5092 
`endif
5093 17 unneback 
 
5094 75 unneback 
`ifdef WB3AVALON_BRIDGE
5095 
`define MODULE wb3avalon_bridge
5096 
module `BASE`MODULE (
5097 
`undef MODULE
5098 
        // wishbone slave side
5099 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5100 77 unneback 
        // avalon master side
5101 75 unneback 
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
5102 
 
5103 85 unneback 
parameter linewrapburst = 1'b0;
5104 
 
5105 75 unneback 
input [31:0] wbs_dat_i;
5106 
input [31:2] wbs_adr_i;
5107 
input [3:0]  wbs_sel_i;
5108 
input [1:0]  wbs_bte_i;
5109 
input [2:0]  wbs_cti_i;
5110 83 unneback 
input wbs_we_i;
5111 
input wbs_cyc_i;
5112 
input wbs_stb_i;
5113 75 unneback 
output [31:0] wbs_dat_o;
5114 
output wbs_ack_o;
5115 
input wbs_clk, wbs_rst;
5116 
 
5117 
input [31:0] readdata;
5118 
output [31:0] writedata;
5119 
output [31:2] address;
5120 
output [3:0]  be;
5121 
output write;
5122 81 unneback 
output read;
5123 75 unneback 
output beginbursttransfer;
5124 
output [3:0] burstcount;
5125 
input readdatavalid;
5126 
input waitrequest;
5127 
input clk;
5128 
input rst;
5129 
 
5130 
wire [1:0] wbm_bte_o;
5131 
wire [2:0] wbm_cti_o;
5132 
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
5133 
reg last_cyc;
5134 79 unneback 
reg [3:0] counter;
5135 82 unneback 
reg read_busy;
5136 75 unneback 
 
5137 
always @ (posedge clk or posedge rst)
5138 
if (rst)
5139 
    last_cyc <= 1'b0;
5140 
else
5141 
    last_cyc <= wbm_cyc_o;
5142 
 
5143 79 unneback 
always @ (posedge clk or posedge rst)
5144 
if (rst)
5145 82 unneback 
    read_busy <= 1'b0;
5146 79 unneback 
else
5147 82 unneback 
    if (read & !waitrequest)
5148 
        read_busy <= 1'b1;
5149 
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
5150 
        read_busy <= 1'b0;
5151 
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
5152 81 unneback 
 
5153 75 unneback 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
5154 
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
5155 
                    (wbm_bte_o==2'b10) ? 4'd8 :
5156 78 unneback 
                    (wbm_bte_o==2'b11) ? 4'd16:
5157 
                    4'd1;
5158 82 unneback 
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
5159 75 unneback 
 
5160 79 unneback 
always @ (posedge clk or posedge rst)
5161 
if (rst) begin
5162 
    counter <= 4'd0;
5163 
end else
5164 80 unneback 
    if (wbm_we_o) begin
5165 
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
5166 85 unneback 
            counter <= burstcount -4'd1;
5167 80 unneback 
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
5168 
            counter <= burstcount;
5169 
        end else if (!waitrequest & wbm_stb_o) begin
5170 
            counter <= counter - 4'd1;
5171 
        end
5172 82 unneback 
    end
5173 81 unneback 
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
5174 79 unneback 
 
5175 75 unneback 
`define MODULE wb3wb3_bridge
5176 77 unneback 
`BASE`MODULE wbwb3inst (
5177 75 unneback 
`undef MODULE
5178 
    // wishbone slave side
5179 
    .wbs_dat_i(wbs_dat_i),
5180 
    .wbs_adr_i(wbs_adr_i),
5181 
    .wbs_sel_i(wbs_sel_i),
5182 
    .wbs_bte_i(wbs_bte_i),
5183 
    .wbs_cti_i(wbs_cti_i),
5184 
    .wbs_we_i(wbs_we_i),
5185 
    .wbs_cyc_i(wbs_cyc_i),
5186 
    .wbs_stb_i(wbs_stb_i),
5187 
    .wbs_dat_o(wbs_dat_o),
5188 
    .wbs_ack_o(wbs_ack_o),
5189 
    .wbs_clk(wbs_clk),
5190 
    .wbs_rst(wbs_rst),
5191 
    // wishbone master side
5192 
    .wbm_dat_o(writedata),
5193 78 unneback 
    .wbm_adr_o(address),
5194 75 unneback 
    .wbm_sel_o(be),
5195 
    .wbm_bte_o(wbm_bte_o),
5196 
    .wbm_cti_o(wbm_cti_o),
5197 
    .wbm_we_o(wbm_we_o),
5198 
    .wbm_cyc_o(wbm_cyc_o),
5199 
    .wbm_stb_o(wbm_stb_o),
5200 
    .wbm_dat_i(readdata),
5201 
    .wbm_ack_i(wbm_ack_i),
5202 
    .wbm_clk(clk),
5203 
    .wbm_rst(rst));
5204 
 
5205 
 
5206 
endmodule
5207 
`endif
5208 
 
5209 40 unneback 
`ifdef WB3_ARBITER_TYPE1
5210 
`define MODULE wb3_arbiter_type1
5211 42 unneback 
module `BASE`MODULE (
5212 40 unneback 
`undef MODULE
5213 39 unneback 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5214 
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
5215 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5216 
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
5217 
    wb_clk, wb_rst
5218 
);
5219 
 
5220 
parameter nr_of_ports = 3;
5221 
parameter adr_size = 26;
5222 
parameter adr_lo   = 2;
5223 
parameter dat_size = 32;
5224 
parameter sel_size = dat_size/8;
5225 
 
5226 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
5227 
localparam dw = dat_size * nr_of_ports;
5228 
localparam sw = sel_size * nr_of_ports;
5229 
localparam cw = 3 * nr_of_ports;
5230 
localparam bw = 2 * nr_of_ports;
5231 
 
5232 
input  [dw-1:0] wbm_dat_o;
5233 
input  [aw-1:0] wbm_adr_o;
5234 
input  [sw-1:0] wbm_sel_o;
5235 
input  [cw-1:0] wbm_cti_o;
5236 
input  [bw-1:0] wbm_bte_o;
5237 
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
5238 
output [dw-1:0] wbm_dat_i;
5239 
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
5240 
 
5241 
output [dat_size-1:0] wbs_dat_i;
5242 
output [adr_size-1:adr_lo] wbs_adr_i;
5243 
output [sel_size-1:0] wbs_sel_i;
5244 
output [2:0] wbs_cti_i;
5245 
output [1:0] wbs_bte_i;
5246 
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
5247 
input  [dat_size-1:0] wbs_dat_o;
5248 
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
5249 
 
5250 
input wb_clk, wb_rst;
5251 
 
5252 44 unneback 
reg  [nr_of_ports-1:0] select;
5253 39 unneback 
wire [nr_of_ports-1:0] state;
5254 
wire [nr_of_ports-1:0] eoc; // end-of-cycle
5255 
wire [nr_of_ports-1:0] sel;
5256 
wire idle;
5257 
 
5258 
genvar i;
5259 
 
5260 
assign idle = !(|state);
5261 
 
5262 
generate
5263 
if (nr_of_ports == 2) begin
5264 
 
5265 
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
5266 
 
5267 
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5268 
 
5269 44 unneback 
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5270 
 
5271 
    always @ (idle or wbm_cyc_o)
5272 
    if (idle)
5273 
        casex (wbm_cyc_o)
5274 
        2'b1x : select = 2'b10;
5275 
        2'b01 : select = 2'b01;
5276 
        default : select = {nr_of_ports{1'b0}};
5277 
        endcase
5278 
    else
5279 
        select = {nr_of_ports{1'b0}};
5280 
 
5281 39 unneback 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5282 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5283 
 
5284 
end
5285 
endgenerate
5286 
 
5287 
generate
5288 
if (nr_of_ports == 3) begin
5289 
 
5290 
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5291 
 
5292 
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5293 
 
5294 44 unneback 
    always @ (idle or wbm_cyc_o)
5295 
    if (idle)
5296 
        casex (wbm_cyc_o)
5297 
        3'b1xx : select = 3'b100;
5298 
        3'b01x : select = 3'b010;
5299 
        3'b001 : select = 3'b001;
5300 
        default : select = {nr_of_ports{1'b0}};
5301 
        endcase
5302 
    else
5303 
        select = {nr_of_ports{1'b0}};
5304 
 
5305 
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5306 39 unneback 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5307 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5308 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5309 
 
5310 
end
5311 
endgenerate
5312 
 
5313 
generate
5314 44 unneback 
if (nr_of_ports == 4) begin
5315 
 
5316 
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5317 
 
5318 
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5319 
 
5320 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5321 
 
5322 
    always @ (idle or wbm_cyc_o)
5323 
    if (idle)
5324 
        casex (wbm_cyc_o)
5325 
        4'b1xxx : select = 4'b1000;
5326 
        4'b01xx : select = 4'b0100;
5327 
        4'b001x : select = 4'b0010;
5328 
        4'b0001 : select = 4'b0001;
5329 
        default : select = {nr_of_ports{1'b0}};
5330 
        endcase
5331 
    else
5332 
        select = {nr_of_ports{1'b0}};
5333 
 
5334 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5335 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5336 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5337 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5338 
 
5339 
end
5340 
endgenerate
5341 
 
5342 
generate
5343 
if (nr_of_ports == 5) begin
5344 
 
5345 
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5346 
 
5347 
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5348 
 
5349 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5350 
 
5351 
    always @ (idle or wbm_cyc_o)
5352 
    if (idle)
5353 
        casex (wbm_cyc_o)
5354 
        5'b1xxxx : select = 5'b10000;
5355 
        5'b01xxx : select = 5'b01000;
5356 
        5'b001xx : select = 5'b00100;
5357 
        5'b0001x : select = 5'b00010;
5358 
        5'b00001 : select = 5'b00001;
5359 
        default : select = {nr_of_ports{1'b0}};
5360 
        endcase
5361 
    else
5362 
        select = {nr_of_ports{1'b0}};
5363 
 
5364 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5365 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5366 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5367 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5368 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5369 
 
5370 
end
5371 
endgenerate
5372 
 
5373 
generate
5374 67 unneback 
if (nr_of_ports == 6) begin
5375 
 
5376 
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5377 
 
5378 
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5379 
 
5380 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5381 
 
5382 
    always @ (idle or wbm_cyc_o)
5383 
    if (idle)
5384 
        casex (wbm_cyc_o)
5385 
        6'b1xxxxx : select = 6'b100000;
5386 
        6'b01xxxx : select = 6'b010000;
5387 
        6'b001xxx : select = 6'b001000;
5388 
        6'b0001xx : select = 6'b000100;
5389 
        6'b00001x : select = 6'b000010;
5390 
        6'b000001 : select = 6'b000001;
5391 
        default : select = {nr_of_ports{1'b0}};
5392 
        endcase
5393 
    else
5394 
        select = {nr_of_ports{1'b0}};
5395 
 
5396 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5397 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5398 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5399 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5400 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5401 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5402 
 
5403 
end
5404 
endgenerate
5405 
 
5406 
generate
5407 
if (nr_of_ports == 7) begin
5408 
 
5409 
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5410 
 
5411 
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5412 
 
5413 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5414 
 
5415 
    always @ (idle or wbm_cyc_o)
5416 
    if (idle)
5417 
        casex (wbm_cyc_o)
5418 
        7'b1xxxxxx : select = 7'b1000000;
5419 
        7'b01xxxxx : select = 7'b0100000;
5420 
        7'b001xxxx : select = 7'b0010000;
5421 
        7'b0001xxx : select = 7'b0001000;
5422 
        7'b00001xx : select = 7'b0000100;
5423 
        7'b000001x : select = 7'b0000010;
5424 
        7'b0000001 : select = 7'b0000001;
5425 
        default : select = {nr_of_ports{1'b0}};
5426 
        endcase
5427 
    else
5428 
        select = {nr_of_ports{1'b0}};
5429 
 
5430 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5431 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5432 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5433 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5434 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5435 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5436 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5437 
 
5438 
end
5439 
endgenerate
5440 
 
5441 
generate
5442 
if (nr_of_ports == 8) begin
5443 
 
5444 
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5445 
 
5446 
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5447 
 
5448 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5449 
 
5450 
    always @ (idle or wbm_cyc_o)
5451 
    if (idle)
5452 
        casex (wbm_cyc_o)
5453 
        8'b1xxxxxxx : select = 8'b10000000;
5454 
        8'b01xxxxxx : select = 8'b01000000;
5455 
        8'b001xxxxx : select = 8'b00100000;
5456 
        8'b0001xxxx : select = 8'b00010000;
5457 
        8'b00001xxx : select = 8'b00001000;
5458 
        8'b000001xx : select = 8'b00000100;
5459 
        8'b0000001x : select = 8'b00000010;
5460 
        8'b00000001 : select = 8'b00000001;
5461 
        default : select = {nr_of_ports{1'b0}};
5462 
        endcase
5463 
    else
5464 
        select = {nr_of_ports{1'b0}};
5465 
 
5466 
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
5467 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5468 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5469 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5470 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5471 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5472 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5473 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5474 
 
5475 
end
5476 
endgenerate
5477 
 
5478 
generate
5479 63 unneback 
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
5480 42 unneback 
`define MODULE spr
5481 
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
5482 
`undef MODULE
5483 39 unneback 
end
5484 
endgenerate
5485 
 
5486 
    assign sel = select | state;
5487 
 
5488 40 unneback 
`define MODULE mux_andor
5489 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
5490 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
5491 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
5492 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
5493 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
5494 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
5495 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
5496 
`undef MODULE
5497 39 unneback 
    assign wbs_cyc_i = |sel;
5498 
 
5499 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
5500 
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
5501 
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
5502 
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
5503 
 
5504 
endmodule
5505 40 unneback 
`endif
5506 39 unneback 
 
5507 60 unneback 
`ifdef WB_B3_RAM_BE
5508 49 unneback 
// WB RAM with byte enable
5509 59 unneback 
`define MODULE wb_b3_ram_be
5510 
module `BASE`MODULE (
5511 
`undef MODULE
5512 69 unneback 
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5513 
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
5514 59 unneback 
 
5515 68 unneback 
parameter adr_size = 16;
5516 85 unneback 
parameter mem_size = 1<<adr_size;
5517 60 unneback 
parameter dat_size = 32;
5518 83 unneback 
parameter max_burst_width = 4;
5519 60 unneback 
parameter memory_init = 1;
5520 
parameter memory_file = "vl_ram.vmem";
5521 59 unneback 
 
5522 85 unneback 
localparam aw = (adr_size);
5523 69 unneback 
localparam dw = dat_size;
5524 
localparam sw = dat_size/8;
5525 
localparam cw = 3;
5526 
localparam bw = 2;
5527 60 unneback 
 
5528 70 unneback 
input [dw-1:0] wbs_dat_i;
5529 
input [aw-1:0] wbs_adr_i;
5530 
input [cw-1:0] wbs_cti_i;
5531 
input [bw-1:0] wbs_bte_i;
5532 
input [sw-1:0] wbs_sel_i;
5533 
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5534 
output [dw-1:0] wbs_dat_o;
5535 
output wbs_ack_o;
5536 71 unneback 
input wb_clk, wb_rst;
5537 59 unneback 
 
5538 83 unneback 
wire [aw-1:0] adr;
5539 59 unneback 
 
5540 60 unneback 
`define MODULE ram_be
5541 
`BASE`MODULE # (
5542 
    .data_width(dat_size),
5543 83 unneback 
    .addr_width(aw),
5544 69 unneback 
    .mem_size(mem_size),
5545 68 unneback 
    .memory_init(memory_init),
5546 
    .memory_file(memory_file))
5547 60 unneback 
ram0(
5548 
`undef MODULE
5549 
    .d(wbs_dat_i),
5550 83 unneback 
    .adr(adr),
5551 60 unneback 
    .be(wbs_sel_i),
5552 86 unneback 
    .we(wbs_we_i & wbs_ack_o),
5553 60 unneback 
    .q(wbs_dat_o),
5554 
    .clk(wb_clk)
5555 
);
5556 
 
5557 83 unneback 
`define MODULE wb_adr_inc
5558 
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
5559 
    .cyc_i(wbs_cyc_i),
5560 
    .stb_i(wbs_stb_i),
5561 
    .cti_i(wbs_cti_i),
5562 
    .bte_i(wbs_bte_i),
5563 
    .adr_i(wbs_adr_i),
5564 85 unneback 
    .we_i(wbs_we_i),
5565 83 unneback 
    .ack_o(wbs_ack_o),
5566 
    .adr_o(adr),
5567 
    .clk(wb_clk),
5568 
    .rst(wb_rst));
5569 
`undef MODULE
5570 60 unneback 
 
5571 59 unneback 
endmodule
5572 
`endif
5573 
 
5574 
`ifdef WB_B4_RAM_BE
5575 
// WB RAM with byte enable
5576 49 unneback 
`define MODULE wb_b4_ram_be
5577 
module `BASE`MODULE (
5578 
`undef MODULE
5579 
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
5580 52 unneback 
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
5581 49 unneback 
 
5582 
    parameter dat_width = 32;
5583 
    parameter adr_width = 8;
5584 
 
5585 
input [dat_width-1:0] wb_dat_i;
5586 
input [adr_width-1:0] wb_adr_i;
5587 
input [dat_width/8-1:0] wb_sel_i;
5588 
input wb_we_i, wb_stb_i, wb_cyc_i;
5589 
output [dat_width-1:0] wb_dat_o;
5590 51 unneback 
reg [dat_width-1:0] wb_dat_o;
5591 52 unneback 
output wb_stall_o;
5592 49 unneback 
output wb_ack_o;
5593 
reg wb_ack_o;
5594 
input wb_clk, wb_rst;
5595 
 
5596 56 unneback 
wire [dat_width/8-1:0] cke;
5597 
 
5598 49 unneback 
generate
5599 
if (dat_width==32) begin
5600 51 unneback 
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
5601 
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
5602 
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
5603 
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
5604 56 unneback 
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
5605 49 unneback 
    always @ (posedge wb_clk)
5606 
    begin
5607 56 unneback 
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
5608 
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
5609 
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
5610 
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
5611 49 unneback 
    end
5612 59 unneback 
    always @ (posedge wb_clk or posedge wb_rst)
5613 
    begin
5614 
        if (wb_rst)
5615 
            wb_dat_o <= 32'h0;
5616 
        else
5617 
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
5618 
    end
5619 49 unneback 
end
5620 
endgenerate
5621 
 
5622 52 unneback 
always @ (posedge wb_clk or posedge wb_rst)
5623 55 unneback 
if (wb_rst)
5624 52 unneback 
    wb_ack_o <= 1'b0;
5625 
else
5626 54 unneback 
    wb_ack_o <= wb_stb_i & wb_cyc_i;
5627 52 unneback 
 
5628 
assign wb_stall_o = 1'b0;
5629 
 
5630 49 unneback 
endmodule
5631 
`endif
5632 
 
5633 48 unneback 
`ifdef WB_B4_ROM
5634 
// WB ROM
5635 
`define MODULE wb_b4_rom
5636 
module `BASE`MODULE (
5637 
`undef MODULE
5638 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5639 
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
5640 
 
5641 
    parameter dat_width = 32;
5642 
    parameter dat_default = 32'h15000000;
5643 
    parameter adr_width = 32;
5644 
 
5645 
/*
5646 
`ifndef ROM
5647 
`define ROM "rom.v"
5648 
`endif
5649 
*/
5650 
    input [adr_width-1:2]   wb_adr_i;
5651 
    input                   wb_stb_i;
5652 
    input                   wb_cyc_i;
5653 
    output [dat_width-1:0]  wb_dat_o;
5654 
    reg [dat_width-1:0]     wb_dat_o;
5655 
    output                  wb_ack_o;
5656 
    reg                     wb_ack_o;
5657 
    output                  stall_o;
5658 
    input                   wb_clk;
5659 
    input                   wb_rst;
5660 
 
5661 
always @ (posedge wb_clk or posedge wb_rst)
5662 
    if (wb_rst)
5663 
        wb_dat_o <= {dat_width{1'b0}};
5664 
    else
5665 
         case (wb_adr_i[adr_width-1:2])
5666 
`ifdef ROM
5667 
`include `ROM
5668 
`endif
5669 
           default:
5670 
             wb_dat_o <= dat_default;
5671 
 
5672 
         endcase // case (wb_adr_i)
5673 
 
5674 
 
5675 
always @ (posedge wb_clk or posedge wb_rst)
5676 
    if (wb_rst)
5677 
        wb_ack_o <= 1'b0;
5678 
    else
5679 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
5680 
 
5681 
assign stall_o = 1'b0;
5682 
 
5683 
endmodule
5684 
`endif
5685 
 
5686 
 
5687 40 unneback 
`ifdef WB_BOOT_ROM
5688 17 unneback 
// WB ROM
5689 40 unneback 
`define MODULE wb_boot_rom
5690 
module `BASE`MODULE (
5691 
`undef MODULE
5692 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5693 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
5694 17 unneback 
 
5695 18 unneback 
    parameter adr_hi = 31;
5696 
    parameter adr_lo = 28;
5697 
    parameter adr_sel = 4'hf;
5698 
    parameter addr_width = 5;
5699 33 unneback 
/*
5700 17 unneback 
`ifndef BOOT_ROM
5701 
`define BOOT_ROM "boot_rom.v"
5702 
`endif
5703 33 unneback 
*/
5704 18 unneback 
    input [adr_hi:2]    wb_adr_i;
5705 
    input               wb_stb_i;
5706 
    input               wb_cyc_i;
5707 
    output [31:0]        wb_dat_o;
5708 
    output              wb_ack_o;
5709 
    output              hit_o;
5710 
    input               wb_clk;
5711 
    input               wb_rst;
5712 
 
5713 
    wire hit;
5714 
    reg [31:0] wb_dat;
5715 
    reg wb_ack;
5716 
 
5717 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
5718 17 unneback 
 
5719 
always @ (posedge wb_clk or posedge wb_rst)
5720 
    if (wb_rst)
5721 18 unneback 
        wb_dat <= 32'h15000000;
5722 17 unneback 
    else
5723 18 unneback 
         case (wb_adr_i[addr_width-1:2])
5724 33 unneback 
`ifdef BOOT_ROM
5725 17 unneback 
`include `BOOT_ROM
5726 33 unneback 
`endif
5727 17 unneback 
           /*
5728 
            // Zero r0 and jump to 0x00000100
5729 18 unneback 
 
5730 
            1 : wb_dat <= 32'hA8200000;
5731 
            2 : wb_dat <= 32'hA8C00100;
5732 
            3 : wb_dat <= 32'h44003000;
5733 
            4 : wb_dat <= 32'h15000000;
5734 17 unneback 
            */
5735 
           default:
5736 18 unneback 
             wb_dat <= 32'h00000000;
5737 17 unneback 
 
5738 
         endcase // case (wb_adr_i)
5739 
 
5740 
 
5741 
always @ (posedge wb_clk or posedge wb_rst)
5742 
    if (wb_rst)
5743 18 unneback 
        wb_ack <= 1'b0;
5744 17 unneback 
    else
5745 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
5746 17 unneback 
 
5747 18 unneback 
assign hit_o = hit;
5748 
assign wb_dat_o = wb_dat & {32{wb_ack}};
5749 
assign wb_ack_o = wb_ack;
5750 
 
5751 17 unneback 
endmodule
5752 40 unneback 
`endif
5753 32 unneback 
 
5754 92 unneback 
`ifdef WB_B3_DPRAM
5755 
`define MODULE wb_b3_dpram
5756 40 unneback 
module `BASE`MODULE (
5757 
`undef MODULE
5758 32 unneback 
        // wishbone slave side a
5759 92 unneback 
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
5760 32 unneback 
        wbsa_clk, wbsa_rst,
5761 92 unneback 
        // wishbone slave side b
5762 
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
5763 32 unneback 
        wbsb_clk, wbsb_rst);
5764 
 
5765 92 unneback 
parameter data_width_a = 32;
5766 
parameter data_width_b = data_width_a;
5767 
parameter addr_width_a = 8;
5768 
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
5769 
   parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
5770 
parameter max_burst_width_a = 4;
5771 
parameter max_burst_width_b = max_burst_width_a;
5772 32 unneback 
 
5773 92 unneback 
input [data_width_a-1:0] wbsa_dat_i;
5774 
input [addr_width_a-1:0] wbsa_adr_i;
5775 
input [data_width_a/8-1:0] wbsa_sel_i;
5776 
input [2:0] wbsa_cti_i;
5777 
input [1:0] wbsa_bte_i;
5778 32 unneback 
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
5779 92 unneback 
output [data_width_a-1:0] wbsa_dat_o;
5780 32 unneback 
output wbsa_ack_o;
5781 
input wbsa_clk, wbsa_rst;
5782 
 
5783 92 unneback 
input [data_width_b-1:0] wbsb_dat_i;
5784 
input [addr_width_b-1:0] wbsb_adr_i;
5785 
input [data_width_b/8-1:0] wbsb_sel_i;
5786 
input [2:0] wbsb_cti_i;
5787 
input [1:0] wbsb_bte_i;
5788 32 unneback 
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
5789 92 unneback 
output [data_width_b-1:0] wbsb_dat_o;
5790 32 unneback 
output wbsb_ack_o;
5791 
input wbsb_clk, wbsb_rst;
5792 
 
5793 92 unneback 
wire [addr_width_a-1:0] adr_a;
5794 
wire [addr_width_b-1:0] adr_b;
5795 32 unneback 
 
5796 92 unneback 
`define MODULE wb_adr_inc
5797 
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
5798 
    .cyc_i(wbsa_cyc_i),
5799 
    .stb_i(wbsa_stb_i),
5800 
    .cti_i(wbsa_cti_i),
5801 
    .bte_i(wbsa_bte_i),
5802 
    .adr_i(wbsa_adr_i),
5803 
    .we_i(wbsa_we_i),
5804 
    .ack_o(wbsa_ack_o),
5805 
    .adr_o(adr_a),
5806 
    .clk(wbsa_clk),
5807 
    .rst(wbsa_rst));
5808 
 
5809 
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
5810 
    .cyc_i(wbsb_cyc_i),
5811 
    .stb_i(wbsb_stb_i),
5812 
    .cti_i(wbsb_cti_i),
5813 
    .bte_i(wbsb_bte_i),
5814 
    .adr_i(wbsb_adr_i),
5815 
    .we_i(wbsb_we_i),
5816 
    .ack_o(wbsb_ack_o),
5817 
    .adr_o(adr_b),
5818 
    .clk(wbsb_clk),
5819 
    .rst(wbsb_rst));
5820 40 unneback 
`undef MODULE
5821 92 unneback 
 
5822 
`define MODULE dpram_be_2r2w
5823 
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
5824 
`undef MODULE
5825 
ram_i (
5826 32 unneback 
    .d_a(wbsa_dat_i),
5827 92 unneback 
    .q_a(wbsa_dat_o),
5828 
    .adr_a(adr_a),
5829 
    .be_a(wbsa_sel_i),
5830 
    .we_a(wbsa_we_i & wbsa_ack_o),
5831 32 unneback 
    .clk_a(wbsa_clk),
5832 
    .d_b(wbsb_dat_i),
5833 92 unneback 
    .q_b(wbsb_dat_o),
5834 
    .adr_b(adr_b),
5835 
    .be_b(wbsb_sel_i),
5836 
    .we_b(wbsb_we_i & wbsb_ack_o),
5837 32 unneback 
    .clk_b(wbsb_clk) );
5838 
 
5839 
endmodule
5840 40 unneback 
`endif
5841 94 unneback 
 
5842 97 unneback 
`ifdef WBB3_WBB4_CACHE
5843 
`define MODULE wbb3_wbb4_cache
5844 
module `BASE`MODULE (
5845 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5846 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
5847 
);
5848 
`undef MODULE
5849 
 
5850 
parameter dw_s = 32;
5851 
parameter aw_s = 24;
5852 
parameter dw_m = dw_s;
5853 
parameter aw_m = dw_s * aw_s / dw_m;
5854 
parameter max_burst_width = 4;
5855 
 
5856 
parameter async = 1; // wbs_clk != wbm_clk
5857 
 
5858 
parameter nr_of_ways = 1;
5859 
parameter aw_offset = 4; // 4 => 16 words per cache line
5860 
parameter aw_slot = 10;
5861 
localparam aw_tag = aw_s - aw_tag_mem - aw_offset;
5862 
parameter wbm_burst_size = 4; // valid options 4,8,16
5863 
`define SIZE2WIDTH wbm_burst_size
5864 
localparam wbm_burst_width `SIZE2WIDTH_EXPR
5865 
`undef SIZE2WIDTH
5866 
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
5867 
`define SIZE2WIDTH nr_of_wbm_burst
5868 
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
5869 
`undef SIZE2WIDTH
5870 
input [dw_s-1:0] wbs_dat_i;
5871 
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
5872 
input [dw_s/8-1:0] wbs-sel_i;
5873 
input [2:0] wbs_cti_i;
5874 
input [1:0] wbs_bte_i;
5875 
input wbs_we_i;
5876 
output [dw_s-1:0] wbs_dat_o;
5877 
output wbs_ack_o;
5878 
input wbs_clk, wbs_rst;
5879 
 
5880 
output [dw_m-1:0] wbm_dat_o;
5881 
output [aw_m-1:0] wbm_adr_o;
5882 
output [dw_m/8-1:0] wbm_sel_o;
5883 
output [2:0] wbm_cti_o;
5884 
output [1:0] wbm_bte_o;
5885 
input [dw_m-1:0] wbm_dat_i;
5886 
input wbm_ack_i;
5887 
input wbm_stall_i;
5888 
input wbm_clk, wbm_rst;
5889 
 
5890 
wire dirty, valid;
5891 
wire [aw_tag-1:0] tag;
5892 
wire tag_mem_we;
5893 
wire [aw_tag-1:0] wbs_adr_tag;
5894 
wire [aw_slot-1:0] wbs_adr_slot;
5895 
wire [aw_offset_1:0] wbs_adr_word;
5896 
wire [aw-1:0] wbs_adr;
5897 
 
5898 
reg [1:0] state;
5899 
localparam idle = 2'h0;
5900 
localparam rdwr = 2'h1;
5901 
localparam push = 2'h2;
5902 
localparam pull = 2'h3;
5903 
wire eoc;
5904 
 
5905 
// cdc
5906 
wire done, mem_alert, mem_done;
5907 
 
5908 
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
5909 
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
5910 
 
5911 
`define MODULE ram
5912 
`BASE`MODULE
5913 
    # ( .data_width(aw_tag), .addr_Width(aw_slot))
5914 
    tag_mem ( .d(wbs_adr_slot), .adr(wbs_adr_tag), .we(done), .q(tag), .clk(wbs_clk));
5915 
`undef MODULE
5916 
assign valid = wbs_adr_tag == tag;
5917 
 
5918 
`define MODULE wb_adr_inc
5919 
`BASE`MODULE # ( .adr_width(aw_slot+aw_offset), .max_burst_width(max_burst_width)) adr_inc0 (
5920 
    .cyc_i(wbs_cyc_i),
5921 
    .stb_i(wbs_stb_i & (state==idle | (state==rw & valid))), // throttle depending on valid
5922 
    .cti_i(wbs_cti_i),
5923 
    .bte_i(wbs_bte_i),
5924 
    .adr_i(wbs_adr_i),
5925 
    .we_i (wbs_we_i),
5926 
    .ack_o(wbs_ack_o),
5927 
    .adr_o(wbs_adr),
5928 
    .clk(wbsa_clk),
5929 
    .rst(wbsa_rst));
5930 
`undef MODULE
5931 
 
5932 
`define MODULE dpram_be_2r2w
5933 
`BASE`MODULE
5934 
    # ( .data_width(aw_tag), .addr_Width(aw_slot+aw_offset))
5935 
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr), be_a(wbs_sel_i), .we_a(wbs_cyc_i &  wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
5936 
                .d_b(wbm_dat_i), .adr_b(wbm_adr), be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
5937 
`undef MODULE
5938 
 
5939 
always @ (posedge wbs_clk or posedge wbs_rst)
5940 
if (wbs_rst)
5941 
    case <= idle;
5942 
else
5943 
    case (state)
5944 
    idle:
5945 
        if (wbs_cyc_i)
5946 
            state <= rdwr;
5947 
    rdwr:
5948 
        if (wbs_we_i & valid & eoc)
5949 
            state <= idle;
5950 
        else if (wbs_we_i & !valid)
5951 
            state <= pull;
5952 
        else if (!wbs_we_i & valid & eoc)
5953 
            state <= idle;
5954 
        else if (!wbs_we_i & !valid & !dirty)
5955 
            state <= pull;
5956 
        else if (!wbs_we_i & !valid & dirty)
5957 
            state <= push;
5958 
    push:
5959 
        if (done)
5960 
            state <= rdwr;
5961 
    pull:
5962 
        if (done)
5963 
            state <= rdwr;
5964 
    default: state <= idle;
5965 
    endcase
5966 
 
5967 
 
5968 
// cdc
5969 
generate
5970 
if (async==1) begin : cdc0
5971 
`define MODULE cdc
5972 
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & !valid), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
5973 
`undef MODULE
5974 
end
5975 
else begin : nocdc
5976 
    assign mem_alert = state==rdwr & !valid;
5977 
    assign done = mem_done;
5978 
end
5979 
endgenerate
5980 
 
5981 
always @ (posedge wbm_clk or posedge wbm_rst)
5982 
if (rst)
5983 
    wbm_burst_adr <= {aw_wbm_burst{1'b0}};
5984 
else
5985 
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i))
5986 
        wbm_burst_adr <= wbm_burst_adr + (aw_wbm_burst)'d1
5987 
 
5988 
// FSM generating a number of burts 4 cycles
5989 
// actual number depends on data width ratio
5990 
// nr_of_wbm_burst
5991 
reg [wbm_burst_width-1:0] cnt0;
5992 
reg [nr_of_wbm_burst_width-1:0] cnt1;
5993 
 
5994 
always @ (posedge wbm_clk or posedge wbm_rst)
5995 
if (wbm_rst)
5996 
    {cnt1,cnt0} <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
5997 
else
5998 
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
5999 
        {cnt1,cnt0} <= (nr_of_wbm_burst_width+wbm_burst_width)1'd1;
6000 
 
6001 
 
6002 
endmodule
6003 
`endif
6004 18 unneback 
//////////////////////////////////////////////////////////////////////
6005 
////                                                              ////
6006 
////  Arithmetic functions                                        ////
6007 
////                                                              ////
6008 
////  Description                                                 ////
6009 
////  Arithmetic functions for ALU and DSP                        ////
6010 
////                                                              ////
6011 
////                                                              ////
6012 
////  To Do:                                                      ////
6013 
////   -                                                          ////
6014 
////                                                              ////
6015 
////  Author(s):                                                  ////
6016 
////      - Michael Unneback, unneback@opencores.org              ////
6017 
////        ORSoC AB                                              ////
6018 
////                                                              ////
6019 
//////////////////////////////////////////////////////////////////////
6020 
////                                                              ////
6021 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
6022 
////                                                              ////
6023 
//// This source file may be used and distributed without         ////
6024 
//// restriction provided that this copyright statement is not    ////
6025 
//// removed from the file and that any derivative work contains  ////
6026 
//// the original copyright notice and the associated disclaimer. ////
6027 
////                                                              ////
6028 
//// This source file is free software; you can redistribute it   ////
6029 
//// and/or modify it under the terms of the GNU Lesser General   ////
6030 
//// Public License as published by the Free Software Foundation; ////
6031 
//// either version 2.1 of the License, or (at your option) any   ////
6032 
//// later version.                                               ////
6033 
////                                                              ////
6034 
//// This source is distributed in the hope that it will be       ////
6035 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
6036 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
6037 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
6038 
//// details.                                                     ////
6039 
////                                                              ////
6040 
//// You should have received a copy of the GNU Lesser General    ////
6041 
//// Public License along with this source; if not, download it   ////
6042 
//// from http://www.opencores.org/lgpl.shtml                     ////
6043 
////                                                              ////
6044 
//////////////////////////////////////////////////////////////////////
6045 
 
6046 40 unneback 
`ifdef MULTS
6047 18 unneback 
// signed multiplication
6048 40 unneback 
`define MODULE mults
6049 
module `BASE`MODULE (a,b,p);
6050 
`undef MODULE
6051 18 unneback 
parameter operand_a_width = 18;
6052 
parameter operand_b_width = 18;
6053 
parameter result_hi = 35;
6054 
parameter result_lo = 0;
6055 
input [operand_a_width-1:0] a;
6056 
input [operand_b_width-1:0] b;
6057 
output [result_hi:result_lo] p;
6058 
wire signed [operand_a_width-1:0] ai;
6059 
wire signed [operand_b_width-1:0] bi;
6060 
wire signed [operand_a_width+operand_b_width-1:0] result;
6061 
 
6062 
    assign ai = a;
6063 
    assign bi = b;
6064 
    assign result = ai * bi;
6065 
    assign p = result[result_hi:result_lo];
6066 
 
6067 
endmodule
6068 40 unneback 
`endif
6069 
`ifdef MULTS18X18
6070 
`define MODULE mults18x18
6071 
module `BASE`MODULE (a,b,p);
6072 
`undef MODULE
6073 18 unneback 
input [17:0] a,b;
6074 
output [35:0] p;
6075 
vl_mult
6076 
    # (.operand_a_width(18), .operand_b_width(18))
6077 
    mult0 (.a(a), .b(b), .p(p));
6078 
endmodule
6079 40 unneback 
`endif
6080 18 unneback 
 
6081 40 unneback 
`ifdef MULT
6082 
`define MODULE mult
6083 18 unneback 
// unsigned multiplication
6084 40 unneback 
module `BASE`MODULE (a,b,p);
6085 
`undef MODULE
6086 18 unneback 
parameter operand_a_width = 18;
6087 
parameter operand_b_width = 18;
6088 
parameter result_hi = 35;
6089 
parameter result_lo = 0;
6090 
input [operand_a_width-1:0] a;
6091 
input [operand_b_width-1:0] b;
6092 
output [result_hi:result_hi] p;
6093 
 
6094 
wire [operand_a_width+operand_b_width-1:0] result;
6095 
 
6096 
    assign result = a * b;
6097 
    assign p = result[result_hi:result_lo];
6098 
 
6099 
endmodule
6100 40 unneback 
`endif
6101 18 unneback 
 
6102 40 unneback 
`ifdef SHIFT_UNIT_32
6103 
`define MODULE shift_unit_32
6104 18 unneback 
// shift unit
6105 
// supporting the following shift functions
6106 
//   SLL
6107 
//   SRL
6108 
//   SRA
6109 
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
6110 40 unneback 
module `BASE`MODULE( din, s, dout, opcode);
6111 
`undef MODULE
6112 18 unneback 
input [31:0] din; // data in operand
6113 
input [4:0] s; // shift operand
6114 
input [1:0] opcode;
6115 
output [31:0] dout;
6116 
 
6117 
parameter opcode_sll = 2'b00;
6118 
//parameter opcode_srl = 2'b01;
6119 
parameter opcode_sra = 2'b10;
6120 
//parameter opcode_ror = 2'b11;
6121 
 
6122 
wire sll, sra;
6123 
assign sll = opcode == opcode_sll;
6124 
assign sra = opcode == opcode_sra;
6125 
 
6126 
wire [15:1] s1;
6127 
wire [3:0] sign;
6128 
wire [7:0] tmp [0:3];
6129 
 
6130 
// first stage is multiplier based
6131 
// shift operand as fractional 8.7
6132 
assign s1[15] = sll & s[2:0]==3'd7;
6133 
assign s1[14] = sll & s[2:0]==3'd6;
6134 
assign s1[13] = sll & s[2:0]==3'd5;
6135 
assign s1[12] = sll & s[2:0]==3'd4;
6136 
assign s1[11] = sll & s[2:0]==3'd3;
6137 
assign s1[10] = sll & s[2:0]==3'd2;
6138 
assign s1[ 9] = sll & s[2:0]==3'd1;
6139 
assign s1[ 8] = s[2:0]==3'd0;
6140 
assign s1[ 7] = !sll & s[2:0]==3'd1;
6141 
assign s1[ 6] = !sll & s[2:0]==3'd2;
6142 
assign s1[ 5] = !sll & s[2:0]==3'd3;
6143 
assign s1[ 4] = !sll & s[2:0]==3'd4;
6144 
assign s1[ 3] = !sll & s[2:0]==3'd5;
6145 
assign s1[ 2] = !sll & s[2:0]==3'd6;
6146 
assign s1[ 1] = !sll & s[2:0]==3'd7;
6147 
 
6148 
assign sign[3] = din[31] & sra;
6149 
assign sign[2] = sign[3] & (&din[31:24]);
6150 
assign sign[1] = sign[2] & (&din[23:16]);
6151 
assign sign[0] = sign[1] & (&din[15:8]);
6152 40 unneback 
`define MODULE mults
6153 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
6154 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
6155 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
6156 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
6157 
`undef MODULE
6158 18 unneback 
// second stage is multiplexer based
6159 
// shift on byte level
6160 
 
6161 
// mux byte 3
6162 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
6163 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
6164 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
6165 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
6166 
                     {8{sign[3]}};
6167 
 
6168 
// mux byte 2
6169 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
6170 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
6171 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
6172 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
6173 
                     (s[4:3]==2'b01) ? tmp[3] :
6174 
                     {8{sign[3]}};
6175 
 
6176 
// mux byte 1
6177 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
6178 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
6179 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
6180 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
6181 
                     (s[4:3]==2'b01) ? tmp[2] :
6182 
                     (s[4:3]==2'b10) ? tmp[3] :
6183 
                     {8{sign[3]}};
6184 
 
6185 
// mux byte 0
6186 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
6187 
                     (sll) ?  {8{1'b0}}:
6188 
                     (s[4:3]==2'b01) ? tmp[1] :
6189 
                     (s[4:3]==2'b10) ? tmp[2] :
6190 
                     tmp[3];
6191 
 
6192 
endmodule
6193 40 unneback 
`endif
6194 18 unneback 
 
6195 40 unneback 
`ifdef LOGIC_UNIT
6196 18 unneback 
// logic unit
6197 
// supporting the following logic functions
6198 
//    a and b
6199 
//    a or  b
6200 
//    a xor b
6201 
//    not b
6202 40 unneback 
`define MODULE logic_unit
6203 
module `BASE`MODULE( a, b, result, opcode);
6204 
`undef MODULE
6205 18 unneback 
parameter width = 32;
6206 
parameter opcode_and = 2'b00;
6207 
parameter opcode_or  = 2'b01;
6208 
parameter opcode_xor = 2'b10;
6209 
input [width-1:0] a,b;
6210 
output [width-1:0] result;
6211 
input [1:0] opcode;
6212 
 
6213 
assign result = (opcode==opcode_and) ? a & b :
6214 
                (opcode==opcode_or)  ? a | b :
6215 
                (opcode==opcode_xor) ? a ^ b :
6216 
                b;
6217 
 
6218 
endmodule
6219 48 unneback 
`endif
6220 18 unneback 
 
6221 48 unneback 
`ifdef ARITH_UNIT
6222 
`define MODULE arith_unit
6223 
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
6224 
`undef MODULE
6225 18 unneback 
parameter width = 32;
6226 
parameter opcode_add = 1'b0;
6227 
parameter opcode_sub = 1'b1;
6228 
input [width-1:0] a,b;
6229 
input c_in, add_sub, sign;
6230 
output [width-1:0] result;
6231 
output c_out, z, ovfl;
6232 
 
6233 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
6234 
assign z = (result=={width{1'b0}});
6235 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
6236 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
6237 
endmodule
6238 40 unneback 
`endif
6239 48 unneback 
 
6240 
`ifdef COUNT_UNIT
6241 
`define MODULE count_unit
6242 
module `BASE`MODULE (din, dout, opcode);
6243 
`undef MODULE
6244 
parameter width = 32;
6245 
input [width-1:0] din;
6246 
output [width-1:0] dout;
6247 
input opcode;
6248 
 
6249 
integer i;
6250 58 unneback 
wire [width/32+4:0] ff1, fl1;
6251 48 unneback 
 
6252 57 unneback 
/*
6253 48 unneback 
always @(din) begin
6254 
    ff1 = 0; i = 0;
6255 
    while (din[i] == 0 && i < width) begin // complex condition
6256 
        ff1 = ff1 + 1;
6257 
        i = i + 1;
6258 
    end
6259 
end
6260 
 
6261 
always @(din) begin
6262 
    fl1 = width; i = width-1;
6263 
    while (din[i] == 0 && i >= width) begin // complex condition
6264 
        fl1 = fl1 - 1;
6265 
        i = i - 1;
6266 
    end
6267 
end
6268 57 unneback 
*/
6269 48 unneback 
 
6270 
generate
6271 
if (width==32) begin
6272 57 unneback 
 
6273 
    assign ff1 = din[0] ? 6'd1 :
6274 
                 din[1] ? 6'd2 :
6275 
                 din[2] ? 6'd3 :
6276 
                 din[3] ? 6'd4 :
6277 
                 din[4] ? 6'd5 :
6278 
                 din[5] ? 6'd6 :
6279 
                 din[6] ? 6'd7 :
6280 
                 din[7] ? 6'd8 :
6281 
                 din[8] ? 6'd9 :
6282 
                 din[9] ? 6'd10 :
6283 
                 din[10] ? 6'd11 :
6284 
                 din[11] ? 6'd12 :
6285 
                 din[12] ? 6'd13 :
6286 
                 din[13] ? 6'd14 :
6287 
                 din[14] ? 6'd15 :
6288 
                 din[15] ? 6'd16 :
6289 
                 din[16] ? 6'd17 :
6290 
                 din[17] ? 6'd18 :
6291 
                 din[18] ? 6'd19 :
6292 
                 din[19] ? 6'd20 :
6293 
                 din[20] ? 6'd21 :
6294 
                 din[21] ? 6'd22 :
6295 
                 din[22] ? 6'd23 :
6296 
                 din[23] ? 6'd24 :
6297 
                 din[24] ? 6'd25 :
6298 
                 din[25] ? 6'd26 :
6299 
                 din[26] ? 6'd27 :
6300 
                 din[27] ? 6'd28 :
6301 
                 din[28] ? 6'd29 :
6302 
                 din[29] ? 6'd30 :
6303 
                 din[30] ? 6'd31 :
6304 
                 din[31] ? 6'd32 :
6305 
                 6'd0;
6306 
 
6307 
    assign fl1 = din[31] ? 6'd32 :
6308 
                 din[30] ? 6'd31 :
6309 
                 din[29] ? 6'd30 :
6310 
                 din[28] ? 6'd29 :
6311 
                 din[27] ? 6'd28 :
6312 
                 din[26] ? 6'd27 :
6313 
                 din[25] ? 6'd26 :
6314 
                 din[24] ? 6'd25 :
6315 
                 din[23] ? 6'd24 :
6316 
                 din[22] ? 6'd23 :
6317 
                 din[21] ? 6'd22 :
6318 
                 din[20] ? 6'd21 :
6319 
                 din[19] ? 6'd20 :
6320 
                 din[18] ? 6'd19 :
6321 
                 din[17] ? 6'd18 :
6322 
                 din[16] ? 6'd17 :
6323 
                 din[15] ? 6'd16 :
6324 
                 din[14] ? 6'd15 :
6325 
                 din[13] ? 6'd14 :
6326 
                 din[12] ? 6'd13 :
6327 
                 din[11] ? 6'd12 :
6328 
                 din[10] ? 6'd11 :
6329 
                 din[9] ? 6'd10 :
6330 
                 din[8] ? 6'd9 :
6331 
                 din[7] ? 6'd8 :
6332 
                 din[6] ? 6'd7 :
6333 
                 din[5] ? 6'd6 :
6334 
                 din[4] ? 6'd5 :
6335 
                 din[3] ? 6'd4 :
6336 
                 din[2] ? 6'd3 :
6337 
                 din[1] ? 6'd2 :
6338 
                 din[0] ? 6'd1 :
6339 
                 6'd0;
6340 
 
6341 
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
6342 48 unneback 
end
6343 
endgenerate
6344 57 unneback 
 
6345 48 unneback 
generate
6346 
if (width==64) begin
6347 57 unneback 
    assign ff1 = 7'd0;
6348 
    assign fl1 = 7'd0;
6349 
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
6350 48 unneback 
end
6351 
endgenerate
6352 
 
6353 
endmodule
6354 
`endif
6355 
 
6356 
`ifdef EXT_UNIT
6357 
`define MODULE ext_unit
6358 
module `BASE`MODULE ( a, b, F, result, opcode);
6359 
`undef MODULE
6360 
parameter width = 32;
6361 
input [width-1:0] a, b;
6362 
input F;
6363 
output reg [width-1:0] result;
6364 
input [2:0] opcode;
6365 
 
6366 
generate
6367 
if (width==32) begin
6368 
always @ (a or b or F or opcode)
6369 
begin
6370 
    case (opcode)
6371 
    3'b000: result = {{24{1'b0}},a[7:0]};
6372 
    3'b001: result = {{24{a[7]}},a[7:0]};
6373 
    3'b010: result = {{16{1'b0}},a[7:0]};
6374 
    3'b011: result = {{16{a[15]}},a[15:0]};
6375 
    3'b110: result = (F) ? a : b;
6376 
    default: result = {b[15:0],16'h0000};
6377 
    endcase
6378 
end
6379 
end
6380 
endgenerate
6381 
 
6382 
generate
6383 
if (width==64) begin
6384 
always @ (a or b or F or opcode)
6385 
begin
6386 
    case (opcode)
6387 
    3'b000: result = {{56{1'b0}},a[7:0]};
6388 
    3'b001: result = {{56{a[7]}},a[7:0]};
6389 
    3'b010: result = {{48{1'b0}},a[7:0]};
6390 
    3'b011: result = {{48{a[15]}},a[15:0]};
6391 57 unneback 
    3'b110: result = (F) ? a : b;
6392 48 unneback 
    default: result = {32'h00000000,b[15:0],16'h0000};
6393 
    endcase
6394 
end
6395 
end
6396 
endgenerate
6397 
endmodule
6398 
`endif

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