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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 98

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 98 unneback 
`ifdef ACTEL
14 
    // ACTEL FPGA should not use logic to handle rw collision
15 
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16 
`else
17 
    `define SYN_NO_RW_CHECK
18 
`endif
19 
 
20 40 unneback 
`ifdef ALL
21 
 
22 
`define GBUF
23 
`define SYNC_RST
24 
`define PLL
25 
 
26 
`define MULTS
27 
`define MULTS18X18
28 
`define MULT
29 
`define SHIFT_UNIT_32
30 
`define LOGIC_UNIT
31 
 
32 
`define CNT_SHREG_WRAP
33 
`define CNT_SHREG_CE_WRAP
34 
`define CNT_SHREG_CE_CLEAR
35 
`define CNT_SHREG_CE_CLEAR_WRAP
36 
 
37 
`define MUX_ANDOR
38 
`define MUX2_ANDOR
39 
`define MUX3_ANDOR
40 
`define MUX4_ANDOR
41 
`define MUX5_ANDOR
42 
`define MUX6_ANDOR
43 43 unneback 
`define PARITY
44 40 unneback 
 
45 
`define ROM_INIT
46 
`define RAM
47 
`define RAM_BE
48 
`define DPRAM_1R1W
49 
`define DPRAM_2R1W
50 
`define DPRAM_2R2W
51 75 unneback 
`define DPRAM_BE_2R2W
52 40 unneback 
`define FIFO_1R1W_FILL_LEVEL_SYNC
53 
`define FIFO_2R2W_SYNC_SIMPLEX
54 
`define FIFO_CMP_ASYNC
55 
`define FIFO_1R1W_ASYNC
56 
`define FIFO_2R2W_ASYNC
57 
`define FIFO_2R2W_ASYNC_SIMPLEX
58 48 unneback 
`define REG_FILE
59 40 unneback 
 
60 
`define DFF
61 
`define DFF_ARRAY
62 
`define DFF_CE
63 
`define DFF_CE_CLEAR
64 
`define DF_CE_SET
65 
`define SPR
66 
`define SRP
67 
`define DFF_SR
68 
`define LATCH
69 
`define SHREG
70 
`define SHREG_CE
71 
`define DELAY
72 
`define DELAY_EMPTYFLAG
73 94 unneback 
`define PULSE2TOGGLE
74 
`define TOGGLE2PULSE
75 
`define SYNCHRONIZER
76 
`define CDC
77 40 unneback 
 
78 75 unneback 
`define WB3AVALON_BRIDGE
79 40 unneback 
`define WB3WB3_BRIDGE
80 
`define WB3_ARBITER_TYPE1
81 83 unneback 
`define WB_ADR_INC
82 59 unneback 
`define WB_B3_RAM_BE
83 49 unneback 
`define WB_B4_RAM_BE
84 48 unneback 
`define WB_B4_ROM
85 40 unneback 
`define WB_BOOT_ROM
86 
`define WB_DPRAM
87 97 unneback 
`define WBB3_WBB4_CACHE
88 40 unneback 
 
89 44 unneback 
`define IO_DFF_OE
90 
`define O_DFF
91 
 
92 40 unneback 
`endif
93 
 
94 
`ifdef PLL
95 
`ifndef SYNC_RST
96 
`define SYNC_RST
97 
`endif
98 
`endif
99 
 
100 
`ifdef SYNC_RST
101 
`ifndef GBUF
102 
`define GBUF
103 
`endif
104 
`endif
105 
 
106 92 unneback 
`ifdef WB_B3_DPRAM
107 
`ifndef WB_ADR_INC
108 
`define WB_ADR_INC
109 40 unneback 
`endif
110 92 unneback 
`ifndef DPRAM_BE_2R2W
111 
`define DPRAM_BE_2R2W
112 40 unneback 
`endif
113 
`endif
114 
 
115 62 unneback 
`ifdef WB_B3_RAM_BE
116 83 unneback 
`ifndef WB_ADR_INC
117 
`define WB_ADR_INC
118 62 unneback 
`endif
119 
`ifndef RAM_BE
120 
`define RAM_BE
121 
`endif
122 
`endif
123 
 
124 40 unneback 
`ifdef WB3_ARBITER_TYPE1
125 42 unneback 
`ifndef SPR
126 
`define SPR
127 
`endif
128 40 unneback 
`ifndef MUX_ANDOR
129 
`define MUX_ANDOR
130 
`endif
131 
`endif
132 
 
133 76 unneback 
`ifdef WB3AVALON_BRIDGE
134 
`ifndef WB3WB3_BRIDGE
135 
`define WB3WB3_BRIDGE
136 
`endif
137 
`endif
138 
 
139 40 unneback 
`ifdef WB3WB3_BRIDGE
140 
`ifndef CNT_SHREG_CE_CLEAR
141 
`define CNT_SHREG_CE_CLEAR
142 
`endif
143 
`ifndef DFF
144 
`define DFF
145 
`endif
146 
`ifndef DFF_CE
147 
`define DFF_CE
148 
`endif
149 
`ifndef CNT_SHREG_CE_CLEAR
150 
`define CNT_SHREG_CE_CLEAR
151 
`endif
152 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
153 
`define FIFO_2R2W_ASYNC_SIMPLEX
154 
`endif
155 
`endif
156 
 
157 97 unneback 
 `ifdef WBB3_WBB4_CACHE
158 
 `ifndef RAM
159 
 `define RAM
160 
 `endif
161 
 `ifndef WB_ADR_INC
162 
 `define WB_ADR_INC
163 
 `endif
164 
 `ifndef dpram_be_2r2w
165 
 `define DPRAM_BE_2R2W
166 
 `endif
167 98 unneback 
 `ifndef CDC
168 
 `define CDC
169 97 unneback 
 `endif
170 98 unneback 
 `endif
171 97 unneback 
 
172 40 unneback 
`ifdef MULTS18X18
173 
`ifndef MULTS
174 
`define MULTS
175 
`endif
176 
`endif
177 
 
178 
`ifdef SHIFT_UNIT_32
179 
`ifndef MULTS
180 
`define MULTS
181 
`endif
182 
`endif
183 
 
184 
`ifdef MUX2_ANDOR
185 
`ifndef MUX_ANDOR
186 
`define MUX_ANDOR
187 
`endif
188 
`endif
189 
 
190 
`ifdef MUX3_ANDOR
191 
`ifndef MUX_ANDOR
192 
`define MUX_ANDOR
193 
`endif
194 
`endif
195 
 
196 
`ifdef MUX4_ANDOR
197 
`ifndef MUX_ANDOR
198 
`define MUX_ANDOR
199 
`endif
200 
`endif
201 
 
202 
`ifdef MUX5_ANDOR
203 
`ifndef MUX_ANDOR
204 
`define MUX_ANDOR
205 
`endif
206 
`endif
207 
 
208 
`ifdef MUX6_ANDOR
209 
`ifndef MUX_ANDOR
210 
`define MUX_ANDOR
211 
`endif
212 
`endif
213 
 
214 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
215 
`ifndef CNT_BIN_CE
216 
`define CNT_BIN_CE
217 
`endif
218 
`ifndef DPRAM_1R1W
219 
`define DPRAM_1R1W
220 
`endif
221 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
222 
`define CNT_BIN_CE_REW_Q_ZQ_L1
223 
`endif
224 
`endif
225 
 
226 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
227 
`ifndef CNT_LFSR_CE
228 
`define CNT_LFSR_CE
229 
`endif
230 
`ifndef DPRAM_2R2W
231 
`define DPRAM_2R2W
232 
`endif
233 
`ifndef CNT_BIN_CE_REW_ZQ_L1
234 
`define CNT_BIN_CE_REW_ZQ_L1
235 
`endif
236 
`endif
237 
 
238 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
239 
`ifndef CNT_GRAY_CE_BIN
240 
`define CNT_GRAY_CE_BIN
241 
`endif
242 
`ifndef DPRAM_2R2W
243 
`define DPRAM_2R2W
244 
`endif
245 
`ifndef FIFO_CMP_ASYNC
246 
`define FIFO_CMP_ASYNC
247 
`endif
248 
`endif
249 
 
250 
`ifdef FIFO_2R2W_ASYNC
251 
`ifndef FIFO_1R1W_ASYNC
252 
`define FIFO_1R1W_ASYNC
253 
`endif
254 
`endif
255 
 
256 
`ifdef FIFO_1R1W_ASYNC
257 
`ifndef CNT_GRAY_CE_BIN
258 
`define CNT_GRAY_CE_BIN
259 
`endif
260 
`ifndef DPRAM_1R1W
261 
`define DPRAM_1R1W
262 
`endif
263 
`ifndef FIFO_CMP_ASYNC
264 
`define FIFO_CMP_ASYNC
265 
`endif
266 
`endif
267 
 
268 
`ifdef FIFO_CMP_ASYNC
269 
`ifndef DFF_SR
270 
`define DFF_SR
271 
`endif
272 
`ifndef DFF
273 
`define DFF
274 
`endif
275 
`endif
276 48 unneback 
 
277 
`ifdef REG_FILE
278 
`ifndef DPRAM_1R1W
279 
`define DPRAM_1R1W
280 
`endif
281 
`endif
282 97 unneback 
 
283 98 unneback 
`ifdef CDC
284 
`ifndef PULSE2TOGGLE
285 
`define PULSE2TOGGLE
286 
`endif
287 
`ifndef TOGGLE2PULSE
288 
`define TOGGLE2PULSE
289 
`endif
290 
`ifndef SYNCHRONIZER
291 
`define SYNCHRONIZER
292 
`endif
293 
`endif
294 
 
295 97 unneback 
// size to width
296 
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
297 62 unneback 
//////////////////////////////////////////////////////////////////////
298 6 unneback 
////                                                              ////
299 
////  Versatile library, clock and reset                          ////
300 
////                                                              ////
301 
////  Description                                                 ////
302 
////  Logic related to clock and reset                            ////
303 
////                                                              ////
304 
////                                                              ////
305 
////  To Do:                                                      ////
306 
////   - add more different registers                             ////
307 
////                                                              ////
308 
////  Author(s):                                                  ////
309 
////      - Michael Unneback, unneback@opencores.org              ////
310 
////        ORSoC AB                                              ////
311 
////                                                              ////
312 
//////////////////////////////////////////////////////////////////////
313 
////                                                              ////
314 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
315 
////                                                              ////
316 
//// This source file may be used and distributed without         ////
317 
//// restriction provided that this copyright statement is not    ////
318 
//// removed from the file and that any derivative work contains  ////
319 
//// the original copyright notice and the associated disclaimer. ////
320 
////                                                              ////
321 
//// This source file is free software; you can redistribute it   ////
322 
//// and/or modify it under the terms of the GNU Lesser General   ////
323 
//// Public License as published by the Free Software Foundation; ////
324 
//// either version 2.1 of the License, or (at your option) any   ////
325 
//// later version.                                               ////
326 
////                                                              ////
327 
//// This source is distributed in the hope that it will be       ////
328 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
329 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
330 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
331 
//// details.                                                     ////
332 
////                                                              ////
333 
//// You should have received a copy of the GNU Lesser General    ////
334 
//// Public License along with this source; if not, download it   ////
335 
//// from http://www.opencores.org/lgpl.shtml                     ////
336 
////                                                              ////
337 
//////////////////////////////////////////////////////////////////////
338 
 
339 48 unneback 
`ifdef ACTEL
340 
`ifdef GBUF
341 
`timescale 1 ns/100 ps
342 6 unneback 
// Global buffer
343 
// usage:
344 
// use to enable global buffers for high fan out signals such as clock and reset
345 
// Version: 8.4 8.4.0.33
346 
module gbuf(GL,CLK);
347 
output GL;
348 
input  CLK;
349 
 
350 
    wire GND;
351 
 
352 
    GND GND_1_net(.Y(GND));
353 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
354 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
355 
 
356 
endmodule
357 
`timescale 1 ns/1 ns
358 40 unneback 
`define MODULE gbuf
359 
module `BASE`MODULE ( i, o);
360 
`undef MODULE
361 6 unneback 
input i;
362 
output o;
363 
`ifdef SIM_GBUF
364 
assign o=i;
365 
`else
366 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
367 
`endif
368 
endmodule
369 40 unneback 
`endif
370 33 unneback 
 
371 6 unneback 
`else
372 33 unneback 
 
373 40 unneback 
`ifdef ALTERA
374 
`ifdef GBUF
375 21 unneback 
//altera
376 40 unneback 
`define MODULE gbuf
377 
module `BASE`MODULE ( i, o);
378 
`undef MODULE
379 33 unneback 
input i;
380 
output o;
381 
assign o = i;
382 
endmodule
383 40 unneback 
`endif
384 33 unneback 
 
385 6 unneback 
`else
386 
 
387 40 unneback 
`ifdef GBUF
388 6 unneback 
`timescale 1 ns/100 ps
389 40 unneback 
`define MODULE
390 
module `BASE`MODULE ( i, o);
391 
`undef MODULE
392 6 unneback 
input i;
393 
output o;
394 
assign o = i;
395 
endmodule
396 40 unneback 
`endif
397 6 unneback 
`endif // ALTERA
398 
`endif //ACTEL
399 
 
400 40 unneback 
`ifdef SYNC_RST
401 6 unneback 
// sync reset
402 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
403 6 unneback 
// output active high global reset sync with two DFFs
404 
`timescale 1 ns/100 ps
405 40 unneback 
`define MODULE sync_rst
406 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
407 
`undef MODULE
408 6 unneback 
input rst_n_i, clk;
409 
output rst_o;
410 18 unneback 
reg [1:0] tmp;
411 6 unneback 
always @ (posedge clk or negedge rst_n_i)
412 
if (!rst_n_i)
413 17 unneback 
        tmp <= 2'b11;
414 6 unneback 
else
415 33 unneback 
        tmp <= {1'b0,tmp[1]};
416 40 unneback 
`define MODULE gbuf
417 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
418 
`undef MODULE
419 6 unneback 
endmodule
420 40 unneback 
`endif
421 6 unneback 
 
422 40 unneback 
`ifdef PLL
423 6 unneback 
// vl_pll
424 
`ifdef ACTEL
425 32 unneback 
///////////////////////////////////////////////////////////////////////////////
426 17 unneback 
`timescale 1 ps/1 ps
427 40 unneback 
`define MODULE pll
428 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
429 
`undef MODULE
430 6 unneback 
parameter index = 0;
431 
parameter number_of_clk = 1;
432 17 unneback 
parameter period_time_0 = 20000;
433 
parameter period_time_1 = 20000;
434 
parameter period_time_2 = 20000;
435 
parameter lock_delay = 2000000;
436 6 unneback 
input clk_i, rst_n_i;
437 
output lock;
438 
output reg [0:number_of_clk-1] clk_o;
439 
output [0:number_of_clk-1] rst_o;
440 
 
441 
`ifdef SIM_PLL
442 
 
443 
always
444 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
445 
 
446 
generate if (number_of_clk > 1)
447 
always
448 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
449 
endgenerate
450 
 
451 
generate if (number_of_clk > 2)
452 
always
453 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
454 
endgenerate
455 
 
456 
genvar i;
457 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
458 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
459 
end
460 
endgenerate
461 
 
462 
assign #lock_delay lock = rst_n_i;
463 
 
464 
endmodule
465 
`else
466 
generate if (number_of_clk==1 & index==0) begin
467 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
468 
end
469 
endgenerate // index==0
470 
generate if (number_of_clk==1 & index==1) begin
471 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
472 
end
473 
endgenerate // index==1
474 
generate if (number_of_clk==1 & index==2) begin
475 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
476 
end
477 
endgenerate // index==2
478 
generate if (number_of_clk==1 & index==3) begin
479 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
480 
end
481 
endgenerate // index==0
482 
 
483 
generate if (number_of_clk==2 & index==0) begin
484 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
485 
end
486 
endgenerate // index==0
487 
generate if (number_of_clk==2 & index==1) begin
488 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
489 
end
490 
endgenerate // index==1
491 
generate if (number_of_clk==2 & index==2) begin
492 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
493 
end
494 
endgenerate // index==2
495 
generate if (number_of_clk==2 & index==3) begin
496 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
497 
end
498 
endgenerate // index==0
499 
 
500 
generate if (number_of_clk==3 & index==0) begin
501 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
502 
end
503 
endgenerate // index==0
504 
generate if (number_of_clk==3 & index==1) begin
505 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
506 
end
507 
endgenerate // index==1
508 
generate if (number_of_clk==3 & index==2) begin
509 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
510 
end
511 
endgenerate // index==2
512 
generate if (number_of_clk==3 & index==3) begin
513 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
514 
end
515 
endgenerate // index==0
516 
 
517 
genvar i;
518 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
519 40 unneback 
`define MODULE sync_rst
520 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
521 
`undef MODULE
522 6 unneback 
end
523 
endgenerate
524 
endmodule
525 
`endif
526 32 unneback 
///////////////////////////////////////////////////////////////////////////////
527 6 unneback 
 
528 
`else
529 
 
530 32 unneback 
///////////////////////////////////////////////////////////////////////////////
531 6 unneback 
`ifdef ALTERA
532 
 
533 32 unneback 
`timescale 1 ps/1 ps
534 40 unneback 
`define MODULE pll
535 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
536 
`undef MODULE
537 32 unneback 
parameter index = 0;
538 
parameter number_of_clk = 1;
539 
parameter period_time_0 = 20000;
540 
parameter period_time_1 = 20000;
541 
parameter period_time_2 = 20000;
542 
parameter period_time_3 = 20000;
543 
parameter period_time_4 = 20000;
544 
parameter lock_delay = 2000000;
545 
input clk_i, rst_n_i;
546 
output lock;
547 
output reg [0:number_of_clk-1] clk_o;
548 
output [0:number_of_clk-1] rst_o;
549 
 
550 
`ifdef SIM_PLL
551 
 
552 
always
553 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
554 
 
555 
generate if (number_of_clk > 1)
556 
always
557 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
558 
endgenerate
559 
 
560 
generate if (number_of_clk > 2)
561 
always
562 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
563 
endgenerate
564 
 
565 33 unneback 
generate if (number_of_clk > 3)
566 32 unneback 
always
567 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
568 
endgenerate
569 
 
570 33 unneback 
generate if (number_of_clk > 4)
571 32 unneback 
always
572 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
573 
endgenerate
574 
 
575 
genvar i;
576 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
577 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
578 
end
579 
endgenerate
580 
 
581 33 unneback 
//assign #lock_delay lock = rst_n_i;
582 
assign lock = rst_n_i;
583 32 unneback 
 
584 
endmodule
585 6 unneback 
`else
586 
 
587 33 unneback 
`ifdef VL_PLL0
588 
`ifdef VL_PLL0_CLK1
589 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
590 
`endif
591 
`ifdef VL_PLL0_CLK2
592 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
593 
`endif
594 
`ifdef VL_PLL0_CLK3
595 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
596 
`endif
597 
`ifdef VL_PLL0_CLK4
598 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
599 
`endif
600 
`ifdef VL_PLL0_CLK5
601 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
602 
`endif
603 
`endif
604 32 unneback 
 
605 33 unneback 
`ifdef VL_PLL1
606 
`ifdef VL_PLL1_CLK1
607 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
608 
`endif
609 
`ifdef VL_PLL1_CLK2
610 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
611 
`endif
612 
`ifdef VL_PLL1_CLK3
613 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
614 
`endif
615 
`ifdef VL_PLL1_CLK4
616 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
617 
`endif
618 
`ifdef VL_PLL1_CLK5
619 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
620 
`endif
621 
`endif
622 32 unneback 
 
623 33 unneback 
`ifdef VL_PLL2
624 
`ifdef VL_PLL2_CLK1
625 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
626 
`endif
627 
`ifdef VL_PLL2_CLK2
628 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
629 
`endif
630 
`ifdef VL_PLL2_CLK3
631 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
632 
`endif
633 
`ifdef VL_PLL2_CLK4
634 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
635 
`endif
636 
`ifdef VL_PLL2_CLK5
637 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
638 
`endif
639 
`endif
640 32 unneback 
 
641 33 unneback 
`ifdef VL_PLL3
642 
`ifdef VL_PLL3_CLK1
643 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
644 
`endif
645 
`ifdef VL_PLL3_CLK2
646 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
647 
`endif
648 
`ifdef VL_PLL3_CLK3
649 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
650 
`endif
651 
`ifdef VL_PLL3_CLK4
652 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
653 
`endif
654 
`ifdef VL_PLL3_CLK5
655 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
656 
`endif
657 
`endif
658 32 unneback 
 
659 
genvar i;
660 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
661 40 unneback 
`define MODULE sync_rst
662 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
663 
`undef MODULE
664 32 unneback 
end
665 
endgenerate
666 
endmodule
667 
`endif
668 
///////////////////////////////////////////////////////////////////////////////
669 
 
670 
`else
671 
 
672 6 unneback 
// generic PLL
673 17 unneback 
`timescale 1 ps/1 ps
674 40 unneback 
`define MODULE pll
675 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
676 
`undef MODULE
677 6 unneback 
parameter index = 0;
678 
parameter number_of_clk = 1;
679 17 unneback 
parameter period_time_0 = 20000;
680 
parameter period_time_1 = 20000;
681 
parameter period_time_2 = 20000;
682 6 unneback 
parameter lock_delay = 2000;
683 
input clk_i, rst_n_i;
684 
output lock;
685 
output reg [0:number_of_clk-1] clk_o;
686 
output [0:number_of_clk-1] rst_o;
687 
 
688 
always
689 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
690 
 
691 
generate if (number_of_clk > 1)
692 
always
693 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
694 
endgenerate
695 
 
696 
generate if (number_of_clk > 2)
697 
always
698 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
699 
endgenerate
700 
 
701 
genvar i;
702 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
703 40 unneback 
`define MODULE sync_rst
704 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
705 
`undef MODULE
706 6 unneback 
end
707 
endgenerate
708 
 
709 
assign #lock_delay lock = rst_n_i;
710 
 
711 
endmodule
712 
 
713 
`endif //altera
714 17 unneback 
`endif //actel
715 40 unneback 
`undef MODULE
716 
`endif//////////////////////////////////////////////////////////////////////
717 6 unneback 
////                                                              ////
718 
////  Versatile library, registers                                ////
719 
////                                                              ////
720 
////  Description                                                 ////
721 
////  Different type of registers                                 ////
722 
////                                                              ////
723 
////                                                              ////
724 
////  To Do:                                                      ////
725 
////   - add more different registers                             ////
726 
////                                                              ////
727 
////  Author(s):                                                  ////
728 
////      - Michael Unneback, unneback@opencores.org              ////
729 
////        ORSoC AB                                              ////
730 
////                                                              ////
731 
//////////////////////////////////////////////////////////////////////
732 
////                                                              ////
733 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
734 
////                                                              ////
735 
//// This source file may be used and distributed without         ////
736 
//// restriction provided that this copyright statement is not    ////
737 
//// removed from the file and that any derivative work contains  ////
738 
//// the original copyright notice and the associated disclaimer. ////
739 
////                                                              ////
740 
//// This source file is free software; you can redistribute it   ////
741 
//// and/or modify it under the terms of the GNU Lesser General   ////
742 
//// Public License as published by the Free Software Foundation; ////
743 
//// either version 2.1 of the License, or (at your option) any   ////
744 
//// later version.                                               ////
745 
////                                                              ////
746 
//// This source is distributed in the hope that it will be       ////
747 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
748 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
749 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
750 
//// details.                                                     ////
751 
////                                                              ////
752 
//// You should have received a copy of the GNU Lesser General    ////
753 
//// Public License along with this source; if not, download it   ////
754 
//// from http://www.opencores.org/lgpl.shtml                     ////
755 
////                                                              ////
756 
//////////////////////////////////////////////////////////////////////
757 
 
758 40 unneback 
`ifdef DFF
759 
`define MODULE dff
760 
module `BASE`MODULE ( d, q, clk, rst);
761 
`undef MODULE
762 6 unneback 
        parameter width = 1;
763 
        parameter reset_value = 0;
764 
 
765 
        input [width-1:0] d;
766 
        input clk, rst;
767 
        output reg [width-1:0] q;
768 
 
769 
        always @ (posedge clk or posedge rst)
770 
        if (rst)
771 
                q <= reset_value;
772 
        else
773 
                q <= d;
774 
 
775 
endmodule
776 40 unneback 
`endif
777 6 unneback 
 
778 40 unneback 
`ifdef DFF_ARRAY
779 
`define MODULE dff_array
780 
module `BASE`MODULE ( d, q, clk, rst);
781 
`undef MODULE
782 6 unneback 
 
783 
        parameter width = 1;
784 
        parameter depth = 2;
785 
        parameter reset_value = 1'b0;
786 
 
787 
        input [width-1:0] d;
788 
        input clk, rst;
789 
        output [width-1:0] q;
790 
        reg  [0:depth-1] q_tmp [width-1:0];
791 
        integer i;
792 
        always @ (posedge clk or posedge rst)
793 
        if (rst) begin
794 
            for (i=0;i<depth;i=i+1)
795 
                q_tmp[i] <= {width{reset_value}};
796 
        end else begin
797 
            q_tmp[0] <= d;
798 
            for (i=1;i<depth;i=i+1)
799 
                q_tmp[i] <= q_tmp[i-1];
800 
        end
801 
 
802 
    assign q = q_tmp[depth-1];
803 
 
804 
endmodule
805 40 unneback 
`endif
806 6 unneback 
 
807 40 unneback 
`ifdef DFF_CE
808 
`define MODULE dff_ce
809 
module `BASE`MODULE ( d, ce, q, clk, rst);
810 
`undef MODULE
811 6 unneback 
 
812 
        parameter width = 1;
813 
        parameter reset_value = 0;
814 
 
815 
        input [width-1:0] d;
816 
        input ce, clk, rst;
817 
        output reg [width-1:0] q;
818 
 
819 
        always @ (posedge clk or posedge rst)
820 
        if (rst)
821 
                q <= reset_value;
822 
        else
823 
                if (ce)
824 
                        q <= d;
825 
 
826 
endmodule
827 40 unneback 
`endif
828 6 unneback 
 
829 40 unneback 
`ifdef DFF_CE_CLEAR
830 
`define MODULE dff_ce_clear
831 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
832 
`undef MODULE
833 8 unneback 
 
834 
        parameter width = 1;
835 
        parameter reset_value = 0;
836 
 
837 
        input [width-1:0] d;
838 10 unneback 
        input ce, clear, clk, rst;
839 8 unneback 
        output reg [width-1:0] q;
840 
 
841 
        always @ (posedge clk or posedge rst)
842 
        if (rst)
843 
            q <= reset_value;
844 
        else
845 
            if (ce)
846 
                if (clear)
847 
                    q <= {width{1'b0}};
848 
                else
849 
                    q <= d;
850 
 
851 
endmodule
852 40 unneback 
`endif
853 8 unneback 
 
854 40 unneback 
`ifdef DF_CE_SET
855 
`define MODULE dff_ce_set
856 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
857 
`undef MODULE
858 24 unneback 
 
859 
        parameter width = 1;
860 
        parameter reset_value = 0;
861 
 
862 
        input [width-1:0] d;
863 
        input ce, set, clk, rst;
864 
        output reg [width-1:0] q;
865 
 
866 
        always @ (posedge clk or posedge rst)
867 
        if (rst)
868 
            q <= reset_value;
869 
        else
870 
            if (ce)
871 
                if (set)
872 
                    q <= {width{1'b1}};
873 
                else
874 
                    q <= d;
875 
 
876 
endmodule
877 40 unneback 
`endif
878 24 unneback 
 
879 40 unneback 
`ifdef SPR
880 
`define MODULE spr
881 
module `BASE`MODULE ( sp, r, q, clk, rst);
882 
`undef MODULE
883 
 
884 64 unneback 
        //parameter width = 1;
885 
        parameter reset_value = 1'b0;
886 29 unneback 
 
887 
        input sp, r;
888 
        output reg q;
889 
        input clk, rst;
890 
 
891 
        always @ (posedge clk or posedge rst)
892 
        if (rst)
893 
            q <= reset_value;
894 
        else
895 
            if (sp)
896 
                q <= 1'b1;
897 
            else if (r)
898 
                q <= 1'b0;
899 
 
900 
endmodule
901 40 unneback 
`endif
902 29 unneback 
 
903 40 unneback 
`ifdef SRP
904 
`define MODULE srp
905 
module `BASE`MODULE ( s, rp, q, clk, rst);
906 
`undef MODULE
907 
 
908 29 unneback 
        parameter width = 1;
909 
        parameter reset_value = 0;
910 
 
911 
        input s, rp;
912 
        output reg q;
913 
        input clk, rst;
914 
 
915 
        always @ (posedge clk or posedge rst)
916 
        if (rst)
917 
            q <= reset_value;
918 
        else
919 
            if (rp)
920 
                q <= 1'b0;
921 
            else if (s)
922 
                q <= 1'b1;
923 
 
924 
endmodule
925 40 unneback 
`endif
926 29 unneback 
 
927 40 unneback 
`ifdef ALTERA
928 29 unneback 
 
929 40 unneback 
`ifdef DFF_SR
930 6 unneback 
// megafunction wizard: %LPM_FF%
931 
// GENERATION: STANDARD
932 
// VERSION: WM1.0
933 
// MODULE: lpm_ff
934 
 
935 
// ============================================================
936 
// File Name: dff_sr.v
937 
// Megafunction Name(s):
938 
//                      lpm_ff
939 
//
940 
// Simulation Library Files(s):
941 
//                      lpm
942 
// ============================================================
943 
// ************************************************************
944 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
945 
//
946 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
947 
// ************************************************************
948 
 
949 
 
950 
//Copyright (C) 1991-2010 Altera Corporation
951 
//Your use of Altera Corporation's design tools, logic functions
952 
//and other software and tools, and its AMPP partner logic
953 
//functions, and any output files from any of the foregoing
954 
//(including device programming or simulation files), and any
955 
//associated documentation or information are expressly subject
956 
//to the terms and conditions of the Altera Program License
957 
//Subscription Agreement, Altera MegaCore Function License
958 
//Agreement, or other applicable license agreement, including,
959 
//without limitation, that your use is for the sole purpose of
960 
//programming logic devices manufactured by Altera and sold by
961 
//Altera or its authorized distributors.  Please refer to the
962 
//applicable agreement for further details.
963 
 
964 
 
965 
// synopsys translate_off
966 
`timescale 1 ps / 1 ps
967 
// synopsys translate_on
968 40 unneback 
`define MODULE dff_sr
969 
module `BASE`MODULE (
970 
`undef MODULE
971 
 
972 6 unneback 
        aclr,
973 
        aset,
974 
        clock,
975 
        data,
976 
        q);
977 
 
978 
        input     aclr;
979 
        input     aset;
980 
        input     clock;
981 
        input     data;
982 
        output    q;
983 
 
984 
        wire [0:0] sub_wire0;
985 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
986 
        wire  q = sub_wire1;
987 
        wire  sub_wire2 = data;
988 
        wire  sub_wire3 = sub_wire2;
989 
 
990 
        lpm_ff  lpm_ff_component (
991 
                                .aclr (aclr),
992 
                                .clock (clock),
993 
                                .data (sub_wire3),
994 
                                .aset (aset),
995 
                                .q (sub_wire0)
996 
                                // synopsys translate_off
997 
                                ,
998 
                                .aload (),
999 
                                .enable (),
1000 
                                .sclr (),
1001 
                                .sload (),
1002 
                                .sset ()
1003 
                                // synopsys translate_on
1004 
                                );
1005 
        defparam
1006 
                lpm_ff_component.lpm_fftype = "DFF",
1007 
                lpm_ff_component.lpm_type = "LPM_FF",
1008 
                lpm_ff_component.lpm_width = 1;
1009 
 
1010 
 
1011 
endmodule
1012 
 
1013 
// ============================================================
1014 
// CNX file retrieval info
1015 
// ============================================================
1016 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1017 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1018 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1019 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1020 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1021 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1022 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1023 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1024 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1025 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1026 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1027 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1028 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1029 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1030 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1031 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1032 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1033 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1034 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1035 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1036 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1037 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1038 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1039 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1040 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1041 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1042 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1043 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1044 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1045 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1046 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1047 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1048 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1049 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1050 
// Retrieval info: LIB_FILE: lpm
1051 40 unneback 
`endif
1052 6 unneback 
 
1053 
`else
1054 
 
1055 40 unneback 
`ifdef DFF_SR
1056 
`define MODULE dff_sr
1057 
module `BASE`MODULE ( aclr, aset, clock, data, q);
1058 
`undef MODULE
1059 6 unneback 
 
1060 
    input         aclr;
1061 
    input         aset;
1062 
    input         clock;
1063 
    input         data;
1064 
    output reg    q;
1065 
 
1066 
   always @ (posedge clock or posedge aclr or posedge aset)
1067 
     if (aclr)
1068 
       q <= 1'b0;
1069 
     else if (aset)
1070 
       q <= 1'b1;
1071 
     else
1072 
       q <= data;
1073 
 
1074 
endmodule
1075 40 unneback 
`endif
1076 6 unneback 
 
1077 
`endif
1078 
 
1079 
// LATCH
1080 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1081 
`ifdef ALTERA
1082 40 unneback 
 
1083 
`ifdef LATCH
1084 
`define MODULE latch
1085 
module `BASE`MODULE ( d, le, q, clk);
1086 
`undef MODULE
1087 6 unneback 
input d, le;
1088 
output q;
1089 
input clk;
1090 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1091 
endmodule
1092 40 unneback 
`endif
1093 
 
1094 6 unneback 
`else
1095 40 unneback 
 
1096 
`ifdef LATCH
1097 
`define MODULE latch
1098 
module `BASE`MODULE ( d, le, q, clk);
1099 
`undef MODULE
1100 6 unneback 
input d, le;
1101 48 unneback 
input clk;
1102 
always @ (le or d)
1103 60 unneback 
if (le)
1104 48 unneback 
    d <= q;
1105 6 unneback 
endmodule
1106 15 unneback 
`endif
1107 
 
1108 40 unneback 
`endif
1109 
 
1110 
`ifdef SHREG
1111 
`define MODULE shreg
1112 
module `BASE`MODULE ( d, q, clk, rst);
1113 
`undef MODULE
1114 
 
1115 17 unneback 
parameter depth = 10;
1116 
input d;
1117 
output q;
1118 
input clk, rst;
1119 
 
1120 
reg [1:depth] dffs;
1121 
 
1122 
always @ (posedge clk or posedge rst)
1123 
if (rst)
1124 
    dffs <= {depth{1'b0}};
1125 
else
1126 
    dffs <= {d,dffs[1:depth-1]};
1127 
assign q = dffs[depth];
1128 
endmodule
1129 40 unneback 
`endif
1130 17 unneback 
 
1131 40 unneback 
`ifdef SHREG_CE
1132 
`define MODULE shreg_ce
1133 
module `BASE`MODULE ( d, ce, q, clk, rst);
1134 
`undef MODULE
1135 17 unneback 
parameter depth = 10;
1136 
input d, ce;
1137 
output q;
1138 
input clk, rst;
1139 
 
1140 
reg [1:depth] dffs;
1141 
 
1142 
always @ (posedge clk or posedge rst)
1143 
if (rst)
1144 
    dffs <= {depth{1'b0}};
1145 
else
1146 
    if (ce)
1147 
        dffs <= {d,dffs[1:depth-1]};
1148 
assign q = dffs[depth];
1149 
endmodule
1150 40 unneback 
`endif
1151 17 unneback 
 
1152 40 unneback 
`ifdef DELAY
1153 
`define MODULE delay
1154 
module `BASE`MODULE ( d, q, clk, rst);
1155 
`undef MODULE
1156 15 unneback 
parameter depth = 10;
1157 
input d;
1158 
output q;
1159 
input clk, rst;
1160 
 
1161 
reg [1:depth] dffs;
1162 
 
1163 
always @ (posedge clk or posedge rst)
1164 
if (rst)
1165 
    dffs <= {depth{1'b0}};
1166 
else
1167 
    dffs <= {d,dffs[1:depth-1]};
1168 
assign q = dffs[depth];
1169 17 unneback 
endmodule
1170 40 unneback 
`endif
1171 17 unneback 
 
1172 40 unneback 
`ifdef DELAY_EMPTYFLAG
1173 
`define MODULE delay_emptyflag
1174 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1175 40 unneback 
`undef MODULE
1176 17 unneback 
parameter depth = 10;
1177 
input d;
1178 
output q, emptyflag;
1179 
input clk, rst;
1180 
 
1181 
reg [1:depth] dffs;
1182 
 
1183 
always @ (posedge clk or posedge rst)
1184 
if (rst)
1185 
    dffs <= {depth{1'b0}};
1186 
else
1187 
    dffs <= {d,dffs[1:depth-1]};
1188 
assign q = dffs[depth];
1189 
assign emptyflag = !(|dffs);
1190 
endmodule
1191 40 unneback 
`endif
1192 75 unneback 
 
1193 94 unneback 
`ifdef PULSE2TOGGLE
1194 98 unneback 
`define MODULE pulse2toggle
1195 
module `BASE`MODULE ( pl, q, clk, rst);
1196 75 unneback 
`undef MODULE
1197 94 unneback 
input pl;
1198 98 unneback 
output reg q;
1199 94 unneback 
input clk, rst;
1200 
always @ (posedge clk or posedge rst)
1201 75 unneback 
if (rst)
1202 94 unneback 
    q <= 1'b0;
1203 75 unneback 
else
1204 94 unneback 
    q <= pl ^ q;
1205 
endmodule
1206 
`endif
1207 75 unneback 
 
1208 94 unneback 
`ifdef TOGGLE2PULSE
1209 98 unneback 
`define MODULE toggle2pulse
1210 94 unneback 
module `BASE`MODULE (d, pl, clk, rst);
1211 97 unneback 
`undef MODULE
1212 94 unneback 
input d;
1213 
output pl;
1214 
input clk, rst;
1215 
reg dff;
1216 
always @ (posedge clk or posedge rst)
1217 
if (rst)
1218 
    dff <= 1'b0;
1219 75 unneback 
else
1220 94 unneback 
    dff <= d;
1221 98 unneback 
assign pl = d ^ dff;
1222 94 unneback 
endmodule
1223 
`endif
1224 75 unneback 
 
1225 94 unneback 
`ifdef SYNCHRONIZER
1226 
`define MODULE synchronizer
1227 
module `BASE`MODULE (d, q, clk, rst);
1228 
`undef MODULE
1229 
input d;
1230 
output reg q;
1231 
output clk, rst;
1232 
reg dff;
1233 
always @ (posedge clk or posedge rst)
1234 
if (rst)
1235 
    {dff,q} <= 2'b00;
1236 75 unneback 
else
1237 94 unneback 
    {dff,q} <= {d,dff};
1238 
endmodule
1239 
`endif
1240 75 unneback 
 
1241 94 unneback 
`ifdef CDC
1242 
`define MODULE cdc
1243 97 unneback 
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1244 94 unneback 
`undef MODULE
1245 
input start_pl;
1246 
output take_it_pl;
1247 
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1248 
output got_it_pl;
1249 
input clk_src, rst_src;
1250 
input clk_dst, rst_dst;
1251 
wire take_it_tg, take_it_tg_sync;
1252 
wire got_it_tg, got_it_tg_sync;
1253 
// src -> dst
1254 
`define MODULE pulse2toggle
1255 
`BASE`MODULE p2t0 (
1256 
`undef MODULE
1257 
    .pl(start_pl),
1258 
    .q(take_it_tg),
1259 
    .clk(clk_src),
1260 
    .rst(rst_src));
1261 75 unneback 
 
1262 94 unneback 
`define MODULE synchronizer
1263 
`BASE`MODULE sync0 (
1264 
`undef MODULE
1265 
    .d(take_it_tg),
1266 
    .q(take_it_tg_sync),
1267 
    .clk(clk_dst),
1268 
    .rst(rst_dst));
1269 
 
1270 
`define MODULE toggle2pulse
1271 
`BASE`MODULE t2p0 (
1272 
`undef MODULE
1273 
    .d(take_it_sync),
1274 
    .pl(take_it_pl),
1275 
    .clk(clk_dst),
1276 
    .rst(rst_dst));
1277 
 
1278 
// dst -> src
1279 
`define MODULE pulse2toggle
1280 98 unneback 
`BASE`MODULE p2t1 (
1281 94 unneback 
`undef MODULE
1282 
    .pl(take_it_grant_pl),
1283 
    .q(got_it_tg),
1284 
    .clk(clk_dst),
1285 
    .rst(rst_dst));
1286 
 
1287 
`define MODULE synchronizer
1288 
`BASE`MODULE sync1 (
1289 
`undef MODULE
1290 
    .d(got_it_tg),
1291 
    .q(got_it_tg_sync),
1292 
    .clk(clk_src),
1293 
    .rst(rst_src));
1294 
 
1295 
`define MODULE toggle2pulse
1296 
`BASE`MODULE t2p1 (
1297 
`undef MODULE
1298 
    .d(take_it_grant_tg_sync),
1299 
    .pl(got_it_pl),
1300 
    .clk(clk_src),
1301 
    .rst(rst_src));
1302 
 
1303 75 unneback 
endmodule
1304 
`endif
1305 17 unneback 
//////////////////////////////////////////////////////////////////////
1306 6 unneback 
////                                                              ////
1307 18 unneback 
////  Logic functions                                             ////
1308 
////                                                              ////
1309 
////  Description                                                 ////
1310 
////  Logic functions such as multiplexers                        ////
1311 
////                                                              ////
1312 
////                                                              ////
1313 
////  To Do:                                                      ////
1314 
////   -                                                          ////
1315 
////                                                              ////
1316 
////  Author(s):                                                  ////
1317 
////      - Michael Unneback, unneback@opencores.org              ////
1318 
////        ORSoC AB                                              ////
1319 
////                                                              ////
1320 
//////////////////////////////////////////////////////////////////////
1321 
////                                                              ////
1322 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1323 
////                                                              ////
1324 
//// This source file may be used and distributed without         ////
1325 
//// restriction provided that this copyright statement is not    ////
1326 
//// removed from the file and that any derivative work contains  ////
1327 
//// the original copyright notice and the associated disclaimer. ////
1328 
////                                                              ////
1329 
//// This source file is free software; you can redistribute it   ////
1330 
//// and/or modify it under the terms of the GNU Lesser General   ////
1331 
//// Public License as published by the Free Software Foundation; ////
1332 
//// either version 2.1 of the License, or (at your option) any   ////
1333 
//// later version.                                               ////
1334 
////                                                              ////
1335 
//// This source is distributed in the hope that it will be       ////
1336 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1337 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1338 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1339 
//// details.                                                     ////
1340 
////                                                              ////
1341 
//// You should have received a copy of the GNU Lesser General    ////
1342 
//// Public License along with this source; if not, download it   ////
1343 
//// from http://www.opencores.org/lgpl.shtml                     ////
1344 
////                                                              ////
1345 
//////////////////////////////////////////////////////////////////////
1346 40 unneback 
`ifdef MUX_ANDOR
1347 
`define MODULE mux_andor
1348 
module `BASE`MODULE ( a, sel, dout);
1349 
`undef MODULE
1350 36 unneback 
 
1351 
parameter width = 32;
1352 
parameter nr_of_ports = 4;
1353 
 
1354 
input [nr_of_ports*width-1:0] a;
1355 
input [nr_of_ports-1:0] sel;
1356 
output reg [width-1:0] dout;
1357 
 
1358 38 unneback 
integer i,j;
1359 
 
1360 36 unneback 
always @ (a, sel)
1361 
begin
1362 
    dout = a[width-1:0] & {width{sel[0]}};
1363 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1364 
        for (j=0;j<width;j=j+1)
1365 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1366 36 unneback 
end
1367 
 
1368 
endmodule
1369 40 unneback 
`endif
1370 36 unneback 
 
1371 40 unneback 
`ifdef MUX2_ANDOR
1372 
`define MODULE mux2_andor
1373 
module `BASE`MODULE ( a1, a0, sel, dout);
1374 
`undef MODULE
1375 18 unneback 
 
1376 34 unneback 
parameter width = 32;
1377 35 unneback 
localparam nr_of_ports = 2;
1378 34 unneback 
input [width-1:0] a1, a0;
1379 
input [nr_of_ports-1:0] sel;
1380 
output [width-1:0] dout;
1381 
 
1382 40 unneback 
`define MODULE mux_andor
1383 
`BASE`MODULE
1384 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1385 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1386 40 unneback 
`undef MODULE
1387 
 
1388 34 unneback 
endmodule
1389 40 unneback 
`endif
1390 34 unneback 
 
1391 40 unneback 
`ifdef MUX3_ANDOR
1392 
`define MODULE mux3_andor
1393 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1394 
`undef MODULE
1395 34 unneback 
 
1396 
parameter width = 32;
1397 35 unneback 
localparam nr_of_ports = 3;
1398 34 unneback 
input [width-1:0] a2, a1, a0;
1399 
input [nr_of_ports-1:0] sel;
1400 
output [width-1:0] dout;
1401 
 
1402 40 unneback 
`define MODULE mux_andor
1403 
`BASE`MODULE
1404 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1405 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1406 40 unneback 
`undef MODULE
1407 34 unneback 
endmodule
1408 40 unneback 
`endif
1409 34 unneback 
 
1410 40 unneback 
`ifdef MUX4_ANDOR
1411 
`define MODULE mux4_andor
1412 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1413 
`undef MODULE
1414 18 unneback 
 
1415 
parameter width = 32;
1416 35 unneback 
localparam nr_of_ports = 4;
1417 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1418 
input [nr_of_ports-1:0] sel;
1419 22 unneback 
output [width-1:0] dout;
1420 18 unneback 
 
1421 40 unneback 
`define MODULE mux_andor
1422 
`BASE`MODULE
1423 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1424 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1425 40 unneback 
`undef MODULE
1426 18 unneback 
 
1427 
endmodule
1428 40 unneback 
`endif
1429 18 unneback 
 
1430 40 unneback 
`ifdef MUX5_ANDOR
1431 
`define MODULE mux5_andor
1432 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1433 
`undef MODULE
1434 18 unneback 
 
1435 
parameter width = 32;
1436 35 unneback 
localparam nr_of_ports = 5;
1437 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1438 
input [nr_of_ports-1:0] sel;
1439 22 unneback 
output [width-1:0] dout;
1440 18 unneback 
 
1441 40 unneback 
`define MODULE mux_andor
1442 
`BASE`MODULE
1443 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1444 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1445 40 unneback 
`undef MODULE
1446 18 unneback 
 
1447 
endmodule
1448 40 unneback 
`endif
1449 18 unneback 
 
1450 40 unneback 
`ifdef MUX6_ANDOR
1451 
`define MODULE mux6_andor
1452 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1453 
`undef MODULE
1454 18 unneback 
 
1455 
parameter width = 32;
1456 35 unneback 
localparam nr_of_ports = 6;
1457 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1458 
input [nr_of_ports-1:0] sel;
1459 22 unneback 
output [width-1:0] dout;
1460 18 unneback 
 
1461 40 unneback 
`define MODULE mux_andor
1462 
`BASE`MODULE
1463 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1464 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1465 40 unneback 
`undef MODULE
1466 18 unneback 
 
1467 
endmodule
1468 40 unneback 
`endif
1469 43 unneback 
 
1470 
`ifdef PARITY
1471 
 
1472 
`define MODULE parity_generate
1473 
module `BASE`MODULE (data, parity);
1474 
`undef MODULE
1475 
parameter word_size = 32;
1476 
parameter chunk_size = 8;
1477 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1478 
input [word_size-1:0] data;
1479 
output reg [word_size/chunk_size-1:0] parity;
1480 
integer i,j;
1481 
always @ (data)
1482 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1483 
    parity[i] = parity_type;
1484 
    for (j=0;j<chunk_size;j=j+1) begin
1485 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1486 43 unneback 
    end
1487 
end
1488 
endmodule
1489 
 
1490 
`define MODULE parity_check
1491 
module `BASE`MODULE( data, parity, parity_error);
1492 
`undef MODULE
1493 
parameter word_size = 32;
1494 
parameter chunk_size = 8;
1495 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1496 
input [word_size-1:0] data;
1497 
input [word_size/chunk_size-1:0] parity;
1498 
output parity_error;
1499 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1500 43 unneback 
integer i,j;
1501 
always @ (data or parity)
1502 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1503 
    error_flag[i] = parity[i] ^ parity_type;
1504 
    for (j=0;j<chunk_size;j=j+1) begin
1505 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1506 43 unneback 
    end
1507 
end
1508 
assign parity_error = |error_flag;
1509 
endmodule
1510 
 
1511 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1512 
////                                                              ////
1513 
////  IO functions                                                ////
1514 
////                                                              ////
1515 
////  Description                                                 ////
1516 
////  IO functions such as IOB flip-flops                         ////
1517 
////                                                              ////
1518 
////                                                              ////
1519 
////  To Do:                                                      ////
1520 
////   -                                                          ////
1521 
////                                                              ////
1522 
////  Author(s):                                                  ////
1523 
////      - Michael Unneback, unneback@opencores.org              ////
1524 
////        ORSoC AB                                              ////
1525 
////                                                              ////
1526 18 unneback 
//////////////////////////////////////////////////////////////////////
1527 
////                                                              ////
1528 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1529 
////                                                              ////
1530 
//// This source file may be used and distributed without         ////
1531 
//// restriction provided that this copyright statement is not    ////
1532 
//// removed from the file and that any derivative work contains  ////
1533 
//// the original copyright notice and the associated disclaimer. ////
1534 
////                                                              ////
1535 
//// This source file is free software; you can redistribute it   ////
1536 
//// and/or modify it under the terms of the GNU Lesser General   ////
1537 
//// Public License as published by the Free Software Foundation; ////
1538 
//// either version 2.1 of the License, or (at your option) any   ////
1539 
//// later version.                                               ////
1540 
////                                                              ////
1541 
//// This source is distributed in the hope that it will be       ////
1542 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1543 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1544 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1545 
//// details.                                                     ////
1546 
////                                                              ////
1547 
//// You should have received a copy of the GNU Lesser General    ////
1548 
//// Public License along with this source; if not, download it   ////
1549 
//// from http://www.opencores.org/lgpl.shtml                     ////
1550 
////                                                              ////
1551 
//////////////////////////////////////////////////////////////////////
1552 45 unneback 
`timescale 1ns/1ns
1553 44 unneback 
`ifdef O_DFF
1554 
`define MODULE o_dff
1555 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1556 
`undef MODULE
1557 
parameter width = 1;
1558 45 unneback 
parameter reset_value = {width{1'b0}};
1559 
input  [width-1:0]  d_i;
1560 44 unneback 
output [width-1:0] o_pad;
1561 
input clk, rst;
1562 
wire [width-1:0] d_i_int `SYN_KEEP;
1563 45 unneback 
reg  [width-1:0] o_pad_int;
1564 44 unneback 
assign d_i_int = d_i;
1565 
genvar i;
1566 45 unneback 
generate
1567 44 unneback 
for (i=0;i<width;i=i+1) begin
1568 
    always @ (posedge clk or posedge rst)
1569 
    if (rst)
1570 45 unneback 
        o_pad_int[i] <= reset_value[i];
1571 44 unneback 
    else
1572 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1573 
    assign #1 o_pad[i] = o_pad_int[i];
1574 44 unneback 
end
1575 
endgenerate
1576 
endmodule
1577 
`endif
1578 
 
1579 45 unneback 
`timescale 1ns/1ns
1580 44 unneback 
`ifdef IO_DFF_OE
1581 
`define MODULE io_dff_oe
1582 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1583 
`undef MODULE
1584 
parameter width = 1;
1585 
input  [width-1:0] d_o;
1586 
output reg [width-1:0] d_i;
1587 
input oe;
1588 
inout [width-1:0] io_pad;
1589 
input clk, rst;
1590 
wire [width-1:0] oe_d `SYN_KEEP;
1591 
reg [width-1:0] oe_q;
1592 
reg [width-1:0] d_o_q;
1593 
assign oe_d = {width{oe}};
1594 
genvar i;
1595 
generate
1596 
for (i=0;i<width;i=i+1) begin
1597 
    always @ (posedge clk or posedge rst)
1598 
    if (rst)
1599 
        oe_q[i] <= 1'b0;
1600 
    else
1601 
        oe_q[i] <= oe_d[i];
1602 
    always @ (posedge clk or posedge rst)
1603 
    if (rst)
1604 
        d_o_q[i] <= 1'b0;
1605 
    else
1606 
        d_o_q[i] <= d_o[i];
1607 
    always @ (posedge clk or posedge rst)
1608 
    if (rst)
1609 
        d_i[i] <= 1'b0;
1610 
    else
1611 
        d_i[i] <= io_pad[i];
1612 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1613 44 unneback 
end
1614 
endgenerate
1615 
endmodule
1616 
`endif
1617 
`ifdef CNT_BIN
1618 
//////////////////////////////////////////////////////////////////////
1619 
////                                                              ////
1620 6 unneback 
////  Versatile counter                                           ////
1621 
////                                                              ////
1622 
////  Description                                                 ////
1623 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1624 
////  counter                                                     ////
1625 
////                                                              ////
1626 
////  To Do:                                                      ////
1627 
////   - add LFSR with more taps                                  ////
1628 
////                                                              ////
1629 
////  Author(s):                                                  ////
1630 
////      - Michael Unneback, unneback@opencores.org              ////
1631 
////        ORSoC AB                                              ////
1632 
////                                                              ////
1633 
//////////////////////////////////////////////////////////////////////
1634 
////                                                              ////
1635 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1636 
////                                                              ////
1637 
//// This source file may be used and distributed without         ////
1638 
//// restriction provided that this copyright statement is not    ////
1639 
//// removed from the file and that any derivative work contains  ////
1640 
//// the original copyright notice and the associated disclaimer. ////
1641 
////                                                              ////
1642 
//// This source file is free software; you can redistribute it   ////
1643 
//// and/or modify it under the terms of the GNU Lesser General   ////
1644 
//// Public License as published by the Free Software Foundation; ////
1645 
//// either version 2.1 of the License, or (at your option) any   ////
1646 
//// later version.                                               ////
1647 
////                                                              ////
1648 
//// This source is distributed in the hope that it will be       ////
1649 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1650 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1651 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1652 
//// details.                                                     ////
1653 
////                                                              ////
1654 
//// You should have received a copy of the GNU Lesser General    ////
1655 
//// Public License along with this source; if not, download it   ////
1656 
//// from http://www.opencores.org/lgpl.shtml                     ////
1657 
////                                                              ////
1658 
//////////////////////////////////////////////////////////////////////
1659 
 
1660 
// binary counter
1661 22 unneback 
 
1662 40 unneback 
`define MODULE cnt_bin
1663 
module `BASE`MODULE (
1664 
`undef MODULE
1665 
 q, rst, clk);
1666 
 
1667 22 unneback 
   parameter length = 4;
1668 
   output [length:1] q;
1669 
   input rst;
1670 
   input clk;
1671 
 
1672 
   parameter clear_value = 0;
1673 
   parameter set_value = 1;
1674 
   parameter wrap_value = 0;
1675 
   parameter level1_value = 15;
1676 
 
1677 
   reg  [length:1] qi;
1678 
   wire [length:1] q_next;
1679 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1680 
 
1681 
   always @ (posedge clk or posedge rst)
1682 
     if (rst)
1683 
       qi <= {length{1'b0}};
1684 
     else
1685 
       qi <= q_next;
1686 
 
1687 
   assign q = qi;
1688 
 
1689 
endmodule
1690 40 unneback 
`endif
1691 
`ifdef CNT_BIN_CLEAR
1692 22 unneback 
//////////////////////////////////////////////////////////////////////
1693 
////                                                              ////
1694 
////  Versatile counter                                           ////
1695 
////                                                              ////
1696 
////  Description                                                 ////
1697 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1698 
////  counter                                                     ////
1699 
////                                                              ////
1700 
////  To Do:                                                      ////
1701 
////   - add LFSR with more taps                                  ////
1702 
////                                                              ////
1703 
////  Author(s):                                                  ////
1704 
////      - Michael Unneback, unneback@opencores.org              ////
1705 
////        ORSoC AB                                              ////
1706 
////                                                              ////
1707 
//////////////////////////////////////////////////////////////////////
1708 
////                                                              ////
1709 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1710 
////                                                              ////
1711 
//// This source file may be used and distributed without         ////
1712 
//// restriction provided that this copyright statement is not    ////
1713 
//// removed from the file and that any derivative work contains  ////
1714 
//// the original copyright notice and the associated disclaimer. ////
1715 
////                                                              ////
1716 
//// This source file is free software; you can redistribute it   ////
1717 
//// and/or modify it under the terms of the GNU Lesser General   ////
1718 
//// Public License as published by the Free Software Foundation; ////
1719 
//// either version 2.1 of the License, or (at your option) any   ////
1720 
//// later version.                                               ////
1721 
////                                                              ////
1722 
//// This source is distributed in the hope that it will be       ////
1723 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1724 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1725 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1726 
//// details.                                                     ////
1727 
////                                                              ////
1728 
//// You should have received a copy of the GNU Lesser General    ////
1729 
//// Public License along with this source; if not, download it   ////
1730 
//// from http://www.opencores.org/lgpl.shtml                     ////
1731 
////                                                              ////
1732 
//////////////////////////////////////////////////////////////////////
1733 
 
1734 
// binary counter
1735 
 
1736 40 unneback 
`define MODULE cnt_bin_clear
1737 
module `BASE`MODULE (
1738 
`undef MODULE
1739 
 clear, q, rst, clk);
1740 
 
1741 22 unneback 
   parameter length = 4;
1742 
   input clear;
1743 
   output [length:1] q;
1744 
   input rst;
1745 
   input clk;
1746 
 
1747 
   parameter clear_value = 0;
1748 
   parameter set_value = 1;
1749 
   parameter wrap_value = 0;
1750 
   parameter level1_value = 15;
1751 
 
1752 
   reg  [length:1] qi;
1753 
   wire [length:1] q_next;
1754 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1755 
 
1756 
   always @ (posedge clk or posedge rst)
1757 
     if (rst)
1758 
       qi <= {length{1'b0}};
1759 
     else
1760 
       qi <= q_next;
1761 
 
1762 
   assign q = qi;
1763 
 
1764 
endmodule
1765 40 unneback 
`endif
1766 
`ifdef CNT_BIN_CE
1767 22 unneback 
//////////////////////////////////////////////////////////////////////
1768 
////                                                              ////
1769 
////  Versatile counter                                           ////
1770 
////                                                              ////
1771 
////  Description                                                 ////
1772 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1773 
////  counter                                                     ////
1774 
////                                                              ////
1775 
////  To Do:                                                      ////
1776 
////   - add LFSR with more taps                                  ////
1777 
////                                                              ////
1778 
////  Author(s):                                                  ////
1779 
////      - Michael Unneback, unneback@opencores.org              ////
1780 
////        ORSoC AB                                              ////
1781 
////                                                              ////
1782 
//////////////////////////////////////////////////////////////////////
1783 
////                                                              ////
1784 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1785 
////                                                              ////
1786 
//// This source file may be used and distributed without         ////
1787 
//// restriction provided that this copyright statement is not    ////
1788 
//// removed from the file and that any derivative work contains  ////
1789 
//// the original copyright notice and the associated disclaimer. ////
1790 
////                                                              ////
1791 
//// This source file is free software; you can redistribute it   ////
1792 
//// and/or modify it under the terms of the GNU Lesser General   ////
1793 
//// Public License as published by the Free Software Foundation; ////
1794 
//// either version 2.1 of the License, or (at your option) any   ////
1795 
//// later version.                                               ////
1796 
////                                                              ////
1797 
//// This source is distributed in the hope that it will be       ////
1798 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1799 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1800 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1801 
//// details.                                                     ////
1802 
////                                                              ////
1803 
//// You should have received a copy of the GNU Lesser General    ////
1804 
//// Public License along with this source; if not, download it   ////
1805 
//// from http://www.opencores.org/lgpl.shtml                     ////
1806 
////                                                              ////
1807 
//////////////////////////////////////////////////////////////////////
1808 
 
1809 
// binary counter
1810 6 unneback 
 
1811 40 unneback 
`define MODULE cnt_bin_ce
1812 
module `BASE`MODULE (
1813 
`undef MODULE
1814 
 cke, q, rst, clk);
1815 
 
1816 6 unneback 
   parameter length = 4;
1817 
   input cke;
1818 
   output [length:1] q;
1819 
   input rst;
1820 
   input clk;
1821 
 
1822 
   parameter clear_value = 0;
1823 
   parameter set_value = 1;
1824 
   parameter wrap_value = 0;
1825 
   parameter level1_value = 15;
1826 
 
1827 
   reg  [length:1] qi;
1828 
   wire [length:1] q_next;
1829 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1830 
 
1831 
   always @ (posedge clk or posedge rst)
1832 
     if (rst)
1833 
       qi <= {length{1'b0}};
1834 
     else
1835 
     if (cke)
1836 
       qi <= q_next;
1837 
 
1838 
   assign q = qi;
1839 
 
1840 
endmodule
1841 40 unneback 
`endif
1842 
`ifdef CNT_BIN_CE_CLEAR
1843 6 unneback 
//////////////////////////////////////////////////////////////////////
1844 
////                                                              ////
1845 
////  Versatile counter                                           ////
1846 
////                                                              ////
1847 
////  Description                                                 ////
1848 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1849 
////  counter                                                     ////
1850 
////                                                              ////
1851 
////  To Do:                                                      ////
1852 
////   - add LFSR with more taps                                  ////
1853 
////                                                              ////
1854 
////  Author(s):                                                  ////
1855 
////      - Michael Unneback, unneback@opencores.org              ////
1856 
////        ORSoC AB                                              ////
1857 
////                                                              ////
1858 
//////////////////////////////////////////////////////////////////////
1859 
////                                                              ////
1860 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1861 
////                                                              ////
1862 
//// This source file may be used and distributed without         ////
1863 
//// restriction provided that this copyright statement is not    ////
1864 
//// removed from the file and that any derivative work contains  ////
1865 
//// the original copyright notice and the associated disclaimer. ////
1866 
////                                                              ////
1867 
//// This source file is free software; you can redistribute it   ////
1868 
//// and/or modify it under the terms of the GNU Lesser General   ////
1869 
//// Public License as published by the Free Software Foundation; ////
1870 
//// either version 2.1 of the License, or (at your option) any   ////
1871 
//// later version.                                               ////
1872 
////                                                              ////
1873 
//// This source is distributed in the hope that it will be       ////
1874 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1875 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1876 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1877 
//// details.                                                     ////
1878 
////                                                              ////
1879 
//// You should have received a copy of the GNU Lesser General    ////
1880 
//// Public License along with this source; if not, download it   ////
1881 
//// from http://www.opencores.org/lgpl.shtml                     ////
1882 
////                                                              ////
1883 
//////////////////////////////////////////////////////////////////////
1884 
 
1885 
// binary counter
1886 
 
1887 40 unneback 
`define MODULE cnt_bin_ce_clear
1888 
module `BASE`MODULE (
1889 
`undef MODULE
1890 
 clear, cke, q, rst, clk);
1891 
 
1892 6 unneback 
   parameter length = 4;
1893 
   input clear;
1894 
   input cke;
1895 
   output [length:1] q;
1896 
   input rst;
1897 
   input clk;
1898 
 
1899 
   parameter clear_value = 0;
1900 
   parameter set_value = 1;
1901 
   parameter wrap_value = 0;
1902 
   parameter level1_value = 15;
1903 
 
1904 
   reg  [length:1] qi;
1905 
   wire [length:1] q_next;
1906 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1907 
 
1908 
   always @ (posedge clk or posedge rst)
1909 
     if (rst)
1910 
       qi <= {length{1'b0}};
1911 
     else
1912 
     if (cke)
1913 
       qi <= q_next;
1914 
 
1915 
   assign q = qi;
1916 
 
1917 
endmodule
1918 40 unneback 
`endif
1919 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1920 6 unneback 
//////////////////////////////////////////////////////////////////////
1921 
////                                                              ////
1922 
////  Versatile counter                                           ////
1923 
////                                                              ////
1924 
////  Description                                                 ////
1925 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1926 
////  counter                                                     ////
1927 
////                                                              ////
1928 
////  To Do:                                                      ////
1929 
////   - add LFSR with more taps                                  ////
1930 
////                                                              ////
1931 
////  Author(s):                                                  ////
1932 
////      - Michael Unneback, unneback@opencores.org              ////
1933 
////        ORSoC AB                                              ////
1934 
////                                                              ////
1935 
//////////////////////////////////////////////////////////////////////
1936 
////                                                              ////
1937 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1938 
////                                                              ////
1939 
//// This source file may be used and distributed without         ////
1940 
//// restriction provided that this copyright statement is not    ////
1941 
//// removed from the file and that any derivative work contains  ////
1942 
//// the original copyright notice and the associated disclaimer. ////
1943 
////                                                              ////
1944 
//// This source file is free software; you can redistribute it   ////
1945 
//// and/or modify it under the terms of the GNU Lesser General   ////
1946 
//// Public License as published by the Free Software Foundation; ////
1947 
//// either version 2.1 of the License, or (at your option) any   ////
1948 
//// later version.                                               ////
1949 
////                                                              ////
1950 
//// This source is distributed in the hope that it will be       ////
1951 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1952 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1953 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1954 
//// details.                                                     ////
1955 
////                                                              ////
1956 
//// You should have received a copy of the GNU Lesser General    ////
1957 
//// Public License along with this source; if not, download it   ////
1958 
//// from http://www.opencores.org/lgpl.shtml                     ////
1959 
////                                                              ////
1960 
//////////////////////////////////////////////////////////////////////
1961 
 
1962 
// binary counter
1963 29 unneback 
 
1964 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1965 
module `BASE`MODULE (
1966 
`undef MODULE
1967 
 clear, cke, q, level1, level2, rst, clk);
1968 
 
1969 29 unneback 
   parameter length = 4;
1970 
   input clear;
1971 
   input cke;
1972 
   output [length:1] q;
1973 
   output reg level1;
1974 
   output reg level2;
1975 
   input rst;
1976 
   input clk;
1977 
 
1978 
   parameter clear_value = 0;
1979 
   parameter set_value = 1;
1980 30 unneback 
   parameter wrap_value = 15;
1981 
   parameter level1_value = 8;
1982 
   parameter level2_value = 15;
1983 29 unneback 
 
1984 
   wire rew;
1985 30 unneback 
   assign rew = 1'b0;
1986 29 unneback 
   reg  [length:1] qi;
1987 
   wire [length:1] q_next;
1988 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1989 
 
1990 
   always @ (posedge clk or posedge rst)
1991 
     if (rst)
1992 
       qi <= {length{1'b0}};
1993 
     else
1994 
     if (cke)
1995 
       qi <= q_next;
1996 
 
1997 
   assign q = qi;
1998 
 
1999 
 
2000 
    always @ (posedge clk or posedge rst)
2001 
    if (rst)
2002 
        level1 <= 1'b0;
2003 
    else
2004 
    if (cke)
2005 
    if (clear)
2006 
        level1 <= 1'b0;
2007 
    else if (q_next == level1_value)
2008 
        level1 <= 1'b1;
2009 
    else if (qi == level1_value & rew)
2010 
        level1 <= 1'b0;
2011 
 
2012 
    always @ (posedge clk or posedge rst)
2013 
    if (rst)
2014 
        level2 <= 1'b0;
2015 
    else
2016 
    if (cke)
2017 
    if (clear)
2018 
        level2 <= 1'b0;
2019 
    else if (q_next == level2_value)
2020 
        level2 <= 1'b1;
2021 
    else if (qi == level2_value & rew)
2022 
        level2 <= 1'b0;
2023 
endmodule
2024 40 unneback 
`endif
2025 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2026 29 unneback 
//////////////////////////////////////////////////////////////////////
2027 
////                                                              ////
2028 
////  Versatile counter                                           ////
2029 
////                                                              ////
2030 
////  Description                                                 ////
2031 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2032 
////  counter                                                     ////
2033 
////                                                              ////
2034 
////  To Do:                                                      ////
2035 
////   - add LFSR with more taps                                  ////
2036 
////                                                              ////
2037 
////  Author(s):                                                  ////
2038 
////      - Michael Unneback, unneback@opencores.org              ////
2039 
////        ORSoC AB                                              ////
2040 
////                                                              ////
2041 
//////////////////////////////////////////////////////////////////////
2042 
////                                                              ////
2043 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2044 
////                                                              ////
2045 
//// This source file may be used and distributed without         ////
2046 
//// restriction provided that this copyright statement is not    ////
2047 
//// removed from the file and that any derivative work contains  ////
2048 
//// the original copyright notice and the associated disclaimer. ////
2049 
////                                                              ////
2050 
//// This source file is free software; you can redistribute it   ////
2051 
//// and/or modify it under the terms of the GNU Lesser General   ////
2052 
//// Public License as published by the Free Software Foundation; ////
2053 
//// either version 2.1 of the License, or (at your option) any   ////
2054 
//// later version.                                               ////
2055 
////                                                              ////
2056 
//// This source is distributed in the hope that it will be       ////
2057 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2058 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2059 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2060 
//// details.                                                     ////
2061 
////                                                              ////
2062 
//// You should have received a copy of the GNU Lesser General    ////
2063 
//// Public License along with this source; if not, download it   ////
2064 
//// from http://www.opencores.org/lgpl.shtml                     ////
2065 
////                                                              ////
2066 
//////////////////////////////////////////////////////////////////////
2067 
 
2068 
// binary counter
2069 6 unneback 
 
2070 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
2071 
module `BASE`MODULE (
2072 
`undef MODULE
2073 
 clear, set, cke, rew, q, rst, clk);
2074 
 
2075 6 unneback 
   parameter length = 4;
2076 
   input clear;
2077 
   input set;
2078 
   input cke;
2079 
   input rew;
2080 
   output [length:1] q;
2081 
   input rst;
2082 
   input clk;
2083 
 
2084 
   parameter clear_value = 0;
2085 
   parameter set_value = 1;
2086 
   parameter wrap_value = 0;
2087 
   parameter level1_value = 15;
2088 
 
2089 
   reg  [length:1] qi;
2090 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2091 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2092 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2093 
   assign q_next = rew ? q_next_rew : q_next_fw;
2094 
 
2095 
   always @ (posedge clk or posedge rst)
2096 
     if (rst)
2097 
       qi <= {length{1'b0}};
2098 
     else
2099 
     if (cke)
2100 
       qi <= q_next;
2101 
 
2102 
   assign q = qi;
2103 
 
2104 
endmodule
2105 40 unneback 
`endif
2106 
`ifdef CNT_BIN_CE_REW_L1
2107 6 unneback 
//////////////////////////////////////////////////////////////////////
2108 
////                                                              ////
2109 
////  Versatile counter                                           ////
2110 
////                                                              ////
2111 
////  Description                                                 ////
2112 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2113 
////  counter                                                     ////
2114 
////                                                              ////
2115 
////  To Do:                                                      ////
2116 
////   - add LFSR with more taps                                  ////
2117 
////                                                              ////
2118 
////  Author(s):                                                  ////
2119 
////      - Michael Unneback, unneback@opencores.org              ////
2120 
////        ORSoC AB                                              ////
2121 
////                                                              ////
2122 
//////////////////////////////////////////////////////////////////////
2123 
////                                                              ////
2124 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2125 
////                                                              ////
2126 
//// This source file may be used and distributed without         ////
2127 
//// restriction provided that this copyright statement is not    ////
2128 
//// removed from the file and that any derivative work contains  ////
2129 
//// the original copyright notice and the associated disclaimer. ////
2130 
////                                                              ////
2131 
//// This source file is free software; you can redistribute it   ////
2132 
//// and/or modify it under the terms of the GNU Lesser General   ////
2133 
//// Public License as published by the Free Software Foundation; ////
2134 
//// either version 2.1 of the License, or (at your option) any   ////
2135 
//// later version.                                               ////
2136 
////                                                              ////
2137 
//// This source is distributed in the hope that it will be       ////
2138 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2139 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2140 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2141 
//// details.                                                     ////
2142 
////                                                              ////
2143 
//// You should have received a copy of the GNU Lesser General    ////
2144 
//// Public License along with this source; if not, download it   ////
2145 
//// from http://www.opencores.org/lgpl.shtml                     ////
2146 
////                                                              ////
2147 
//////////////////////////////////////////////////////////////////////
2148 
 
2149 
// binary counter
2150 
 
2151 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
2152 
module `BASE`MODULE (
2153 
`undef MODULE
2154 
 cke, rew, level1, rst, clk);
2155 
 
2156 6 unneback 
   parameter length = 4;
2157 
   input cke;
2158 
   input rew;
2159 
   output reg level1;
2160 
   input rst;
2161 
   input clk;
2162 
 
2163 
   parameter clear_value = 0;
2164 
   parameter set_value = 1;
2165 
   parameter wrap_value = 1;
2166 
   parameter level1_value = 15;
2167 
 
2168 29 unneback 
   wire clear;
2169 30 unneback 
   assign clear = 1'b0;
2170 6 unneback 
   reg  [length:1] qi;
2171 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2172 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2173 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2174 
   assign q_next = rew ? q_next_rew : q_next_fw;
2175 
 
2176 
   always @ (posedge clk or posedge rst)
2177 
     if (rst)
2178 
       qi <= {length{1'b0}};
2179 
     else
2180 
     if (cke)
2181 
       qi <= q_next;
2182 
 
2183 
 
2184 
 
2185 
    always @ (posedge clk or posedge rst)
2186 
    if (rst)
2187 
        level1 <= 1'b0;
2188 
    else
2189 
    if (cke)
2190 29 unneback 
    if (clear)
2191 
        level1 <= 1'b0;
2192 
    else if (q_next == level1_value)
2193 6 unneback 
        level1 <= 1'b1;
2194 
    else if (qi == level1_value & rew)
2195 
        level1 <= 1'b0;
2196 
endmodule
2197 40 unneback 
`endif
2198 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2199 6 unneback 
//////////////////////////////////////////////////////////////////////
2200 
////                                                              ////
2201 
////  Versatile counter                                           ////
2202 
////                                                              ////
2203 
////  Description                                                 ////
2204 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2205 
////  counter                                                     ////
2206 
////                                                              ////
2207 
////  To Do:                                                      ////
2208 
////   - add LFSR with more taps                                  ////
2209 
////                                                              ////
2210 
////  Author(s):                                                  ////
2211 
////      - Michael Unneback, unneback@opencores.org              ////
2212 
////        ORSoC AB                                              ////
2213 
////                                                              ////
2214 
//////////////////////////////////////////////////////////////////////
2215 
////                                                              ////
2216 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2217 
////                                                              ////
2218 
//// This source file may be used and distributed without         ////
2219 
//// restriction provided that this copyright statement is not    ////
2220 
//// removed from the file and that any derivative work contains  ////
2221 
//// the original copyright notice and the associated disclaimer. ////
2222 
////                                                              ////
2223 
//// This source file is free software; you can redistribute it   ////
2224 
//// and/or modify it under the terms of the GNU Lesser General   ////
2225 
//// Public License as published by the Free Software Foundation; ////
2226 
//// either version 2.1 of the License, or (at your option) any   ////
2227 
//// later version.                                               ////
2228 
////                                                              ////
2229 
//// This source is distributed in the hope that it will be       ////
2230 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2231 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2232 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2233 
//// details.                                                     ////
2234 
////                                                              ////
2235 
//// You should have received a copy of the GNU Lesser General    ////
2236 
//// Public License along with this source; if not, download it   ////
2237 
//// from http://www.opencores.org/lgpl.shtml                     ////
2238 
////                                                              ////
2239 
//////////////////////////////////////////////////////////////////////
2240 
 
2241 25 unneback 
// binary counter
2242 
 
2243 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2244 
module `BASE`MODULE (
2245 
`undef MODULE
2246 
 cke, rew, zq, level1, rst, clk);
2247 
 
2248 25 unneback 
   parameter length = 4;
2249 
   input cke;
2250 
   input rew;
2251 
   output reg zq;
2252 
   output reg level1;
2253 
   input rst;
2254 
   input clk;
2255 
 
2256 
   parameter clear_value = 0;
2257 
   parameter set_value = 1;
2258 
   parameter wrap_value = 1;
2259 
   parameter level1_value = 15;
2260 
 
2261 29 unneback 
   wire clear;
2262 30 unneback 
   assign clear = 1'b0;
2263 25 unneback 
   reg  [length:1] qi;
2264 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2265 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2266 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2267 
   assign q_next = rew ? q_next_rew : q_next_fw;
2268 
 
2269 
   always @ (posedge clk or posedge rst)
2270 
     if (rst)
2271 
       qi <= {length{1'b0}};
2272 
     else
2273 
     if (cke)
2274 
       qi <= q_next;
2275 
 
2276 
 
2277 
 
2278 
   always @ (posedge clk or posedge rst)
2279 
     if (rst)
2280 
       zq <= 1'b1;
2281 
     else
2282 
     if (cke)
2283 
       zq <= q_next == {length{1'b0}};
2284 
 
2285 
    always @ (posedge clk or posedge rst)
2286 
    if (rst)
2287 
        level1 <= 1'b0;
2288 
    else
2289 
    if (cke)
2290 29 unneback 
    if (clear)
2291 
        level1 <= 1'b0;
2292 
    else if (q_next == level1_value)
2293 25 unneback 
        level1 <= 1'b1;
2294 
    else if (qi == level1_value & rew)
2295 
        level1 <= 1'b0;
2296 
endmodule
2297 40 unneback 
`endif
2298 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2299 25 unneback 
//////////////////////////////////////////////////////////////////////
2300 
////                                                              ////
2301 
////  Versatile counter                                           ////
2302 
////                                                              ////
2303 
////  Description                                                 ////
2304 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2305 
////  counter                                                     ////
2306 
////                                                              ////
2307 
////  To Do:                                                      ////
2308 
////   - add LFSR with more taps                                  ////
2309 
////                                                              ////
2310 
////  Author(s):                                                  ////
2311 
////      - Michael Unneback, unneback@opencores.org              ////
2312 
////        ORSoC AB                                              ////
2313 
////                                                              ////
2314 
//////////////////////////////////////////////////////////////////////
2315 
////                                                              ////
2316 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2317 
////                                                              ////
2318 
//// This source file may be used and distributed without         ////
2319 
//// restriction provided that this copyright statement is not    ////
2320 
//// removed from the file and that any derivative work contains  ////
2321 
//// the original copyright notice and the associated disclaimer. ////
2322 
////                                                              ////
2323 
//// This source file is free software; you can redistribute it   ////
2324 
//// and/or modify it under the terms of the GNU Lesser General   ////
2325 
//// Public License as published by the Free Software Foundation; ////
2326 
//// either version 2.1 of the License, or (at your option) any   ////
2327 
//// later version.                                               ////
2328 
////                                                              ////
2329 
//// This source is distributed in the hope that it will be       ////
2330 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2331 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2332 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2333 
//// details.                                                     ////
2334 
////                                                              ////
2335 
//// You should have received a copy of the GNU Lesser General    ////
2336 
//// Public License along with this source; if not, download it   ////
2337 
//// from http://www.opencores.org/lgpl.shtml                     ////
2338 
////                                                              ////
2339 
//////////////////////////////////////////////////////////////////////
2340 
 
2341 
// binary counter
2342 
 
2343 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2344 
module `BASE`MODULE (
2345 
`undef MODULE
2346 
 cke, rew, q, zq, level1, rst, clk);
2347 
 
2348 25 unneback 
   parameter length = 4;
2349 
   input cke;
2350 
   input rew;
2351 
   output [length:1] q;
2352 
   output reg zq;
2353 
   output reg level1;
2354 
   input rst;
2355 
   input clk;
2356 
 
2357 
   parameter clear_value = 0;
2358 
   parameter set_value = 1;
2359 
   parameter wrap_value = 1;
2360 
   parameter level1_value = 15;
2361 
 
2362 29 unneback 
   wire clear;
2363 30 unneback 
   assign clear = 1'b0;
2364 25 unneback 
   reg  [length:1] qi;
2365 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2366 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2367 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2368 
   assign q_next = rew ? q_next_rew : q_next_fw;
2369 
 
2370 
   always @ (posedge clk or posedge rst)
2371 
     if (rst)
2372 
       qi <= {length{1'b0}};
2373 
     else
2374 
     if (cke)
2375 
       qi <= q_next;
2376 
 
2377 
   assign q = qi;
2378 
 
2379 
 
2380 
   always @ (posedge clk or posedge rst)
2381 
     if (rst)
2382 
       zq <= 1'b1;
2383 
     else
2384 
     if (cke)
2385 
       zq <= q_next == {length{1'b0}};
2386 
 
2387 
    always @ (posedge clk or posedge rst)
2388 
    if (rst)
2389 
        level1 <= 1'b0;
2390 
    else
2391 
    if (cke)
2392 29 unneback 
    if (clear)
2393 
        level1 <= 1'b0;
2394 
    else if (q_next == level1_value)
2395 25 unneback 
        level1 <= 1'b1;
2396 
    else if (qi == level1_value & rew)
2397 
        level1 <= 1'b0;
2398 
endmodule
2399 40 unneback 
`endif
2400 
`ifdef CNT_LFSR_ZQ
2401 25 unneback 
//////////////////////////////////////////////////////////////////////
2402 
////                                                              ////
2403 
////  Versatile counter                                           ////
2404 
////                                                              ////
2405 
////  Description                                                 ////
2406 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2407 
////  counter                                                     ////
2408 
////                                                              ////
2409 
////  To Do:                                                      ////
2410 
////   - add LFSR with more taps                                  ////
2411 
////                                                              ////
2412 
////  Author(s):                                                  ////
2413 
////      - Michael Unneback, unneback@opencores.org              ////
2414 
////        ORSoC AB                                              ////
2415 
////                                                              ////
2416 
//////////////////////////////////////////////////////////////////////
2417 
////                                                              ////
2418 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2419 
////                                                              ////
2420 
//// This source file may be used and distributed without         ////
2421 
//// restriction provided that this copyright statement is not    ////
2422 
//// removed from the file and that any derivative work contains  ////
2423 
//// the original copyright notice and the associated disclaimer. ////
2424 
////                                                              ////
2425 
//// This source file is free software; you can redistribute it   ////
2426 
//// and/or modify it under the terms of the GNU Lesser General   ////
2427 
//// Public License as published by the Free Software Foundation; ////
2428 
//// either version 2.1 of the License, or (at your option) any   ////
2429 
//// later version.                                               ////
2430 
////                                                              ////
2431 
//// This source is distributed in the hope that it will be       ////
2432 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2433 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2434 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2435 
//// details.                                                     ////
2436 
////                                                              ////
2437 
//// You should have received a copy of the GNU Lesser General    ////
2438 
//// Public License along with this source; if not, download it   ////
2439 
//// from http://www.opencores.org/lgpl.shtml                     ////
2440 
////                                                              ////
2441 
//////////////////////////////////////////////////////////////////////
2442 
 
2443 6 unneback 
// LFSR counter
2444 
 
2445 40 unneback 
`define MODULE cnt_lfsr_zq
2446 
module `BASE`MODULE (
2447 
`undef MODULE
2448 
 zq, rst, clk);
2449 
 
2450 6 unneback 
   parameter length = 4;
2451 
   output reg zq;
2452 
   input rst;
2453 
   input clk;
2454 
 
2455 
   parameter clear_value = 0;
2456 
   parameter set_value = 1;
2457 
   parameter wrap_value = 8;
2458 
   parameter level1_value = 15;
2459 
 
2460 
   reg  [length:1] qi;
2461 
   reg lfsr_fb;
2462 
   wire [length:1] q_next;
2463 
   reg [32:1] polynom;
2464 
   integer i;
2465 
 
2466 
   always @ (qi)
2467 
   begin
2468 
        case (length)
2469 
         2: polynom = 32'b11;                               // 0x3
2470 
         3: polynom = 32'b110;                              // 0x6
2471 
         4: polynom = 32'b1100;                             // 0xC
2472 
         5: polynom = 32'b10100;                            // 0x14
2473 
         6: polynom = 32'b110000;                           // 0x30
2474 
         7: polynom = 32'b1100000;                          // 0x60
2475 
         8: polynom = 32'b10111000;                         // 0xb8
2476 
         9: polynom = 32'b100010000;                        // 0x110
2477 
        10: polynom = 32'b1001000000;                       // 0x240
2478 
        11: polynom = 32'b10100000000;                      // 0x500
2479 
        12: polynom = 32'b100000101001;                     // 0x829
2480 
        13: polynom = 32'b1000000001100;                    // 0x100C
2481 
        14: polynom = 32'b10000000010101;                   // 0x2015
2482 
        15: polynom = 32'b110000000000000;                  // 0x6000
2483 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2484 
        17: polynom = 32'b10010000000000000;                // 0x12000
2485 
        18: polynom = 32'b100000010000000000;               // 0x20400
2486 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2487 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2488 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2489 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2490 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2491 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2492 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2493 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2494 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2495 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2496 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2497 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2498 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2499 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2500 
        default: polynom = 32'b0;
2501 
        endcase
2502 
        lfsr_fb = qi[length];
2503 
        for (i=length-1; i>=1; i=i-1) begin
2504 
            if (polynom[i])
2505 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2506 
        end
2507 
    end
2508 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2509 
 
2510 
   always @ (posedge clk or posedge rst)
2511 
     if (rst)
2512 
       qi <= {length{1'b0}};
2513 
     else
2514 
       qi <= q_next;
2515 
 
2516 
 
2517 
 
2518 
   always @ (posedge clk or posedge rst)
2519 
     if (rst)
2520 
       zq <= 1'b1;
2521 
     else
2522 
       zq <= q_next == {length{1'b0}};
2523 
endmodule
2524 40 unneback 
`endif
2525 75 unneback 
`ifdef CNT_LFSR_CE
2526 
//////////////////////////////////////////////////////////////////////
2527 
////                                                              ////
2528 
////  Versatile counter                                           ////
2529 
////                                                              ////
2530 
////  Description                                                 ////
2531 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2532 
////  counter                                                     ////
2533 
////                                                              ////
2534 
////  To Do:                                                      ////
2535 
////   - add LFSR with more taps                                  ////
2536 
////                                                              ////
2537 
////  Author(s):                                                  ////
2538 
////      - Michael Unneback, unneback@opencores.org              ////
2539 
////        ORSoC AB                                              ////
2540 
////                                                              ////
2541 
//////////////////////////////////////////////////////////////////////
2542 
////                                                              ////
2543 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2544 
////                                                              ////
2545 
//// This source file may be used and distributed without         ////
2546 
//// restriction provided that this copyright statement is not    ////
2547 
//// removed from the file and that any derivative work contains  ////
2548 
//// the original copyright notice and the associated disclaimer. ////
2549 
////                                                              ////
2550 
//// This source file is free software; you can redistribute it   ////
2551 
//// and/or modify it under the terms of the GNU Lesser General   ////
2552 
//// Public License as published by the Free Software Foundation; ////
2553 
//// either version 2.1 of the License, or (at your option) any   ////
2554 
//// later version.                                               ////
2555 
////                                                              ////
2556 
//// This source is distributed in the hope that it will be       ////
2557 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2558 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2559 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2560 
//// details.                                                     ////
2561 
////                                                              ////
2562 
//// You should have received a copy of the GNU Lesser General    ////
2563 
//// Public License along with this source; if not, download it   ////
2564 
//// from http://www.opencores.org/lgpl.shtml                     ////
2565 
////                                                              ////
2566 
//////////////////////////////////////////////////////////////////////
2567 
 
2568 
// LFSR counter
2569 
 
2570 
`define MODULE cnt_lfsr_ce
2571 
module `BASE`MODULE (
2572 
`undef MODULE
2573 
 cke, zq, rst, clk);
2574 
 
2575 
   parameter length = 4;
2576 
   input cke;
2577 
   output reg zq;
2578 
   input rst;
2579 
   input clk;
2580 
 
2581 
   parameter clear_value = 0;
2582 
   parameter set_value = 1;
2583 
   parameter wrap_value = 0;
2584 
   parameter level1_value = 15;
2585 
 
2586 
   reg  [length:1] qi;
2587 
   reg lfsr_fb;
2588 
   wire [length:1] q_next;
2589 
   reg [32:1] polynom;
2590 
   integer i;
2591 
 
2592 
   always @ (qi)
2593 
   begin
2594 
        case (length)
2595 
         2: polynom = 32'b11;                               // 0x3
2596 
         3: polynom = 32'b110;                              // 0x6
2597 
         4: polynom = 32'b1100;                             // 0xC
2598 
         5: polynom = 32'b10100;                            // 0x14
2599 
         6: polynom = 32'b110000;                           // 0x30
2600 
         7: polynom = 32'b1100000;                          // 0x60
2601 
         8: polynom = 32'b10111000;                         // 0xb8
2602 
         9: polynom = 32'b100010000;                        // 0x110
2603 
        10: polynom = 32'b1001000000;                       // 0x240
2604 
        11: polynom = 32'b10100000000;                      // 0x500
2605 
        12: polynom = 32'b100000101001;                     // 0x829
2606 
        13: polynom = 32'b1000000001100;                    // 0x100C
2607 
        14: polynom = 32'b10000000010101;                   // 0x2015
2608 
        15: polynom = 32'b110000000000000;                  // 0x6000
2609 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2610 
        17: polynom = 32'b10010000000000000;                // 0x12000
2611 
        18: polynom = 32'b100000010000000000;               // 0x20400
2612 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2613 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2614 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2615 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2616 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2617 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2618 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2619 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2620 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2621 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2622 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2623 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2624 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2625 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2626 
        default: polynom = 32'b0;
2627 
        endcase
2628 
        lfsr_fb = qi[length];
2629 
        for (i=length-1; i>=1; i=i-1) begin
2630 
            if (polynom[i])
2631 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2632 
        end
2633 
    end
2634 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2635 
 
2636 
   always @ (posedge clk or posedge rst)
2637 
     if (rst)
2638 
       qi <= {length{1'b0}};
2639 
     else
2640 
     if (cke)
2641 
       qi <= q_next;
2642 
 
2643 
 
2644 
 
2645 
   always @ (posedge clk or posedge rst)
2646 
     if (rst)
2647 
       zq <= 1'b1;
2648 
     else
2649 
     if (cke)
2650 
       zq <= q_next == {length{1'b0}};
2651 
endmodule
2652 
`endif
2653 40 unneback 
`ifdef CNT_LFSR_CE_ZQ
2654 6 unneback 
//////////////////////////////////////////////////////////////////////
2655 
////                                                              ////
2656 
////  Versatile counter                                           ////
2657 
////                                                              ////
2658 
////  Description                                                 ////
2659 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2660 
////  counter                                                     ////
2661 
////                                                              ////
2662 
////  To Do:                                                      ////
2663 
////   - add LFSR with more taps                                  ////
2664 
////                                                              ////
2665 
////  Author(s):                                                  ////
2666 
////      - Michael Unneback, unneback@opencores.org              ////
2667 
////        ORSoC AB                                              ////
2668 
////                                                              ////
2669 
//////////////////////////////////////////////////////////////////////
2670 
////                                                              ////
2671 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2672 
////                                                              ////
2673 
//// This source file may be used and distributed without         ////
2674 
//// restriction provided that this copyright statement is not    ////
2675 
//// removed from the file and that any derivative work contains  ////
2676 
//// the original copyright notice and the associated disclaimer. ////
2677 
////                                                              ////
2678 
//// This source file is free software; you can redistribute it   ////
2679 
//// and/or modify it under the terms of the GNU Lesser General   ////
2680 
//// Public License as published by the Free Software Foundation; ////
2681 
//// either version 2.1 of the License, or (at your option) any   ////
2682 
//// later version.                                               ////
2683 
////                                                              ////
2684 
//// This source is distributed in the hope that it will be       ////
2685 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2686 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2687 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2688 
//// details.                                                     ////
2689 
////                                                              ////
2690 
//// You should have received a copy of the GNU Lesser General    ////
2691 
//// Public License along with this source; if not, download it   ////
2692 
//// from http://www.opencores.org/lgpl.shtml                     ////
2693 
////                                                              ////
2694 
//////////////////////////////////////////////////////////////////////
2695 
 
2696 
// LFSR counter
2697 
 
2698 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2699 
module `BASE`MODULE (
2700 
`undef MODULE
2701 
 cke, zq, rst, clk);
2702 
 
2703 6 unneback 
   parameter length = 4;
2704 
   input cke;
2705 
   output reg zq;
2706 
   input rst;
2707 
   input clk;
2708 
 
2709 
   parameter clear_value = 0;
2710 
   parameter set_value = 1;
2711 
   parameter wrap_value = 8;
2712 
   parameter level1_value = 15;
2713 
 
2714 
   reg  [length:1] qi;
2715 
   reg lfsr_fb;
2716 
   wire [length:1] q_next;
2717 
   reg [32:1] polynom;
2718 
   integer i;
2719 
 
2720 
   always @ (qi)
2721 
   begin
2722 
        case (length)
2723 
         2: polynom = 32'b11;                               // 0x3
2724 
         3: polynom = 32'b110;                              // 0x6
2725 
         4: polynom = 32'b1100;                             // 0xC
2726 
         5: polynom = 32'b10100;                            // 0x14
2727 
         6: polynom = 32'b110000;                           // 0x30
2728 
         7: polynom = 32'b1100000;                          // 0x60
2729 
         8: polynom = 32'b10111000;                         // 0xb8
2730 
         9: polynom = 32'b100010000;                        // 0x110
2731 
        10: polynom = 32'b1001000000;                       // 0x240
2732 
        11: polynom = 32'b10100000000;                      // 0x500
2733 
        12: polynom = 32'b100000101001;                     // 0x829
2734 
        13: polynom = 32'b1000000001100;                    // 0x100C
2735 
        14: polynom = 32'b10000000010101;                   // 0x2015
2736 
        15: polynom = 32'b110000000000000;                  // 0x6000
2737 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2738 
        17: polynom = 32'b10010000000000000;                // 0x12000
2739 
        18: polynom = 32'b100000010000000000;               // 0x20400
2740 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2741 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2742 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2743 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2744 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2745 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2746 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2747 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2748 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2749 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2750 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2751 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2752 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2753 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2754 
        default: polynom = 32'b0;
2755 
        endcase
2756 
        lfsr_fb = qi[length];
2757 
        for (i=length-1; i>=1; i=i-1) begin
2758 
            if (polynom[i])
2759 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2760 
        end
2761 
    end
2762 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2763 
 
2764 
   always @ (posedge clk or posedge rst)
2765 
     if (rst)
2766 
       qi <= {length{1'b0}};
2767 
     else
2768 
     if (cke)
2769 
       qi <= q_next;
2770 
 
2771 
 
2772 
 
2773 
   always @ (posedge clk or posedge rst)
2774 
     if (rst)
2775 
       zq <= 1'b1;
2776 
     else
2777 
     if (cke)
2778 
       zq <= q_next == {length{1'b0}};
2779 
endmodule
2780 40 unneback 
`endif
2781 
`ifdef CNT_LFSR_CE_Q
2782 6 unneback 
//////////////////////////////////////////////////////////////////////
2783 
////                                                              ////
2784 
////  Versatile counter                                           ////
2785 
////                                                              ////
2786 
////  Description                                                 ////
2787 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2788 
////  counter                                                     ////
2789 
////                                                              ////
2790 
////  To Do:                                                      ////
2791 
////   - add LFSR with more taps                                  ////
2792 
////                                                              ////
2793 
////  Author(s):                                                  ////
2794 
////      - Michael Unneback, unneback@opencores.org              ////
2795 
////        ORSoC AB                                              ////
2796 
////                                                              ////
2797 
//////////////////////////////////////////////////////////////////////
2798 
////                                                              ////
2799 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2800 
////                                                              ////
2801 
//// This source file may be used and distributed without         ////
2802 
//// restriction provided that this copyright statement is not    ////
2803 
//// removed from the file and that any derivative work contains  ////
2804 
//// the original copyright notice and the associated disclaimer. ////
2805 
////                                                              ////
2806 
//// This source file is free software; you can redistribute it   ////
2807 
//// and/or modify it under the terms of the GNU Lesser General   ////
2808 
//// Public License as published by the Free Software Foundation; ////
2809 
//// either version 2.1 of the License, or (at your option) any   ////
2810 
//// later version.                                               ////
2811 
////                                                              ////
2812 
//// This source is distributed in the hope that it will be       ////
2813 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2814 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2815 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2816 
//// details.                                                     ////
2817 
////                                                              ////
2818 
//// You should have received a copy of the GNU Lesser General    ////
2819 
//// Public License along with this source; if not, download it   ////
2820 
//// from http://www.opencores.org/lgpl.shtml                     ////
2821