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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 98

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 98 unneback 
`ifdef ACTEL
14 
    // ACTEL FPGA should not use logic to handle rw collision
15 
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16 
`else
17 
    `define SYN_NO_RW_CHECK
18 
`endif
19 
 
20 40 unneback 
`ifdef ALL
21 
 
22 
`define GBUF
23 
`define SYNC_RST
24 
`define PLL
25 
 
26 
`define MULTS
27 
`define MULTS18X18
28 
`define MULT
29 
`define SHIFT_UNIT_32
30 
`define LOGIC_UNIT
31 
 
32 
`define CNT_SHREG_WRAP
33 
`define CNT_SHREG_CE_WRAP
34 
`define CNT_SHREG_CE_CLEAR
35 
`define CNT_SHREG_CE_CLEAR_WRAP
36 
 
37 
`define MUX_ANDOR
38 
`define MUX2_ANDOR
39 
`define MUX3_ANDOR
40 
`define MUX4_ANDOR
41 
`define MUX5_ANDOR
42 
`define MUX6_ANDOR
43 43 unneback 
`define PARITY
44 40 unneback 
 
45 
`define ROM_INIT
46 
`define RAM
47 
`define RAM_BE
48 
`define DPRAM_1R1W
49 
`define DPRAM_2R1W
50 
`define DPRAM_2R2W
51 75 unneback 
`define DPRAM_BE_2R2W
52 40 unneback 
`define FIFO_1R1W_FILL_LEVEL_SYNC
53 
`define FIFO_2R2W_SYNC_SIMPLEX
54 
`define FIFO_CMP_ASYNC
55 
`define FIFO_1R1W_ASYNC
56 
`define FIFO_2R2W_ASYNC
57 
`define FIFO_2R2W_ASYNC_SIMPLEX
58 48 unneback 
`define REG_FILE
59 40 unneback 
 
60 
`define DFF
61 
`define DFF_ARRAY
62 
`define DFF_CE
63 
`define DFF_CE_CLEAR
64 
`define DF_CE_SET
65 
`define SPR
66 
`define SRP
67 
`define DFF_SR
68 
`define LATCH
69 
`define SHREG
70 
`define SHREG_CE
71 
`define DELAY
72 
`define DELAY_EMPTYFLAG
73 94 unneback 
`define PULSE2TOGGLE
74 
`define TOGGLE2PULSE
75 
`define SYNCHRONIZER
76 
`define CDC
77 40 unneback 
 
78 75 unneback 
`define WB3AVALON_BRIDGE
79 40 unneback 
`define WB3WB3_BRIDGE
80 
`define WB3_ARBITER_TYPE1
81 83 unneback 
`define WB_ADR_INC
82 59 unneback 
`define WB_B3_RAM_BE
83 49 unneback 
`define WB_B4_RAM_BE
84 48 unneback 
`define WB_B4_ROM
85 40 unneback 
`define WB_BOOT_ROM
86 
`define WB_DPRAM
87 97 unneback 
`define WBB3_WBB4_CACHE
88 40 unneback 
 
89 44 unneback 
`define IO_DFF_OE
90 
`define O_DFF
91 
 
92 40 unneback 
`endif
93 
 
94 
`ifdef PLL
95 
`ifndef SYNC_RST
96 
`define SYNC_RST
97 
`endif
98 
`endif
99 
 
100 
`ifdef SYNC_RST
101 
`ifndef GBUF
102 
`define GBUF
103 
`endif
104 
`endif
105 
 
106 92 unneback 
`ifdef WB_B3_DPRAM
107 
`ifndef WB_ADR_INC
108 
`define WB_ADR_INC
109 40 unneback 
`endif
110 92 unneback 
`ifndef DPRAM_BE_2R2W
111 
`define DPRAM_BE_2R2W
112 40 unneback 
`endif
113 
`endif
114 
 
115 62 unneback 
`ifdef WB_B3_RAM_BE
116 83 unneback 
`ifndef WB_ADR_INC
117 
`define WB_ADR_INC
118 62 unneback 
`endif
119 
`ifndef RAM_BE
120 
`define RAM_BE
121 
`endif
122 
`endif
123 
 
124 40 unneback 
`ifdef WB3_ARBITER_TYPE1
125 42 unneback 
`ifndef SPR
126 
`define SPR
127 
`endif
128 40 unneback 
`ifndef MUX_ANDOR
129 
`define MUX_ANDOR
130 
`endif
131 
`endif
132 
 
133 76 unneback 
`ifdef WB3AVALON_BRIDGE
134 
`ifndef WB3WB3_BRIDGE
135 
`define WB3WB3_BRIDGE
136 
`endif
137 
`endif
138 
 
139 40 unneback 
`ifdef WB3WB3_BRIDGE
140 
`ifndef CNT_SHREG_CE_CLEAR
141 
`define CNT_SHREG_CE_CLEAR
142 
`endif
143 
`ifndef DFF
144 
`define DFF
145 
`endif
146 
`ifndef DFF_CE
147 
`define DFF_CE
148 
`endif
149 
`ifndef CNT_SHREG_CE_CLEAR
150 
`define CNT_SHREG_CE_CLEAR
151 
`endif
152 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
153 
`define FIFO_2R2W_ASYNC_SIMPLEX
154 
`endif
155 
`endif
156 
 
157 97 unneback 
 `ifdef WBB3_WBB4_CACHE
158 
 `ifndef RAM
159 
 `define RAM
160 
 `endif
161 
 `ifndef WB_ADR_INC
162 
 `define WB_ADR_INC
163 
 `endif
164 
 `ifndef dpram_be_2r2w
165 
 `define DPRAM_BE_2R2W
166 
 `endif
167 98 unneback 
 `ifndef CDC
168 
 `define CDC
169 97 unneback 
 `endif
170 98 unneback 
 `endif
171 97 unneback 
 
172 40 unneback 
`ifdef MULTS18X18
173 
`ifndef MULTS
174 
`define MULTS
175 
`endif
176 
`endif
177 
 
178 
`ifdef SHIFT_UNIT_32
179 
`ifndef MULTS
180 
`define MULTS
181 
`endif
182 
`endif
183 
 
184 
`ifdef MUX2_ANDOR
185 
`ifndef MUX_ANDOR
186 
`define MUX_ANDOR
187 
`endif
188 
`endif
189 
 
190 
`ifdef MUX3_ANDOR
191 
`ifndef MUX_ANDOR
192 
`define MUX_ANDOR
193 
`endif
194 
`endif
195 
 
196 
`ifdef MUX4_ANDOR
197 
`ifndef MUX_ANDOR
198 
`define MUX_ANDOR
199 
`endif
200 
`endif
201 
 
202 
`ifdef MUX5_ANDOR
203 
`ifndef MUX_ANDOR
204 
`define MUX_ANDOR
205 
`endif
206 
`endif
207 
 
208 
`ifdef MUX6_ANDOR
209 
`ifndef MUX_ANDOR
210 
`define MUX_ANDOR
211 
`endif
212 
`endif
213 
 
214 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
215 
`ifndef CNT_BIN_CE
216 
`define CNT_BIN_CE
217 
`endif
218 
`ifndef DPRAM_1R1W
219 
`define DPRAM_1R1W
220 
`endif
221 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
222 
`define CNT_BIN_CE_REW_Q_ZQ_L1
223 
`endif
224 
`endif
225 
 
226 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
227 
`ifndef CNT_LFSR_CE
228 
`define CNT_LFSR_CE
229 
`endif
230 
`ifndef DPRAM_2R2W
231 
`define DPRAM_2R2W
232 
`endif
233 
`ifndef CNT_BIN_CE_REW_ZQ_L1
234 
`define CNT_BIN_CE_REW_ZQ_L1
235 
`endif
236 
`endif
237 
 
238 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
239 
`ifndef CNT_GRAY_CE_BIN
240 
`define CNT_GRAY_CE_BIN
241 
`endif
242 
`ifndef DPRAM_2R2W
243 
`define DPRAM_2R2W
244 
`endif
245 
`ifndef FIFO_CMP_ASYNC
246 
`define FIFO_CMP_ASYNC
247 
`endif
248 
`endif
249 
 
250 
`ifdef FIFO_2R2W_ASYNC
251 
`ifndef FIFO_1R1W_ASYNC
252 
`define FIFO_1R1W_ASYNC
253 
`endif
254 
`endif
255 
 
256 
`ifdef FIFO_1R1W_ASYNC
257 
`ifndef CNT_GRAY_CE_BIN
258 
`define CNT_GRAY_CE_BIN
259 
`endif
260 
`ifndef DPRAM_1R1W
261 
`define DPRAM_1R1W
262 
`endif
263 
`ifndef FIFO_CMP_ASYNC
264 
`define FIFO_CMP_ASYNC
265 
`endif
266 
`endif
267 
 
268 
`ifdef FIFO_CMP_ASYNC
269 
`ifndef DFF_SR
270 
`define DFF_SR
271 
`endif
272 
`ifndef DFF
273 
`define DFF
274 
`endif
275 
`endif
276 48 unneback 
 
277 
`ifdef REG_FILE
278 
`ifndef DPRAM_1R1W
279 
`define DPRAM_1R1W
280 
`endif
281 
`endif
282 97 unneback 
 
283 98 unneback 
`ifdef CDC
284 
`ifndef PULSE2TOGGLE
285 
`define PULSE2TOGGLE
286 
`endif
287 
`ifndef TOGGLE2PULSE
288 
`define TOGGLE2PULSE
289 
`endif
290 
`ifndef SYNCHRONIZER
291 
`define SYNCHRONIZER
292 
`endif
293 
`endif
294 
 
295 97 unneback 
// size to width
296 
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
297 62 unneback 
//////////////////////////////////////////////////////////////////////
298 6 unneback 
////                                                              ////
299 
////  Versatile library, clock and reset                          ////
300 
////                                                              ////
301 
////  Description                                                 ////
302 
////  Logic related to clock and reset                            ////
303 
////                                                              ////
304 
////                                                              ////
305 
////  To Do:                                                      ////
306 
////   - add more different registers                             ////
307 
////                                                              ////
308 
////  Author(s):                                                  ////
309 
////      - Michael Unneback, unneback@opencores.org              ////
310 
////        ORSoC AB                                              ////
311 
////                                                              ////
312 
//////////////////////////////////////////////////////////////////////
313 
////                                                              ////
314 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
315 
////                                                              ////
316 
//// This source file may be used and distributed without         ////
317 
//// restriction provided that this copyright statement is not    ////
318 
//// removed from the file and that any derivative work contains  ////
319 
//// the original copyright notice and the associated disclaimer. ////
320 
////                                                              ////
321 
//// This source file is free software; you can redistribute it   ////
322 
//// and/or modify it under the terms of the GNU Lesser General   ////
323 
//// Public License as published by the Free Software Foundation; ////
324 
//// either version 2.1 of the License, or (at your option) any   ////
325 
//// later version.                                               ////
326 
////                                                              ////
327 
//// This source is distributed in the hope that it will be       ////
328 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
329 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
330 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
331 
//// details.                                                     ////
332 
////                                                              ////
333 
//// You should have received a copy of the GNU Lesser General    ////
334 
//// Public License along with this source; if not, download it   ////
335 
//// from http://www.opencores.org/lgpl.shtml                     ////
336 
////                                                              ////
337 
//////////////////////////////////////////////////////////////////////
338 
 
339 48 unneback 
`ifdef ACTEL
340 
`ifdef GBUF
341 
`timescale 1 ns/100 ps
342 6 unneback 
// Global buffer
343 
// usage:
344 
// use to enable global buffers for high fan out signals such as clock and reset
345 
// Version: 8.4 8.4.0.33
346 
module gbuf(GL,CLK);
347 
output GL;
348 
input  CLK;
349 
 
350 
    wire GND;
351 
 
352 
    GND GND_1_net(.Y(GND));
353 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
354 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
355 
 
356 
endmodule
357 
`timescale 1 ns/1 ns
358 40 unneback 
`define MODULE gbuf
359 
module `BASE`MODULE ( i, o);
360 
`undef MODULE
361 6 unneback 
input i;
362 
output o;
363 
`ifdef SIM_GBUF
364 
assign o=i;
365 
`else
366 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
367 
`endif
368 
endmodule
369 40 unneback 
`endif
370 33 unneback 
 
371 6 unneback 
`else
372 33 unneback 
 
373 40 unneback 
`ifdef ALTERA
374 
`ifdef GBUF
375 21 unneback 
//altera
376 40 unneback 
`define MODULE gbuf
377 
module `BASE`MODULE ( i, o);
378 
`undef MODULE
379 33 unneback 
input i;
380 
output o;
381 
assign o = i;
382 
endmodule
383 40 unneback 
`endif
384 33 unneback 
 
385 6 unneback 
`else
386 
 
387 40 unneback 
`ifdef GBUF
388 6 unneback 
`timescale 1 ns/100 ps
389 40 unneback 
`define MODULE
390 
module `BASE`MODULE ( i, o);
391 
`undef MODULE
392 6 unneback 
input i;
393 
output o;
394 
assign o = i;
395 
endmodule
396 40 unneback 
`endif
397 6 unneback 
`endif // ALTERA
398 
`endif //ACTEL
399 
 
400 40 unneback 
`ifdef SYNC_RST
401 6 unneback 
// sync reset
402 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
403 6 unneback 
// output active high global reset sync with two DFFs
404 
`timescale 1 ns/100 ps
405 40 unneback 
`define MODULE sync_rst
406 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
407 
`undef MODULE
408 6 unneback 
input rst_n_i, clk;
409 
output rst_o;
410 18 unneback 
reg [1:0] tmp;
411 6 unneback 
always @ (posedge clk or negedge rst_n_i)
412 
if (!rst_n_i)
413 17 unneback 
        tmp <= 2'b11;
414 6 unneback 
else
415 33 unneback 
        tmp <= {1'b0,tmp[1]};
416 40 unneback 
`define MODULE gbuf
417 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
418 
`undef MODULE
419 6 unneback 
endmodule
420 40 unneback 
`endif
421 6 unneback 
 
422 40 unneback 
`ifdef PLL
423 6 unneback 
// vl_pll
424 
`ifdef ACTEL
425 32 unneback 
///////////////////////////////////////////////////////////////////////////////
426 17 unneback 
`timescale 1 ps/1 ps
427 40 unneback 
`define MODULE pll
428 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
429 
`undef MODULE
430 6 unneback 
parameter index = 0;
431 
parameter number_of_clk = 1;
432 17 unneback 
parameter period_time_0 = 20000;
433 
parameter period_time_1 = 20000;
434 
parameter period_time_2 = 20000;
435 
parameter lock_delay = 2000000;
436 6 unneback 
input clk_i, rst_n_i;
437 
output lock;
438 
output reg [0:number_of_clk-1] clk_o;
439 
output [0:number_of_clk-1] rst_o;
440 
 
441 
`ifdef SIM_PLL
442 
 
443 
always
444 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
445 
 
446 
generate if (number_of_clk > 1)
447 
always
448 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
449 
endgenerate
450 
 
451 
generate if (number_of_clk > 2)
452 
always
453 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
454 
endgenerate
455 
 
456 
genvar i;
457 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
458 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
459 
end
460 
endgenerate
461 
 
462 
assign #lock_delay lock = rst_n_i;
463 
 
464 
endmodule
465 
`else
466 
generate if (number_of_clk==1 & index==0) begin
467 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
468 
end
469 
endgenerate // index==0
470 
generate if (number_of_clk==1 & index==1) begin
471 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
472 
end
473 
endgenerate // index==1
474 
generate if (number_of_clk==1 & index==2) begin
475 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
476 
end
477 
endgenerate // index==2
478 
generate if (number_of_clk==1 & index==3) begin
479 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
480 
end
481 
endgenerate // index==0
482 
 
483 
generate if (number_of_clk==2 & index==0) begin
484 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
485 
end
486 
endgenerate // index==0
487 
generate if (number_of_clk==2 & index==1) begin
488 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
489 
end
490 
endgenerate // index==1
491 
generate if (number_of_clk==2 & index==2) begin
492 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
493 
end
494 
endgenerate // index==2
495 
generate if (number_of_clk==2 & index==3) begin
496 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
497 
end
498 
endgenerate // index==0
499 
 
500 
generate if (number_of_clk==3 & index==0) begin
501 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
502 
end
503 
endgenerate // index==0
504 
generate if (number_of_clk==3 & index==1) begin
505 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
506 
end
507 
endgenerate // index==1
508 
generate if (number_of_clk==3 & index==2) begin
509 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
510 
end
511 
endgenerate // index==2
512 
generate if (number_of_clk==3 & index==3) begin
513 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
514 
end
515 
endgenerate // index==0
516 
 
517 
genvar i;
518 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
519 40 unneback 
`define MODULE sync_rst
520 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
521 
`undef MODULE
522 6 unneback 
end
523 
endgenerate
524 
endmodule
525 
`endif
526 32 unneback 
///////////////////////////////////////////////////////////////////////////////
527 6 unneback 
 
528 
`else
529 
 
530 32 unneback 
///////////////////////////////////////////////////////////////////////////////
531 6 unneback 
`ifdef ALTERA
532 
 
533 32 unneback 
`timescale 1 ps/1 ps
534 40 unneback 
`define MODULE pll
535 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
536 
`undef MODULE
537 32 unneback 
parameter index = 0;
538 
parameter number_of_clk = 1;
539 
parameter period_time_0 = 20000;
540 
parameter period_time_1 = 20000;
541 
parameter period_time_2 = 20000;
542 
parameter period_time_3 = 20000;
543 
parameter period_time_4 = 20000;
544 
parameter lock_delay = 2000000;
545 
input clk_i, rst_n_i;
546 
output lock;
547 
output reg [0:number_of_clk-1] clk_o;
548 
output [0:number_of_clk-1] rst_o;
549 
 
550 
`ifdef SIM_PLL
551 
 
552 
always
553 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
554 
 
555 
generate if (number_of_clk > 1)
556 
always
557 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
558 
endgenerate
559 
 
560 
generate if (number_of_clk > 2)
561 
always
562 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
563 
endgenerate
564 
 
565 33 unneback 
generate if (number_of_clk > 3)
566 32 unneback 
always
567 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
568 
endgenerate
569 
 
570 33 unneback 
generate if (number_of_clk > 4)
571 32 unneback 
always
572 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
573 
endgenerate
574 
 
575 
genvar i;
576 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
577 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
578 
end
579 
endgenerate
580 
 
581 33 unneback 
//assign #lock_delay lock = rst_n_i;
582 
assign lock = rst_n_i;
583 32 unneback 
 
584 
endmodule
585 6 unneback 
`else
586 
 
587 33 unneback 
`ifdef VL_PLL0
588 
`ifdef VL_PLL0_CLK1
589 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
590 
`endif
591 
`ifdef VL_PLL0_CLK2
592 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
593 
`endif
594 
`ifdef VL_PLL0_CLK3
595 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
596 
`endif
597 
`ifdef VL_PLL0_CLK4
598 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
599 
`endif
600 
`ifdef VL_PLL0_CLK5
601 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
602 
`endif
603 
`endif
604 32 unneback 
 
605 33 unneback 
`ifdef VL_PLL1
606 
`ifdef VL_PLL1_CLK1
607 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
608 
`endif
609 
`ifdef VL_PLL1_CLK2
610 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
611 
`endif
612 
`ifdef VL_PLL1_CLK3
613 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
614 
`endif
615 
`ifdef VL_PLL1_CLK4
616 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
617 
`endif
618 
`ifdef VL_PLL1_CLK5
619 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
620 
`endif
621 
`endif
622 32 unneback 
 
623 33 unneback 
`ifdef VL_PLL2
624 
`ifdef VL_PLL2_CLK1
625 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
626 
`endif
627 
`ifdef VL_PLL2_CLK2
628 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
629 
`endif
630 
`ifdef VL_PLL2_CLK3
631 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
632 
`endif
633 
`ifdef VL_PLL2_CLK4
634 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
635 
`endif
636 
`ifdef VL_PLL2_CLK5
637 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
638 
`endif
639 
`endif
640 32 unneback 
 
641 33 unneback 
`ifdef VL_PLL3
642 
`ifdef VL_PLL3_CLK1
643 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
644 
`endif
645 
`ifdef VL_PLL3_CLK2
646 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
647 
`endif
648 
`ifdef VL_PLL3_CLK3
649 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
650 
`endif
651 
`ifdef VL_PLL3_CLK4
652 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
653 
`endif
654 
`ifdef VL_PLL3_CLK5
655 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
656 
`endif
657 
`endif
658 32 unneback 
 
659 
genvar i;
660 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
661 40 unneback 
`define MODULE sync_rst
662 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
663 
`undef MODULE
664 32 unneback 
end
665 
endgenerate
666 
endmodule
667 
`endif
668 
///////////////////////////////////////////////////////////////////////////////
669 
 
670 
`else
671 
 
672 6 unneback 
// generic PLL
673 17 unneback 
`timescale 1 ps/1 ps
674 40 unneback 
`define MODULE pll
675 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
676 
`undef MODULE
677 6 unneback 
parameter index = 0;
678 
parameter number_of_clk = 1;
679 17 unneback 
parameter period_time_0 = 20000;
680 
parameter period_time_1 = 20000;
681 
parameter period_time_2 = 20000;
682 6 unneback 
parameter lock_delay = 2000;
683 
input clk_i, rst_n_i;
684 
output lock;
685 
output reg [0:number_of_clk-1] clk_o;
686 
output [0:number_of_clk-1] rst_o;
687 
 
688 
always
689 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
690 
 
691 
generate if (number_of_clk > 1)
692 
always
693 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
694 
endgenerate
695 
 
696 
generate if (number_of_clk > 2)
697 
always
698 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
699 
endgenerate
700 
 
701 
genvar i;
702 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
703 40 unneback 
`define MODULE sync_rst
704 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
705 
`undef MODULE
706 6 unneback 
end
707 
endgenerate
708 
 
709 
assign #lock_delay lock = rst_n_i;
710 
 
711 
endmodule
712 
 
713 
`endif //altera
714 17 unneback 
`endif //actel
715 40 unneback 
`undef MODULE
716 
`endif//////////////////////////////////////////////////////////////////////
717 6 unneback 
////                                                              ////
718 
////  Versatile library, registers                                ////
719 
////                                                              ////
720 
////  Description                                                 ////
721 
////  Different type of registers                                 ////
722 
////                                                              ////
723 
////                                                              ////
724 
////  To Do:                                                      ////
725 
////   - add more different registers                             ////
726 
////                                                              ////
727 
////  Author(s):                                                  ////
728 
////      - Michael Unneback, unneback@opencores.org              ////
729 
////        ORSoC AB                                              ////
730 
////                                                              ////
731 
//////////////////////////////////////////////////////////////////////
732 
////                                                              ////
733 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
734 
////                                                              ////
735 
//// This source file may be used and distributed without         ////
736 
//// restriction provided that this copyright statement is not    ////
737 
//// removed from the file and that any derivative work contains  ////
738 
//// the original copyright notice and the associated disclaimer. ////
739 
////                                                              ////
740 
//// This source file is free software; you can redistribute it   ////
741 
//// and/or modify it under the terms of the GNU Lesser General   ////
742 
//// Public License as published by the Free Software Foundation; ////
743 
//// either version 2.1 of the License, or (at your option) any   ////
744 
//// later version.                                               ////
745 
////                                                              ////
746 
//// This source is distributed in the hope that it will be       ////
747 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
748 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
749 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
750 
//// details.                                                     ////
751 
////                                                              ////
752 
//// You should have received a copy of the GNU Lesser General    ////
753 
//// Public License along with this source; if not, download it   ////
754 
//// from http://www.opencores.org/lgpl.shtml                     ////
755 
////                                                              ////
756 
//////////////////////////////////////////////////////////////////////
757 
 
758 40 unneback 
`ifdef DFF
759 
`define MODULE dff
760 
module `BASE`MODULE ( d, q, clk, rst);
761 
`undef MODULE
762 6 unneback 
        parameter width = 1;
763 
        parameter reset_value = 0;
764 
 
765 
        input [width-1:0] d;
766 
        input clk, rst;
767 
        output reg [width-1:0] q;
768 
 
769 
        always @ (posedge clk or posedge rst)
770 
        if (rst)
771 
                q <= reset_value;
772 
        else
773 
                q <= d;
774 
 
775 
endmodule
776 40 unneback 
`endif
777 6 unneback 
 
778 40 unneback 
`ifdef DFF_ARRAY
779 
`define MODULE dff_array
780 
module `BASE`MODULE ( d, q, clk, rst);
781 
`undef MODULE
782 6 unneback 
 
783 
        parameter width = 1;
784 
        parameter depth = 2;
785 
        parameter reset_value = 1'b0;
786 
 
787 
        input [width-1:0] d;
788 
        input clk, rst;
789 
        output [width-1:0] q;
790 
        reg  [0:depth-1] q_tmp [width-1:0];
791 
        integer i;
792 
        always @ (posedge clk or posedge rst)
793 
        if (rst) begin
794 
            for (i=0;i<depth;i=i+1)
795 
                q_tmp[i] <= {width{reset_value}};
796 
        end else begin
797 
            q_tmp[0] <= d;
798 
            for (i=1;i<depth;i=i+1)
799 
                q_tmp[i] <= q_tmp[i-1];
800 
        end
801 
 
802 
    assign q = q_tmp[depth-1];
803 
 
804 
endmodule
805 40 unneback 
`endif
806 6 unneback 
 
807 40 unneback 
`ifdef DFF_CE
808 
`define MODULE dff_ce
809 
module `BASE`MODULE ( d, ce, q, clk, rst);
810 
`undef MODULE
811 6 unneback 
 
812 
        parameter width = 1;
813 
        parameter reset_value = 0;
814 
 
815 
        input [width-1:0] d;
816 
        input ce, clk, rst;
817 
        output reg [width-1:0] q;
818 
 
819 
        always @ (posedge clk or posedge rst)
820 
        if (rst)
821 
                q <= reset_value;
822 
        else
823 
                if (ce)
824 
                        q <= d;
825 
 
826 
endmodule
827 40 unneback 
`endif
828 6 unneback 
 
829 40 unneback 
`ifdef DFF_CE_CLEAR
830 
`define MODULE dff_ce_clear
831 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
832 
`undef MODULE
833 8 unneback 
 
834 
        parameter width = 1;
835 
        parameter reset_value = 0;
836 
 
837 
        input [width-1:0] d;
838 10 unneback 
        input ce, clear, clk, rst;
839 8 unneback 
        output reg [width-1:0] q;
840 
 
841 
        always @ (posedge clk or posedge rst)
842 
        if (rst)
843 
            q <= reset_value;
844 
        else
845 
            if (ce)
846 
                if (clear)
847 
                    q <= {width{1'b0}};
848 
                else
849 
                    q <= d;
850 
 
851 
endmodule
852 40 unneback 
`endif
853 8 unneback 
 
854 40 unneback 
`ifdef DF_CE_SET
855 
`define MODULE dff_ce_set
856 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
857 
`undef MODULE
858 24 unneback 
 
859 
        parameter width = 1;
860 
        parameter reset_value = 0;
861 
 
862 
        input [width-1:0] d;
863 
        input ce, set, clk, rst;
864 
        output reg [width-1:0] q;
865 
 
866 
        always @ (posedge clk or posedge rst)
867 
        if (rst)
868 
            q <= reset_value;
869 
        else
870 
            if (ce)
871 
                if (set)
872 
                    q <= {width{1'b1}};
873 
                else
874 
                    q <= d;
875 
 
876 
endmodule
877 40 unneback 
`endif
878 24 unneback 
 
879 40 unneback 
`ifdef SPR
880 
`define MODULE spr
881 
module `BASE`MODULE ( sp, r, q, clk, rst);
882 
`undef MODULE
883 
 
884 64 unneback 
        //parameter width = 1;
885 
        parameter reset_value = 1'b0;
886 29 unneback 
 
887 
        input sp, r;
888 
        output reg q;
889 
        input clk, rst;
890 
 
891 
        always @ (posedge clk or posedge rst)
892 
        if (rst)
893 
            q <= reset_value;
894 
        else
895 
            if (sp)
896 
                q <= 1'b1;
897 
            else if (r)
898 
                q <= 1'b0;
899 
 
900 
endmodule
901 40 unneback 
`endif
902 29 unneback 
 
903 40 unneback 
`ifdef SRP
904 
`define MODULE srp
905 
module `BASE`MODULE ( s, rp, q, clk, rst);
906 
`undef MODULE
907 
 
908 29 unneback 
        parameter width = 1;
909 
        parameter reset_value = 0;
910 
 
911 
        input s, rp;
912 
        output reg q;
913 
        input clk, rst;
914 
 
915 
        always @ (posedge clk or posedge rst)
916 
        if (rst)
917 
            q <= reset_value;
918 
        else
919 
            if (rp)
920 
                q <= 1'b0;
921 
            else if (s)
922 
                q <= 1'b1;
923 
 
924 
endmodule
925 40 unneback 
`endif
926 29 unneback 
 
927 40 unneback 
`ifdef ALTERA
928 29 unneback 
 
929 40 unneback 
`ifdef DFF_SR
930 6 unneback 
// megafunction wizard: %LPM_FF%
931 
// GENERATION: STANDARD
932 
// VERSION: WM1.0
933 
// MODULE: lpm_ff
934 
 
935 
// ============================================================
936 
// File Name: dff_sr.v
937 
// Megafunction Name(s):
938 
//                      lpm_ff
939 
//
940 
// Simulation Library Files(s):
941 
//                      lpm
942 
// ============================================================
943 
// ************************************************************
944 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
945 
//
946 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
947 
// ************************************************************
948 
 
949 
 
950 
//Copyright (C) 1991-2010 Altera Corporation
951 
//Your use of Altera Corporation's design tools, logic functions
952 
//and other software and tools, and its AMPP partner logic
953 
//functions, and any output files from any of the foregoing
954 
//(including device programming or simulation files), and any
955 
//associated documentation or information are expressly subject
956 
//to the terms and conditions of the Altera Program License
957 
//Subscription Agreement, Altera MegaCore Function License
958 
//Agreement, or other applicable license agreement, including,
959 
//without limitation, that your use is for the sole purpose of
960 
//programming logic devices manufactured by Altera and sold by
961 
//Altera or its authorized distributors.  Please refer to the
962 
//applicable agreement for further details.
963 
 
964 
 
965 
// synopsys translate_off
966 
`timescale 1 ps / 1 ps
967 
// synopsys translate_on
968 40 unneback 
`define MODULE dff_sr
969 
module `BASE`MODULE (
970 
`undef MODULE
971 
 
972 6 unneback 
        aclr,
973 
        aset,
974 
        clock,
975 
        data,
976 
        q);
977 
 
978 
        input     aclr;
979 
        input     aset;
980 
        input     clock;
981 
        input     data;
982 
        output    q;
983 
 
984 
        wire [0:0] sub_wire0;
985 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
986 
        wire  q = sub_wire1;
987 
        wire  sub_wire2 = data;
988 
        wire  sub_wire3 = sub_wire2;
989 
 
990 
        lpm_ff  lpm_ff_component (
991 
                                .aclr (aclr),
992 
                                .clock (clock),
993 
                                .data (sub_wire3),
994 
                                .aset (aset),
995 
                                .q (sub_wire0)
996 
                                // synopsys translate_off
997 
                                ,
998 
                                .aload (),
999 
                                .enable (),
1000 
                                .sclr (),
1001 
                                .sload (),
1002 
                                .sset ()
1003 
                                // synopsys translate_on
1004 
                                );
1005 
        defparam
1006 
                lpm_ff_component.lpm_fftype = "DFF",
1007 
                lpm_ff_component.lpm_type = "LPM_FF",
1008 
                lpm_ff_component.lpm_width = 1;
1009 
 
1010 
 
1011 
endmodule
1012 
 
1013 
// ============================================================
1014 
// CNX file retrieval info
1015 
// ============================================================
1016 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1017 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1018 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1019 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1020 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1021 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1022 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1023 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1024 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1025 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1026 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1027 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1028 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1029 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1030 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1031 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1032 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1033 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1034 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1035 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1036 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1037 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1038 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1039 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1040 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1041 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1042 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1043 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1044 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1045 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1046 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1047 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1048 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1049 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1050 
// Retrieval info: LIB_FILE: lpm
1051 40 unneback 
`endif
1052 6 unneback 
 
1053 
`else
1054 
 
1055 40 unneback 
`ifdef DFF_SR
1056 
`define MODULE dff_sr
1057 
module `BASE`MODULE ( aclr, aset, clock, data, q);
1058 
`undef MODULE
1059 6 unneback 
 
1060 
    input         aclr;
1061 
    input         aset;
1062 
    input         clock;
1063 
    input         data;
1064 
    output reg    q;
1065 
 
1066 
   always @ (posedge clock or posedge aclr or posedge aset)
1067 
     if (aclr)
1068 
       q <= 1'b0;
1069 
     else if (aset)
1070 
       q <= 1'b1;
1071 
     else
1072 
       q <= data;
1073 
 
1074 
endmodule
1075 40 unneback 
`endif
1076 6 unneback 
 
1077 
`endif
1078 
 
1079 
// LATCH
1080 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1081 
`ifdef ALTERA
1082 40 unneback 
 
1083 
`ifdef LATCH
1084 
`define MODULE latch
1085 
module `BASE`MODULE ( d, le, q, clk);
1086 
`undef MODULE
1087 6 unneback 
input d, le;
1088 
output q;
1089 
input clk;
1090 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1091 
endmodule
1092 40 unneback 
`endif
1093 
 
1094 6 unneback 
`else
1095 40 unneback 
 
1096 
`ifdef LATCH
1097 
`define MODULE latch
1098 
module `BASE`MODULE ( d, le, q, clk);
1099 
`undef MODULE
1100 6 unneback 
input d, le;
1101 48 unneback 
input clk;
1102 
always @ (le or d)
1103 60 unneback 
if (le)
1104 48 unneback 
    d <= q;
1105 6 unneback 
endmodule
1106 15 unneback 
`endif
1107 
 
1108 40 unneback 
`endif
1109 
 
1110 
`ifdef SHREG
1111 
`define MODULE shreg
1112 
module `BASE`MODULE ( d, q, clk, rst);
1113 
`undef MODULE
1114 
 
1115 17 unneback 
parameter depth = 10;
1116 
input d;
1117 
output q;
1118 
input clk, rst;
1119 
 
1120 
reg [1:depth] dffs;
1121 
 
1122 
always @ (posedge clk or posedge rst)
1123 
if (rst)
1124 
    dffs <= {depth{1'b0}};
1125 
else
1126 
    dffs <= {d,dffs[1:depth-1]};
1127 
assign q = dffs[depth];
1128 
endmodule
1129 40 unneback 
`endif
1130 17 unneback 
 
1131 40 unneback 
`ifdef SHREG_CE
1132 
`define MODULE shreg_ce
1133 
module `BASE`MODULE ( d, ce, q, clk, rst);
1134 
`undef MODULE
1135 17 unneback 
parameter depth = 10;
1136 
input d, ce;
1137 
output q;
1138 
input clk, rst;
1139 
 
1140 
reg [1:depth] dffs;
1141 
 
1142 
always @ (posedge clk or posedge rst)
1143 
if (rst)
1144 
    dffs <= {depth{1'b0}};
1145 
else
1146 
    if (ce)
1147 
        dffs <= {d,dffs[1:depth-1]};
1148 
assign q = dffs[depth];
1149 
endmodule
1150 40 unneback 
`endif
1151 17 unneback 
 
1152 40 unneback 
`ifdef DELAY
1153 
`define MODULE delay
1154 
module `BASE`MODULE ( d, q, clk, rst);
1155 
`undef MODULE
1156 15 unneback 
parameter depth = 10;
1157 
input d;
1158 
output q;
1159 
input clk, rst;
1160 
 
1161 
reg [1:depth] dffs;
1162 
 
1163 
always @ (posedge clk or posedge rst)
1164 
if (rst)
1165 
    dffs <= {depth{1'b0}};
1166 
else
1167 
    dffs <= {d,dffs[1:depth-1]};
1168 
assign q = dffs[depth];
1169 17 unneback 
endmodule
1170 40 unneback 
`endif
1171 17 unneback 
 
1172 40 unneback 
`ifdef DELAY_EMPTYFLAG
1173 
`define MODULE delay_emptyflag
1174 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1175 40 unneback 
`undef MODULE
1176 17 unneback 
parameter depth = 10;
1177 
input d;
1178 
output q, emptyflag;
1179 
input clk, rst;
1180 
 
1181 
reg [1:depth] dffs;
1182 
 
1183 
always @ (posedge clk or posedge rst)
1184 
if (rst)
1185 
    dffs <= {depth{1'b0}};
1186 
else
1187 
    dffs <= {d,dffs[1:depth-1]};
1188 
assign q = dffs[depth];
1189 
assign emptyflag = !(|dffs);
1190 
endmodule
1191 40 unneback 
`endif
1192 75 unneback 
 
1193 94 unneback 
`ifdef PULSE2TOGGLE
1194 98 unneback 
`define MODULE pulse2toggle
1195 
module `BASE`MODULE ( pl, q, clk, rst);
1196 75 unneback 
`undef MODULE
1197 94 unneback 
input pl;
1198 98 unneback 
output reg q;
1199 94 unneback 
input clk, rst;
1200 
always @ (posedge clk or posedge rst)
1201 75 unneback 
if (rst)
1202 94 unneback 
    q <= 1'b0;
1203 75 unneback 
else
1204 94 unneback 
    q <= pl ^ q;
1205 
endmodule
1206 
`endif
1207 75 unneback 
 
1208 94 unneback 
`ifdef TOGGLE2PULSE
1209 98 unneback 
`define MODULE toggle2pulse
1210 94 unneback 
module `BASE`MODULE (d, pl, clk, rst);
1211 97 unneback 
`undef MODULE
1212 94 unneback 
input d;
1213 
output pl;
1214 
input clk, rst;
1215 
reg dff;
1216 
always @ (posedge clk or posedge rst)
1217 
if (rst)
1218 
    dff <= 1'b0;
1219 75 unneback 
else
1220 94 unneback 
    dff <= d;
1221 98 unneback 
assign pl = d ^ dff;
1222 94 unneback 
endmodule
1223 
`endif
1224 75 unneback 
 
1225 94 unneback 
`ifdef SYNCHRONIZER
1226 
`define MODULE synchronizer
1227 
module `BASE`MODULE (d, q, clk, rst);
1228 
`undef MODULE
1229 
input d;
1230 
output reg q;
1231 
output clk, rst;
1232 
reg dff;
1233 
always @ (posedge clk or posedge rst)
1234 
if (rst)
1235 
    {dff,q} <= 2'b00;
1236 75 unneback 
else
1237 94 unneback 
    {dff,q} <= {d,dff};
1238 
endmodule
1239 
`endif
1240 75 unneback 
 
1241 94 unneback 
`ifdef CDC
1242 
`define MODULE cdc
1243 97 unneback 
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1244 94 unneback 
`undef MODULE
1245 
input start_pl;
1246 
output take_it_pl;
1247 
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1248 
output got_it_pl;
1249 
input clk_src, rst_src;
1250 
input clk_dst, rst_dst;
1251 
wire take_it_tg, take_it_tg_sync;
1252 
wire got_it_tg, got_it_tg_sync;
1253 
// src -> dst
1254 
`define MODULE pulse2toggle
1255 
`BASE`MODULE p2t0 (
1256 
`undef MODULE
1257 
    .pl(start_pl),
1258 
    .q(take_it_tg),
1259 
    .clk(clk_src),
1260 
    .rst(rst_src));
1261 75 unneback 
 
1262 94 unneback 
`define MODULE synchronizer
1263 
`BASE`MODULE sync0 (
1264 
`undef MODULE
1265 
    .d(take_it_tg),
1266 
    .q(take_it_tg_sync),
1267 
    .clk(clk_dst),
1268 
    .rst(rst_dst));
1269 
 
1270 
`define MODULE toggle2pulse
1271 
`BASE`MODULE t2p0 (
1272 
`undef MODULE
1273 
    .d(take_it_sync),
1274 
    .pl(take_it_pl),
1275 
    .clk(clk_dst),
1276 
    .rst(rst_dst));
1277 
 
1278 
// dst -> src
1279 
`define MODULE pulse2toggle
1280 98 unneback 
`BASE`MODULE p2t1 (
1281 94 unneback 
`undef MODULE
1282 
    .pl(take_it_grant_pl),
1283 
    .q(got_it_tg),
1284 
    .clk(clk_dst),
1285 
    .rst(rst_dst));
1286 
 
1287 
`define MODULE synchronizer
1288 
`BASE`MODULE sync1 (
1289 
`undef MODULE
1290 
    .d(got_it_tg),
1291 
    .q(got_it_tg_sync),
1292 
    .clk(clk_src),
1293 
    .rst(rst_src));
1294 
 
1295 
`define MODULE toggle2pulse
1296 
`BASE`MODULE t2p1 (
1297 
`undef MODULE
1298 
    .d(take_it_grant_tg_sync),
1299 
    .pl(got_it_pl),
1300 
    .clk(clk_src),
1301 
    .rst(rst_src));
1302 
 
1303 75 unneback 
endmodule
1304 
`endif
1305 17 unneback 
//////////////////////////////////////////////////////////////////////
1306 6 unneback 
////                                                              ////
1307 18 unneback 
////  Logic functions                                             ////
1308 
////                                                              ////
1309 
////  Description                                                 ////
1310 
////  Logic functions such as multiplexers                        ////
1311 
////                                                              ////
1312 
////                                                              ////
1313 
////  To Do:                                                      ////
1314 
////   -                                                          ////
1315 
////                                                              ////
1316 
////  Author(s):                                                  ////
1317 
////      - Michael Unneback, unneback@opencores.org              ////
1318 
////        ORSoC AB                                              ////
1319 
////                                                              ////
1320 
//////////////////////////////////////////////////////////////////////
1321 
////                                                              ////
1322 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1323 
////                                                              ////
1324 
//// This source file may be used and distributed without         ////
1325 
//// restriction provided that this copyright statement is not    ////
1326 
//// removed from the file and that any derivative work contains  ////
1327 
//// the original copyright notice and the associated disclaimer. ////
1328 
////                                                              ////
1329 
//// This source file is free software; you can redistribute it   ////
1330 
//// and/or modify it under the terms of the GNU Lesser General   ////
1331 
//// Public License as published by the Free Software Foundation; ////
1332 
//// either version 2.1 of the License, or (at your option) any   ////
1333 
//// later version.                                               ////
1334 
////                                                              ////
1335 
//// This source is distributed in the hope that it will be       ////
1336 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1337 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1338 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1339 
//// details.                                                     ////
1340 
////                                                              ////
1341 
//// You should have received a copy of the GNU Lesser General    ////
1342 
//// Public License along with this source; if not, download it   ////
1343 
//// from http://www.opencores.org/lgpl.shtml                     ////
1344 
////                                                              ////
1345 
//////////////////////////////////////////////////////////////////////
1346 40 unneback 
`ifdef MUX_ANDOR
1347 
`define MODULE mux_andor
1348 
module `BASE`MODULE ( a, sel, dout);
1349 
`undef MODULE
1350 36 unneback 
 
1351 
parameter width = 32;
1352 
parameter nr_of_ports = 4;
1353 
 
1354 
input [nr_of_ports*width-1:0] a;
1355 
input [nr_of_ports-1:0] sel;
1356 
output reg [width-1:0] dout;
1357 
 
1358 38 unneback 
integer i,j;
1359 
 
1360 36 unneback 
always @ (a, sel)
1361 
begin
1362 
    dout = a[width-1:0] & {width{sel[0]}};
1363 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1364 
        for (j=0;j<width;j=j+1)
1365 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1366 36 unneback 
end
1367 
 
1368 
endmodule
1369 40 unneback 
`endif
1370 36 unneback 
 
1371 40 unneback 
`ifdef MUX2_ANDOR
1372 
`define MODULE mux2_andor
1373 
module `BASE`MODULE ( a1, a0, sel, dout);
1374 
`undef MODULE
1375 18 unneback 
 
1376 34 unneback 
parameter width = 32;
1377 35 unneback 
localparam nr_of_ports = 2;
1378 34 unneback 
input [width-1:0] a1, a0;
1379 
input [nr_of_ports-1:0] sel;
1380 
output [width-1:0] dout;
1381 
 
1382 40 unneback 
`define MODULE mux_andor
1383 
`BASE`MODULE
1384 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1385 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1386 40 unneback 
`undef MODULE
1387 
 
1388 34 unneback 
endmodule
1389 40 unneback 
`endif
1390 34 unneback 
 
1391 40 unneback 
`ifdef MUX3_ANDOR
1392 
`define MODULE mux3_andor
1393 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1394 
`undef MODULE
1395 34 unneback 
 
1396 
parameter width = 32;
1397 35 unneback 
localparam nr_of_ports = 3;
1398 34 unneback 
input [width-1:0] a2, a1, a0;
1399 
input [nr_of_ports-1:0] sel;
1400 
output [width-1:0] dout;
1401 
 
1402 40 unneback 
`define MODULE mux_andor
1403 
`BASE`MODULE
1404 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1405 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1406 40 unneback 
`undef MODULE
1407 34 unneback 
endmodule
1408 40 unneback 
`endif
1409 34 unneback 
 
1410 40 unneback 
`ifdef MUX4_ANDOR
1411 
`define MODULE mux4_andor
1412 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1413 
`undef MODULE
1414 18 unneback 
 
1415 
parameter width = 32;
1416 35 unneback 
localparam nr_of_ports = 4;
1417 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1418 
input [nr_of_ports-1:0] sel;
1419 22 unneback 
output [width-1:0] dout;
1420 18 unneback 
 
1421 40 unneback 
`define MODULE mux_andor
1422 
`BASE`MODULE
1423 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1424 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1425 40 unneback 
`undef MODULE
1426 18 unneback 
 
1427 
endmodule
1428 40 unneback 
`endif
1429 18 unneback 
 
1430 40 unneback 
`ifdef MUX5_ANDOR
1431 
`define MODULE mux5_andor
1432 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1433 
`undef MODULE
1434 18 unneback 
 
1435 
parameter width = 32;
1436 35 unneback 
localparam nr_of_ports = 5;
1437 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1438 
input [nr_of_ports-1:0] sel;
1439 22 unneback 
output [width-1:0] dout;
1440 18 unneback 
 
1441 40 unneback 
`define MODULE mux_andor
1442 
`BASE`MODULE
1443 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1444 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1445 40 unneback 
`undef MODULE
1446 18 unneback 
 
1447 
endmodule
1448 40 unneback 
`endif
1449 18 unneback 
 
1450 40 unneback 
`ifdef MUX6_ANDOR
1451 
`define MODULE mux6_andor
1452 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1453 
`undef MODULE
1454 18 unneback 
 
1455 
parameter width = 32;
1456 35 unneback 
localparam nr_of_ports = 6;
1457 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1458 
input [nr_of_ports-1:0] sel;
1459 22 unneback 
output [width-1:0] dout;
1460 18 unneback 
 
1461 40 unneback 
`define MODULE mux_andor
1462 
`BASE`MODULE
1463 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1464 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1465 40 unneback 
`undef MODULE
1466 18 unneback 
 
1467 
endmodule
1468 40 unneback 
`endif
1469 43 unneback 
 
1470 
`ifdef PARITY
1471 
 
1472 
`define MODULE parity_generate
1473 
module `BASE`MODULE (data, parity);
1474 
`undef MODULE
1475 
parameter word_size = 32;
1476 
parameter chunk_size = 8;
1477 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1478 
input [word_size-1:0] data;
1479 
output reg [word_size/chunk_size-1:0] parity;
1480 
integer i,j;
1481 
always @ (data)
1482 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1483 
    parity[i] = parity_type;
1484 
    for (j=0;j<chunk_size;j=j+1) begin
1485 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1486 43 unneback 
    end
1487 
end
1488 
endmodule
1489 
 
1490 
`define MODULE parity_check
1491 
module `BASE`MODULE( data, parity, parity_error);
1492 
`undef MODULE
1493 
parameter word_size = 32;
1494 
parameter chunk_size = 8;
1495 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1496 
input [word_size-1:0] data;
1497 
input [word_size/chunk_size-1:0] parity;
1498 
output parity_error;
1499 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1500 43 unneback 
integer i,j;
1501 
always @ (data or parity)
1502 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1503 
    error_flag[i] = parity[i] ^ parity_type;
1504 
    for (j=0;j<chunk_size;j=j+1) begin
1505 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1506 43 unneback 
    end
1507 
end
1508 
assign parity_error = |error_flag;
1509 
endmodule
1510 
 
1511 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1512 
////                                                              ////
1513 
////  IO functions                                                ////
1514 
////                                                              ////
1515 
////  Description                                                 ////
1516 
////  IO functions such as IOB flip-flops                         ////
1517 
////                                                              ////
1518 
////                                                              ////
1519 
////  To Do:                                                      ////
1520 
////   -                                                          ////
1521 
////                                                              ////
1522 
////  Author(s):                                                  ////
1523 
////      - Michael Unneback, unneback@opencores.org              ////
1524 
////        ORSoC AB                                              ////
1525 
////                                                              ////
1526 18 unneback 
//////////////////////////////////////////////////////////////////////
1527 
////                                                              ////
1528 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1529 
////                                                              ////
1530 
//// This source file may be used and distributed without         ////
1531 
//// restriction provided that this copyright statement is not    ////
1532 
//// removed from the file and that any derivative work contains  ////
1533 
//// the original copyright notice and the associated disclaimer. ////
1534 
////                                                              ////
1535 
//// This source file is free software; you can redistribute it   ////
1536 
//// and/or modify it under the terms of the GNU Lesser General   ////
1537 
//// Public License as published by the Free Software Foundation; ////
1538 
//// either version 2.1 of the License, or (at your option) any   ////
1539 
//// later version.                                               ////
1540 
////                                                              ////
1541 
//// This source is distributed in the hope that it will be       ////
1542 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1543 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1544 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1545 
//// details.                                                     ////
1546 
////                                                              ////
1547 
//// You should have received a copy of the GNU Lesser General    ////
1548 
//// Public License along with this source; if not, download it   ////
1549 
//// from http://www.opencores.org/lgpl.shtml                     ////
1550 
////                                                              ////
1551 
//////////////////////////////////////////////////////////////////////
1552 45 unneback 
`timescale 1ns/1ns
1553 44 unneback 
`ifdef O_DFF
1554 
`define MODULE o_dff
1555 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1556 
`undef MODULE
1557 
parameter width = 1;
1558 45 unneback 
parameter reset_value = {width{1'b0}};
1559 
input  [width-1:0]  d_i;
1560 44 unneback 
output [width-1:0] o_pad;
1561 
input clk, rst;
1562 
wire [width-1:0] d_i_int `SYN_KEEP;
1563 45 unneback 
reg  [width-1:0] o_pad_int;
1564 44 unneback 
assign d_i_int = d_i;
1565 
genvar i;
1566 45 unneback 
generate
1567 44 unneback 
for (i=0;i<width;i=i+1) begin
1568 
    always @ (posedge clk or posedge rst)
1569 
    if (rst)
1570 45 unneback 
        o_pad_int[i] <= reset_value[i];
1571 44 unneback 
    else
1572 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1573 
    assign #1 o_pad[i] = o_pad_int[i];
1574 44 unneback 
end
1575 
endgenerate
1576 
endmodule
1577 
`endif
1578 
 
1579 45 unneback 
`timescale 1ns/1ns
1580 44 unneback 
`ifdef IO_DFF_OE
1581 
`define MODULE io_dff_oe
1582 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1583 
`undef MODULE
1584 
parameter width = 1;
1585 
input  [width-1:0] d_o;
1586 
output reg [width-1:0] d_i;
1587 
input oe;
1588 
inout [width-1:0] io_pad;
1589 
input clk, rst;
1590 
wire [width-1:0] oe_d `SYN_KEEP;
1591 
reg [width-1:0] oe_q;
1592 
reg [width-1:0] d_o_q;
1593 
assign oe_d = {width{oe}};
1594 
genvar i;
1595 
generate
1596 
for (i=0;i<width;i=i+1) begin
1597 
    always @ (posedge clk or posedge rst)
1598 
    if (rst)
1599 
        oe_q[i] <= 1'b0;
1600 
    else
1601 
        oe_q[i] <= oe_d[i];
1602 
    always @ (posedge clk or posedge rst)
1603 
    if (rst)
1604 
        d_o_q[i] <= 1'b0;
1605 
    else
1606 
        d_o_q[i] <= d_o[i];
1607 
    always @ (posedge clk or posedge rst)
1608 
    if (rst)
1609 
        d_i[i] <= 1'b0;
1610 
    else
1611 
        d_i[i] <= io_pad[i];
1612 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1613 44 unneback 
end
1614 
endgenerate
1615 
endmodule
1616 
`endif
1617 
`ifdef CNT_BIN
1618 
//////////////////////////////////////////////////////////////////////
1619 
////                                                              ////
1620 6 unneback 
////  Versatile counter                                           ////
1621 
////                                                              ////
1622 
////  Description                                                 ////
1623 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1624 
////  counter                                                     ////
1625 
////                                                              ////
1626 
////  To Do:                                                      ////
1627 
////   - add LFSR with more taps                                  ////
1628 
////                                                              ////
1629 
////  Author(s):                                                  ////
1630 
////      - Michael Unneback, unneback@opencores.org              ////
1631 
////        ORSoC AB                                              ////
1632 
////                                                              ////
1633 
//////////////////////////////////////////////////////////////////////
1634 
////                                                              ////
1635 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1636 
////                                                              ////
1637 
//// This source file may be used and distributed without         ////
1638 
//// restriction provided that this copyright statement is not    ////
1639 
//// removed from the file and that any derivative work contains  ////
1640 
//// the original copyright notice and the associated disclaimer. ////
1641 
////                                                              ////
1642 
//// This source file is free software; you can redistribute it   ////
1643 
//// and/or modify it under the terms of the GNU Lesser General   ////
1644 
//// Public License as published by the Free Software Foundation; ////
1645 
//// either version 2.1 of the License, or (at your option) any   ////
1646 
//// later version.                                               ////
1647 
////                                                              ////
1648 
//// This source is distributed in the hope that it will be       ////
1649 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1650 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1651 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1652 
//// details.                                                     ////
1653 
////                                                              ////
1654 
//// You should have received a copy of the GNU Lesser General    ////
1655 
//// Public License along with this source; if not, download it   ////
1656 
//// from http://www.opencores.org/lgpl.shtml                     ////
1657 
////                                                              ////
1658 
//////////////////////////////////////////////////////////////////////
1659 
 
1660 
// binary counter
1661 22 unneback 
 
1662 40 unneback 
`define MODULE cnt_bin
1663 
module `BASE`MODULE (
1664 
`undef MODULE
1665 
 q, rst, clk);
1666 
 
1667 22 unneback 
   parameter length = 4;
1668 
   output [length:1] q;
1669 
   input rst;
1670 
   input clk;
1671 
 
1672 
   parameter clear_value = 0;
1673 
   parameter set_value = 1;
1674 
   parameter wrap_value = 0;
1675 
   parameter level1_value = 15;
1676 
 
1677 
   reg  [length:1] qi;
1678 
   wire [length:1] q_next;
1679 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1680 
 
1681 
   always @ (posedge clk or posedge rst)
1682 
     if (rst)
1683 
       qi <= {length{1'b0}};
1684 
     else
1685 
       qi <= q_next;
1686 
 
1687 
   assign q = qi;
1688 
 
1689 
endmodule
1690 40 unneback 
`endif
1691 
`ifdef CNT_BIN_CLEAR
1692 22 unneback 
//////////////////////////////////////////////////////////////////////
1693 
////                                                              ////
1694 
////  Versatile counter                                           ////
1695 
////                                                              ////
1696 
////  Description                                                 ////
1697 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1698 
////  counter                                                     ////
1699 
////                                                              ////
1700 
////  To Do:                                                      ////
1701 
////   - add LFSR with more taps                                  ////
1702 
////                                                              ////
1703 
////  Author(s):                                                  ////
1704 
////      - Michael Unneback, unneback@opencores.org              ////
1705 
////        ORSoC AB                                              ////
1706 
////                                                              ////
1707 
//////////////////////////////////////////////////////////////////////
1708 
////                                                              ////
1709 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1710 
////                                                              ////
1711 
//// This source file may be used and distributed without         ////
1712 
//// restriction provided that this copyright statement is not    ////
1713 
//// removed from the file and that any derivative work contains  ////
1714 
//// the original copyright notice and the associated disclaimer. ////
1715 
////                                                              ////
1716 
//// This source file is free software; you can redistribute it   ////
1717 
//// and/or modify it under the terms of the GNU Lesser General   ////
1718 
//// Public License as published by the Free Software Foundation; ////
1719 
//// either version 2.1 of the License, or (at your option) any   ////
1720 
//// later version.                                               ////
1721 
////                                                              ////
1722 
//// This source is distributed in the hope that it will be       ////
1723 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1724 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1725 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1726 
//// details.                                                     ////
1727 
////                                                              ////
1728 
//// You should have received a copy of the GNU Lesser General    ////
1729 
//// Public License along with this source; if not, download it   ////
1730 
//// from http://www.opencores.org/lgpl.shtml                     ////
1731 
////                                                              ////
1732 
//////////////////////////////////////////////////////////////////////
1733 
 
1734 
// binary counter
1735 
 
1736 40 unneback 
`define MODULE cnt_bin_clear
1737 
module `BASE`MODULE (
1738 
`undef MODULE
1739 
 clear, q, rst, clk);
1740 
 
1741 22 unneback 
   parameter length = 4;
1742 
   input clear;
1743 
   output [length:1] q;
1744 
   input rst;
1745 
   input clk;
1746 
 
1747 
   parameter clear_value = 0;
1748 
   parameter set_value = 1;
1749 
   parameter wrap_value = 0;
1750 
   parameter level1_value = 15;
1751 
 
1752 
   reg  [length:1] qi;
1753 
   wire [length:1] q_next;
1754 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1755 
 
1756 
   always @ (posedge clk or posedge rst)
1757 
     if (rst)
1758 
       qi <= {length{1'b0}};
1759 
     else
1760 
       qi <= q_next;
1761 
 
1762 
   assign q = qi;
1763 
 
1764 
endmodule
1765 40 unneback 
`endif
1766 
`ifdef CNT_BIN_CE
1767 22 unneback 
//////////////////////////////////////////////////////////////////////
1768 
////                                                              ////
1769 
////  Versatile counter                                           ////
1770 
////                                                              ////
1771 
////  Description                                                 ////
1772 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1773 
////  counter                                                     ////
1774 
////                                                              ////
1775 
////  To Do:                                                      ////
1776 
////   - add LFSR with more taps                                  ////
1777 
////                                                              ////
1778 
////  Author(s):                                                  ////
1779 
////      - Michael Unneback, unneback@opencores.org              ////
1780 
////        ORSoC AB                                              ////
1781 
////                                                              ////
1782 
//////////////////////////////////////////////////////////////////////
1783 
////                                                              ////
1784 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1785 
////                                                              ////
1786 
//// This source file may be used and distributed without         ////
1787 
//// restriction provided that this copyright statement is not    ////
1788 
//// removed from the file and that any derivative work contains  ////
1789 
//// the original copyright notice and the associated disclaimer. ////
1790 
////                                                              ////
1791 
//// This source file is free software; you can redistribute it   ////
1792 
//// and/or modify it under the terms of the GNU Lesser General   ////
1793 
//// Public License as published by the Free Software Foundation; ////
1794 
//// either version 2.1 of the License, or (at your option) any   ////
1795 
//// later version.                                               ////
1796 
////                                                              ////
1797 
//// This source is distributed in the hope that it will be       ////
1798 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1799 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1800 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1801 
//// details.                                                     ////
1802 
////                                                              ////
1803 
//// You should have received a copy of the GNU Lesser General    ////
1804 
//// Public License along with this source; if not, download it   ////
1805 
//// from http://www.opencores.org/lgpl.shtml                     ////
1806 
////                                                              ////
1807 
//////////////////////////////////////////////////////////////////////
1808 
 
1809 
// binary counter
1810 6 unneback 
 
1811 40 unneback 
`define MODULE cnt_bin_ce
1812 
module `BASE`MODULE (
1813 
`undef MODULE
1814 
 cke, q, rst, clk);
1815 
 
1816 6 unneback 
   parameter length = 4;
1817 
   input cke;
1818 
   output [length:1] q;
1819 
   input rst;
1820 
   input clk;
1821 
 
1822 
   parameter clear_value = 0;
1823 
   parameter set_value = 1;
1824 
   parameter wrap_value = 0;
1825 
   parameter level1_value = 15;
1826 
 
1827 
   reg  [length:1] qi;
1828 
   wire [length:1] q_next;
1829 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1830 
 
1831 
   always @ (posedge clk or posedge rst)
1832 
     if (rst)
1833 
       qi <= {length{1'b0}};
1834 
     else
1835 
     if (cke)
1836 
       qi <= q_next;
1837 
 
1838 
   assign q = qi;
1839 
 
1840 
endmodule
1841 40 unneback 
`endif
1842 
`ifdef CNT_BIN_CE_CLEAR
1843 6 unneback 
//////////////////////////////////////////////////////////////////////
1844 
////                                                              ////
1845 
////  Versatile counter                                           ////
1846 
////                                                              ////
1847 
////  Description                                                 ////
1848 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1849 
////  counter                                                     ////
1850 
////                                                              ////
1851 
////  To Do:                                                      ////
1852 
////   - add LFSR with more taps                                  ////
1853 
////                                                              ////
1854 
////  Author(s):                                                  ////
1855 
////      - Michael Unneback, unneback@opencores.org              ////
1856 
////        ORSoC AB                                              ////
1857 
////                                                              ////
1858 
//////////////////////////////////////////////////////////////////////
1859 
////                                                              ////
1860 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1861 
////                                                              ////
1862 
//// This source file may be used and distributed without         ////
1863 
//// restriction provided that this copyright statement is not    ////
1864 
//// removed from the file and that any derivative work contains  ////
1865 
//// the original copyright notice and the associated disclaimer. ////
1866 
////                                                              ////
1867 
//// This source file is free software; you can redistribute it   ////
1868 
//// and/or modify it under the terms of the GNU Lesser General   ////
1869 
//// Public License as published by the Free Software Foundation; ////
1870 
//// either version 2.1 of the License, or (at your option) any   ////
1871 
//// later version.                                               ////
1872 
////                                                              ////
1873 
//// This source is distributed in the hope that it will be       ////
1874 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1875 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1876 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1877 
//// details.                                                     ////
1878 
////                                                              ////
1879 
//// You should have received a copy of the GNU Lesser General    ////
1880 
//// Public License along with this source; if not, download it   ////
1881 
//// from http://www.opencores.org/lgpl.shtml                     ////
1882 
////                                                              ////
1883 
//////////////////////////////////////////////////////////////////////
1884 
 
1885 
// binary counter
1886 
 
1887 40 unneback 
`define MODULE cnt_bin_ce_clear
1888 
module `BASE`MODULE (
1889 
`undef MODULE
1890 
 clear, cke, q, rst, clk);
1891 
 
1892 6 unneback 
   parameter length = 4;
1893 
   input clear;
1894 
   input cke;
1895 
   output [length:1] q;
1896 
   input rst;
1897 
   input clk;
1898 
 
1899 
   parameter clear_value = 0;
1900 
   parameter set_value = 1;
1901 
   parameter wrap_value = 0;
1902 
   parameter level1_value = 15;
1903 
 
1904 
   reg  [length:1] qi;
1905 
   wire [length:1] q_next;
1906 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1907 
 
1908 
   always @ (posedge clk or posedge rst)
1909 
     if (rst)
1910 
       qi <= {length{1'b0}};
1911 
     else
1912 
     if (cke)
1913 
       qi <= q_next;
1914 
 
1915 
   assign q = qi;
1916 
 
1917 
endmodule
1918 40 unneback 
`endif
1919 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1920 6 unneback 
//////////////////////////////////////////////////////////////////////
1921 
////                                                              ////
1922 
////  Versatile counter                                           ////
1923 
////                                                              ////
1924 
////  Description                                                 ////
1925 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1926 
////  counter                                                     ////
1927 
////                                                              ////
1928 
////  To Do:                                                      ////
1929 
////   - add LFSR with more taps                                  ////
1930 
////                                                              ////
1931 
////  Author(s):                                                  ////
1932 
////      - Michael Unneback, unneback@opencores.org              ////
1933 
////        ORSoC AB                                              ////
1934 
////                                                              ////
1935 
//////////////////////////////////////////////////////////////////////
1936 
////                                                              ////
1937 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1938 
////                                                              ////
1939 
//// This source file may be used and distributed without         ////
1940 
//// restriction provided that this copyright statement is not    ////
1941 
//// removed from the file and that any derivative work contains  ////
1942 
//// the original copyright notice and the associated disclaimer. ////
1943 
////                                                              ////
1944 
//// This source file is free software; you can redistribute it   ////
1945 
//// and/or modify it under the terms of the GNU Lesser General   ////
1946 
//// Public License as published by the Free Software Foundation; ////
1947 
//// either version 2.1 of the License, or (at your option) any   ////
1948 
//// later version.                                               ////
1949 
////                                                              ////
1950 
//// This source is distributed in the hope that it will be       ////
1951 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1952 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1953 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1954 
//// details.                                                     ////
1955 
////                                                              ////
1956 
//// You should have received a copy of the GNU Lesser General    ////
1957 
//// Public License along with this source; if not, download it   ////
1958 
//// from http://www.opencores.org/lgpl.shtml                     ////
1959 
////                                                              ////
1960 
//////////////////////////////////////////////////////////////////////
1961 
 
1962 
// binary counter
1963 29 unneback 
 
1964 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1965 
module `BASE`MODULE (
1966 
`undef MODULE
1967 
 clear, cke, q, level1, level2, rst, clk);
1968 
 
1969 29 unneback 
   parameter length = 4;
1970 
   input clear;
1971 
   input cke;
1972 
   output [length:1] q;
1973 
   output reg level1;
1974 
   output reg level2;
1975 
   input rst;
1976 
   input clk;
1977 
 
1978 
   parameter clear_value = 0;
1979 
   parameter set_value = 1;
1980 30 unneback 
   parameter wrap_value = 15;
1981 
   parameter level1_value = 8;
1982 
   parameter level2_value = 15;
1983 29 unneback 
 
1984 
   wire rew;
1985 30 unneback 
   assign rew = 1'b0;
1986 29 unneback 
   reg  [length:1] qi;
1987 
   wire [length:1] q_next;
1988 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1989 
 
1990 
   always @ (posedge clk or posedge rst)
1991 
     if (rst)
1992 
       qi <= {length{1'b0}};
1993 
     else
1994 
     if (cke)
1995 
       qi <= q_next;
1996 
 
1997 
   assign q = qi;
1998 
 
1999 
 
2000 
    always @ (posedge clk or posedge rst)
2001 
    if (rst)
2002 
        level1 <= 1'b0;
2003 
    else
2004 
    if (cke)
2005 
    if (clear)
2006 
        level1 <= 1'b0;
2007 
    else if (q_next == level1_value)
2008 
        level1 <= 1'b1;
2009 
    else if (qi == level1_value & rew)
2010 
        level1 <= 1'b0;
2011 
 
2012 
    always @ (posedge clk or posedge rst)
2013 
    if (rst)
2014 
        level2 <= 1'b0;
2015 
    else
2016 
    if (cke)
2017 
    if (clear)
2018 
        level2 <= 1'b0;
2019 
    else if (q_next == level2_value)
2020 
        level2 <= 1'b1;
2021 
    else if (qi == level2_value & rew)
2022 
        level2 <= 1'b0;
2023 
endmodule
2024 40 unneback 
`endif
2025 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2026 29 unneback 
//////////////////////////////////////////////////////////////////////
2027 
////                                                              ////
2028 
////  Versatile counter                                           ////
2029 
////                                                              ////
2030 
////  Description                                                 ////
2031 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2032 
////  counter                                                     ////
2033 
////                                                              ////
2034 
////  To Do:                                                      ////
2035 
////   - add LFSR with more taps                                  ////
2036 
////                                                              ////
2037 
////  Author(s):                                                  ////
2038 
////      - Michael Unneback, unneback@opencores.org              ////
2039 
////        ORSoC AB                                              ////
2040 
////                                                              ////
2041 
//////////////////////////////////////////////////////////////////////
2042 
////                                                              ////
2043 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2044 
////                                                              ////
2045 
//// This source file may be used and distributed without         ////
2046 
//// restriction provided that this copyright statement is not    ////
2047 
//// removed from the file and that any derivative work contains  ////
2048 
//// the original copyright notice and the associated disclaimer. ////
2049 
////                                                              ////
2050 
//// This source file is free software; you can redistribute it   ////
2051 
//// and/or modify it under the terms of the GNU Lesser General   ////
2052 
//// Public License as published by the Free Software Foundation; ////
2053 
//// either version 2.1 of the License, or (at your option) any   ////
2054 
//// later version.                                               ////
2055 
////                                                              ////
2056 
//// This source is distributed in the hope that it will be       ////
2057 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2058 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2059 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2060 
//// details.                                                     ////
2061 
////                                                              ////
2062 
//// You should have received a copy of the GNU Lesser General    ////
2063 
//// Public License along with this source; if not, download it   ////
2064 
//// from http://www.opencores.org/lgpl.shtml                     ////
2065 
////                                                              ////
2066 
//////////////////////////////////////////////////////////////////////
2067 
 
2068 
// binary counter
2069 6 unneback 
 
2070 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
2071 
module `BASE`MODULE (
2072 
`undef MODULE
2073 
 clear, set, cke, rew, q, rst, clk);
2074 
 
2075 6 unneback 
   parameter length = 4;
2076 
   input clear;
2077 
   input set;
2078 
   input cke;
2079 
   input rew;
2080 
   output [length:1] q;
2081 
   input rst;
2082 
   input clk;
2083 
 
2084 
   parameter clear_value = 0;
2085 
   parameter set_value = 1;
2086 
   parameter wrap_value = 0;
2087 
   parameter level1_value = 15;
2088 
 
2089 
   reg  [length:1] qi;
2090 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2091 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2092 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2093 
   assign q_next = rew ? q_next_rew : q_next_fw;
2094 
 
2095 
   always @ (posedge clk or posedge rst)
2096 
     if (rst)
2097 
       qi <= {length{1'b0}};
2098 
     else
2099 
     if (cke)
2100 
       qi <= q_next;
2101 
 
2102 
   assign q = qi;
2103 
 
2104 
endmodule
2105 40 unneback 
`endif
2106 
`ifdef CNT_BIN_CE_REW_L1
2107 6 unneback 
//////////////////////////////////////////////////////////////////////
2108 
////                                                              ////
2109 
////  Versatile counter                                           ////
2110 
////                                                              ////
2111 
////  Description                                                 ////
2112 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2113 
////  counter                                                     ////
2114 
////                                                              ////
2115 
////  To Do:                                                      ////
2116 
////   - add LFSR with more taps                                  ////
2117 
////                                                              ////
2118 
////  Author(s):                                                  ////
2119 
////      - Michael Unneback, unneback@opencores.org              ////
2120 
////        ORSoC AB                                              ////
2121 
////                                                              ////
2122 
//////////////////////////////////////////////////////////////////////
2123 
////                                                              ////
2124 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2125 
////                                                              ////
2126 
//// This source file may be used and distributed without         ////
2127 
//// restriction provided that this copyright statement is not    ////
2128 
//// removed from the file and that any derivative work contains  ////
2129 
//// the original copyright notice and the associated disclaimer. ////
2130 
////                                                              ////
2131 
//// This source file is free software; you can redistribute it   ////
2132 
//// and/or modify it under the terms of the GNU Lesser General   ////
2133 
//// Public License as published by the Free Software Foundation; ////
2134 
//// either version 2.1 of the License, or (at your option) any   ////
2135 
//// later version.                                               ////
2136 
////                                                              ////
2137 
//// This source is distributed in the hope that it will be       ////
2138 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2139 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2140 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2141 
//// details.                                                     ////
2142 
////                                                              ////
2143 
//// You should have received a copy of the GNU Lesser General    ////
2144 
//// Public License along with this source; if not, download it   ////
2145 
//// from http://www.opencores.org/lgpl.shtml                     ////
2146 
////                                                              ////
2147 
//////////////////////////////////////////////////////////////////////
2148 
 
2149 
// binary counter
2150 
 
2151 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
2152 
module `BASE`MODULE (
2153 
`undef MODULE
2154 
 cke, rew, level1, rst, clk);
2155 
 
2156 6 unneback 
   parameter length = 4;
2157 
   input cke;
2158 
   input rew;
2159 
   output reg level1;
2160 
   input rst;
2161 
   input clk;
2162 
 
2163 
   parameter clear_value = 0;
2164 
   parameter set_value = 1;
2165 
   parameter wrap_value = 1;
2166 
   parameter level1_value = 15;
2167 
 
2168 29 unneback 
   wire clear;
2169 30 unneback 
   assign clear = 1'b0;
2170 6 unneback 
   reg  [length:1] qi;
2171 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2172 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2173 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2174 
   assign q_next = rew ? q_next_rew : q_next_fw;
2175 
 
2176 
   always @ (posedge clk or posedge rst)
2177 
     if (rst)
2178 
       qi <= {length{1'b0}};
2179 
     else
2180 
     if (cke)
2181 
       qi <= q_next;
2182 
 
2183 
 
2184 
 
2185 
    always @ (posedge clk or posedge rst)
2186 
    if (rst)
2187 
        level1 <= 1'b0;
2188 
    else
2189 
    if (cke)
2190 29 unneback 
    if (clear)
2191 
        level1 <= 1'b0;
2192 
    else if (q_next == level1_value)
2193 6 unneback 
        level1 <= 1'b1;
2194 
    else if (qi == level1_value & rew)
2195 
        level1 <= 1'b0;
2196 
endmodule
2197 40 unneback 
`endif
2198 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2199 6 unneback 
//////////////////////////////////////////////////////////////////////
2200 
////                                                              ////
2201 
////  Versatile counter                                           ////
2202 
////                                                              ////
2203 
////  Description                                                 ////
2204 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2205 
////  counter                                                     ////
2206 
////                                                              ////
2207 
////  To Do:                                                      ////
2208 
////   - add LFSR with more taps                                  ////
2209 
////                                                              ////
2210 
////  Author(s):                                                  ////
2211 
////      - Michael Unneback, unneback@opencores.org              ////
2212 
////        ORSoC AB                                              ////
2213 
////                                                              ////
2214 
//////////////////////////////////////////////////////////////////////
2215 
////                                                              ////
2216 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2217 
////                                                              ////
2218 
//// This source file may be used and distributed without         ////
2219 
//// restriction provided that this copyright statement is not    ////
2220 
//// removed from the file and that any derivative work contains  ////
2221 
//// the original copyright notice and the associated disclaimer. ////
2222 
////                                                              ////
2223 
//// This source file is free software; you can redistribute it   ////
2224 
//// and/or modify it under the terms of the GNU Lesser General   ////
2225 
//// Public License as published by the Free Software Foundation; ////
2226 
//// either version 2.1 of the License, or (at your option) any   ////
2227 
//// later version.                                               ////
2228 
////                                                              ////
2229 
//// This source is distributed in the hope that it will be       ////
2230 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2231 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2232 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2233 
//// details.                                                     ////
2234 
////                                                              ////
2235 
//// You should have received a copy of the GNU Lesser General    ////
2236 
//// Public License along with this source; if not, download it   ////
2237 
//// from http://www.opencores.org/lgpl.shtml                     ////
2238 
////                                                              ////
2239 
//////////////////////////////////////////////////////////////////////
2240 
 
2241 25 unneback 
// binary counter
2242 
 
2243 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2244 
module `BASE`MODULE (
2245 
`undef MODULE
2246 
 cke, rew, zq, level1, rst, clk);
2247 
 
2248 25 unneback 
   parameter length = 4;
2249 
   input cke;
2250 
   input rew;
2251 
   output reg zq;
2252 
   output reg level1;
2253 
   input rst;
2254 
   input clk;
2255 
 
2256 
   parameter clear_value = 0;
2257 
   parameter set_value = 1;
2258 
   parameter wrap_value = 1;
2259 
   parameter level1_value = 15;
2260 
 
2261 29 unneback 
   wire clear;
2262 30 unneback 
   assign clear = 1'b0;
2263 25 unneback 
   reg  [length:1] qi;
2264 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2265 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2266 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2267 
   assign q_next = rew ? q_next_rew : q_next_fw;
2268 
 
2269 
   always @ (posedge clk or posedge rst)
2270 
     if (rst)
2271 
       qi <= {length{1'b0}};
2272 
     else
2273 
     if (cke)
2274 
       qi <= q_next;
2275 
 
2276 
 
2277 
 
2278 
   always @ (posedge clk or posedge rst)
2279 
     if (rst)
2280 
       zq <= 1'b1;
2281 
     else
2282 
     if (cke)
2283 
       zq <= q_next == {length{1'b0}};
2284 
 
2285 
    always @ (posedge clk or posedge rst)
2286 
    if (rst)
2287 
        level1 <= 1'b0;
2288 
    else
2289 
    if (cke)
2290 29 unneback 
    if (clear)
2291 
        level1 <= 1'b0;
2292 
    else if (q_next == level1_value)
2293 25 unneback 
        level1 <= 1'b1;
2294 
    else if (qi == level1_value & rew)
2295 
        level1 <= 1'b0;
2296 
endmodule
2297 40 unneback 
`endif
2298 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2299 25 unneback 
//////////////////////////////////////////////////////////////////////
2300 
////                                                              ////
2301 
////  Versatile counter                                           ////
2302 
////                                                              ////
2303 
////  Description                                                 ////
2304 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2305 
////  counter                                                     ////
2306 
////                                                              ////
2307 
////  To Do:                                                      ////
2308 
////   - add LFSR with more taps                                  ////
2309 
////                                                              ////
2310 
////  Author(s):                                                  ////
2311 
////      - Michael Unneback, unneback@opencores.org              ////
2312 
////        ORSoC AB                                              ////
2313 
////                                                              ////
2314 
//////////////////////////////////////////////////////////////////////
2315 
////                                                              ////
2316 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2317 
////                                                              ////
2318 
//// This source file may be used and distributed without         ////
2319 
//// restriction provided that this copyright statement is not    ////
2320 
//// removed from the file and that any derivative work contains  ////
2321 
//// the original copyright notice and the associated disclaimer. ////
2322 
////                                                              ////
2323 
//// This source file is free software; you can redistribute it   ////
2324 
//// and/or modify it under the terms of the GNU Lesser General   ////
2325 
//// Public License as published by the Free Software Foundation; ////
2326 
//// either version 2.1 of the License, or (at your option) any   ////
2327 
//// later version.                                               ////
2328 
////                                                              ////
2329 
//// This source is distributed in the hope that it will be       ////
2330 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2331 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2332 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2333 
//// details.                                                     ////
2334 
////                                                              ////
2335 
//// You should have received a copy of the GNU Lesser General    ////
2336 
//// Public License along with this source; if not, download it   ////
2337 
//// from http://www.opencores.org/lgpl.shtml                     ////
2338 
////                                                              ////
2339 
//////////////////////////////////////////////////////////////////////
2340 
 
2341 
// binary counter
2342 
 
2343 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2344 
module `BASE`MODULE (
2345 
`undef MODULE
2346 
 cke, rew, q, zq, level1, rst, clk);
2347 
 
2348 25 unneback 
   parameter length = 4;
2349 
   input cke;
2350 
   input rew;
2351 
   output [length:1] q;
2352 
   output reg zq;
2353 
   output reg level1;
2354 
   input rst;
2355 
   input clk;
2356 
 
2357 
   parameter clear_value = 0;
2358 
   parameter set_value = 1;
2359 
   parameter wrap_value = 1;
2360 
   parameter level1_value = 15;
2361 
 
2362 29 unneback 
   wire clear;
2363 30 unneback 
   assign clear = 1'b0;
2364 25 unneback 
   reg  [length:1] qi;
2365 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2366 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2367 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2368 
   assign q_next = rew ? q_next_rew : q_next_fw;
2369 
 
2370 
   always @ (posedge clk or posedge rst)
2371 
     if (rst)
2372 
       qi <= {length{1'b0}};
2373 
     else
2374 
     if (cke)
2375 
       qi <= q_next;
2376 
 
2377 
   assign q = qi;
2378 
 
2379 
 
2380 
   always @ (posedge clk or posedge rst)
2381 
     if (rst)
2382 
       zq <= 1'b1;
2383 
     else
2384 
     if (cke)
2385 
       zq <= q_next == {length{1'b0}};
2386 
 
2387 
    always @ (posedge clk or posedge rst)
2388 
    if (rst)
2389 
        level1 <= 1'b0;
2390 
    else
2391 
    if (cke)
2392 29 unneback 
    if (clear)
2393 
        level1 <= 1'b0;
2394 
    else if (q_next == level1_value)
2395 25 unneback 
        level1 <= 1'b1;
2396 
    else if (qi == level1_value & rew)
2397 
        level1 <= 1'b0;
2398 
endmodule
2399 40 unneback 
`endif
2400 
`ifdef CNT_LFSR_ZQ
2401 25 unneback 
//////////////////////////////////////////////////////////////////////
2402 
////                                                              ////
2403 
////  Versatile counter                                           ////
2404 
////                                                              ////
2405 
////  Description                                                 ////
2406 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2407 
////  counter                                                     ////
2408 
////                                                              ////
2409 
////  To Do:                                                      ////
2410 
////   - add LFSR with more taps                                  ////
2411 
////                                                              ////
2412 
////  Author(s):                                                  ////
2413 
////      - Michael Unneback, unneback@opencores.org              ////
2414 
////        ORSoC AB                                              ////
2415 
////                                                              ////
2416 
//////////////////////////////////////////////////////////////////////
2417 
////                                                              ////
2418 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2419 
////                                                              ////
2420 
//// This source file may be used and distributed without         ////
2421 
//// restriction provided that this copyright statement is not    ////
2422 
//// removed from the file and that any derivative work contains  ////
2423 
//// the original copyright notice and the associated disclaimer. ////
2424 
////                                                              ////
2425 
//// This source file is free software; you can redistribute it   ////
2426 
//// and/or modify it under the terms of the GNU Lesser General   ////
2427 
//// Public License as published by the Free Software Foundation; ////
2428 
//// either version 2.1 of the License, or (at your option) any   ////
2429 
//// later version.                                               ////
2430 
////                                                              ////
2431 
//// This source is distributed in the hope that it will be       ////
2432 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2433 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2434 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2435 
//// details.                                                     ////
2436 
////                                                              ////
2437 
//// You should have received a copy of the GNU Lesser General    ////
2438 
//// Public License along with this source; if not, download it   ////
2439 
//// from http://www.opencores.org/lgpl.shtml                     ////
2440 
////                                                              ////
2441 
//////////////////////////////////////////////////////////////////////
2442 
 
2443 6 unneback 
// LFSR counter
2444 
 
2445 40 unneback 
`define MODULE cnt_lfsr_zq
2446 
module `BASE`MODULE (
2447 
`undef MODULE
2448 
 zq, rst, clk);
2449 
 
2450 6 unneback 
   parameter length = 4;
2451 
   output reg zq;
2452 
   input rst;
2453 
   input clk;
2454 
 
2455 
   parameter clear_value = 0;
2456 
   parameter set_value = 1;
2457 
   parameter wrap_value = 8;
2458 
   parameter level1_value = 15;
2459 
 
2460 
   reg  [length:1] qi;
2461 
   reg lfsr_fb;
2462 
   wire [length:1] q_next;
2463 
   reg [32:1] polynom;
2464 
   integer i;
2465 
 
2466 
   always @ (qi)
2467 
   begin
2468 
        case (length)
2469 
         2: polynom = 32'b11;                               // 0x3
2470 
         3: polynom = 32'b110;                              // 0x6
2471 
         4: polynom = 32'b1100;                             // 0xC
2472 
         5: polynom = 32'b10100;                            // 0x14
2473 
         6: polynom = 32'b110000;                           // 0x30
2474 
         7: polynom = 32'b1100000;                          // 0x60
2475 
         8: polynom = 32'b10111000;                         // 0xb8
2476 
         9: polynom = 32'b100010000;                        // 0x110
2477 
        10: polynom = 32'b1001000000;                       // 0x240
2478 
        11: polynom = 32'b10100000000;                      // 0x500
2479 
        12: polynom = 32'b100000101001;                     // 0x829
2480 
        13: polynom = 32'b1000000001100;                    // 0x100C
2481 
        14: polynom = 32'b10000000010101;                   // 0x2015
2482 
        15: polynom = 32'b110000000000000;                  // 0x6000
2483 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2484 
        17: polynom = 32'b10010000000000000;                // 0x12000
2485 
        18: polynom = 32'b100000010000000000;               // 0x20400
2486 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2487 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2488 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2489 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2490 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2491 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2492 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2493 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2494 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2495 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2496 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2497 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2498 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2499 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2500 
        default: polynom = 32'b0;
2501 
        endcase
2502 
        lfsr_fb = qi[length];
2503 
        for (i=length-1; i>=1; i=i-1) begin
2504 
            if (polynom[i])
2505 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2506 
        end
2507 
    end
2508 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2509 
 
2510 
   always @ (posedge clk or posedge rst)
2511 
     if (rst)
2512 
       qi <= {length{1'b0}};
2513 
     else
2514 
       qi <= q_next;
2515 
 
2516 
 
2517 
 
2518 
   always @ (posedge clk or posedge rst)
2519 
     if (rst)
2520 
       zq <= 1'b1;
2521 
     else
2522 
       zq <= q_next == {length{1'b0}};
2523 
endmodule
2524 40 unneback 
`endif
2525 75 unneback 
`ifdef CNT_LFSR_CE
2526 
//////////////////////////////////////////////////////////////////////
2527 
////                                                              ////
2528 
////  Versatile counter                                           ////
2529 
////                                                              ////
2530 
////  Description                                                 ////
2531 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2532 
////  counter                                                     ////
2533 
////                                                              ////
2534 
////  To Do:                                                      ////
2535 
////   - add LFSR with more taps                                  ////
2536 
////                                                              ////
2537 
////  Author(s):                                                  ////
2538 
////      - Michael Unneback, unneback@opencores.org              ////
2539 
////        ORSoC AB                                              ////
2540 
////                                                              ////
2541 
//////////////////////////////////////////////////////////////////////
2542 
////                                                              ////
2543 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2544 
////                                                              ////
2545 
//// This source file may be used and distributed without         ////
2546 
//// restriction provided that this copyright statement is not    ////
2547 
//// removed from the file and that any derivative work contains  ////
2548 
//// the original copyright notice and the associated disclaimer. ////
2549 
////                                                              ////
2550 
//// This source file is free software; you can redistribute it   ////
2551 
//// and/or modify it under the terms of the GNU Lesser General   ////
2552 
//// Public License as published by the Free Software Foundation; ////
2553 
//// either version 2.1 of the License, or (at your option) any   ////
2554 
//// later version.                                               ////
2555 
////                                                              ////
2556 
//// This source is distributed in the hope that it will be       ////
2557 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2558 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2559 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2560 
//// details.                                                     ////
2561 
////                                                              ////
2562 
//// You should have received a copy of the GNU Lesser General    ////
2563 
//// Public License along with this source; if not, download it   ////
2564 
//// from http://www.opencores.org/lgpl.shtml                     ////
2565 
////                                                              ////
2566 
//////////////////////////////////////////////////////////////////////
2567 
 
2568 
// LFSR counter
2569 
 
2570 
`define MODULE cnt_lfsr_ce
2571 
module `BASE`MODULE (
2572 
`undef MODULE
2573 
 cke, zq, rst, clk);
2574 
 
2575 
   parameter length = 4;
2576 
   input cke;
2577 
   output reg zq;
2578 
   input rst;
2579 
   input clk;
2580 
 
2581 
   parameter clear_value = 0;
2582 
   parameter set_value = 1;
2583 
   parameter wrap_value = 0;
2584 
   parameter level1_value = 15;
2585 
 
2586 
   reg  [length:1] qi;
2587 
   reg lfsr_fb;
2588 
   wire [length:1] q_next;
2589 
   reg [32:1] polynom;
2590 
   integer i;
2591 
 
2592 
   always @ (qi)
2593 
   begin
2594 
        case (length)
2595 
         2: polynom = 32'b11;                               // 0x3
2596 
         3: polynom = 32'b110;                              // 0x6
2597 
         4: polynom = 32'b1100;                             // 0xC
2598 
         5: polynom = 32'b10100;                            // 0x14
2599 
         6: polynom = 32'b110000;                           // 0x30
2600 
         7: polynom = 32'b1100000;                          // 0x60
2601 
         8: polynom = 32'b10111000;                         // 0xb8
2602 
         9: polynom = 32'b100010000;                        // 0x110
2603 
        10: polynom = 32'b1001000000;                       // 0x240
2604 
        11: polynom = 32'b10100000000;                      // 0x500
2605 
        12: polynom = 32'b100000101001;                     // 0x829
2606 
        13: polynom = 32'b1000000001100;                    // 0x100C
2607 
        14: polynom = 32'b10000000010101;                   // 0x2015
2608 
        15: polynom = 32'b110000000000000;                  // 0x6000
2609 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2610 
        17: polynom = 32'b10010000000000000;                // 0x12000
2611 
        18: polynom = 32'b100000010000000000;               // 0x20400
2612 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2613 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2614 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2615 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2616 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2617 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2618 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2619 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2620 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2621 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2622 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2623 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2624 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2625 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2626 
        default: polynom = 32'b0;
2627 
        endcase
2628 
        lfsr_fb = qi[length];
2629 
        for (i=length-1; i>=1; i=i-1) begin
2630 
            if (polynom[i])
2631 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2632 
        end
2633 
    end
2634 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2635 
 
2636 
   always @ (posedge clk or posedge rst)
2637 
     if (rst)
2638 
       qi <= {length{1'b0}};
2639 
     else
2640 
     if (cke)
2641 
       qi <= q_next;
2642 
 
2643 
 
2644 
 
2645 
   always @ (posedge clk or posedge rst)
2646 
     if (rst)
2647 
       zq <= 1'b1;
2648 
     else
2649 
     if (cke)
2650 
       zq <= q_next == {length{1'b0}};
2651 
endmodule
2652 
`endif
2653 40 unneback 
`ifdef CNT_LFSR_CE_ZQ
2654 6 unneback 
//////////////////////////////////////////////////////////////////////
2655 
////                                                              ////
2656 
////  Versatile counter                                           ////
2657 
////                                                              ////
2658 
////  Description                                                 ////
2659 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2660 
////  counter                                                     ////
2661 
////                                                              ////
2662 
////  To Do:                                                      ////
2663 
////   - add LFSR with more taps                                  ////
2664 
////                                                              ////
2665 
////  Author(s):                                                  ////
2666 
////      - Michael Unneback, unneback@opencores.org              ////
2667 
////        ORSoC AB                                              ////
2668 
////                                                              ////
2669 
//////////////////////////////////////////////////////////////////////
2670 
////                                                              ////
2671 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2672 
////                                                              ////
2673 
//// This source file may be used and distributed without         ////
2674 
//// restriction provided that this copyright statement is not    ////
2675 
//// removed from the file and that any derivative work contains  ////
2676 
//// the original copyright notice and the associated disclaimer. ////
2677 
////                                                              ////
2678 
//// This source file is free software; you can redistribute it   ////
2679 
//// and/or modify it under the terms of the GNU Lesser General   ////
2680 
//// Public License as published by the Free Software Foundation; ////
2681 
//// either version 2.1 of the License, or (at your option) any   ////
2682 
//// later version.                                               ////
2683 
////                                                              ////
2684 
//// This source is distributed in the hope that it will be       ////
2685 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2686 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2687 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2688 
//// details.                                                     ////
2689 
////                                                              ////
2690 
//// You should have received a copy of the GNU Lesser General    ////
2691 
//// Public License along with this source; if not, download it   ////
2692 
//// from http://www.opencores.org/lgpl.shtml                     ////
2693 
////                                                              ////
2694 
//////////////////////////////////////////////////////////////////////
2695 
 
2696 
// LFSR counter
2697 
 
2698 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2699 
module `BASE`MODULE (
2700 
`undef MODULE
2701 
 cke, zq, rst, clk);
2702 
 
2703 6 unneback 
   parameter length = 4;
2704 
   input cke;
2705 
   output reg zq;
2706 
   input rst;
2707 
   input clk;
2708 
 
2709 
   parameter clear_value = 0;
2710 
   parameter set_value = 1;
2711 
   parameter wrap_value = 8;
2712 
   parameter level1_value = 15;
2713 
 
2714 
   reg  [length:1] qi;
2715 
   reg lfsr_fb;
2716 
   wire [length:1] q_next;
2717 
   reg [32:1] polynom;
2718 
   integer i;
2719 
 
2720 
   always @ (qi)
2721 
   begin
2722 
        case (length)
2723 
         2: polynom = 32'b11;                               // 0x3
2724 
         3: polynom = 32'b110;                              // 0x6
2725 
         4: polynom = 32'b1100;                             // 0xC
2726 
         5: polynom = 32'b10100;                            // 0x14
2727 
         6: polynom = 32'b110000;                           // 0x30
2728 
         7: polynom = 32'b1100000;                          // 0x60
2729 
         8: polynom = 32'b10111000;                         // 0xb8
2730 
         9: polynom = 32'b100010000;                        // 0x110
2731 
        10: polynom = 32'b1001000000;                       // 0x240
2732 
        11: polynom = 32'b10100000000;                      // 0x500
2733 
        12: polynom = 32'b100000101001;                     // 0x829
2734 
        13: polynom = 32'b1000000001100;                    // 0x100C
2735 
        14: polynom = 32'b10000000010101;                   // 0x2015
2736 
        15: polynom = 32'b110000000000000;                  // 0x6000
2737 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2738 
        17: polynom = 32'b10010000000000000;                // 0x12000
2739 
        18: polynom = 32'b100000010000000000;               // 0x20400
2740 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2741 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2742 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2743 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2744 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2745 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2746 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2747 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2748 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2749 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2750 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2751 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2752 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2753 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2754 
        default: polynom = 32'b0;
2755 
        endcase
2756 
        lfsr_fb = qi[length];
2757 
        for (i=length-1; i>=1; i=i-1) begin
2758 
            if (polynom[i])
2759 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2760 
        end
2761 
    end
2762 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2763 
 
2764 
   always @ (posedge clk or posedge rst)
2765 
     if (rst)
2766 
       qi <= {length{1'b0}};
2767 
     else
2768 
     if (cke)
2769 
       qi <= q_next;
2770 
 
2771 
 
2772 
 
2773 
   always @ (posedge clk or posedge rst)
2774 
     if (rst)
2775 
       zq <= 1'b1;
2776 
     else
2777 
     if (cke)
2778 
       zq <= q_next == {length{1'b0}};
2779 
endmodule
2780 40 unneback 
`endif
2781 
`ifdef CNT_LFSR_CE_Q
2782 6 unneback 
//////////////////////////////////////////////////////////////////////
2783 
////                                                              ////
2784 
////  Versatile counter                                           ////
2785 
////                                                              ////
2786 
////  Description                                                 ////
2787 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2788 
////  counter                                                     ////
2789 
////                                                              ////
2790 
////  To Do:                                                      ////
2791 
////   - add LFSR with more taps                                  ////
2792 
////                                                              ////
2793 
////  Author(s):                                                  ////
2794 
////      - Michael Unneback, unneback@opencores.org              ////
2795 
////        ORSoC AB                                              ////
2796 
////                                                              ////
2797 
//////////////////////////////////////////////////////////////////////
2798 
////                                                              ////
2799 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2800 
////                                                              ////
2801 
//// This source file may be used and distributed without         ////
2802 
//// restriction provided that this copyright statement is not    ////
2803 
//// removed from the file and that any derivative work contains  ////
2804 
//// the original copyright notice and the associated disclaimer. ////
2805 
////                                                              ////
2806 
//// This source file is free software; you can redistribute it   ////
2807 
//// and/or modify it under the terms of the GNU Lesser General   ////
2808 
//// Public License as published by the Free Software Foundation; ////
2809 
//// either version 2.1 of the License, or (at your option) any   ////
2810 
//// later version.                                               ////
2811 
////                                                              ////
2812 
//// This source is distributed in the hope that it will be       ////
2813 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2814 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2815 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2816 
//// details.                                                     ////
2817 
////                                                              ////
2818 
//// You should have received a copy of the GNU Lesser General    ////
2819 
//// Public License along with this source; if not, download it   ////
2820 
//// from http://www.opencores.org/lgpl.shtml                     ////
2821 
////                                                              ////
2822 
//////////////////////////////////////////////////////////////////////
2823 22 unneback 
 
2824 
// LFSR counter
2825 27 unneback 
 
2826 40 unneback 
`define MODULE cnt_lfsr_ce_q
2827 
module `BASE`MODULE (
2828 
`undef MODULE
2829 
 cke, q, rst, clk);
2830 
 
2831 27 unneback 
   parameter length = 4;
2832 
   input cke;
2833 
   output [length:1] q;
2834 
   input rst;
2835 
   input clk;
2836 
 
2837 
   parameter clear_value = 0;
2838 
   parameter set_value = 1;
2839 
   parameter wrap_value = 8;
2840 
   parameter level1_value = 15;
2841 
 
2842 
   reg  [length:1] qi;
2843 
   reg lfsr_fb;
2844 
   wire [length:1] q_next;
2845 
   reg [32:1] polynom;
2846 
   integer i;
2847 
 
2848 
   always @ (qi)
2849 
   begin
2850 
        case (length)
2851 
         2: polynom = 32'b11;                               // 0x3
2852 
         3: polynom = 32'b110;                              // 0x6
2853 
         4: polynom = 32'b1100;                             // 0xC
2854 
         5: polynom = 32'b10100;                            // 0x14
2855 
         6: polynom = 32'b110000;                           // 0x30
2856 
         7: polynom = 32'b1100000;                          // 0x60
2857 
         8: polynom = 32'b10111000;                         // 0xb8
2858 
         9: polynom = 32'b100010000;                        // 0x110
2859 
        10: polynom = 32'b1001000000;                       // 0x240
2860 
        11: polynom = 32'b10100000000;                      // 0x500
2861 
        12: polynom = 32'b100000101001;                     // 0x829
2862 
        13: polynom = 32'b1000000001100;                    // 0x100C
2863 
        14: polynom = 32'b10000000010101;                   // 0x2015
2864 
        15: polynom = 32'b110000000000000;                  // 0x6000
2865 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2866 
        17: polynom = 32'b10010000000000000;                // 0x12000
2867 
        18: polynom = 32'b100000010000000000;               // 0x20400
2868 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2869 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2870 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2871 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2872 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2873 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2874 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2875 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2876 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2877 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2878 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2879 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2880 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2881 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2882 
        default: polynom = 32'b0;
2883 
        endcase
2884 
        lfsr_fb = qi[length];
2885 
        for (i=length-1; i>=1; i=i-1) begin
2886 
            if (polynom[i])
2887 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2888 
        end
2889 
    end
2890 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2891 
 
2892 
   always @ (posedge clk or posedge rst)
2893 
     if (rst)
2894 
       qi <= {length{1'b0}};
2895 
     else
2896 
     if (cke)
2897 
       qi <= q_next;
2898 
 
2899 
   assign q = qi;
2900 
 
2901 
endmodule
2902 40 unneback 
`endif
2903 
`ifdef CNT_LFSR_CE_CLEAR_Q
2904 27 unneback 
//////////////////////////////////////////////////////////////////////
2905 
////                                                              ////
2906 
////  Versatile counter                                           ////
2907 
////                                                              ////
2908 
////  Description                                                 ////
2909 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2910 
////  counter                                                     ////
2911 
////                                                              ////
2912 
////  To Do:                                                      ////
2913 
////   - add LFSR with more taps                                  ////
2914 
////                                                              ////
2915 
////  Author(s):                                                  ////
2916 
////      - Michael Unneback, unneback@opencores.org              ////
2917 
////        ORSoC AB                                              ////
2918 
////                                                              ////
2919 
//////////////////////////////////////////////////////////////////////
2920 
////                                                              ////
2921 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2922 
////                                                              ////
2923 
//// This source file may be used and distributed without         ////
2924 
//// restriction provided that this copyright statement is not    ////
2925 
//// removed from the file and that any derivative work contains  ////
2926 
//// the original copyright notice and the associated disclaimer. ////
2927 
////                                                              ////
2928 
//// This source file is free software; you can redistribute it   ////
2929 
//// and/or modify it under the terms of the GNU Lesser General   ////
2930 
//// Public License as published by the Free Software Foundation; ////
2931 
//// either version 2.1 of the License, or (at your option) any   ////
2932 
//// later version.                                               ////
2933 
////                                                              ////
2934 
//// This source is distributed in the hope that it will be       ////
2935 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2936 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2937 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2938 
//// details.                                                     ////
2939 
////                                                              ////
2940 
//// You should have received a copy of the GNU Lesser General    ////
2941 
//// Public License along with this source; if not, download it   ////
2942 
//// from http://www.opencores.org/lgpl.shtml                     ////
2943 
////                                                              ////
2944 
//////////////////////////////////////////////////////////////////////
2945 
 
2946 
// LFSR counter
2947 
 
2948 40 unneback 
`define MODULE cnt_lfsr_ce_clear_q
2949 
module `BASE`MODULE (
2950 
`undef MODULE
2951 
 clear, cke, q, rst, clk);
2952 
 
2953 27 unneback 
   parameter length = 4;
2954 
   input clear;
2955 
   input cke;
2956 
   output [length:1] q;
2957 
   input rst;
2958 
   input clk;
2959 
 
2960 
   parameter clear_value = 0;
2961 
   parameter set_value = 1;
2962 
   parameter wrap_value = 8;
2963 
   parameter level1_value = 15;
2964 
 
2965 
   reg  [length:1] qi;
2966 
   reg lfsr_fb;
2967 
   wire [length:1] q_next;
2968 
   reg [32:1] polynom;
2969 
   integer i;
2970 
 
2971 
   always @ (qi)
2972 
   begin
2973 
        case (length)
2974 
         2: polynom = 32'b11;                               // 0x3
2975 
         3: polynom = 32'b110;                              // 0x6
2976 
         4: polynom = 32'b1100;                             // 0xC
2977 
         5: polynom = 32'b10100;                            // 0x14
2978 
         6: polynom = 32'b110000;                           // 0x30
2979 
         7: polynom = 32'b1100000;                          // 0x60
2980 
         8: polynom = 32'b10111000;                         // 0xb8
2981 
         9: polynom = 32'b100010000;                        // 0x110
2982 
        10: polynom = 32'b1001000000;                       // 0x240
2983 
        11: polynom = 32'b10100000000;                      // 0x500
2984 
        12: polynom = 32'b100000101001;                     // 0x829
2985 
        13: polynom = 32'b1000000001100;                    // 0x100C
2986 
        14: polynom = 32'b10000000010101;                   // 0x2015
2987 
        15: polynom = 32'b110000000000000;                  // 0x6000
2988 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2989 
        17: polynom = 32'b10010000000000000;                // 0x12000
2990 
        18: polynom = 32'b100000010000000000;               // 0x20400
2991 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2992 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2993 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2994 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2995 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2996 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2997 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2998 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2999 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3000 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3001 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3002 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3003 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3004 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3005 
        default: polynom = 32'b0;
3006 
        endcase
3007 
        lfsr_fb = qi[length];
3008 
        for (i=length-1; i>=1; i=i-1) begin
3009 
            if (polynom[i])
3010 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3011 
        end
3012 
    end
3013 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3014 
 
3015 
   always @ (posedge clk or posedge rst)
3016 
     if (rst)
3017 
       qi <= {length{1'b0}};
3018 
     else
3019 
     if (cke)
3020 
       qi <= q_next;
3021 
 
3022 
   assign q = qi;
3023 
 
3024 
endmodule
3025 40 unneback 
`endif
3026 
`ifdef CNT_LFSR_CE_Q_ZQ
3027 27 unneback 
//////////////////////////////////////////////////////////////////////
3028 
////                                                              ////
3029 
////  Versatile counter                                           ////
3030 
////                                                              ////
3031 
////  Description                                                 ////
3032 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3033 
////  counter                                                     ////
3034 
////                                                              ////
3035 
////  To Do:                                                      ////
3036 
////   - add LFSR with more taps                                  ////
3037 
////                                                              ////
3038 
////  Author(s):                                                  ////
3039 
////      - Michael Unneback, unneback@opencores.org              ////
3040 
////        ORSoC AB                                              ////
3041 
////                                                              ////
3042 
//////////////////////////////////////////////////////////////////////
3043 
////                                                              ////
3044 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3045 
////                                                              ////
3046 
//// This source file may be used and distributed without         ////
3047 
//// restriction provided that this copyright statement is not    ////
3048 
//// removed from the file and that any derivative work contains  ////
3049 
//// the original copyright notice and the associated disclaimer. ////
3050 
////                                                              ////
3051 
//// This source file is free software; you can redistribute it   ////
3052 
//// and/or modify it under the terms of the GNU Lesser General   ////
3053 
//// Public License as published by the Free Software Foundation; ////
3054 
//// either version 2.1 of the License, or (at your option) any   ////
3055 
//// later version.                                               ////
3056 
////                                                              ////
3057 
//// This source is distributed in the hope that it will be       ////
3058 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3059 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3060 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3061 
//// details.                                                     ////
3062 
////                                                              ////
3063 
//// You should have received a copy of the GNU Lesser General    ////
3064 
//// Public License along with this source; if not, download it   ////
3065 
//// from http://www.opencores.org/lgpl.shtml                     ////
3066 
////                                                              ////
3067 
//////////////////////////////////////////////////////////////////////
3068 
 
3069 
// LFSR counter
3070 22 unneback 
 
3071 40 unneback 
`define MODULE cnt_lfsr_ce_q_zq
3072 
module `BASE`MODULE (
3073 
`undef MODULE
3074 
 cke, q, zq, rst, clk);
3075 
 
3076 22 unneback 
   parameter length = 4;
3077 
   input cke;
3078 
   output [length:1] q;
3079 
   output reg zq;
3080 
   input rst;
3081 
   input clk;
3082 
 
3083 
   parameter clear_value = 0;
3084 
   parameter set_value = 1;
3085 
   parameter wrap_value = 8;
3086 
   parameter level1_value = 15;
3087 
 
3088 
   reg  [length:1] qi;
3089 
   reg lfsr_fb;
3090 
   wire [length:1] q_next;
3091 
   reg [32:1] polynom;
3092 
   integer i;
3093 
 
3094 
   always @ (qi)
3095 
   begin
3096 
        case (length)
3097 
         2: polynom = 32'b11;                               // 0x3
3098 
         3: polynom = 32'b110;                              // 0x6
3099 
         4: polynom = 32'b1100;                             // 0xC
3100 
         5: polynom = 32'b10100;                            // 0x14
3101 
         6: polynom = 32'b110000;                           // 0x30
3102 
         7: polynom = 32'b1100000;                          // 0x60
3103 
         8: polynom = 32'b10111000;                         // 0xb8
3104 
         9: polynom = 32'b100010000;                        // 0x110
3105 
        10: polynom = 32'b1001000000;                       // 0x240
3106 
        11: polynom = 32'b10100000000;                      // 0x500
3107 
        12: polynom = 32'b100000101001;                     // 0x829
3108 
        13: polynom = 32'b1000000001100;                    // 0x100C
3109 
        14: polynom = 32'b10000000010101;                   // 0x2015
3110 
        15: polynom = 32'b110000000000000;                  // 0x6000
3111 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3112 
        17: polynom = 32'b10010000000000000;                // 0x12000
3113 
        18: polynom = 32'b100000010000000000;               // 0x20400
3114 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3115 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3116 22 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3117 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3118 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3119 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3120 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3121 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3122 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3123 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3124 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3125 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3126 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3127 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3128 
        default: polynom = 32'b0;
3129 
        endcase
3130 
        lfsr_fb = qi[length];
3131 
        for (i=length-1; i>=1; i=i-1) begin
3132 
            if (polynom[i])
3133 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3134 
        end
3135 
    end
3136 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3137 
 
3138 
   always @ (posedge clk or posedge rst)
3139 
     if (rst)
3140 
       qi <= {length{1'b0}};
3141 
     else
3142 
     if (cke)
3143 
       qi <= q_next;
3144 
 
3145 
   assign q = qi;
3146 
 
3147 
 
3148 
   always @ (posedge clk or posedge rst)
3149 
     if (rst)
3150 
       zq <= 1'b1;
3151 
     else
3152 
     if (cke)
3153 
       zq <= q_next == {length{1'b0}};
3154 
endmodule
3155 40 unneback 
`endif
3156 
`ifdef CNT_LFSR_CE_REW_L1
3157 22 unneback 
//////////////////////////////////////////////////////////////////////
3158 
////                                                              ////
3159 
////  Versatile counter                                           ////
3160 
////                                                              ////
3161 
////  Description                                                 ////
3162 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3163 
////  counter                                                     ////
3164 
////                                                              ////
3165 
////  To Do:                                                      ////
3166 
////   - add LFSR with more taps                                  ////
3167 
////                                                              ////
3168 
////  Author(s):                                                  ////
3169 
////      - Michael Unneback, unneback@opencores.org              ////
3170 
////        ORSoC AB                                              ////
3171 
////                                                              ////
3172 
//////////////////////////////////////////////////////////////////////
3173 
////                                                              ////
3174 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3175 
////                                                              ////
3176 
//// This source file may be used and distributed without         ////
3177 
//// restriction provided that this copyright statement is not    ////
3178 
//// removed from the file and that any derivative work contains  ////
3179 
//// the original copyright notice and the associated disclaimer. ////
3180 
////                                                              ////
3181 
//// This source file is free software; you can redistribute it   ////
3182 
//// and/or modify it under the terms of the GNU Lesser General   ////
3183 
//// Public License as published by the Free Software Foundation; ////
3184 
//// either version 2.1 of the License, or (at your option) any   ////
3185 
//// later version.                                               ////
3186 
////                                                              ////
3187 
//// This source is distributed in the hope that it will be       ////
3188 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3189 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3190 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3191 
//// details.                                                     ////
3192 
////                                                              ////
3193 
//// You should have received a copy of the GNU Lesser General    ////
3194 
//// Public License along with this source; if not, download it   ////
3195 
//// from http://www.opencores.org/lgpl.shtml                     ////
3196 
////                                                              ////
3197 
//////////////////////////////////////////////////////////////////////
3198 6 unneback 
 
3199 
// LFSR counter
3200 
 
3201 40 unneback 
`define MODULE cnt_lfsr_ce_rew_l1
3202 
module `BASE`MODULE (
3203 
`undef MODULE
3204 
 cke, rew, level1, rst, clk);
3205 
 
3206 6 unneback 
   parameter length = 4;
3207 
   input cke;
3208 
   input rew;
3209 
   output reg level1;
3210 
   input rst;
3211 
   input clk;
3212 
 
3213 
   parameter clear_value = 0;
3214 
   parameter set_value = 1;
3215 
   parameter wrap_value = 8;
3216 
   parameter level1_value = 15;
3217 
 
3218 29 unneback 
   wire clear;
3219 30 unneback 
   assign clear = 1'b0;
3220 6 unneback 
   reg  [length:1] qi;
3221 
   reg lfsr_fb, lfsr_fb_rew;
3222 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
3223 
   reg [32:1] polynom_rew;
3224 
   integer j;
3225 
   reg [32:1] polynom;
3226 
   integer i;
3227 
 
3228 
   always @ (qi)
3229 
   begin
3230 
        case (length)
3231 
         2: polynom = 32'b11;                               // 0x3
3232 
         3: polynom = 32'b110;                              // 0x6
3233 
         4: polynom = 32'b1100;                             // 0xC
3234 
         5: polynom = 32'b10100;                            // 0x14
3235 
         6: polynom = 32'b110000;                           // 0x30
3236 
         7: polynom = 32'b1100000;                          // 0x60
3237 
         8: polynom = 32'b10111000;                         // 0xb8
3238 
         9: polynom = 32'b100010000;                        // 0x110
3239 
        10: polynom = 32'b1001000000;                       // 0x240
3240 
        11: polynom = 32'b10100000000;                      // 0x500
3241 
        12: polynom = 32'b100000101001;                     // 0x829
3242 
        13: polynom = 32'b1000000001100;                    // 0x100C
3243 
        14: polynom = 32'b10000000010101;                   // 0x2015
3244 
        15: polynom = 32'b110000000000000;                  // 0x6000
3245 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3246 
        17: polynom = 32'b10010000000000000;                // 0x12000
3247 
        18: polynom = 32'b100000010000000000;               // 0x20400
3248 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3249 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3250 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3251 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3252 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3253 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3254 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3255 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3256 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3257 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3258 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3259 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3260 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3261 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3262 
        default: polynom = 32'b0;
3263 
        endcase
3264 
        lfsr_fb = qi[length];
3265 
        for (i=length-1; i>=1; i=i-1) begin
3266 
            if (polynom[i])
3267 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3268 
        end
3269 
    end
3270 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3271 
   always @ (qi)
3272 
   begin
3273 
        case (length)
3274 
         2: polynom_rew = 32'b11;
3275 
         3: polynom_rew = 32'b110;
3276 
         4: polynom_rew = 32'b1100;
3277 
         5: polynom_rew = 32'b10100;
3278 
         6: polynom_rew = 32'b110000;
3279 
         7: polynom_rew = 32'b1100000;
3280 
         8: polynom_rew = 32'b10111000;
3281 
         9: polynom_rew = 32'b100010000;
3282 
        10: polynom_rew = 32'b1001000000;
3283 
        11: polynom_rew = 32'b10100000000;
3284 
        12: polynom_rew = 32'b100000101001;
3285 
        13: polynom_rew = 32'b1000000001100;
3286 
        14: polynom_rew = 32'b10000000010101;
3287 
        15: polynom_rew = 32'b110000000000000;
3288 
        16: polynom_rew = 32'b1101000000001000;
3289 
        17: polynom_rew = 32'b10010000000000000;
3290 
        18: polynom_rew = 32'b100000010000000000;
3291 
        19: polynom_rew = 32'b1000000000000100011;
3292 
        20: polynom_rew = 32'b10000010000000000000;
3293 
        21: polynom_rew = 32'b101000000000000000000;
3294 
        22: polynom_rew = 32'b1100000000000000000000;
3295 
        23: polynom_rew = 32'b10000100000000000000000;
3296 
        24: polynom_rew = 32'b111000010000000000000000;
3297 
        25: polynom_rew = 32'b1001000000000000000000000;
3298 
        26: polynom_rew = 32'b10000000000000000000100011;
3299 
        27: polynom_rew = 32'b100000000000000000000010011;
3300 
        28: polynom_rew = 32'b1100100000000000000000000000;
3301 
        29: polynom_rew = 32'b10100000000000000000000000000;
3302 
        30: polynom_rew = 32'b100000000000000000000000101001;
3303 
        31: polynom_rew = 32'b1001000000000000000000000000000;
3304 
        32: polynom_rew = 32'b10000000001000000000000000000011;
3305 
        default: polynom_rew = 32'b0;
3306 
        endcase
3307 
        // rotate left
3308 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3309 
        lfsr_fb_rew = qi[length];
3310 
        for (i=length-1; i>=1; i=i-1) begin
3311 
            if (polynom_rew[i])
3312 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3313 
        end
3314 
    end
3315 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3316 
   assign q_next = rew ? q_next_rew : q_next_fw;
3317 
 
3318 
   always @ (posedge clk or posedge rst)
3319 
     if (rst)
3320 
       qi <= {length{1'b0}};
3321 
     else
3322 
     if (cke)
3323 
       qi <= q_next;
3324 
 
3325 
 
3326 
 
3327 
    always @ (posedge clk or posedge rst)
3328 
    if (rst)
3329 
        level1 <= 1'b0;
3330 
    else
3331 
    if (cke)
3332 29 unneback 
    if (clear)
3333 
        level1 <= 1'b0;
3334 
    else if (q_next == level1_value)
3335 6 unneback 
        level1 <= 1'b1;
3336 
    else if (qi == level1_value & rew)
3337 
        level1 <= 1'b0;
3338 
endmodule
3339 40 unneback 
`endif
3340 
`ifdef CNT_GRAY
3341 6 unneback 
//////////////////////////////////////////////////////////////////////
3342 
////                                                              ////
3343 
////  Versatile counter                                           ////
3344 
////                                                              ////
3345 
////  Description                                                 ////
3346 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3347 
////  counter                                                     ////
3348 
////                                                              ////
3349 
////  To Do:                                                      ////
3350 
////   - add LFSR with more taps                                  ////
3351 
////                                                              ////
3352 
////  Author(s):                                                  ////
3353 
////      - Michael Unneback, unneback@opencores.org              ////
3354 
////        ORSoC AB                                              ////
3355 
////                                                              ////
3356 
//////////////////////////////////////////////////////////////////////
3357 
////                                                              ////
3358 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3359 
////                                                              ////
3360 
//// This source file may be used and distributed without         ////
3361 
//// restriction provided that this copyright statement is not    ////
3362 
//// removed from the file and that any derivative work contains  ////
3363 
//// the original copyright notice and the associated disclaimer. ////
3364 
////                                                              ////
3365 
//// This source file is free software; you can redistribute it   ////
3366 
//// and/or modify it under the terms of the GNU Lesser General   ////
3367 
//// Public License as published by the Free Software Foundation; ////
3368 
//// either version 2.1 of the License, or (at your option) any   ////
3369 
//// later version.                                               ////
3370 
////                                                              ////
3371 
//// This source is distributed in the hope that it will be       ////
3372 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3373 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3374 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3375 
//// details.                                                     ////
3376 
////                                                              ////
3377 
//// You should have received a copy of the GNU Lesser General    ////
3378 
//// Public License along with this source; if not, download it   ////
3379 
//// from http://www.opencores.org/lgpl.shtml                     ////
3380 
////                                                              ////
3381 
//////////////////////////////////////////////////////////////////////
3382 
 
3383 
// GRAY counter
3384 
 
3385 40 unneback 
`define MODULE cnt_gray
3386 
module `BASE`MODULE (
3387 
`undef MODULE
3388 
 q, rst, clk);
3389 
 
3390 6 unneback 
   parameter length = 4;
3391 
   output reg [length:1] q;
3392 
   input rst;
3393 
   input clk;
3394 
 
3395 
   parameter clear_value = 0;
3396 
   parameter set_value = 1;
3397 
   parameter wrap_value = 8;
3398 
   parameter level1_value = 15;
3399 
 
3400 
   reg  [length:1] qi;
3401 
   wire [length:1] q_next;
3402 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3403 
 
3404 
   always @ (posedge clk or posedge rst)
3405 
     if (rst)
3406 
       qi <= {length{1'b0}};
3407 
     else
3408 
       qi <= q_next;
3409 
 
3410 
   always @ (posedge clk or posedge rst)
3411 
     if (rst)
3412 
       q <= {length{1'b0}};
3413 
     else
3414 
         q <= (q_next>>1) ^ q_next;
3415 
 
3416 
endmodule
3417 40 unneback 
`endif
3418 
`ifdef CNT_GRAY_CE
3419 6 unneback 
//////////////////////////////////////////////////////////////////////
3420 
////                                                              ////
3421 
////  Versatile counter                                           ////
3422 
////                                                              ////
3423 
////  Description                                                 ////
3424 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3425 
////  counter                                                     ////
3426 
////                                                              ////
3427 
////  To Do:                                                      ////
3428 
////   - add LFSR with more taps                                  ////
3429 
////                                                              ////
3430 
////  Author(s):                                                  ////
3431 
////      - Michael Unneback, unneback@opencores.org              ////
3432 
////        ORSoC AB                                              ////
3433 
////                                                              ////
3434 
//////////////////////////////////////////////////////////////////////
3435 
////                                                              ////
3436 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3437 
////                                                              ////
3438 
//// This source file may be used and distributed without         ////
3439 
//// restriction provided that this copyright statement is not    ////
3440 
//// removed from the file and that any derivative work contains  ////
3441 
//// the original copyright notice and the associated disclaimer. ////
3442 
////                                                              ////
3443 
//// This source file is free software; you can redistribute it   ////
3444 
//// and/or modify it under the terms of the GNU Lesser General   ////
3445 
//// Public License as published by the Free Software Foundation; ////
3446 
//// either version 2.1 of the License, or (at your option) any   ////
3447 
//// later version.                                               ////
3448 
////                                                              ////
3449 
//// This source is distributed in the hope that it will be       ////
3450 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3451 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3452 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3453 
//// details.                                                     ////
3454 
////                                                              ////
3455 
//// You should have received a copy of the GNU Lesser General    ////
3456 
//// Public License along with this source; if not, download it   ////
3457 
//// from http://www.opencores.org/lgpl.shtml                     ////
3458 
////                                                              ////
3459 
//////////////////////////////////////////////////////////////////////
3460 
 
3461 
// GRAY counter
3462 
 
3463 40 unneback 
`define MODULE cnt_gray_ce
3464 
module `BASE`MODULE (
3465 
`undef MODULE
3466 
 cke, q, rst, clk);
3467 
 
3468 6 unneback 
   parameter length = 4;
3469 
   input cke;
3470 
   output reg [length:1] q;
3471 
   input rst;
3472 
   input clk;
3473 
 
3474 
   parameter clear_value = 0;
3475 
   parameter set_value = 1;
3476 
   parameter wrap_value = 8;
3477 
   parameter level1_value = 15;
3478 
 
3479 
   reg  [length:1] qi;
3480 
   wire [length:1] q_next;
3481 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3482 
 
3483 
   always @ (posedge clk or posedge rst)
3484 
     if (rst)
3485 
       qi <= {length{1'b0}};
3486 
     else
3487 
     if (cke)
3488 
       qi <= q_next;
3489 
 
3490 
   always @ (posedge clk or posedge rst)
3491 
     if (rst)
3492 
       q <= {length{1'b0}};
3493 
     else
3494 
       if (cke)
3495 
         q <= (q_next>>1) ^ q_next;
3496 
 
3497 
endmodule
3498 40 unneback 
`endif
3499 
`ifdef CNT_GRAY_CE_BIN
3500 6 unneback 
//////////////////////////////////////////////////////////////////////
3501 
////                                                              ////
3502 
////  Versatile counter                                           ////
3503 
////                                                              ////
3504 
////  Description                                                 ////
3505 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3506 
////  counter                                                     ////
3507 
////                                                              ////
3508 
////  To Do:                                                      ////
3509 
////   - add LFSR with more taps                                  ////
3510 
////                                                              ////
3511 
////  Author(s):                                                  ////
3512 
////      - Michael Unneback, unneback@opencores.org              ////
3513 
////        ORSoC AB                                              ////
3514 
////                                                              ////
3515 
//////////////////////////////////////////////////////////////////////
3516 
////                                                              ////
3517 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3518 
////                                                              ////
3519 
//// This source file may be used and distributed without         ////
3520 
//// restriction provided that this copyright statement is not    ////
3521 
//// removed from the file and that any derivative work contains  ////
3522 
//// the original copyright notice and the associated disclaimer. ////
3523 
////                                                              ////
3524 
//// This source file is free software; you can redistribute it   ////
3525 
//// and/or modify it under the terms of the GNU Lesser General   ////
3526 
//// Public License as published by the Free Software Foundation; ////
3527 
//// either version 2.1 of the License, or (at your option) any   ////
3528 
//// later version.                                               ////
3529 
////                                                              ////
3530 
//// This source is distributed in the hope that it will be       ////
3531 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3532 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3533 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3534 
//// details.                                                     ////
3535 
////                                                              ////
3536 
//// You should have received a copy of the GNU Lesser General    ////
3537 
//// Public License along with this source; if not, download it   ////
3538 
//// from http://www.opencores.org/lgpl.shtml                     ////
3539 
////                                                              ////
3540 
//////////////////////////////////////////////////////////////////////
3541 
 
3542 
// GRAY counter
3543 
 
3544 40 unneback 
`define MODULE cnt_gray_ce_bin
3545 
module `BASE`MODULE (
3546 
`undef MODULE
3547 
 cke, q, q_bin, rst, clk);
3548 
 
3549 6 unneback 
   parameter length = 4;
3550 
   input cke;
3551 
   output reg [length:1] q;
3552 
   output [length:1] q_bin;
3553 
   input rst;
3554 
   input clk;
3555 
 
3556 
   parameter clear_value = 0;
3557 
   parameter set_value = 1;
3558 
   parameter wrap_value = 8;
3559 
   parameter level1_value = 15;
3560 
 
3561 
   reg  [length:1] qi;
3562 
   wire [length:1] q_next;
3563 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3564 
 
3565 
   always @ (posedge clk or posedge rst)
3566 
     if (rst)
3567 
       qi <= {length{1'b0}};
3568 
     else
3569 
     if (cke)
3570 
       qi <= q_next;
3571 
 
3572 
   always @ (posedge clk or posedge rst)
3573 
     if (rst)
3574 
       q <= {length{1'b0}};
3575 
     else
3576 
       if (cke)
3577 
         q <= (q_next>>1) ^ q_next;
3578 
 
3579 
   assign q_bin = qi;
3580 
 
3581 
endmodule
3582 40 unneback 
`endif
3583 6 unneback 
//////////////////////////////////////////////////////////////////////
3584 
////                                                              ////
3585 
////  Versatile library, counters                                 ////
3586 
////                                                              ////
3587 
////  Description                                                 ////
3588 
////  counters                                                    ////
3589 
////                                                              ////
3590 
////                                                              ////
3591 
////  To Do:                                                      ////
3592 
////   - add more counters                                        ////
3593 
////                                                              ////
3594 
////  Author(s):                                                  ////
3595 
////      - Michael Unneback, unneback@opencores.org              ////
3596 
////        ORSoC AB                                              ////
3597 
////                                                              ////
3598 
//////////////////////////////////////////////////////////////////////
3599 
////                                                              ////
3600 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3601 
////                                                              ////
3602 
//// This source file may be used and distributed without         ////
3603 
//// restriction provided that this copyright statement is not    ////
3604 
//// removed from the file and that any derivative work contains  ////
3605 
//// the original copyright notice and the associated disclaimer. ////
3606 
////                                                              ////
3607 
//// This source file is free software; you can redistribute it   ////
3608 
//// and/or modify it under the terms of the GNU Lesser General   ////
3609 
//// Public License as published by the Free Software Foundation; ////
3610 
//// either version 2.1 of the License, or (at your option) any   ////
3611 
//// later version.                                               ////
3612 
////                                                              ////
3613 
//// This source is distributed in the hope that it will be       ////
3614 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3615 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3616 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3617 
//// details.                                                     ////
3618 
////                                                              ////
3619 
//// You should have received a copy of the GNU Lesser General    ////
3620 
//// Public License along with this source; if not, download it   ////
3621 
//// from http://www.opencores.org/lgpl.shtml                     ////
3622 
////                                                              ////
3623 
//////////////////////////////////////////////////////////////////////
3624 
 
3625 40 unneback 
`ifdef CNT_SHREG_WRAP
3626 
`define MODULE cnt_shreg_wrap
3627 
module `BASE`MODULE ( q, rst, clk);
3628 
`undef MODULE
3629 6 unneback 
 
3630 
   parameter length = 4;
3631 
   output reg [0:length-1] q;
3632 
   input rst;
3633 
   input clk;
3634 
 
3635 
    always @ (posedge clk or posedge rst)
3636 
    if (rst)
3637 
        q <= {1'b1,{length-1{1'b0}}};
3638 
    else
3639 
        q <= {q[length-1],q[0:length-2]};
3640 
 
3641 
endmodule
3642 40 unneback 
`endif
3643 6 unneback 
 
3644 40 unneback 
`ifdef CNT_SHREG_CE_WRAP
3645 
`define MODULE cnt_shreg_ce_wrap
3646 
module `BASE`MODULE ( cke, q, rst, clk);
3647 
`undef MODULE
3648 6 unneback 
 
3649 
   parameter length = 4;
3650 
   input cke;
3651 
   output reg [0:length-1] q;
3652 
   input rst;
3653 
   input clk;
3654 
 
3655 
    always @ (posedge clk or posedge rst)
3656 
    if (rst)
3657 
        q <= {1'b1,{length-1{1'b0}}};
3658 
    else
3659 
        if (cke)
3660 
            q <= {q[length-1],q[0:length-2]};
3661 
 
3662 
endmodule
3663 40 unneback 
`endif
3664 6 unneback 
 
3665 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR
3666 
`define MODULE cnt_shreg_ce_clear
3667 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3668 
`undef MODULE
3669 6 unneback 
 
3670 
   parameter length = 4;
3671 
   input cke, clear;
3672 
   output reg [0:length-1] q;
3673 
   input rst;
3674 
   input clk;
3675 
 
3676 
    always @ (posedge clk or posedge rst)
3677 
    if (rst)
3678 
        q <= {1'b1,{length-1{1'b0}}};
3679 
    else
3680 
        if (cke)
3681 
            if (clear)
3682 
                q <= {1'b1,{length-1{1'b0}}};
3683 
            else
3684 
                q <= q >> 1;
3685 
 
3686 
endmodule
3687 40 unneback 
`endif
3688 6 unneback 
 
3689 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3690 
`define MODULE cnt_shreg_ce_clear_wrap
3691 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3692 
`undef MODULE
3693 6 unneback 
 
3694 
   parameter length = 4;
3695 
   input cke, clear;
3696 
   output reg [0:length-1] q;
3697 
   input rst;
3698 
   input clk;
3699 
 
3700 
    always @ (posedge clk or posedge rst)
3701 
    if (rst)
3702 
        q <= {1'b1,{length-1{1'b0}}};
3703 
    else
3704 
        if (cke)
3705 
            if (clear)
3706 
                q <= {1'b1,{length-1{1'b0}}};
3707 
            else
3708 
            q <= {q[length-1],q[0:length-2]};
3709 
 
3710 
endmodule
3711 40 unneback 
`endif
3712 6 unneback 
//////////////////////////////////////////////////////////////////////
3713 
////                                                              ////
3714 
////  Versatile library, memories                                 ////
3715 
////                                                              ////
3716 
////  Description                                                 ////
3717 
////  memories                                                    ////
3718 
////                                                              ////
3719 
////                                                              ////
3720 
////  To Do:                                                      ////
3721 
////   - add more memory types                                    ////
3722 
////                                                              ////
3723 
////  Author(s):                                                  ////
3724 
////      - Michael Unneback, unneback@opencores.org              ////
3725 
////        ORSoC AB                                              ////
3726 
////                                                              ////
3727 
//////////////////////////////////////////////////////////////////////
3728 
////                                                              ////
3729 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3730 
////                                                              ////
3731 
//// This source file may be used and distributed without         ////
3732 
//// restriction provided that this copyright statement is not    ////
3733 
//// removed from the file and that any derivative work contains  ////
3734 
//// the original copyright notice and the associated disclaimer. ////
3735 
////                                                              ////
3736 
//// This source file is free software; you can redistribute it   ////
3737 
//// and/or modify it under the terms of the GNU Lesser General   ////
3738 
//// Public License as published by the Free Software Foundation; ////
3739 
//// either version 2.1 of the License, or (at your option) any   ////
3740 
//// later version.                                               ////
3741 
////                                                              ////
3742 
//// This source is distributed in the hope that it will be       ////
3743 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3744 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3745 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3746 
//// details.                                                     ////
3747 
////                                                              ////
3748 
//// You should have received a copy of the GNU Lesser General    ////
3749 
//// Public License along with this source; if not, download it   ////
3750 
//// from http://www.opencores.org/lgpl.shtml                     ////
3751 
////                                                              ////
3752 
//////////////////////////////////////////////////////////////////////
3753 
 
3754 40 unneback 
`ifdef ROM_INIT
3755 6 unneback 
/// ROM
3756 40 unneback 
`define MODULE rom_init
3757 
module `BASE`MODULE ( adr, q, clk);
3758 
`undef MODULE
3759 6 unneback 
 
3760 7 unneback 
   parameter data_width = 32;
3761 
   parameter addr_width = 8;
3762 75 unneback 
   parameter mem_size = 1<<addr_width;
3763 7 unneback 
   input [(addr_width-1):0]       adr;
3764 
   output reg [(data_width-1):0] q;
3765 
   input                         clk;
3766 75 unneback 
   reg [data_width-1:0] rom [mem_size-1:0];
3767 7 unneback 
   parameter memory_file = "vl_rom.vmem";
3768 
   initial
3769 
     begin
3770 
        $readmemh(memory_file, rom);
3771 
     end
3772 
 
3773 
   always @ (posedge clk)
3774 
     q <= rom[adr];
3775 6 unneback 
 
3776 7 unneback 
endmodule
3777 40 unneback 
`endif
3778 7 unneback 
 
3779 40 unneback 
`ifdef RAM
3780 
`define MODULE ram
3781 6 unneback 
// Single port RAM
3782 40 unneback 
module `BASE`MODULE ( d, adr, we, q, clk);
3783 
`undef MODULE
3784 6 unneback 
 
3785 
   parameter data_width = 32;
3786 
   parameter addr_width = 8;
3787 75 unneback 
   parameter mem_size = 1<<addr_width;
3788 6 unneback 
   input [(data_width-1):0]      d;
3789 
   input [(addr_width-1):0]       adr;
3790 
   input                         we;
3791 7 unneback 
   output reg [(data_width-1):0] q;
3792 6 unneback 
   input                         clk;
3793 98 unneback 
   reg [data_width-1:0] ram [mem_size-1:0];
3794 7 unneback 
   parameter init = 0;
3795 
   parameter memory_file = "vl_ram.vmem";
3796 
   generate if (init) begin : init_mem
3797 
   initial
3798 
     begin
3799 
        $readmemh(memory_file, ram);
3800 
     end
3801 
   end
3802 
   endgenerate
3803 
 
3804 6 unneback 
   always @ (posedge clk)
3805 
   begin
3806 
   if (we)
3807 
     ram[adr] <= d;
3808 
   q <= ram[adr];
3809 
   end
3810 
 
3811 
endmodule
3812 40 unneback 
`endif
3813 6 unneback 
 
3814 40 unneback 
`ifdef RAM_BE
3815 
`define MODULE ram_be
3816 91 unneback 
module `BASE`MODULE ( d, adr, be, we, q, clk);
3817 40 unneback 
`undef MODULE
3818 
 
3819 7 unneback 
   parameter data_width = 32;
3820 72 unneback 
   parameter addr_width = 6;
3821 75 unneback 
   parameter mem_size = 1<<addr_width;
3822 7 unneback 
   input [(data_width-1):0]      d;
3823 
   input [(addr_width-1):0]       adr;
3824 73 unneback 
   input [(data_width/8)-1:0]    be;
3825 7 unneback 
   input                         we;
3826 
   output reg [(data_width-1):0] q;
3827 
   input                         clk;
3828 
 
3829 85 unneback 
 
3830 65 unneback 
`ifdef SYSTEMVERILOG
3831 95 unneback 
    // use a multi-dimensional packed array
3832 
    //t o model individual bytes within the word
3833 
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
3834 65 unneback 
`else
3835 85 unneback 
    reg [data_width-1:0] ram [mem_size-1:0];
3836 
    wire [data_width/8-1:0] cke;
3837 65 unneback 
`endif
3838 
 
3839 60 unneback 
   parameter memory_init = 0;
3840 7 unneback 
   parameter memory_file = "vl_ram.vmem";
3841 60 unneback 
   generate if (memory_init) begin : init_mem
3842 7 unneback 
   initial
3843 
     begin
3844 
        $readmemh(memory_file, ram);
3845 
     end
3846 
   end
3847 
   endgenerate
3848 
 
3849 60 unneback 
`ifdef SYSTEMVERILOG
3850 
 
3851 
always_ff@(posedge clk)
3852 
begin
3853 95 unneback 
    if(we) begin
3854 86 unneback 
        if(be[3]) ram[adr][3] <= d[31:24];
3855 
        if(be[2]) ram[adr][2] <= d[23:16];
3856 
        if(be[1]) ram[adr][1] <= d[15:8];
3857 
        if(be[0]) ram[adr][0] <= d[7:0];
3858 60 unneback 
    end
3859 90 unneback 
        q <= ram[adr];
3860 60 unneback 
end
3861 
 
3862 
`else
3863 
 
3864 85 unneback 
assign cke = {data_width/8{we}} & be;
3865 7 unneback 
   genvar i;
3866 85 unneback 
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
3867 7 unneback 
      always @ (posedge clk)
3868 85 unneback 
      if (cke[i])
3869 7 unneback 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3870 
   end
3871 
   endgenerate
3872 
 
3873 
   always @ (posedge clk)
3874 
      q <= ram[adr];
3875 
 
3876 60 unneback 
`endif
3877 
 
3878 93 unneback 
`ifdef verilator
3879 85 unneback 
   // Function to access RAM (for use by Verilator).
3880 
   function [31:0] get_mem;
3881 
      // verilator public
3882 90 unneback 
      input [addr_width-1:0]             addr;
3883 85 unneback 
      get_mem = ram[addr];
3884 
   endfunction // get_mem
3885 
 
3886 
   // Function to write RAM (for use by Verilator).
3887 
   function set_mem;
3888 
      // verilator public
3889 90 unneback 
      input [addr_width-1:0]             addr;
3890 
      input [data_width-1:0]             data;
3891 85 unneback 
      ram[addr] = data;
3892 
   endfunction // set_mem
3893 93 unneback 
`endif
3894 85 unneback 
 
3895 7 unneback 
endmodule
3896 40 unneback 
`endif
3897 7 unneback 
 
3898 40 unneback 
`ifdef DPRAM_1R1W
3899 
`define MODULE dpram_1r1w
3900 
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3901 
`undef MODULE
3902 6 unneback 
   parameter data_width = 32;
3903 
   parameter addr_width = 8;
3904 75 unneback 
   parameter mem_size = 1<<addr_width;
3905 6 unneback 
   input [(data_width-1):0]      d_a;
3906 
   input [(addr_width-1):0]       adr_a;
3907 
   input [(addr_width-1):0]       adr_b;
3908 
   input                         we_a;
3909 
   output [(data_width-1):0]      q_b;
3910 
   input                         clk_a, clk_b;
3911 
   reg [(addr_width-1):0]         adr_b_reg;
3912 98 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
3913 7 unneback 
 
3914 
   parameter init = 0;
3915 
   parameter memory_file = "vl_ram.vmem";
3916 
   generate if (init) begin : init_mem
3917 
   initial
3918 
     begin
3919 
        $readmemh(memory_file, ram);
3920 
     end
3921 
   end
3922 
   endgenerate
3923 
 
3924 6 unneback 
   always @ (posedge clk_a)
3925 
   if (we_a)
3926 
     ram[adr_a] <= d_a;
3927 
   always @ (posedge clk_b)
3928 
   adr_b_reg <= adr_b;
3929 
   assign q_b = ram[adr_b_reg];
3930 40 unneback 
 
3931 6 unneback 
endmodule
3932 40 unneback 
`endif
3933 6 unneback 
 
3934 40 unneback 
`ifdef DPRAM_2R1W
3935 
`define MODULE dpram_2r1w
3936 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3937 
`undef MODULE
3938 
 
3939 6 unneback 
   parameter data_width = 32;
3940 
   parameter addr_width = 8;
3941 75 unneback 
   parameter mem_size = 1<<addr_width;
3942 6 unneback 
   input [(data_width-1):0]      d_a;
3943 
   input [(addr_width-1):0]       adr_a;
3944 
   input [(addr_width-1):0]       adr_b;
3945 
   input                         we_a;
3946 
   output [(data_width-1):0]      q_b;
3947 
   output reg [(data_width-1):0] q_a;
3948 
   input                         clk_a, clk_b;
3949 
   reg [(data_width-1):0]         q_b;
3950 98 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
3951 7 unneback 
 
3952 
   parameter init = 0;
3953 
   parameter memory_file = "vl_ram.vmem";
3954 
   generate if (init) begin : init_mem
3955 
   initial
3956 
     begin
3957 
        $readmemh(memory_file, ram);
3958 
     end
3959 
   end
3960 
   endgenerate
3961 
 
3962 6 unneback 
   always @ (posedge clk_a)
3963 
     begin
3964 
        q_a <= ram[adr_a];
3965 
        if (we_a)
3966 
             ram[adr_a] <= d_a;
3967 
     end
3968 
   always @ (posedge clk_b)
3969 
          q_b <= ram[adr_b];
3970 
endmodule
3971 40 unneback 
`endif
3972 6 unneback 
 
3973 40 unneback 
`ifdef DPRAM_2R2W
3974 
`define MODULE dpram_2r2w
3975 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3976 
`undef MODULE
3977 
 
3978 6 unneback 
   parameter data_width = 32;
3979 
   parameter addr_width = 8;
3980 75 unneback 
   parameter mem_size = 1<<addr_width;
3981 6 unneback 
   input [(data_width-1):0]      d_a;
3982 
   input [(addr_width-1):0]       adr_a;
3983 
   input [(addr_width-1):0]       adr_b;
3984 
   input                         we_a;
3985 
   output [(data_width-1):0]      q_b;
3986 
   input [(data_width-1):0]       d_b;
3987 
   output reg [(data_width-1):0] q_a;
3988 
   input                         we_b;
3989 
   input                         clk_a, clk_b;
3990 
   reg [(data_width-1):0]         q_b;
3991 98 unneback 
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
3992 7 unneback 
 
3993 
   parameter init = 0;
3994 
   parameter memory_file = "vl_ram.vmem";
3995 
   generate if (init) begin : init_mem
3996 
   initial
3997 
     begin
3998 
        $readmemh(memory_file, ram);
3999 
     end
4000 
   end
4001 
   endgenerate
4002 
 
4003 6 unneback 
   always @ (posedge clk_a)
4004 
     begin
4005 
        q_a <= ram[adr_a];
4006 
        if (we_a)
4007 
             ram[adr_a] <= d_a;
4008 
     end
4009 
   always @ (posedge clk_b)
4010 
     begin
4011 
        q_b <= ram[adr_b];
4012 
        if (we_b)
4013 
          ram[adr_b] <= d_b;
4014 
     end
4015 
endmodule
4016 40 unneback 
`endif
4017 6 unneback 
 
4018 83 unneback 
 
4019 75 unneback 
`ifdef DPRAM_BE_2R2W
4020 
`define MODULE dpram_be_2r2w
4021 92 unneback 
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
4022 75 unneback 
`undef MODULE
4023 
 
4024 
   parameter a_data_width = 32;
4025 
   parameter a_addr_width = 8;
4026 95 unneback 
   parameter b_data_width = 64; //a_data_width;
4027 91 unneback 
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
4028 95 unneback 
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
4029 
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
4030 91 unneback 
 
4031 95 unneback 
   parameter init = 0;
4032 
   parameter memory_file = "vl_ram.vmem";
4033 
 
4034 75 unneback 
   input [(a_data_width-1):0]      d_a;
4035 91 unneback 
   input [(a_addr_width-1):0]       adr_a;
4036 
   input [(a_data_width/8-1):0]    be_a;
4037 
   input                           we_a;
4038 75 unneback 
   output reg [(a_data_width-1):0] q_a;
4039 91 unneback 
   input [(b_data_width-1):0]       d_b;
4040 
   input [(b_addr_width-1):0]       adr_b;
4041 92 unneback 
   input [(b_data_width/8-1):0]    be_b;
4042 
   input                           we_b;
4043 
   output reg [(b_data_width-1):0]          q_b;
4044 91 unneback 
   input                           clk_a, clk_b;
4045 75 unneback 
 
4046 91 unneback 
`ifdef SYSTEMVERILOG
4047 
// use a multi-dimensional packed array
4048 
//to model individual bytes within the word
4049 
 
4050 75 unneback 
generate
4051 91 unneback 
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
4052 75 unneback 
 
4053 98 unneback 
    logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4054 95 unneback 
 
4055 
    initial
4056 
        if (init)
4057 
            $readmemh(memory_file, ram);
4058 91 unneback 
 
4059 
    always_ff@(posedge clk_a)
4060 
    begin
4061 
        if(we_a) begin
4062 
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
4063 
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
4064 
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
4065 
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
4066 
        end
4067 
    end
4068 
 
4069 92 unneback 
    always@(posedge clk_a)
4070 
        q_a = ram[adr_a];
4071 91 unneback 
 
4072 
    always_ff@(posedge clk_b)
4073 92 unneback 
    begin
4074 
        if(we_b) begin
4075 
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
4076 
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
4077 
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
4078 
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
4079 
        end
4080 
    end
4081 91 unneback 
 
4082 92 unneback 
    always@(posedge clk_b)
4083 
        q_b = ram[adr_b];
4084 91 unneback 
 
4085 75 unneback 
end
4086 
endgenerate
4087 
 
4088 95 unneback 
generate
4089 
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
4090 
 
4091 98 unneback 
    logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4092 95 unneback 
 
4093 
    initial
4094 
        if (init)
4095 
            $readmemh(memory_file, ram);
4096 
 
4097 
    always_ff@(posedge clk_a)
4098 
    begin
4099 
        if(we_a) begin
4100 
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
4101 
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
4102 
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
4103 
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
4104 
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
4105 
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
4106 
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
4107 
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
4108 
        end
4109 
    end
4110 
 
4111 
    always@(posedge clk_a)
4112 
        q_a = ram[adr_a];
4113 
 
4114 
    always_ff@(posedge clk_b)
4115 
    begin
4116 
        if(we_b) begin
4117 
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
4118 
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
4119 
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
4120 
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
4121 
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
4122 
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
4123 
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
4124 
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
4125 
        end
4126 
    end
4127 
 
4128 
    always@(posedge clk_b)
4129 
        q_b = ram[adr_b];
4130 
 
4131 
end
4132 
endgenerate
4133 
 
4134 
generate
4135 
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
4136 
logic [31:0] temp;
4137 
`define MODULE dpram_be_2r2w
4138 
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
4139 
`undef MODULE
4140 
dpram6464 (
4141 
    .d_a(d_a),
4142 
    .q_a(q_a),
4143 
    .adr_a(adr_a),
4144 
    .be_a(be_a),
4145 
    .we_a(we_a),
4146 
    .clk_a(clk_a),
4147 
    .d_b({d_b,d_b}),
4148 
    .q_b(temp),
4149 
    .adr_b(adr_b),
4150 
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
4151 
    .we_b(we_b),
4152 
    .clk_b(clk_b)
4153 
);
4154 
 
4155 
always_comb
4156 
    if (adr_b[0])
4157 
        q_b = temp[31:16];
4158 
    else
4159 
        q_b = temp[15:0];
4160 
 
4161 
end
4162 
endgenerate
4163 
 
4164 
generate
4165 
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
4166 
logic [63:0] temp;
4167 
`define MODULE dpram_be_2r2w
4168 
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
4169 
`undef MODULE
4170 
dpram6464 (
4171 
    .d_a({d_a,d_a}),
4172 
    .q_a(temp),
4173 
    .adr_a(adr_a[a_addr_width-1:1]),
4174 
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
4175 
    .we_a(we_a),
4176 
    .clk_a(clk_a),
4177 
    .d_b(d_b),
4178 
    .q_b(q_b),
4179 
    .adr_b(adr_b),
4180 
    .be_b(be_b),
4181 
    .we_b(we_b),
4182 
    .clk_b(clk_b)
4183 
);
4184 
 
4185 
always_comb
4186 
    if (adr_a[0])
4187 
        q_a = temp[63:32];
4188 
    else
4189 
        q_a = temp[31:0];
4190 
 
4191 
end
4192 
endgenerate
4193 
 
4194 91 unneback 
`else
4195 92 unneback 
    // This modules requires SystemVerilog
4196 98 unneback 
    // at this point anyway
4197 91 unneback 
`endif
4198 75 unneback 
endmodule
4199 
`endif
4200 
 
4201 91 unneback 
`ifdef CAM
4202 6 unneback 
// Content addresable memory, CAM
4203 91 unneback 
`endif
4204 6 unneback 
 
4205 40 unneback 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
4206 6 unneback 
// FIFO
4207 40 unneback 
`define MODULE fifo_1r1w_fill_level_sync
4208 
module `BASE`MODULE (
4209 
`undef MODULE
4210 25 unneback 
    d, wr, fifo_full,
4211 
    q, rd, fifo_empty,
4212 
    fill_level,
4213 
    clk, rst
4214 
    );
4215 
 
4216 
parameter data_width = 18;
4217 
parameter addr_width = 4;
4218 6 unneback 
 
4219 25 unneback 
// write side
4220 
input  [data_width-1:0] d;
4221 
input                   wr;
4222 
output                  fifo_full;
4223 
// read side
4224 
output [data_width-1:0] q;
4225 
input                   rd;
4226 
output                  fifo_empty;
4227 
// common
4228 
output [addr_width:0]   fill_level;
4229 
input rst, clk;
4230 
 
4231 
wire [addr_width:1] wadr, radr;
4232 
 
4233 40 unneback 
`define MODULE cnt_bin_ce
4234 
`BASE`MODULE
4235 25 unneback 
    # ( .length(addr_width))
4236 
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
4237 40 unneback 
`BASE`MODULE
4238 25 unneback 
    # (.length(addr_width))
4239 
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
4240 40 unneback 
`undef MODULE
4241 25 unneback 
 
4242 40 unneback 
`define MODULE dpram_1r1w
4243 
`BASE`MODULE
4244 25 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4245 
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
4246 40 unneback 
`undef MODULE
4247 25 unneback 
 
4248 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
4249 
`BASE`MODULE
4250 27 unneback 
    # (.length(addr_width+1), .level1_value(1<<addr_width))
4251 25 unneback 
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
4252 40 unneback 
`undef MODULE
4253 25 unneback 
endmodule
4254 40 unneback 
`endif
4255 25 unneback 
 
4256 40 unneback 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
4257 27 unneback 
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
4258 
// RAM is supposed to be larger than the two FIFOs
4259 
// LFSR counters used adr pointers
4260 40 unneback 
`define MODULE fifo_2r2w_sync_simplex
4261 
module `BASE`MODULE (
4262 
`undef MODULE
4263 27 unneback 
    // a side
4264 
    a_d, a_wr, a_fifo_full,
4265 
    a_q, a_rd, a_fifo_empty,
4266 
    a_fill_level,
4267 
    // b side
4268 
    b_d, b_wr, b_fifo_full,
4269 
    b_q, b_rd, b_fifo_empty,
4270 
    b_fill_level,
4271 
    // common
4272 
    clk, rst
4273 
    );
4274 
parameter data_width = 8;
4275 
parameter addr_width = 5;
4276 
parameter fifo_full_level = (1<<addr_width)-1;
4277 
 
4278 
// a side
4279 
input  [data_width-1:0] a_d;
4280 
input                   a_wr;
4281 
output                  a_fifo_full;
4282 
output [data_width-1:0] a_q;
4283 
input                   a_rd;
4284 
output                  a_fifo_empty;
4285 
output [addr_width-1:0] a_fill_level;
4286 
 
4287 
// b side
4288 
input  [data_width-1:0] b_d;
4289 
input                   b_wr;
4290 
output                  b_fifo_full;
4291 
output [data_width-1:0] b_q;
4292 
input                   b_rd;
4293 
output                  b_fifo_empty;
4294 
output [addr_width-1:0] b_fill_level;
4295 
 
4296 
input                   clk;
4297 
input                   rst;
4298 
 
4299 
// adr_gen
4300 
wire [addr_width:1] a_wadr, a_radr;
4301 
wire [addr_width:1] b_wadr, b_radr;
4302 
// dpram
4303 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4304 
 
4305 40 unneback 
`define MODULE cnt_lfsr_ce
4306 
`BASE`MODULE
4307 27 unneback 
    # ( .length(addr_width))
4308 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
4309 
 
4310 40 unneback 
`BASE`MODULE
4311 27 unneback 
    # (.length(addr_width))
4312 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
4313 
 
4314 40 unneback 
`BASE`MODULE
4315 27 unneback 
    # ( .length(addr_width))
4316 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
4317 
 
4318 40 unneback 
`BASE`MODULE
4319 27 unneback 
    # (.length(addr_width))
4320 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
4321 40 unneback 
`undef MODULE
4322 27 unneback 
 
4323 
// mux read or write adr to DPRAM
4324 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
4325 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
4326 
 
4327 40 unneback 
`define MODULE dpram_2r2w
4328 
`BASE`MODULE
4329 27 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4330 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4331 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4332 40 unneback 
`undef MODULE
4333 
 
4334 
`define MODULE cnt_bin_ce_rew_zq_l1
4335 
`BASE`MODULE
4336 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4337 27 unneback 
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
4338 
 
4339 40 unneback 
`BASE`MODULE
4340 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4341 27 unneback 
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
4342 40 unneback 
`undef MODULE
4343 27 unneback 
 
4344 
endmodule
4345 40 unneback 
`endif
4346 27 unneback 
 
4347 40 unneback 
`ifdef FIFO_CMP_ASYNC
4348 
`define MODULE fifo_cmp_async
4349 
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
4350 
`undef MODULE
4351 6 unneback 
 
4352 11 unneback 
   parameter addr_width = 4;
4353 
   parameter N = addr_width-1;
4354 6 unneback 
 
4355 
   parameter Q1 = 2'b00;
4356 
   parameter Q2 = 2'b01;
4357 
   parameter Q3 = 2'b11;
4358 
   parameter Q4 = 2'b10;
4359 
 
4360 
   parameter going_empty = 1'b0;
4361 
   parameter going_full  = 1'b1;
4362 
 
4363 
   input [N:0]  wptr, rptr;
4364 14 unneback 
   output       fifo_empty;
4365 6 unneback 
   output       fifo_full;
4366 
   input        wclk, rclk, rst;
4367 
 
4368 
`ifndef GENERATE_DIRECTION_AS_LATCH
4369 
   wire direction;
4370 
`endif
4371 
`ifdef GENERATE_DIRECTION_AS_LATCH
4372 
   reg direction;
4373 
`endif
4374 
   reg  direction_set, direction_clr;
4375 
 
4376 
   wire async_empty, async_full;
4377 
   wire fifo_full2;
4378 14 unneback 
   wire fifo_empty2;
4379 6 unneback 
 
4380 
   // direction_set
4381 
   always @ (wptr[N:N-1] or rptr[N:N-1])
4382 
     case ({wptr[N:N-1],rptr[N:N-1]})
4383 
       {Q1,Q2} : direction_set <= 1'b1;
4384 
       {Q2,Q3} : direction_set <= 1'b1;
4385 
       {Q3,Q4} : direction_set <= 1'b1;
4386 
       {Q4,Q1} : direction_set <= 1'b1;
4387 
       default : direction_set <= 1'b0;
4388 
     endcase
4389 
 
4390 
   // direction_clear
4391 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
4392 
     if (rst)
4393 
       direction_clr <= 1'b1;
4394 
     else
4395 
       case ({wptr[N:N-1],rptr[N:N-1]})
4396 
         {Q2,Q1} : direction_clr <= 1'b1;
4397 
         {Q3,Q2} : direction_clr <= 1'b1;
4398 
         {Q4,Q3} : direction_clr <= 1'b1;
4399 
         {Q1,Q4} : direction_clr <= 1'b1;
4400 
         default : direction_clr <= 1'b0;
4401 
       endcase
4402 
 
4403 40 unneback 
`define MODULE dff_sr
4404 6 unneback 
`ifndef GENERATE_DIRECTION_AS_LATCH
4405 40 unneback 
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
4406 6 unneback 
`endif
4407 
 
4408 
`ifdef GENERATE_DIRECTION_AS_LATCH
4409 
   always @ (posedge direction_set or posedge direction_clr)
4410 
     if (direction_clr)
4411 
       direction <= going_empty;
4412 
     else
4413 
       direction <= going_full;
4414 
`endif
4415 
 
4416 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
4417 
   assign async_full  = (wptr == rptr) && (direction==going_full);
4418 
 
4419 40 unneback 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
4420 
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
4421 
`undef MODULE
4422 6 unneback 
 
4423 
/*
4424 
   always @ (posedge wclk or posedge rst or posedge async_full)
4425 
     if (rst)
4426 
       {fifo_full, fifo_full2} <= 2'b00;
4427 
     else if (async_full)
4428 
       {fifo_full, fifo_full2} <= 2'b11;
4429 
     else
4430 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
4431 
*/
4432 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
4433 6 unneback 
     if (async_empty)
4434 
       {fifo_empty, fifo_empty2} <= 2'b11;
4435 
     else
4436 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
4437 40 unneback 
`define MODULE dff
4438 
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
4439 
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
4440 
`undef MODULE
4441 27 unneback 
endmodule // async_compb
4442 40 unneback 
`endif
4443 6 unneback 
 
4444 40 unneback 
`ifdef FIFO_1R1W_ASYNC
4445 
`define MODULE fifo_1r1w_async
4446 
module `BASE`MODULE (
4447 
`undef MODULE
4448 6 unneback 
    d, wr, fifo_full, wr_clk, wr_rst,
4449 
    q, rd, fifo_empty, rd_clk, rd_rst
4450 
    );
4451 
 
4452 
parameter data_width = 18;
4453 
parameter addr_width = 4;
4454 
 
4455 
// write side
4456 
input  [data_width-1:0] d;
4457 
input                   wr;
4458 
output                  fifo_full;
4459 
input                   wr_clk;
4460 
input                   wr_rst;
4461 
// read side
4462 
output [data_width-1:0] q;
4463 
input                   rd;
4464 
output                  fifo_empty;
4465 
input                   rd_clk;
4466 
input                   rd_rst;
4467 
 
4468 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
4469 23 unneback 
 
4470 40 unneback 
`define MODULE cnt_gray_ce_bin
4471 
`BASE`MODULE
4472 6 unneback 
    # ( .length(addr_width))
4473 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
4474 
 
4475 40 unneback 
`BASE`MODULE
4476 6 unneback 
    # (.length(addr_width))
4477 23 unneback 
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
4478 40 unneback 
`undef MODULE
4479 6 unneback 
 
4480 40 unneback 
`define MODULE dpram_1r1w
4481 
`BASE`MODULE
4482 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4483 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
4484 40 unneback 
`undef MODULE
4485 6 unneback 
 
4486 40 unneback 
`define MODULE fifo_cmp_async
4487 
`BASE`MODULE
4488 6 unneback 
    # (.addr_width(addr_width))
4489 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
4490 40 unneback 
`undef MODULE
4491 6 unneback 
 
4492 
endmodule
4493 40 unneback 
`endif
4494 6 unneback 
 
4495 40 unneback 
`ifdef FIFO_2R2W_ASYNC
4496 
`define MODULE fifo_2r2w_async
4497 
module `BASE`MODULE (
4498 
`undef MODULE
4499 6 unneback 
    // a side
4500 
    a_d, a_wr, a_fifo_full,
4501 
    a_q, a_rd, a_fifo_empty,
4502 
    a_clk, a_rst,
4503 
    // b side
4504 
    b_d, b_wr, b_fifo_full,
4505 
    b_q, b_rd, b_fifo_empty,
4506 
    b_clk, b_rst
4507 
    );
4508 
 
4509 
parameter data_width = 18;
4510 
parameter addr_width = 4;
4511 
 
4512 
// a side
4513 
input  [data_width-1:0] a_d;
4514 
input                   a_wr;
4515 
output                  a_fifo_full;
4516 
output [data_width-1:0] a_q;
4517 
input                   a_rd;
4518 
output                  a_fifo_empty;
4519 
input                   a_clk;
4520 
input                   a_rst;
4521 
 
4522 
// b side
4523 
input  [data_width-1:0] b_d;
4524 
input                   b_wr;
4525 
output                  b_fifo_full;
4526 
output [data_width-1:0] b_q;
4527 
input                   b_rd;
4528 
output                  b_fifo_empty;
4529 
input                   b_clk;
4530 
input                   b_rst;
4531 
 
4532 40 unneback 
`define MODULE fifo_1r1w_async
4533 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4534 6 unneback 
vl_fifo_1r1w_async_a (
4535 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4536 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4537 
    );
4538 
 
4539 40 unneback 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4540 6 unneback 
vl_fifo_1r1w_async_b (
4541 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4542 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4543 
    );
4544 40 unneback 
`undef MODULE
4545 
 
4546 6 unneback 
endmodule
4547 40 unneback 
`endif
4548 6 unneback 
 
4549 40 unneback 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4550 
`define MODULE fifo_2r2w_async_simplex
4551 
module `BASE`MODULE (
4552 
`undef MODULE
4553 6 unneback 
    // a side
4554 
    a_d, a_wr, a_fifo_full,
4555 
    a_q, a_rd, a_fifo_empty,
4556 
    a_clk, a_rst,
4557 
    // b side
4558 
    b_d, b_wr, b_fifo_full,
4559 
    b_q, b_rd, b_fifo_empty,
4560 
    b_clk, b_rst
4561 
    );
4562 
 
4563 
parameter data_width = 18;
4564 
parameter addr_width = 4;
4565 
 
4566 
// a side
4567 
input  [data_width-1:0] a_d;
4568 
input                   a_wr;
4569 
output                  a_fifo_full;
4570 
output [data_width-1:0] a_q;
4571 
input                   a_rd;
4572 
output                  a_fifo_empty;
4573 
input                   a_clk;
4574 
input                   a_rst;
4575 
 
4576 
// b side
4577 
input  [data_width-1:0] b_d;
4578 
input                   b_wr;
4579 
output                  b_fifo_full;
4580 
output [data_width-1:0] b_q;
4581 
input                   b_rd;
4582 
output                  b_fifo_empty;
4583 
input                   b_clk;
4584 
input                   b_rst;
4585 
 
4586 
// adr_gen
4587 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4588 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4589 
// dpram
4590 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4591 
 
4592 40 unneback 
`define MODULE cnt_gray_ce_bin
4593 
`BASE`MODULE
4594 6 unneback 
    # ( .length(addr_width))
4595 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4596 
 
4597 40 unneback 
`BASE`MODULE
4598 6 unneback 
    # (.length(addr_width))
4599 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4600 
 
4601 40 unneback 
`BASE`MODULE
4602 6 unneback 
    # ( .length(addr_width))
4603 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4604 
 
4605 40 unneback 
`BASE`MODULE
4606 6 unneback 
    # (.length(addr_width))
4607 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4608 40 unneback 
`undef MODULE
4609 6 unneback 
 
4610 
// mux read or write adr to DPRAM
4611 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4612 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4613 
 
4614 40 unneback 
`define MODULE dpram_2r2w
4615 
`BASE`MODULE
4616 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4617 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4618 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4619 40 unneback 
`undef MODULE
4620 6 unneback 
 
4621 40 unneback 
`define MODULE fifo_cmp_async
4622 
`BASE`MODULE
4623 6 unneback 
    # (.addr_width(addr_width))
4624 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4625 
 
4626 40 unneback 
`BASE`MODULE
4627 6 unneback 
    # (.addr_width(addr_width))
4628 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4629 40 unneback 
`undef MODULE
4630 6 unneback 
 
4631 
endmodule
4632 40 unneback 
`endif
4633 48 unneback 
 
4634 
`ifdef REG_FILE
4635 
`define MODULE reg_file
4636 
module `BASE`MODULE (
4637 
`undef MODULE
4638 
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4639 
);
4640 
parameter data_width = 32;
4641 
parameter addr_width = 5;
4642 
input [addr_width-1:0] a1, a2, a3;
4643 
input [data_width-1:0] wd3;
4644 
input we3;
4645 
output [data_width-1:0] rd1, rd2;
4646 
input clk;
4647 
 
4648 
`ifdef ACTEL
4649 
reg [data_width-1:0] wd3_reg;
4650 
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4651 
reg we3_reg;
4652 98 unneback 
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
4653 
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
4654 48 unneback 
always @ (posedge clk or posedge rst)
4655 
if (rst)
4656 
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4657 
else
4658 
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4659 
 
4660 
    always @ (negedge clk)
4661 
    if (we3_reg)
4662 
        ram1[a3_reg] <= wd3;
4663 
    always @ (posedge clk)
4664 
        a1_reg <= a1;
4665 
    assign rd1 = ram1[a1_reg];
4666 
 
4667 
    always @ (negedge clk)
4668 
    if (we3_reg)
4669 
        ram2[a3_reg] <= wd3;
4670 
    always @ (posedge clk)
4671 
        a2_reg <= a2;
4672 
    assign rd2 = ram2[a2_reg];
4673 
 
4674 
`else
4675 
 
4676 
`define MODULE dpram_1r1w
4677 
`BASE`MODULE
4678 
    # ( .data_width(data_width), .addr_width(addr_width))
4679 
    ram1 (
4680 
        .d_a(wd3),
4681 
        .adr_a(a3),
4682 
        .we_a(we3),
4683 
        .clk_a(clk),
4684 
        .q_b(rd1),
4685 
        .adr_b(a1),
4686 
        .clk_b(clk) );
4687 
 
4688 
`BASE`MODULE
4689 
    # ( .data_width(data_width), .addr_width(addr_width))
4690 
    ram2 (
4691 
        .d_a(wd3),
4692 
        .adr_a(a3),
4693 
        .we_a(we3),
4694 
        .clk_a(clk),
4695 
        .q_b(rd2),
4696 
        .adr_b(a2),
4697 
        .clk_b(clk) );
4698 
`undef MODULE
4699 
 
4700 
`endif
4701 
 
4702 
endmodule
4703 
`endif
4704 12 unneback 
//////////////////////////////////////////////////////////////////////
4705 
////                                                              ////
4706 
////  Versatile library, wishbone stuff                           ////
4707 
////                                                              ////
4708 
////  Description                                                 ////
4709 
////  Wishbone compliant modules                                  ////
4710 
////                                                              ////
4711 
////                                                              ////
4712 
////  To Do:                                                      ////
4713 
////   -                                                          ////
4714 
////                                                              ////
4715 
////  Author(s):                                                  ////
4716 
////      - Michael Unneback, unneback@opencores.org              ////
4717 
////        ORSoC AB                                              ////
4718 
////                                                              ////
4719 
//////////////////////////////////////////////////////////////////////
4720 
////                                                              ////
4721 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4722 
////                                                              ////
4723 
//// This source file may be used and distributed without         ////
4724 
//// restriction provided that this copyright statement is not    ////
4725 
//// removed from the file and that any derivative work contains  ////
4726 
//// the original copyright notice and the associated disclaimer. ////
4727 
////                                                              ////
4728 
//// This source file is free software; you can redistribute it   ////
4729 
//// and/or modify it under the terms of the GNU Lesser General   ////
4730 
//// Public License as published by the Free Software Foundation; ////
4731 
//// either version 2.1 of the License, or (at your option) any   ////
4732 
//// later version.                                               ////
4733 
////                                                              ////
4734 
//// This source is distributed in the hope that it will be       ////
4735 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4736 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4737 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4738 
//// details.                                                     ////
4739 
////                                                              ////
4740 
//// You should have received a copy of the GNU Lesser General    ////
4741 
//// Public License along with this source; if not, download it   ////
4742 
//// from http://www.opencores.org/lgpl.shtml                     ////
4743 
////                                                              ////
4744 
//////////////////////////////////////////////////////////////////////
4745 
 
4746 75 unneback 
`ifdef WB_ADR_INC
4747 
// async wb3 - wb3 bridge
4748 
`timescale 1ns/1ns
4749 
`define MODULE wb_adr_inc
4750 85 unneback 
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
4751 75 unneback 
`undef MODULE
4752 83 unneback 
parameter adr_width = 10;
4753 
parameter max_burst_width = 4;
4754 85 unneback 
input cyc_i, stb_i, we_i;
4755 83 unneback 
input [2:0] cti_i;
4756 
input [1:0] bte_i;
4757 
input [adr_width-1:0] adr_i;
4758 
output [adr_width-1:0] adr_o;
4759 
output ack_o;
4760 
input clk, rst;
4761 75 unneback 
 
4762 83 unneback 
reg [adr_width-1:0] adr;
4763 90 unneback 
wire [max_burst_width-1:0] to_adr;
4764 91 unneback 
reg [max_burst_width-1:0] last_adr;
4765 92 unneback 
reg last_cycle;
4766 
localparam idle_or_eoc = 1'b0;
4767 
localparam cyc_or_ws   = 1'b1;
4768 90 unneback 
 
4769 91 unneback 
always @ (posedge clk or posedge rst)
4770 
if (rst)
4771 
    last_adr <= {max_burst_width{1'b0}};
4772 
else
4773 
    if (stb_i)
4774 92 unneback 
        last_adr <=adr_o[max_burst_width-1:0];
4775 91 unneback 
 
4776 83 unneback 
generate
4777 
if (max_burst_width==0) begin : inst_0
4778 97 unneback 
 
4779 
        reg ack_o;
4780 
        assign adr_o = adr_i;
4781 
        always @ (posedge clk or posedge rst)
4782 
        if (rst)
4783 
            ack_o <= 1'b0;
4784 
        else
4785 
            ack_o <= cyc_i & stb_i & !ack_o;
4786 
 
4787 83 unneback 
end else begin
4788 
 
4789 
    always @ (posedge clk or posedge rst)
4790 
    if (rst)
4791 92 unneback 
        last_cycle <= idle_or_eoc;
4792 83 unneback 
    else
4793 92 unneback 
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
4794 
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
4795 
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
4796 
                      cyc_or_ws; // cyc
4797 
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
4798 85 unneback 
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
4799 91 unneback 
                                        (!stb_i) ? last_adr :
4800 92 unneback 
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
4801 85 unneback 
                                        adr[max_burst_width-1:0];
4802 92 unneback 
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
4803 97 unneback 
 
4804 83 unneback 
end
4805 
endgenerate
4806 
 
4807 
generate
4808 
if (max_burst_width==2) begin : inst_2
4809 
    always @ (posedge clk or posedge rst)
4810 
    if (rst)
4811 
        adr <= 2'h0;
4812 
    else
4813 
        if (cyc_i & stb_i)
4814 
            adr[1:0] <= to_adr[1:0] + 2'd1;
4815 75 unneback 
        else
4816 83 unneback 
            adr <= to_adr[1:0];
4817 
end
4818 
endgenerate
4819 
 
4820 
generate
4821 
if (max_burst_width==3) begin : inst_3
4822 
    always @ (posedge clk or posedge rst)
4823 
    if (rst)
4824 
        adr <= 3'h0;
4825 
    else
4826 
        if (cyc_i & stb_i)
4827 
            case (bte_i)
4828 
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
4829 
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
4830 75 unneback 
            endcase
4831 83 unneback 
        else
4832 
            adr <= to_adr[2:0];
4833 
end
4834 
endgenerate
4835 
 
4836 
generate
4837 
if (max_burst_width==4) begin : inst_4
4838 
    always @ (posedge clk or posedge rst)
4839 
    if (rst)
4840 
        adr <= 4'h0;
4841 
    else
4842 91 unneback 
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
4843 83 unneback 
            case (bte_i)
4844 
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
4845 
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
4846 
            default: adr[3:0] <= to_adr + 4'd1;
4847 
            endcase
4848 
        else
4849 
            adr <= to_adr[3:0];
4850 
end
4851 
endgenerate
4852 
 
4853 
generate
4854 
if (adr_width > max_burst_width) begin : pass_through
4855 
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
4856 
end
4857 
endgenerate
4858 
 
4859 
endmodule
4860 75 unneback 
`endif
4861 
 
4862 40 unneback 
`ifdef WB3WB3_BRIDGE
4863 12 unneback 
// async wb3 - wb3 bridge
4864 
`timescale 1ns/1ns
4865 40 unneback 
`define MODULE wb3wb3_bridge
4866 
module `BASE`MODULE (
4867 
`undef MODULE
4868 12 unneback 
        // wishbone slave side
4869 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4870 
        // wishbone master side
4871 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4872 
 
4873 95 unneback 
parameter style = "FIFO"; // valid: simple, FIFO
4874 
parameter addr_width = 4;
4875 
 
4876 12 unneback 
input [31:0] wbs_dat_i;
4877 
input [31:2] wbs_adr_i;
4878 
input [3:0]  wbs_sel_i;
4879 
input [1:0]  wbs_bte_i;
4880 
input [2:0]  wbs_cti_i;
4881 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4882 
output [31:0] wbs_dat_o;
4883 14 unneback 
output wbs_ack_o;
4884 12 unneback 
input wbs_clk, wbs_rst;
4885 
 
4886 
output [31:0] wbm_dat_o;
4887 
output reg [31:2] wbm_adr_o;
4888 
output [3:0]  wbm_sel_o;
4889 
output reg [1:0]  wbm_bte_o;
4890 
output reg [2:0]  wbm_cti_o;
4891 14 unneback 
output reg wbm_we_o;
4892 
output wbm_cyc_o;
4893 12 unneback 
output wbm_stb_o;
4894 
input [31:0]  wbm_dat_i;
4895 
input wbm_ack_i;
4896 
input wbm_clk, wbm_rst;
4897 
 
4898 
// bte
4899 
parameter linear       = 2'b00;
4900 
parameter wrap4        = 2'b01;
4901 
parameter wrap8        = 2'b10;
4902 
parameter wrap16       = 2'b11;
4903 
// cti
4904 
parameter classic      = 3'b000;
4905 
parameter incburst     = 3'b010;
4906 
parameter endofburst   = 3'b111;
4907 
 
4908 95 unneback 
localparam wbs_adr  = 1'b0;
4909 
localparam wbs_data = 1'b1;
4910 12 unneback 
 
4911 95 unneback 
localparam wbm_adr0      = 2'b00;
4912 
localparam wbm_adr1      = 2'b01;
4913 
localparam wbm_data      = 2'b10;
4914 
localparam wbm_data_wait = 2'b11;
4915 12 unneback 
 
4916 
reg [1:0] wbs_bte_reg;
4917 
reg wbs;
4918 
wire wbs_eoc_alert, wbm_eoc_alert;
4919 
reg wbs_eoc, wbm_eoc;
4920 
reg [1:0] wbm;
4921 
 
4922 14 unneback 
wire [1:16] wbs_count, wbm_count;
4923 12 unneback 
 
4924 
wire [35:0] a_d, a_q, b_d, b_q;
4925 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4926 
reg a_rd_reg;
4927 
wire b_rd_adr, b_rd_data;
4928 14 unneback 
wire b_rd_data_reg;
4929 
wire [35:0] temp;
4930 12 unneback 
 
4931 
`define WE 5
4932 
`define BTE 4:3
4933 
`define CTI 2:0
4934 
 
4935 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4936 
always @ (posedge wbs_clk or posedge wbs_rst)
4937 
if (wbs_rst)
4938 
        wbs_eoc <= 1'b0;
4939 
else
4940 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4941 78 unneback 
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
4942 12 unneback 
        else if (wbs_eoc_alert & (a_rd | a_wr))
4943 
                wbs_eoc <= 1'b1;
4944 
 
4945 40 unneback 
`define MODULE cnt_shreg_ce_clear
4946 
`BASE`MODULE # ( .length(16))
4947 
`undef MODULE
4948 12 unneback 
    cnt0 (
4949 
        .cke(wbs_ack_o),
4950 
        .clear(wbs_eoc),
4951 
        .q(wbs_count),
4952 
        .rst(wbs_rst),
4953 
        .clk(wbs_clk));
4954 
 
4955 
always @ (posedge wbs_clk or posedge wbs_rst)
4956 
if (wbs_rst)
4957 
        wbs <= wbs_adr;
4958 
else
4959 75 unneback 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
4960 12 unneback 
                wbs <= wbs_data;
4961 
        else if (wbs_eoc & wbs_ack_o)
4962 
                wbs <= wbs_adr;
4963 
 
4964 
// wbs FIFO
4965 75 unneback 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
4966 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
4967 12 unneback 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4968 
              1'b0;
4969 
assign a_rd = !a_fifo_empty;
4970 
always @ (posedge wbs_clk or posedge wbs_rst)
4971 
if (wbs_rst)
4972 
        a_rd_reg <= 1'b0;
4973 
else
4974 
        a_rd_reg <= a_rd;
4975 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4976 
 
4977 
assign wbs_dat_o = a_q[35:4];
4978 
 
4979 
always @ (posedge wbs_clk or posedge wbs_rst)
4980 
if (wbs_rst)
4981 13 unneback 
        wbs_bte_reg <= 2'b00;
4982 12 unneback 
else
4983 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
4984 12 unneback 
 
4985 
// wbm FIFO
4986 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4987 
always @ (posedge wbm_clk or posedge wbm_rst)
4988 
if (wbm_rst)
4989 
        wbm_eoc <= 1'b0;
4990 
else
4991 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4992 
                wbm_eoc <= b_q[`BTE] == linear;
4993 
        else if (wbm_eoc_alert & wbm_ack_i)
4994 
                wbm_eoc <= 1'b1;
4995 
 
4996 
always @ (posedge wbm_clk or posedge wbm_rst)
4997 
if (wbm_rst)
4998 
        wbm <= wbm_adr0;
4999 
else
5000 33 unneback 
/*
5001 12 unneback 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
5002 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
5003 
        (wbm==wbm_adr1 & !wbm_we_o) |
5004 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
5005 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
5006 33 unneback 
*/
5007 
    case (wbm)
5008 
    wbm_adr0:
5009 
        if (!b_fifo_empty)
5010 
            wbm <= wbm_adr1;
5011 
    wbm_adr1:
5012 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
5013 
            wbm <= wbm_data;
5014 
    wbm_data:
5015 
        if (wbm_ack_i & wbm_eoc)
5016 
            wbm <= wbm_adr0;
5017 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
5018 
            wbm <= wbm_data_wait;
5019 
    wbm_data_wait:
5020 
        if (!b_fifo_empty)
5021 
            wbm <= wbm_data;
5022 
    endcase
5023 12 unneback 
 
5024 
assign b_d = {wbm_dat_i,4'b1111};
5025 
assign b_wr = !wbm_we_o & wbm_ack_i;
5026 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
5027 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
5028 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
5029 33 unneback 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
5030 12 unneback 
                   1'b0;
5031 
assign b_rd = b_rd_adr | b_rd_data;
5032 
 
5033 40 unneback 
`define MODULE dff
5034 
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
5035 
`undef MODULE
5036 
`define MODULE dff_ce
5037 
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
5038 
`undef MODULE
5039 12 unneback 
 
5040 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
5041 
 
5042 40 unneback 
`define MODULE cnt_shreg_ce_clear
5043 42 unneback 
`BASE`MODULE # ( .length(16))
5044 40 unneback 
`undef MODULE
5045 12 unneback 
    cnt1 (
5046 
        .cke(wbm_ack_i),
5047 
        .clear(wbm_eoc),
5048 
        .q(wbm_count),
5049 
        .rst(wbm_rst),
5050 
        .clk(wbm_clk));
5051 
 
5052 33 unneback 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
5053 
assign wbm_stb_o = (wbm==wbm_data);
5054 12 unneback 
 
5055 
always @ (posedge wbm_clk or posedge wbm_rst)
5056 
if (wbm_rst)
5057 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
5058 
else begin
5059 
        if (wbm==wbm_adr0 & !b_fifo_empty)
5060 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
5061 
        else if (wbm_eoc_alert & wbm_ack_i)
5062 
                wbm_cti_o <= endofburst;
5063 
end
5064 
 
5065 
//async_fifo_dw_simplex_top
5066 40 unneback 
`define MODULE fifo_2r2w_async_simplex
5067 
`BASE`MODULE
5068 
`undef MODULE
5069 12 unneback 
# ( .data_width(36), .addr_width(addr_width))
5070 
fifo (
5071 
    // a side
5072 
    .a_d(a_d),
5073 
    .a_wr(a_wr),
5074 
    .a_fifo_full(a_fifo_full),
5075 
    .a_q(a_q),
5076 
    .a_rd(a_rd),
5077 
    .a_fifo_empty(a_fifo_empty),
5078 
    .a_clk(wbs_clk),
5079 
    .a_rst(wbs_rst),
5080 
    // b side
5081 
    .b_d(b_d),
5082 
    .b_wr(b_wr),
5083 
    .b_fifo_full(b_fifo_full),
5084 
    .b_q(b_q),
5085 
    .b_rd(b_rd),
5086 
    .b_fifo_empty(b_fifo_empty),
5087 
    .b_clk(wbm_clk),
5088 
    .b_rst(wbm_rst)
5089 
    );
5090 
 
5091 
endmodule
5092 40 unneback 
`undef WE
5093 
`undef BTE
5094 
`undef CTI
5095 
`endif
5096 17 unneback 
 
5097 75 unneback 
`ifdef WB3AVALON_BRIDGE
5098 
`define MODULE wb3avalon_bridge
5099 
module `BASE`MODULE (
5100 
`undef MODULE
5101 
        // wishbone slave side
5102 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5103 77 unneback 
        // avalon master side
5104 75 unneback 
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
5105 
 
5106 85 unneback 
parameter linewrapburst = 1'b0;
5107 
 
5108 75 unneback 
input [31:0] wbs_dat_i;
5109 
input [31:2] wbs_adr_i;
5110 
input [3:0]  wbs_sel_i;
5111 
input [1:0]  wbs_bte_i;
5112 
input [2:0]  wbs_cti_i;
5113 83 unneback 
input wbs_we_i;
5114 
input wbs_cyc_i;
5115 
input wbs_stb_i;
5116 75 unneback 
output [31:0] wbs_dat_o;
5117 
output wbs_ack_o;
5118 
input wbs_clk, wbs_rst;
5119 
 
5120 
input [31:0] readdata;
5121 
output [31:0] writedata;
5122 
output [31:2] address;
5123 
output [3:0]  be;
5124 
output write;
5125 81 unneback 
output read;
5126 75 unneback 
output beginbursttransfer;
5127 
output [3:0] burstcount;
5128 
input readdatavalid;
5129 
input waitrequest;
5130 
input clk;
5131 
input rst;
5132 
 
5133 
wire [1:0] wbm_bte_o;
5134 
wire [2:0] wbm_cti_o;
5135 
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
5136 
reg last_cyc;
5137 79 unneback 
reg [3:0] counter;
5138 82 unneback 
reg read_busy;
5139 75 unneback 
 
5140 
always @ (posedge clk or posedge rst)
5141 
if (rst)
5142 
    last_cyc <= 1'b0;
5143 
else
5144 
    last_cyc <= wbm_cyc_o;
5145 
 
5146 79 unneback 
always @ (posedge clk or posedge rst)
5147 
if (rst)
5148 82 unneback 
    read_busy <= 1'b0;
5149 79 unneback 
else
5150 82 unneback 
    if (read & !waitrequest)
5151 
        read_busy <= 1'b1;
5152 
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
5153 
        read_busy <= 1'b0;
5154 
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
5155 81 unneback 
 
5156 75 unneback 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
5157 
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
5158 
                    (wbm_bte_o==2'b10) ? 4'd8 :
5159 78 unneback 
                    (wbm_bte_o==2'b11) ? 4'd16:
5160 
                    4'd1;
5161 82 unneback 
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
5162 75 unneback 
 
5163 79 unneback 
always @ (posedge clk or posedge rst)
5164 
if (rst) begin
5165 
    counter <= 4'd0;
5166 
end else
5167 80 unneback 
    if (wbm_we_o) begin
5168 
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
5169 85 unneback 
            counter <= burstcount -4'd1;
5170 80 unneback 
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
5171 
            counter <= burstcount;
5172 
        end else if (!waitrequest & wbm_stb_o) begin
5173 
            counter <= counter - 4'd1;
5174 
        end
5175 82 unneback 
    end
5176 81 unneback 
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
5177 79 unneback 
 
5178 75 unneback 
`define MODULE wb3wb3_bridge
5179 77 unneback 
`BASE`MODULE wbwb3inst (
5180 75 unneback 
`undef MODULE
5181 
    // wishbone slave side
5182 
    .wbs_dat_i(wbs_dat_i),
5183 
    .wbs_adr_i(wbs_adr_i),
5184 
    .wbs_sel_i(wbs_sel_i),
5185 
    .wbs_bte_i(wbs_bte_i),
5186 
    .wbs_cti_i(wbs_cti_i),
5187 
    .wbs_we_i(wbs_we_i),
5188 
    .wbs_cyc_i(wbs_cyc_i),
5189 
    .wbs_stb_i(wbs_stb_i),
5190 
    .wbs_dat_o(wbs_dat_o),
5191 
    .wbs_ack_o(wbs_ack_o),
5192 
    .wbs_clk(wbs_clk),
5193 
    .wbs_rst(wbs_rst),
5194 
    // wishbone master side
5195 
    .wbm_dat_o(writedata),
5196 78 unneback 
    .wbm_adr_o(address),
5197 75 unneback 
    .wbm_sel_o(be),
5198 
    .wbm_bte_o(wbm_bte_o),
5199 
    .wbm_cti_o(wbm_cti_o),
5200 
    .wbm_we_o(wbm_we_o),
5201 
    .wbm_cyc_o(wbm_cyc_o),
5202 
    .wbm_stb_o(wbm_stb_o),
5203 
    .wbm_dat_i(readdata),
5204 
    .wbm_ack_i(wbm_ack_i),
5205 
    .wbm_clk(clk),
5206 
    .wbm_rst(rst));
5207 
 
5208 
 
5209 
endmodule
5210 
`endif
5211 
 
5212 40 unneback 
`ifdef WB3_ARBITER_TYPE1
5213 
`define MODULE wb3_arbiter_type1
5214 42 unneback 
module `BASE`MODULE (
5215 40 unneback 
`undef MODULE
5216 39 unneback 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5217 
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
5218 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5219 
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
5220 
    wb_clk, wb_rst
5221 
);
5222 
 
5223 
parameter nr_of_ports = 3;
5224 
parameter adr_size = 26;
5225 
parameter adr_lo   = 2;
5226 
parameter dat_size = 32;
5227 
parameter sel_size = dat_size/8;
5228 
 
5229 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
5230 
localparam dw = dat_size * nr_of_ports;
5231 
localparam sw = sel_size * nr_of_ports;
5232 
localparam cw = 3 * nr_of_ports;
5233 
localparam bw = 2 * nr_of_ports;
5234 
 
5235 
input  [dw-1:0] wbm_dat_o;
5236 
input  [aw-1:0] wbm_adr_o;
5237 
input  [sw-1:0] wbm_sel_o;
5238 
input  [cw-1:0] wbm_cti_o;
5239 
input  [bw-1:0] wbm_bte_o;
5240 
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
5241 
output [dw-1:0] wbm_dat_i;
5242 
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
5243 
 
5244 
output [dat_size-1:0] wbs_dat_i;
5245 
output [adr_size-1:adr_lo] wbs_adr_i;
5246 
output [sel_size-1:0] wbs_sel_i;
5247 
output [2:0] wbs_cti_i;
5248 
output [1:0] wbs_bte_i;
5249 
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
5250 
input  [dat_size-1:0] wbs_dat_o;
5251 
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
5252 
 
5253 
input wb_clk, wb_rst;
5254 
 
5255 44 unneback 
reg  [nr_of_ports-1:0] select;
5256 39 unneback 
wire [nr_of_ports-1:0] state;
5257 
wire [nr_of_ports-1:0] eoc; // end-of-cycle
5258 
wire [nr_of_ports-1:0] sel;
5259 
wire idle;
5260 
 
5261 
genvar i;
5262 
 
5263 
assign idle = !(|state);
5264 
 
5265 
generate
5266 
if (nr_of_ports == 2) begin
5267 
 
5268 
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
5269 
 
5270 
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5271 
 
5272 44 unneback 
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5273 
 
5274 
    always @ (idle or wbm_cyc_o)
5275 
    if (idle)
5276 
        casex (wbm_cyc_o)
5277 
        2'b1x : select = 2'b10;
5278 
        2'b01 : select = 2'b01;
5279 
        default : select = {nr_of_ports{1'b0}};
5280 
        endcase
5281 
    else
5282 
        select = {nr_of_ports{1'b0}};
5283 
 
5284 39 unneback 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5285 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5286 
 
5287 
end
5288 
endgenerate
5289 
 
5290 
generate
5291 
if (nr_of_ports == 3) begin
5292 
 
5293 
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5294 
 
5295 
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5296 
 
5297 44 unneback 
    always @ (idle or wbm_cyc_o)
5298 
    if (idle)
5299 
        casex (wbm_cyc_o)
5300 
        3'b1xx : select = 3'b100;
5301 
        3'b01x : select = 3'b010;
5302 
        3'b001 : select = 3'b001;
5303 
        default : select = {nr_of_ports{1'b0}};
5304 
        endcase
5305 
    else
5306 
        select = {nr_of_ports{1'b0}};
5307 
 
5308 
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5309 39 unneback 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5310 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5311 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5312 
 
5313 
end
5314 
endgenerate
5315 
 
5316 
generate
5317 44 unneback 
if (nr_of_ports == 4) begin
5318 
 
5319 
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5320 
 
5321 
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5322 
 
5323 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5324 
 
5325 
    always @ (idle or wbm_cyc_o)
5326 
    if (idle)
5327 
        casex (wbm_cyc_o)
5328 
        4'b1xxx : select = 4'b1000;
5329 
        4'b01xx : select = 4'b0100;
5330 
        4'b001x : select = 4'b0010;
5331 
        4'b0001 : select = 4'b0001;
5332 
        default : select = {nr_of_ports{1'b0}};
5333 
        endcase
5334 
    else
5335 
        select = {nr_of_ports{1'b0}};
5336 
 
5337 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5338 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5339 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5340 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5341 
 
5342 
end
5343 
endgenerate
5344 
 
5345 
generate
5346 
if (nr_of_ports == 5) begin
5347 
 
5348 
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5349 
 
5350 
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5351 
 
5352 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5353 
 
5354 
    always @ (idle or wbm_cyc_o)
5355 
    if (idle)
5356 
        casex (wbm_cyc_o)
5357 
        5'b1xxxx : select = 5'b10000;
5358 
        5'b01xxx : select = 5'b01000;
5359 
        5'b001xx : select = 5'b00100;
5360 
        5'b0001x : select = 5'b00010;
5361 
        5'b00001 : select = 5'b00001;
5362 
        default : select = {nr_of_ports{1'b0}};
5363 
        endcase
5364 
    else
5365 
        select = {nr_of_ports{1'b0}};
5366 
 
5367 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5368 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5369 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5370 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5371 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5372 
 
5373 
end
5374 
endgenerate
5375 
 
5376 
generate
5377 67 unneback 
if (nr_of_ports == 6) begin
5378 
 
5379 
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5380 
 
5381 
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5382 
 
5383 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5384 
 
5385 
    always @ (idle or wbm_cyc_o)
5386 
    if (idle)
5387 
        casex (wbm_cyc_o)
5388 
        6'b1xxxxx : select = 6'b100000;
5389 
        6'b01xxxx : select = 6'b010000;
5390 
        6'b001xxx : select = 6'b001000;
5391 
        6'b0001xx : select = 6'b000100;
5392 
        6'b00001x : select = 6'b000010;
5393 
        6'b000001 : select = 6'b000001;
5394 
        default : select = {nr_of_ports{1'b0}};
5395 
        endcase
5396 
    else
5397 
        select = {nr_of_ports{1'b0}};
5398 
 
5399 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5400 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5401 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5402 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5403 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5404 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5405 
 
5406 
end
5407 
endgenerate
5408 
 
5409 
generate
5410 
if (nr_of_ports == 7) begin
5411 
 
5412 
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5413 
 
5414 
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5415 
 
5416 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5417 
 
5418 
    always @ (idle or wbm_cyc_o)
5419 
    if (idle)
5420 
        casex (wbm_cyc_o)
5421 
        7'b1xxxxxx : select = 7'b1000000;
5422 
        7'b01xxxxx : select = 7'b0100000;
5423 
        7'b001xxxx : select = 7'b0010000;
5424 
        7'b0001xxx : select = 7'b0001000;
5425 
        7'b00001xx : select = 7'b0000100;
5426 
        7'b000001x : select = 7'b0000010;
5427 
        7'b0000001 : select = 7'b0000001;
5428 
        default : select = {nr_of_ports{1'b0}};
5429 
        endcase
5430 
    else
5431 
        select = {nr_of_ports{1'b0}};
5432 
 
5433 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5434 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5435 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5436 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5437 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5438 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5439 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5440 
 
5441 
end
5442 
endgenerate
5443 
 
5444 
generate
5445 
if (nr_of_ports == 8) begin
5446 
 
5447 
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5448 
 
5449 
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5450 
 
5451 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5452 
 
5453 
    always @ (idle or wbm_cyc_o)
5454 
    if (idle)
5455 
        casex (wbm_cyc_o)
5456 
        8'b1xxxxxxx : select = 8'b10000000;
5457 
        8'b01xxxxxx : select = 8'b01000000;
5458 
        8'b001xxxxx : select = 8'b00100000;
5459 
        8'b0001xxxx : select = 8'b00010000;
5460 
        8'b00001xxx : select = 8'b00001000;
5461 
        8'b000001xx : select = 8'b00000100;
5462 
        8'b0000001x : select = 8'b00000010;
5463 
        8'b00000001 : select = 8'b00000001;
5464 
        default : select = {nr_of_ports{1'b0}};
5465 
        endcase
5466 
    else
5467 
        select = {nr_of_ports{1'b0}};
5468 
 
5469 
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
5470 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5471 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5472 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5473 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5474 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5475 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5476 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5477 
 
5478 
end
5479 
endgenerate
5480 
 
5481 
generate
5482 63 unneback 
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
5483 42 unneback 
`define MODULE spr
5484 
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
5485 
`undef MODULE
5486 39 unneback 
end
5487 
endgenerate
5488 
 
5489 
    assign sel = select | state;
5490 
 
5491 40 unneback 
`define MODULE mux_andor
5492 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
5493 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
5494 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
5495 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
5496 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
5497 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
5498 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
5499 
`undef MODULE
5500 39 unneback 
    assign wbs_cyc_i = |sel;
5501 
 
5502 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
5503 
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
5504 
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
5505 
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
5506 
 
5507 
endmodule
5508 40 unneback 
`endif
5509 39 unneback 
 
5510 60 unneback 
`ifdef WB_B3_RAM_BE
5511 49 unneback 
// WB RAM with byte enable
5512 59 unneback 
`define MODULE wb_b3_ram_be
5513 
module `BASE`MODULE (
5514 
`undef MODULE
5515 69 unneback 
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5516 
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
5517 59 unneback 
 
5518 68 unneback 
parameter adr_size = 16;
5519 85 unneback 
parameter mem_size = 1<<adr_size;
5520 60 unneback 
parameter dat_size = 32;
5521 83 unneback 
parameter max_burst_width = 4;
5522 60 unneback 
parameter memory_init = 1;
5523 
parameter memory_file = "vl_ram.vmem";
5524 59 unneback 
 
5525 85 unneback 
localparam aw = (adr_size);
5526 69 unneback 
localparam dw = dat_size;
5527 
localparam sw = dat_size/8;
5528 
localparam cw = 3;
5529 
localparam bw = 2;
5530 60 unneback 
 
5531 70 unneback 
input [dw-1:0] wbs_dat_i;
5532 
input [aw-1:0] wbs_adr_i;
5533 
input [cw-1:0] wbs_cti_i;
5534 
input [bw-1:0] wbs_bte_i;
5535 
input [sw-1:0] wbs_sel_i;
5536 
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5537 
output [dw-1:0] wbs_dat_o;
5538 
output wbs_ack_o;
5539 71 unneback 
input wb_clk, wb_rst;
5540 59 unneback 
 
5541 83 unneback 
wire [aw-1:0] adr;
5542 59 unneback 
 
5543 60 unneback 
`define MODULE ram_be
5544 
`BASE`MODULE # (
5545 
    .data_width(dat_size),
5546 83 unneback 
    .addr_width(aw),
5547 69 unneback 
    .mem_size(mem_size),
5548 68 unneback 
    .memory_init(memory_init),
5549 
    .memory_file(memory_file))
5550 60 unneback 
ram0(
5551 
`undef MODULE
5552 
    .d(wbs_dat_i),
5553 83 unneback 
    .adr(adr),
5554 60 unneback 
    .be(wbs_sel_i),
5555 86 unneback 
    .we(wbs_we_i & wbs_ack_o),
5556 60 unneback 
    .q(wbs_dat_o),
5557 
    .clk(wb_clk)
5558 
);
5559 
 
5560 83 unneback 
`define MODULE wb_adr_inc
5561 
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
5562 
    .cyc_i(wbs_cyc_i),
5563 
    .stb_i(wbs_stb_i),
5564 
    .cti_i(wbs_cti_i),
5565 
    .bte_i(wbs_bte_i),
5566 
    .adr_i(wbs_adr_i),
5567 85 unneback 
    .we_i(wbs_we_i),
5568 83 unneback 
    .ack_o(wbs_ack_o),
5569 
    .adr_o(adr),
5570 
    .clk(wb_clk),
5571 
    .rst(wb_rst));
5572 
`undef MODULE
5573 60 unneback 
 
5574 59 unneback 
endmodule
5575 
`endif
5576 
 
5577 
`ifdef WB_B4_RAM_BE
5578 
// WB RAM with byte enable
5579 49 unneback 
`define MODULE wb_b4_ram_be
5580 
module `BASE`MODULE (
5581 
`undef MODULE
5582 
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
5583 52 unneback 
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
5584 49 unneback 
 
5585 
    parameter dat_width = 32;
5586 
    parameter adr_width = 8;
5587 
 
5588 
input [dat_width-1:0] wb_dat_i;
5589 
input [adr_width-1:0] wb_adr_i;
5590 
input [dat_width/8-1:0] wb_sel_i;
5591 
input wb_we_i, wb_stb_i, wb_cyc_i;
5592 
output [dat_width-1:0] wb_dat_o;
5593 51 unneback 
reg [dat_width-1:0] wb_dat_o;
5594 52 unneback 
output wb_stall_o;
5595 49 unneback 
output wb_ack_o;
5596 
reg wb_ack_o;
5597 
input wb_clk, wb_rst;
5598 
 
5599 56 unneback 
wire [dat_width/8-1:0] cke;
5600 
 
5601 49 unneback 
generate
5602 
if (dat_width==32) begin
5603 51 unneback 
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
5604 
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
5605 
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
5606 
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
5607 56 unneback 
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
5608 49 unneback 
    always @ (posedge wb_clk)
5609 
    begin
5610 56 unneback 
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
5611 
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
5612 
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
5613 
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
5614 49 unneback 
    end
5615 59 unneback 
    always @ (posedge wb_clk or posedge wb_rst)
5616 
    begin
5617 
        if (wb_rst)
5618 
            wb_dat_o <= 32'h0;
5619 
        else
5620 
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
5621 
    end
5622 49 unneback 
end
5623 
endgenerate
5624 
 
5625 52 unneback 
always @ (posedge wb_clk or posedge wb_rst)
5626 55 unneback 
if (wb_rst)
5627 52 unneback 
    wb_ack_o <= 1'b0;
5628 
else
5629 54 unneback 
    wb_ack_o <= wb_stb_i & wb_cyc_i;
5630 52 unneback 
 
5631 
assign wb_stall_o = 1'b0;
5632 
 
5633 49 unneback 
endmodule
5634 
`endif
5635 
 
5636 48 unneback 
`ifdef WB_B4_ROM
5637 
// WB ROM
5638 
`define MODULE wb_b4_rom
5639 
module `BASE`MODULE (
5640 
`undef MODULE
5641 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5642 
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
5643 
 
5644 
    parameter dat_width = 32;
5645 
    parameter dat_default = 32'h15000000;
5646 
    parameter adr_width = 32;
5647 
 
5648 
/*
5649 
`ifndef ROM
5650 
`define ROM "rom.v"
5651 
`endif
5652 
*/
5653 
    input [adr_width-1:2]   wb_adr_i;
5654 
    input                   wb_stb_i;
5655 
    input                   wb_cyc_i;
5656 
    output [dat_width-1:0]  wb_dat_o;
5657 
    reg [dat_width-1:0]     wb_dat_o;
5658 
    output                  wb_ack_o;
5659 
    reg                     wb_ack_o;
5660 
    output                  stall_o;
5661 
    input                   wb_clk;
5662 
    input                   wb_rst;
5663 
 
5664 
always @ (posedge wb_clk or posedge wb_rst)
5665 
    if (wb_rst)
5666 
        wb_dat_o <= {dat_width{1'b0}};
5667 
    else
5668 
         case (wb_adr_i[adr_width-1:2])
5669 
`ifdef ROM
5670 
`include `ROM
5671 
`endif
5672 
           default:
5673 
             wb_dat_o <= dat_default;
5674 
 
5675 
         endcase // case (wb_adr_i)
5676 
 
5677 
 
5678 
always @ (posedge wb_clk or posedge wb_rst)
5679 
    if (wb_rst)
5680 
        wb_ack_o <= 1'b0;
5681 
    else
5682 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
5683 
 
5684 
assign stall_o = 1'b0;
5685 
 
5686 
endmodule
5687 
`endif
5688 
 
5689 
 
5690 40 unneback 
`ifdef WB_BOOT_ROM
5691 17 unneback 
// WB ROM
5692 40 unneback 
`define MODULE wb_boot_rom
5693 
module `BASE`MODULE (
5694 
`undef MODULE
5695 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5696 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
5697 17 unneback 
 
5698 18 unneback 
    parameter adr_hi = 31;
5699 
    parameter adr_lo = 28;
5700 
    parameter adr_sel = 4'hf;
5701 
    parameter addr_width = 5;
5702 33 unneback 
/*
5703 17 unneback 
`ifndef BOOT_ROM
5704 
`define BOOT_ROM "boot_rom.v"
5705 
`endif
5706 33 unneback 
*/
5707 18 unneback 
    input [adr_hi:2]    wb_adr_i;
5708 
    input               wb_stb_i;
5709 
    input               wb_cyc_i;
5710 
    output [31:0]        wb_dat_o;
5711 
    output              wb_ack_o;
5712 
    output              hit_o;
5713 
    input               wb_clk;
5714 
    input               wb_rst;
5715 
 
5716 
    wire hit;
5717 
    reg [31:0] wb_dat;
5718 
    reg wb_ack;
5719 
 
5720 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
5721 17 unneback 
 
5722 
always @ (posedge wb_clk or posedge wb_rst)
5723 
    if (wb_rst)
5724 18 unneback 
        wb_dat <= 32'h15000000;
5725 17 unneback 
    else
5726 18 unneback 
         case (wb_adr_i[addr_width-1:2])
5727 33 unneback 
`ifdef BOOT_ROM
5728 17 unneback 
`include `BOOT_ROM
5729 33 unneback 
`endif
5730 17 unneback 
           /*
5731 
            // Zero r0 and jump to 0x00000100
5732 18 unneback 
 
5733 
            1 : wb_dat <= 32'hA8200000;
5734 
            2 : wb_dat <= 32'hA8C00100;
5735 
            3 : wb_dat <= 32'h44003000;
5736 
            4 : wb_dat <= 32'h15000000;
5737 17 unneback 
            */
5738 
           default:
5739 18 unneback 
             wb_dat <= 32'h00000000;
5740 17 unneback 
 
5741 
         endcase // case (wb_adr_i)
5742 
 
5743 
 
5744 
always @ (posedge wb_clk or posedge wb_rst)
5745 
    if (wb_rst)
5746 18 unneback 
        wb_ack <= 1'b0;
5747 17 unneback 
    else
5748 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
5749 17 unneback 
 
5750 18 unneback 
assign hit_o = hit;
5751 
assign wb_dat_o = wb_dat & {32{wb_ack}};
5752 
assign wb_ack_o = wb_ack;
5753 
 
5754 17 unneback 
endmodule
5755 40 unneback 
`endif
5756 32 unneback 
 
5757 92 unneback 
`ifdef WB_B3_DPRAM
5758 
`define MODULE wb_b3_dpram
5759 40 unneback 
module `BASE`MODULE (
5760 
`undef MODULE
5761 32 unneback 
        // wishbone slave side a
5762 92 unneback 
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
5763 32 unneback 
        wbsa_clk, wbsa_rst,
5764 92 unneback 
        // wishbone slave side b
5765 
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
5766 32 unneback 
        wbsb_clk, wbsb_rst);
5767 
 
5768 92 unneback 
parameter data_width_a = 32;
5769 
parameter data_width_b = data_width_a;
5770 
parameter addr_width_a = 8;
5771 
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
5772 
   parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
5773 
parameter max_burst_width_a = 4;
5774 
parameter max_burst_width_b = max_burst_width_a;
5775 32 unneback 
 
5776 92 unneback 
input [data_width_a-1:0] wbsa_dat_i;
5777 
input [addr_width_a-1:0] wbsa_adr_i;
5778 
input [data_width_a/8-1:0] wbsa_sel_i;
5779 
input [2:0] wbsa_cti_i;
5780 
input [1:0] wbsa_bte_i;
5781 32 unneback 
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
5782 92 unneback 
output [data_width_a-1:0] wbsa_dat_o;
5783 32 unneback 
output wbsa_ack_o;
5784 
input wbsa_clk, wbsa_rst;
5785 
 
5786 92 unneback 
input [data_width_b-1:0] wbsb_dat_i;
5787 
input [addr_width_b-1:0] wbsb_adr_i;
5788 
input [data_width_b/8-1:0] wbsb_sel_i;
5789 
input [2:0] wbsb_cti_i;
5790 
input [1:0] wbsb_bte_i;
5791 32 unneback 
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
5792 92 unneback 
output [data_width_b-1:0] wbsb_dat_o;
5793 32 unneback 
output wbsb_ack_o;
5794 
input wbsb_clk, wbsb_rst;
5795 
 
5796 92 unneback 
wire [addr_width_a-1:0] adr_a;
5797 
wire [addr_width_b-1:0] adr_b;
5798 32 unneback 
 
5799 92 unneback 
`define MODULE wb_adr_inc
5800 
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
5801 
    .cyc_i(wbsa_cyc_i),
5802 
    .stb_i(wbsa_stb_i),
5803 
    .cti_i(wbsa_cti_i),
5804 
    .bte_i(wbsa_bte_i),
5805 
    .adr_i(wbsa_adr_i),
5806 
    .we_i(wbsa_we_i),
5807 
    .ack_o(wbsa_ack_o),
5808 
    .adr_o(adr_a),
5809 
    .clk(wbsa_clk),
5810 
    .rst(wbsa_rst));
5811 
 
5812 
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
5813 
    .cyc_i(wbsb_cyc_i),
5814 
    .stb_i(wbsb_stb_i),
5815 
    .cti_i(wbsb_cti_i),
5816 
    .bte_i(wbsb_bte_i),
5817 
    .adr_i(wbsb_adr_i),
5818 
    .we_i(wbsb_we_i),
5819 
    .ack_o(wbsb_ack_o),
5820 
    .adr_o(adr_b),
5821 
    .clk(wbsb_clk),
5822 
    .rst(wbsb_rst));
5823 40 unneback 
`undef MODULE
5824 92 unneback 
 
5825 
`define MODULE dpram_be_2r2w
5826 
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
5827 
`undef MODULE
5828 
ram_i (
5829 32 unneback 
    .d_a(wbsa_dat_i),
5830 92 unneback 
    .q_a(wbsa_dat_o),
5831 
    .adr_a(adr_a),
5832 
    .be_a(wbsa_sel_i),
5833 
    .we_a(wbsa_we_i & wbsa_ack_o),
5834 32 unneback 
    .clk_a(wbsa_clk),
5835 
    .d_b(wbsb_dat_i),
5836 92 unneback 
    .q_b(wbsb_dat_o),
5837 
    .adr_b(adr_b),
5838 
    .be_b(wbsb_sel_i),
5839 
    .we_b(wbsb_we_i & wbsb_ack_o),
5840 32 unneback 
    .clk_b(wbsb_clk) );
5841 
 
5842 
endmodule
5843 40 unneback 
`endif
5844 94 unneback 
 
5845 97 unneback 
`ifdef WBB3_WBB4_CACHE
5846 
`define MODULE wbb3_wbb4_cache
5847 
module `BASE`MODULE (
5848 98 unneback 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5849 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
5850 97 unneback 
);
5851 
`undef MODULE
5852 
 
5853 
parameter dw_s = 32;
5854 
parameter aw_s = 24;
5855 
parameter dw_m = dw_s;
5856 
parameter aw_m = dw_s * aw_s / dw_m;
5857 
parameter max_burst_width = 4;
5858 
 
5859 
parameter async = 1; // wbs_clk != wbm_clk
5860 
 
5861 
parameter nr_of_ways = 1;
5862 
parameter aw_offset = 4; // 4 => 16 words per cache line
5863 
parameter aw_slot = 10;
5864 98 unneback 
localparam aw_tag = aw_s - aw_slot - aw_offset;
5865 97 unneback 
parameter wbm_burst_size = 4; // valid options 4,8,16
5866 98 unneback 
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
5867 97 unneback 
`define SIZE2WIDTH wbm_burst_size
5868 
localparam wbm_burst_width `SIZE2WIDTH_EXPR
5869 
`undef SIZE2WIDTH
5870 
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
5871 
`define SIZE2WIDTH nr_of_wbm_burst
5872 
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
5873 
`undef SIZE2WIDTH
5874 
input [dw_s-1:0] wbs_dat_i;
5875 
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
5876 98 unneback 
input [dw_s/8-1:0] wbs_sel_i;
5877 97 unneback 
input [2:0] wbs_cti_i;
5878 
input [1:0] wbs_bte_i;
5879 98 unneback 
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5880 97 unneback 
output [dw_s-1:0] wbs_dat_o;
5881 
output wbs_ack_o;
5882 
input wbs_clk, wbs_rst;
5883 
 
5884 
output [dw_m-1:0] wbm_dat_o;
5885 
output [aw_m-1:0] wbm_adr_o;
5886 
output [dw_m/8-1:0] wbm_sel_o;
5887 
output [2:0] wbm_cti_o;
5888 
output [1:0] wbm_bte_o;
5889 98 unneback 
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
5890 97 unneback 
input [dw_m-1:0] wbm_dat_i;
5891 
input wbm_ack_i;
5892 
input wbm_stall_i;
5893 
input wbm_clk, wbm_rst;
5894 
 
5895 
wire dirty, valid;
5896 
wire [aw_tag-1:0] tag;
5897 
wire tag_mem_we;
5898 
wire [aw_tag-1:0] wbs_adr_tag;
5899 
wire [aw_slot-1:0] wbs_adr_slot;
5900 98 unneback 
wire [aw_offset-1:0] wbs_adr_word;
5901 
wire [aw_s-1:0] wbs_adr;
5902 97 unneback 
 
5903 
reg [1:0] state;
5904 
localparam idle = 2'h0;
5905 
localparam rdwr = 2'h1;
5906 
localparam push = 2'h2;
5907 
localparam pull = 2'h3;
5908 
wire eoc;
5909 
 
5910 
// cdc
5911 
wire done, mem_alert, mem_done;
5912 
 
5913 98 unneback 
// wbm side
5914 
reg [aw_m-1:0] wbm_radr;
5915 
reg [aw_m-1:0] wbm_wadr;
5916 
wire [aw_slot+-1:0] wbm_adr;
5917 
wire wbm_radr_cke, wbm_wadr_cke;
5918 
 
5919 
reg [1:0] phase;
5920 
localparam wbm_wait = 2'b00;
5921 
localparam wbm_rd = 2'b10;
5922 
localparam wbm_wr = 2'b11;
5923 
 
5924 97 unneback 
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
5925 
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
5926 
 
5927 
`define MODULE ram
5928 
`BASE`MODULE
5929 98 unneback 
    # ( .data_width(aw_tag), .addr_width(aw_slot))
5930 97 unneback 
    tag_mem ( .d(wbs_adr_slot), .adr(wbs_adr_tag), .we(done), .q(tag), .clk(wbs_clk));
5931 
`undef MODULE
5932 
assign valid = wbs_adr_tag == tag;
5933 
 
5934 
`define MODULE wb_adr_inc
5935 98 unneback 
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(max_burst_width)) adr_inc0 (
5936 97 unneback 
    .cyc_i(wbs_cyc_i),
5937 
    .stb_i(wbs_stb_i & (state==idle | (state==rw & valid))), // throttle depending on valid
5938 
    .cti_i(wbs_cti_i),
5939 
    .bte_i(wbs_bte_i),
5940 
    .adr_i(wbs_adr_i),
5941 
    .we_i (wbs_we_i),
5942 
    .ack_o(wbs_ack_o),
5943 
    .adr_o(wbs_adr),
5944 
    .clk(wbsa_clk),
5945 
    .rst(wbsa_rst));
5946 
`undef MODULE
5947 
 
5948 
`define MODULE dpram_be_2r2w
5949 
`BASE`MODULE
5950 98 unneback 
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m) )
5951 
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(wbs_cyc_i &  wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
5952 
                .d_b(wbm_dat_i), .adr_b(wbm_adr), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
5953 97 unneback 
`undef MODULE
5954 
 
5955 
always @ (posedge wbs_clk or posedge wbs_rst)
5956 
if (wbs_rst)
5957 98 unneback 
    state <= idle;
5958 97 unneback 
else
5959 
    case (state)
5960 
    idle:
5961 
        if (wbs_cyc_i)
5962 
            state <= rdwr;
5963 
    rdwr:
5964 
        if (wbs_we_i & valid & eoc)
5965 
            state <= idle;
5966 
        else if (wbs_we_i & !valid)
5967 
            state <= pull;
5968 
        else if (!wbs_we_i & valid & eoc)
5969 
            state <= idle;
5970 
        else if (!wbs_we_i & !valid & !dirty)
5971 
            state <= pull;
5972 
        else if (!wbs_we_i & !valid & dirty)
5973 
            state <= push;
5974 
    push:
5975 
        if (done)
5976 
            state <= rdwr;
5977 
    pull:
5978 
        if (done)
5979 
            state <= rdwr;
5980 
    default: state <= idle;
5981 
    endcase
5982 
 
5983 
 
5984 
// cdc
5985 
generate
5986 
if (async==1) begin : cdc0
5987 
`define MODULE cdc
5988 
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & !valid), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
5989 
`undef MODULE
5990 
end
5991 
else begin : nocdc
5992 
    assign mem_alert = state==rdwr & !valid;
5993 
    assign done = mem_done;
5994 
end
5995 
endgenerate
5996 
 
5997 
// FSM generating a number of burts 4 cycles
5998 
// actual number depends on data width ratio
5999 
// nr_of_wbm_burst
6000 98 unneback 
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt0;
6001 
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt1;
6002 97 unneback 
 
6003 
always @ (posedge wbm_clk or posedge wbm_rst)
6004 
if (wbm_rst)
6005 98 unneback 
    cnt0 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
6006 97 unneback 
else
6007 98 unneback 
    if (wbm_radr_cke)
6008 
        cnt0 <= cnt0 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
6009 
assign wbm_radr_cke = wbm_cyc_o & wbm_stb_o & !wbm_stall_i;
6010 
assign wbm_radr = {wbs_adr_tag, tag, cnt0};
6011 97 unneback 
 
6012 98 unneback 
always @ (posedge wbm_clk or posedge wbm_rst)
6013 
if (wbm_rst)
6014 
    cnt1 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
6015 
else
6016 
    if (wbm_wadr_cke)
6017 
        cnt1 <= cnt1 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
6018 
assign wbm_wadr_cke = wbm_ack_i;
6019 
assign wbm_wadr = {wbs_adr_tag, wbs_adr_slot, cnt1};
6020 97 unneback 
 
6021 98 unneback 
always @ (posedge wbm_clk or posedge wbm_rst)
6022 
if (wbm_rst)
6023 
    phase <= wbm_wait;
6024 
else
6025 
    case (phase)
6026 
    wbm_wait:
6027 
        if (mem_alert)
6028 
            phase <= state;
6029 
    wbm_wr:
6030 
        if (&cnt1 & wbm_ack_i)
6031 
            phase <= wbm_rd;
6032 
    wbm_rd:
6033 
        if (&cnt0 & wbm_ack_i)
6034 
            phase <= idle;
6035 
    default: phase <= wbm_wait;
6036 
    endcase
6037 
 
6038 
assign wbm_adr_o = (phase==wbm_wr) ? {tag, wbs_adr_slot, cnt1} : {wbs_adr_tag, wbs_adr_slot, cnt1};
6039 
assign wbm_adr   = (phase==wbm_wr) ? {wbs_adr_slot, cnt1} : {wbs_adr_slot, cnt1};
6040 
assign wbm_cti_o = (&cnt0 | &cnt1) ? 3'b111 : 3'b010;
6041 
assign wbm_bte_o = bte;
6042 
assign wbm_we_o  = phase==wbm_wr;
6043 
 
6044 97 unneback 
endmodule
6045 
`endif
6046 18 unneback 
//////////////////////////////////////////////////////////////////////
6047 
////                                                              ////
6048 
////  Arithmetic functions                                        ////
6049 
////                                                              ////
6050 
////  Description                                                 ////
6051 
////  Arithmetic functions for ALU and DSP                        ////
6052 
////                                                              ////
6053 
////                                                              ////
6054 
////  To Do:                                                      ////
6055 
////   -                                                          ////
6056 
////                                                              ////
6057 
////  Author(s):                                                  ////
6058 
////      - Michael Unneback, unneback@opencores.org              ////
6059 
////        ORSoC AB                                              ////
6060 
////                                                              ////
6061 
//////////////////////////////////////////////////////////////////////
6062 
////                                                              ////
6063 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
6064 
////                                                              ////
6065 
//// This source file may be used and distributed without         ////
6066 
//// restriction provided that this copyright statement is not    ////
6067 
//// removed from the file and that any derivative work contains  ////
6068 
//// the original copyright notice and the associated disclaimer. ////
6069 
////                                                              ////
6070 
//// This source file is free software; you can redistribute it   ////
6071 
//// and/or modify it under the terms of the GNU Lesser General   ////
6072 
//// Public License as published by the Free Software Foundation; ////
6073 
//// either version 2.1 of the License, or (at your option) any   ////
6074 
//// later version.                                               ////
6075 
////                                                              ////
6076 
//// This source is distributed in the hope that it will be       ////
6077 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
6078 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
6079 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
6080 
//// details.                                                     ////
6081 
////                                                              ////
6082 
//// You should have received a copy of the GNU Lesser General    ////
6083 
//// Public License along with this source; if not, download it   ////
6084 
//// from http://www.opencores.org/lgpl.shtml                     ////
6085 
////                                                              ////
6086 
//////////////////////////////////////////////////////////////////////
6087 
 
6088 40 unneback 
`ifdef MULTS
6089 18 unneback 
// signed multiplication
6090 40 unneback 
`define MODULE mults
6091 
module `BASE`MODULE (a,b,p);
6092 
`undef MODULE
6093 18 unneback 
parameter operand_a_width = 18;
6094 
parameter operand_b_width = 18;
6095 
parameter result_hi = 35;
6096 
parameter result_lo = 0;
6097 
input [operand_a_width-1:0] a;
6098 
input [operand_b_width-1:0] b;
6099 
output [result_hi:result_lo] p;
6100 
wire signed [operand_a_width-1:0] ai;
6101 
wire signed [operand_b_width-1:0] bi;
6102 
wire signed [operand_a_width+operand_b_width-1:0] result;
6103 
 
6104 
    assign ai = a;
6105 
    assign bi = b;
6106 
    assign result = ai * bi;
6107 
    assign p = result[result_hi:result_lo];
6108 
 
6109 
endmodule
6110 40 unneback 
`endif
6111 
`ifdef MULTS18X18
6112 
`define MODULE mults18x18
6113 
module `BASE`MODULE (a,b,p);
6114 
`undef MODULE
6115 18 unneback 
input [17:0] a,b;
6116 
output [35:0] p;
6117 
vl_mult
6118 
    # (.operand_a_width(18), .operand_b_width(18))
6119 
    mult0 (.a(a), .b(b), .p(p));
6120 
endmodule
6121 40 unneback 
`endif
6122 18 unneback 
 
6123 40 unneback 
`ifdef MULT
6124 
`define MODULE mult
6125 18 unneback 
// unsigned multiplication
6126 40 unneback 
module `BASE`MODULE (a,b,p);
6127 
`undef MODULE
6128 18 unneback 
parameter operand_a_width = 18;
6129 
parameter operand_b_width = 18;
6130 
parameter result_hi = 35;
6131 
parameter result_lo = 0;
6132 
input [operand_a_width-1:0] a;
6133 
input [operand_b_width-1:0] b;
6134 
output [result_hi:result_hi] p;
6135 
 
6136 
wire [operand_a_width+operand_b_width-1:0] result;
6137 
 
6138 
    assign result = a * b;
6139 
    assign p = result[result_hi:result_lo];
6140 
 
6141 
endmodule
6142 40 unneback 
`endif
6143 18 unneback 
 
6144 40 unneback 
`ifdef SHIFT_UNIT_32
6145 
`define MODULE shift_unit_32
6146 18 unneback 
// shift unit
6147 
// supporting the following shift functions
6148 
//   SLL
6149 
//   SRL
6150 
//   SRA
6151 
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
6152 40 unneback 
module `BASE`MODULE( din, s, dout, opcode);
6153 
`undef MODULE
6154 18 unneback 
input [31:0] din; // data in operand
6155 
input [4:0] s; // shift operand
6156 
input [1:0] opcode;
6157 
output [31:0] dout;
6158 
 
6159 
parameter opcode_sll = 2'b00;
6160 
//parameter opcode_srl = 2'b01;
6161 
parameter opcode_sra = 2'b10;
6162 
//parameter opcode_ror = 2'b11;
6163 
 
6164 
wire sll, sra;
6165 
assign sll = opcode == opcode_sll;
6166 
assign sra = opcode == opcode_sra;
6167 
 
6168 
wire [15:1] s1;
6169 
wire [3:0] sign;
6170 
wire [7:0] tmp [0:3];
6171 
 
6172 
// first stage is multiplier based
6173 
// shift operand as fractional 8.7
6174 
assign s1[15] = sll & s[2:0]==3'd7;
6175 
assign s1[14] = sll & s[2:0]==3'd6;
6176 
assign s1[13] = sll & s[2:0]==3'd5;
6177 
assign s1[12] = sll & s[2:0]==3'd4;
6178 
assign s1[11] = sll & s[2:0]==3'd3;
6179 
assign s1[10] = sll & s[2:0]==3'd2;
6180 
assign s1[ 9] = sll & s[2:0]==3'd1;
6181 
assign s1[ 8] = s[2:0]==3'd0;
6182 
assign s1[ 7] = !sll & s[2:0]==3'd1;
6183 
assign s1[ 6] = !sll & s[2:0]==3'd2;
6184 
assign s1[ 5] = !sll & s[2:0]==3'd3;
6185 
assign s1[ 4] = !sll & s[2:0]==3'd4;
6186 
assign s1[ 3] = !sll & s[2:0]==3'd5;
6187 
assign s1[ 2] = !sll & s[2:0]==3'd6;
6188 
assign s1[ 1] = !sll & s[2:0]==3'd7;
6189 
 
6190 
assign sign[3] = din[31] & sra;
6191 
assign sign[2] = sign[3] & (&din[31:24]);
6192 
assign sign[1] = sign[2] & (&din[23:16]);
6193 
assign sign[0] = sign[1] & (&din[15:8]);
6194 40 unneback 
`define MODULE mults
6195 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
6196 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
6197 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
6198 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
6199 
`undef MODULE
6200 18 unneback 
// second stage is multiplexer based
6201 
// shift on byte level
6202 
 
6203 
// mux byte 3
6204 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
6205 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
6206 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
6207 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
6208 
                     {8{sign[3]}};
6209 
 
6210 
// mux byte 2
6211 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
6212 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
6213 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
6214 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
6215 
                     (s[4:3]==2'b01) ? tmp[3] :
6216 
                     {8{sign[3]}};
6217 
 
6218 
// mux byte 1
6219 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
6220 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
6221 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
6222 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
6223 
                     (s[4:3]==2'b01) ? tmp[2] :
6224 
                     (s[4:3]==2'b10) ? tmp[3] :
6225 
                     {8{sign[3]}};
6226 
 
6227 
// mux byte 0
6228 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
6229 
                     (sll) ?  {8{1'b0}}:
6230 
                     (s[4:3]==2'b01) ? tmp[1] :
6231 
                     (s[4:3]==2'b10) ? tmp[2] :
6232 
                     tmp[3];
6233 
 
6234 
endmodule
6235 40 unneback 
`endif
6236 18 unneback 
 
6237 40 unneback 
`ifdef LOGIC_UNIT
6238 18 unneback 
// logic unit
6239 
// supporting the following logic functions
6240 
//    a and b
6241 
//    a or  b
6242 
//    a xor b
6243 
//    not b
6244 40 unneback 
`define MODULE logic_unit
6245 
module `BASE`MODULE( a, b, result, opcode);
6246 
`undef MODULE
6247 18 unneback 
parameter width = 32;
6248 
parameter opcode_and = 2'b00;
6249 
parameter opcode_or  = 2'b01;
6250 
parameter opcode_xor = 2'b10;
6251 
input [width-1:0] a,b;
6252 
output [width-1:0] result;
6253 
input [1:0] opcode;
6254 
 
6255 
assign result = (opcode==opcode_and) ? a & b :
6256 
                (opcode==opcode_or)  ? a | b :
6257 
                (opcode==opcode_xor) ? a ^ b :
6258 
                b;
6259 
 
6260 
endmodule
6261 48 unneback 
`endif
6262 18 unneback 
 
6263 48 unneback 
`ifdef ARITH_UNIT
6264 
`define MODULE arith_unit
6265 
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
6266 
`undef MODULE
6267 18 unneback 
parameter width = 32;
6268 
parameter opcode_add = 1'b0;
6269 
parameter opcode_sub = 1'b1;
6270 
input [width-1:0] a,b;
6271 
input c_in, add_sub, sign;
6272 
output [width-1:0] result;
6273 
output c_out, z, ovfl;
6274 
 
6275 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
6276 
assign z = (result=={width{1'b0}});
6277 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
6278 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
6279 
endmodule
6280 40 unneback 
`endif
6281 48 unneback 
 
6282 
`ifdef COUNT_UNIT
6283 
`define MODULE count_unit
6284 
module `BASE`MODULE (din, dout, opcode);
6285 
`undef MODULE
6286 
parameter width = 32;
6287 
input [width-1:0] din;
6288 
output [width-1:0] dout;
6289 
input opcode;
6290 
 
6291 
integer i;
6292 58 unneback 
wire [width/32+4:0] ff1, fl1;
6293 48 unneback 
 
6294 57 unneback 
/*
6295 48 unneback 
always @(din) begin
6296 
    ff1 = 0; i = 0;
6297 
    while (din[i] == 0 && i < width) begin // complex condition
6298 
        ff1 = ff1 + 1;
6299 
        i = i + 1;
6300 
    end
6301 
end
6302 
 
6303 
always @(din) begin
6304 
    fl1 = width; i = width-1;
6305 
    while (din[i] == 0 && i >= width) begin // complex condition
6306 
        fl1 = fl1 - 1;
6307 
        i = i - 1;
6308 
    end
6309 
end
6310 57 unneback 
*/
6311 48 unneback 
 
6312 
generate
6313 
if (width==32) begin
6314 57 unneback 
 
6315 
    assign ff1 = din[0] ? 6'd1 :
6316 
                 din[1] ? 6'd2 :
6317 
                 din[2] ? 6'd3 :
6318 
                 din[3] ? 6'd4 :
6319 
                 din[4] ? 6'd5 :
6320 
                 din[5] ? 6'd6 :
6321 
                 din[6] ? 6'd7 :
6322 
                 din[7] ? 6'd8 :
6323 
                 din[8] ? 6'd9 :
6324 
                 din[9] ? 6'd10 :
6325 
                 din[10] ? 6'd11 :
6326 
                 din[11] ? 6'd12 :
6327 
                 din[12] ? 6'd13 :
6328 
                 din[13] ? 6'd14 :
6329 
                 din[14] ? 6'd15 :
6330 
                 din[15] ? 6'd16 :
6331 
                 din[16] ? 6'd17 :
6332 
                 din[17] ? 6'd18 :
6333 
                 din[18] ? 6'd19 :
6334 
                 din[19] ? 6'd20 :
6335 
                 din[20] ? 6'd21 :
6336 
                 din[21] ? 6'd22 :
6337 
                 din[22] ? 6'd23 :
6338 
                 din[23] ? 6'd24 :
6339 
                 din[24] ? 6'd25 :
6340 
                 din[25] ? 6'd26 :
6341 
                 din[26] ? 6'd27 :
6342 
                 din[27] ? 6'd28 :
6343 
                 din[28] ? 6'd29 :
6344 
                 din[29] ? 6'd30 :
6345 
                 din[30] ? 6'd31 :
6346 
                 din[31] ? 6'd32 :
6347 
                 6'd0;
6348 
 
6349 
    assign fl1 = din[31] ? 6'd32 :
6350 
                 din[30] ? 6'd31 :
6351 
                 din[29] ? 6'd30 :
6352 
                 din[28] ? 6'd29 :
6353 
                 din[27] ? 6'd28 :
6354 
                 din[26] ? 6'd27 :
6355 
                 din[25] ? 6'd26 :
6356 
                 din[24] ? 6'd25 :
6357 
                 din[23] ? 6'd24 :
6358 
                 din[22] ? 6'd23 :
6359 
                 din[21] ? 6'd22 :
6360 
                 din[20] ? 6'd21 :
6361 
                 din[19] ? 6'd20 :
6362 
                 din[18] ? 6'd19 :
6363 
                 din[17] ? 6'd18 :
6364 
                 din[16] ? 6'd17 :
6365 
                 din[15] ? 6'd16 :
6366 
                 din[14] ? 6'd15 :
6367 
                 din[13] ? 6'd14 :
6368 
                 din[12] ? 6'd13 :
6369 
                 din[11] ? 6'd12 :
6370 
                 din[10] ? 6'd11 :
6371 
                 din[9] ? 6'd10 :
6372 
                 din[8] ? 6'd9 :
6373 
                 din[7] ? 6'd8 :
6374 
                 din[6] ? 6'd7 :
6375 
                 din[5] ? 6'd6 :
6376 
                 din[4] ? 6'd5 :
6377 
                 din[3] ? 6'd4 :
6378 
                 din[2] ? 6'd3 :
6379 
                 din[1] ? 6'd2 :
6380 
                 din[0] ? 6'd1 :
6381 
                 6'd0;
6382 
 
6383 
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
6384 48 unneback 
end
6385 
endgenerate
6386 57 unneback 
 
6387 48 unneback 
generate
6388 
if (width==64) begin
6389 57 unneback 
    assign ff1 = 7'd0;
6390 
    assign fl1 = 7'd0;
6391 
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
6392 48 unneback 
end
6393 
endgenerate
6394 
 
6395 
endmodule
6396 
`endif
6397 
 
6398 
`ifdef EXT_UNIT
6399 
`define MODULE ext_unit
6400 
module `BASE`MODULE ( a, b, F, result, opcode);
6401 
`undef MODULE
6402 
parameter width = 32;
6403 
input [width-1:0] a, b;
6404 
input F;
6405 
output reg [width-1:0] result;
6406 
input [2:0] opcode;
6407 
 
6408 
generate
6409 
if (width==32) begin
6410 
always @ (a or b or F or opcode)
6411 
begin
6412 
    case (opcode)
6413 
    3'b000: result = {{24{1'b0}},a[7:0]};
6414 
    3'b001: result = {{24{a[7]}},a[7:0]};
6415 
    3'b010: result = {{16{1'b0}},a[7:0]};
6416 
    3'b011: result = {{16{a[15]}},a[15:0]};
6417 
    3'b110: result = (F) ? a : b;
6418 
    default: result = {b[15:0],16'h0000};
6419 
    endcase
6420 
end
6421 
end
6422 
endgenerate
6423 
 
6424 
generate
6425 
if (width==64) begin
6426 
always @ (a or b or F or opcode)
6427 
begin
6428 
    case (opcode)
6429 
    3'b000: result = {{56{1'b0}},a[7:0]};
6430 
    3'b001: result = {{56{a[7]}},a[7:0]};
6431 
    3'b010: result = {{48{1'b0}},a[7:0]};
6432 
    3'b011: result = {{48{a[15]}},a[15:0]};
6433 57 unneback 
    3'b110: result = (F) ? a : b;
6434 48 unneback 
    default: result = {32'h00000000,b[15:0],16'h0000};
6435 
    endcase
6436 
end
6437 
end
6438 
endgenerate
6439 
endmodule
6440 
`endif

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