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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Blame information for rev 137

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Line No. Rev Author Line
1 60 unneback
// default SYN_KEEP definition
2 98 unneback
    // ACTEL FPGA should not use logic to handle rw collision
3 136 unneback
///////////////////////////////////////
4
// dependencies
5
///////////////////////////////////////
6 97 unneback
// size to width
7 6 unneback
//////////////////////////////////////////////////////////////////////
8
////                                                              ////
9
////  Versatile library, clock and reset                          ////
10
////                                                              ////
11
////  Description                                                 ////
12
////  Logic related to clock and reset                            ////
13
////                                                              ////
14
////                                                              ////
15
////  To Do:                                                      ////
16
////   - add more different registers                             ////
17
////                                                              ////
18
////  Author(s):                                                  ////
19
////      - Michael Unneback, unneback@opencores.org              ////
20
////        ORSoC AB                                              ////
21
////                                                              ////
22
//////////////////////////////////////////////////////////////////////
23
////                                                              ////
24
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
25
////                                                              ////
26
//// This source file may be used and distributed without         ////
27
//// restriction provided that this copyright statement is not    ////
28
//// removed from the file and that any derivative work contains  ////
29
//// the original copyright notice and the associated disclaimer. ////
30
////                                                              ////
31
//// This source file is free software; you can redistribute it   ////
32
//// and/or modify it under the terms of the GNU Lesser General   ////
33
//// Public License as published by the Free Software Foundation; ////
34
//// either version 2.1 of the License, or (at your option) any   ////
35
//// later version.                                               ////
36
////                                                              ////
37
//// This source is distributed in the hope that it will be       ////
38
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
39
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
40
//// PURPOSE.  See the GNU Lesser General Public License for more ////
41
//// details.                                                     ////
42
////                                                              ////
43
//// You should have received a copy of the GNU Lesser General    ////
44
//// Public License along with this source; if not, download it   ////
45
//// from http://www.opencores.org/lgpl.shtml                     ////
46
////                                                              ////
47
//////////////////////////////////////////////////////////////////////
48 48 unneback
`timescale 1 ns/100 ps
49 6 unneback
// Global buffer
50
// usage:
51
// use to enable global buffers for high fan out signals such as clock and reset
52
// Version: 8.4 8.4.0.33
53
module gbuf(GL,CLK);
54
output GL;
55
input  CLK;
56
    wire GND;
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
endmodule
61
`timescale 1 ns/1 ns
62
module vl_gbuf ( i, o);
63
input i;
64
output o;
65
`ifdef SIM_GBUF
66
assign o=i;
67
`else
68
gbuf gbuf_i0 ( .CLK(i), .GL(o));
69
`endif
70
endmodule
71
 //ACTEL
72
// sync reset
73 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
74 6 unneback
// output active high global reset sync with two DFFs 
75
`timescale 1 ns/100 ps
76
module vl_sync_rst ( rst_n_i, rst_o, clk);
77
input rst_n_i, clk;
78
output rst_o;
79 18 unneback
reg [1:0] tmp;
80 6 unneback
always @ (posedge clk or negedge rst_n_i)
81
if (!rst_n_i)
82 17 unneback
        tmp <= 2'b11;
83 6 unneback
else
84 33 unneback
        tmp <= {1'b0,tmp[1]};
85 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
86 6 unneback
endmodule
87
// vl_pll
88 32 unneback
///////////////////////////////////////////////////////////////////////////////
89 17 unneback
`timescale 1 ps/1 ps
90 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
91
parameter index = 0;
92
parameter number_of_clk = 1;
93 17 unneback
parameter period_time_0 = 20000;
94
parameter period_time_1 = 20000;
95
parameter period_time_2 = 20000;
96
parameter lock_delay = 2000000;
97 6 unneback
input clk_i, rst_n_i;
98
output lock;
99
output reg [0:number_of_clk-1] clk_o;
100
output [0:number_of_clk-1] rst_o;
101
`ifdef SIM_PLL
102
always
103
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
104
generate if (number_of_clk > 1)
105
always
106
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
107
endgenerate
108
generate if (number_of_clk > 2)
109
always
110
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
111
endgenerate
112
genvar i;
113
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
114
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
115
end
116
endgenerate
117
assign #lock_delay lock = rst_n_i;
118
endmodule
119
`else
120
generate if (number_of_clk==1 & index==0) begin
121
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
122
end
123
endgenerate // index==0
124
generate if (number_of_clk==1 & index==1) begin
125
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
126
end
127
endgenerate // index==1
128
generate if (number_of_clk==1 & index==2) begin
129
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
130
end
131
endgenerate // index==2
132
generate if (number_of_clk==1 & index==3) begin
133
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
134
end
135
endgenerate // index==0
136
generate if (number_of_clk==2 & index==0) begin
137
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
138
end
139
endgenerate // index==0
140
generate if (number_of_clk==2 & index==1) begin
141
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
142
end
143
endgenerate // index==1
144
generate if (number_of_clk==2 & index==2) begin
145
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
146
end
147
endgenerate // index==2
148
generate if (number_of_clk==2 & index==3) begin
149
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
150
end
151
endgenerate // index==0
152
generate if (number_of_clk==3 & index==0) begin
153
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
154
end
155
endgenerate // index==0
156
generate if (number_of_clk==3 & index==1) begin
157
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
158
end
159
endgenerate // index==1
160
generate if (number_of_clk==3 & index==2) begin
161
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
162
end
163
endgenerate // index==2
164
generate if (number_of_clk==3 & index==3) begin
165
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
166
end
167
endgenerate // index==0
168
genvar i;
169
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
170 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
171 6 unneback
end
172
endgenerate
173
endmodule
174
`endif
175 32 unneback
///////////////////////////////////////////////////////////////////////////////
176 6 unneback
 //actel
177
//////////////////////////////////////////////////////////////////////
178
////                                                              ////
179
////  Versatile library, registers                                ////
180
////                                                              ////
181
////  Description                                                 ////
182
////  Different type of registers                                 ////
183
////                                                              ////
184
////                                                              ////
185
////  To Do:                                                      ////
186
////   - add more different registers                             ////
187
////                                                              ////
188
////  Author(s):                                                  ////
189
////      - Michael Unneback, unneback@opencores.org              ////
190
////        ORSoC AB                                              ////
191
////                                                              ////
192
//////////////////////////////////////////////////////////////////////
193
////                                                              ////
194
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
195
////                                                              ////
196
//// This source file may be used and distributed without         ////
197
//// restriction provided that this copyright statement is not    ////
198
//// removed from the file and that any derivative work contains  ////
199
//// the original copyright notice and the associated disclaimer. ////
200
////                                                              ////
201
//// This source file is free software; you can redistribute it   ////
202
//// and/or modify it under the terms of the GNU Lesser General   ////
203
//// Public License as published by the Free Software Foundation; ////
204
//// either version 2.1 of the License, or (at your option) any   ////
205
//// later version.                                               ////
206
////                                                              ////
207
//// This source is distributed in the hope that it will be       ////
208
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
209
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
210
//// PURPOSE.  See the GNU Lesser General Public License for more ////
211
//// details.                                                     ////
212
////                                                              ////
213
//// You should have received a copy of the GNU Lesser General    ////
214
//// Public License along with this source; if not, download it   ////
215
//// from http://www.opencores.org/lgpl.shtml                     ////
216
////                                                              ////
217
//////////////////////////////////////////////////////////////////////
218 18 unneback
module vl_dff ( d, q, clk, rst);
219 6 unneback
        parameter width = 1;
220
        parameter reset_value = 0;
221
        input [width-1:0] d;
222
        input clk, rst;
223
        output reg [width-1:0] q;
224
        always @ (posedge clk or posedge rst)
225
        if (rst)
226
                q <= reset_value;
227
        else
228
                q <= d;
229
endmodule
230 18 unneback
module vl_dff_array ( d, q, clk, rst);
231 6 unneback
        parameter width = 1;
232
        parameter depth = 2;
233
        parameter reset_value = 1'b0;
234
        input [width-1:0] d;
235
        input clk, rst;
236
        output [width-1:0] q;
237
        reg  [0:depth-1] q_tmp [width-1:0];
238
        integer i;
239
        always @ (posedge clk or posedge rst)
240
        if (rst) begin
241
            for (i=0;i<depth;i=i+1)
242
                q_tmp[i] <= {width{reset_value}};
243
        end else begin
244
            q_tmp[0] <= d;
245
            for (i=1;i<depth;i=i+1)
246
                q_tmp[i] <= q_tmp[i-1];
247
        end
248
    assign q = q_tmp[depth-1];
249
endmodule
250 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
251 6 unneback
        parameter width = 1;
252
        parameter reset_value = 0;
253
        input [width-1:0] d;
254
        input ce, clk, rst;
255
        output reg [width-1:0] q;
256
        always @ (posedge clk or posedge rst)
257
        if (rst)
258
                q <= reset_value;
259
        else
260
                if (ce)
261
                        q <= d;
262
endmodule
263 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
264 8 unneback
        parameter width = 1;
265
        parameter reset_value = 0;
266
        input [width-1:0] d;
267 10 unneback
        input ce, clear, clk, rst;
268 8 unneback
        output reg [width-1:0] q;
269
        always @ (posedge clk or posedge rst)
270
        if (rst)
271
            q <= reset_value;
272
        else
273
            if (ce)
274
                if (clear)
275
                    q <= {width{1'b0}};
276
                else
277
                    q <= d;
278
endmodule
279 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
280
        parameter width = 1;
281
        parameter reset_value = 0;
282
        input [width-1:0] d;
283
        input ce, set, clk, rst;
284
        output reg [width-1:0] q;
285
        always @ (posedge clk or posedge rst)
286
        if (rst)
287
            q <= reset_value;
288
        else
289
            if (ce)
290
                if (set)
291
                    q <= {width{1'b1}};
292
                else
293
                    q <= d;
294
endmodule
295 29 unneback
module vl_spr ( sp, r, q, clk, rst);
296 64 unneback
        //parameter width = 1;
297
        parameter reset_value = 1'b0;
298 29 unneback
        input sp, r;
299
        output reg q;
300
        input clk, rst;
301
        always @ (posedge clk or posedge rst)
302
        if (rst)
303
            q <= reset_value;
304
        else
305
            if (sp)
306
                q <= 1'b1;
307
            else if (r)
308
                q <= 1'b0;
309
endmodule
310
module vl_srp ( s, rp, q, clk, rst);
311
        parameter width = 1;
312
        parameter reset_value = 0;
313
        input s, rp;
314
        output reg q;
315
        input clk, rst;
316
        always @ (posedge clk or posedge rst)
317
        if (rst)
318
            q <= reset_value;
319
        else
320
            if (rp)
321
                q <= 1'b0;
322
            else if (s)
323
                q <= 1'b1;
324
endmodule
325 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
326 6 unneback
    input         aclr;
327
    input         aset;
328
    input         clock;
329
    input         data;
330
    output reg    q;
331
   always @ (posedge clock or posedge aclr or posedge aset)
332
     if (aclr)
333
       q <= 1'b0;
334
     else if (aset)
335
       q <= 1'b1;
336
     else
337
       q <= data;
338
endmodule
339
// LATCH
340
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
341 40 unneback
module vl_latch ( d, le, q, clk);
342 6 unneback
input d, le;
343 48 unneback
input clk;
344
always @ (le or d)
345 60 unneback
if (le)
346 48 unneback
    d <= q;
347 6 unneback
endmodule
348 18 unneback
module vl_shreg ( d, q, clk, rst);
349 17 unneback
parameter depth = 10;
350
input d;
351
output q;
352
input clk, rst;
353
reg [1:depth] dffs;
354
always @ (posedge clk or posedge rst)
355
if (rst)
356
    dffs <= {depth{1'b0}};
357
else
358
    dffs <= {d,dffs[1:depth-1]};
359
assign q = dffs[depth];
360
endmodule
361 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
362 17 unneback
parameter depth = 10;
363
input d, ce;
364
output q;
365
input clk, rst;
366
reg [1:depth] dffs;
367
always @ (posedge clk or posedge rst)
368
if (rst)
369
    dffs <= {depth{1'b0}};
370
else
371
    if (ce)
372
        dffs <= {d,dffs[1:depth-1]};
373
assign q = dffs[depth];
374
endmodule
375 18 unneback
module vl_delay ( d, q, clk, rst);
376 15 unneback
parameter depth = 10;
377
input d;
378
output q;
379
input clk, rst;
380
reg [1:depth] dffs;
381
always @ (posedge clk or posedge rst)
382
if (rst)
383
    dffs <= {depth{1'b0}};
384
else
385
    dffs <= {d,dffs[1:depth-1]};
386
assign q = dffs[depth];
387
endmodule
388 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
389 17 unneback
parameter depth = 10;
390
input d;
391
output q, emptyflag;
392
input clk, rst;
393
reg [1:depth] dffs;
394
always @ (posedge clk or posedge rst)
395
if (rst)
396
    dffs <= {depth{1'b0}};
397
else
398
    dffs <= {d,dffs[1:depth-1]};
399
assign q = dffs[depth];
400
assign emptyflag = !(|dffs);
401
endmodule
402 98 unneback
module vl_pulse2toggle ( pl, q, clk, rst);
403 94 unneback
input pl;
404 98 unneback
output reg q;
405 94 unneback
input clk, rst;
406
always @ (posedge clk or posedge rst)
407
if (rst)
408
    q <= 1'b0;
409
else
410
    q <= pl ^ q;
411
endmodule
412 98 unneback
module vl_toggle2pulse (d, pl, clk, rst);
413 94 unneback
input d;
414
output pl;
415
input clk, rst;
416
reg dff;
417
always @ (posedge clk or posedge rst)
418
if (rst)
419
    dff <= 1'b0;
420
else
421
    dff <= d;
422 98 unneback
assign pl = d ^ dff;
423 94 unneback
endmodule
424
module vl_synchronizer (d, q, clk, rst);
425
input d;
426
output reg q;
427 116 unneback
input clk, rst;
428 94 unneback
reg dff;
429
always @ (posedge clk or posedge rst)
430
if (rst)
431 100 unneback
    {q,dff} <= 2'b00;
432 94 unneback
else
433 100 unneback
    {q,dff} <= {dff,d};
434 94 unneback
endmodule
435 97 unneback
module vl_cdc ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
436 94 unneback
input start_pl;
437
output take_it_pl;
438
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
439
output got_it_pl;
440
input clk_src, rst_src;
441
input clk_dst, rst_dst;
442
wire take_it_tg, take_it_tg_sync;
443
wire got_it_tg, got_it_tg_sync;
444
// src -> dst
445
vl_pulse2toggle p2t0 (
446
    .pl(start_pl),
447
    .q(take_it_tg),
448
    .clk(clk_src),
449
    .rst(rst_src));
450
vl_synchronizer sync0 (
451
    .d(take_it_tg),
452
    .q(take_it_tg_sync),
453
    .clk(clk_dst),
454
    .rst(rst_dst));
455
vl_toggle2pulse t2p0 (
456 100 unneback
    .d(take_it_tg_sync),
457 94 unneback
    .pl(take_it_pl),
458
    .clk(clk_dst),
459
    .rst(rst_dst));
460
// dst -> src
461 98 unneback
vl_pulse2toggle p2t1 (
462 94 unneback
    .pl(take_it_grant_pl),
463
    .q(got_it_tg),
464
    .clk(clk_dst),
465
    .rst(rst_dst));
466
vl_synchronizer sync1 (
467
    .d(got_it_tg),
468
    .q(got_it_tg_sync),
469
    .clk(clk_src),
470
    .rst(rst_src));
471
vl_toggle2pulse t2p1 (
472 100 unneback
    .d(got_it_tg_sync),
473 94 unneback
    .pl(got_it_pl),
474
    .clk(clk_src),
475
    .rst(rst_src));
476
endmodule
477 6 unneback
//////////////////////////////////////////////////////////////////////
478
////                                                              ////
479 18 unneback
////  Logic functions                                             ////
480
////                                                              ////
481
////  Description                                                 ////
482
////  Logic functions such as multiplexers                        ////
483
////                                                              ////
484
////                                                              ////
485
////  To Do:                                                      ////
486
////   -                                                          ////
487
////                                                              ////
488
////  Author(s):                                                  ////
489
////      - Michael Unneback, unneback@opencores.org              ////
490
////        ORSoC AB                                              ////
491
////                                                              ////
492
//////////////////////////////////////////////////////////////////////
493
////                                                              ////
494
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
495
////                                                              ////
496
//// This source file may be used and distributed without         ////
497
//// restriction provided that this copyright statement is not    ////
498
//// removed from the file and that any derivative work contains  ////
499
//// the original copyright notice and the associated disclaimer. ////
500
////                                                              ////
501
//// This source file is free software; you can redistribute it   ////
502
//// and/or modify it under the terms of the GNU Lesser General   ////
503
//// Public License as published by the Free Software Foundation; ////
504
//// either version 2.1 of the License, or (at your option) any   ////
505
//// later version.                                               ////
506
////                                                              ////
507
//// This source is distributed in the hope that it will be       ////
508
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
509
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
510
//// PURPOSE.  See the GNU Lesser General Public License for more ////
511
//// details.                                                     ////
512
////                                                              ////
513
//// You should have received a copy of the GNU Lesser General    ////
514
//// Public License along with this source; if not, download it   ////
515
//// from http://www.opencores.org/lgpl.shtml                     ////
516
////                                                              ////
517
//////////////////////////////////////////////////////////////////////
518 36 unneback
module vl_mux_andor ( a, sel, dout);
519
parameter width = 32;
520
parameter nr_of_ports = 4;
521
input [nr_of_ports*width-1:0] a;
522
input [nr_of_ports-1:0] sel;
523
output reg [width-1:0] dout;
524 38 unneback
integer i,j;
525 36 unneback
always @ (a, sel)
526
begin
527
    dout = a[width-1:0] & {width{sel[0]}};
528 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
529
        for (j=0;j<width;j=j+1)
530
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
531 36 unneback
end
532
endmodule
533 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
534
parameter width = 32;
535 35 unneback
localparam nr_of_ports = 2;
536 34 unneback
input [width-1:0] a1, a0;
537
input [nr_of_ports-1:0] sel;
538
output [width-1:0] dout;
539 36 unneback
vl_mux_andor
540 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
541 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
542 34 unneback
endmodule
543
module vl_mux3_andor ( a2, a1, a0, sel, dout);
544
parameter width = 32;
545 35 unneback
localparam nr_of_ports = 3;
546 34 unneback
input [width-1:0] a2, a1, a0;
547
input [nr_of_ports-1:0] sel;
548
output [width-1:0] dout;
549 36 unneback
vl_mux_andor
550 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
551 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
552 34 unneback
endmodule
553 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
554
parameter width = 32;
555 35 unneback
localparam nr_of_ports = 4;
556 18 unneback
input [width-1:0] a3, a2, a1, a0;
557
input [nr_of_ports-1:0] sel;
558 22 unneback
output [width-1:0] dout;
559 36 unneback
vl_mux_andor
560 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
561 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
562 18 unneback
endmodule
563
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
564
parameter width = 32;
565 35 unneback
localparam nr_of_ports = 5;
566 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
567
input [nr_of_ports-1:0] sel;
568 22 unneback
output [width-1:0] dout;
569 36 unneback
vl_mux_andor
570 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
571 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
572 18 unneback
endmodule
573
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
574
parameter width = 32;
575 35 unneback
localparam nr_of_ports = 6;
576 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
577
input [nr_of_ports-1:0] sel;
578 22 unneback
output [width-1:0] dout;
579 36 unneback
vl_mux_andor
580 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
581 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
582 18 unneback
endmodule
583 43 unneback
module vl_parity_generate (data, parity);
584
parameter word_size = 32;
585
parameter chunk_size = 8;
586
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
587
input [word_size-1:0] data;
588
output reg [word_size/chunk_size-1:0] parity;
589
integer i,j;
590
always @ (data)
591
for (i=0;i<word_size/chunk_size;i=i+1) begin
592
    parity[i] = parity_type;
593
    for (j=0;j<chunk_size;j=j+1) begin
594 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
595 43 unneback
    end
596
end
597
endmodule
598
module vl_parity_check( data, parity, parity_error);
599
parameter word_size = 32;
600
parameter chunk_size = 8;
601
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
602
input [word_size-1:0] data;
603
input [word_size/chunk_size-1:0] parity;
604
output parity_error;
605 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
606 43 unneback
integer i,j;
607
always @ (data or parity)
608
for (i=0;i<word_size/chunk_size;i=i+1) begin
609
    error_flag[i] = parity[i] ^ parity_type;
610
    for (j=0;j<chunk_size;j=j+1) begin
611 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
612 43 unneback
    end
613
end
614
assign parity_error = |error_flag;
615
endmodule
616 18 unneback
//////////////////////////////////////////////////////////////////////
617
////                                                              ////
618 44 unneback
////  IO functions                                                ////
619
////                                                              ////
620
////  Description                                                 ////
621
////  IO functions such as IOB flip-flops                         ////
622
////                                                              ////
623
////                                                              ////
624
////  To Do:                                                      ////
625
////   -                                                          ////
626
////                                                              ////
627
////  Author(s):                                                  ////
628
////      - Michael Unneback, unneback@opencores.org              ////
629
////        ORSoC AB                                              ////
630
////                                                              ////
631
//////////////////////////////////////////////////////////////////////
632
////                                                              ////
633
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
634
////                                                              ////
635
//// This source file may be used and distributed without         ////
636
//// restriction provided that this copyright statement is not    ////
637
//// removed from the file and that any derivative work contains  ////
638
//// the original copyright notice and the associated disclaimer. ////
639
////                                                              ////
640
//// This source file is free software; you can redistribute it   ////
641
//// and/or modify it under the terms of the GNU Lesser General   ////
642
//// Public License as published by the Free Software Foundation; ////
643
//// either version 2.1 of the License, or (at your option) any   ////
644
//// later version.                                               ////
645
////                                                              ////
646
//// This source is distributed in the hope that it will be       ////
647
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
648
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
649
//// PURPOSE.  See the GNU Lesser General Public License for more ////
650
//// details.                                                     ////
651
////                                                              ////
652
//// You should have received a copy of the GNU Lesser General    ////
653
//// Public License along with this source; if not, download it   ////
654
//// from http://www.opencores.org/lgpl.shtml                     ////
655
////                                                              ////
656
//////////////////////////////////////////////////////////////////////
657 45 unneback
`timescale 1ns/1ns
658 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
659
parameter width = 1;
660 45 unneback
parameter reset_value = {width{1'b0}};
661
input  [width-1:0]  d_i;
662 44 unneback
output [width-1:0] o_pad;
663
input clk, rst;
664
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
665 45 unneback
reg  [width-1:0] o_pad_int;
666 44 unneback
assign d_i_int = d_i;
667
genvar i;
668 45 unneback
generate
669 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
670 44 unneback
    always @ (posedge clk or posedge rst)
671
    if (rst)
672 45 unneback
        o_pad_int[i] <= reset_value[i];
673 44 unneback
    else
674 45 unneback
        o_pad_int[i] <= d_i_int[i];
675
    assign #1 o_pad[i] = o_pad_int[i];
676 44 unneback
end
677
endgenerate
678
endmodule
679 45 unneback
`timescale 1ns/1ns
680 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
681
parameter width = 1;
682
input  [width-1:0] d_o;
683
output reg [width-1:0] d_i;
684
input oe;
685
inout [width-1:0] io_pad;
686
input clk, rst;
687
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
688
reg [width-1:0] oe_q;
689
reg [width-1:0] d_o_q;
690
assign oe_d = {width{oe}};
691
genvar i;
692
generate
693 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
694 44 unneback
    always @ (posedge clk or posedge rst)
695
    if (rst)
696
        oe_q[i] <= 1'b0;
697
    else
698
        oe_q[i] <= oe_d[i];
699
    always @ (posedge clk or posedge rst)
700
    if (rst)
701
        d_o_q[i] <= 1'b0;
702
    else
703
        d_o_q[i] <= d_o[i];
704
    always @ (posedge clk or posedge rst)
705
    if (rst)
706
        d_i[i] <= 1'b0;
707
    else
708
        d_i[i] <= io_pad[i];
709 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
710 44 unneback
end
711
endgenerate
712
endmodule
713 136 unneback
module vl_o_ddr (d_h_i, d_l_i, o_pad, clk, rst);
714
parameter width = 1;
715
input  [width-1:0] d_h_i, d_l_i;
716
output [width-1:0] o_pad;
717
input clk, rst;
718
reg [width-1:0] ff1;
719
reg [width-1:0] ff2;
720
genvar i;
721
generate
722
for (i=0;i<width;i=i+1) begin : ddr
723
    always @ (posedge clk or posedge rst)
724
    if (rst)
725
        ff1[i] <= 1'b0;
726
    else
727
        ff1[i] <= d_h_i[i];
728
    always @ (posedge clk or posedge rst)
729
    if (rst)
730
        ff2[i] <= 1'b0;
731
    else
732
        ff2[i] <= d_l_i[i];
733
    assign o_pad = (clk) ? ff1 : ff2;
734
end
735
endgenerate
736
endmodule
737
module vl_o_clk ( clk_o_pad, clk, rst);
738
input clk, rst;
739
output clk_o_pad;
740
vl_o_ddr o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
741
endmodule
742 44 unneback
//////////////////////////////////////////////////////////////////////
743
////                                                              ////
744 6 unneback
////  Versatile counter                                           ////
745
////                                                              ////
746
////  Description                                                 ////
747
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
748
////  counter                                                     ////
749
////                                                              ////
750
////  To Do:                                                      ////
751
////   - add LFSR with more taps                                  ////
752
////                                                              ////
753
////  Author(s):                                                  ////
754
////      - Michael Unneback, unneback@opencores.org              ////
755
////        ORSoC AB                                              ////
756
////                                                              ////
757
//////////////////////////////////////////////////////////////////////
758
////                                                              ////
759
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
760
////                                                              ////
761
//// This source file may be used and distributed without         ////
762
//// restriction provided that this copyright statement is not    ////
763
//// removed from the file and that any derivative work contains  ////
764
//// the original copyright notice and the associated disclaimer. ////
765
////                                                              ////
766
//// This source file is free software; you can redistribute it   ////
767
//// and/or modify it under the terms of the GNU Lesser General   ////
768
//// Public License as published by the Free Software Foundation; ////
769
//// either version 2.1 of the License, or (at your option) any   ////
770
//// later version.                                               ////
771
////                                                              ////
772
//// This source is distributed in the hope that it will be       ////
773
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
774
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
775
//// PURPOSE.  See the GNU Lesser General Public License for more ////
776
//// details.                                                     ////
777
////                                                              ////
778
//// You should have received a copy of the GNU Lesser General    ////
779
//// Public License along with this source; if not, download it   ////
780
//// from http://www.opencores.org/lgpl.shtml                     ////
781
////                                                              ////
782
//////////////////////////////////////////////////////////////////////
783
// binary counter
784 40 unneback
module vl_cnt_bin_ce (
785
 cke, q, rst, clk);
786 22 unneback
   parameter length = 4;
787 6 unneback
   input cke;
788
   output [length:1] q;
789
   input rst;
790
   input clk;
791
   parameter clear_value = 0;
792
   parameter set_value = 1;
793
   parameter wrap_value = 0;
794
   parameter level1_value = 15;
795
   reg  [length:1] qi;
796
   wire [length:1] q_next;
797
   assign q_next = qi + {{length-1{1'b0}},1'b1};
798
   always @ (posedge clk or posedge rst)
799
     if (rst)
800
       qi <= {length{1'b0}};
801
     else
802
     if (cke)
803
       qi <= q_next;
804
   assign q = qi;
805
endmodule
806
//////////////////////////////////////////////////////////////////////
807
////                                                              ////
808
////  Versatile counter                                           ////
809
////                                                              ////
810
////  Description                                                 ////
811
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
812
////  counter                                                     ////
813
////                                                              ////
814
////  To Do:                                                      ////
815
////   - add LFSR with more taps                                  ////
816
////                                                              ////
817
////  Author(s):                                                  ////
818
////      - Michael Unneback, unneback@opencores.org              ////
819
////        ORSoC AB                                              ////
820
////                                                              ////
821
//////////////////////////////////////////////////////////////////////
822
////                                                              ////
823
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
824
////                                                              ////
825
//// This source file may be used and distributed without         ////
826
//// restriction provided that this copyright statement is not    ////
827
//// removed from the file and that any derivative work contains  ////
828
//// the original copyright notice and the associated disclaimer. ////
829
////                                                              ////
830
//// This source file is free software; you can redistribute it   ////
831
//// and/or modify it under the terms of the GNU Lesser General   ////
832
//// Public License as published by the Free Software Foundation; ////
833
//// either version 2.1 of the License, or (at your option) any   ////
834
//// later version.                                               ////
835
////                                                              ////
836
//// This source is distributed in the hope that it will be       ////
837
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
838
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
839
//// PURPOSE.  See the GNU Lesser General Public License for more ////
840
//// details.                                                     ////
841
////                                                              ////
842
//// You should have received a copy of the GNU Lesser General    ////
843
//// Public License along with this source; if not, download it   ////
844
//// from http://www.opencores.org/lgpl.shtml                     ////
845
////                                                              ////
846
//////////////////////////////////////////////////////////////////////
847
// binary counter
848 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
849
 cke, rew, zq, level1, rst, clk);
850 6 unneback
   parameter length = 4;
851
   input cke;
852
   input rew;
853 25 unneback
   output reg zq;
854
   output reg level1;
855
   input rst;
856
   input clk;
857
   parameter clear_value = 0;
858
   parameter set_value = 1;
859
   parameter wrap_value = 1;
860
   parameter level1_value = 15;
861 29 unneback
   wire clear;
862 30 unneback
   assign clear = 1'b0;
863 25 unneback
   reg  [length:1] qi;
864
   wire  [length:1] q_next, q_next_fw, q_next_rew;
865
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
866
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
867
   assign q_next = rew ? q_next_rew : q_next_fw;
868
   always @ (posedge clk or posedge rst)
869
     if (rst)
870
       qi <= {length{1'b0}};
871
     else
872
     if (cke)
873
       qi <= q_next;
874
   always @ (posedge clk or posedge rst)
875
     if (rst)
876
       zq <= 1'b1;
877
     else
878
     if (cke)
879
       zq <= q_next == {length{1'b0}};
880
    always @ (posedge clk or posedge rst)
881
    if (rst)
882
        level1 <= 1'b0;
883
    else
884
    if (cke)
885 29 unneback
    if (clear)
886
        level1 <= 1'b0;
887
    else if (q_next == level1_value)
888 25 unneback
        level1 <= 1'b1;
889
    else if (qi == level1_value & rew)
890
        level1 <= 1'b0;
891
endmodule
892
//////////////////////////////////////////////////////////////////////
893
////                                                              ////
894
////  Versatile counter                                           ////
895
////                                                              ////
896
////  Description                                                 ////
897
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
898
////  counter                                                     ////
899
////                                                              ////
900
////  To Do:                                                      ////
901
////   - add LFSR with more taps                                  ////
902
////                                                              ////
903
////  Author(s):                                                  ////
904
////      - Michael Unneback, unneback@opencores.org              ////
905
////        ORSoC AB                                              ////
906
////                                                              ////
907
//////////////////////////////////////////////////////////////////////
908
////                                                              ////
909
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
910
////                                                              ////
911
//// This source file may be used and distributed without         ////
912
//// restriction provided that this copyright statement is not    ////
913
//// removed from the file and that any derivative work contains  ////
914
//// the original copyright notice and the associated disclaimer. ////
915
////                                                              ////
916
//// This source file is free software; you can redistribute it   ////
917
//// and/or modify it under the terms of the GNU Lesser General   ////
918
//// Public License as published by the Free Software Foundation; ////
919
//// either version 2.1 of the License, or (at your option) any   ////
920
//// later version.                                               ////
921
////                                                              ////
922
//// This source is distributed in the hope that it will be       ////
923
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
924
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
925
//// PURPOSE.  See the GNU Lesser General Public License for more ////
926
//// details.                                                     ////
927
////                                                              ////
928
//// You should have received a copy of the GNU Lesser General    ////
929
//// Public License along with this source; if not, download it   ////
930
//// from http://www.opencores.org/lgpl.shtml                     ////
931
////                                                              ////
932
//////////////////////////////////////////////////////////////////////
933
// binary counter
934 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
935
 cke, rew, q, zq, level1, rst, clk);
936 25 unneback
   parameter length = 4;
937
   input cke;
938
   input rew;
939
   output [length:1] q;
940
   output reg zq;
941
   output reg level1;
942
   input rst;
943
   input clk;
944
   parameter clear_value = 0;
945
   parameter set_value = 1;
946
   parameter wrap_value = 1;
947
   parameter level1_value = 15;
948 29 unneback
   wire clear;
949 30 unneback
   assign clear = 1'b0;
950 25 unneback
   reg  [length:1] qi;
951
   wire  [length:1] q_next, q_next_fw, q_next_rew;
952
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
953
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
954
   assign q_next = rew ? q_next_rew : q_next_fw;
955
   always @ (posedge clk or posedge rst)
956
     if (rst)
957
       qi <= {length{1'b0}};
958
     else
959
     if (cke)
960
       qi <= q_next;
961
   assign q = qi;
962
   always @ (posedge clk or posedge rst)
963
     if (rst)
964
       zq <= 1'b1;
965
     else
966
     if (cke)
967
       zq <= q_next == {length{1'b0}};
968
    always @ (posedge clk or posedge rst)
969
    if (rst)
970
        level1 <= 1'b0;
971
    else
972
    if (cke)
973 29 unneback
    if (clear)
974
        level1 <= 1'b0;
975
    else if (q_next == level1_value)
976 25 unneback
        level1 <= 1'b1;
977
    else if (qi == level1_value & rew)
978
        level1 <= 1'b0;
979
endmodule
980
//////////////////////////////////////////////////////////////////////
981
////                                                              ////
982
////  Versatile counter                                           ////
983
////                                                              ////
984
////  Description                                                 ////
985
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
986
////  counter                                                     ////
987
////                                                              ////
988
////  To Do:                                                      ////
989
////   - add LFSR with more taps                                  ////
990
////                                                              ////
991
////  Author(s):                                                  ////
992
////      - Michael Unneback, unneback@opencores.org              ////
993
////        ORSoC AB                                              ////
994
////                                                              ////
995
//////////////////////////////////////////////////////////////////////
996
////                                                              ////
997
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
998
////                                                              ////
999
//// This source file may be used and distributed without         ////
1000
//// restriction provided that this copyright statement is not    ////
1001
//// removed from the file and that any derivative work contains  ////
1002
//// the original copyright notice and the associated disclaimer. ////
1003
////                                                              ////
1004
//// This source file is free software; you can redistribute it   ////
1005
//// and/or modify it under the terms of the GNU Lesser General   ////
1006
//// Public License as published by the Free Software Foundation; ////
1007
//// either version 2.1 of the License, or (at your option) any   ////
1008
//// later version.                                               ////
1009
////                                                              ////
1010
//// This source is distributed in the hope that it will be       ////
1011
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1012
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1013
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1014
//// details.                                                     ////
1015
////                                                              ////
1016
//// You should have received a copy of the GNU Lesser General    ////
1017
//// Public License along with this source; if not, download it   ////
1018
//// from http://www.opencores.org/lgpl.shtml                     ////
1019
////                                                              ////
1020
//////////////////////////////////////////////////////////////////////
1021 75 unneback
// LFSR counter
1022 136 unneback
module vl_cnt_lfsr_zq (
1023
 zq, rst, clk);
1024
   parameter length = 4;
1025
   output reg zq;
1026
   input rst;
1027
   input clk;
1028
   parameter clear_value = 0;
1029
   parameter set_value = 1;
1030
   parameter wrap_value = 8;
1031
   parameter level1_value = 15;
1032
   reg  [length:1] qi;
1033
   reg lfsr_fb;
1034
   wire [length:1] q_next;
1035
   reg [32:1] polynom;
1036
   integer i;
1037
   always @ (qi)
1038
   begin
1039
        case (length)
1040
         2: polynom = 32'b11;                               // 0x3
1041
         3: polynom = 32'b110;                              // 0x6
1042
         4: polynom = 32'b1100;                             // 0xC
1043
         5: polynom = 32'b10100;                            // 0x14
1044
         6: polynom = 32'b110000;                           // 0x30
1045
         7: polynom = 32'b1100000;                          // 0x60
1046
         8: polynom = 32'b10111000;                         // 0xb8
1047
         9: polynom = 32'b100010000;                        // 0x110
1048
        10: polynom = 32'b1001000000;                       // 0x240
1049
        11: polynom = 32'b10100000000;                      // 0x500
1050
        12: polynom = 32'b100000101001;                     // 0x829
1051
        13: polynom = 32'b1000000001100;                    // 0x100C
1052
        14: polynom = 32'b10000000010101;                   // 0x2015
1053
        15: polynom = 32'b110000000000000;                  // 0x6000
1054
        16: polynom = 32'b1101000000001000;                 // 0xD008
1055
        17: polynom = 32'b10010000000000000;                // 0x12000
1056
        18: polynom = 32'b100000010000000000;               // 0x20400
1057
        19: polynom = 32'b1000000000000100011;              // 0x40023
1058
        20: polynom = 32'b10010000000000000000;             // 0x90000
1059
        21: polynom = 32'b101000000000000000000;            // 0x140000
1060
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1061
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1062
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1063
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1064
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1065
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1066
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1067
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1068
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1069
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1070
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1071
        default: polynom = 32'b0;
1072
        endcase
1073
        lfsr_fb = qi[length];
1074
        for (i=length-1; i>=1; i=i-1) begin
1075
            if (polynom[i])
1076
                lfsr_fb = lfsr_fb  ~^ qi[i];
1077
        end
1078
    end
1079
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1080
   always @ (posedge clk or posedge rst)
1081
     if (rst)
1082
       qi <= {length{1'b0}};
1083
     else
1084
       qi <= q_next;
1085
   always @ (posedge clk or posedge rst)
1086
     if (rst)
1087
       zq <= 1'b1;
1088
     else
1089
       zq <= q_next == {length{1'b0}};
1090
endmodule
1091
//////////////////////////////////////////////////////////////////////
1092
////                                                              ////
1093
////  Versatile counter                                           ////
1094
////                                                              ////
1095
////  Description                                                 ////
1096
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1097
////  counter                                                     ////
1098
////                                                              ////
1099
////  To Do:                                                      ////
1100
////   - add LFSR with more taps                                  ////
1101
////                                                              ////
1102
////  Author(s):                                                  ////
1103
////      - Michael Unneback, unneback@opencores.org              ////
1104
////        ORSoC AB                                              ////
1105
////                                                              ////
1106
//////////////////////////////////////////////////////////////////////
1107
////                                                              ////
1108
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1109
////                                                              ////
1110
//// This source file may be used and distributed without         ////
1111
//// restriction provided that this copyright statement is not    ////
1112
//// removed from the file and that any derivative work contains  ////
1113
//// the original copyright notice and the associated disclaimer. ////
1114
////                                                              ////
1115
//// This source file is free software; you can redistribute it   ////
1116
//// and/or modify it under the terms of the GNU Lesser General   ////
1117
//// Public License as published by the Free Software Foundation; ////
1118
//// either version 2.1 of the License, or (at your option) any   ////
1119
//// later version.                                               ////
1120
////                                                              ////
1121
//// This source is distributed in the hope that it will be       ////
1122
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1123
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1124
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1125
//// details.                                                     ////
1126
////                                                              ////
1127
//// You should have received a copy of the GNU Lesser General    ////
1128
//// Public License along with this source; if not, download it   ////
1129
//// from http://www.opencores.org/lgpl.shtml                     ////
1130
////                                                              ////
1131
//////////////////////////////////////////////////////////////////////
1132
// LFSR counter
1133 75 unneback
module vl_cnt_lfsr_ce (
1134
 cke, zq, rst, clk);
1135
   parameter length = 4;
1136
   input cke;
1137
   output reg zq;
1138
   input rst;
1139
   input clk;
1140
   parameter clear_value = 0;
1141
   parameter set_value = 1;
1142
   parameter wrap_value = 0;
1143
   parameter level1_value = 15;
1144
   reg  [length:1] qi;
1145
   reg lfsr_fb;
1146
   wire [length:1] q_next;
1147
   reg [32:1] polynom;
1148
   integer i;
1149
   always @ (qi)
1150
   begin
1151
        case (length)
1152
         2: polynom = 32'b11;                               // 0x3
1153
         3: polynom = 32'b110;                              // 0x6
1154
         4: polynom = 32'b1100;                             // 0xC
1155
         5: polynom = 32'b10100;                            // 0x14
1156
         6: polynom = 32'b110000;                           // 0x30
1157
         7: polynom = 32'b1100000;                          // 0x60
1158
         8: polynom = 32'b10111000;                         // 0xb8
1159
         9: polynom = 32'b100010000;                        // 0x110
1160
        10: polynom = 32'b1001000000;                       // 0x240
1161
        11: polynom = 32'b10100000000;                      // 0x500
1162
        12: polynom = 32'b100000101001;                     // 0x829
1163
        13: polynom = 32'b1000000001100;                    // 0x100C
1164
        14: polynom = 32'b10000000010101;                   // 0x2015
1165
        15: polynom = 32'b110000000000000;                  // 0x6000
1166
        16: polynom = 32'b1101000000001000;                 // 0xD008
1167
        17: polynom = 32'b10010000000000000;                // 0x12000
1168
        18: polynom = 32'b100000010000000000;               // 0x20400
1169
        19: polynom = 32'b1000000000000100011;              // 0x40023
1170
        20: polynom = 32'b10010000000000000000;             // 0x90000
1171
        21: polynom = 32'b101000000000000000000;            // 0x140000
1172
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1173
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1174
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1175
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1176
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1177
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1178
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1179
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1180
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1181
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1182
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1183
        default: polynom = 32'b0;
1184
        endcase
1185
        lfsr_fb = qi[length];
1186
        for (i=length-1; i>=1; i=i-1) begin
1187
            if (polynom[i])
1188
                lfsr_fb = lfsr_fb  ~^ qi[i];
1189
        end
1190
    end
1191
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1192
   always @ (posedge clk or posedge rst)
1193
     if (rst)
1194
       qi <= {length{1'b0}};
1195
     else
1196
     if (cke)
1197
       qi <= q_next;
1198
   always @ (posedge clk or posedge rst)
1199
     if (rst)
1200
       zq <= 1'b1;
1201
     else
1202
     if (cke)
1203
       zq <= q_next == {length{1'b0}};
1204
endmodule
1205
//////////////////////////////////////////////////////////////////////
1206
////                                                              ////
1207
////  Versatile counter                                           ////
1208
////                                                              ////
1209
////  Description                                                 ////
1210
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1211
////  counter                                                     ////
1212
////                                                              ////
1213
////  To Do:                                                      ////
1214
////   - add LFSR with more taps                                  ////
1215
////                                                              ////
1216
////  Author(s):                                                  ////
1217
////      - Michael Unneback, unneback@opencores.org              ////
1218
////        ORSoC AB                                              ////
1219
////                                                              ////
1220
//////////////////////////////////////////////////////////////////////
1221
////                                                              ////
1222
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1223
////                                                              ////
1224
//// This source file may be used and distributed without         ////
1225
//// restriction provided that this copyright statement is not    ////
1226
//// removed from the file and that any derivative work contains  ////
1227
//// the original copyright notice and the associated disclaimer. ////
1228
////                                                              ////
1229
//// This source file is free software; you can redistribute it   ////
1230
//// and/or modify it under the terms of the GNU Lesser General   ////
1231
//// Public License as published by the Free Software Foundation; ////
1232
//// either version 2.1 of the License, or (at your option) any   ////
1233
//// later version.                                               ////
1234
////                                                              ////
1235
//// This source is distributed in the hope that it will be       ////
1236
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1237
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1238
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1239
//// details.                                                     ////
1240
////                                                              ////
1241
//// You should have received a copy of the GNU Lesser General    ////
1242
//// Public License along with this source; if not, download it   ////
1243
//// from http://www.opencores.org/lgpl.shtml                     ////
1244
////                                                              ////
1245
//////////////////////////////////////////////////////////////////////
1246 6 unneback
// GRAY counter
1247 40 unneback
module vl_cnt_gray_ce_bin (
1248
 cke, q, q_bin, rst, clk);
1249 6 unneback
   parameter length = 4;
1250
   input cke;
1251
   output reg [length:1] q;
1252
   output [length:1] q_bin;
1253
   input rst;
1254
   input clk;
1255
   parameter clear_value = 0;
1256
   parameter set_value = 1;
1257
   parameter wrap_value = 8;
1258
   parameter level1_value = 15;
1259
   reg  [length:1] qi;
1260
   wire [length:1] q_next;
1261
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1262
   always @ (posedge clk or posedge rst)
1263
     if (rst)
1264
       qi <= {length{1'b0}};
1265
     else
1266
     if (cke)
1267
       qi <= q_next;
1268
   always @ (posedge clk or posedge rst)
1269
     if (rst)
1270
       q <= {length{1'b0}};
1271
     else
1272
       if (cke)
1273
         q <= (q_next>>1) ^ q_next;
1274
   assign q_bin = qi;
1275
endmodule
1276
//////////////////////////////////////////////////////////////////////
1277
////                                                              ////
1278
////  Versatile library, counters                                 ////
1279
////                                                              ////
1280
////  Description                                                 ////
1281
////  counters                                                    ////
1282
////                                                              ////
1283
////                                                              ////
1284
////  To Do:                                                      ////
1285
////   - add more counters                                        ////
1286
////                                                              ////
1287
////  Author(s):                                                  ////
1288
////      - Michael Unneback, unneback@opencores.org              ////
1289
////        ORSoC AB                                              ////
1290
////                                                              ////
1291
//////////////////////////////////////////////////////////////////////
1292
////                                                              ////
1293
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1294
////                                                              ////
1295
//// This source file may be used and distributed without         ////
1296
//// restriction provided that this copyright statement is not    ////
1297
//// removed from the file and that any derivative work contains  ////
1298
//// the original copyright notice and the associated disclaimer. ////
1299
////                                                              ////
1300
//// This source file is free software; you can redistribute it   ////
1301
//// and/or modify it under the terms of the GNU Lesser General   ////
1302
//// Public License as published by the Free Software Foundation; ////
1303
//// either version 2.1 of the License, or (at your option) any   ////
1304
//// later version.                                               ////
1305
////                                                              ////
1306
//// This source is distributed in the hope that it will be       ////
1307
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1308
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1309
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1310
//// details.                                                     ////
1311
////                                                              ////
1312
//// You should have received a copy of the GNU Lesser General    ////
1313
//// Public License along with this source; if not, download it   ////
1314
//// from http://www.opencores.org/lgpl.shtml                     ////
1315
////                                                              ////
1316
//////////////////////////////////////////////////////////////////////
1317 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1318 6 unneback
   parameter length = 4;
1319
   output reg [0:length-1] q;
1320
   input rst;
1321
   input clk;
1322
    always @ (posedge clk or posedge rst)
1323
    if (rst)
1324
        q <= {1'b1,{length-1{1'b0}}};
1325
    else
1326
        q <= {q[length-1],q[0:length-2]};
1327
endmodule
1328 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1329 6 unneback
   parameter length = 4;
1330
   input cke;
1331
   output reg [0:length-1] q;
1332
   input rst;
1333
   input clk;
1334
    always @ (posedge clk or posedge rst)
1335
    if (rst)
1336
        q <= {1'b1,{length-1{1'b0}}};
1337
    else
1338
        if (cke)
1339
            q <= {q[length-1],q[0:length-2]};
1340
endmodule
1341 105 unneback
module vl_cnt_shreg_clear ( clear, q, rst, clk);
1342
   parameter length = 4;
1343
   input clear;
1344
   output reg [0:length-1] q;
1345
   input rst;
1346
   input clk;
1347
    always @ (posedge clk or posedge rst)
1348
    if (rst)
1349
        q <= {1'b1,{length-1{1'b0}}};
1350
    else
1351
        if (clear)
1352
            q <= {1'b1,{length-1{1'b0}}};
1353
        else
1354
            q <= q >> 1;
1355
endmodule
1356 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1357 6 unneback
   parameter length = 4;
1358
   input cke, clear;
1359
   output reg [0:length-1] q;
1360
   input rst;
1361
   input clk;
1362
    always @ (posedge clk or posedge rst)
1363
    if (rst)
1364
        q <= {1'b1,{length-1{1'b0}}};
1365
    else
1366
        if (cke)
1367
            if (clear)
1368
                q <= {1'b1,{length-1{1'b0}}};
1369
            else
1370
                q <= q >> 1;
1371
endmodule
1372 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1373 6 unneback
   parameter length = 4;
1374
   input cke, clear;
1375
   output reg [0:length-1] q;
1376
   input rst;
1377
   input clk;
1378
    always @ (posedge clk or posedge rst)
1379
    if (rst)
1380
        q <= {1'b1,{length-1{1'b0}}};
1381
    else
1382
        if (cke)
1383
            if (clear)
1384
                q <= {1'b1,{length-1{1'b0}}};
1385
            else
1386
            q <= {q[length-1],q[0:length-2]};
1387
endmodule
1388
//////////////////////////////////////////////////////////////////////
1389
////                                                              ////
1390
////  Versatile library, memories                                 ////
1391
////                                                              ////
1392
////  Description                                                 ////
1393
////  memories                                                    ////
1394
////                                                              ////
1395
////                                                              ////
1396
////  To Do:                                                      ////
1397
////   - add more memory types                                    ////
1398
////                                                              ////
1399
////  Author(s):                                                  ////
1400
////      - Michael Unneback, unneback@opencores.org              ////
1401
////        ORSoC AB                                              ////
1402
////                                                              ////
1403
//////////////////////////////////////////////////////////////////////
1404
////                                                              ////
1405
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1406
////                                                              ////
1407
//// This source file may be used and distributed without         ////
1408
//// restriction provided that this copyright statement is not    ////
1409
//// removed from the file and that any derivative work contains  ////
1410
//// the original copyright notice and the associated disclaimer. ////
1411
////                                                              ////
1412
//// This source file is free software; you can redistribute it   ////
1413
//// and/or modify it under the terms of the GNU Lesser General   ////
1414
//// Public License as published by the Free Software Foundation; ////
1415
//// either version 2.1 of the License, or (at your option) any   ////
1416
//// later version.                                               ////
1417
////                                                              ////
1418
//// This source is distributed in the hope that it will be       ////
1419
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1420
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1421
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1422
//// details.                                                     ////
1423
////                                                              ////
1424
//// You should have received a copy of the GNU Lesser General    ////
1425
//// Public License along with this source; if not, download it   ////
1426
//// from http://www.opencores.org/lgpl.shtml                     ////
1427
////                                                              ////
1428
//////////////////////////////////////////////////////////////////////
1429
/// ROM
1430 7 unneback
module vl_rom_init ( adr, q, clk);
1431
   parameter data_width = 32;
1432
   parameter addr_width = 8;
1433 75 unneback
   parameter mem_size = 1<<addr_width;
1434 7 unneback
   input [(addr_width-1):0]       adr;
1435
   output reg [(data_width-1):0] q;
1436
   input                         clk;
1437 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
1438 7 unneback
   parameter memory_file = "vl_rom.vmem";
1439
   initial
1440
     begin
1441
        $readmemh(memory_file, rom);
1442
     end
1443
   always @ (posedge clk)
1444
     q <= rom[adr];
1445
endmodule
1446 6 unneback
// Single port RAM
1447
module vl_ram ( d, adr, we, q, clk);
1448
   parameter data_width = 32;
1449
   parameter addr_width = 8;
1450 75 unneback
   parameter mem_size = 1<<addr_width;
1451 100 unneback
   parameter debug = 0;
1452 6 unneback
   input [(data_width-1):0]      d;
1453
   input [(addr_width-1):0]       adr;
1454
   input                         we;
1455 7 unneback
   output reg [(data_width-1):0] q;
1456 6 unneback
   input                         clk;
1457 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
1458 100 unneback
    parameter memory_init = 0;
1459
    parameter memory_file = "vl_ram.vmem";
1460
    generate
1461
    if (memory_init == 1) begin : init_mem
1462
        initial
1463
            $readmemh(memory_file, ram);
1464
   end else if (memory_init == 2) begin : init_zero
1465
        integer k;
1466
        initial
1467
            for (k = 0; k < mem_size; k = k + 1)
1468
                ram[k] = 0;
1469 7 unneback
   end
1470
   endgenerate
1471 100 unneback
    generate
1472
    if (debug==1) begin : debug_we
1473
        always @ (posedge clk)
1474
        if (we)
1475
            $display ("Value %h written at address %h : time %t", d, adr, $time);
1476
    end
1477
    endgenerate
1478 6 unneback
   always @ (posedge clk)
1479
   begin
1480
   if (we)
1481
     ram[adr] <= d;
1482
   q <= ram[adr];
1483
   end
1484
endmodule
1485 91 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1486 7 unneback
   parameter data_width = 32;
1487 72 unneback
   parameter addr_width = 6;
1488 75 unneback
   parameter mem_size = 1<<addr_width;
1489 7 unneback
   input [(data_width-1):0]      d;
1490
   input [(addr_width-1):0]       adr;
1491 73 unneback
   input [(data_width/8)-1:0]    be;
1492 7 unneback
   input                         we;
1493
   output reg [(data_width-1):0] q;
1494
   input                         clk;
1495 65 unneback
`ifdef SYSTEMVERILOG
1496 95 unneback
    // use a multi-dimensional packed array
1497
    //t o model individual bytes within the word
1498
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
1499 65 unneback
`else
1500 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
1501
    wire [data_width/8-1:0] cke;
1502 65 unneback
`endif
1503 100 unneback
    parameter memory_init = 0;
1504
    parameter memory_file = "vl_ram.vmem";
1505
    generate
1506
    if (memory_init == 1) begin : init_mem
1507
        initial
1508
            $readmemh(memory_file, ram);
1509
    end else if (memory_init == 2) begin : init_zero
1510
        integer k;
1511
        initial
1512
            for (k = 0; k < mem_size; k = k + 1)
1513
                ram[k] = 0;
1514
    end
1515 7 unneback
   endgenerate
1516 60 unneback
`ifdef SYSTEMVERILOG
1517
always_ff@(posedge clk)
1518
begin
1519 95 unneback
    if(we) begin
1520 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
1521
        if(be[2]) ram[adr][2] <= d[23:16];
1522
        if(be[1]) ram[adr][1] <= d[15:8];
1523
        if(be[0]) ram[adr][0] <= d[7:0];
1524 60 unneback
    end
1525 90 unneback
        q <= ram[adr];
1526 60 unneback
end
1527
`else
1528 85 unneback
assign cke = {data_width/8{we}} & be;
1529 7 unneback
   genvar i;
1530 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
1531 7 unneback
      always @ (posedge clk)
1532 85 unneback
      if (cke[i])
1533 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1534
   end
1535
   endgenerate
1536
   always @ (posedge clk)
1537
      q <= ram[adr];
1538 60 unneback
`endif
1539 93 unneback
`ifdef verilator
1540 85 unneback
   // Function to access RAM (for use by Verilator).
1541
   function [31:0] get_mem;
1542
      // verilator public
1543 90 unneback
      input [addr_width-1:0]             addr;
1544 85 unneback
      get_mem = ram[addr];
1545
   endfunction // get_mem
1546
   // Function to write RAM (for use by Verilator).
1547
   function set_mem;
1548
      // verilator public
1549 90 unneback
      input [addr_width-1:0]             addr;
1550
      input [data_width-1:0]             data;
1551 85 unneback
      ram[addr] = data;
1552
   endfunction // set_mem
1553 93 unneback
`endif
1554 7 unneback
endmodule
1555
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1556 6 unneback
   parameter data_width = 32;
1557
   parameter addr_width = 8;
1558 75 unneback
   parameter mem_size = 1<<addr_width;
1559 6 unneback
   input [(data_width-1):0]      d_a;
1560
   input [(addr_width-1):0]       adr_a;
1561
   input [(addr_width-1):0]       adr_b;
1562
   input                         we_a;
1563 118 unneback
   output reg [(data_width-1):0]          q_b;
1564 6 unneback
   input                         clk_a, clk_b;
1565 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1566 100 unneback
    parameter memory_init = 0;
1567
    parameter memory_file = "vl_ram.vmem";
1568
    parameter debug = 0;
1569
    generate
1570
    if (memory_init == 1) begin : init_mem
1571
        initial
1572
            $readmemh(memory_file, ram);
1573
    end else if (memory_init == 2) begin : init_zero
1574
        integer k;
1575
        initial
1576
            for (k = 0; k < mem_size; k = k + 1)
1577
                ram[k] = 0;
1578
    end
1579 7 unneback
   endgenerate
1580 100 unneback
    generate
1581
    if (debug==1) begin : debug_we
1582
        always @ (posedge clk_a)
1583
        if (we_a)
1584
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1585
    end
1586
    endgenerate
1587 6 unneback
   always @ (posedge clk_a)
1588
   if (we_a)
1589
     ram[adr_a] <= d_a;
1590
   always @ (posedge clk_b)
1591 118 unneback
      q_b = ram[adr_b];
1592 6 unneback
endmodule
1593 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1594 6 unneback
   parameter data_width = 32;
1595
   parameter addr_width = 8;
1596 75 unneback
   parameter mem_size = 1<<addr_width;
1597 6 unneback
   input [(data_width-1):0]      d_a;
1598
   input [(addr_width-1):0]       adr_a;
1599
   input [(addr_width-1):0]       adr_b;
1600
   input                         we_a;
1601
   output [(data_width-1):0]      q_b;
1602
   output reg [(data_width-1):0] q_a;
1603
   input                         clk_a, clk_b;
1604
   reg [(data_width-1):0]         q_b;
1605 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1606 100 unneback
    parameter memory_init = 0;
1607
    parameter memory_file = "vl_ram.vmem";
1608
    parameter debug = 0;
1609
    generate
1610
    if (memory_init == 1) begin : init_mem
1611
        initial
1612
            $readmemh(memory_file, ram);
1613
    end else if (memory_init == 2) begin : init_zero
1614
        integer k;
1615
        initial
1616
            for (k = 0; k < mem_size; k = k + 1)
1617
                ram[k] = 0;
1618
    end
1619 7 unneback
   endgenerate
1620 100 unneback
    generate
1621
    if (debug==1) begin : debug_we
1622
        always @ (posedge clk_a)
1623
        if (we_a)
1624
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1625
    end
1626
    endgenerate
1627 6 unneback
   always @ (posedge clk_a)
1628
     begin
1629
        q_a <= ram[adr_a];
1630
        if (we_a)
1631
             ram[adr_a] <= d_a;
1632
     end
1633
   always @ (posedge clk_b)
1634
          q_b <= ram[adr_b];
1635
endmodule
1636 100 unneback
module vl_dpram_1r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
1637
   parameter data_width = 32;
1638
   parameter addr_width = 8;
1639
   parameter mem_size = 1<<addr_width;
1640
   input [(data_width-1):0]      d_a;
1641
   input [(addr_width-1):0]       adr_a;
1642
   input [(addr_width-1):0]       adr_b;
1643
   input                         we_a;
1644
   input [(data_width-1):0]       d_b;
1645
   output reg [(data_width-1):0] q_a;
1646
   input                         we_b;
1647
   input                         clk_a, clk_b;
1648
   reg [(data_width-1):0]         q_b;
1649 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1650 100 unneback
    parameter memory_init = 0;
1651
    parameter memory_file = "vl_ram.vmem";
1652
    parameter debug = 0;
1653
    generate
1654
    if (memory_init == 1) begin : init_mem
1655
        initial
1656
            $readmemh(memory_file, ram);
1657
    end else if (memory_init == 2) begin : init_zero
1658
        integer k;
1659
        initial
1660
            for (k = 0; k < mem_size; k = k + 1)
1661
                ram[k] = 0;
1662
    end
1663
   endgenerate
1664
    generate
1665
    if (debug==1) begin : debug_we
1666
        always @ (posedge clk_a)
1667
        if (we_a)
1668
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1669
        always @ (posedge clk_b)
1670
        if (we_b)
1671
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
1672
    end
1673
    endgenerate
1674
   always @ (posedge clk_a)
1675
     begin
1676
        q_a <= ram[adr_a];
1677
        if (we_a)
1678
             ram[adr_a] <= d_a;
1679
     end
1680
   always @ (posedge clk_b)
1681
     begin
1682
        if (we_b)
1683
          ram[adr_b] <= d_b;
1684
     end
1685
endmodule
1686 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1687 6 unneback
   parameter data_width = 32;
1688
   parameter addr_width = 8;
1689 75 unneback
   parameter mem_size = 1<<addr_width;
1690 6 unneback
   input [(data_width-1):0]      d_a;
1691
   input [(addr_width-1):0]       adr_a;
1692
   input [(addr_width-1):0]       adr_b;
1693
   input                         we_a;
1694
   output [(data_width-1):0]      q_b;
1695
   input [(data_width-1):0]       d_b;
1696
   output reg [(data_width-1):0] q_a;
1697
   input                         we_b;
1698
   input                         clk_a, clk_b;
1699
   reg [(data_width-1):0]         q_b;
1700 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1701 100 unneback
    parameter memory_init = 0;
1702
    parameter memory_file = "vl_ram.vmem";
1703
    parameter debug = 0;
1704
    generate
1705
    if (memory_init) begin : init_mem
1706
        initial
1707
            $readmemh(memory_file, ram);
1708
    end else if (memory_init == 2) begin : init_zero
1709
        integer k;
1710
        initial
1711
            for (k = 0; k < mem_size; k = k + 1)
1712
                ram[k] = 0;
1713
    end
1714 7 unneback
   endgenerate
1715 100 unneback
    generate
1716
    if (debug==1) begin : debug_we
1717
        always @ (posedge clk_a)
1718
        if (we_a)
1719
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1720
        always @ (posedge clk_b)
1721
        if (we_b)
1722
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
1723
    end
1724
    endgenerate
1725 6 unneback
   always @ (posedge clk_a)
1726
     begin
1727
        q_a <= ram[adr_a];
1728
        if (we_a)
1729
             ram[adr_a] <= d_a;
1730
     end
1731
   always @ (posedge clk_b)
1732
     begin
1733
        q_b <= ram[adr_b];
1734
        if (we_b)
1735
          ram[adr_b] <= d_b;
1736
     end
1737
endmodule
1738 92 unneback
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
1739 75 unneback
   parameter a_data_width = 32;
1740
   parameter a_addr_width = 8;
1741 95 unneback
   parameter b_data_width = 64; //a_data_width;
1742 124 unneback
   //localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
1743
   localparam b_addr_width =
1744 125 unneback
        (a_data_width==b_data_width) ? a_addr_width :
1745
        (a_data_width==b_data_width*2) ? a_addr_width+1 :
1746
        (a_data_width==b_data_width*4) ? a_addr_width+2 :
1747
        (a_data_width==b_data_width*8) ? a_addr_width+3 :
1748
        (a_data_width==b_data_width*16) ? a_addr_width+4 :
1749
        (a_data_width==b_data_width*32) ? a_addr_width+5 :
1750
        (a_data_width==b_data_width/2) ? a_addr_width-1 :
1751
        (a_data_width==b_data_width/4) ? a_addr_width-2 :
1752
        (a_data_width==b_data_width/8) ? a_addr_width-3 :
1753
        (a_data_width==b_data_width/16) ? a_addr_width-4 :
1754
        (a_data_width==b_data_width/32) ? a_addr_width-5 : 0;
1755 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
1756
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
1757 100 unneback
   parameter memory_init = 0;
1758 95 unneback
   parameter memory_file = "vl_ram.vmem";
1759 100 unneback
   parameter debug = 0;
1760 75 unneback
   input [(a_data_width-1):0]      d_a;
1761 91 unneback
   input [(a_addr_width-1):0]       adr_a;
1762
   input [(a_data_width/8-1):0]    be_a;
1763
   input                           we_a;
1764 75 unneback
   output reg [(a_data_width-1):0] q_a;
1765 91 unneback
   input [(b_data_width-1):0]       d_b;
1766
   input [(b_addr_width-1):0]       adr_b;
1767 92 unneback
   input [(b_data_width/8-1):0]    be_b;
1768
   input                           we_b;
1769
   output reg [(b_data_width-1):0]          q_b;
1770 91 unneback
   input                           clk_a, clk_b;
1771 100 unneback
    generate
1772
    if (debug==1) begin : debug_we
1773
        always @ (posedge clk_a)
1774
        if (we_a)
1775
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1776
        always @ (posedge clk_b)
1777
        if (we_b)
1778
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
1779
    end
1780
    endgenerate
1781 91 unneback
`ifdef SYSTEMVERILOG
1782
// use a multi-dimensional packed array
1783
//to model individual bytes within the word
1784 75 unneback
generate
1785 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
1786 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1787 95 unneback
    initial
1788 100 unneback
        if (memory_init==1)
1789 95 unneback
            $readmemh(memory_file, ram);
1790 100 unneback
    integer k;
1791
    initial
1792
        if (memory_init==2)
1793
            for (k = 0; k < mem_size; k = k + 1)
1794
                ram[k] = 0;
1795 91 unneback
    always_ff@(posedge clk_a)
1796
    begin
1797
        if(we_a) begin
1798 100 unneback
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
1799
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
1800
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
1801
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
1802 91 unneback
        end
1803
    end
1804 92 unneback
    always@(posedge clk_a)
1805
        q_a = ram[adr_a];
1806 91 unneback
    always_ff@(posedge clk_b)
1807 92 unneback
    begin
1808
        if(we_b) begin
1809 100 unneback
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
1810
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
1811
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
1812
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
1813 92 unneback
        end
1814
    end
1815
    always@(posedge clk_b)
1816
        q_b = ram[adr_b];
1817 75 unneback
end
1818
endgenerate
1819 95 unneback
generate
1820
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
1821 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1822 95 unneback
    initial
1823 100 unneback
        if (memory_init==1)
1824 95 unneback
            $readmemh(memory_file, ram);
1825 100 unneback
    integer k;
1826
    initial
1827
        if (memory_init==2)
1828
            for (k = 0; k < mem_size; k = k + 1)
1829
                ram[k] = 0;
1830 95 unneback
    always_ff@(posedge clk_a)
1831
    begin
1832
        if(we_a) begin
1833
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
1834
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
1835
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
1836
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
1837
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
1838
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
1839
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
1840
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
1841
        end
1842
    end
1843
    always@(posedge clk_a)
1844
        q_a = ram[adr_a];
1845
    always_ff@(posedge clk_b)
1846
    begin
1847
        if(we_b) begin
1848
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
1849
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
1850
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
1851
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
1852
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
1853
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
1854
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
1855
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
1856
        end
1857
    end
1858
    always@(posedge clk_b)
1859
        q_b = ram[adr_b];
1860
end
1861
endgenerate
1862
generate
1863
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
1864
logic [31:0] temp;
1865 128 unneback
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
1866
dpram3232 (
1867 95 unneback
    .d_a(d_a),
1868
    .q_a(q_a),
1869
    .adr_a(adr_a),
1870
    .be_a(be_a),
1871
    .we_a(we_a),
1872
    .clk_a(clk_a),
1873
    .d_b({d_b,d_b}),
1874
    .q_b(temp),
1875 128 unneback
    .adr_b(adr_b[b_addr_width-1:1]),
1876 137 unneback
    .be_b({be_b,be_b} & {{2{!adr_b[0]}},{2{adr_b[0]}}}),
1877 95 unneback
    .we_b(we_b),
1878
    .clk_b(clk_b)
1879
);
1880 100 unneback
always @ (adr_b[0] or temp)
1881 95 unneback
    if (adr_b[0])
1882
        q_b = temp[31:16];
1883
    else
1884
        q_b = temp[15:0];
1885
end
1886
endgenerate
1887
generate
1888
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
1889
logic [63:0] temp;
1890 128 unneback
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
1891 95 unneback
dpram6464 (
1892
    .d_a({d_a,d_a}),
1893
    .q_a(temp),
1894
    .adr_a(adr_a[a_addr_width-1:1]),
1895
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
1896
    .we_a(we_a),
1897
    .clk_a(clk_a),
1898
    .d_b(d_b),
1899
    .q_b(q_b),
1900
    .adr_b(adr_b),
1901
    .be_b(be_b),
1902
    .we_b(we_b),
1903
    .clk_b(clk_b)
1904
);
1905 100 unneback
always @ (adr_a[0] or temp)
1906 95 unneback
    if (adr_a[0])
1907
        q_a = temp[63:32];
1908
    else
1909
        q_a = temp[31:0];
1910
end
1911
endgenerate
1912 91 unneback
`else
1913 92 unneback
    // This modules requires SystemVerilog
1914 98 unneback
    // at this point anyway
1915 91 unneback
`endif
1916 75 unneback
endmodule
1917 6 unneback
// FIFO
1918 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1919
    d, wr, fifo_full,
1920
    q, rd, fifo_empty,
1921
    fill_level,
1922
    clk, rst
1923
    );
1924
parameter data_width = 18;
1925
parameter addr_width = 4;
1926
// write side
1927
input  [data_width-1:0] d;
1928
input                   wr;
1929
output                  fifo_full;
1930
// read side
1931
output [data_width-1:0] q;
1932
input                   rd;
1933
output                  fifo_empty;
1934
// common
1935
output [addr_width:0]   fill_level;
1936
input rst, clk;
1937
wire [addr_width:1] wadr, radr;
1938
vl_cnt_bin_ce
1939
    # ( .length(addr_width))
1940
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1941
vl_cnt_bin_ce
1942
    # (.length(addr_width))
1943
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1944
vl_dpram_1r1w
1945
    # (.data_width(data_width), .addr_width(addr_width))
1946
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1947 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1948 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1949 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1950
endmodule
1951 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1952
// RAM is supposed to be larger than the two FIFOs
1953
// LFSR counters used adr pointers
1954
module vl_fifo_2r2w_sync_simplex (
1955
    // a side
1956
    a_d, a_wr, a_fifo_full,
1957
    a_q, a_rd, a_fifo_empty,
1958
    a_fill_level,
1959
    // b side
1960
    b_d, b_wr, b_fifo_full,
1961
    b_q, b_rd, b_fifo_empty,
1962
    b_fill_level,
1963
    // common
1964
    clk, rst
1965
    );
1966
parameter data_width = 8;
1967
parameter addr_width = 5;
1968
parameter fifo_full_level = (1<<addr_width)-1;
1969
// a side
1970
input  [data_width-1:0] a_d;
1971
input                   a_wr;
1972
output                  a_fifo_full;
1973
output [data_width-1:0] a_q;
1974
input                   a_rd;
1975
output                  a_fifo_empty;
1976
output [addr_width-1:0] a_fill_level;
1977
// b side
1978
input  [data_width-1:0] b_d;
1979
input                   b_wr;
1980
output                  b_fifo_full;
1981
output [data_width-1:0] b_q;
1982
input                   b_rd;
1983
output                  b_fifo_empty;
1984
output [addr_width-1:0] b_fill_level;
1985
input                   clk;
1986
input                   rst;
1987
// adr_gen
1988
wire [addr_width:1] a_wadr, a_radr;
1989
wire [addr_width:1] b_wadr, b_radr;
1990
// dpram
1991
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1992
vl_cnt_lfsr_ce
1993
    # ( .length(addr_width))
1994
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1995
vl_cnt_lfsr_ce
1996
    # (.length(addr_width))
1997
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1998
vl_cnt_lfsr_ce
1999
    # ( .length(addr_width))
2000
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
2001
vl_cnt_lfsr_ce
2002
    # (.length(addr_width))
2003
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
2004
// mux read or write adr to DPRAM
2005
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
2006
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
2007
vl_dpram_2r2w
2008
    # (.data_width(data_width), .addr_width(addr_width+1))
2009
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2010
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2011
vl_cnt_bin_ce_rew_zq_l1
2012 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2013 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
2014
vl_cnt_bin_ce_rew_zq_l1
2015 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2016 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
2017
endmodule
2018 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2019 11 unneback
   parameter addr_width = 4;
2020
   parameter N = addr_width-1;
2021 6 unneback
   parameter Q1 = 2'b00;
2022
   parameter Q2 = 2'b01;
2023
   parameter Q3 = 2'b11;
2024
   parameter Q4 = 2'b10;
2025
   parameter going_empty = 1'b0;
2026
   parameter going_full  = 1'b1;
2027
   input [N:0]  wptr, rptr;
2028 14 unneback
   output       fifo_empty;
2029 6 unneback
   output       fifo_full;
2030
   input        wclk, rclk, rst;
2031
   wire direction;
2032
   reg  direction_set, direction_clr;
2033
   wire async_empty, async_full;
2034
   wire fifo_full2;
2035 14 unneback
   wire fifo_empty2;
2036 6 unneback
   // direction_set
2037
   always @ (wptr[N:N-1] or rptr[N:N-1])
2038
     case ({wptr[N:N-1],rptr[N:N-1]})
2039
       {Q1,Q2} : direction_set <= 1'b1;
2040
       {Q2,Q3} : direction_set <= 1'b1;
2041
       {Q3,Q4} : direction_set <= 1'b1;
2042
       {Q4,Q1} : direction_set <= 1'b1;
2043
       default : direction_set <= 1'b0;
2044
     endcase
2045
   // direction_clear
2046
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2047
     if (rst)
2048
       direction_clr <= 1'b1;
2049
     else
2050
       case ({wptr[N:N-1],rptr[N:N-1]})
2051
         {Q2,Q1} : direction_clr <= 1'b1;
2052
         {Q3,Q2} : direction_clr <= 1'b1;
2053
         {Q4,Q3} : direction_clr <= 1'b1;
2054
         {Q1,Q4} : direction_clr <= 1'b1;
2055
         default : direction_clr <= 1'b0;
2056
       endcase
2057 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2058 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2059
   assign async_full  = (wptr == rptr) && (direction==going_full);
2060 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2061
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2062 6 unneback
/*
2063
   always @ (posedge wclk or posedge rst or posedge async_full)
2064
     if (rst)
2065
       {fifo_full, fifo_full2} <= 2'b00;
2066
     else if (async_full)
2067
       {fifo_full, fifo_full2} <= 2'b11;
2068
     else
2069
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2070
*/
2071 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2072 6 unneback
     if (async_empty)
2073
       {fifo_empty, fifo_empty2} <= 2'b11;
2074
     else
2075 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2076 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2077
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2078 27 unneback
endmodule // async_compb
2079 6 unneback
module vl_fifo_1r1w_async (
2080
    d, wr, fifo_full, wr_clk, wr_rst,
2081
    q, rd, fifo_empty, rd_clk, rd_rst
2082
    );
2083
parameter data_width = 18;
2084
parameter addr_width = 4;
2085
// write side
2086
input  [data_width-1:0] d;
2087
input                   wr;
2088
output                  fifo_full;
2089
input                   wr_clk;
2090
input                   wr_rst;
2091
// read side
2092
output [data_width-1:0] q;
2093
input                   rd;
2094
output                  fifo_empty;
2095
input                   rd_clk;
2096
input                   rd_rst;
2097
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
2098 18 unneback
vl_cnt_gray_ce_bin
2099 6 unneback
    # ( .length(addr_width))
2100
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2101 18 unneback
vl_cnt_gray_ce_bin
2102 6 unneback
    # (.length(addr_width))
2103 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
2104 7 unneback
vl_dpram_1r1w
2105 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2106
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2107
vl_fifo_cmp_async
2108
    # (.addr_width(addr_width))
2109
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2110
endmodule
2111 8 unneback
module vl_fifo_2r2w_async (
2112 6 unneback
    // a side
2113
    a_d, a_wr, a_fifo_full,
2114
    a_q, a_rd, a_fifo_empty,
2115
    a_clk, a_rst,
2116
    // b side
2117
    b_d, b_wr, b_fifo_full,
2118
    b_q, b_rd, b_fifo_empty,
2119
    b_clk, b_rst
2120
    );
2121
parameter data_width = 18;
2122
parameter addr_width = 4;
2123
// a side
2124
input  [data_width-1:0] a_d;
2125
input                   a_wr;
2126
output                  a_fifo_full;
2127
output [data_width-1:0] a_q;
2128
input                   a_rd;
2129
output                  a_fifo_empty;
2130
input                   a_clk;
2131
input                   a_rst;
2132
// b side
2133
input  [data_width-1:0] b_d;
2134
input                   b_wr;
2135
output                  b_fifo_full;
2136
output [data_width-1:0] b_q;
2137
input                   b_rd;
2138
output                  b_fifo_empty;
2139
input                   b_clk;
2140
input                   b_rst;
2141
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2142
vl_fifo_1r1w_async_a (
2143
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2144
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2145
    );
2146
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2147
vl_fifo_1r1w_async_b (
2148
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2149
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2150
    );
2151
endmodule
2152 8 unneback
module vl_fifo_2r2w_async_simplex (
2153 6 unneback
    // a side
2154
    a_d, a_wr, a_fifo_full,
2155
    a_q, a_rd, a_fifo_empty,
2156
    a_clk, a_rst,
2157
    // b side
2158
    b_d, b_wr, b_fifo_full,
2159
    b_q, b_rd, b_fifo_empty,
2160
    b_clk, b_rst
2161
    );
2162
parameter data_width = 18;
2163
parameter addr_width = 4;
2164
// a side
2165
input  [data_width-1:0] a_d;
2166
input                   a_wr;
2167
output                  a_fifo_full;
2168
output [data_width-1:0] a_q;
2169
input                   a_rd;
2170
output                  a_fifo_empty;
2171
input                   a_clk;
2172
input                   a_rst;
2173
// b side
2174
input  [data_width-1:0] b_d;
2175
input                   b_wr;
2176
output                  b_fifo_full;
2177
output [data_width-1:0] b_q;
2178
input                   b_rd;
2179
output                  b_fifo_empty;
2180
input                   b_clk;
2181
input                   b_rst;
2182
// adr_gen
2183
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2184
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2185
// dpram
2186
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2187 18 unneback
vl_cnt_gray_ce_bin
2188 6 unneback
    # ( .length(addr_width))
2189
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2190 18 unneback
vl_cnt_gray_ce_bin
2191 6 unneback
    # (.length(addr_width))
2192
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2193 18 unneback
vl_cnt_gray_ce_bin
2194 6 unneback
    # ( .length(addr_width))
2195
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2196 18 unneback
vl_cnt_gray_ce_bin
2197 6 unneback
    # (.length(addr_width))
2198
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2199
// mux read or write adr to DPRAM
2200
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2201
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2202 11 unneback
vl_dpram_2r2w
2203 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2204
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2205
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2206 11 unneback
vl_fifo_cmp_async
2207 6 unneback
    # (.addr_width(addr_width))
2208
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2209 11 unneback
vl_fifo_cmp_async
2210 6 unneback
    # (.addr_width(addr_width))
2211
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2212
endmodule
2213 48 unneback
module vl_reg_file (
2214
    a1, a2, a3, wd3, we3, rd1, rd2, clk
2215
);
2216
parameter data_width = 32;
2217
parameter addr_width = 5;
2218
input [addr_width-1:0] a1, a2, a3;
2219
input [data_width-1:0] wd3;
2220
input we3;
2221
output [data_width-1:0] rd1, rd2;
2222
input clk;
2223
reg [data_width-1:0] wd3_reg;
2224
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
2225
reg we3_reg;
2226
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2227
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2228
always @ (posedge clk or posedge rst)
2229
if (rst)
2230
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
2231
else
2232
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
2233
    always @ (negedge clk)
2234
    if (we3_reg)
2235
        ram1[a3_reg] <= wd3;
2236
    always @ (posedge clk)
2237
        a1_reg <= a1;
2238
    assign rd1 = ram1[a1_reg];
2239
    always @ (negedge clk)
2240
    if (we3_reg)
2241
        ram2[a3_reg] <= wd3;
2242
    always @ (posedge clk)
2243
        a2_reg <= a2;
2244
    assign rd2 = ram2[a2_reg];
2245
endmodule
2246 12 unneback
//////////////////////////////////////////////////////////////////////
2247
////                                                              ////
2248
////  Versatile library, wishbone stuff                           ////
2249
////                                                              ////
2250
////  Description                                                 ////
2251
////  Wishbone compliant modules                                  ////
2252
////                                                              ////
2253
////                                                              ////
2254
////  To Do:                                                      ////
2255
////   -                                                          ////
2256
////                                                              ////
2257
////  Author(s):                                                  ////
2258
////      - Michael Unneback, unneback@opencores.org              ////
2259
////        ORSoC AB                                              ////
2260
////                                                              ////
2261
//////////////////////////////////////////////////////////////////////
2262
////                                                              ////
2263
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2264
////                                                              ////
2265
//// This source file may be used and distributed without         ////
2266
//// restriction provided that this copyright statement is not    ////
2267
//// removed from the file and that any derivative work contains  ////
2268
//// the original copyright notice and the associated disclaimer. ////
2269
////                                                              ////
2270
//// This source file is free software; you can redistribute it   ////
2271
//// and/or modify it under the terms of the GNU Lesser General   ////
2272
//// Public License as published by the Free Software Foundation; ////
2273
//// either version 2.1 of the License, or (at your option) any   ////
2274
//// later version.                                               ////
2275
////                                                              ////
2276
//// This source is distributed in the hope that it will be       ////
2277
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2278
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2279
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2280
//// details.                                                     ////
2281
////                                                              ////
2282
//// You should have received a copy of the GNU Lesser General    ////
2283
//// Public License along with this source; if not, download it   ////
2284
//// from http://www.opencores.org/lgpl.shtml                     ////
2285
////                                                              ////
2286
//////////////////////////////////////////////////////////////////////
2287
`timescale 1ns/1ns
2288 85 unneback
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
2289 83 unneback
parameter adr_width = 10;
2290
parameter max_burst_width = 4;
2291 85 unneback
input cyc_i, stb_i, we_i;
2292 83 unneback
input [2:0] cti_i;
2293
input [1:0] bte_i;
2294
input [adr_width-1:0] adr_i;
2295
output [adr_width-1:0] adr_o;
2296
output ack_o;
2297
input clk, rst;
2298
reg [adr_width-1:0] adr;
2299 90 unneback
wire [max_burst_width-1:0] to_adr;
2300 91 unneback
reg [max_burst_width-1:0] last_adr;
2301 92 unneback
reg last_cycle;
2302
localparam idle_or_eoc = 1'b0;
2303
localparam cyc_or_ws   = 1'b1;
2304 91 unneback
always @ (posedge clk or posedge rst)
2305
if (rst)
2306
    last_adr <= {max_burst_width{1'b0}};
2307
else
2308
    if (stb_i)
2309 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
2310 83 unneback
generate
2311
if (max_burst_width==0) begin : inst_0
2312 97 unneback
        reg ack_o;
2313
        assign adr_o = adr_i;
2314
        always @ (posedge clk or posedge rst)
2315
        if (rst)
2316
            ack_o <= 1'b0;
2317
        else
2318
            ack_o <= cyc_i & stb_i & !ack_o;
2319 83 unneback
end else begin
2320
    always @ (posedge clk or posedge rst)
2321
    if (rst)
2322 92 unneback
        last_cycle <= idle_or_eoc;
2323 83 unneback
    else
2324 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
2325
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
2326
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
2327
                      cyc_or_ws; // cyc
2328
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
2329 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
2330 91 unneback
                                        (!stb_i) ? last_adr :
2331 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
2332 85 unneback
                                        adr[max_burst_width-1:0];
2333 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
2334 83 unneback
end
2335
endgenerate
2336
generate
2337
if (max_burst_width==2) begin : inst_2
2338
    always @ (posedge clk or posedge rst)
2339
    if (rst)
2340
        adr <= 2'h0;
2341
    else
2342
        if (cyc_i & stb_i)
2343
            adr[1:0] <= to_adr[1:0] + 2'd1;
2344
        else
2345
            adr <= to_adr[1:0];
2346
end
2347
endgenerate
2348
generate
2349
if (max_burst_width==3) begin : inst_3
2350
    always @ (posedge clk or posedge rst)
2351
    if (rst)
2352
        adr <= 3'h0;
2353
    else
2354
        if (cyc_i & stb_i)
2355
            case (bte_i)
2356
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
2357
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
2358
            endcase
2359
        else
2360
            adr <= to_adr[2:0];
2361
end
2362
endgenerate
2363
generate
2364
if (max_burst_width==4) begin : inst_4
2365
    always @ (posedge clk or posedge rst)
2366
    if (rst)
2367
        adr <= 4'h0;
2368
    else
2369 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
2370 83 unneback
            case (bte_i)
2371
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
2372
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
2373
            default: adr[3:0] <= to_adr + 4'd1;
2374
            endcase
2375
        else
2376
            adr <= to_adr[3:0];
2377
end
2378
endgenerate
2379
generate
2380
if (adr_width > max_burst_width) begin : pass_through
2381
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
2382
end
2383
endgenerate
2384
endmodule
2385
// async wb3 - wb3 bridge
2386
`timescale 1ns/1ns
2387 18 unneback
module vl_wb3wb3_bridge (
2388 12 unneback
        // wishbone slave side
2389
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2390
        // wishbone master side
2391
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2392 95 unneback
parameter style = "FIFO"; // valid: simple, FIFO
2393
parameter addr_width = 4;
2394 12 unneback
input [31:0] wbs_dat_i;
2395
input [31:2] wbs_adr_i;
2396
input [3:0]  wbs_sel_i;
2397
input [1:0]  wbs_bte_i;
2398
input [2:0]  wbs_cti_i;
2399
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2400
output [31:0] wbs_dat_o;
2401 14 unneback
output wbs_ack_o;
2402 12 unneback
input wbs_clk, wbs_rst;
2403
output [31:0] wbm_dat_o;
2404
output reg [31:2] wbm_adr_o;
2405
output [3:0]  wbm_sel_o;
2406
output reg [1:0]  wbm_bte_o;
2407
output reg [2:0]  wbm_cti_o;
2408 14 unneback
output reg wbm_we_o;
2409
output wbm_cyc_o;
2410 12 unneback
output wbm_stb_o;
2411
input [31:0]  wbm_dat_i;
2412
input wbm_ack_i;
2413
input wbm_clk, wbm_rst;
2414
// bte
2415
parameter linear       = 2'b00;
2416
parameter wrap4        = 2'b01;
2417
parameter wrap8        = 2'b10;
2418
parameter wrap16       = 2'b11;
2419
// cti
2420
parameter classic      = 3'b000;
2421
parameter incburst     = 3'b010;
2422
parameter endofburst   = 3'b111;
2423 95 unneback
localparam wbs_adr  = 1'b0;
2424
localparam wbs_data = 1'b1;
2425
localparam wbm_adr0      = 2'b00;
2426
localparam wbm_adr1      = 2'b01;
2427
localparam wbm_data      = 2'b10;
2428
localparam wbm_data_wait = 2'b11;
2429 12 unneback
reg [1:0] wbs_bte_reg;
2430
reg wbs;
2431
wire wbs_eoc_alert, wbm_eoc_alert;
2432
reg wbs_eoc, wbm_eoc;
2433
reg [1:0] wbm;
2434 14 unneback
wire [1:16] wbs_count, wbm_count;
2435 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
2436
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2437
reg a_rd_reg;
2438
wire b_rd_adr, b_rd_data;
2439 14 unneback
wire b_rd_data_reg;
2440
wire [35:0] temp;
2441 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2442
always @ (posedge wbs_clk or posedge wbs_rst)
2443
if (wbs_rst)
2444
        wbs_eoc <= 1'b0;
2445
else
2446
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2447 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
2448 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
2449
                wbs_eoc <= 1'b1;
2450 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2451 12 unneback
    cnt0 (
2452
        .cke(wbs_ack_o),
2453
        .clear(wbs_eoc),
2454
        .q(wbs_count),
2455
        .rst(wbs_rst),
2456
        .clk(wbs_clk));
2457
always @ (posedge wbs_clk or posedge wbs_rst)
2458
if (wbs_rst)
2459
        wbs <= wbs_adr;
2460
else
2461 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
2462 12 unneback
                wbs <= wbs_data;
2463
        else if (wbs_eoc & wbs_ack_o)
2464
                wbs <= wbs_adr;
2465
// wbs FIFO
2466 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
2467
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
2468 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2469
              1'b0;
2470
assign a_rd = !a_fifo_empty;
2471
always @ (posedge wbs_clk or posedge wbs_rst)
2472
if (wbs_rst)
2473
        a_rd_reg <= 1'b0;
2474
else
2475
        a_rd_reg <= a_rd;
2476
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2477
assign wbs_dat_o = a_q[35:4];
2478
always @ (posedge wbs_clk or posedge wbs_rst)
2479
if (wbs_rst)
2480 13 unneback
        wbs_bte_reg <= 2'b00;
2481 12 unneback
else
2482 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2483 12 unneback
// wbm FIFO
2484
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2485
always @ (posedge wbm_clk or posedge wbm_rst)
2486
if (wbm_rst)
2487
        wbm_eoc <= 1'b0;
2488
else
2489
        if (wbm==wbm_adr0 & !b_fifo_empty)
2490
                wbm_eoc <= b_q[4:3] == linear;
2491
        else if (wbm_eoc_alert & wbm_ack_i)
2492
                wbm_eoc <= 1'b1;
2493
always @ (posedge wbm_clk or posedge wbm_rst)
2494
if (wbm_rst)
2495
        wbm <= wbm_adr0;
2496
else
2497 33 unneback
/*
2498 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2499
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2500
        (wbm==wbm_adr1 & !wbm_we_o) |
2501
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2502
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2503 33 unneback
*/
2504
    case (wbm)
2505
    wbm_adr0:
2506
        if (!b_fifo_empty)
2507
            wbm <= wbm_adr1;
2508
    wbm_adr1:
2509
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
2510
            wbm <= wbm_data;
2511
    wbm_data:
2512
        if (wbm_ack_i & wbm_eoc)
2513
            wbm <= wbm_adr0;
2514
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
2515
            wbm <= wbm_data_wait;
2516
    wbm_data_wait:
2517
        if (!b_fifo_empty)
2518
            wbm <= wbm_data;
2519
    endcase
2520 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
2521
assign b_wr = !wbm_we_o & wbm_ack_i;
2522
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2523
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2524
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2525 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
2526 12 unneback
                   1'b0;
2527
assign b_rd = b_rd_adr | b_rd_data;
2528 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2529
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2530 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2531 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2532 12 unneback
    cnt1 (
2533
        .cke(wbm_ack_i),
2534
        .clear(wbm_eoc),
2535
        .q(wbm_count),
2536
        .rst(wbm_rst),
2537
        .clk(wbm_clk));
2538 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
2539
assign wbm_stb_o = (wbm==wbm_data);
2540 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
2541
if (wbm_rst)
2542
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2543
else begin
2544
        if (wbm==wbm_adr0 & !b_fifo_empty)
2545
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2546
        else if (wbm_eoc_alert & wbm_ack_i)
2547
                wbm_cti_o <= endofburst;
2548
end
2549
//async_fifo_dw_simplex_top
2550
vl_fifo_2r2w_async_simplex
2551
# ( .data_width(36), .addr_width(addr_width))
2552
fifo (
2553
    // a side
2554
    .a_d(a_d),
2555
    .a_wr(a_wr),
2556
    .a_fifo_full(a_fifo_full),
2557
    .a_q(a_q),
2558
    .a_rd(a_rd),
2559
    .a_fifo_empty(a_fifo_empty),
2560
    .a_clk(wbs_clk),
2561
    .a_rst(wbs_rst),
2562
    // b side
2563
    .b_d(b_d),
2564
    .b_wr(b_wr),
2565
    .b_fifo_full(b_fifo_full),
2566
    .b_q(b_q),
2567
    .b_rd(b_rd),
2568
    .b_fifo_empty(b_fifo_empty),
2569
    .b_clk(wbm_clk),
2570
    .b_rst(wbm_rst)
2571
    );
2572
endmodule
2573 75 unneback
module vl_wb3avalon_bridge (
2574
        // wishbone slave side
2575
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2576 77 unneback
        // avalon master side
2577 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
2578 85 unneback
parameter linewrapburst = 1'b0;
2579 75 unneback
input [31:0] wbs_dat_i;
2580
input [31:2] wbs_adr_i;
2581
input [3:0]  wbs_sel_i;
2582
input [1:0]  wbs_bte_i;
2583
input [2:0]  wbs_cti_i;
2584 83 unneback
input wbs_we_i;
2585
input wbs_cyc_i;
2586
input wbs_stb_i;
2587 75 unneback
output [31:0] wbs_dat_o;
2588
output wbs_ack_o;
2589
input wbs_clk, wbs_rst;
2590
input [31:0] readdata;
2591
output [31:0] writedata;
2592
output [31:2] address;
2593
output [3:0]  be;
2594
output write;
2595 81 unneback
output read;
2596 75 unneback
output beginbursttransfer;
2597
output [3:0] burstcount;
2598
input readdatavalid;
2599
input waitrequest;
2600
input clk;
2601
input rst;
2602
wire [1:0] wbm_bte_o;
2603
wire [2:0] wbm_cti_o;
2604
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
2605
reg last_cyc;
2606 79 unneback
reg [3:0] counter;
2607 82 unneback
reg read_busy;
2608 75 unneback
always @ (posedge clk or posedge rst)
2609
if (rst)
2610
    last_cyc <= 1'b0;
2611
else
2612
    last_cyc <= wbm_cyc_o;
2613 79 unneback
always @ (posedge clk or posedge rst)
2614
if (rst)
2615 82 unneback
    read_busy <= 1'b0;
2616 79 unneback
else
2617 82 unneback
    if (read & !waitrequest)
2618
        read_busy <= 1'b1;
2619
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
2620
        read_busy <= 1'b0;
2621
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
2622 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
2623
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
2624
                    (wbm_bte_o==2'b10) ? 4'd8 :
2625 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
2626
                    4'd1;
2627 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
2628 79 unneback
always @ (posedge clk or posedge rst)
2629
if (rst) begin
2630
    counter <= 4'd0;
2631
end else
2632 80 unneback
    if (wbm_we_o) begin
2633
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
2634 85 unneback
            counter <= burstcount -4'd1;
2635 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
2636
            counter <= burstcount;
2637
        end else if (!waitrequest & wbm_stb_o) begin
2638
            counter <= counter - 4'd1;
2639
        end
2640 82 unneback
    end
2641 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
2642 77 unneback
vl_wb3wb3_bridge wbwb3inst (
2643 75 unneback
    // wishbone slave side
2644
    .wbs_dat_i(wbs_dat_i),
2645
    .wbs_adr_i(wbs_adr_i),
2646
    .wbs_sel_i(wbs_sel_i),
2647
    .wbs_bte_i(wbs_bte_i),
2648
    .wbs_cti_i(wbs_cti_i),
2649
    .wbs_we_i(wbs_we_i),
2650
    .wbs_cyc_i(wbs_cyc_i),
2651
    .wbs_stb_i(wbs_stb_i),
2652
    .wbs_dat_o(wbs_dat_o),
2653
    .wbs_ack_o(wbs_ack_o),
2654
    .wbs_clk(wbs_clk),
2655
    .wbs_rst(wbs_rst),
2656
    // wishbone master side
2657
    .wbm_dat_o(writedata),
2658 78 unneback
    .wbm_adr_o(address),
2659 75 unneback
    .wbm_sel_o(be),
2660
    .wbm_bte_o(wbm_bte_o),
2661
    .wbm_cti_o(wbm_cti_o),
2662
    .wbm_we_o(wbm_we_o),
2663
    .wbm_cyc_o(wbm_cyc_o),
2664
    .wbm_stb_o(wbm_stb_o),
2665
    .wbm_dat_i(readdata),
2666
    .wbm_ack_i(wbm_ack_i),
2667
    .wbm_clk(clk),
2668
    .wbm_rst(rst));
2669
endmodule
2670 49 unneback
// WB RAM with byte enable
2671 101 unneback
module vl_wb_ram (
2672 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
2673 101 unneback
    wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
2674
parameter adr_width = 16;
2675
parameter mem_size = 1<<adr_width;
2676
parameter dat_width = 32;
2677
parameter max_burst_width = 4; // only used for B3
2678
parameter mode = "B3"; // valid options: B3, B4
2679 60 unneback
parameter memory_init = 1;
2680
parameter memory_file = "vl_ram.vmem";
2681 101 unneback
input [dat_width-1:0] wbs_dat_i;
2682
input [adr_width-1:0] wbs_adr_i;
2683
input [2:0] wbs_cti_i;
2684
input [1:0] wbs_bte_i;
2685
input [dat_width/8-1:0] wbs_sel_i;
2686 70 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
2687 101 unneback
output [dat_width-1:0] wbs_dat_o;
2688 70 unneback
output wbs_ack_o;
2689 101 unneback
output wbs_stall_o;
2690 71 unneback
input wb_clk, wb_rst;
2691 101 unneback
wire [adr_width-1:0] adr;
2692
wire we;
2693
generate
2694
if (mode=="B3") begin : B3_inst
2695
vl_wb_adr_inc # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
2696 83 unneback
    .cyc_i(wbs_cyc_i),
2697
    .stb_i(wbs_stb_i),
2698
    .cti_i(wbs_cti_i),
2699
    .bte_i(wbs_bte_i),
2700
    .adr_i(wbs_adr_i),
2701 85 unneback
    .we_i(wbs_we_i),
2702 83 unneback
    .ack_o(wbs_ack_o),
2703
    .adr_o(adr),
2704
    .clk(wb_clk),
2705
    .rst(wb_rst));
2706 101 unneback
assign we = wbs_we_i & wbs_ack_o;
2707
end else if (mode=="B4") begin : B4_inst
2708
reg wbs_ack_o_reg;
2709
always @ (posedge wb_clk or posedge wb_rst)
2710
    if (wb_rst)
2711
        wbs_ack_o_reg <= 1'b0;
2712
    else
2713
        wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
2714
assign wbs_ack_o = wbs_ack_o_reg;
2715
assign wbs_stall_o = 1'b0;
2716
assign adr = wbs_adr_i;
2717
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
2718
end
2719
endgenerate
2720 100 unneback
vl_ram_be # (
2721
    .data_width(dat_width),
2722
    .addr_width(adr_width),
2723
    .mem_size(mem_size),
2724
    .memory_init(memory_init),
2725
    .memory_file(memory_file))
2726
ram0(
2727 101 unneback
    .d(wbs_dat_i),
2728
    .adr(adr),
2729
    .be(wbs_sel_i),
2730
    .we(we),
2731
    .q(wbs_dat_o),
2732 100 unneback
    .clk(wb_clk)
2733
);
2734 49 unneback
endmodule
2735 103 unneback
// A wishbone compliant RAM module that can be placed in front of other memory controllers
2736
module vl_wb_shadow_ram (
2737
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
2738
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
2739
    wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
2740
    wbm_dat_i, wbm_ack_i, wbm_stall_i,
2741
    wb_clk, wb_rst);
2742
parameter dat_width = 32;
2743
parameter mode = "B4";
2744
parameter max_burst_width = 4; // only used for B3
2745
parameter shadow_mem_adr_width = 10;
2746
parameter shadow_mem_size = 1024;
2747
parameter shadow_mem_init = 2;
2748
parameter shadow_mem_file = "vl_ram.v";
2749
parameter main_mem_adr_width = 24;
2750
input [dat_width-1:0] wbs_dat_i;
2751
input [main_mem_adr_width-1:0] wbs_adr_i;
2752
input [2:0] wbs_cti_i;
2753
input [1:0] wbs_bte_i;
2754
input [dat_width/8-1:0] wbs_sel_i;
2755
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
2756
output [dat_width-1:0] wbs_dat_o;
2757
output wbs_ack_o;
2758
output wbs_stall_o;
2759
output [dat_width-1:0] wbm_dat_o;
2760
output [main_mem_adr_width-1:0] wbm_adr_o;
2761
output [2:0] wbm_cti_o;
2762
output [1:0] wbm_bte_o;
2763
output [dat_width/8-1:0] wbm_sel_o;
2764
output wbm_we_o, wbm_stb_o, wbm_cyc_o;
2765
input [dat_width-1:0] wbm_dat_i;
2766
input wbm_ack_i, wbm_stall_i;
2767
input wb_clk, wb_rst;
2768
generate
2769
if (shadow_mem_size>0) begin : shadow_ram_inst
2770
wire cyc;
2771
wire [dat_width-1:0] dat;
2772
wire stall, ack;
2773
assign cyc = wbs_cyc_i & (wbs_adr_i<=shadow_mem_size);
2774
vl_wb_ram # (
2775
    .dat_width(dat_width),
2776
    .adr_width(shadow_mem_adr_width),
2777
    .mem_size(shadow_mem_size),
2778
    .memory_init(shadow_mem_init),
2779 117 unneback
    .memory_file(shadow_mem_file),
2780 103 unneback
    .mode(mode))
2781
shadow_mem0 (
2782
    .wbs_dat_i(wbs_dat_i),
2783
    .wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),
2784
    .wbs_sel_i(wbs_sel_i),
2785
    .wbs_we_i (wbs_we_i),
2786
    .wbs_bte_i(wbs_bte_i),
2787
    .wbs_cti_i(wbs_cti_i),
2788
    .wbs_stb_i(wbs_stb_i),
2789
    .wbs_cyc_i(cyc),
2790
    .wbs_dat_o(dat),
2791
    .wbs_stall_o(stall),
2792
    .wbs_ack_o(ack),
2793
    .wb_clk(wb_clk),
2794
    .wb_rst(wb_rst));
2795
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o} =
2796
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i};
2797
assign wbm_cyc_o = wbs_cyc_i & (wbs_adr_i>shadow_mem_size);
2798
assign wbs_dat_o = (dat & {dat_width{cyc}}) | (wbm_dat_i & {dat_width{wbm_cyc_o}});
2799
assign wbs_ack_o = (ack & cyc) | (wbm_ack_i & wbm_cyc_o);
2800
assign wbs_stall_o = (stall & cyc) | (wbm_stall_i & wbm_cyc_o);
2801
end else begin : no_shadow_ram_inst
2802
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o} =
2803
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i};
2804
assign {wbs_dat_o, wbs_ack_o, wbs_stall_o} = {wbm_dat_i, wbm_ack_i, wbm_stall_i};
2805
end
2806
endgenerate
2807
endmodule
2808 17 unneback
// WB ROM
2809 48 unneback
module vl_wb_b4_rom (
2810
    wb_adr_i, wb_stb_i, wb_cyc_i,
2811
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
2812
    parameter dat_width = 32;
2813
    parameter dat_default = 32'h15000000;
2814
    parameter adr_width = 32;
2815
/*
2816
`ifndef ROM
2817
`define ROM "rom.v"
2818
`endif
2819
*/
2820
    input [adr_width-1:2]   wb_adr_i;
2821
    input                   wb_stb_i;
2822
    input                   wb_cyc_i;
2823
    output [dat_width-1:0]  wb_dat_o;
2824
    reg [dat_width-1:0]     wb_dat_o;
2825
    output                  wb_ack_o;
2826
    reg                     wb_ack_o;
2827
    output                  stall_o;
2828
    input                   wb_clk;
2829
    input                   wb_rst;
2830
always @ (posedge wb_clk or posedge wb_rst)
2831
    if (wb_rst)
2832
        wb_dat_o <= {dat_width{1'b0}};
2833
    else
2834
         case (wb_adr_i[adr_width-1:2])
2835
`ifdef ROM
2836
`include `ROM
2837
`endif
2838
           default:
2839
             wb_dat_o <= dat_default;
2840
         endcase // case (wb_adr_i)
2841
always @ (posedge wb_clk or posedge wb_rst)
2842
    if (wb_rst)
2843
        wb_ack_o <= 1'b0;
2844
    else
2845
        wb_ack_o <= wb_stb_i & wb_cyc_i;
2846
assign stall_o = 1'b0;
2847
endmodule
2848
// WB ROM
2849 18 unneback
module vl_wb_boot_rom (
2850 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2851 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2852
    parameter adr_hi = 31;
2853
    parameter adr_lo = 28;
2854
    parameter adr_sel = 4'hf;
2855
    parameter addr_width = 5;
2856 33 unneback
/*
2857 17 unneback
`ifndef BOOT_ROM
2858
`define BOOT_ROM "boot_rom.v"
2859
`endif
2860 33 unneback
*/
2861 18 unneback
    input [adr_hi:2]    wb_adr_i;
2862
    input               wb_stb_i;
2863
    input               wb_cyc_i;
2864
    output [31:0]        wb_dat_o;
2865
    output              wb_ack_o;
2866
    output              hit_o;
2867
    input               wb_clk;
2868
    input               wb_rst;
2869
    wire hit;
2870
    reg [31:0] wb_dat;
2871
    reg wb_ack;
2872
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2873 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2874
    if (wb_rst)
2875 18 unneback
        wb_dat <= 32'h15000000;
2876 17 unneback
    else
2877 18 unneback
         case (wb_adr_i[addr_width-1:2])
2878 33 unneback
`ifdef BOOT_ROM
2879 17 unneback
`include `BOOT_ROM
2880 33 unneback
`endif
2881 17 unneback
           /*
2882
            // Zero r0 and jump to 0x00000100
2883 18 unneback
 
2884
            1 : wb_dat <= 32'hA8200000;
2885
            2 : wb_dat <= 32'hA8C00100;
2886
            3 : wb_dat <= 32'h44003000;
2887
            4 : wb_dat <= 32'h15000000;
2888 17 unneback
            */
2889
           default:
2890 18 unneback
             wb_dat <= 32'h00000000;
2891 17 unneback
         endcase // case (wb_adr_i)
2892
always @ (posedge wb_clk or posedge wb_rst)
2893
    if (wb_rst)
2894 18 unneback
        wb_ack <= 1'b0;
2895 17 unneback
    else
2896 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2897
assign hit_o = hit;
2898
assign wb_dat_o = wb_dat & {32{wb_ack}};
2899
assign wb_ack_o = wb_ack;
2900 17 unneback
endmodule
2901 106 unneback
module vl_wb_dpram (
2902
        // wishbone slave side a
2903
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, wbsa_stall_o,
2904
        wbsa_clk, wbsa_rst,
2905
        // wishbone slave side b
2906
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, wbsb_stall_o,
2907
        wbsb_clk, wbsb_rst);
2908
parameter data_width_a = 32;
2909
parameter data_width_b = data_width_a;
2910
parameter addr_width_a = 8;
2911
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
2912
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
2913
parameter max_burst_width_a = 4;
2914
parameter max_burst_width_b = max_burst_width_a;
2915
parameter mode = "B3";
2916 109 unneback
parameter memory_init = 0;
2917
parameter memory_file = "vl_ram.v";
2918 106 unneback
input [data_width_a-1:0] wbsa_dat_i;
2919
input [addr_width_a-1:0] wbsa_adr_i;
2920
input [data_width_a/8-1:0] wbsa_sel_i;
2921
input [2:0] wbsa_cti_i;
2922
input [1:0] wbsa_bte_i;
2923
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
2924
output [data_width_a-1:0] wbsa_dat_o;
2925 109 unneback
output wbsa_ack_o;
2926 106 unneback
output wbsa_stall_o;
2927
input wbsa_clk, wbsa_rst;
2928
input [data_width_b-1:0] wbsb_dat_i;
2929
input [addr_width_b-1:0] wbsb_adr_i;
2930
input [data_width_b/8-1:0] wbsb_sel_i;
2931
input [2:0] wbsb_cti_i;
2932
input [1:0] wbsb_bte_i;
2933
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
2934
output [data_width_b-1:0] wbsb_dat_o;
2935 109 unneback
output wbsb_ack_o;
2936 106 unneback
output wbsb_stall_o;
2937
input wbsb_clk, wbsb_rst;
2938
wire [addr_width_a-1:0] adr_a;
2939
wire [addr_width_b-1:0] adr_b;
2940
wire we_a, we_b;
2941
generate
2942
if (mode=="B3") begin : b3_inst
2943
vl_wb_adr_inc # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
2944
    .cyc_i(wbsa_cyc_i),
2945
    .stb_i(wbsa_stb_i),
2946
    .cti_i(wbsa_cti_i),
2947
    .bte_i(wbsa_bte_i),
2948
    .adr_i(wbsa_adr_i),
2949
    .we_i(wbsa_we_i),
2950
    .ack_o(wbsa_ack_o),
2951
    .adr_o(adr_a),
2952
    .clk(wbsa_clk),
2953
    .rst(wbsa_rst));
2954
assign we_a = wbsa_we_i & wbsa_ack_o;
2955
vl_wb_adr_inc # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
2956
    .cyc_i(wbsb_cyc_i),
2957
    .stb_i(wbsb_stb_i),
2958
    .cti_i(wbsb_cti_i),
2959
    .bte_i(wbsb_bte_i),
2960
    .adr_i(wbsb_adr_i),
2961
    .we_i(wbsb_we_i),
2962
    .ack_o(wbsb_ack_o),
2963
    .adr_o(adr_b),
2964
    .clk(wbsb_clk),
2965
    .rst(wbsb_rst));
2966
assign we_b = wbsb_we_i & wbsb_ack_o;
2967
end else if (mode=="B4") begin : b4_inst
2968 109 unneback
vl_dff dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
2969 106 unneback
assign wbsa_stall_o = 1'b0;
2970
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
2971 109 unneback
vl_dff dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
2972 106 unneback
assign wbsb_stall_o = 1'b0;
2973
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
2974
end
2975
endgenerate
2976 109 unneback
vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
2977 110 unneback
                 .b_data_width(data_width_b),
2978 109 unneback
                 .memory_init(memory_init), .memory_file(memory_file))
2979 106 unneback
ram_i (
2980
    .d_a(wbsa_dat_i),
2981
    .q_a(wbsa_dat_o),
2982
    .adr_a(adr_a),
2983
    .be_a(wbsa_sel_i),
2984
    .we_a(we_a),
2985
    .clk_a(wbsa_clk),
2986
    .d_b(wbsb_dat_i),
2987
    .q_b(wbsb_dat_o),
2988
    .adr_b(adr_b),
2989
    .be_b(wbsb_sel_i),
2990
    .we_b(we_b),
2991
    .clk_b(wbsb_clk) );
2992
endmodule
2993 101 unneback
module vl_wb_cache (
2994 103 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
2995 98 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
2996 97 unneback
);
2997
parameter dw_s = 32;
2998
parameter aw_s = 24;
2999
parameter dw_m = dw_s;
3000 124 unneback
//localparam aw_m = dw_s * aw_s / dw_m;
3001
localparam aw_m =
3002 126 unneback
        (dw_s==dw_m) ? aw_s :
3003
        (dw_s==dw_m*2) ? aw_s+1 :
3004
        (dw_s==dw_m*4) ? aw_s+2 :
3005
        (dw_s==dw_m*8) ? aw_s+3 :
3006
        (dw_s==dw_m*16) ? aw_s+4 :
3007
        (dw_s==dw_m*32) ? aw_s+5 :
3008
        (dw_s==dw_m/2) ? aw_s-1 :
3009 127 unneback
        (dw_s==dw_m/4) ? aw_s-2 :
3010 126 unneback
        (dw_s==dw_m/8) ? aw_s-3 :
3011
        (dw_s==dw_m/16) ? aw_s-4 :
3012
        (dw_s==dw_m/32) ? aw_s-5 : 0;
3013 100 unneback
parameter wbs_max_burst_width = 4;
3014 103 unneback
parameter wbs_mode = "B3";
3015 97 unneback
parameter async = 1; // wbs_clk != wbm_clk
3016
parameter nr_of_ways = 1;
3017
parameter aw_offset = 4; // 4 => 16 words per cache line
3018
parameter aw_slot = 10;
3019 100 unneback
parameter valid_mem = 0;
3020
parameter debug = 0;
3021
localparam aw_b_offset = aw_offset * dw_s / dw_m;
3022 98 unneback
localparam aw_tag = aw_s - aw_slot - aw_offset;
3023 97 unneback
parameter wbm_burst_size = 4; // valid options 4,8,16
3024 98 unneback
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
3025 100 unneback
localparam wbm_burst_width = (wbm_burst_size==1) ? 0 : (wbm_burst_size==2) ? 1 : (wbm_burst_size==4) ? 2 : (wbm_burst_size==8) ? 3 : (wbm_burst_size==16) ? 4 : (wbm_burst_size==32) ? 5 : (wbm_burst_size==64) ? 6 : (wbm_burst_size==128) ? 7 : 8;
3026 97 unneback
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
3027 100 unneback
localparam nr_of_wbm_burst_width = (nr_of_wbm_burst==1) ? 0 : (nr_of_wbm_burst==2) ? 1 : (nr_of_wbm_burst==4) ? 2 : (nr_of_wbm_burst==8) ? 3 : (nr_of_wbm_burst==16) ? 4 : (nr_of_wbm_burst==32) ? 5 : (nr_of_wbm_burst==64) ? 6 : (nr_of_wbm_burst==128) ? 7 : 8;
3028 97 unneback
input [dw_s-1:0] wbs_dat_i;
3029
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
3030 98 unneback
input [dw_s/8-1:0] wbs_sel_i;
3031 97 unneback
input [2:0] wbs_cti_i;
3032
input [1:0] wbs_bte_i;
3033 98 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
3034 97 unneback
output [dw_s-1:0] wbs_dat_o;
3035
output wbs_ack_o;
3036 103 unneback
output wbs_stall_o;
3037 97 unneback
input wbs_clk, wbs_rst;
3038
output [dw_m-1:0] wbm_dat_o;
3039
output [aw_m-1:0] wbm_adr_o;
3040
output [dw_m/8-1:0] wbm_sel_o;
3041
output [2:0] wbm_cti_o;
3042
output [1:0] wbm_bte_o;
3043 98 unneback
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
3044 97 unneback
input [dw_m-1:0] wbm_dat_i;
3045
input wbm_ack_i;
3046
input wbm_stall_i;
3047
input wbm_clk, wbm_rst;
3048 100 unneback
wire valid, dirty, hit;
3049 97 unneback
wire [aw_tag-1:0] tag;
3050
wire tag_mem_we;
3051
wire [aw_tag-1:0] wbs_adr_tag;
3052
wire [aw_slot-1:0] wbs_adr_slot;
3053 98 unneback
wire [aw_offset-1:0] wbs_adr_word;
3054
wire [aw_s-1:0] wbs_adr;
3055 97 unneback
reg [1:0] state;
3056
localparam idle = 2'h0;
3057
localparam rdwr = 2'h1;
3058
localparam push = 2'h2;
3059
localparam pull = 2'h3;
3060
wire eoc;
3061 103 unneback
wire we;
3062 97 unneback
// cdc
3063
wire done, mem_alert, mem_done;
3064 98 unneback
// wbm side
3065
reg [aw_m-1:0] wbm_radr;
3066
reg [aw_m-1:0] wbm_wadr;
3067 137 unneback
//wire [aw_slot-1:0] wbm_adr;
3068
wire [aw_m-1:0] wbm_adr;
3069 98 unneback
wire wbm_radr_cke, wbm_wadr_cke;
3070 100 unneback
reg [2:0] phase;
3071
// phase = {we,stb,cyc}
3072
localparam wbm_wait     = 3'b000;
3073
localparam wbm_wr       = 3'b111;
3074
localparam wbm_wr_drain = 3'b101;
3075
localparam wbm_rd       = 3'b011;
3076
localparam wbm_rd_drain = 3'b001;
3077 97 unneback
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
3078 100 unneback
generate
3079
if (valid_mem==0) begin : no_valid_mem
3080
assign valid = 1'b1;
3081
end else begin : valid_mem_inst
3082
vl_dpram_1r1w
3083
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
3084
    valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
3085
                .q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
3086
end
3087
endgenerate
3088
vl_dpram_1r1w
3089
    # ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
3090
    tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
3091
              .q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
3092
assign hit = wbs_adr_tag == tag;
3093
vl_dpram_1r2w
3094
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
3095
    dirty_mem (
3096
        .d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
3097
        .d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
3098 103 unneback
generate
3099
if (wbs_mode=="B3") begin : inst_b3
3100 100 unneback
vl_wb_adr_inc # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
3101
    .cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
3102
    .stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
3103 97 unneback
    .cti_i(wbs_cti_i),
3104
    .bte_i(wbs_bte_i),
3105
    .adr_i(wbs_adr_i),
3106
    .we_i (wbs_we_i),
3107
    .ack_o(wbs_ack_o),
3108
    .adr_o(wbs_adr),
3109 100 unneback
    .clk(wbs_clk),
3110
    .rst(wbs_rst));
3111 103 unneback
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
3112
assign we = wbs_cyc_i &  wbs_we_i & wbs_ack_o;
3113
end else if (wbs_mode=="B4") begin : inst_b4
3114
end
3115
endgenerate
3116 131 unneback
localparam cache_mem_b_aw =
3117
    (dw_s==dw_m) ? aw_slot+aw_offset :
3118 133 unneback
    (dw_s==dw_m/2) ? aw_slot+aw_offset-1 :
3119
    (dw_s==dw_m/4) ? aw_slot+aw_offset-2 :
3120
    (dw_s==dw_m/8) ? aw_slot+aw_offset-3 :
3121
    (dw_s==dw_m/16) ? aw_slot+aw_offset-4 :
3122
    (dw_s==dw_m*2) ? aw_slot+aw_offset+1 :
3123
    (dw_s==dw_m*4) ? aw_slot+aw_offset+2 :
3124
    (dw_s==dw_m*8) ? aw_slot+aw_offset+3 :
3125
    (dw_s==dw_m*16) ? aw_slot+aw_offset+4 : 0;
3126 97 unneback
vl_dpram_be_2r2w
3127 100 unneback
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
3128 103 unneback
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
3129 136 unneback
                .d_b(wbm_dat_i), .adr_b(wbm_adr[cache_mem_b_aw-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbm_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
3130 97 unneback
always @ (posedge wbs_clk or posedge wbs_rst)
3131
if (wbs_rst)
3132 98 unneback
    state <= idle;
3133 97 unneback
else
3134
    case (state)
3135
    idle:
3136
        if (wbs_cyc_i)
3137
            state <= rdwr;
3138
    rdwr:
3139 100 unneback
        casex ({valid, hit, dirty, eoc})
3140
        4'b0xxx: state <= pull;
3141
        4'b11x1: state <= idle;
3142
        4'b101x: state <= push;
3143
        4'b100x: state <= pull;
3144
        endcase
3145 97 unneback
    push:
3146
        if (done)
3147
            state <= rdwr;
3148
    pull:
3149
        if (done)
3150
            state <= rdwr;
3151
    default: state <= idle;
3152
    endcase
3153
// cdc
3154
generate
3155
if (async==1) begin : cdc0
3156 100 unneback
vl_cdc cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
3157 97 unneback
end
3158
else begin : nocdc
3159 100 unneback
    assign mem_alert = state==rdwr & (!valid | !hit);
3160 97 unneback
    assign done = mem_done;
3161
end
3162
endgenerate
3163 136 unneback
// FSM generating a number of bursts 4 cycles
3164 97 unneback
// actual number depends on data width ratio
3165
// nr_of_wbm_burst
3166 101 unneback
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0]       cnt_rw, cnt_ack;
3167 97 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
3168
if (wbm_rst)
3169 100 unneback
    cnt_rw <= {wbm_burst_width{1'b0}};
3170 97 unneback
else
3171 100 unneback
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
3172
        cnt_rw <= cnt_rw + 1;
3173 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
3174
if (wbm_rst)
3175 100 unneback
    cnt_ack <= {wbm_burst_width{1'b0}};
3176 98 unneback
else
3177 100 unneback
    if (wbm_ack_i)
3178
        cnt_ack <= cnt_ack + 1;
3179
generate
3180 101 unneback
if (nr_of_wbm_burst==1) begin : one_burst
3181 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
3182
if (wbm_rst)
3183
    phase <= wbm_wait;
3184
else
3185
    case (phase)
3186
    wbm_wait:
3187
        if (mem_alert)
3188 100 unneback
            if (state==push)
3189
                phase <= wbm_wr;
3190
            else
3191
                phase <= wbm_rd;
3192 98 unneback
    wbm_wr:
3193 100 unneback
        if (&cnt_rw)
3194
            phase <= wbm_wr_drain;
3195
    wbm_wr_drain:
3196
        if (&cnt_ack)
3197 98 unneback
            phase <= wbm_rd;
3198
    wbm_rd:
3199 100 unneback
        if (&cnt_rw)
3200
            phase <= wbm_rd_drain;
3201
    wbm_rd_drain:
3202
        if (&cnt_ack)
3203
            phase <= wbm_wait;
3204 98 unneback
    default: phase <= wbm_wait;
3205
    endcase
3206 100 unneback
end else begin : multiple_burst
3207 101 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
3208
if (wbm_rst)
3209
    phase <= wbm_wait;
3210
else
3211
    case (phase)
3212
    wbm_wait:
3213
        if (mem_alert)
3214
            if (state==push)
3215
                phase <= wbm_wr;
3216
            else
3217
                phase <= wbm_rd;
3218
    wbm_wr:
3219
        if (&cnt_rw[wbm_burst_width-1:0])
3220
            phase <= wbm_wr_drain;
3221
    wbm_wr_drain:
3222
        if (&cnt_ack)
3223
            phase <= wbm_rd;
3224
        else if (&cnt_ack[wbm_burst_width-1:0])
3225
            phase <= wbm_wr;
3226
    wbm_rd:
3227
        if (&cnt_rw[wbm_burst_width-1:0])
3228
            phase <= wbm_rd_drain;
3229
    wbm_rd_drain:
3230
        if (&cnt_ack)
3231
            phase <= wbm_wait;
3232
        else if (&cnt_ack[wbm_burst_width-1:0])
3233
            phase <= wbm_rd;
3234
    default: phase <= wbm_wait;
3235
    endcase
3236 100 unneback
end
3237
endgenerate
3238 101 unneback
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
3239 100 unneback
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
3240 137 unneback
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_ack};
3241 100 unneback
assign wbm_sel_o = {dw_m/8{1'b1}};
3242
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
3243 98 unneback
assign wbm_bte_o = bte;
3244 100 unneback
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
3245 97 unneback
endmodule
3246 103 unneback
// Wishbone to avalon bridge supporting one type of burst transfer only
3247
// intended use is together with cache above
3248
// WB B4 -> pipelined avalon
3249
module vl_wb_avalon_bridge (
3250
        // wishbone slave side
3251
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
3252
        // avalon master side
3253
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
3254 136 unneback
        init_done,
3255 103 unneback
        // common
3256
        clk, rst);
3257
parameter adr_width = 30;
3258
parameter dat_width = 32;
3259
parameter burst_size = 4;
3260
input [dat_width-1:0] wbs_dat_i;
3261
input [adr_width-1:0] wbs_adr_i;
3262
input [dat_width/8-1:0]  wbs_sel_i;
3263
input [1:0]  wbs_bte_i;
3264
input [2:0]  wbs_cti_i;
3265
input wbs_we_i;
3266
input wbs_cyc_i;
3267
input wbs_stb_i;
3268 130 unneback
output [dat_width-1:0] wbs_dat_o;
3269 103 unneback
output wbs_ack_o;
3270
output wbs_stall_o;
3271
input [dat_width-1:0] readdata;
3272
input readdatavalid;
3273
output [dat_width-1:0] writedata;
3274
output [adr_width-1:0] address;
3275
output [dat_width/8-1:0]  be;
3276
output write;
3277
output read;
3278
output beginbursttransfer;
3279
output [3:0] burstcount;
3280
input waitrequest;
3281 136 unneback
input init_done;
3282 103 unneback
input clk, rst;
3283 136 unneback
// cnt1 - initiated read or writes
3284
// cnt2 - # of read or writes in pipeline
3285
reg [3:0] cnt1;
3286
reg [3:0] cnt2;
3287
reg next_state, state;
3288
localparam s0 = 1'b0;
3289
localparam s1 = 1'b1;
3290
wire eoc;
3291
always @ *
3292
begin
3293
    case (state)
3294
    s0: if (init_done & wbs_cyc_i) next_state <= s1;
3295
    s1:
3296
    default: next_state <= state;
3297
    end
3298
end
3299 103 unneback
always @ (posedge clk or posedge rst)
3300
if (rst)
3301 136 unneback
    state <= s0;
3302 103 unneback
else
3303 136 unneback
    state <= next_state;
3304
assign eoc = state==s1 & !(read | write) & (& !waitrequest & cnt2=;
3305
always @ (posedge clk or posedge rst)
3306
if (rst)
3307
    cnt1 <= 4'h0;
3308
else
3309
    if (read & !waitrequest & init_done)
3310
        cnt1 <= burst_size - 1;
3311
    else if (write & !waitrequest & init_done)
3312
        cnt1 <= cnt1 + 4'h1;
3313
    else if (next_state==idle)
3314
        cnt1 <= 4'h0;
3315
always @ (posedge clk or posedge rst)
3316
if (rst)
3317
    cnt2 <= 4'h0;
3318
else
3319
    if (read & !waitrequest & init_done)
3320
        cnt2 <= burst_size - 1;
3321
    else if (write & !waitrequest & init_done & )
3322
        cnt2 <= cnt1 + 4'h1;
3323
    else if (next_state==idle)
3324
        cnt2 <= 4'h0;
3325 103 unneback
reg wr_ack;
3326
always @ (posedge clk or posedge rst)
3327
if (rst)
3328
    wr_ack <= 1'b0;
3329
else
3330
    wr_ack <=  (wbs_we_i & wbs_cyc_i & wbs_stb_i & !wbs_stall_o);
3331
// to avalon
3332
assign writedata = wbs_dat_i;
3333
assign address = wbs_adr_i;
3334
assign be = wbs_sel_i;
3335 136 unneback
assign write = cnt!=4'h0 & wbs_cyc_i &  wbs_we_i;
3336
assign read  = cnt!=4'h0 & wbs_cyc_i & !wbs_we_i;
3337
assign beginbursttransfer = state==s0 & next_state==s1;
3338 103 unneback
assign burstcount = burst_size;
3339
// to wishbone
3340
assign wbs_dat_o = readdata;
3341
assign wbs_ack_o = wr_ack | readdatavalid;
3342
assign wbs_stall_o = waitrequest;
3343
endmodule
3344
module vl_wb_avalon_mem_cache (
3345
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
3346
    readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst
3347
);
3348
// wishbone
3349
parameter wb_dat_width = 32;
3350
parameter wb_adr_width = 22;
3351
parameter wb_max_burst_width = 4;
3352
parameter wb_mode = "B4";
3353
// avalon
3354
parameter avalon_dat_width = 32;
3355 121 unneback
//localparam avalon_adr_width = wb_dat_width * wb_adr_width / avalon_dat_width;
3356 122 unneback
localparam avalon_adr_width =
3357
        (wb_dat_width==avalon_dat_width) ? wb_adr_width :
3358
        (wb_dat_width==avalon_dat_width*2) ? wb_adr_width+1 :
3359
        (wb_dat_width==avalon_dat_width*4) ? wb_adr_width+2 :
3360
        (wb_dat_width==avalon_dat_width*8) ? wb_adr_width+3 :
3361
        (wb_dat_width==avalon_dat_width*16) ? wb_adr_width+4 :
3362
        (wb_dat_width==avalon_dat_width*32) ? wb_adr_width+5 :
3363
        (wb_dat_width==avalon_dat_width/2) ? wb_adr_width-1 :
3364
        (wb_dat_width==avalon_dat_width/4) ? wb_adr_width-2 :
3365
        (wb_dat_width==avalon_dat_width/8) ? wb_adr_width-3 :
3366
        (wb_dat_width==avalon_dat_width/16) ? wb_adr_width-4 :
3367 123 unneback
        (wb_dat_width==avalon_dat_width/32) ? wb_adr_width-5 : 0;
3368 103 unneback
parameter avalon_burst_size = 4;
3369
// cache
3370
parameter async = 1;
3371
parameter nr_of_ways = 1;
3372
parameter aw_offset = 4;
3373
parameter aw_slot = 10;
3374
parameter valid_mem = 1;
3375
// shadow RAM
3376
parameter shadow_ram = 0;
3377
parameter shadow_ram_adr_width = 10;
3378
parameter shadow_ram_size = 1024;
3379
parameter shadow_ram_init = 2; // 0: no init, 1: from file, 2: with zero
3380
parameter shadow_ram_file = "vl_ram.v";
3381
input [wb_dat_width-1:0] wbs_dat_i;
3382
input [wb_adr_width-1:0] wbs_adr_i; // dont include a1,a0
3383
input [wb_dat_width/8-1:0] wbs_sel_i;
3384
input [2:0] wbs_cti_i;
3385
input [1:0] wbs_bte_i;
3386
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
3387
output [wb_dat_width-1:0] wbs_dat_o;
3388
output wbs_ack_o;
3389
output wbs_stall_o;
3390
input wbs_clk, wbs_rst;
3391
input [avalon_dat_width-1:0] readdata;
3392
input readdatavalid;
3393
output [avalon_dat_width-1:0] writedata;
3394
output [avalon_adr_width-1:0] address;
3395
output [avalon_dat_width/8-1:0]  be;
3396
output write;
3397
output read;
3398
output beginbursttransfer;
3399
output [3:0] burstcount;
3400
input waitrequest;
3401
input clk, rst;
3402
wire [wb_dat_width-1:0] wb1_dat_o;
3403
wire [wb_adr_width-1:0] wb1_adr_o;
3404
wire [wb_dat_width/8-1:0] wb1_sel_o;
3405
wire [2:0] wb1_cti_o;
3406
wire [1:0] wb1_bte_o;
3407
wire wb1_we_o;
3408
wire wb1_stb_o;
3409
wire wb1_cyc_o;
3410
wire wb1_stall_i;
3411
wire [wb_dat_width-1:0] wb1_dat_i;
3412
wire wb1_ack_i;
3413 129 unneback
wire [avalon_dat_width-1:0] wb2_dat_o;
3414
wire [avalon_adr_width-1:0] wb2_adr_o;
3415
wire [avalon_dat_width/8-1:0] wb2_sel_o;
3416 103 unneback
wire [2:0] wb2_cti_o;
3417
wire [1:0] wb2_bte_o;
3418
wire wb2_we_o;
3419
wire wb2_stb_o;
3420
wire wb2_cyc_o;
3421
wire wb2_stall_i;
3422 129 unneback
wire [avalon_dat_width-1:0] wb2_dat_i;
3423 103 unneback
wire wb2_ack_i;
3424
vl_wb_shadow_ram # ( .dat_width(wb_dat_width), .mode(wb_mode), .max_burst_width(wb_max_burst_width),
3425 120 unneback
                 .shadow_mem_adr_width(shadow_ram_adr_width), .shadow_mem_size(shadow_ram_size), .shadow_mem_init(shadow_ram_init), .shadow_mem_file(shadow_ram_file),
3426 103 unneback
                 .main_mem_adr_width(wb_adr_width))
3427
shadow_ram0 (
3428
    .wbs_dat_i(wbs_dat_i), .wbs_adr_i(wbs_adr_i), .wbs_cti_i(wbs_cti_i), .wbs_bte_i(wbs_bte_i), .wbs_sel_i(wbs_sel_i), .wbs_we_i(wbs_we_i), .wbs_stb_i(wbs_stb_i), .wbs_cyc_i(wbs_cyc_i),
3429
    .wbs_dat_o(wbs_dat_o), .wbs_ack_o(wbs_ack_o), .wbs_stall_o(wbs_stall_o),
3430
    .wbm_dat_o(wb1_dat_o), .wbm_adr_o(wb1_adr_o), .wbm_cti_o(wb1_cti_o), .wbm_bte_o(wb1_bte_o), .wbm_sel_o(wb1_sel_o), .wbm_we_o(wb1_we_o), .wbm_stb_o(wb1_stb_o), .wbm_cyc_o(wb1_cyc_o),
3431
    .wbm_dat_i(wb1_dat_i), .wbm_ack_i(wb1_ack_i), .wbm_stall_i(wb1_stall_i),
3432
    .wb_clk(wbs_clk), .wb_rst(wbs_rst));
3433
vl_wb_cache
3434
# ( .dw_s(wb_dat_width), .aw_s(wb_adr_width), .dw_m(avalon_dat_width), .wbs_mode(wb_mode), .wbs_max_burst_width(wb_max_burst_width), .async(async), .nr_of_ways(nr_of_ways), .aw_offset(aw_offset), .aw_slot(aw_slot), .valid_mem(valid_mem))
3435
cache0 (
3436
    .wbs_dat_i(wb1_dat_o), .wbs_adr_i(wb1_adr_o), .wbs_sel_i(wb1_sel_o), .wbs_cti_i(wb1_cti_o), .wbs_bte_i(wb1_bte_o), .wbs_we_i(wb1_we_o), .wbs_stb_i(wb1_stb_o), .wbs_cyc_i(wb1_cyc_o),
3437
    .wbs_dat_o(wb1_dat_i), .wbs_ack_o(wb1_ack_i), .wbs_stall_o(wb1_stall_i), .wbs_clk(wbs_clk), .wbs_rst(wbs_rst),
3438
    .wbm_dat_o(wb2_dat_o), .wbm_adr_o(wb2_adr_o), .wbm_sel_o(wb2_sel_o), .wbm_cti_o(wb2_cti_o), .wbm_bte_o(wb2_bte_o), .wbm_we_o(wb2_we_o), .wbm_stb_o(wb2_stb_o), .wbm_cyc_o(wb2_cyc_o),
3439
    .wbm_dat_i(wb2_dat_i), .wbm_ack_i(wb2_ack_i), .wbm_stall_i(wb2_stall_i), .wbm_clk(clk), .wbm_rst(rst));
3440
vl_wb_avalon_bridge # ( .adr_width(avalon_adr_width), .dat_width(avalon_dat_width), .burst_size(avalon_burst_size))
3441
bridge0 (
3442
        // wishbone slave side
3443
        .wbs_dat_i(wb2_dat_o), .wbs_adr_i(wb2_adr_o), .wbs_sel_i(wb2_sel_o), .wbs_bte_i(wb2_bte_o), .wbs_cti_i(wb2_cti_o), .wbs_we_i(wb2_we_o), .wbs_cyc_i(wb2_cyc_o), .wbs_stb_i(wb2_stb_o),
3444
        .wbs_dat_o(wb2_dat_i), .wbs_ack_o(wb2_ack_i), .wbs_stall_o(wb2_stall_i),
3445
        // avalon master side
3446
        .readdata(readdata), .readdatavalid(readdatavalid), .address(address), .read(read), .be(be), .write(write), .burstcount(burstcount), .writedata(writedata), .waitrequest(waitrequest), .beginbursttransfer(beginbursttransfer),
3447
        // common
3448
        .clk(clk), .rst(rst));
3449
endmodule
3450 136 unneback
module vl_wb_sdr_sdram (
3451
    // wisbone i/f
3452
    dat_i, adr_i, sel_i, we_i, cyc_i, stb_i, dat_o, ack_o, stall_o,
3453
    // SDR SDRAM
3454
    ba, a, cmd, cke, cs_n, dqm, dq_i, dq_o, dq_oe,
3455
    // system
3456
    clk, rst);
3457
    // external data bus size
3458
    parameter dat_size = 16;
3459
    // memory geometry parameters
3460
    parameter ba_size  = 2;
3461
    parameter row_size = 13;
3462
    parameter col_size = 9;
3463
    parameter cl = 2;
3464
    // memory timing parameters
3465
    parameter tRFC = 9;
3466
    parameter tRP  = 2;
3467
    parameter tRCD = 2;
3468
    parameter tMRD = 2;
3469
    // LMR
3470
    // [12:10] reserved
3471
    // [9]     WB, write burst; 0 - programmed burst length, 1 - single location
3472
    // [8:7]   OP Mode, 2'b00
3473
    // [6:4]   CAS Latency; 3'b010 - 2, 3'b011 - 3
3474
    // [3]     BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
3475
    // [2:0]   Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
3476
    localparam init_wb = 1'b1;
3477
    localparam init_cl = (cl==2) ? 3'b010 : 3'b011;
3478
    localparam init_bt = 1'b0;
3479
    localparam init_bl = 3'b000;
3480
    input [dat_size-1:0] dat_i;
3481
    input [ba_size+col_size+row_size-1:0] adr_i;
3482
    input [dat_size/8-1:0] sel_i;
3483
    input we_i, cyc_i, stb_i;
3484
    output [dat_size-1:0] dat_o;
3485
    output ack_o;
3486
    output reg stall_o;
3487
    output [ba_size-1:0]    ba;
3488
    output reg [12:0]   a;
3489
    output reg [2:0]    cmd; // {ras,cas,we}
3490
    output cke, cs_n;
3491
    output reg [dat_size/8-1:0]    dqm;
3492
    output [dat_size-1:0]       dq_o;
3493
    output reg          dq_oe;
3494
    input  [dat_size-1:0]       dq_i;
3495
    input clk, rst;
3496
    wire [ba_size-1:0]   bank;
3497
    wire [row_size-1:0] row;
3498
    wire [col_size-1:0] col;
3499
    wire [0:31]  shreg;
3500
    wire                ref_cnt_zero;
3501
    reg                 refresh_req;
3502
    wire ack_rd, rd_ack_emptyflag;
3503
    wire ack_wr;
3504
    // to keep track of open rows per bank
3505
    reg [row_size-1:0]   open_row[0:3];
3506
    reg [0:3]            open_ba;
3507
    reg                 current_bank_closed, current_row_open;
3508
    parameter rfr_length = 10;
3509
    parameter rfr_wrap_value = 1010;
3510
    parameter [2:0] cmd_nop = 3'b111,
3511
                    cmd_act = 3'b011,
3512
                    cmd_rd  = 3'b101,
3513
                    cmd_wr  = 3'b100,
3514
                    cmd_pch = 3'b010,
3515
                    cmd_rfr = 3'b001,
3516
                    cmd_lmr = 3'b000;
3517
// ctrl FSM
3518
    assign cke = 1'b1;
3519
    assign cs_n = 1'b0;
3520
    reg [2:0] state, next;
3521
    function [12:0] a10_fix;
3522
        input [col_size-1:0] a;
3523
        integer i;
3524
    begin
3525
        for (i=0;i<13;i=i+1) begin
3526
            if (i<10)
3527
              if (i<col_size)
3528
                a10_fix[i] = a[i];
3529
              else
3530
                a10_fix[i] = 1'b0;
3531
            else if (i==10)
3532
              a10_fix[i] = 1'b0;
3533
            else
3534
              if (i<col_size)
3535
                a10_fix[i] = a[i-1];
3536
              else
3537
                a10_fix[i] = 1'b0;
3538
        end
3539
    end
3540
    endfunction
3541
    assign {bank,row,col} = adr_i;
3542
    always @ (posedge clk or posedge rst)
3543
    if (rst)
3544
       state <= 3'b000;
3545
    else
3546
       state <= next;
3547
    always @*
3548
    begin
3549
        next = state;
3550
        case (state)
3551
        3'b000:
3552
            if (shreg[3+tRP+tRFC+tRFC+tMRD]) next = 3'b001;
3553
        3'b001:
3554
            if (refresh_req) next = 3'b010;
3555
            else if (cyc_i & stb_i & rd_ack_emptyflag) next = 3'b011;
3556
        3'b010:
3557
            if (shreg[tRP+tRFC-2]) next = 3'b001; // take away two cycles because no cmd will be issued in idle and adr
3558
        3'b011:
3559
            if (current_bank_closed) next = 3'b101;
3560
            else if (current_row_open) next = 3'b111;
3561
            else next = 3'b100;
3562
        3'b100:
3563
            if (shreg[tRP]) next = 3'b101;
3564
        3'b101:
3565
            if (shreg[tRCD]) next = 3'b111;
3566
        3'b111:
3567
            if (!stb_i) next = 3'b001;
3568
        endcase
3569
    end
3570
    // counter
3571
    vl_cnt_shreg_clear # ( .length(32))
3572
        cnt0 (
3573
            .clear(state!=next),
3574
            .q(shreg),
3575
            .rst(rst),
3576
            .clk(clk));
3577
    // ba, a, cmd
3578
    // outputs dependent on state vector
3579
    always @ (*)
3580
        begin
3581
            {a,cmd} = {13'd0,cmd_nop};
3582
            dqm = 2'b11;
3583
            dq_oe = 1'b0;
3584
            stall_o = 1'b1;
3585
            case (state)
3586
            3'b000:
3587
                if (shreg[3]) begin
3588
                    {a,cmd} = {13'b0010000000000, cmd_pch};
3589
                end else if (shreg[3+tRP] | shreg[3+tRP+tRFC])
3590
                    {a,cmd} = {13'd0, cmd_rfr};
3591
                else if (shreg[3+tRP+tRFC+tRFC])
3592
                    {a,cmd} = {3'b000,init_wb,2'b00,init_cl,init_bt,init_bl,cmd_lmr};
3593
            3'b010:
3594
                if (shreg[0])
3595
                    {a,cmd} = {13'b0010000000000, cmd_pch};
3596
                else if (shreg[tRP])
3597
                    {a,cmd} = {13'd0, cmd_rfr};
3598
            3'b100:
3599
                if (shreg[0])
3600
                    {a,cmd} = {13'd0,cmd_pch};
3601
            3'b101:
3602
                if (shreg[0])
3603
                    {a[row_size-1:0],cmd} = {row,cmd_act};
3604
            3'b111:
3605
                begin
3606
                    if (we_i)
3607
                        cmd = cmd_wr;
3608
                    else
3609
                        cmd = cmd_rd;
3610
                    if (we_i)
3611
                        dqm = ~sel_i;
3612
                    else
3613
                        dqm = 2'b00;
3614
                    if (we_i)
3615
                        dq_oe = 1'b1;
3616
                    a = a10_fix(col);
3617
                    stall_o = 1'b0;
3618
                end
3619
            endcase
3620
        end
3621
    assign ba = bank;
3622
    // precharge individual bank A10=0
3623
    // precharge all bank A10=1
3624
    genvar i;
3625
    generate
3626
    for (i=0;i<2<<ba_size-1;i=i+1) begin : open_ba_logic
3627
        always @ (posedge clk or posedge rst)
3628
        if (rst)
3629
            {open_ba[i],open_row[i]} <= {1'b0,{row_size{1'b0}}};
3630
        else
3631
            if (cmd==cmd_pch & (a[10] | bank==i))
3632
                open_ba[i] <= 1'b0;
3633
            else if (cmd==cmd_act & bank==i)
3634
                {open_ba[i],open_row[i]} <= {1'b1,row};
3635
    end
3636
    endgenerate
3637
    // bank and row open ?
3638
    always @ (posedge clk or posedge rst)
3639
    if (rst)
3640
       {current_bank_closed, current_row_open} <= {1'b1, 1'b0};
3641
    else
3642
       {current_bank_closed, current_row_open} <= {!(open_ba[bank]), open_row[bank]==row};
3643
    // refresh counter
3644
    vl_cnt_lfsr_zq # ( .length(rfr_length), .wrap_value (rfr_wrap_value)) ref_counter0( .zq(ref_cnt_zero), .rst(rst), .clk(clk));
3645
    always @ (posedge clk or posedge rst)
3646
    if (rst)
3647
        refresh_req <= 1'b0;
3648
    else
3649
        if (ref_cnt_zero)
3650
            refresh_req <= 1'b1;
3651
        else if (state==3'b010)
3652
            refresh_req <= 1'b0;
3653
    assign dat_o = dq_i;
3654
    assign ack_wr = (state==3'b111 & we_i);
3655
    vl_delay_emptyflag # ( .depth(cl+2)) delay0 ( .d(state==3'b111 & stb_i & !we_i), .q(ack_rd), .emptyflag(rd_ack_emptyflag), .clk(clk), .rst(rst));
3656
    assign ack_o = ack_rd | ack_wr;
3657
    assign dq_o = dat_i;
3658
endmodule
3659
module vl_wb_sdr_sdram_ctrl (
3660
    // WB i/f
3661
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
3662
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
3663
    // SDR SDRAM
3664
    mem_ba, mem_a, mem_cmd, mem_cke, mem_cs_n, mem_dqm, mem_dq_i, mem_dq_o, mem_dq_oe,
3665
    // system
3666
    wb_clk, wb_rst, mem_clk, mem_rst);
3667
    // WB slave
3668
    parameter wbs_dat_width = 32;
3669
    parameter wbs_adr_width = 24;
3670
    parameter wbs_mode = "B3";
3671
    parameter wbs_max_burst_width = 4;
3672
    // Shadow RAM
3673
    parameter shadow_mem_adr_width = 10;
3674
    parameter shadow_mem_size = 1024;
3675
    parameter shadow_mem_init = 2;
3676
    parameter shadow_mem_file = "vl_ram.v";
3677
    // Cache
3678
    parameter cache_async = 1; // wbs_clk != wbm_clk
3679
    parameter cache_nr_of_ways = 1;
3680
    parameter cache_aw_offset = 4; // 4 => 16 words per cache line
3681
    parameter cache_aw_slot = 10;
3682
    parameter cache_valid_mem = 0;
3683
    parameter cache_debug = 0;
3684
    // SDRAM parameters
3685
    parameter mem_dat_size = 16;
3686
    parameter mem_ba_size  = 2;
3687
    parameter mem_row_size = 13;
3688
    parameter mem_col_size = 9;
3689
    parameter mem_cl = 2;
3690
    parameter mem_tRFC = 9;
3691
    parameter mem_tRP  = 2;
3692
    parameter mem_tRCD = 2;
3693
    parameter mem_tMRD = 2;
3694
    parameter mem_rfr_length = 10;
3695
    parameter mem_rfr_wrap_value = 1010;
3696
    input [wbs_dat_width-1:0] wbs_dat_i;
3697
    input [wbs_adr_width-1:0] wbs_adr_i;
3698
    input [2:0] wbs_cti_i;
3699
    input [1:0] wbs_bte_i;
3700
    input [wbs_dat_width/8-1:0] wbs_sel_i;
3701
    input wbs_we_i, wbs_stb_i, wbs_cyc_i;
3702
    output [wbs_dat_width-1:0] wbs_dat_o;
3703
    output wbs_ack_o;
3704
    output wbs_stall_o;
3705
    output [mem_ba_size-1:0]    mem_ba;
3706
    output reg [12:0]           mem_a;
3707
    output reg [2:0]            mem_cmd; // {ras,cas,we}
3708
    output                      mem_cke, mem_cs_n;
3709
    output reg [mem_dat_size/8-1:0] mem_dqm;
3710
    output [mem_dat_size-1:0]       mem_dq_o;
3711
    output reg                  mem_dq_oe;
3712
    input  [mem_dat_size-1:0]       mem_dq_i;
3713
    input wb_clk, wb_rst, mem_clk, mem_rst;
3714
    // wbm1
3715
    wire [wbs_dat_width-1:0] wbm1_dat_o;
3716
    wire [wbs_adr_width-1:0] wbm1_adr_o;
3717
    wire [2:0] wbm1_cti_o;
3718
    wire [1:0] wbm1_bte_o;
3719
    wire [wbs_dat_width/8-1:0] wbm1_sel_o;
3720
    wire wbm1_we_o, wbm1_stb_o, wbm1_cyc_o;
3721
    wire [wbs_dat_width-1:0] wbm1_dat_i;
3722
    wire wbm1_ack_i, wbm1_stall_i;
3723
    // wbm2
3724
    wire [mem_dat_size-1:0] wbm2_dat_o;
3725
    wire [mem_ba_size+mem_row_size+mem_col_size-1:0] wbm2_adr_o;
3726
    wire [2:0] wbm2_cti_o;
3727
    wire [1:0] wbm2_bte_o;
3728
    wire [mem_dat_size/8-1:0] wbm2_sel_o;
3729
    wire wbm2_we_o, wbm2_stb_o, wbm2_cyc_o;
3730
    wire [mem_dat_size-1:0] wbm2_dat_i;
3731
    wire wbm2_ack_i, wbm2_stall_i;
3732
vl_wb_shadow_ram # (
3733
    .shadow_mem_adr_width(shadow_mem_adr_width), .shadow_mem_size(shadow_mem_size), .shadow_mem_init(shadow_mem_init), .shadow_mem_file(shadow_mem_file), .main_mem_adr_width(wbs_adr_width), .dat_width(wbs_dat_width), .mode(wbs_mode), .max_burst_width(wbs_max_burst_width) )
3734
shadow_ram0 (
3735
    .wbs_dat_i(wbs_dat_i),
3736
    .wbs_adr_i(wbs_adr_i),
3737
    .wbs_cti_i(wbs_cti_i),
3738
    .wbs_bte_i(wbs_bte_i),
3739
    .wbs_sel_i(wbs_sel_i),
3740
    .wbs_we_i (wbs_we_i),
3741
    .wbs_stb_i(wbs_stb_i),
3742
    .wbs_cyc_i(wbs_cyc_i),
3743
    .wbs_dat_o(wbs_dat_o),
3744
    .wbs_ack_o(wbs_ack_o),
3745
    .wbs_stall_o(wbs_stall_o),
3746
    .wbm_dat_o(wbm1_dat_o),
3747
    .wbm_adr_o(wbm1_adr_o),
3748
    .wbm_cti_o(wbm1_cti_o),
3749
    .wbm_bte_o(wbm1_bte_o),
3750
    .wbm_sel_o(wbm1_sel_o),
3751
    .wbm_we_o(wbm1_we_o),
3752
    .wbm_stb_o(wbm1_stb_o),
3753
    .wbm_cyc_o(wbm1_cyc_o),
3754
    .wbm_dat_i(wbm1_dat_i),
3755
    .wbm_ack_i(wbm1_ack_i),
3756
    .wbm_stall_i(wbm1_stall_i),
3757
    .wb_clk(wb_clk),
3758
    .wb_rst(wb_rst) );
3759
vl_wb_cache # (
3760
    .dw_s(wbs_dat_width), .aw_s(wbs_adr_width), .dw_m(mem_dat_size), .wbs_max_burst_width(cache_aw_offset), .wbs_mode(wbs_mode), .async(cache_async), .nr_of_ways(cache_nr_of_ways), .aw_offset(cache_aw_offset), .aw_slot(cache_aw_slot), .valid_mem(cache_valid_mem) )
3761
cache0 (
3762
    .wbs_dat_i(wbm1_dat_o),
3763
    .wbs_adr_i(wbm1_adr_o),
3764
    .wbs_sel_i(wbm1_sel_o),
3765
    .wbs_cti_i(wbm1_cti_o),
3766
    .wbs_bte_i(wbm1_bte_o),
3767
    .wbs_we_i (wbm1_we_o),
3768
    .wbs_stb_i(wbm1_stb_o),
3769
    .wbs_cyc_i(wbm1_cyc_o),
3770
    .wbs_dat_o(wbm1_dat_i),
3771
    .wbs_ack_o(wbm1_ack_i),
3772
    .wbs_stall_o(wbm1_stall_i),
3773
    .wbs_clk(wb_clk),
3774
    .wbs_rst(wb_rst),
3775
    .wbm_dat_o(wbm2_dat_o),
3776
    .wbm_adr_o(wbm2_adr_o),
3777
    .wbm_sel_o(wbm2_sel_o),
3778
    .wbm_cti_o(wbm2_cti_o),
3779
    .wbm_bte_o(wbm2_bte_o),
3780
    .wbm_we_o (wbm2_we_o),
3781
    .wbm_stb_o(wbm2_stb_o),
3782
    .wbm_cyc_o(wbm2_cyc_o),
3783
    .wbm_dat_i(wbm2_dat_i),
3784
    .wbm_ack_i(wbm2_ack_i),
3785
    .wbm_stall_i(wbm2_stall_i),
3786
    .wbm_clk(mem_clk),
3787
    .wbm_rst(mem_rst) );
3788
vl_wb_sdr_sdram # (
3789
    .dat_size(mem_dat_size), .ba_size(mem_ba_size), .row_size(mem_row_size), .col_size(mem_col_size), .cl(mem_cl), .tRFC(mem_tRFC), .tRP(mem_tRP), .tRCD(mem_tRCD), .tMRD(mem_tMRD), .rfr_length(mem_rfr_length), .rfr_wrap_value(mem_rfr_wrap_value) )
3790
ctrl0(
3791
    // wisbone i/f
3792
    .dat_i(wbm2_dat_o),
3793
    .adr_i(wbm2_adr_o),
3794
    .sel_i(wbm2_sel_o),
3795
    .we_i (wbm2_we_o),
3796
    .cyc_i(wbm2_cyc_o),
3797
    .stb_i(wbm2_stb_o),
3798
    .dat_o(wbm2_dat_i),
3799
    .ack_o(wbm2_ack_i),
3800
    .stall_o(wbm2_stall_i),
3801
    // SDR SDRAM
3802
    .ba(mem_ba),
3803
    .a(mem_a),
3804
    .cmd(mem_cmd),
3805
    .cke(mem_cke),
3806
    .cs_n(mem_cs_n),
3807
    .dqm(mem_dqm),
3808
    .dq_i(mem_dq_i),
3809
    .dq_o(mem_dq_o),
3810
    .dq_oe(mem_dq_oe),
3811
    // system
3812
    .clk(mem_clk),
3813
    .rst(mem_rst) );
3814
endmodule
3815 18 unneback
//////////////////////////////////////////////////////////////////////
3816
////                                                              ////
3817
////  Arithmetic functions                                        ////
3818
////                                                              ////
3819
////  Description                                                 ////
3820
////  Arithmetic functions for ALU and DSP                        ////
3821
////                                                              ////
3822
////                                                              ////
3823
////  To Do:                                                      ////
3824
////   -                                                          ////
3825
////                                                              ////
3826
////  Author(s):                                                  ////
3827
////      - Michael Unneback, unneback@opencores.org              ////
3828
////        ORSoC AB                                              ////
3829
////                                                              ////
3830
//////////////////////////////////////////////////////////////////////
3831
////                                                              ////
3832
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3833
////                                                              ////
3834
//// This source file may be used and distributed without         ////
3835
//// restriction provided that this copyright statement is not    ////
3836
//// removed from the file and that any derivative work contains  ////
3837
//// the original copyright notice and the associated disclaimer. ////
3838
////                                                              ////
3839
//// This source file is free software; you can redistribute it   ////
3840
//// and/or modify it under the terms of the GNU Lesser General   ////
3841
//// Public License as published by the Free Software Foundation; ////
3842
//// either version 2.1 of the License, or (at your option) any   ////
3843
//// later version.                                               ////
3844
////                                                              ////
3845
//// This source is distributed in the hope that it will be       ////
3846
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3847
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3848
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3849
//// details.                                                     ////
3850
////                                                              ////
3851
//// You should have received a copy of the GNU Lesser General    ////
3852
//// Public License along with this source; if not, download it   ////
3853
//// from http://www.opencores.org/lgpl.shtml                     ////
3854
////                                                              ////
3855
//////////////////////////////////////////////////////////////////////
3856
// signed multiplication
3857
module vl_mults (a,b,p);
3858
parameter operand_a_width = 18;
3859
parameter operand_b_width = 18;
3860
parameter result_hi = 35;
3861
parameter result_lo = 0;
3862
input [operand_a_width-1:0] a;
3863
input [operand_b_width-1:0] b;
3864
output [result_hi:result_lo] p;
3865
wire signed [operand_a_width-1:0] ai;
3866
wire signed [operand_b_width-1:0] bi;
3867
wire signed [operand_a_width+operand_b_width-1:0] result;
3868
    assign ai = a;
3869
    assign bi = b;
3870
    assign result = ai * bi;
3871
    assign p = result[result_hi:result_lo];
3872
endmodule
3873
module vl_mults18x18 (a,b,p);
3874
input [17:0] a,b;
3875
output [35:0] p;
3876
vl_mult
3877
    # (.operand_a_width(18), .operand_b_width(18))
3878
    mult0 (.a(a), .b(b), .p(p));
3879
endmodule
3880
// unsigned multiplication
3881
module vl_mult (a,b,p);
3882
parameter operand_a_width = 18;
3883
parameter operand_b_width = 18;
3884
parameter result_hi = 35;
3885
parameter result_lo = 0;
3886
input [operand_a_width-1:0] a;
3887
input [operand_b_width-1:0] b;
3888
output [result_hi:result_hi] p;
3889
wire [operand_a_width+operand_b_width-1:0] result;
3890
    assign result = a * b;
3891
    assign p = result[result_hi:result_lo];
3892
endmodule
3893
// shift unit
3894
// supporting the following shift functions
3895
//   SLL
3896
//   SRL
3897
//   SRA
3898
module vl_shift_unit_32( din, s, dout, opcode);
3899
input [31:0] din; // data in operand
3900
input [4:0] s; // shift operand
3901
input [1:0] opcode;
3902
output [31:0] dout;
3903
parameter opcode_sll = 2'b00;
3904
//parameter opcode_srl = 2'b01;
3905
parameter opcode_sra = 2'b10;
3906
//parameter opcode_ror = 2'b11;
3907
wire sll, sra;
3908
assign sll = opcode == opcode_sll;
3909
assign sra = opcode == opcode_sra;
3910
wire [15:1] s1;
3911
wire [3:0] sign;
3912
wire [7:0] tmp [0:3];
3913
// first stage is multiplier based
3914
// shift operand as fractional 8.7
3915
assign s1[15] = sll & s[2:0]==3'd7;
3916
assign s1[14] = sll & s[2:0]==3'd6;
3917
assign s1[13] = sll & s[2:0]==3'd5;
3918
assign s1[12] = sll & s[2:0]==3'd4;
3919
assign s1[11] = sll & s[2:0]==3'd3;
3920
assign s1[10] = sll & s[2:0]==3'd2;
3921
assign s1[ 9] = sll & s[2:0]==3'd1;
3922
assign s1[ 8] = s[2:0]==3'd0;
3923
assign s1[ 7] = !sll & s[2:0]==3'd1;
3924
assign s1[ 6] = !sll & s[2:0]==3'd2;
3925
assign s1[ 5] = !sll & s[2:0]==3'd3;
3926
assign s1[ 4] = !sll & s[2:0]==3'd4;
3927
assign s1[ 3] = !sll & s[2:0]==3'd5;
3928
assign s1[ 2] = !sll & s[2:0]==3'd6;
3929
assign s1[ 1] = !sll & s[2:0]==3'd7;
3930
assign sign[3] = din[31] & sra;
3931
assign sign[2] = sign[3] & (&din[31:24]);
3932
assign sign[1] = sign[2] & (&din[23:16]);
3933
assign sign[0] = sign[1] & (&din[15:8]);
3934
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
3935
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
3936
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
3937
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
3938
// second stage is multiplexer based
3939
// shift on byte level
3940
// mux byte 3
3941
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
3942
                     (sll & s[4:3]==2'b01) ? tmp[2] :
3943
                     (sll & s[4:3]==2'b10) ? tmp[1] :
3944
                     (sll & s[4:3]==2'b11) ? tmp[0] :
3945
                     {8{sign[3]}};
3946
// mux byte 2
3947
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
3948
                     (sll & s[4:3]==2'b01) ? tmp[1] :
3949
                     (sll & s[4:3]==2'b10) ? tmp[0] :
3950
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
3951
                     (s[4:3]==2'b01) ? tmp[3] :
3952
                     {8{sign[3]}};
3953
// mux byte 1
3954
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
3955
                     (sll & s[4:3]==2'b01) ? tmp[0] :
3956
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
3957
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
3958
                     (s[4:3]==2'b01) ? tmp[2] :
3959
                     (s[4:3]==2'b10) ? tmp[3] :
3960
                     {8{sign[3]}};
3961
// mux byte 0
3962
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
3963
                     (sll) ?  {8{1'b0}}:
3964
                     (s[4:3]==2'b01) ? tmp[1] :
3965
                     (s[4:3]==2'b10) ? tmp[2] :
3966
                     tmp[3];
3967
endmodule
3968
// logic unit
3969
// supporting the following logic functions
3970
//    a and b
3971
//    a or  b
3972
//    a xor b
3973
//    not b
3974
module vl_logic_unit( a, b, result, opcode);
3975
parameter width = 32;
3976
parameter opcode_and = 2'b00;
3977
parameter opcode_or  = 2'b01;
3978
parameter opcode_xor = 2'b10;
3979
input [width-1:0] a,b;
3980
output [width-1:0] result;
3981
input [1:0] opcode;
3982
assign result = (opcode==opcode_and) ? a & b :
3983
                (opcode==opcode_or)  ? a | b :
3984
                (opcode==opcode_xor) ? a ^ b :
3985
                b;
3986
endmodule

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